CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 3 of 10
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3 ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
Switching Characteristics[5]
Parameter Description
7C109B-12
7C1009B-12 7C109B-15
7C1009B-15 7C109B-20
7C1009B-20
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 12 15 20 ns
tAA Address to Data Valid 12 15 20 ns
tOHA Data Hold from Address Change 3 3 3 ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 12 15 20 ns
tDOE OE LOW to Data Valid 6 7 8 ns
tLZOE OE LOW to Low Z 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 678ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 333ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 678ns
tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0 0 0 ns
tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down 12 15 20 ns
Write Cycle[8]
tWC Wr it e C ycle Time[9] 12 15 20 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Write End 10 12 15 ns
tAW Address Set-Up to Write End 10 12 15 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Width 10 12 12 ns
tSD Data Set-Up to Write End 7 8 10 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 333ns
tHZWE WE LOW to High Z[6, 7] 678ns
Notes:
5. Test conditions assume signal transit ion time of 3 ns o r less, timi ng refe rence l evels of 1.5V, input pulse l evels of 0 t o 3. 0 V, and output load ing o f the specif ied
IOL/IOH and 30-pF load cap acitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacit ance of 5 pF as in part (b) of AC Test Loads. Tra nsition is measured ±500 mV f rom steady-state vo ltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signa ls can terminate the write. The input data set-up and hold timing should be refe renced to the leading ed ge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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