128K x 8 Static RAM
CY7C109B
CY7C1009B
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05038 Rev. *C Revised August 3, 2006
Features
•High speed
—t
AA = 12 ns
• Low active power
— 495 mW (max.)
• Low CMOS standby power
— 11 mW (max.) (L Version)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
• CY7C109B is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009B is
available in a 300-mil-wide SOJ package
Functional Description[1]
The CY7C109B/CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device
is accomplished b y taking Chip Enabl e One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
CY7C109B is available in standard 400-mil-wide SOJ and 32-
pin TSOP type I packages. The CY7C1009B is available in a
300-mil-wide SOJ package. The CY7C109B and CY7C1009B
are functionally equivalent in all other respects
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. NC pins are not connected on the die.
14
15
Logic Block Diagram Pin
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE1
A
A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
Configurations[2]
128K x 8
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 2 of 10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .. ... ... ................. ........–65°C to +150°C
Ambient Temperature with
Power Applied............................ ... ... ...........–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[3] ....................................–0.5V to VCC + 0.5V
DC Input V oltage[3].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
St atic Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide 7C109B-12
7C1009B-12 7C109B-15
7C1009B-15 7C109B-20
7C1009B-20 Unit
Maximum Access T i me 12 15 20 ns
Maximum Operating Current 90 80 75 mA
Maximum CMOS Standby Current 10 10 10 mA
Maximum CMOS Standby Current (L) 2mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C109B-12
7C1009B-12 7C109B-15
7C1009B-15 7C109B-20
7C1009B-20
UnitMin. Max. Min. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 2.2 VCC + 0. 3 V
VIL Input LOW Voltage[3] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current GND < VI < VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI < VCC,
Output Disabled –5 +5 –5 +5 –5 +5 µA
ICC VCC Operating
Supply Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC 90 80 75 mA
ISB1 Automatic CE
Power-Down C ur r en t
—TTL Inputs
Max. VCC, CE1 > VIH
or CE2 < VIL,VIN > VIH or
VIN < VIL, f = fMAX
45 40 30 mA
ISB2 Automatic CE
Power-Down C ur r en t
—CMOS Inputs
Max. VCC,
CE1 > VCC – 0.3V,
or CE2 < 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10 10 10 mA
L2mA
Capacitance[4]
Parameter Description Test Co nditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 9pF
COUT Output Capacitance 8 pF
Notes:
3. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 3 of 10
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3 ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: VENIN EQUIVALENT
1.73V
THÉ
Switching Characteristics[5]
Parameter Description
7C109B-12
7C1009B-12 7C109B-15
7C1009B-15 7C109B-20
7C1009B-20
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 12 15 20 ns
tAA Address to Data Valid 12 15 20 ns
tOHA Data Hold from Address Change 3 3 3 ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 12 15 20 ns
tDOE OE LOW to Data Valid 6 7 8 ns
tLZOE OE LOW to Low Z 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 678ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z[7] 333ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z[6, 7] 678ns
tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0 0 0 ns
tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down 12 15 20 ns
Write Cycle[8]
tWC Wr it e C ycle Time[9] 12 15 20 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Write End 10 12 15 ns
tAW Address Set-Up to Write End 10 12 15 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 ns
tPWE WE Pulse Width 10 12 12 ns
tSD Data Set-Up to Write End 7 8 10 ns
tHD Data Hold from Write End 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 333ns
tHZWE WE LOW to High Z[6, 7] 678ns
Notes:
5. Test conditions assume signal transit ion time of 3 ns o r less, timi ng refe rence l evels of 1.5V, input pulse l evels of 0 t o 3. 0 V, and output load ing o f the specif ied
IOL/IOH and 30-pF load cap acitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacit ance of 5 pF as in part (b) of AC Test Loads. Tra nsition is measured ±500 mV f rom steady-state vo ltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signa ls can terminate the write. The input data set-up and hold timing should be refe renced to the leading ed ge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 4 of 10
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter Description Conditions Min. Max. Unit
VDR VCC for Data Retention No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0 V
ICCDR Data Retention Current 150 µA
tCDR Chip Deselect to Data Retention Time 0 ns
tROperation Recovery Time 200 µs
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1[10, 11]
Read Cycle No. 2 (OE Controlled)[11, 12]
Notes:
10.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12.Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4.5V4.5V
CE
VCC
tCDR
VDR
>
2V
DATA RETENTION MODE
tR
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 5 of 10
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
Notes:
13.Dat a I/O is high impedance if OE = VIH.
14.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 15
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 6 of 10
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
Truth Table
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X High Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATA I/O NOTE 15
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 7 of 10
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
12 CY7C 109B-12VC 51-85033 32-pin (400-Mil) Molded SOJ Commercial
CY7C1009B-12VC 51 -85041 32-pin (300-Mil) Molded SOJ
CY7C109B-12ZC 51-85056 32-pin TSOP Ty pe I
CY7C109B-12ZXC 32-pin TSOP Type I (Pb-Free)
15 CY7C 109BL-15VC 51-85033 32-pin (400-Mi l) Molded SOJ Commercial
CY7C109B-15VC 32-pin (400-Mil) Molded SOJ
CY7C109B-15VXC 32-pin (400-Mil) Molded SOJ (Pb-Free)
CY7C1009B-15VC 51 -85041 32-pin (300-Mil) Molded SOJ
CY7C1009B-15VXC 32-pin (300-Mil) Molded SOJ (Pb-Free)
CY7C109B-15ZC 51-85056 32-pin TSOP Ty pe I
CY7C109B-15ZXC 32-pin TSOP Type I (Pb-Free)
CY7C109B-15VI 51-85033 32-pin (400-Mil) Molded SOJ I ndustrial
CY7C1009B-15VI 51-85041 32-pin (300-Mi l) Molded SOJ
20 CY7C109B-20ZC 51-85056 32-pin TSOP Type I Commercial
CY7C1009B-20VC 51 -85041 32-pin (300-Mil) Molded SOJ
CY7C109B-20VI 51-85033 32-pin (400-Mil) Molded SOJ I ndustrial
Please contact local sales representative regarding availability of parts
Package Diagrams
32-pin (300-Mil) Molded (51-85041)
51-85041-*A
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 9 of 10
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em icon ductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders
Package Diagrams (continued)
51-85056-*D
32-pin TSOP Type I (8 x 20 mm) (51-85056)
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CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *C Page 10 of 10
Document History Page
Document Title: CY7C109B/CY7C1009B 128K x 8 Static RAM
Document Number: 38-05038
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106832 09/22/01 SZV Change from Spec number: 38-00971 to 38-05038
*A 116467 09/16/02 CEA Added applications foot note to data sheet, page 1
*B 397875 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champi on Court”
Updated the Ordering Information Table on page 7
*C 493543 See ECN NXR Removed 25 ns and 35 ns speed bin from product offering
Added note# 2 on page# 1
Changed the description of IIX from Input Load Curren t to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the Ordering Information Table
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