74HC4017D,652 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible

with the HEF4017.

The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded active

HIGH outputs (Q0 to Q9), an active LOW output from the most signiﬁcant ﬂip-ﬂop (Q5-9),

active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous

master reset input (MR).

The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or

a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3).

When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,

6, 7, 8 and 9, can be used to drive the CP0 input of the next counter.

A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW)

independent of the clock inputs (CP0 and CP1).

Automatic code correction of the counter is provided by an internal circuit: following any

illegal code the counter returns to a proper counting mode within 11 clock pulses.

2. Features

■Multiple package options

■Complies with JEDEC standard no. 7 A

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A115-A exceeds 200 V

■Speciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Rev. 03 — 8 January 2008 Product data sheet

Product data sheet Rev. 03 — 8 January 2008 2 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC4017

74HC4017N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HC4017D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm SOT109-1

74HC4017DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

74HC4017PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

74HC4017BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal-enhanced

very thin quad ﬂat package; no leads; 16 terminals;

body 2.5 ×3.5 × 0.85 mm

SOT763-1

74HCT4017

74HCT4017N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74HCT4017D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm SOT109-1

74HCT4017BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal-enhanced

very thin quad ﬂat package; no leads; 16 terminals;

body 2.5 ×3.5 × 0.85 mm

SOT763-1

Fig 1. Functional diagram

001aah242

DECODING AND OUTPUT CIRCUITRY

5-STAGE JOHNSON COUNTER

CP0

13 CP1

Q5-9

Product data sheet Rev. 03 — 8 January 2008 3 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 2. Logic symbol Fig 3. IEC logic symbol

Q5-9

Q8 9

MR15

13 CP0

CP1

Q7 6

Q5 1

Q3 7

Q2 4

Q1 2

Q0 3

001aah239

CT≥5

CT = 0

CTRDIV10/DEC

001aah240

Fig 4. Logic diagram

001aah243

CP1

CP0

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q5-9

Product data sheet Rev. 03 — 8 January 2008 4 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 5. Timing diagram

001aah244

CP0 INPUT

CP1 INPUT

MR INPUT

Q0 OUTPUT

Q1 OUTPUT

Q2 OUTPUT

Q3 OUTPUT

Q4 OUTPUT

Q5 OUTPUT

Q6 OUTPUT

Q7 OUTPUT

Q8 OUTPUT

Q9 OUTPUT

Q5-9 OUTPUT

Product data sheet Rev. 03 — 8 January 2008 5 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 6. Pin conﬁguration DIP16, SO16 and (T)SSOP16 Fig 7. Pin conﬁguration DHVQFN16

74HC4017

74HCT4017

Q5 VCC

Q1 MR

Q0 CP0

Q2 CP1

Q6 Q5-9

Q7 Q9

Q3 Q4

GND Q8

001aah238

001aah241

74HC4017

74HCT4017

Q3 Q4

Q7 Q9

Q6 Q5-9

Q2 CP1

Q0 CP0

Q1 MR

GND

VCC

Transparent top view

7 10

6 11

5 12

4 13

3 14

2 15

terminal 1

index area

GND(1)

Table 2. Pin description

Symbol Pin Description

Q[0:9] 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output

GND 8 ground (0 V)

Q5-9 12 carry output (active LOW)

CP1 13 clock input (HIGH-to-LOW edge-triggered)

CP0 14 clock input (LOW-to-HIGH edge-triggered)

MR 15 master reset input (active HIGH)

VCC 16 supply voltage

Product data sheet Rev. 03 — 8 January 2008 6 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

↑= LOW-to-HIGH transition;

↓= HIGH-to-LOW transition;

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Ptot derates linearly with 12 mW/K above 70 °C.

[3] Ptot derates linearly with 8 mW/K above 70 °C.

[4] Ptot derates linearly with 5.5 mW/K above 60 °C.

[5] Ptot derates linearly with 4.5 mW/K above 60 °C.

Table 3. Function table[1]

MR CP0 CP1 Operation

H X X Q0 = Q5-9 = HIGH;

Q1 to Q9 = LOW

LH↓counter advances

L↑L counter advances

L L X no change

L X H no change

LH↑no change

L↓L no change

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input clamping current VI < −0.5 V or VI>V

CC + 0.5 V [1] -±20 mA

IOK output clamping current VO<−0.5 V or VO>V

CC + 0.5 V [1] -±20 mA

IOoutput current −0.5 V < VO < VCC + 0.5 V - ±25 mA

ICC supply current - 50 mA

IGND ground current −50 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C

DIP16 package [2] - 750 mW

SO16 package [3] - 500 mW

(T)SSOP16 package [4] - 500 mW

DHVQFN16 package [5] - 500 mW

Product data sheet Rev. 03 — 8 January 2008 7 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

74HC4017

VCC supply voltage 2.0 5.0 6.0 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V

VCC = 4.5 V - 1.67 139 ns/V

VCC = 6.0 V - - 83 ns/V

Tamb ambient temperature −40 - +125 °C

74HCT4017

VCC supply voltage 4.5 5.0 5.5 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

∆t/∆V input transition rise and fall rate VCC = 4.5 V - 1.67 139 ns/V

Tamb ambient temperature −40 - +125 °C

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74HC4017

VIH HIGH-level

input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-level

input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VOH HIGH-level

output voltage VI=V

IH or VIL

IO=−20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO=−20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO=−20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

IO=−4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

IO=−5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

Product data sheet Rev. 03 — 8 January 2008 8 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

VOL LOW-level

output voltage VI=V

IH or VIL

IO=20µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO=20µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO=20µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC = 6.0 V --±0.1 - ±1.0 - ±1.0 µA

ICC supply current VI=V

CC or GND; IO=0A;

VCC = 6.0 V - - 8.0 - 80 - 160 µA

CIinput

capacitance - 3.5 - - - - - pF

74HCT4017

VIH HIGH-level

input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

VIL LOW-level

input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-level

output voltage VI=V

IH or VIL; VCC = 4.5 V

IO=−20 µA 4.4 4.5 - 4.4 - 4.4 - V

IO=−4 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-level

output voltage VI=V

IH or VIL; VCC = 4.5 V

IO=20µA - 0 0.1 - 0.1 - 0.1 V

IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V

IIinput leakage

current VI=V

CC or GND;

VCC = 5.5 V --±0.1 - ±1.0 - ±1.0 µA

ICC supply current VI=V

CC or GND;

VCC = 5.5 V; IO=0A - - 8.0 - 80 - 160 µA

∆ICC additional

supply current per input pin;

VI=V

CC −2.1 V;

other inputs at VCC or GND;

VCC = 4.5 V to 5.5 V;

IO=0A

CP0 input - 25 90 - 113 - 123 µA

CP1 input - 40 144 - 180 - 196 µA

MR input - 50 180 - 225 - 245 µA

CIinput

capacitance - 3.5 - - - - - pF

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 8 January 2008 9 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

10. Dynamic characteristics

Table 7. Dynamic characteristics

GND = 0 V; t

= t

= 6 ns; C

= 50 pF; see Figure 11.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

74HC4017

tpd propagation

delay CP0 to Qn; CP0 to Q5-9;

see Figure 10 [1]

VCC = 2.0 V - 63 230 - 290 - 345 ns

VCC = 4.5 V - 23 46 - 58 - 69 ns

VCC = 5.0 V;

CL=15pF -20- - - - -ns

VCC = 6.0 V - 18 39 - 49 - 59 ns

CP1 to Qn; CP1 to Q5-9;

see Figure 10

VCC = 2.0 V - 61 250 - 315 - 375 ns

VCC = 4.5 V - 22 50 - 63 - 75 ns

VCC = 5.0 V;

CL=15pF -20- - - - -ns

VCC = 6.0 V - 18 43 - 54 - 64 ns

tPHL HIGH to LOW

propagation

delay

MR to Q[1:9];

see Figure 10

VCC = 2.0 V - 52 230 - 290 - 345 ns

VCC = 4.5 V - 19 46 - 58 - 69 ns

VCC = 6.0 V - 15 39 - 49 - 59 ns

tPLH LOW to HIGH

propagation

delay

MR to Q5-9, Q0;

see Figure 10

VCC = 2.0 V - 55 230 - 290 - 345 ns

VCC = 4.5 V - 20 46 - 58 - 69 ns

VCC = 6.0 V - 16 39 - 49 - 59 ns

tttransition time see Figure 10 [2]

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

tWpulse width CP0 and CP1 (HIGH or

LOW); see Figure 9

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

MR (HIGH); see Figure 9

VCC = 2.0 V 80 19 - 100 - 120 - ns

VCC = 4.5 V 16 7 - 20 - 24 - ns

VCC = 6.0 V 14 6 - 17 - 20 - ns

Product data sheet Rev. 03 — 8 January 2008 10 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

tsu set-up time CP1 to CP0; CP0 to CP1;

see Figure 8

VCC = 2.0 V 50 −8 - 65 - 75 - ns

VCC = 4.5 V 10 −3 - 13 - 15 - ns

VCC = 6.0 V 9 −2 - 11 - 13 - ns

thhold time CP1 to CP0; CP0 to CP1;

see Figure 8

VCC = 2.0 V 50 17 - 65 - 75 - ns

VCC = 4.5 V 10 6 - 13 - 15 - ns

VCC = 6.0 V 9 5 - 11 - 13 - ns

trec recovery time MR to CP0 and

MR to CP1; see Figure 9

VCC = 2.0 V 5 −17 - 5 - 5 - ns

VCC = 4.5 V 5 −6- 5 - 5 -ns

VCC = 6.0 V 5 −5- 5 - 5 -ns

fmax maximum

frequency CP0 or CP1; see Figure 9

VCC = 2.0 V 6.0 23 - 4.8 - 4.0 - MHz

VCC = 4.5 V 30 70 - 24 - 20 - MHz

VCC = 5.0 V;

CL=15pF - 77 - - - - - MHz

VCC = 6.0 V 25 83 - 28 - 24 - MHz

CPD power

dissipation

capacitance

VI = GND to VCC;

VCC =5V; f

i= 1 MHz [3] -35- - - - -pF

74HCT4017

tpd propagation

delay CP0 to Qn; CP0 to Q5-9;

see Figure 10 [1]

VCC = 4.5 V - 25 46 - 58 - 69 ns

VCC = 5.0 V;

CL=15pF -21- - - - -ns

CP1 to Qn; CP1 to Q5-9;

see Figure 10

VCC = 4.5 V - 25 50 - 63 - 75 ns

VCC = 5.0 V;

CL=15pF -21- - - - -ns

tPHL HIGH to LOW

propagation

delay

MR to Q[1:9];

see Figure 10

VCC = 4.5 V - 22 46 - 58 - 69 ns

tPLH LOW to HIGH

propagation

delay

MR to Q5-9, Q0;

see Figure 10

VCC = 4.5 V - 20 46 - 58 - 69 ns

Table 7. Dynamic characteristics

…continued

GND = 0 V; t

= t

= 6 ns; C

= 50 pF; see Figure 11.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 8 January 2008 11 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in µW):

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

tttransition time see Figure 10 [2]

VCC = 4.5 V - 7 15 - 19 - 22 ns

tWpulse width CP0 and CP1 (HIGH or

LOW); see Figure 9

VCC = 4.5 V 16 7 - 20 - 24 - ns

MR (HIGH); see Figure 9

VCC = 4.5 V 16 4 - 20 - 24 - ns

tsu set-up time CP1 to CP0; CP0 to CP1;

see Figure 8

VCC = 4.5 V 10 −3 - 13 - 15 - ns

thhold time CP1 to CP0; CP0 to CP1;

see Figure 8

VCC = 4.5 V 10 6 - 13 - 15 - ns

trec recovery time MR to CP0 and

MR to CP1; see Figure 9

VCC = 4.5 V 5 −5- 5 - 5 -ns

fmax maximum

frequency CP0 or CP1; see Figure 9

VCC = 4.5 V 30 61 - 24 - 20 - MHz

VCC = 5.0 V;

CL=15pF - 67 - - - - - MHz

CPD power

dissipation

capacitance

VI = GND to VCC −1.5 V;

VCC =5V; f

i= 1 MHz [3] -36- - - - -pF

Table 7. Dynamic characteristics

…continued

GND = 0 V; t

= t

= 6 ns; C

= 50 pF; see Figure 11.

Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

Product data sheet Rev. 03 — 8 January 2008 12 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0

tsu

CP0 input

GND

CP1 input

tsu

001aah245

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for

CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays

CP0 input

GND

VOH

VOL

VOH

VOL

Q1 - Q9

output

MR input

CP1 input

1/f max tW

tWtrec

1/f max

tPLH

tPHL

001aah246

Q0, Q5 - Q9

output

Product data sheet Rev. 03 — 8 January 2008 13 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a

HIGH-to-LOW transition.

Fig 10. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition

times

CP0 input

GND

VOH

VOL

VOH

VOL

Q1 - Q9

output

CP1 input

tPLH

tPHL tPLH

tPHL

tTLH tTHL

001aah247

Q0, Q5 - Q9

output

Table 8. Measurement points

Type Input Output

VMVM

74HC4017 0.5 ×VCC 0.5 ×VCC

74HCT4017 1.3 V 1.3 V

Product data sheet Rev. 03 — 8 January 2008 14 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

12. Application information

Some examples of applications for the 74HC4017; 74HCT4017 are:

•Decade counter with decimal decoding

•1 out of n decoding counter (when cascaded)

•Sequential controller

•Timer

Figure 12 shows a technique for extending the number of decoded output states for the

74HC4017; 74HCT4017. Decoded outputs are sequential within each stage and from

stage to stage, with no dead time (except propagation delay).

Test data is given in Table 9.

Deﬁnitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig 11. Load circuitry for measuring switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aad983

DUT

VCC VCC

VIVO

RLS1

open

PULSE

GENERATOR

Table 9. Test data

Type Input Load S1 position

VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ

74HC4017 VCC 6 ns 15 pF, 50 pF 1 kΩopen GND VCC

74HCT4017 3 V 6 ns 15 pF, 50 pF 1 kΩopen GND VCC

Product data sheet Rev. 03 — 8 January 2008 15 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0

when CP1 is LOW, as this would cause an extra count.

Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one

74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset,

the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output

pulse widths can be enlarged by inserting an RC network at the MR input.

Fig 12. Counter expansion

Fig 13. Divide-by 2 through divide-by 10

001aah248

8 decoded

outputs

8 decoded

outputs

CP0

CP1

Q0 Q1 Q8 Q9

74HC4017

74HCT4017 74HC4017

74HCT4017

- - - -

CP0

CP1

Q0 Q1 Q8 Q9

- - - -

CP0

CP1

Q1 Q8 Q9

- - - - - -

clock first stage last stageintermediate stages

MR MR

9 decoded

outputs

Q8GND

divide - by 4

divide - by 8

Q9 divide - by 9

Q3divide - by 3

Q7divide - by 7

Q6divide - by 6

Q2divide - by 2

Q5divide - by 5

Q5-9 divide - by 10

CP1

CP0 fin

fout

VCC VCC

001aah249

74HC4017

74HCT4017

Product data sheet Rev. 03 — 8 January 2008 16 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

13. Package outline

Fig 14. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 03 — 8 January 2008 17 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 15. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 03 — 8 January 2008 18 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 16. Package outline SOT338-1 (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 03 — 8 January 2008 19 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 17. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 8 January 2008 20 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Fig 18. Package outline SOT763-1 (DHVQFN16)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.6

3.4

2.15

1.85

2.6

2.4 1.15

0.85

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT763-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT763-1

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

15 10

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

02-10-17

03-01-27

Product data sheet Rev. 03 — 8 January 2008 21 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

14. Abbreviations

15. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT4017_3 20080108 Product data sheet - 74HC_HCT4017_CNV_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 3: DHVQFN16 package added.

•Section 7: derating values added for DHVQFN16 package.

•Section 13: outline drawing added for DHVQFN16 package.

74HC_HCT4017_CNV_2 19970829 Product speciﬁcation - -

Product data sheet Rev. 03 — 8 January 2008 22 of 23

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 January 2008

Document identifier: 74HC_HCT4017_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 6

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Recommended operating conditions. . . . . . . . 7

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

12 Application information. . . . . . . . . . . . . . . . . . 14

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

17 Contact information. . . . . . . . . . . . . . . . . . . . . 22

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23