Media Accelerated Processor for Consumer Appliances MAP-CATM Data Sheet DS#00008 3/31/2000 MAP-CA Overview MAP-CATM - Media Accelerated Processor for Consumer Appliances- offers a highly integrated single chip solution for multimedia products such as set-top boxes, digital TVs, video conferencing systems, medical imaging products, digital video editing equipment and office automation products. The MAP-CA is a member of Equator's MAP-CA series of VLIW media processors. A parallelizing C compiler, linker, source level debugger, simulators and libraries are available from Equator. Reference software modules, including MPEG2 encode and decode, JPEG encode and decode, video post-filtering, audio, telephony, video teleconferencing codecs are also available from Equator to accelerate customer product development. Because core media applications are delivered in software on the MAP-CA platform, it is easy to add, remove or enhance functionality of final products. MAP-CA provides the proven and effective solution for rapidly evolving multimedia applications. VLIW Core * Highly pipelined Very Long Instruction Word processor that issues four operations per clock cycle. - 4 32-bit integer ALUs, 2 64-bit shuffle/partitioned add units, and 2 128-bit multimedia units - 128 32-bit general purpose registers which can be treated as 64 64-bit general purpose registers - 32 1-bit predicate registers - 8 special 128-bit registers * 11+ GOPS sustained 16-bit SIMD operations @300MHz * 24+ GOPS sustained 8-bit SIMD operations @300MHz * 30+ GOPS @300MHz for sum-of-absolute difference block matching. * 1800 MIPS @ 300 MHz in 32-bit integer arithmetic. * Bi-endian support. Memory Hierarchy * 32 KB 2-way set associative, LRU replacement policy compressed format Instruction Cache. * 32 KB 4-way set associative, four bank interleaved, true LRU, write-back Data Cache. * Separate MMUs for Instruction, Data and DMA with fully associative 16 entry TLB for each MMU. Co-processors * Programmable 16-bit RISC processor with acceleration for variable length decoding and encoding (VLx) with 4KB data memory and 4KB instruction memory. * 4(vertical) x 5(horizontal) / 3 x 5 / 2 x 5 tap Video Filter with 6KB line buffer memory. * Programmable 64-channel DMA engine (DataStreamerTM) with 8KB buffer memory. SYSTEM DIAGRAM MAP-CATM Media Accelerated Processor for Consumer Appliances 32Bit PCI Bus @33/66MHz JTAG JTAG Flash ROM FLASH ROM I/F RGB Monitor Display Refresh Controller Audio CODECs IEC958 I2C/DDC I2C/DDC Core Voltage Regulators SDRAM Controller PCI I2 S 1.8V 3.3V VLIW processor ITU-R BT.656 Input 0 TCI Input 0 on-chip memories Coprocessors ITU-R BT.656 Input 1 64bit SDRAM @150MHz Video Camera NTSC/PAL Decoder DEMOD FEC TUNER ITU-R BT.656 Output NTSC/PAL Encoder TV Monitor PLLs 27MHz VCXO TCI Input 1 I/O Equator Technologies, Inc. MAP-CA Data Sheet IO Interfaces * Video input: - 2 parallel DVB compliant Transport Channel Interface or For additional information, contact Equator Technologies, Inc. info@equator.com - 1 parallel DVB compliant Transport Channel Interface & 1 ITU-R BT.601/656 in http://www.equator.com or - 2 ITU-R BT.601/656 in * ITU-R BT.601/656 video out. * Display Refresh Controller (DRC) with on-chip color space conversion, palette table lookup, alpha-blending, and hardware cursor. * 110MHz RAMDAC with sync on green for analog RGB monitor. * I2S/IEC958 audio interfaces. * I2C/DDC master/slave interface. * Glueless high-speed 150MHz SDRAM/SGRAM interface, support up to 128MB. * 33MHz / 66MHz 32-bit PCI bus. * Flash ROM (EEPROM) interface. * IEEE compliant JTAG interface. Data Sheet Overview This data sheet provides the following information: * An overview of the MAP-CA architecture * A description of the software development platform * A description of the hardware development platform * Packaging information * Electrical specifications. Equator Technologies, Inc. 1300 White Oaks Road Campbell, CA 95008 Phone: (408) 369-5200 FAX: (408) 371-9106 Copyright (c) Equator Technologies, Inc. [2000] All Rights Reserved Equator makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. Equator reserves the right to change or discontinue this product at any time, without notice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document. The following are trademarks of Equator Technologies, Inc., and may be used to identify Equator products only: Equator, MAP, MAP1000, MAP1000A, MAP-CA, MAP Series, FIRtree, DataStreamer, iMMediaC, Media Intrinsics, VersaPort and SofTV. Other product and company names contained herein may be trademarks of their respective owners. MAP-CA were jointly developed by Equator Technologies, Inc. and Hitachi, Ltd. Equator Technologies, Inc. ii 1. Architecture Overview .........................1 1.1 The VLIW Approach ...............................2 Execution Units ..................................................2 Register Resources .............................................3 3. BGA PIN_OUT Assignment...............12 4. Signal Descriptions ............................15 4.1 Processor Clock ..................................... 15 1.2 Timers ......................................................3 4.2 PCI Bus.................................................. 15 1.3 Interrupts and Exceptions ........................3 4.3 SDRAM................................................. 16 Core Interrupts and Exceptions ........................4 Interrupt Controller ............................................4 4.4 Flash ROM ............................................ 17 1.4 Memory Hierarchy...................................5 Caches ................................................................5 Address Translation............................................5 1.5 Databuses and Controllers .......................5 Data Transfer Switch (DTS) ..............................5 DataStreamerTM ................................................6 I/O Bus ...............................................................6 PCI Bus ..............................................................6 Memory Interface Controller .............................6 1.6 Co-processors...........................................7 VLx.....................................................................7 4.5 Analog CRT........................................... 17 4.6 ITU-R BT.601/656 Output .................... 17 4.7 Video Input Ports................................... 18 Transport Channel Interface (TCI) .................. 18 ITU-R BT.601/656 Input ................................. 19 4.8 I2S ......................................................... 19 4.9 IEC958................................................... 20 4.10 I2C ....................................................... 20 4.11 JTAG.................................................... 20 4.12 ROM and Reset Strap.......................... 20 Video Filter ........................................................7 4.13 Power/Ground Pins.............................. 21 1.7 I/O Interfaces ...........................................7 4.14 Signal List Summary ........................... 22 Video Interfaces .................................................7 Audio Interfaces .................................................8 Display Refresh Controller.................................8 4.15 Interface Summary .............................. 23 DACs..................................................................8 I2C Interface Unit...............................................9 ROM Controller .................................................9 Reset Strap..........................................................9 5. External Connection Examples .........24 5.1 ROM ...................................................... 24 5.2 SDRAM................................................. 24 5.3 NTSC Decoder ...................................... 26 5.4 NTSC Encoder ...................................... 26 2. Software Development.......................10 2.1 The C Compiler......................................10 The FIRtreeTM Media Intrinsics .....................10 2.2 Libraries .................................................10 2.3 Assembler ..............................................10 2.4 Linker.....................................................10 5.5 IEC958................................................... 26 5.6 I2S ......................................................... 27 5.7 I2C/DDC ............................................... 27 5.8 Transport Channel Interface (TCI) ........ 28 5.9 CRT........................................................ 28 2.5 Debugger................................................10 6. Electrical Specifications ...................29 2.6 Simulators ..............................................11 6.1 Absolute Maximum Rating .................. 29 2.7 Boot........................................................11 6.2 Power Supply Specifications................. 29 Equator Technologies, Inc. iii MAP-CA Data Sheet 6.3 Operating Parameters.............................29 6.4 AC Characteristics .................................30 SDRAM Interface Timing .............................. 30 PCI Bus Timing (66MHz) ............................... 31 I2C Interface Timing ....................................... 33 ITU-R BT.656 Interfaces Timing.................... 34 Transport Channel Interface Timing .............. 35 IEC958 Interface Timing................................. 36 I2S Interface Timing ....................................... 36 7. Acronyms............................................ 38 iv Equator Technologies, Inc. MAP-CA Data Sheet PCI-A JTAG Video Filter Analog RGB Audio I/O I2C I-ALU IG-ALU co-processor memory DataStreamer 16-bit RISC processor Glueless SDRAM Controller 64bit SDRAM PLLs Display Refresh Controller I2S IEC958 ITU-R BT.656 OUT ITU-R BT.656 IN 0 ITU-R TCI BT.656 IN 0 IN 1 TCI IN 1 Flash ROM ROM I/F I2C Video Out 1. Architecture Overview The MAP-CA is a high performance media processor that combines general purpose RISC processing with high performance signal and image processing. The MAP-CA supports programmable video, image, and signal processing software implementations of compression and decompression algorithms. The MAP-CA matches the cost/performance features of dedicated fixed function chips with the added flexibility to rapidly respond to evolving standards. A block diagram of the MAP-CA is shown above. The MAP-CA consists of a VLIW core, programmable co-processors, onchip memories and I/O interfaces. The VLIW core executes four operations in parallel and supports partitioned SIMD operations for 8/16/32/64-bit data types. Co-processors on the MAP-CA help accelerate serial operations like variable length encoding/decoding and video filtering. Several audio/video interfaces are supported, including ITU-R BT.656 input and output, MPEG2 Transport Channel 1 IG-ALU VLIW core co-processor memory 27 MHz I-ALU Instruction Cache Data Cache 32-bit 66MHz JTAG Register Register File File Block Diagram Video In 0 Video In 1 Interface (TCI), an I2C selectable interface, IEC958 and I2S digital audio interfaces. Two video inputs (2 BT.656s, or 1 BT.656 & 1 TCI, or 2 TCIs) can be used at the same time. The DRC unit not only supports RGB computer screen refresh, but also has hardware support for overlaying a hardware cursor and graphics/text or a secondary video channel on the primary video channel. A glueless SDRAM controller supports access up to 150MHz SDRAM. The maximum memory size supported is 128MB. A 32-bit 33/66MHz PCI bus interface is also supported. The MAP-CA can be booted up either via PCI bus or Flash ROM interface. These I/O functions execute in parallel with the CPU and eliminate the need for several external ASICs with the associated cost and bandwidth issues. There are 3 PLLs (core/SDRAM, pixel, audio) on chip to generate all the internal clocks from a single 27MHz external clock input. A software PLL mechanism is provided in Equator Technologies, Inc. MAP-CA Data Sheet conjunction with the TCI to track the reference clock (PCR) embedded in the transport stream An IEEE compliant JTAG interface is provided for manufacturing test. 1.1 The VLIW Approach Real-time handling of multi-media data stresses processor performance. There are three basic ways to increase a processor's performance: decrease the cycle time, decrease the number of cycles required to execute an instruction, and execute more instructions per cycle. The first two are becoming increasingly difficult to improve beyond process scheduling, while the last is still underexploited. Executing more instructions per cycle exploits the natural parallelism available in most software. Very Long Instruction Word (VLIW) processors explictly describe this parallelism by packing multiple operations into a single instruction word, which is then executed as a unit. VLIW differs from superscalar architectures in that the grouping and scheduling of instructions for execution is done at compile time, rather than execution time. The compiler searches for eligible operations, checks for dependencies and control resource conflicts, and packages them into VLIW instruction words. The compiler can explore beyond the limited search window seen in superscalar architectures, and cross natural boundaries such as branches to search for opportunities for parallelism. The Equator compiler uses a technique known as Trace Scheduling to search a whole routine for eligible operations. By moving the difficult task of finding parallelism into software, VLIW techniques dramatically simplify the CPU, design by reducing gate count and freeing valuable die area for other performance enhancements or lower costs. While VLIW is primarily designed to exploit parallelism, its simplification of the processor architecture allows for reduced cycle times as well. 1.1.1 Execution Units The basic operation format for the MAP-CA consists of three-operand register-to-register operations. Native data types include 1-bit logical values, 8, 16, 32, and 64-bit integers, and 32-bit addresses. The Media Intrinsic operations include partitioned operations over these data types. Load and store operations can perform 1, 2, 4, and 8-byte accesses, with support for both little and big-endian byte orderings. Dynamic address translation and virtual memory protection is fully supported. The 1-bit logical values are also used to support predicated execution, which substantially enhances available parallelism by allowing partial speculation and eliminating branches. Each MAP-CA instruction contains four operations. The MAP-CA has four functional units: two I-ALUs, and 2 two IG-ALUs. Each I-ALU contains a Load-Store unit, an integer ALU, and a Branch unit. Each IG-ALU contains an Integer/Graphics unit and a Multimedia Operation unit. There are 128 32-bit registers usable in pairs as 64-bit registers, 32 1-bit predicate registers, and eight special 128-bit registers. The 128-bit (PLC/PLV) registers are used for FIR filter, SAD, FFT, ADD, DCT, and other specialized partitioned integer operations. The large register files help minimize unnecessary instruction dependencies caused by logically distinct register reuses. The MAP-CA operations are primarily 3-operand RISC operations. As in a typical RISC architecture, load and store operations are the only means of referencing memory. The IALU and IG-ALU support different operations, but many integer and logical operations are implemented in both units. This overlap allows the compiler to schedule more operations in parallel and make more efficient use of all the functional units. A new operation of any type can be issued on every cycle. 1.1.1.1 I-ALU The I-ALU performs the following operations: * 32-bit integer arithmetic operations including compare and more. * Logical and bitwise logical operations. The result of a logical operation can be sent to a general register or a predicate register. * Address calculations for indexed addressing * Memory reference * Branching * System control operations 1.1.1.2 IG-ALU The IG-ALU performs the following operations: * 32-bit integer arithmetic operations (same as the I-ALU) * Logical and bitwise logical operations (same as the I-ALU) * 64-bit integer arithmetic operations. * Shift/Extract/Merge operations * 64-bit SIMD operations (with 8-bit, 16-bit, and 32-bit partitions) including selection, comparison, selecting maximums and minimums, addition, multiply-add, complex multiplication, inner-product, and sum-of-absolute difference. * 128-bit partitioned (with 8-bit, 16-bit, and 32-bit partitions) SIMD operations including inner-product with new partition shift-in for efficient FIR operation and sum-of-abso- Equator Technologies, Inc. lute difference with new partition shift-in for efficient block matching operation. registers. When reading or writing 64-bit registers an evennumbered register must be specified. For example, the register pair [R5, R4] is referenced as R4 in 64-bit access. 1.1.1.3 Simple Interlocks Certain operations (such as SIMD operations) require more than one cycle to complete. No hardware interlocks are needed to prevent issue of an operation which attempts to read a result not yet completed. The compiler is responsible for correct scheduling, not hardware. Register scoreboarding is supported for outstanding loads. 1.1.2.4 Predicate Registers There are 32 1-bit predicate registers. Predicate registers are used in predicated operations, logical operations, and branches. They provide a destination for operations with a judged condition. 1.1.1.4 Extensive Predication Nearly all operations can have their effect controlled by the value of a selected (1-bit) predicate register. A predicate register is tested to determine whether or not the operation should be performed. This allows the compiler to aggressively convert control flow into data flow, enabling a substantially higher degree of instruction-level parallelism. This also greatly helps to reduce any penalties for branching, without the cost and complexity of hardware branch prediction. 1.1.2.5 PLC/PLV 128-bit registers The IG-ALU has four special 128-bit registers - two pairs of Partitioned Local Constant (PLC) and Partitioned Local Variable (PLV). These registers are used for powerful SIMD DSP partitioned operations. The registers can be configured as sixteen 8-bit operation partitions, eight 16-bit operation partitions, or four 32-bit operation partitions. For numerous digital signal processing and compression algorithms, this allows MAP-CA to match the cost/performance of fixedfunction chips without the loss of reprogrammability. 1.1.2 Register Resources There are several types of registers on the MAP-CA. These include system registers, breakpoint registers, general purpose registers, predicate registers, and special purpose 128-bit registers. 1.1.2.1 Global Registers Global registers on the MAP-CA consist of system registers and implementation-dependent I/O registers (PIO registers). Dedicated operations manipulate the system registers, while conventional load and store operations manipulate the I/O registers. All system registers are 32-bit registers. 1.1.2.2 Breakpoint Registers MAP-CA has two sets of breakpoint registers, instructionbreakpoint, and data-breakpoint registers. These registers provide hardware breakpoint capability for various debugging tools. Instruction-breakpoint registers cause an exception when an operation in the specified address is about to be executed. Similarly, the data-breakpoint registers cause an exception when the data at the specified address is about to be accessed. In both cases a mask can be used to specify a range of addresses. By registering an exception handling routine associated with either of these exceptions, a software developer can control what happens when a hardware breakpoint occurs. For example, the exception handling routine may be used to signal an external application such as a source-level debugger that a breakpoint has occurred. 1.1.2.3 General Registers There are 128 32-bit registers that can be treated as pairs of 64-bit general registers using odd-even pairs of the 32-bit 1.2 Timers The MAP-CA has two independent programmable interval timers plus a free-running counter. Each interval timer has a 32-bit counter register and period register. The counter is incremented once per cycle. When the counter reaches the period value, the counter is reset, a bit is set in the system Event Seen Register (ESR), and a maskable interrupt is asserted. The free-running counter counts up once per cycle as well. When it overflows to zero a bit is set in ESR and a maskable interrupt is asserted. The Transport Channel Interface also has programmable timer with a resolution of 27MHz that can be used to generate periodic interrupts. 1.3 Interrupts and Exceptions The MAP-CA has a flexible interrupt structure. Interrupts and exceptions internal to the core are reflected directly in the system registers. PCI, DataStreamer, and other non-core interrupts are gathered by the on-chip Interrupt Collector. S oftw ar e generated interrupts are provided f or multiprocessing or interprocess communication support. Each interrupt can be individually routed to one of four core interrupts or to one of two PCI interrupt signals. Routing and masking of interrupts is programmable. All interrupts are at a single priority level, allowing prioritization to be managed by software. All interrupts and processor exceptions can be masked or unmasked at the core by clearing or setting the EXCP bit of the Processor Status Word (PSW) system register. In addition, all of the interrupts controlled by the Interrupt Collector can be masked based on their routing Equator Technologies, Inc. 3 MAP-CA Data Sheet destination, using the enable bits in the IntrControl register. Event Vector System Registers 1.3.1 Core Interrupts and Exceptions The Event Seen system register (ESR) has bits for the following events: Register Event EVDTLBVR DTLB miss EVITLBR ITLB miss System Events EVSYSR system call (trap instruction) EVINTVR Interval timer interrupt EVIO0R I/O interrupt 0 Name Event Maskable? IO0..IO3 I/O interrupts (from interrupt controller) Yes EVIO1R I/O interrupt 1 I/O interrupt 2 SINT0..SINT1 Software interrupts Yes EVIO2R FCNT Free running counter overflow Yes EVIO3R I/O interrupt 3 INTV0..INTV1 Interval timers Yes EVGENR General event ILPC Illegal program counter No IBPT Instruction address break Yes BPOP Breakpoint operation No SYS System call (trap instruction) No ITLBAA ITLB application access No ITLBR ITLB reference No ITLBM ITLB miss No Other system registers (CESR0 and CESR1) have bits for the events described in the following tables: Operation Events of the PSW) is set to kernel, and the exception PCs are stored in a series of three Event PC system registers (EPCR0, EPCR1, and EPCR2). The prior EXCP and PL settings are saved in PEXCP and PPL, also in the PSW. The handler is responsible for saving and restoring any state it modifies. Eight Event Save system registers (ESV0 through ESV7) are available to each I-ALU and IG-ALU pair to assist in saving state. The handler returns control to the interrupted code by issuing an RFE instruction. This instruction restores the PSW's EXCP and PL settings from PEXCP and PPL, and then branches to the address(es) contained in EPCR0 through EPCR2. Name Event Maskable? IEXZ Integer divide by zero Yes 1.3.2 Interrupt Controller ILLO Illegal operation No PLV Privilege violation No DBPT Data address break Yes DALN Data alignment error No DTLBKW DTLB kernel write No The MAP-CA interrupt controller supports multiple maskable interrupts. These non-core interrupt sources include on-chip devices such as TCI, DRC or the DataStreamer, and PCI interrupts from external devices or hosts. Software g e n er a te d sh o ul d er -t a p i n t er u p ts ar e pr o v i d ed f o r muliprocessing or interprocess communication support. DTLBAW DTLB application write No DTLBAA DTLB application access No DTLBR DTLB reference No DTLBM DTLB miss No When an event occurs, the appropriate bit is set in the ESR or one of the CESR registers. If the event is not masked (or not maskable), the address for a handler will be fetched from one of the Event Vector system registers. The core also has the event vector system registers as shown in the Event System Registers table. The general event handler is called for any event or exception not covered by another vector. When a handler is called due to an exception or interrupt, the EXCP bit of the PSW is cleared, the privilege level (PL bit 4 MAP-CA interrupts can be examined and enabled in the PIO registers of the ROMCON control block. Interrupt status is organized into two 32-bit registers (InterStatus0 and InterStatus1). Bit assignments for these registers are shown in the following table. Routing and masking of interrupts is programmable. Each interrupt can be individually routed to one of four core interrupts or to one of two PCI interrupt signals. All interrupts can be masked based on their routing destination, using the I n t r M a s te r E n a b l e C o r e , I n t r M a st e r E n a b l e A A , a n d IntrMasterEnableAB bits of the IntrControlRegister. The interrupt controller can be programmed through the ROMCON PIO registers, either from the core or from another Equator Technologies, Inc. IntrStatus0: Bit Name 0 operations. In addition, these memories are also available to the DataStreamer and for external use via PCI. The line buffer memory is used to store the content of flash ROM at a system boot up. Interrupt unused 1 IrqAlwaysOne debug interrupt, always asserted 2 IrqIIC I2C 3 IrqTCI0 primary TCI 4 IrqDRC display refresh controller 5 IrqNTSCIn0 primary ITU.R-BT601/656 in 6 unused 7 IrqNTSCIn1 secondary ITU.R-BT601/656 in 8 IrqTCI1 secondary TCI 9 IrqPCIAA PCI interrupt pin A 10 IrqPCIAB PCI interrupt pin B 11 IrqNTSCOut ITU.R-BT601/656 out 14 IrqIEC958 IEC958 audio 15 IrqIIS IIS audio 12 13 16 unused 17..31 unused Bit Name Interrupt 0 IrqPCIAPME PCIA power management event (pme pin) 1 IrqDS0 DataStreamer interrupt 0 2 IrqDS1 DataStreamer interrupt 1 3 IrqDSTLB DataStreamer TLB miss 4 IrqDSBufOvrFlow DataStreamer I/O input overflow 12..31 Unused IrqSoftWare The I-cache holds instructions in a compressed form. It is organized as a 2-way set associative cache with a LRU replacement algorithm. The D-cache is a 32KB, 4-way set-associative (with true LRU replacement), write-back cache. The data cache supports four simultaneous 64-bit data accesses per cycle. The cache is non-blocking; up to 8 outstanding misses to different cache lines and up to 64 outstanding misses overall are allowed. 1.4.2 Address Translation The MAP-CA provides memory management support in the form of separate TLBs for the instruction stream, each IALU data access, and the DataStreamer. The four TLBs can be programmed independently. IntrStatus1: 15-11 1.4.1 Caches MAP-CA has a 32KB instruction cache (I-cache) and a separate, multi-bank 32KB data cache (D-cache). Both caches are physically addressed, so that problems of aliasing and context switching do not arise. For fast address translation, the cache index is virtual but the tags are physical. Software-controlled interrupts The DTS-ID is part of the virtual address and can be used to direct accesses when the TLBs are disabled. Each TLB has sixteen fully-associative entries. Each entry contains a Virtual Page Number (VPN), an 8-bit Address Space Identifier (ASID), access protection bits, and page size information. Each entry can map a page of any valid size, where the valid sizes are 16KB, 64KB, 256KB, 1MB, 4MB, 16MB, 64MB, 256MB,and 1GB. host processor via the PCI interface. 1.4 Memory Hierarchy The MAP-CA supports several on-chip memories and access to SDRAM and other memories via the PCI bus. The VLIW is equipped with a 32KB instruction cache and 32KB data cache used for caching instructions and data from SDRAM. In addition to supporting I-ALU ports, the data cache supports a port to the DTS, supporting data in the data cache available to the DataStreamer. 4KB instruction memory and 4KB data memory are used by the VLx co-processor. The Video Filter uses 6KB line buffer memory. These memories (total 14KB) are also accessible by the VLIW core through uncached load/store When a TLB miss occurs, an exception is generated. The exception handler can modify a TLB entry and retry the failed operation. Separate exception handlers can be installed for data, instruction, and DataStreamer TLB misses. 1.5 Databuses and Controllers The various buses and controllers on the MAP-CA are described in the following sections. 1.5.1 Data Transfer Switch (DTS) The DTS is a split-transaction bus. The DTS contains the data and address buses, a high speed bridging system and bus arbiter. The bridge, arbiter and bus arrangement is a very highspeed communication solution that allows multiple media Equator Technologies, Inc. 5 MAP-CA Data Sheet applications to be executed concurrently. The arbiter can handle asynchronous requestors using priority based scheduling. 1.5.2 DataStreamerTM The DataStreamer is a high performance, programmable DMA engine that provides buffered data transfer between different MAP-CA memory subsystems or between memories and I/O devices. The DataStreamer initiates transfers to and from memory, whereas the I/O Devices initiate I/O transfers between themselves and the DataStreamer. These transfers are done under software control without consuming cycles from other on-chip processing units. This feature is useful for the following classes of transfers: * memory-to-memory - perform block transfers; * memory-to-data cache - preload data into the cache; * memory-to-I/O and I/O-to-memory - perform I/O transfers; *constant-to-memory - fill a memory region with 0 or 1 bits. The DataStreamer is connected to the DTS through a system of queues. Queueing requests and transfers allows multiple active channels performing reads and writes to be serviced in a highly pipelined fashion. This maximizes resource utilization and overall data throughput. The DataStreamer is also connected to the I/O bus through a separate I/O Controller, allowing on-chip devices to stream data directly to and from DataStreamer buffers. For example, a digitized NTSC input stream can be transfered directly into a DataStreamer buffer, and a channel started to copy the data into a series of frame structures in memory for processing. Except for setting up and starting the NTSC input device and the DataStreamer buffer and channel, no core involvement is required to perform this continuous transfer. 1.5.2.1 Features of the DataStreamer * 64 independent programmable channels for transfers between memory and the DataStreamer's internal buffer. * 8KB internal memory that can be partitioned into as many as 64 variable-sized buffers. Each buffer is simultaneously the sink for an input I/O or memory channel and the source for an output I/O or memory channel. * Channels have 4 priority levels. The DataStreamer schedules channels based on buffer fullness and priority. A burst of transfers (either writes or read requests) is generated for each channel when scheduled. * Channel programs are composed of one or more descriptors. Each descriptor names a source or destination address, a data width, a skip value, a repetition count, a next descriptor address, and a number of control bits. * Descriptor lists allow transfers of arbitrary or infinite length to be specified. Regular and irregular patterns of non-contiguous transfers are easy to specify. 6 * Memories that can be accessed include SDRAM, on-chip memories, and PCI bus accessible memories. Cache policy can be specified for SDRAM transfers * Three per-channel interrupts are provided. Two are asserted by control bits on a descriptor, and the third is a TLB miss interrupt. * One per-buffer overflow interrupt is provided. It is used to detect overflow on I/O input transfers. * Interrupts are routed to the Interrupt Controller where they can be masked and/or routed to the VLIW core or to PCI interrupts. 1.5.3 I/O Bus All on-chip peripheral devices are connected via the internal I/O Bus (IOB). This is a 32-bit internal bus running at half of the VLIW core frequency. The IOB connects to the DTS through the DataStreamer. The IOB can handle isochronous requests. 1.5.4 PCI Bus The PCI unit implements a 32-bit PCI interface with speed up to 66MHz. The PCI interface is a single function device with two BARs. Certain fields in the configuration registers may be initialized on power-up through ROM control. As a PCI target, the PCI interface allows access to the MAP-CA SDRAM (coherently or non-coherently with respect to the Data-Cache). It also allows access to several programmer visible control registers, PIO space and SDRAM. As a PCI m a st e r, t h e P C I i n t e r f a c e a l lo w s t h e V L I W c o r e , DataStreamer and co-processors to initiate PCI bus requests. The PCI unit can initiate memory, I/O and configuration commands on the PCI bus. The MAP-CA can act as a host and provide three pairs of request/grant lines for other devices on a PCI bus. This enables a multi-processor configuration to connect upto 4 MAP-CAs together on a PCI bus without a bridge. The PCI interface implements two separate interrupt lines. If the MAP-CA is not the host, any internal interrupt can be routed to any of these PC interrupts. If the MAP-CA is the host, the PCI interrupts are sampled by the MAP-CA and can be routed to the MAP-CA VLIW core. The MAP-CA is a 3.3V only I/O device. If the MAP-CA is used in a system with a 5V PCI bus architecture, then a 5V to 3.3V level translator is required. The PCI bus interface can support any PCI Rev2.2 compliant device. 1.5.5 Memory Interface Controller The Memory Controller Unit allows customers to easily build high performance, external memory up to 128MB using SDRAM/SGRAM without any external glue logic. Local Equator Technologies, Inc. memory supports externally initiated PCI accesses through the Address Translation Unit within the PCI module. The Memory Controller Unit also includes hardware which queues, prioritizes, and transfers data from memory-tomemory or memory-to-cache asynchronously to the initiating software. The PLL on chip generates the clock for the memory controller and provides clock synchronization between the MAP-CA and external SDRAM. This provides support for various combinations of CPU core and memory speeds. 1.6 Co-processors 1.6.1 VLx The Variable Length Encoder/Decoder (VLx) is a 16-bit VLx registers Bitstream processor 32-bit * Supports 8-bit coefficients. * Supports both interspersed and co-sited pixel positioning. * Supports vertical 4-tap polyphase (8 phases) filters for Luma and Chroma. * Supports horizontal 5-tap polyphase (8 phases) filters for Luma and Chroma. * Can scale up to a maximum resolution of 2047x2047 (depends upon memory bandwidth available for the video scaling operation). * Can scale up from a minimum resolution of 17x4. * The maximum scale down ratio is 1:7. 1.7 I/O Interfaces Co-processor on the MAP-CA help off-load "serial" tasks from the VLIW core or accelerate special purpose processing for video operations. The co-processors operate in parallel with the VLIW core resulting in improved video processing. 16-bit CPU the video bus. Its features are described below. 64-bit instruction memory (4KB) 16-bit data memory (4KB) I/O Bus VLx co-processor RISC co-processor with 32 16-bit registers that offloads the VLIW CPU core from bit sequential tasks of Variable Length Encoding and Variable Length Decoding (VLE/VLD), and accelerates applications such as JPEG, MPEG, H.263, JBIG, DV, etc. It includes special purpose hardware for bitstream processing, hardware accelerated MPEG2 table lookup and general purpose variable length decoding. 1.6.2 Video Filter A polyphase (8 phase) 2D Video Filter takes 4:2:0 or 4:2:2 YUV stream as input and scales either up or down as required. 4 (vertical) x 5 (horizontal) filters support up to 768 horizontal pixels, 3 x 5 up to 1024 horizontal pixels, and 2 x 5 up to 1536 horizontal pixels. The Video Filter pumps out scaled 4:4:4 YUV data to the SDRAM or the DRC through 1.7.1 Video Interfaces MAP-CA provides two video input ports. Each port supports either TCI input or ITU-R.BT 601/656 input. Also, MAP-CA supports a ITU-R.BT 601/656 complaint output. 1.7.1.1 Transport Channel Interfaces The video input unit implements two DVB compliant transport channel interfaces which receive demodulated channel data in transport layer format. The Transport Channel Interface (TCI) accepts MPEG-2 system transport packets in either in byte parallel or bit serial form (default). Data rates up to 80Mbps (serial) or 30MBps (byte-wide parallel) are supported. By default, serial data is input on tci_data[0] and parallel data is input on tci_data[7:0] with bit 7 the most significant. These orientations can be reversed by PIO programming. The TCI synchronizes packet data received in broadcast applications such as satellite or cable. The TCI can detect inline sync bytes, which are the first byte of every transport header. Alternatively, the TCI can utilize the external tci_sync signal. Once byte-sync has been detected, the TCI moves b yte-al igned d ata in to MA P -CA memo ry usin g t he DataStreamer. The number of bytes in each packet is programmable. At the end of every packet, the TCI appends an eight-byte postscript that includes time stamps from the local clock counter. This information is used for implementing a software loop filter for controlling an external VCXO. The clock counter within the TCI can also be used as a programmable timer with a resolution of 27MHz to generate periodic interrupts. The two Transport Channel Interface peripherals (primary and secondary) are identical, except that the secondary TCI cannot control the external VCX0. Equator Technologies, Inc. 7 MAP-CA Data Sheet 1.7.1.3 ITU-R.BT 601/605 Output Interface A glueless interface to a ITU-R BT.656 NTSC video encoder is provided enabling the MAP-CA to directly generate high-quality NTSC or PAL video-output signals. This interface supports ITU-R BT.601/656 8-bit 525 and 625 line resolutions with either separate H,V sync (601) or inline sync (656). Advanced video post-filtering on the MAP-CA processor via software can produce flicker free output when converting interlace-to-progressive output. The external NTSC/PAL encoder is controlled using the I2C Serial Bus. The 656 output can also be used as an additional output for transferring data at 54MB/s . Various product configurations use this I/O for additional bandwidth beyond the PCI buses in multiprocessor system. The clock of this interface can be sourced from either pclk or pixelclk_bpy)in through PIO programming. internally generated lr clock and bit clock to the input (slave) . 1.7.3 Display Refresh Controller Sophisticated video blending, 2D graphics with alpha blending, PIP, and hardware cursor overlays for EPGs (Electronic Program Guides) and navigation services have been designed into the display refresh controller. Color space conversion, Gamma correction, and choice of YCbCr or RGB output format is supported. IMBus Memory Controller CRTC Display List Cursor Generator Alpha channel state controls to all sections 8 Video Video Bus Filter Graphic Video #2 Fmt Conversion Format Up/Down Scaling Conversion Key Video #1 Rcv MUX MUX Color Space Conversion RGB<-->YUV MUX By Pass Pipeline MUX Color Space Conversion RGB<-->YUV MUX By Pass Pipeline MUX MUX 1.7.2.1 IEC958 Audio Interface This interface supports several audio standards: 1.7.2.2 I 2S Interface The I2S interface drives high quality (better than 95 dB SNR) audio D/A converters for home theater. The MAP-CA interface meets the requirements of the standard serial data protocol, and provides connection up to three stereo DAC and one ADC. It supports 48KHz, 44.1KHz and 32KHz audio sample rates. Timing is software configurable to either 24, 20, 18 or 16-bit mode. Data sourced from MAP-CA is software configurable to 24 or 16-bit format with either straight or reverse order. MAP-CA I2S supports both master and slave mode interface, with the choice of using either external or VS mem IOBus 1.7.2 Audio Interfaces * Sony Phillips Digital Interface (SPDIF) * Audio Engineering Society/European Broadcast Union (AES/EBU) interface * TOSLINK interface * The TOSLINK interface requires external IR devices. * The IEC958 protocol convention calls for each multi-bit field in a sound sample to be shifted in or out with the least significant bit first (little-Endian). The MAP-CA interface corrects this so that 16-bit samples are "MSB justified" within a 20-bit software sample. The MAP-CA IEC958 interface also automatically calculates even parity on each sub-frame before inserting it into the bit stream. PMBus Data Streamer Alpha Pipe Insert 1.7.1.2 ITU-R.BT 601/656 Input Interface This interface provides direct connection to a ITU-R BT.656 format NTSC/PAL video input decoder. The decoder is controlled using the I2C Serial Bus. The interface can be used as an additional input for transferring data at 54 MB/s. Cursor Insert | Alpha Blender NTSC Output ITU-R 656 output Byte-wide parallel horizontal blender chroma subsampler ITU-R 656 formatter slow bus fast bus Signature analyzer Display Refresh Controller NTSC/PAL Encoder (off chip) 1.7.4 DACs The MAP-CA RGB DACs (Digital-To-Analog Converter) are part of the Display Refresh Controller block. The DACs are 8-bits with pixel clock rate up to 110 MHz. MAP-CA generates RS-343A compatible monitor signals into doubly terminated 75Ohm load and is capable of driving standard SVGA monitors. The full scale output level is determined by an external reference voltage Vref at 1.235V and an external resistor Rnominal=1117 Ohms. The full scale level can be adjusted by adjusting the resistor value. The DACs output the three primary analog color signals: red video, green video and blue video, with the video sync information superimposed on the green video output. Note: internally, there are actually 4 DACs - the R, G, B DACs and Equator Technologies, Inc. a SYNC DAC. The SYNC ouput is superimposed on the green DAC output). programmed to be taken out of bypass mode until after the VLIW core has been unstalled. 1.7.5 I2C Interface Unit The Inter-Integrated-Circuit bus (I 2 C) was originally developed to facilitate communications and control among integrated circuits in consumer electronics. Equator utilizes this standard primarily to facilitate communications between the MAP-CA and external devices. Comprising a two-line serial interface, I2 C provides the physical layer (signaling) allowing the MAP-CA to serve as a master or slave device residing on the I2C bus. It requires no additional hardware for a MAP-CA system to relay status and control information to external devices. Alternatively, for booting via the PCI interface, ROMCON plays a mostly passive role. In this case, an external host loads the VfMem with boot code and initiates boot of the VLIW core via a PIO write to unstall the VLIW CPU. The I 2 C interface unit has an additional output signal, iic_select (part of the I/O Switchable Pin Selector) that allows MAP-CA software to control an e xternal analog multiplexer/level converter that can multiplex between a regular I 2C bus and any other external bus like DDC for a monitor interface. This signal can also be used as a general purpose output 1.7.6 ROM Controller The ROM Controller (ROMCON) unit performs four distinct functions: * Chip Configuration and ROM Boot Sequencer: a state machine for reading chip configuration and boot code at system startup; * Flash ROM Interface: controls the actual reading and and writing of an off-chip Flash ROM device; * Interrupt Controller/Collector: provides a means for enabling, setting, and clearing hardware and software interrupts to the VLIW core and PCI bus controller; and * PLL I/O: provides direct PIO access to the programmable registers related to the various on-chip PLLs. ROMCON also runs power-on diagnostics during the boot, and may be paused at various points for status testing. ROMCON requires minimal chip resources so that standard power-on diagnostics can run without having to bring up all portions of the chip, so that the chip can be tested in more maneable stages. The power-on self-tests generate a single success or failure message on the I2C bus. The three on-chip PLLs for the core/SDRAM, pixel, and audio clocks are programmed indirectly via PIO registers within the ROMCON unit. 1.7.7 Reset Strap During reset the eight ntsc_out_data pads are used as inputs to read pre-boot configuration settings. These are settings that must be known before the actual boot process begins, namely, whether the system should boot from ROM, and whether PCI should serve as host for its bus. There are also four straps available whose meaning can be defined in software. Each strap pad is pulled high (to IOVDD) or low (to GND) through a 20 K-ohm resister. The pads are sampled into flipflops until reset is deasserted and then saved in the so ftwa re -visib le St ra pBits field of P IO registe r ConfigBusControl. For more information see Section 4.12 ROM and Reset Strap on page 20. The purpose of the Configuration/Boot Sequencer is to control the boot up process of the chip. During reset, the resistor straps connected to the ntsc_out_data[7:0] pins are examined to determine how MAP-CA will configure itself and boot. If the resistor straps indicate to boot from ROM, the BootSequencer directs the Flash ROM Interface Controller to transfer bytes from the external ROM device to the MAP-CA configuration registers and to the PCI configuration registers. The 6KB line buffer memory of the Video Filter is then used to store the bootstrap program for system boot up. ROMCON copies the next 4KB from ROM into the Video Filter memory (VfMem) through an 8-bit configuration bus. After the boot code has been loaded, ROMCON unstalls the VLIW CPU which in turn begins to execute the boot code out of VfMem. Th e RO M C ON u ni t op er ate s a t 27 M H z du ri ng th e configuration loading, since the core PLL cannot be Equator Technologies, Inc. 9 MAP-CA Data Sheet 2. Software Development include: The Equator iMMediaTools software developer kit includes * Uncover instruction-level parallelism * Manage registers, pipelines and functional units * Highly-optimized, parallelizing C-language compiler * FIRtreeTM Media Intrinsic C-language extensions * Assembler * Linker * Source-level debugger * Assembly-level debugger * Profiling CPU simulator * Virtual-machine, cycle-accurate simulator * Assorted libraries T he E quator iMMedia CTM Compiler s upports development in a host environment that differs from the target environment. The virtual-machine simulators allows testing and debugging on your host system. The supported host development environments are Microsoft Windows NT and Linux. 2.1 The C Compiler T h e M A P - C A de v elo p m e n t sy st em i n cl ud e s th e iMMediaC Compiler with FIRtreeTM Media Intrinsic. The FIRtreeTM extensions are proprietary SIMD-style high-speed media processing extensions. The C Compiler uses aggressive optimization and global scheduling technology (including Trace Scheduling) to deliver full hardware performance without using laborious assembly language programming. It allows programmers to focus efforts on algorithm optimization versus assembly scheduling, resource allocation and debug. Unlike existing DSPs or dedicated-function devices which have heretofore been used to meet media processing requirements, a programmer will program the MAP-CA in a high-level language (C). Benefits of programming in C include: * Reduced development costs * Reduced time to market * Lower system costs * Reduced maintenance time * Software-based upgrades The MAP-CA development environment includes a C compiler with F IRtree T M M ed ia I ntrin sic operatio n extensions. The FIRtreeTM extensions are proprietary SIMDstyle high-speed media processing extensions. * Generate instruction operation schedules that exploit parallelism * Support extensive global optimization, analysis and scheduling * Provide local scheduling and optimization * Support media-oriented machine facilities * Manages all timing dependencies to maximize scheduling efficiency The C Compiler shell program lets you compile, examine, test, profile, assemble, and link source programs with a single command, by using various options. 2.1.1 The FIRtreeTM Media Intrinsics The FIRtreeTM Media Intrinsics read 128-bit words of data memory for each cluster, each of which contain multiple data items, and perform operations simultaneously on each of the items within the word. The FIRtreeTM Media Intrinsics C-language extensions perform operations on partitioned native data types within 32or 64-bit operands, making use of the PLV and PLC registers on the IG-ALU to store intermediate values. 2.2 Libraries The Equator iMMediaC Compiler includes standard C runtime libraries and libraries specifically designed to support M AP -CA resources su ch as DataStreamer and VLx coprocessor for media applications. 2.3 Assembler The assembler lets the programmer take the assembly language source files generated by the compiler, and convert them into object code files, ready for the linker. Developers will not typically write assembly language modules themselves. 2.4 Linker The linker combines object code files into an executable module, accepting both object files and object libraries as input. During linking, the linker resolves all external references. 2.5 Debugger The Equator compiler uses complex inline expansion, assertions, and loop unrolling with trace frequency estimation algorithms to maximize C code efficiency. The optimizations 10 Equator's development environment includes a sourcelevel debugger based on gdb (GNU debugger). Equator's gdb (egdb) runs on both the Windows NT and Linux platforms. Equator Technologies, Inc. The egdb debugger allows the user to an application. * load a MAP-CA application from the host PC file system onto the MAP-CA and run it * set, list, and clear software and hardware breakpoints * single step through both C source code and assembly instructions * source level debug of optimized C code * examine and deposit values into local variables, global variables and PIO space * examine and deposit values into all registers * examine the stack, including stack backtracing Numerous freeware or low-cost gdb GUI front ends exist on both the Windows NT and Linux platforms that will transparently layer on egdb's command line interface and provide a window-based debugging environment. 2.6 Simulators The software developer's toolkit includes three software simulators: trsim, sim, and casim. Trsim is a high speed, instruction level simulator of the MAP-CA core unit. This simulator works on an intermediate representation of a software program and can be used to initially develop applications and experiment with the performance of different algorithms and use of compiler options. Sim is also a high speed, instruction level simulator. This simulator works off actual MAP-CA binaries. Sim is a functional simulator of the MAP-CA core unit with data cache, DataStreamer, and a subset of I/O devices. It provides runtime checks against resource constraints and all MAP-CA features necessary to simulate a MAP-CA running a real-time operating system and applications. Casim is a nearly cycle accurate software simulator for the MAP-CA and models more accurate ly the core, DataStreamer, VLx, Video Filter, instruction and data caches, memories, buses, and a subset of supported I/O devices. Like sim, this simulator operates off actual MAP-CA binaries. Casim provides more detailed runtime checks against resource constraints. Casim provides visibility into internal machine state and bandwith and augments debugging and tuning of interactions between VLIW core, DataStreamer, and VLx programs. Sim and casim work in conjunction with Equator's sourcelevel debugger. 2.7 Boot Software must contain boot code for execution on MAPCA. This boot code configures TLBs and caches. Equator software tools can automatically add boot code when building Equator Technologies, Inc. 11 MAP-CA Data Sheet 3. BGA PIN_OUT Assignment Signal assignment on the BGA352 package is shown here. . The diagram is the bottom view, with the balls facing the viewer Signal Name 26 Ball audioclk_byp_in A2 aVdd18 B3 aVss C4 aVdd18 D5 aVss A3 24 25 22 23 20 21 18 19 16 17 14 15 12 13 10 11 8 9 6 7 4 5 2 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF pixelclk_byp_in B4 ntsc_out_data[3] C5 ntsc_out_data[4] B5 ntsc_out_data[5] A4 ntsc_out_data[6] C6 ntsc_out_data[7] D7 video_ina[0] B6 video_ina[1] C7 video_ina[2] D8 video_ina[3] A6 video_ina[4] B7 video_ina[5] A7 video_ina[6] C8 Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball video_ina[7] D9 ntsc_inb_clk27 D14 sddata[2] D19 sddata[20] G24 sdras_ T25 video_ina[8] B8 vsync A16 sddata[3] A23 sddata[21] G25 sdcas_ T24 video_ina[9] C9 hsync B15 sddqm[0] B22 sddata[22] H25 sdwe_ U25 tcia_inuse A8 tms B16 sddata[4] C21 sddata[23] H24 sdadr[0] U24 tcia_sync A9 trst C15 sddata[5] A24 sddata[24] H26 sdadr[1] V26 tcia_clk C10 aVss A17 sddata[6] B23 sddata[25] J24 sdadr[2] V24 tcia_vdac B10 gdac_fscale B17 sddata[7] C22 sddata[26] J25 sdadr[3] W25 ntsc_ina_clk27 A10 gdac_comp C16 sddata[8] D21 sddata[27] K24 sdadr[4] Y26 video_inb[0] C11 aVdd33 D16 sddata[9] A25 sddqm[3] K26 sdadr[5] W24 video_inb[1] B11 gdac_green C17 sddata[10] B24 sddata[28] L24 sdadr[6] Y25 video_inb[2] A11 gdac_blue A18 sddata[11] C23 sddata[29] L25 sdadr[7] Y24 video_inb[3] D12 gdac_red A19 sddqm[1] D22 sddata[30] M25 sdadr[8] AA25 video_inb[4] C12 gdac_cvgg (aVss) C18 sddata[12] D24 sddata[31] M24 sdadr[9] AA24 video_inb[5] B12 aVddx (aVdd18) D17 sddata[13] B26 sdcs_[0] M26 sdadr[10] AB26 video_inb[6] A13 aVssx (aVss) B19 sddata[14] C25 sdcs_[1] N24 sdadr[11] AD26 video_inb[7] C13 tdi A20 sddata[15] E24 sdcs_[2] N25 sdadr[12] AB24 video_inb[8] D13 tck B20 sddata[16] D25 sdcs_[3] P26 sdadr[13] AD25 video_inb[9] B13 tdo C19 sddata[17] D26 sdrtnclk P24 sddata[32] AC24 tcib_inuse A14 no connection A21 sddata[18] E25 sdclk R25 sddata[33] AB23 tcib_sync B14 sddata[0] B21 sddata[19] F24 sdclk1 R24 aVss AC22 tcib_clk C14 sddata[1] C20 sddqm[2] F26 sdclk2 T26 aVssq (aVss) AD23 12 26 24 25 22 23 20 21 18 19 16 17 14 15 12 13 10 11 Equator Technologies, Inc. 8 9 6 7 4 5 2 3 1 Signal Name Ball aVddq (aVdd18) aVdd18 Signal Name Ball Signal Name Ball Signal Name Ball Signal Name Ball AE24 pci_ad[3] AF8 pci_ad[30] T2 Vdd18 T23 Vdd33 L4 AF25 pci_ad[4] AD9 pci_ad[31] R3 Vdd18 V23 Vdd33 H4 sdclk_byp_in AC21 pci_ad[5] AE8 pci_req_[0] R2 Vdd18 W23 Vss A1 pclk AD22 pci_ad[6] AC9 pci_req_[1] R1 Vdd18 AA23 Vss B1 coreclk_byp_in AE23 pci_ad[7] AD8 pci_req_[2] P3 Vdd18 AC20 Vss B2 pci_clk AF24 AF7 pci_gnt_[0] P1 Vdd18 AC16 Vss A5 sddata[34] AD21 pci_ad[8] AF6 pci_gnt_[1] N1 Vdd18 AC11 Vss B9 sddata[35] AF23 pci_ad[9] AD7 pci_gnt_[2] N2 Vdd18 AC7 Vss A12 sddqm[4] AF22 pci_ad[10] AC8 pclk_out N3 Vdd18 AB4 Vss A15 sddata[36] AE21 pci_ad[11] AE6 pci_rst_ M2 Vdd18 AA4 Vss B18 sddata[37] AC19 pci_ad[12] AF5 pci_inta_ M3 Vdd18 W4 Vss A22 sddata[38] AD20 pci_ad[13] AF4 pci_pme_ L1 Vdd18 T4 Vss A26 sddata[39] AF21 pci_ad[14] AD6 iic_sda L2 Vdd18 P4 Vss B25 sddata[40] AF20 pci_ad[15] AF3 iic_sck L3 Vdd18 N4 Vss C26 sddata[41] AC18 pci_cbe_[1] AE4 ddc_select K1 Vdd18 M4 Vss E26 sddata[42] AD19 pci_par AD5 iis_in_data K3 Vdd18 J4 Vss F25 sddata[43] AE19 pci_serr_intb_ AC6 iis_in_lr J1 Vdd18 G4 Vss G26 sddqm[5] AD18 pci_stop_ AF2 iis_in_bclk K4 Vdd18 F4 Vss J26 sddata[44] AF19 AE3 iis_out_data[0] J2 Vdd33 C3 Vss K25 sddata[45] AE18 pci_trdy_ AD4 iis_out_data[1] J3 Vdd33 D4 Vss L26 sddata[46] AD17 pci_irdy_ AC5 iis_out_data[2] H2 Vdd33 E4 Vss N26 sddata[47] AE17 Vsbb (Vss) AD2 iis_out_lr G1 Vdd33 D10 Vss P25 sddata[48] AF17 Vsbc (Vdd18) AE1 iis_out_bclk H3 Vdd33 D18 Vss R26 sddata[49] AD16 Vdbb (Vdd18) AC3 iec958_in G2 Vdd33 C24 Vss U26 sddata[50] AF16 Vdbc (Vss) AB3 iec958_out G3 Vdd33 D23 Vss V25 sddata[51] AC15 pci_frame_ AC2 rom_cs_ F1 Vdd33 F23 Vss W26 sddqm[6] AD15 pci_cbe_[2] AC1 ntsc_out_hsync F3 Vdd33 J23 Vss AA26 sddata[52] AE15 pci_ad[16] AB1 ntsc_out_vsync E1 Vdd33 L23 Vss AB25 sddata[53] AF15 pci_ad[17] AA2 ntsc_out_data[0] E2 Vdd33 N23 Vss AC26 sddata[54] AD14 pci_ad[18] AA3 ntsc_out_data[1] E3 Vdd33 R23 Vss AC25 sddata[55] AE14 pci_ad[19] AA1 ntsc_out_data[2] C1 Vdd33 U23 Vss AE26 sddata[56] AF13 pci_ad[20] Y3 audioclk_out C2 Vdd33 Y23 Vss AE25 sddata[57] AD13 pci_ad[21] Y2 pixelclk_out D3 Vdd33 AD24 Vss AF26 sddata[58] AF12 pci_ad[22] W1 Vdd18 D6 Vdd33 AC23 Vss AE22 sddata[59] AE12 pci_ad[23] W2 Vdd18 D11 Vdd33 AC17 Vss AE20 sddqm[7] AD12 pci_idsel W3 Vdd18 D15 Vdd33 AC14 Vss AF18 sddata[60] AC12 pci_cbe_[3] V1 Vdd18 D20 Vdd33 AC13 Vss AE16 sddata[61] AF11 pci_ad[24] V3 Vdd18 E23 Vdd33 AC10 Vss AF14 sddata[62] AD11 pci_ad[25] U1 Vdd18 G23 Vdd33 AD3 Vss AE13 sddata[63] AF10 pci_ad[26] U4 Vdd18 H23 Vdd33 AC4 Vss AE11 pci_ad[0] AE10 pci_ad[27] U3 Vdd18 K23 Vdd33 Y4 Vss AF9 pci_ad[1] AD10 pci_ad[28] U2 Vdd18 M23 Vdd33 V4 Vss AE7 pci_ad[2] AE9 T3 Vdd18 P23 Vdd33 R4 Vss AE5 pci_cbe_[0] pci_devsel_ pci_ad[29] Equator Technologies, Inc. 13 MAP-CA Data Sheet Signal Name Ball Vss AF1 Vss AE2 Vss AD1 Vss AB2 Vss Y1 Vss V2 Vss T1 Vss P2 Vss M1 Vss K2 Vss H1 Vss F2 Vss D1 Vss D2 14 Equator Technologies, Inc. 4. Signal Descriptions 4.1 Processor Clock 7KHUHLVDVLQJOHUHIHUHQFHFORFNVLJQDOZKLFKLV0+]7KUHH3//VDUHXVHGWRJHQHUDWHFORFNVQHHGHGLQWHUQDOO\E\ UHIHUULQJWRWKH0+]FORFN $%/(352&(6625&/2&.6,*1$/'(6&5,37,21 7 SIGNAL #a I/Ob DESCRIPTION SFON , 0+]9&;2RVFLOODWRULQSXWLVSURYLGHGWRWKH &RUH6'5$0SL[HODQGDXGLR3//V,WLV DOVRDUHIHUHQFHFORFNWR,785%72XWDQG, & FRUHFONBE\SBLQ , %\SDVVLQSXWIRUWKHFRUHFORFN VGFONBE\SBLQ , %\SDVVLQSXWIRUWKH6'5$0FORFN SL[HOFONBE\SBLQ , %\SDVVLQSXWIRUWKHSL[HOFORFN DXGLRFONBE\SBLQ , %\SDVVLQSXWIRUWKHDXGLRFORFN FRUHFONBRXW 2 2XWSXWIRUWKHFRUHFORFN SL[HOFONBRXW 2 2XWSXWIRUWKHSL[HOFORFN DXGLRFONBRXW 2 2XWSXWIRUWKHDXGLRFORFN 727$/ a. Number of pins b. I: Input; O: output; B: bi-directional. 4.2 PCI Bus 0$3&$SURYLGHVWKH3&,EXVDVWKHSULPDU\V\VWHPLQWHUIDFH,WFDQVXSSRUWXSWRIRXUORDGVRQWKH3&,EXV $%/(3&,6,*1$/'(6&5,37,21 7 SIGNAL # I/O SFLBDG>@ % SFLBFEHB>@ % SFLBIUDPHB % SFLBWUG\B % DESCRIPTION 3&,PXOWLSOH[HGDGGUHVVDQGGDWDOLQHV7KHDGGUHVVLVGULYHQZKHQSFLBIUDPHBLVILUVWDVVHU WHG'DWD LVWUDQVIHU UHGRQWKLVEXVLQVXEVHTXHQWFORFNV )RU3&,F\FOHVWKHEXVFRPPDQGDQGE\WHHQDEOHVDUHXVHGWRWUDQVIHUWKH3&,FRPPDQGGXULQJ WKHDGGUHVVSKDVHDQGDUHXVHGWRWUDQVIHUE\WHODQHHQDEOHVGXULQJVXEVHTXHQWGDWDSKDVHV 7UDQVDFWLRQIUDPLQJIRU3&,WUDQVIHUV7KHLQLWLDODVVHUWLRQLQGLFDWHVWKHDGGUHVVSKDVHDQGWKHVWDUW RID3&,WUDQVDFWLRQ&RQWLQXHGDVVHUWLRQGHWHU PLQHVWKHEXUVWVL]HRIWKHWUDQVDFWLRQ 7KHWDUJHWUHDG\VLJQDOLVDVVHUWHGZKHQWKH3&,WDUJHWLVUHDG\IRUDGDWDWUDQVIHU SFLBLUG\B % 7KHLQLWLDWRUUHDG\VLJQDOLVDVVHUWHGZKHQWKH3&,PDVWHULVUHDG\IRUDGDWDWUDQVIHU SFLBVWRSB % SFLBVWRSBLVDVVHUWHGE\WKHWDUJHWWRUHTXHVWWKHPDVWHUWRVWRSWKHFXUUHQWWUDQVDFWLRQ SFLBSDU % $VLQJOHSDULW\ELWLVFDOFXODWHGRYHUSFLBDG>@DQGSFLBFBEH>@DQGWUDQVI HUUHGRYHUWKLVVLJQDO $WDUJHWDVVHUWVWKHSFLBGHYVHOBVLJQDOOLQHWRLQGLFDWHLWKDVGHFRGHGWKHDGGUHVVRQWKHSFLBDG>@ EXVDQGZLOOSDUWLFLSDWHLQFODLP WKHFXUUHQWWUDQVDFWLRQ7KH3&,EXVPDVWHUPXVWPRQLWRUWKH SFLBGHYVHOB % SFLBGHYVHOBVLJQDOOLQHWRGHWHU PLQHLIDWDUJHWEXVKDVFODLPHGWKHWUDQVDFWLRQRULID0DVWHU$ERUW WHU PLQDWLRQZLOOEHH[HFXWHGSFLBGHYVHOBZLOOEHWULVWDWHGIURPWKHOHDGLQJHGJHRISFLBUVWB SFLBGHYVHOBUHPDLQVWULVWDWHGXQWLOGULYHQE\WKHWDUJHW SFLBFONSURYLGHVWLPLQJIRUDOO3&,WUDQVDFWLRQVRQWKH3&,EXV$OORWKHU3&,VLJQDOVDUHVDPSOHG SFLBFON , RQWKHULVLQJHGJHRISFLBFONDQGDOOWLPLQJSDUDPHWHUVDUHGHILQHGZLWKUHVSHFWWRWKLVHGJH 127(7KH0$3&$FRUHFORFNSOOGRHVQRWXVHWKLVFORFNDVDFRUHSOOUHIHUHQFHFORFN 7KLVVLJQDOLQGLFDWHVDUHVHWRIDOO3&,UHVRXUFHV,QDGGLWLRQWKHLQWHUQDO0$3&$&38FRUHHWF SFLBUVWB , DUHUHVHWE\WKHDVVHUWLRQRIWKLVVLJQDO3&,SDGFHOOGULYHUVDUHGLVDEOHGE\WKHDVVHU WLRQRIWKLV VLJQDODVVSHFLILHGLQWKH3&,GRFXPHQW Equator Technologies, Inc. 15 MAP-CA Data Sheet $%/(3&,6,*1$/'(6&5,37,21 7 :KHQWKH0$3&$LVQRWGHVLJQDWHGDVWKH+267IRUWKH3&,EXVWKHQWKLVVLJQDOLVWKHRSHQ SFLBLQWDB % RG GUDLQRXWSXWXVHGWRJHQHUDWHDQDV\QFKURQRXVOHYHOVHQVLWLYHLQWHUU XSWRQWKH3&,EXV7KH0$3 &$SDGFHOOGRHV127FRQWDLQDSXOOXSIRUWKLVVLJQDO :KHQWKH0$3&$LVGHVLJQDWHGDVWKH+267IRUWKH3&,EXVWKHQWKLVVLJQDOLVDQLQWHUU XSW UHTXHVWLQSXWIURP3&,GHYLFHV7KLVLQWHUU XSWLVVHHQDQGXWLOL]HGE\0$3&$ SFLBLGVHO , SFLBUHTB>@ % SFLBJQWB>@ % 7KHLQLWLDOL]DWLRQGHYLFHVHOHFWLVXVHGDVDVORWDGGUHVVHGFKLSVHOHFWLQSXWGXULQJFRQILJXUDWLRQUHDG DQGZULWHWUDQVDFWLRQV7KLVVLJQDOLVLQDFWLYHLQDVHOIKRVWHGFRQILJXUDWLRQ 7KHDVVHUWLRQRISFLBUHTBLQDQRQVHOIKRVWHGFRQILJXUDWLRQLQGLFDWHVWKDW0$3&$GHVLUHVWKHXVH RIWKH3&,EXV 7KHDVVHUWLRQRISFLBJQWBLQDQRQVHOIKRVWHGHQYLURQPHQWLQGLFDWHVWKDW0$3&$KDVEHHQ JUDQWHGWKHXVHRIWKH3&,EXV 7KLVRSHQGUDLQRXWSXWFDQHLWKHUEHXVHGWRJHQHUDWHDQDV\QFKURQRXVOHYHOVHQVLWLYHLQWHU UXSWRQ WKH3&,EXVRURSWLRQDOO\WRVLJQDO6<67(0(55256HHWKH0$3&$FRQILJXUDWLRQFRQWURO UHJLVWHUIRUWKHFXU UHQWXVHRIWKLVVLJQDO SFLBVHUUBLQWEB % :KHQ0$3&$LVQRWGHVLJQDWHGDVWKH+267IRUWKH3&,EXVWKHQWKLVVLJQDOLVWKHRSHQGUDLQ RG RXWSXWXVHGWRJHQHUDWHDQDV\QFKURQRXVOHYHOVHQVLWLYHLQWHU UXSWRQWKH3&,EXV7KH0$3&$SDG FHOOGRHV127FRQWDLQDSXOOXSIRUWKLVVLJQDO :KHQ0$3&$LVGHVLJQDWHGDVWKH+267IRUWKH3&,EXVWKHQWKLVVLJQDOLVDQLQWHUU XSW UHTXHVWLQSXWIURP3&,GHYLFHV7KLVLQWHUU XSWLVVHHQDQGXWLOL]HGE\WKH0$3&$ :KHQ0$3&$LVQRWLQ3&,KRVWPRGHWKLVVLJQDOLVDQRSHQGUDLQRXWSXWXVHGWRUHTXHVWD SFLBSPHB % FKDQJHLQSRZHUPDQDJHPHQWVWDWH RG :KHQ0$3&$LVLQ3&,KRVWPRGHWKLVLVDQLQSXWVLJQDOWRZKLFK3&,GHYLFHVLQGLFDWHFKDQJHVLQ SRZHUPDQDJHPHQWVWDWH 727$/ 4.3 SDRAM 0$3&$VXSSRUWVHLWKHU6'5$0RU6*5$0PHPRU\V\VWHPXVLQJVLJQDOVVKRZQEHORZ$PHPRU\V\VWHPRIELWRU ELWGDWDZLGWKLVVXSSRUWHG'5$0ZLGWKVRIELWELWRUELWDUHVXSSRUWHG $%/(0(025<,17(5)$&(6,*1$/6 7 16 SIGNAL # I/O DESCRIPTION VGDGU>@ 2 VGGDWD>@ % VGFVB>@ 2 $GGUHVVOLQHVLQGLFDWHURZDGGUHVVHVZKHQVGUDVBLVDFWLYHZKLOH$GGUHVVOLQHVLQGLFDWHFROXPQ DGGUHVVHVZKHQVGFDVBLVDFWLYH 'DWD,QSXW2XWSXWOLQHVWUDQVIHUGDWDEHWZHHQWKHPHPRU\DQG0$3&$7KHVHDUHDOVRLQSXWPDVN ELWVIRU:ULWHSHU%LW:KHQEORFNZULWHLVDFWLYDWHGWKHVHOLQHVSURYLGHFROXPQDGGUHVVPDVN &KLS6HOHFWVLJQDOOLQHVLQGLFDWHWKDWWKHFRPPDQGRQWKHRXWSXWOLQHVLVIRUHDFKPHPRU\FKLS,IWKLV VLJQDOLVKLJKWKHRXWSXWFRPPDQGV ZLOOEHLJQRUHGE\HDFKFRUUHVSRQGLQJPHPRU \FKLS VGUDVB 2 VGUDVBLVSDUWRIWKHRXWSXWFRPPDQGWRWKH6'*5$0 VGFDVB 2 VGFDVBLVSDUWRIWKHRXWSXWFRPPDQGWRWKH6'*5$0 VGZHB 2 :ULWHHQDEOHVGZHB LVSDUWRIWKHRXWSXWFRPPDQG VGGTP>@ 2 VGFONVGFONVGFON 2 VGUWQFON , 727$/ 'XULQJUHDGVGGTP WXUQVRIIWKHRXWSXWEXIIHUVRI6'*5$0'XULQJZULWHVGGTP SUHYHQWV DZULWHWRWKHFXU UHQWPHPRU\ORFDWLRQ VGFONVGFONDQGVGFONDUHGULYHQE\WKH0$3&$6'5$0FORFN$OO6'*5$0LQSXWVLJQDOVDUH VDPSOHGRQWKHSRVLWLYHHGJHRIVGFON VGUWQFONLVGULYHQE\VGFON7KLVVLJQDOLVXVHGIRUODWFKLQJWKHGDWDIURP6'6*5$0 Equator Technologies, Inc. 4.4 Flash ROM $)ODVK520((3520 LQWHUIDFHLVSURYLGHGRQ0$3&$WRDVVLVWLQERRWXS7 KH)ODVK520LVDFWLYHGXULQJWKH ERRWXSSURFHVVDQGPXVWEHGLVDEOHGWKURXJKLWVFKLSVHOHFWVLJQDO $%/(520,17(5)$&(6,*1$/6 7 Name # I/O DESCRIPTION URPBFVB 2 7KLVSLQLVWKHFKLSHQDEOHVLJQDO URPBRHB 2 7KLVDFWLYHORZVLJQDOLVDVVHU WHGRQ520UHDGF\FOHV7KLVVLJQDOLVPXOWLSOH[HGZLWKLLVBRXWBGDWD>@ URPBZUWB 2 URPBDOH 2 7KLVDFWLYHORZVLJQDOLVDVVHUWHGRQ520ZULWHF\FOHV7KLVVLJQDOLVPXOWLSOH[HGZLWK LLVBRXWBGDWD>@ $GGUHVVODWFKHQDEOHURPBDGGU>@DQGURPBDGGU>@DUHODWFKHGRQWKHULVLQJHGJH URPBDGGU>@DQGURPBDGGU>@DUHODWFKHGRQWKHIDOOLQJHGJH7KLVVLJQDOLVPXOWLSOH[HGZLWK LLVBRXWBGDWD>@ URPBDGGU>@U RPBDGGU>@UR 7ZR/6%VDQGKLJKRUGHUELWVRIWKH520DGGUHVVDUHDOZD\VGHPX[HG 2 URPBDGGU>@URPBDGGU>@URPBDGGU>@LVPXOWLSOH[HGZLWKQWVFBRXWBKV\QF PBDGGU>@ URPBDGGU>@URPBDGGU>@URPBDGGU>@LVPXOWLSOH[HGZLWKQWVFBRXWBYV\QF URPBDGGU>@URP BDGGU>@URPB ,2 520GDWDDQGDGGUHVVEXV7KLVVLJQDOLVPXOWLSOH[HGZLWKQWVFBRXWBGDWD>@ GDWD>@ 727$/ 4.5 Analog CRT $Q5*%PRQLWRUFDQEHGLUHFWO\GULYHQE\0$3&$ $%/(&57,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION YV\QF 2 9HU WLFDOV\QFKURQL]DWLRQVLJQDOIRU&57 KV\QF 2 +RUL]RQWDOV\QFKURQL]DWLRQVLJQDOIRU&57 JGDFBIVFDOH $ )XOOVFDOHFXU UHQWDGMXVWLQJUHVLVWHU JGDFBFRPS $ 9UHIE\SDVVDQGFRPSHQVDWLRQFDSDFLWRU JGDFBEOXH $ $QDORJEOXHRXWSXW JGDFBJUHHQ $ $QDORJJUHHQRXWSXW JGDFBUHG $ $QDORJUHGRXWSXW 727$/ 4.6 ITU-R BT.601/656 Output . 7$%/(,785%7287387 , 17(5)$&(6,*1$/6 0$3&$KDVDGLUHFW,785%7RXWSXWLQWHUIDFH SIGNAL # I/O DESCRIPTION WFLDBYGDF 2 QWVFBFONBYF[R , QWVFBRXWBKV\QF 2 9&;2IUHTXHQF\FRQWUROVWUHDP 0+],785%7SL[HOFORFNIURPYLGHR9&;2FORFNLQSXW7KLVVLJQDOLV DFWXDOO\SFON6HH6HFWLRQ3URFHVVRU&ORFN +RUL]RQWDOV\QF QWVFBRXWBYV\QF 2 9HUWLFDOV\QF QWVFBRXWBGDWD>@ % ,785%7IRUPDWWHG176&RU3$/RXWSXWGDWD 727$/ Note that ntsc_out_data[7:0], ntsc_out_hync, and ntsc_out_vsync are multiplexed over ROM address/data signals. See the Section 4.12, ROM and Reset Strap. Equator Technologies, Inc. 17 MAP-CA Data Sheet 4.7 Video Input Ports 0$3&$SURYLGHVWZR9LGHR,QSRUWV(DFKSRUWFDQEHFRQILJXUHGDVHLWKHUD7&,RU,785%7SRUW7KH\ ERWKKDYHWKHVDPHVLJQDOV7KH\DUHPX[HGDVVKRZQEHORZ $%/(35,0$5<9,'(2,13257 7 Two Selectable Video Input Ports SIGNAL # I/O YLGHRBLQD>@ , WFLDBHU UB Parallel TCI QWVFBLQDBYV\QF 601 Input YLGHRBLQD>@ , WFLDBHQDEOH QWVFBLQDBKV\QF YLGHRBLQD>@ , WFLDBGDWD>@ QWVFBLQDBGDWD>@ 727$/ $%/(6(&21'$5<9,'(2,13257 7 Two Selectable Video Input Ports SIGNAL # I/O Parallel TCI 601 Input YLGHRBLQE>@ , WFLEBHU UB QWVFBLQEBYV\QF YLGHRBLQE>@ , WFLEBHQDEOH QWVFBLQEBKV\QF YLGHRBLQE>@ , WFLEBGDWD>@ QWVFBLQEBGDWD>@ 727$/ 4.7.1 Transport Channel Interface (TCI) 0$3&$SURYLGHVWZRSDUDOOHOVHULDO7&,LQWHUIDFHV $%/(35,0$5<7&,,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION WFLDBGDWD>@ , WFLDBHQDEOH , 7&,GDWDLQSXW $OOELWVRILQSXWDUHXVHGLQSDUDOOHOPRGH2QO\WFLBGDWD>@LVXVHGLQVHULDOPRGH 7UDQVSRUWFKDQQHOHQDEOH DFFHSWDE\WHRI7&,LQSXW VWDOO7&,LQSXW 9LGHRLQSXWSRUWH[WHU QDOPX[VHOHFW WFLDBLQXVH 2 VHOHFWWUDQVSRUWVWUHDPIRUYLGHRLQSXWSRUW VHOHFW ,785%7 VWUHDPIRUYLGHRLQSXW&DQDOVREHXVHGDVDJHQHUDOSXUSRVHRXWSXWLI G\QDPLFYLGHRPX[LQJLVQRWUHTXLUHG WFLDBV\QF , WFLDBHU UB , WFLDBFON , WFLDBYGDF 2 727$/ 'HPRGXODWRU)(&KDVPDUNHGWKHV\QFKURQL]DWLRQSRLQWLQWKH%03(*SDFNHW 7KLVDFWLYHORZVLJQDOLQGLFDWHVWKDWWKH'HPRGXODWRU)(&KDVGHWHFWHGDQXQFRUUHFWDEOH HUURULQ WKHFXU UHQWSDFNHW 7UDQVSRUWFKDQQHOFORFNFDQDFFHSWLQSXWXSWR0+]IRUSDUDOOHOPRGHDQGXSWR0+]IRU VHULDOPRGH 6LPXODWHGVLJPDGHOWDRXWSXWSURYLGLQJ9&;2RIIVHWIRUWKHYLGHRFORFNVRXUFH $%/(6(&21'$5<7&,,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION WFLEBGDWD>@ , WFLEBHQDEOH , 7&,GDWDLQSXW $OOELWVRILQSXWDUHXVHGLQSDUDOOHOPRGH2QO\WFLBGDWD>@LVXVHGLQVHULDOPRGH 7UDQVSRUWFKDQQHOHQDEOH DFFHSWDE\WHRI7&,LQSXW VWDOO7&,LQSXW 9LGHRLQSXWSRUWH[WHU QDOPX[VHOHFW WFLEBLQXVH 2 VHOHFWWUDQVSRUWVWUHDPIRUYLGHRLQSXWSRUW G\QDPLFYLGHRPX[LQJLVQRWUHTXLUHG 18 VHOHFW ,785%7 VWUHDPIRUYLGHRLQSXW&DQDOVREHXVHGDVDJHQHUDOSXUSRVHRXWSXWLI Equator Technologies, Inc. $%/(6(&21'$5<7&,,17(5)$&(6,*1$/6 7 WFLEBV\QF , WFLEBHUUB , WFLEBFON , 727$/ 'HPRGXODWRU)(&KDVPDUNHGWKHV\QFKURQL]DWLRQSRLQWLQWKH%03(*SDFNHW 7KLVDFWLYHORZVLJQDOLQGLFDWHVWKDWWKH'HPRGXODWRU)(&KDVGHWHFWHGDQXQFRU UHFWDEOH HUURULQ WKHFXUUHQWSDFNHW 7UDQVSRUWFKDQQHOFORFNFDQDFFHSWLQSXWXSWR0+]IRUSDUDOOHOPRGHDQGXSWR0+]IRU VHULDOPRGH 4.7.2 ITU-R BT.601/656 Input $QDORJYLGHRFDQEHVWUHDPHGLQYLDD176&3$/RU69,'(2GHFRGHUZLWK,785%7IRUPDWWHGLQSXW7 KH SULPDU\DQGVHFRQGDU\,785%7,QSRUWVKDYHWKHVDPHVLJQDOVDVVKRZQEHORZ $%/(35,0$5<,785%7,1387,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION QWVFBLQDBFON , 0+] ,785%7 FORFNIURPYLGHRGHFRGHU QWVFBLQDBKV\QF , +RUL]RQWDOV\QF QWVFBLQDBYV\QF , 9HU WLFDOV\QF QWVFBLQDBGDWD>@ , 727$/ ,785%7 IRU PDWWHG176&RU3$/YLGHR LQSXWVWUHDP $%/(6(&21'$5<,785%7,1387,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION QWVFBLQEBFON , 0+],785%7 FORFNIURPYLGHRGHFRGHU QWVFBLQEBKV\QF , +RUL]RQWDOV\QF QWVFBLQEBYV\QF , 9HU WLFDOV\QF QWVFBLQEBGDWD>@ , 727$/ ,785%7 IRU PDWWHG176&RU3$/YLGHR LQSXWVWUHDP 4.8 I2S 0$3&$SURYLGHVDQ,6GLJLWDODXGLRLQWHUIDFHDVVKRZQEHORZ $%/(,6,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION LLVBLQBGDWD , 6HULDO7'0LQSXWVWUHDPWRSULPDU \FRGHF LLVBLQBOU , 6HOHFWOHIWULJKWFKDQQHOLQWKHVHULDOLQSXWOLQH LLVBLQBEFON , , 6FORFNWRLQSXWGDWDRQWKHVHULDOLQSXWOLQH LLVBRXWBGDWD>@ 2 6HULDO7'0RXWSXWVWUHDPWRSULPDU \FRGHF LLVBRXWBPFON 2 , 6RXWSXWPDVWHUFORFN7KLVVLJQDOLVDFWXDOO\ DXGLRFONBRXW6HH6HFWLRQ3URFHVVRU&ORFN LLVBRXWBOU 2 6HOHFWOHIWULJKWFKDQQHOLQDVHULDORXWSXWOLQH LLVBRXWBEFON 2 , 6FORFNWRWUDQVIHUGDWDRQGLJLWDODXGLRVHULDOOLQHV 727$/ Equator Technologies, Inc. 19 MAP-CA Data Sheet 4.9 IEC958 0$3&$SURYLGHVDQ,(&LQWHUIDFHDVVKRZQEHORZ $%/(,(&,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION LHFBLQ , 6HULDOLQSXWOLQHIRU,(&GLJLWDODXGLR LHFBRXW 2 6HULDORXWSXWOLQHIRU,(&GLJLWDODXGLR 727$/ 4.10 I2C MAP-CA provides an I2C interface to communicate with external peripherals such as NTSC decoders, NTSC encoders, Demodulators, etc. This interface can also be used to control a monitor such as by the DDC for a monitor through software control (iic_select). The pin description is shown in the following table. $%/(,&,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION LLFBVGD % , &GDWDOLQH LLFBVFN % , &FORFNOLQH LLFBVHOHFW 2 3URJUDPPDEOH,2SLQXVHGWRVHOHFWEHWZHHQ, &DQGDQRWKHUH[WHUQDOEXV 727$/ 4.11 JTAG 7KH-7$*SLQVRQ0$3&$FRQIRU PWRWKH,(((-7$*VSHFXVHGIRUPDQXIDFWXULQJWHVW $%/(-7$*,17(5)$&(6,*1$/6 7 SIGNAL # I/O DESCRIPTION WFN , 7HVWFORFNLQSXW WPV , 7HVWPRGHVHOHFWWRFRQWUROWHVWRSHUDWLRQV WGL , 7HVWGDWDLQSXWGDWD WGR 2 7HVWGDWDRXWSXW WUVW , 7HVWUHVHWVLJQDOWRDV\QFKURQRXVO\UHVHWWKH7$3FRQWUROOHU 727$/ 4.12 ROM and Reset Strap 7RVDYHSLQV0$3&$DOORZVDFFHVVWRD)ODVK520RQO\ZKHQWKH9HUVD3RUWSLQVDUHHQDEOHGIRUXVHE\520&21 HJGXULQJERRW DQGWRWKHUHVHWVWUDSVRQO\GXULQJUHVHW7KH520DQG5HVHW6WUDSVLJQDOVVKRXOGEHFRQQHFWHGWR 0$3&$VLJQDOVDVVKRZQEHORZ $%/(520$1'5(6(7675$3&211(&7,216 7 Signal Run Time 20 Signal Pin # Reset Time Rom Boot Description for Resistor Straps QWVFBRXWBGDWD>@ VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW QWVFBRXWBGDWD>@ VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW QWVFBRXWBGDWD>@ VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW QWVFBRXWBGDWD>@ VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW QWVFBRXWBGDWD>@ QWVFBRXWBGDWD>@ 8QXVHG 8QXVHG URPBDGGU>@URPBDGGU>@URPBGDWD>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ Equator Technologies, Inc. $%/(520$1'5(6(7675$3&211(&7,216 7 9'' QWVFBRXWBGDWD>@ SFLBKRVW QWVFBRXWBGDWD>@ LLVBRXWBGDWD>@ LLVBRXWBGDWD>@ LLVBRXWBGDWD>@ QWVFBRXWBKV\QF QWVFBRXWBYV\QF 727$/ URPBDGGU>@URPBDGGU>@URPBGDWD>@ URPBERRW URPBDGGU>@URPBDGGU>@URPBGDWD>@ 8QXVHG 8QXVHG 8QXVHG 8QXVHG 8QXVHG 0$3&$LVKRVWLQJWKHSULPDU \ 3&,EXV *1' 0$3&$LVQRWKRVWLQJ 9'' )ODVK520LVXVHGIRUERRW *1' 520OHVVERRW URPBRHB URPBZUWB URPBDOH URPBDGGU>@URPBDGGU>@URPBDGGU>@ URPBDGGU>@URPBDGGU>@URPBDGGU>@ 4.13 Power/Ground Pins 7KHIROORZLQJSRZHUDQGJURXQGSLQVDUHSURYLGHG $%/(32:(5*5281'3,16 7 Name # DESCRIPTION 9GG 'LJLWDO&RUH9GG 9GG ,23RZHU6XSSO\9 9VV 'LJLWDO9VV D9GG &OHDQDQDORJ9GG D9VV &OHDQDQDORJ9VV D9GG &OHDQDQDORJ9GG D9GGT &OHDQDQDORJ9GGIRU&RUH3// D9VVT &OHDQDQDORJ9VVIRU&RUH3// D9GG[ &OHDQDQDORJ9GGIRU9LGHR'$& D9VV[ &OHDQDQDORJ9VVIRU9LGHR'$& JGDFBFYJJ &OHDQDQDORJ9VVIRU9LGHR'$& 727$/ Note: There are 4 pins dedicated for grounds and power signals for back bias: Vsbb (vss) : Back bias supply pin for NMOS. Vsbc (Vdd18) : Back bias control pin for NMOS. Vdbb (Vdd18) : Back bias supply pin for PMOS. Vdbc (Vss) : Back bias control pin for PMOS. In regular operation, Vsbb and Vdbc are connected to Vss, Vsbc and Vdbb are connected to Vdd. Equator Technologies, Inc. 21 MAP-CA Data Sheet 4.14 Signal List Summary 7$%/(0$3&$3 ,1/,67 Interface Frequency # Pins Remarks 0$3&$&ORFNV 9DULRXV 2VFLOODWRUVIRUFORFNVLQFOXGLQJE\SDVVFORFNV 3&, 0+] +RVW6\VWHP,QWHUIDFH '5$0 0+] 0HPRU\,QWHUIDFHV6'5$0 )ODVK520 0+] 5HVHW6WUDSV &572XW 0+] ,785%72XW 0+] ,785%7,Q ((3520 &RQILJXUDWLRQLQSXWV $QDORJ9LGHR2XW 'LJLWDO9LGHR2XW 0+] 7ZR9LGHR,QSXW6WUHDPV 7&,,785%7 3DUDOOHO6HULDO7&, 0+] ,6 0+] 'LJLWDO$XGLR,2 ,(& 0+] 'LJLWDO$XGLR,2 ,&''& N+] 3HULSKHUDO&RQWURO -7$* 0+] 0DQXIDFWXULQJ7HVW RU7&,,785%7 6LJQDO3LQV7RWDO 3RZHU*URXQG 'LJLWDO&RUH9GG 6XSSO\FRQWUROEDFNELDV QRFRQQHFWLRQ %DFNELDV 0LVF 1& 7RWDO 22 Equator Technologies, Inc. 4.15 Interface Summary ( ) --- valid during boot-up < > --- valid during reset MAP-CA iis_in_data iis_in_lr iis_in_bclk iis_out_lr iis_out_bclk (rom_oe#)/iis_out_data[2] (rom_wrt#)/iis_out_data[1] (rom_ale)/iis_out_data[0] rom_cs# SDRAM Controller PCI vsync hsync CRT (DRC) I2S gdac_fscale gdac_comp gdac_blue gdac_green gdac_red VIDEO INPUT FLASH ROM (rom_addr[19]/rom_addr[21]/rom_addr[1])/ ntsc_out_hsync (rom_addr[18]/rom_addr[20]/rom_addr[0])/ ntsc_out_vsync IEC958 <reset_strap[7:0]>/ (rom_addr[9:2]/rom_addr[17:10]/rom_data[7:0])/ ntsc_out_data[7:0] VIDEO OUTPUT sdadr[13:0] sddata[63:0] sdcs[3:0]# sdras# sdcas# sdwe# sddqm[7:0] sdclk sdclk1 sdclk2 sdrtnclk iic_sda iic_sck ddc_select I2C/DDC port0 pci_ad[31:0] pci_cbe[3:0] pci_frame# pci_trdy# pci_irdy# pci_stop# pci_par pci_devsel# pci_clk pci_rst# pci_inta# pci_idsel pci_req#[2:0] pci_gnt#[2:0] pci_serr_intb# pci_pme# Processor Clock (PLL) port1 pclk/ntsc_clk27_vcxo coreclk_byp_in sdclk_byp_in pixelclk_byp_in audioclk_byp_in coreclk_out pixelclk_out audioclk_out/iis_out_mclk JTAG Equator Technologies, Inc. tcia_inuse tcia_sync tcia_clk tcia_vdac tcia_err# / ntsc_ina_vsync tcia_enable / ntsc_ina_hsync tcia_data[7:0] / ntsc_ina_data[7:0] ntsc_ina_clk27 tcib_inuse tcib_sync tcib_clk tcib_err# / ntsc_inb_vsync tcib_enable / ntsc_inb_hsync tcib_data[7:0] / ntsc_inb_data[7:0] ntsc_inb_clk27 iec958_in iec958_out tck tms tdi tdo trst 23 MAP-CA Data Sheet 5. External Connection Examples 5.1 ROM URPBGDWD>@ K WFD O DGGU>@ DGGU>@ URPBDOH DGGU>@ K FW DO K FW DO FLASH ROM MAP-CA FLASH ROM INTERFACE K WFD O DGGU>@ URPBDGGU>@ URPBFV URPBZU URPBRH 5.2 SDRAM VGFV>@ VGDGU>@ VGGDWD>@ VGUDV VGFDV VGZH VGGTP>@ VGFON VGUWQFON VGGDWD>@ VGGTP>@ VGFV>@ VGFV>@ 1& . EDQNV [ELW 6*5$0 . EDQNV [ELW 6*5$0 VGFV>@ VGDGU>@ VGGDWD>@ VGUDV VGFDV VGZH VGGTP>@ VGFON VGUWQFON VGGDWD>@ VGGTP>@ VGGTP>@ . EDQNV [ELW 6*5$0 VGGDWD>@ VGGTP>@ 64-bit, 4MB configuration using x32, 8Mb parts 24 VGFV>@ . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 VGFV>@ 1& VGFV>@ 1& . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 . EDQNV [ELW 6'5$0 1& VGGDWD>@ . EDQNV [ELW 6*5$0 VGFV>@ 64-bit, 16MB configuration using x16, 16Mb parts Equator Technologies, Inc. VGFV>@ VGDGU>@ VGGDWD>@ VGUDV VGFDV VGZH VGGTP>@ VGFON VGGDWD>@ 0 EDQNV [ELW 6'5$0 VGGTP>@ 0 EDQNV [ELW 6'5$0 1& VGFDV VGFV>@ VGGTP>@ VGGDWD>@ VGGTP>@ VGGDWD>@ VGGTP>@ 0 EDQNV [ELW 6'5$0 VGGDWD>@ 0 EDQNV [ELW 6'5$0 VGGTP>@ 0 EDQNV [ELW 6'5$0 VGGDWD>@ 0 EDQNV [ELW 6'5$0 VGGTP>@ 0 EDQNV [ELW 6'5$0 VGGDWD>@ VGGTP>@ VGFV>@ VGFV>@ 1& VGUDV VGFDV VGZH [ELW 6'5$0 VGGDWD>@ 0 EDQNV [ELW 6'5$0 EDQNV 0 EDQNV 0 EDQNV [ELW [ELW 6'5$0 6'5$0 VGGTP>@ 0 0 EDQNV [ELW [ELW 6'5$0 6'5$0 VGGDWD>@ 0 EDQNV 0 EDQNV [ELW [ELW 6'5$0 6'5$0 VGGTP>@ 64-bit, 64MB configuration using x16, 64Mb parts VGFV>@ VGFV>@ 0 VGUDV EDQNV VGFDV [ELW [ELW [ELW 6'5$0 6'5$0 6'5$0 VGZH VGFV>@ VGFV>@ 1& VGDGU>@ 0 [ELW 6'5$0 VGUWQFON VGGDWD>@ 0 1& VGGTP>@ VGFV>@ 1& 0 EDQNV [ELW 6'5$0 VGGTP>@ VGFON VGFON VGUWQFON VGUWQFON VGGDWD>@ VGGDWD>@ 0 0 0 0 EDQNV EDQNV EDQNV EDQNV [ELW [ELW [ELW [ELW 6'5$0 6'5$0 6'5$0 6'5$0 VGGTP>@ 0 0 0 EDQNV EDQNV EDQNV EDQNV [ELW [ELW [ELW [ELW 6'5$0 6'5$0 6'5$0 6'5$0 0 EDQNV [ELW 6'5$0 VGGTP>@ VGGDWD>@ 0 0 EDQNV [ELW 6'5$0 VGGTP>@ VGGTP>@ VGGDWD>@ EDQNV EDQNV VGGTP>@ VGGDWD>@ 0 EDQNV VGFV>@ VGGTP>@ VGGDWD>@ VGDGU>@ VGGDWD>@ 1& 0 EDQNV 0 EDQNV [ELW 6'5$0 VGFV>@ VGZH VGFV>@ VGFON 1& 64-bit, 16MB configuration using x8, 16Mb parts VGFV>@ VGFV>@ VGDGU>@ VGGDWD>@ VGUDV VGUWQFON VGGDWD>@ VGFV>@ VGFV>@ VGGDWD>@ 0 0 0 0 EDQNV EDQNV EDQNV EDQNV [ELW [ELW [ELW [ELW 6'5$0 6'5$0 6'5$0 6'5$0 0 EDQNV [ELW 6'5$0 VGGTP>@ VGGTP>@ 64-bit, 128MB configuration using x16, 64Mb parts 64-bit, 64MB configuration using x16, 128Mb parts Equator Technologies, Inc. 25 MAP-CA Data Sheet 5.3 NTSC Decoder Video In Port 0 MAP-CA QWVFBLQDBKV\QF QWVFBLQDBYV\QF NTSC/PAL Decoder QWVFBLQDBGDWD>@ QWVFBLQDBFON SL[HOBFONBRXW ITU-R BT.656 NTSC/PAL DECODER INTERFACE 5.4 NTSC Encoder MAP-CA ITU-R BT.601/656 Output QWVFBRXWBKV\QF QWVFBRXWBYV\QF NTSC/PAL Encoder QWVFBRXWBGDWD>@ QWVFBYF[RBFON 9&;2 0+] ITU-R BT.656 NTSC/PAL ENCODER INTERFACE LHFBRXW LHFBLQ IEC958 INTERFACE 26 Equator Technologies, Inc. IEC958 COUPLER IEC958 Interface MAP-CA 5.5 IEC958 5.6 I2S LLVBLQBEFON LLVBLQBOU LLVBLQBGDWD IIS audio CODEC LLVBRXWBEFON MAP-CA I2S INTERFACE LLVBRXWBOU LLVBGDWD>@ IIS audio DECODE LLVBGDWD>@ IIS audio DECODE LLVBGDWD>@ LLVBRXWBPFON I2S INTERFACE 5.7 I2C/DDC I2C/DDC MAP-CA LLFBVGD ;8 0 LLFGDWDOLQH ''&GDWDOLQH GGFBVHOHFW LLFBVFN ;8 0 LLFFORFNOLQH ''&FORFNOLQH I2C/DDC INTERFACE Equator Technologies, Inc. 27 MAP-CA Data Sheet 5.8 Transport Channel Interface (TCI) MAP-CA VIDEO IN PORT 0 tcia_clk tcia_data tcia_enable tcia_sync tcia_err# SATELLITE/CABLE SOURCE DECODER (QAM-QPSK) & FOWARD ERROR CORRECTION tcia_inuse 9 2& . X) X) U . 9&;2 0+] TRANSPORT CHANNEL INTERFACE 5.9 CRT ANALOG CRT INTERFACE MAP-CA gdac_green Zo= 37.5 Ohms L 75Ohms C Zl=75Ohms C gdac_blue gdac_red vsync Note: gdac_blue and gdac_red has the same connections as those of gdac_green. hsync gdac_comp Vref=1.235V gdac_fscale R=1117Ohms 28 Equator Technologies, Inc. 6. Electrical Specifications 6.1 Absolute Maximum Rating Operation beyond the limits set forth in this table may impair the life of the device. Parameter Min Max Units Voltage on any pin -0.5 Vdd33+0.5 V Storage Temperature -65 150 o Operating Temperature 0 Tj=85 o C C 6.2 Power Supply Specifications Power Supply Nominal Voltage Voltage Tolerance Estimated Max Steady State Current Estimated Max power Vdd 1.8V +/-5% 2.8A 5W Vdd33 3.3V +/-5% .25A 0.8W AVdd 1.8V +/-5% 6mA 10mW AVdd33 3.3V +/-5% 80mA 0.2W Avddx 1.8V +/-5% 5mA 10mW Maximum total power estimate: 6W @300MHz. 6.3 Operating Parameters TABLE 1. PCI Signals Parameter Description Min V IL input low voltage -0.5 VIH input high voltage 0.5Vdd33 Vdd33+0.5 V VOL output low voltage -0.5 0.1Vdd33 V VOH output high voltage 2.4 ILI input leakage current -10 10 uA ILO output leakage current -10 10 uA IOZ tri-state output leakage -10 10 uA CIN input pin capacitance 10 pF CIDSEL idsel pin capacitance 8 pF CCLK pci_clk pin capacitance 12 pF 5 Equator Technologies, Inc. Max 0.3Vcc Unit V V 29 MAP-CA Data Sheet TABLE 2. Non-PCI Signal Parameter Description Min Max Unit VIL input low voltage -0.5 0.2Vdd33 V VIH input high voltage 2.0 Vdd33+0.5 V V OL output low voltage -0.5 0.2Vdd33 V VOH output high voltage 2.4 ILI input leakage current -10 10 uA ILO output leakage current -10 10 uA IOZ tri-state output leakage -10 10 uA CIN input pin capacitance 10 pF CIO input/output pin capacitance 12 pF ICCOP operating current 3(?) A V 6.4 AC Characteristics 6.4.1 SDRAM Interface Timing sdclk,sdclk1,2 tpd toh address, data-out, control sdrtnclk tds tdh data-in SDRAM timing measurement conditions 30 Symbol Description fsdram Min Max Units sdclk frequency 133 MHz tpd propagation delay of address. data, control (sdras_, sdcas_, sdwe_, sddqm) 5 ns 1 toh output hold time of address, data, control (sdras_, sdcas_, sdwe_, sddqm) 1.5 ns 1 tds input data setup time 1 ns 2, 3 tdh input data hold time 2 ns 2, 3 Equator Technologies, Inc. Notes Notes: 20. The center of the rising edges of sdclk1and sdclk2 is used as the reference point. 21. sdrtnclk is used as the reference clock 22. A matching mechanism is provided to compensate for the propagation delay through circuit board traces to and from the external SDRAM devices. To optimize read timing margin, sdrtnclk should be connected to sdclk with a dedicated trace, with an optional lumped RC load attached to the middle, to account for the number of SDRAM devices attached to the clock line. 23. Correct setup and hold times can be guaranteed through internal delay adjustment, controlled by bit [30:24] of the synchronizer/clock control register in MAP-CA memory block. The SdMrckDly and SdMckDly fields control internal delay circuits that affect the timing of signals going to and from the SDRAM components. They should be adjusted so that setup and hold requirements of both the SDRAM's and the MAP-CA are met. 6.4.2 PCI Bus Timing (66MHz) Vth clk V test Vrl tfval output delay V tfall trval output delay tri-state output V trise ton toff PCI Output Timing Measurement Conditions Equator Technologies, Inc. 31 MAP-CA Data Sheet Vth clk Vtest Vtl th tsu Vth input Vmax V test input valid Vtest Vtl PCI Input Timing Measurement Conditions Symbol Description Min Max Units tcycle clock cycle time 15 30 ns thigh clock high time 6 ns tlow clock low time 6 ns clkslew clock slew rate 1.5 tsu input set up time to clk, bussed signals 3 ns tsu(ptp) input set up time to clk, point-to-point signals 5 ns tval clk to signal valid delay, bussed signals 2 6 ns tval(ptp) clk to signal valid delay, point to point signal 2 6 ns ton float to active delay 2 toff active to float delay trst reset active time after power stable 1 ms trst-clk reset active time after clk stable 100 us trst-off reset active to output float delay 4 ns 14 40 TABLE 3. Measurement Condition Parameters 32 Symbol Value Units Vth 0.6Vcc V Vtl 0.2Vcc V Vtest 0.4Vcc V Vtrise 0.285Vcc V Vtfall 0.615Vcc V Vmax 0.4Vcc V input signal slew rate 1.5 V/ns Equator Technologies, Inc. V/ns ns ns 6.4.3 I2C Interface Timing tbuf iic_sda thd_sta tsu_dt thd_dt thd_sta tr thigh tsu_sta tf tsu_sto iic_sck tlow I2C Timing Diagram Standard Mode Symbol Description Fast Mode Min Max Min Max Units 100 0 400 kHz fscl iic_sck clock frequency 0 tbuf bus free time between a stop and start condition 4.7 1.3 us thd_sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 0.6 us tlow low period of the iic_sck clock 4.7 1.3 us thigh high period of the I2CSCL clock 4.0 0.6 us tsu_sta setup time for a repeated start condition 4.7 0.6 us thd_dat data hold time 0 (*1) 0(*1) tsu_dat data setup time 250 100 (*3) tr rise time for iic_sda, iic_sck 1000 20+0.1Cb (*4) 300 ns tf fall time for iic_sda, iic_sck 300 20+0.1Cb (*4) 300 ns tsu_sto setup time for stop condition Cb capacitive load for each bus line 4.0 0.9(*2) ns 0.6 400 us us 400 pf Note: Equator Technologies, Inc. 33 MAP-CA Data Sheet 1. A device must internally provide a hold time of at least 300ns for the iic_sda signal (referred to the Vihmin of the iic_sck signal) in order to bridge the undefined region of the falling edge of iic_sck. 2. The maximum thd_dat has only to be met if the device does not stretch the low period (tlow) of the iic_sck signal. 3. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tsu_dat of 250ns must be met. This will automatically be the case if the device does not stretch the low period of the iic_sck signal, it must output the next data bit to the iic_sda line t_rmax+tsu_dat=1000+250=1250ns (according to the standard-mode I2C-bus specification) before the iic_sck line is released. 4. Cab = total capacitance of one bus line in pF. 6.4.4 ITU-R BT.656 Interfaces Timing ntsc_ina_clk27 tS tH video_ina[9:0] pclk tmaxdelay t hold ntsc_out_data[7:0] ntsc_out_hsync ntsc_out_vsync ITU-R. BT656 Signal Timing Diagram Symbol 34 Description Min Max Units fntsc_in ntsc_ina_clk27p frequency 27 +/- 54+/- MHz tcyc pclk cycle time 18.5 +/- 37 +/- ns tH input hold time for video_ina[7:0], from cross over of rising clock 0 ns tS input setup time video_in[7:0], to the cross over of rising clock 4 ns tmaxdelay maximum delay time thold output hold time 6.5 2 Equator Technologies, Inc. ns ns Notes: The ITU timing diagram and table includes information for the primary video input port. Secondary video input signals have indentical timing relationships and values. Primary video input bus video_ina[9:0] includes the byte-wide data bus (bits 7:0), horizontal sync (bit 8) and vertical sync (bit 9). 6.4.5 Transport Channel Interface Timing tci_clk tS tH video_ina[9:0] tci_sync pclk tClk2Q tci_vdac TCI Signal Diagram Notes: timing diagram and table are relevant to the primary TCI input port. Timing relationships and input setup and hold times are identical for the secondary TCI input port. The tci_vdac output is not present on the secondary output port, however. Inputs video_ina[9:0] include tci_data[7:0] (bits 7:0), tci_enable (bit 8) and tci_err_ (bit 9). TABLE 4. Symbol Description Min Max Units Note 30 MHz 1 ftci_clk_p parallel mode TCI clock frequency tH hold time for video_ina[9:0], tci_sync 1 ns tS setup time for video_ina[9:0], tci_sync 4 ns tClk2Q output hold time 2.5 ns fcore/faudio ratio, VLIW core clock/audio clock freq. >4 3 fcore/fvideo ratio, VLIW core clock/video clock freq. >4 4 2 Note: 1. Additionally, VLIW core clock frequency must be > 1.5 times tci_clk frequency (parallel mode). 2: Additionally, VLIW core clock frequency must be > 6/32 times tci_clk frequency (serial mode) 3: for correct tci audio clock counter operation. Audio clock is audioclk_out, coming on on-chip PLL. 4: for correct tci video clock counters operation. Video clock is pclk, driving ntsc_out, PLLs, etc. Equator Technologies, Inc. 35 MAP-CA Data Sheet 6.4.6 IEC958 Interface Timing audioclk_out tClk2Q iec958_out IEC958 Signal Diagram Symbol tClk2Q Description Min output hold time 2.5 6.4.7 I2S Interface Timing iis_out_bclk tClk2Q iis_out_data[2:0] iis_out_lr I2S Output Timing Signal Diagram 36 Equator Technologies, Inc. Max Units ns iis_in_bclk tSS tHS iis_in_data, iis_in_lr I2S Input Timing Signal Diagram (MAP as bit clock slave) iis_out_bclk tSM tHM iis_in_data I2S Input Timing Signal Diagram (MAP as bit clock master) Symbol Description Min tClk2Q output hold time tSS setup time, MAP as bit clock slave tHS hold time, MAP as bit clock slave tSM setup time, MAP as bit clock master tHM hold time, MAP as bit clock master Max -1 ns 4.5 4.5 Equator Technologies, Inc. ns ns 5 5 Units ns ns 37 MAP-CA Data Sheet 7. Acronyms Acronyms/names used in the data sheet and their expansion/explanation Acronyms used in this document 38 Acronym/name Expansion DataStreamer High speed DMA engine that operates independent from VLIW core DRC Display Refresh Controller DTS Data Transfer Switch - high speed MAP and MAP-CA series internal data bus I-ALU Integer ALU - performs loads, stores, branches, integer arithmetic, and logical operations. IG-ALU Integer, Graphics unit - performs integer arithmetic and (partitioned) multimedia operations. MAP-CA Media Accelerated Processors for Consumer Appliances from Equator Technologies, Inc. MMU Memory Management Unit PLC 128-bit Partitioned Local Constant register PLV 128-bit Partitioned Local Variable register VLx Co-processor on MAP and MAP-CA series that can accelerate variable length encoding and decoding. Equator Technologies, Inc.