Media Accelerated Processor for Consumer Appliances
MAP-CA™ Data Sheet
DS#00008 3/31/2000
Equator Technologies, Inc.
MAP-CA Overview
MAP-CA™ - Media Accelerated Processor for Consumer Appliances- offers a highly integrated single chip solution for
multimedia products such as set-top boxes, digital TVs, video conferencing systems, medical imaging products, digital video
editing equipment and office automation products. The MAP-CA is a member of Equator’s MAP-CA series of VLIW media
processors. A parallelizing C compiler, linker, source level debugger, simulators and libraries are available from Equator.
Reference software modules, including MPEG2 encode and decode, JPEG encode and decode, video post-filtering, audio,
telephony, video teleconferencing codecs are also available from Equator to accelerate customer product development.
Because core media applications are delivered in software on the MAP-CA platform, it is easy to add, remove or enhance
functionality of final products. MAP-CA provides the proven and effective solution for rapidly evolving multimedia applications.
SYSTEM DIAGRAM
VLIW Core
• Highly pipelined Very Long Instruction Word processor that
issues four operations per clock cycle.
- 4 32-bit integer ALUs, 2 64-bit shuffle/partitioned add
units, and 2 128-bit multimedia units
- 128 32-bit general purpose registers which can be treated
as 64 64-bit general purpose registers
- 32 1-bit predicate registers
- 8 special 128-bit registers
• 11+ GOPS sustained 16-bit SIMD operations @300MHz
• 24+ GOPS sustained 8-bit SIMD operations @300MHz
• 30+ GOPS @300MHz for sum-of-absolute difference block
matching.
• 1800 MIPS @ 300 MHz in 32-bit integer arithmetic.
• Bi-endian support.
Memory Hierarchy
• 32 KB 2-way set associative, LRU replacement policy com-
pressed format Instruction Cache.
• 32 KB 4-way set associative, four bank interleaved, true
LRU, write-back Data Cache.
• Separate MMUs for Instruction, Data and DMA with fully
associative 16 entry TLB for each MMU.
Co-processors
• Programmable 16-bit RISC processor with acceleration for
variable length decoding and encoding (VLx) with 4KB
data memory and 4KB instruction memory.
• 4(vertical) x 5(horizontal) / 3 x 5 / 2 x 5 tap Video Filter with
6KB line buffer memory.
• Programmable 64-channel DMA engine (DataStreamerTM)
with 8KB buffer memory.
MAP-CATM
Media Accelerated Processor for Consumer Appliances
Display
Refresh
Vo l t a g e
Regulators
1.8V
3.3V
Core
I/O
Audio
CODECs I2S
RGB
Monitor
PCI
32Bit PCI Bus
@33/66MHz
DEMOD
FEC
NTSC/PAL
Encoder
Decoder
Video
Camera
PLLs 27MHz
VCXO
64bit SDRAM
@150MHz
ITU-R BT.656
Input 1
ITU-R BT.656
Input 0
TCI Input 0
FLASH
ROM I/F
TV
Monitor
TUNER
Controller
I2C/DDC
VLIW
processor
on-chip
memories
Coprocessors
SDRAM
Controller
NTSC/PAL
JTAG
IEC958
Flash ROM
I2C/DDC ITU-R BT.656
Output
TCI Input 1
JTAG
MAP-CA Data Sheet
Equator Technologies, Inc. ii
IO Interfaces
• Video input:
- 2 parallel DVB compliant Transport Channel Interface
or
- 1 parallel DVB compliant Transport Channel Interface &
1 ITU-R BT.601/656 in
or
- 2 ITU-R BT.601/656 in
• ITU-R BT.601/656 video out.
• Display Refresh Controller (DRC) with on-chip color space
conversion, palette table lookup, alpha-blending, and
hardware cursor.
• 110MHz RAMDAC with sync on green for analog RGB
monitor.
• I2S/IEC958 audio interfaces.
• I2C/DDC master/slave interface.
• Glueless high-speed 150MHz SDRAM/SGRAM interface,
support up to 128MB.
• 33MHz / 66MHz 32-bit PCI bus.
• Flash ROM (EEPROM) interface.
• IEEE compliant JTAG interface.
Data Sheet Overview
This data sheet provides the following information:
• An overview of the MAP-CA architecture
• A description of the software development platform
• A description of the hardware development platform
• Packaging information
• Electrical specifications.
For additional information, contact Equator Technologies,
Inc.
info@equator.com
http://www.equator.com
Equator Technologies, Inc.
1300 White Oaks Road
Campbell, CA 95008
Phone: (408) 369-5200
FAX: (408) 371-9106
Copyright © Equator Technologies, Inc. [2000]
All Rights Reserved
Equator makes no warranty for the use of its products,
assumes no responsibility for any errors which may appear in
this document, and makes no commitment to update the
information contained herein. Equator reserves the right to
change or discontinue this product at any time, without notice.
There are no express or implied licenses granted hereunder to
design or fabricate any integrated circuits based on
information in this document.
The following are trademarks of Equator Technologies, Inc.,
and may be used to identify Equator products only: Equator,
MAP, MAP1000, MAP1000A, MAP-CA, MAP Series,
FIRtree, DataStreamer, iMMediaC, Media Intrinsics,
VersaPort and SofTV. Other product and company names
contained herein may be trademarks of their respective
owners.
MAP-CA were jointly developed by Equator Technologies,
Inc. and Hitachi, Ltd.
Equator Technologies, Inc. iii
1. Architecture Overview .........................1
1.1 The VLIW Approach ...............................2
Execution Units ..................................................2
Register Resources .............................................3
1.2 Timers ......................................................3
1.3 Interrupts and Exceptions ........................3
Core Interrupts and Exceptions ........................4
Interrupt Controller ............................................4
1.4 Memory Hierarchy...................................5
Caches ................................................................5
Address Translation............................................5
1.5 Databuses and Controllers .......................5
Data Transfer Switch (DTS) ..............................5
DataStreamerTM ................................................6
I/O Bus ...............................................................6
PCI Bus ..............................................................6
Memory Interface Controller .............................6
1.6 Co-processors...........................................7
VLx.....................................................................7
Video Filter ........................................................7
1.7 I/O Interfaces ...........................................7
Video Interfaces .................................................7
Audio Interfaces .................................................8
Display Refresh Controller.................................8
DACs ..................................................................8
I2C Interface Unit...............................................9
ROM Controller .................................................9
Reset Strap..........................................................9
2. Software Development.......................10
2.1 The C Compiler......................................10
The FIRtreeTM Media Intrinsics .....................10
2.2 Libraries .................................................10
2.3 Assembler ..............................................10
2.4 Linker.....................................................10
2.5 Debugger................................................10
2.6 Simulators ..............................................11
2.7 Boot........................................................11
3. BGA PIN_OUT Assignment...............12
4. Signal Descriptions ............................15
4.1 Processor Clock ..................................... 15
4.2 PCI Bus.................................................. 15
4.3 SDRAM................................................. 16
4.4 Flash ROM ............................................ 17
4.5 Analog CRT........................................... 17
4.6 ITU-R BT.601/656 Output .................... 17
4.7 Video Input Ports................................... 18
Transport Channel Interface (TCI) .................. 18
ITU-R BT.601/656 Input ................................. 19
4.8 I2S ......................................................... 19
4.9 IEC958................................................... 20
4.10 I2C ....................................................... 20
4.11 JTAG.................................................... 20
4.12 ROM and Reset Strap.......................... 20
4.13 Power/Ground Pins.............................. 21
4.14 Signal List Summary ........................... 22
4.15 Interface Summary .............................. 23
5. External Connection Examples .........24
5.1 ROM...................................................... 24
5.2 SDRAM................................................. 24
5.3 NTSC Decoder ...................................... 26
5.4 NTSC Encoder ...................................... 26
5.5 IEC958................................................... 26
5.6 I2S ......................................................... 27
5.7 I2C/DDC ............................................... 27
5.8 Transport Channel Interface (TCI) ........ 28
5.9 CRT........................................................ 28
6. Electrical Specifications ...................29
6.1 Absolute Maximum Rating .................. 29
6.2 Power Supply Specifications................. 29
iv Equator Technologies, Inc.
MAP-CA Data Sheet
6.3 Operating Parameters.............................29
6.4 AC Characteristics .................................30
SDRAM Interface Timing .............................. 30
PCI Bus Timing (66MHz) ............................... 31
I2C Interface Timing ....................................... 33
ITU-R BT.656 Interfaces Timing.................... 34
Transport Channel Interface Timing .............. 35
IEC958 Interface Timing................................. 36
I2S Interface Timing ....................................... 36
7. Acronyms............................................ 38
1 Equator Technologies, Inc.
MAP-CA Data Sheet
1. Architecture Overview
The MAP-CA is a high performance media processor that
combines general purpose RISC processing with high
performance signal and image processing. The MAP-CA
supports programmable video, image, and signal processing
software implementations of compression and decompression
algorithms. The MAP-CA matches the cost/performance
features of dedicated fixed function chips with the added
flexibility to rapidly respond to evolving standards. A block
diagram of the MAP-CA is shown above. The MAP-CA
consists of a VLIW core, programmable co-processors, on-
chip memories and I/O interfaces.
The VLIW core executes four operations in parallel and
supports partitioned SIMD operations for 8/16/32/64-bit data
types. Co-processors on the MAP-CA help accelerate serial
operations like variable length encoding/decoding and video
filtering.
Several audio/video interfaces are supported, including
ITU-R BT.656 input and output, MPEG2 Transport Channel
Interface (TCI), an I2C selectable interface, IEC958 and I2S
digital audio interfaces. Two video inputs (2 BT.656s, or 1
BT.656 & 1 TCI, or 2 TCIs) can be used at the same time. The
DRC unit not only supports RGB computer screen refresh,
but also has hardware support for overlaying a hardware
cursor and graphics/text or a secondary video channel on the
primary video channel.
A glueless SDRAM controller supports access up to
150MHz SDRAM. The maximum memory size supported is
128MB. A 32-bit 33/66MHz PCI bus interface is also
supported. The MAP-CA can be booted up either via PCI bus
or Flash ROM interface.
These I/O functions execute in parallel with the CPU and
eliminate the need for several external ASICs with the
associated cost and bandwidth issues.
There are 3 PLLs (core/SDRAM, pixel, audio) on chip to
generate all the internal clocks from a single 27MHz external
clock input. A software PLL mechanism is provided in
I-ALU
IG-ALU
Data Cache
Instruction
Cache
Register
I-ALU
IG-ALU
File
Register
File
TCI
Display
Refresh
Controller
I
2
C
PLLs
JTAG
Glueless
SDRAM
Controller
ITU-R
BT.656
OUT
ITU-R
BT.656
IN 0
32-bit 66MHz
Block Diagram
PCI-A
co-processor
memory
DataStreamer
VLIW core
I
2
S
IEC958
IN 0
ROM I/F
ITU-R
BT.656
IN 1
TCI
IN 1
JTAG
SDRAM
Flash
ROM
co-processor
memory
64bit
Video Filter 16-bit RISC
processor
Video In 0 Video In 1
Video Out
27 MHz
Analog RGB
Audio I/O
I
2
C
2 Equator Technologies, Inc.
MAP-CA Data Sheet
conjunction with the TCI to track the reference clock (PCR)
embedded in the transport stream
An IEEE compliant JTAG interface is provided for
manufacturing test.
1.1 The VLIW Approach
Real-time handling of multi-media data stresses processor
performance. There are three basic ways to increase a
processor’s performance: decrease the cycle time, decrease the
number of cycles required to execute an instruction, and
execute more instructions per cycle. The first two are
becoming increasingly difficult to improve beyond process
scheduling, while the last is still underexploited. Executing
more instructions per cycle exploits the natural parallelism
available in most software. Very Long Instruction Word
(VLIW) processors explictly describe this parallelism by
packing multiple operations into a single instruction word,
which is then executed as a unit.
VLIW differs from superscalar architectures in that the
grouping and scheduling of instructions for execution is done
at compile time, rather than execution time. The compiler
searches for eligible operations, checks for dependencies and
control resource conflicts, and packages them into VLIW
instruction words. The compiler can explore beyond the
limited search window seen in superscalar architectures, and
cross natural boundaries such as branches to search for
opportunities for parallelism. The Equator compiler uses a
technique known as Trace Scheduling to search a whole
routine for eligible operations.
By moving the difficult task of finding parallelism into
software, VLIW techniques dramatically simplify the CPU,
design by reducing gate count and freeing valuable die area
for other performance enhancements or lower costs. While
VLIW is primarily designed to exploit parallelism, its
simplification of the processor architecture allows for reduced
cycle times as well.
1.1.1 Execution Units
The basic operation format for the MAP-CA consists of
three-operand register-to-register operations. Native data
types include 1-bit logical values, 8, 16, 32, and 64-bit
integers, and 32-bit addresses. The Media Intrinsic operations
include partitioned operations over these data types. Load and
store operations can perform 1, 2, 4, and 8-byte accesses, with
support for both little and big-endian byte orderings. Dynamic
address translation and virtual memory protection is fully
supported. The 1-bit logical values are also used to support
predicated execution, which substantially enhances available
parallelism by allowing partial speculation and eliminating
branches. Each MAP-CA instruction contains four operations.
The MAP-CA has four functional units: two I-ALUs, and
two IG-ALUs. Each I-ALU contains a Load-Store unit, an
integer ALU, and a Branch unit. Each IG-ALU contains an
Integer/Graphics unit and a Multimedia Operation unit.
There are 128 32-bit registers usable in pairs as 64-bit
registers, 32 1-bit predicate registers, and eight special 128-bit
registers. The 128-bit (PLC/PLV) registers are used for FIR
filter, SAD, FFT, ADD, DCT, and other specialized
partitioned integer operations. The large register files help
minimize unnecessary instruction dependencies caused by
logically distinct register reuses.
The MAP-CA operations are primarily 3-operand RISC
operations. As in a typical RISC architecture, load and store
operations are the only means of referencing memory. The I-
ALU and IG-ALU support different operations, but many
integer and logical operations are implemented in both units.
This overlap allows the compiler to schedule more operations
in parallel and make more efficient use of all the functional
units.
A new operation of any type can be issued on every cycle.
1.1.1.1 I-ALU
The I-ALU performs the following operations:
• 32-bit integer arithmetic operations including compare and
more.
• Logical and bitwise logical operations. The result of a logi-
cal operation can be sent to a general register or a predicate
register.
• Address calculations for indexed addressing
• Memory reference
• Branching
• System control operations
1.1.1.2 IG-ALU
The IG-ALU performs the following operations:
• 32-bit integer arithmetic operations (same as the I-ALU)
• Logical and bitwise logical operations (same as the I-ALU)
• 64-bit integer arithmetic operations.
• Shift/Extract/Merge operations
• 64-bit SIMD operations (with 8-bit, 16-bit, and 32-bit parti-
tions) including selection, comparison, selecting maxi-
mums and minimums, addition, multiply-add, complex
multiplication, inner-product, and sum-of-absolute differ-
ence.
• 128-bit partitioned (with 8-bit, 16-bit, and 32-bit partitions)
SIMD operations including inner-product with new parti-
tion shift-in for efficient FIR operation and sum-of-abso-
Equator Technologies, Inc. 3
lute difference with new partition shift-in for efficient
block matching operation.
1.1.1.3 Simple Interlocks
Certain operations (such as SIMD operations) require more
than one cycle to complete. No hardware interlocks are
needed to prevent issue of an operation which attempts to read
a result not yet completed. The compiler is responsible for
correct scheduling, not hardware. Register scoreboarding is
supported for outstanding loads.
1.1.1.4 Extensive Predication
Nearly all operations can have their effect controlled by the
value of a selected (1-bit) predicate register. A predicate
register is tested to determine whether or not the operation
should be performed. This allows the compiler to aggressively
convert control flow into data flow, enabling a substantially
higher degree of instruction-level parallelism. This also
greatly helps to reduce any penalties for branching, without
the cost and complexity of hardware branch prediction.
1.1.2 Register Resources
There are several types of registers on the MAP-CA. These
include system registers, breakpoint registers, general purpose
registers, predicate registers, and special purpose 128-bit
registers.
1.1.2.1 Global Registers
Global registers on the MAP-CA consist of system
registers and implementation-dependent I/O registers (PIO
registers). Dedicated operations manipulate the system
registers, while conventional load and store operations
manipulate the I/O registers. All system registers are 32-bit
registers.
1.1.2.2 Breakpoint Registers
MAP-CA has two sets of breakpoint registers, instruction-
breakpoint, and data-breakpoint registers. These registers
provide hardware breakpoint capability for various debugging
tools. Instruction-breakpoint registers cause an exception
when an operation in the specified address is about to be
executed. Similarly, the data-breakpoint registers cause an
exception when the data at the specified address is about to be
accessed. In both cases a mask can be used to specify a range
of addresses.
By registering an exception handling routine associated
with either of these exceptions, a software developer can
control what happens when a hardware breakpoint occurs.
For example, the exception handling routine may be used to
signal an external application such as a source-level debugger
that a breakpoint has occurred.
1.1.2.3 General Registers
There are 128 32-bit registers that can be treated as pairs
of 64-bit general registers using odd-even pairs of the 32-bit
registers. When reading or writing 64-bit registers an even-
numbered register must be specified. For example, the register
pair [R5, R4] is referenced as R4 in 64-bit access.
1.1.2.4 Predicate Registers
There are 32 1-bit predicate registers. Predicate registers
are used in predicated operations, logical operations, and
branches. They provide a destination for operations with a
judged condition.
1.1.2.5 PLC/PLV 128-bit registers
The IG-ALU has four special 128-bit registers - two pairs
of Partitioned Local Constant (PLC) and Partitioned Local
Variable (PLV). These registers are used for powerful SIMD
DSP partitioned operations. The registers can be configured
as sixteen 8-bit operation partitions, eight 16-bit operation
partitions, or four 32-bit operation partitions. For numerous
digital signal processing and compression algorithms, this
allows MAP-CA to match the cost/performance of fixed-
function chips without the loss of reprogrammability.
1.2 Timers
The MAP-CA has two independent programmable interval
timers plus a free-running counter. Each interval timer has a
32-bit counter register and period register. The counter is
incremented once per cycle. When the counter reaches the
period value, the counter is reset, a bit is set in the system
Event Seen Register (ESR), and a maskable interrupt is
asserted. The free-running counter counts up once per cycle as
well. When it overflows to zero a bit is set in ESR and a
maskable interrupt is asserted.
The Transport Channel Interface also has programmable
timer with a resolution of 27MHz that can be used to generate
periodic interrupts.
1.3 Interrupts and Exceptions
The MAP-CA has a flexible interrupt structure. Interrupts
and exceptions internal to the core are reflected directly in the
system registers. PCI, DataStreamer, and other non-core
interrupts are gathered by the on-chip Interrupt Collector.
Software generated interrupts are provided for
multiprocessing or interprocess communication support.
Each interrupt can be individually routed to one of four core
interrupts or to one of two PCI interrupt signals.
Routing and masking of interrupts is programmable. All
interrupts are at a single priority level, allowing prioritization
to be managed by software. All interrupts and processor
exceptions can be masked or unmasked at the core by clearing
or setting the EXCP bit of the Processor Status Word (PSW)
system register. In addition, all of the interrupts controlled by
the Interrupt Collector can be masked based on their routing
4 Equator Technologies, Inc.
MAP-CA Data Sheet
destination, using the enable bits in the IntrControl register.
1.3.1 Core Interrupts and Exceptions
The Event Seen system register (ESR) has bits for the
following events:
Other system registers (CESR0 and CESR1) have bits for
the events described in the following tables:
When an event occurs, the appropriate bit is set in the ESR
or one of the CESR registers. If the event is not masked (or
not maskable), the address for a handler will be fetched from
one of the Event Vector system registers. The core also has the
event vector system registers as shown in the Event System
Registers table.
The general event handler is called for any event or
exception not covered by another vector.
When a handler is called due to an exception or interrupt,
the EXCP bit of the PSW is cleared, the privilege level (PL bit
of the PSW) is set to kernel, and the exception PCs are stored
in a series of three Event PC system registers (EPCR0,
EPCR1, and EPCR2). The prior EXCP and PL settings are
saved in PEXCP and PPL, also in the PSW. The handler is
responsible for saving and restoring any state it modifies.
Eight Event Save system registers (ESV0 through ESV7) are
available to each I-ALU and IG-ALU pair to assist in saving
state.
The handler returns control to the interrupted code by
issuing an RFE instruction. This instruction restores the
PSW’s EXCP and PL settings from PEXCP and PPL, and then
branches to the address(es) contained in EPCR0 through
EPCR2.
1.3.2 Interrupt Controller
The MAP-CA interrupt controller supports multiple
maskable interrupts. These non-core interrupt sources include
on-chip devices such as TCI, DRC or the DataStreamer, and
PCI interrupts from external devices or hosts. Software
generated shoulder-tap interupts are provided for
muliprocessing or interprocess communication support.
MAP-CA interrupts can be examined and enabled in the
PIO registers of the ROMCON control block. Interrupt status
is organized into two 32-bit registers (InterStatus0 and
InterStatus1). Bit assignments for these registers are shown in
the following table.
Routing and masking of interrupts is programmable. Each
interrupt can be individually routed to one of four core
interrupts or to one of two PCI interrupt signals. All interrupts
can be masked based on their routing destination, using the
IntrMasterEnableCore, IntrMasterEnableAA, and
IntrMasterEnableAB bits of the IntrControlRegister.
The interrupt controller can be programmed through the
ROMCON PIO registers, either from the core or from another
System Events
Name Event Maskable?
IO0..IO3
I/O interrupts (from interrupt
controller) Yes
SINT0..SINT1 Software interrupts Yes
FCNT Free running counter overflow Yes
INTV0..INTV1 Interval timers Yes
ILPC Illegal program counter No
IBPT Instruction address break Yes
BPOP Breakpoint operation No
SYS System call (trap instruction) No
ITLBAA ITLB application access No
ITLBR ITLB reference No
ITLBM ITLB miss No
Operation Events
Name Event Maskable?
IEXZ Integer divide by zero Yes
ILLO Illegal operation No
PLV Privilege violation No
DBPT Data address break Yes
DALN Data alignment error No
DTLBKW DTLB kernel write No
DTLBAW DTLB application write No
DTLBAA DTLB application access No
DTLBR DTLB reference No
DTLBM DTLB miss No
Event Vector System Registers
Register Event
EVDTLBVR DTLB miss
EVITLBR ITLB miss
EVSYSR system call (trap instruction)
EVINTVR Interval timer interrupt
EVIO0R I/O interrupt 0
EVIO1R I/O interrupt 1
EVIO2R I/O interrupt 2
EVIO3R I/O interrupt 3
EVGENR General event
Equator Technologies, Inc. 5
host processor via the PCI interface.
1.4 Memory Hierarchy
The MAP-CA supports several on-chip memories and
access to SDRAM and other memories via the PCI bus. The
VLIW is equipped with a 32KB instruction cache and 32KB
data cache used for caching instructions and data from
SDRAM. In addition to supporting I-ALU ports, the data
cache supports a port to the DTS, supporting data in the data
cache available to the DataStreamer.
4KB instruction memory and 4KB data memory are used
by the VLx co-processor. The Video Filter uses 6KB line
buffer memory. These memories (total 14KB) are also
accessible by the VLIW core through uncached load/store
operations. In addition, these memories are also available to
the DataStreamer and for external use via PCI. The line buffer
memory is used to store the content of flash ROM at a system
boot up.
1.4.1 Caches
MAP-CA has a 32KB instruction cache (I-cache) and a
separate, multi-bank 32KB data cache (D-cache). Both caches
are physically addressed, so that problems of aliasing and
context switching do not arise. For fast address translation, the
cache index is virtual but the tags are physical.
The I-cache holds instructions in a compressed form. It is
organized as a 2-way set associative cache with a LRU
replacement algorithm.
The D-cache is a 32KB, 4-way set-associative (with true
LRU replacement), write-back cache. The data cache
supports four simultaneous 64-bit data accesses per cycle. The
cache is non-blocking; up to 8 outstanding misses to different
cache lines and up to 64 outstanding misses overall are
allowed.
1.4.2 Address Translation
The MAP-CA provides memory management support in
the form of separate TLBs for the instruction stream, each I-
ALU data access, and the DataStreamer. The four TLBs can
be programmed independently.
The DTS-ID is part of the virtual address and can be used
to direct accesses when the TLBs are disabled.
Each TLB has sixteen fully-associative entries. Each entry
contains a Virtual Page Number (VPN), an 8-bit Address
Space Identifier (ASID), access protection bits, and page size
information. Each entry can map a page of any valid size,
where the valid sizes are 16KB, 64KB, 256KB, 1MB, 4MB,
16MB, 64MB, 256MB,and 1GB.
When a TLB miss occurs, an exception is generated. The
exception handler can modify a TLB entry and retry the failed
operation. Separate exception handlers can be installed for
data, instruction, and DataStreamer TLB misses.
1.5 Databuses and Controllers
The various buses and controllers on the MAP-CA are
described in the following sections.
1.5.1 Data Transfer Switch (DTS)
The DTS is a split-transaction bus. The DTS contains the
data and address buses, a high speed bridging system and bus
arbiter. The bridge, arbiter and bus arrangement is a very high-
speed communication solution that allows multiple media
IntrStatus0:
Bit Name Interrupt
0 unused
1 IrqAlwaysOne debug interrupt, always asserted
2IrqIIC I
2C
3 IrqTCI0 primary TCI
4 IrqDRC display refresh controller
5 IrqNTSCIn0 primary ITU.R-BT601/656 in
6 unused
7 IrqNTSCIn1 secondary ITU.R-BT601/656 in
8 IrqTCI1 secondary TCI
9 IrqPCIAA PCI interrupt pin A
10 IrqPCIAB PCI interrupt pin B
11 IrqNTSCOut ITU.R-BT601/656 out
12
13
14 IrqIEC958 IEC958 audio
15 IrqIIS IIS audio
16 unused
17..31 unused
IntrStatus1:
Bit Name Interrupt
0 IrqPCIAPME
PCIA power management event
(pme pin)
1 IrqDS0 DataStreamer interrupt 0
2 IrqDS1 DataStreamer interrupt 1
3 IrqDSTLB DataStreamer TLB miss
4 IrqDSBufOvrFlow DataStreamer I/O input overflow
15-11 Unused
12..31 IrqSoftWare Software-controlled interrupts
6 Equator Technologies, Inc.
MAP-CA Data Sheet
applications to be executed concurrently.
The arbiter can handle asynchronous requestors using
priority based scheduling.
1.5.2 DataStreamer
TM
The DataStreamer is a high performance, programmable
DMA engine that provides buffered data transfer between
different MAP-CA memory subsystems or between memories
and I/O devices. The DataStreamer initiates transfers to and
from memory, whereas the I/O Devices initiate I/O transfers
between themselves and the DataStreamer. These transfers are
done under software control without consuming cycles from
other on-chip processing units. This feature is useful for the
following classes of transfers:
• memory-to-memory - perform block transfers;
• memory-to-data cache - preload data into the cache;
• memory-to-I/O and I/O-to-memory - perform I/O transfers;
•constant-to-memory - fill a memory region with 0 or 1 bits.
The DataStreamer is connected to the DTS through a
system of queues. Queueing requests and transfers allows
multiple active channels performing reads and writes to be
serviced in a highly pipelined fashion. This maximizes
resource utilization and overall data throughput.
The DataStreamer is also connected to the I/O bus through
a separate I/O Controller, allowing on-chip devices to stream
data directly to and from DataStreamer buffers. For example,
a digitized NTSC input stream can be transfered directly into
a DataStreamer buffer, and a channel started to copy the data
into a series of frame structures in memory for processing.
Except for setting up and starting the NTSC input device and
the DataStreamer buffer and channel, no core involvement is
required to perform this continuous transfer.
1.5.2.1 Features of the DataStreamer
• 64 independent programmable channels for transfers
between memory and the DataStreamer’s internal buffer.
• 8KB internal memory that can be partitioned into as many
as 64 variable-sized buffers. Each buffer is simultaneously
the sink for an input I/O or memory channel and the source
for an output I/O or memory channel.
• Channels have 4 priority levels. The DataStreamer schedules
channels based on buffer fullness and priority. A burst of
transfers (either writes or read requests) is generated for
each channel when scheduled.
• Channel programs are composed of one or more descriptors.
Each descriptor names a source or destination address, a
data width, a skip value, a repetition count, a next
descriptor address, and a number of control bits.
• Descriptor lists allow transfers of arbitrary or infinite
length to be specified. Regular and irregular patterns of
non-contiguous transfers are easy to specify.
• Memories that can be accessed include SDRAM, on-chip
memories, and PCI bus accessible memories. Cache policy
can be specified for SDRAM transfers
• Three per-channel interrupts are provided. Two are asserted
by control bits on a descriptor, and the third is a TLB miss
interrupt.
• One per-buffer overflow interrupt is provided. It is used to
detect overflow on I/O input transfers.
• Interrupts are routed to the Interrupt Controller where they
can be masked and/or routed to the VLIW core or to PCI
interrupts.
1.5.3 I/O Bus
All on-chip peripheral devices are connected via the
internal I/O Bus (IOB). This is a 32-bit internal bus running at
half of the VLIW core frequency. The IOB connects to the
DTS through the DataStreamer. The IOB can handle
isochronous requests.
1.5.4 PCI Bus
The PCI unit implements a 32-bit PCI interface with speed
up to 66MHz. The PCI interface is a single function device
with two BARs. Certain fields in the configuration registers
may be initialized on power-up through ROM control. As a
PCI target, the PCI interface allows access to the MAP-CA
SDRAM (coherently or non-coherently with respect to the
Data-Cache). It also allows access to several programmer
visible control registers, PIO space and SDRAM. As a PCI
master, the PCI interface allows the VLIW core,
DataStreamer and co-processors to initiate PCI bus requests.
The PCI unit can initiate memory, I/O and configuration
commands on the PCI bus.
The MAP-CA can act as a host and provide three pairs of
request/grant lines for other devices on a PCI bus. This
enables a multi-processor configuration to connect upto 4
MAP-CAs together on a PCI bus without a bridge.
The PCI interface implements two separate interrupt lines.
If the MAP-CA is not the host, any internal interrupt can be
routed to any of these PC interrupts. If the MAP-CA is the
host, the PCI interrupts are sampled by the MAP-CA and can
be routed to the MAP-CA VLIW core.
The MAP-CA is a 3.3V only I/O device. If the MAP-CA
is used in a system with a 5V PCI bus architecture, then a 5V
to 3.3V level translator is required.
The PCI bus interface can support any PCI Rev2.2
compliant device.
1.5.5 Memory Interface Controller
The Memory Controller Unit allows customers to easily
build high performance, external memory up to 128MB using
SDRAM/SGRAM without any external glue logic. Local
Equator Technologies, Inc. 7
memory supports externally initiated PCI accesses through
the Address Translation Unit within the PCI module.
The Memory Controller Unit also includes hardware which
queues, prioritizes, and transfers data from memory-to-
memory or memory-to-cache asynchronously to the initiating
software.
The PLL on chip generates the clock for the memory
controller and provides clock synchronization between the
MAP-CA and external SDRAM. This provides support for
various combinations of CPU core and memory speeds.
1.6 Co-processors
Co-processor on the MAP-CA help off-load “serial” tasks
from the VLIW core or accelerate special purpose processing
for video operations. The co-processors operate in parallel
with the VLIW core resulting in improved video processing.
1.6.1 VLx
The Variable Length Encoder/Decoder (VLx) is a 16-bit
RISC co-processor with 32 16-bit registers that offloads the
VLIW CPU core from bit sequential tasks of Variable Length
Encoding and Variable Length Decoding (VLE/VLD), and
accelerates applications such as JPEG, MPEG, H.263, JBIG,
DV, etc. It includes special purpose hardware for bitstream
processing, hardware accelerated MPEG2 table lookup and
general purpose variable length decoding.
1.6.2 Video Filter
A polyphase (8 phase) 2D Video Filter takes 4:2:0 or 4:2:2
YUV stream as input and scales either up or down as
required. 4 (vertical) x 5 (horizontal) filters support up to 768
horizontal pixels, 3 x 5 up to 1024 horizontal pixels, and 2 x 5
up to 1536 horizontal pixels. The Video Filter pumps out
scaled 4:4:4 YUV data to the SDRAM or the DRC through
the video bus. Its features are described below.
• Supports 8-bit coefficients.
• Supports both interspersed and co-sited pixel positioning.
• Supports vertical 4-tap polyphase (8 phases) filters for Luma
and Chroma.
• Supports horizontal 5-tap polyphase (8 phases) filters for
Luma and Chroma.
• Can scale up to a maximum resolution of 2047x2047
(depends upon memory bandwidth available for the video
scaling operation).
• Can scale up from a minimum resolution of 17x4.
• The maximum scale down ratio is 1:7.
1.7 I/O Interfaces
1.7.1 Video Interfaces
MAP-CA provides two video input ports. Each port
supports either TCI input or ITU-R.BT 601/656 input. Also,
MAP-CA supports a ITU-R.BT 601/656 complaint output.
1.7.1.1 Transport Channel Interfaces
The video input unit implements two DVB compliant
transport channel interfaces which receive demodulated
channel data in transport layer format. The Transport Channel
Interface (TCI) accepts MPEG-2 system transport packets in
either in byte parallel or bit serial form (default). Data rates up
to 80Mbps (serial) or 30MBps (byte-wide parallel) are
supported. By default, serial data is input on tci_data[0] and
parallel data is input on tci_data[7:0] with bit 7 the most
significant. These orientations can be reversed by PIO
programming.
The TCI synchronizes packet data received in broadcast
applications such as satellite or cable. The TCI can detect
inline sync bytes, which are the first byte of every transport
header. Alternatively, the TCI can utilize the external tci_sync
signal. Once byte-sync has been detected, the TCI moves
byte-aligned data into MAP-CA memory using the
DataStreamer.
The number of bytes in each packet is programmable. At
the end of every packet, the TCI appends an eight-byte
postscript that includes time stamps from the local clock
counter. This information is used for implementing a software
loop filter for controlling an external VCXO. The clock
counter within the TCI can also be used as a programmable
timer with a resolution of 27MHz to generate periodic
interrupts.
The two Transport Channel Interface peripherals (primary
and secondary) are identical, except that the secondary TCI
cannot control the external VCX0.
I/O Bus
VLx
16-bit CPU
64-bit
registers
16-bit
32-bit
instruction
VLx co-processor
memory
(4KB)
data
memory
(4KB)
Bitstream
processor
8 Equator Technologies, Inc.
MAP-CA Data Sheet
1.7.1.2 ITU-R.BT 601/656 Input Interface
This interface provides direct connection to a ITU-R
BT.656 format NTSC/PAL video input decoder. The decoder
is controlled using the I2C Serial Bus. The interface can be
used as an additional input for transferring data at 54 MB/s.
1.7.1.3 ITU-R.BT 601/605 Output Interface
A glueless interface to a ITU-R BT.656 NTSC video
encoder is provided enabling the MAP-CA to directly
generate high-quality NTSC or PAL video-output signals.
This interface supports ITU-R BT.601/656 8-bit 525 and 625
line resolutions with either separate H,V sync (601) or inline
sync (656). Advanced video post-filtering on the MAP-CA
processor via software can produce flicker free output when
converting interlace-to-progressive output. The external
NTSC/PAL encoder is controlled using the I2C Serial Bus.
The 656 output can also be used as an additional output for
transferring data at 54MB/s . Various product configurations
use this I/O for additional bandwidth beyond the PCI buses in
multiprocessor system. The clock of this interface can be
sourced from either pclk or pixelclk_bpy)in through PIO
programming.
1.7.2 Audio Interfaces
1.7.2.1 IEC958 Audio Interface
This interface supports several audio standards:
• Sony Phillips Digital Interface (SPDIF)
• Audio Engineering Society/European Broadcast Union
(AES/EBU) interface
• TOSLINK interface
• The TOSLINK interface requires external IR devices.
• The IEC958 protocol convention calls for each multi-bit
field in a sound sample to be shifted in or out with the least
significant bit first (little-Endian). The MAP-CA interface
corrects this so that 16-bit samples are “MSB justified”
within a 20-bit software sample.
The MAP-CA IEC958 interface also automatically
calculates even parity on each sub-frame before inserting it
into the bit stream.
1.7.2.2 I
2
S Interface
The I2S interface drives high quality (better than 95 dB
SNR) audio D/A converters for home theater. The MAP-CA
interface meets the requirements of the standard serial data
protocol, and provides connection up to three stereo DAC and
one ADC. It supports 48KHz, 44.1KHz and 32KHz audio
sample rates. Timing is software configurable to either 24, 20,
18 or 16-bit mode. Data sourced from MAP-CA is software
configurable to 24 or 16-bit format with either straight or
reverse order. MAP-CA I2S supports both master and slave
mode interface, with the choice of using either external or
internally generated lr clock and bit clock to the input (slave) .
1.7.3 Display Refresh Controller
Sophisticated video blending, 2D graphics with alpha
blending, PIP, and hardware cursor overlays for EPGs
(Electronic Program Guides) and navigation services have
been designed into the display refresh controller. Color space
conversion, Gamma correction, and choice of YCbCr or RGB
output format is supported.
1.7.4 DACs
The MAP-CA RGB DACs (Digital-To-Analog Converter)
are part of the Display Refresh Controller block. The DACs
are 8-bits with pixel clock rate up to 110 MHz. MAP-CA
generates RS-343A compatible monitor signals into doubly
terminated 75Ohm load and is capable of driving standard
SVGA monitors.
The full scale output level is determined by an external
reference voltage Vref at 1.235V and an external resistor
Rnominal=1117 Ohms. The full scale level can be adjusted by
adjusting the resistor value.
The DACs output the three primary analog color signals:
red video, green video and blue video, with the video sync
information superimposed on the green video output. Note:
internally, there are actually 4 DACs - the R, G, B DACs and
Data
Streamer
Memory
Controller
CRTC
Display
List
state controls
to all sections
Cursor
Generator
Alpha
channel
Graphic
Format
Conversion
Video #2 Fmt Conversion
Up/Down Scaling
MUX
MUX MUX
Vide o
#1 Rcv
IOBus
Key
Alpha Pipe Insert
Video
Filter
VS
IMBus PMBus
MUX
Pipeline
MUX
Color Space
Conversion
RGB<-->YUV
By
Pass
MUX
Pipeline
MUX
Color Space
Conversion
RGB<-->YUV
By
Pass
Cursor Insert | Alpha Blender
Signature analyzer
fast bus
slow bus
horizontal blender
chroma subsampler
ITU-R 656
formatter
NTSC/PAL Encoder
ITU-R 656 output
Byte-wide parallel
NTSC Output
(off chip)
Video Bus
Display Refresh Controller
mem
Equator Technologies, Inc. 9
a SYNC DAC. The SYNC ouput is superimposed on the green
DAC output).
1.7.5 I
2
C Interface Unit
The Inter-Integrated-Circuit bus (I2C) was originally
developed to facilitate communications and control among
integrated circuits in consumer electronics. Equator utilizes
this standard primarily to facilitate communications between
the MAP-CA and external devices. Comprising a two-line
serial interface, I2C provides the physical layer (signaling)
allowing the MAP-CA to serve as a master or slave device
residing on the I2C bus. It requires no additional hardware for
a MAP-CA system to relay status and control information to
external devices.
The I2C interface unit has an additional output signal,
iic_select (part of the I/O Switchable Pin Selector) that allows
MAP-CA software to control an external analog
multiplexer/level converter that can multiplex between a
regular I2C bus and any other external bus like DDC for a
monitor interface. This signal can also be used as a general
purpose output
1.7.6 ROM Controller
The ROM Controller (ROMCON) unit performs four
distinct functions:
• Chip Configuration and ROM Boot Sequencer: a state
machine for reading chip configuration and boot code at
system startup;
• Flash ROM Interface: controls the actual reading and and
writing of an off-chip Flash ROM device;
• Interrupt Controller/Collector: provides a means for
enabling, setting, and clearing hardware and software
interrupts to the VLIW core and PCI bus controller; and
• PLL I/O: provides direct PIO access to the programmable
registers related to the various on-chip PLLs.
The purpose of the Configuration/Boot Sequencer is to
control the boot up process of the chip. During reset, the
resistor straps connected to the ntsc_out_data[7:0] pins are
examined to determine how MAP-CA will configure itself
and boot. If the resistor straps indicate to boot from ROM, the
BootSequencer directs the Flash ROM Interface Controller to
transfer bytes from the external ROM device to the MAP-CA
configuration registers and to the PCI configuration registers.
The 6KB line buffer memory of the Video Filter is then used
to store the bootstrap program for system boot up. ROMCON
copies the next 4KB from ROM into the Video Filter memory
(VfMem) through an 8-bit configuration bus. After the boot
code has been loaded, ROMCON unstalls the VLIW CPU
which in turn begins to execute the boot code out of VfMem.
The ROMCON unit operates at 27MHz during the
configuration loading, since the core PLL cannot be
programmed to be taken out of bypass mode until after the
VLIW core has been unstalled.
Alternatively, for booting via the PCI interface, ROMCON
plays a mostly passive role. In this case, an external host loads
the VfMem with boot code and initiates boot of the VLIW
core via a PIO write to unstall the VLIW CPU.
ROMCON also runs power-on diagnostics during the boot,
and may be paused at various points for status testing.
ROMCON requires minimal chip resources so that standard
power-on diagnostics can run without having to bring up all
portions of the chip, so that the chip can be tested in more
maneable stages. The power-on self-tests generate a single
success or failure message on the I2C bus.
The three on-chip PLLs for the core/SDRAM, pixel, and
audio clocks are programmed indirectly via PIO registers
within the ROMCON unit.
1.7.7 Reset Strap
During reset the eight ntsc_out_data pads are used as
inputs to read pre-boot configuration settings. These are
settings that must be known before the actual boot process
begins, namely, whether the system should boot from ROM,
and whether PCI should serve as host for its bus. There are
also four straps available whose meaning can be defined in
software.
Each strap pad is pulled high (to IOVDD) or low (to GND)
through a 20 K-ohm resister. The pads are sampled into
flipflops until reset is deasserted and then saved in the
software-visible StrapBits field of PIO register
ConfigBusControl. For more information see Section 4.12
ROM and Reset Strap on page 20.
10 Equator Technologies, Inc.
MAP-CA Data Sheet
2. Software Development
The Equator iMMediaTools software developer kit
includes
• Highly-optimized, parallelizing C-language compiler
• FIRtreeTM Media Intrinsic C-language extensions
• Assembler
• Linker
• Source-level debugger
• Assembly-level debugger
• Profiling CPU simulator
• Virtual-machine, cycle-accurate simulator
• Assorted libraries
The Equator iMMediaCTM Compiler supports
development in a host environment that differs from the target
environment. The virtual-machine simulators allows testing
and debugging on your host system. The supported host
development environments are Microsoft Windows NT and
Linux.
2.1 The C Compiler
The MAP-CA development system includes the
iMMediaC Compiler with FIRtreeTM Media Intrinsic. The
FIRtreeTM extensions are proprietary SIMD-style high-speed
media processing extensions.
The C Compiler uses aggressive optimization and global
scheduling technology (including Trace Scheduling) to
deliver full hardware performance without using laborious
assembly language programming. It allows programmers to
focus efforts on algorithm optimization versus assembly
scheduling, resource allocation and debug.
Unlike existing DSPs or dedicated-function devices which
have heretofore been used to meet media processing
requirements, a programmer will program the MAP-CA in a
high-level language (C). Benefits of programming in C
include:
• Reduced development costs
• Reduced time to market
• Lower system costs
• Reduced maintenance time
• Software-based upgrades
The MAP-CA development environment includes a C
compiler with FIRtreeTM Media Intrinsic operation
extensions. The FIRtreeTM extensions are proprietary SIMD-
style high-speed media processing extensions.
The Equator compiler uses complex inline expansion,
assertions, and loop unrolling with trace frequency estimation
algorithms to maximize C code efficiency. The optimizations
include:
• Uncover instruction-level parallelism
• Manage registers, pipelines and functional units
• Generate instruction operation schedules that exploit paral-
lelism
• Support extensive global optimization, analysis and schedul-
ing
• Provide local scheduling and optimization
• Support media-oriented machine facilities
• Manages all timing dependencies to maximize scheduling
efficiency
The C Compiler shell program lets you compile, examine,
test, profile, assemble, and link source programs with a single
command, by using various options.
2.1.1 The FIRtree
TM
Media Intrinsics
The FIRtreeTM Media Intrinsics read 128-bit words of data
memory for each cluster, each of which contain multiple data
items, and perform operations simultaneously on each of the
items within the word.
The FIRtreeTM Media Intrinsics C-language extensions
perform operations on partitioned native data types within 32-
or 64-bit operands, making use of the PLV and PLC registers
on the IG-ALU to store intermediate values.
2.2 Libraries
The Equator iMMediaC Compiler includes standard C
runtime libraries and libraries specifically designed to support
MAP-CA resources such as DataStreamer and VLx
coprocessor for media applications.
2.3 Assembler
The assembler lets the programmer take the assembly
language source files generated by the compiler, and convert
them into object code files, ready for the linker. Developers
will not typically write assembly language modules
themselves.
2.4 Linker
The linker combines object code files into an executable
module, accepting both object files and object libraries as
input. During linking, the linker resolves all external
references.
2.5 Debugger
Equator’s development environment includes a source-
level debugger based on gdb (GNU debugger). Equator’s gdb
(egdb) runs on both the Windows NT and Linux platforms.
Equator Technologies, Inc. 11
The egdb debugger allows the user to
• load a MAP-CA application from the host PC file system
onto the MAP-CA and run it
• set, list, and clear software and hardware breakpoints
• single step through both C source code and assembly instruc-
tions
• source level debug of optimized C code
• examine and deposit values into local variables, global vari-
ables and PIO space
• examine and deposit values into all registers
• examine the stack, including stack backtracing
Numerous freeware or low-cost gdb GUI front ends exist
on both the Windows NT and Linux platforms that will
transparently layer on egdb’s command line interface and
provide a window-based debugging environment.
2.6 Simulators
The software developer’s toolkit includes three software
simulators: trsim, sim, and casim.
Trsim is a high speed, instruction level simulator of the
MAP-CA core unit. This simulator works on an intermediate
representation of a software program and can be used to
initially develop applications and experiment with the
performance of different algorithms and use of compiler
options.
Sim is also a high speed, instruction level simulator. This
simulator works off actual MAP-CA binaries. Sim is a
functional simulator of the MAP-CA core unit with data
cache, DataStreamer, and a subset of I/O devices. It provides
runtime checks against resource constraints and all MAP-CA
features necessary to simulate a MAP-CA running a real-time
operating system and applications.
Casim is a nearly cycle accurate software simulator for the
MAP-CA and models more accurately the core,
DataStreamer, VLx, Video Filter, instruction and data caches,
memories, buses, and a subset of supported I/O devices. Like
sim, this simulator operates off actual MAP-CA binaries.
Casim provides more detailed runtime checks against
resource constraints. Casim provides visibility into internal
machine state and bandwith and augments debugging and
tuning of interactions between VLIW core, DataStreamer, and
VLx programs.
Sim and casim work in conjunction with Equator’s source-
level debugger.
2.7 Boot
Software must contain boot code for execution on MAP-
CA. This boot code configures TLBs and caches. Equator
software tools can automatically add boot code when building
an application.
12 Equator Technologies, Inc.
MAP-CA Data Sheet
3. BGA PIN_OUT Assignment
Signal assignment on the BGA352 package is shown here. . The diagram is the bottom view, with the balls facing the viewer
Signal Name Ball
audioclk_byp_in A2
aVdd18 B3
aVss C4
aVdd18 D5
aVss A3
pixelclk_byp_in B4
ntsc_out_data[3] C5
ntsc_out_data[4] B5
ntsc_out_data[5] A4
ntsc_out_data[6] C6
ntsc_out_data[7] D7
video_ina[0] B6
video_ina[1] C7
video_ina[2] D8
video_ina[3] A6
video_ina[4] B7
video_ina[5] A7
video_ina[6] C8
video_ina[7] D9
video_ina[8] B8
video_ina[9] C9
tcia_inuse A8
tcia_sync A9
tcia_clk C10
tcia_vdac B10
ntsc_ina_clk27 A10
video_inb[0] C11
video_inb[1] B11
video_inb[2] A11
video_inb[3] D12
video_inb[4] C12
video_inb[5] B12
video_inb[6] A13
video_inb[7] C13
video_inb[8] D13
video_inb[9] B13
tcib_inuse A14
tcib_sync B14
tcib_clk C14
Signal Name Ball
ntsc_inb_clk27 D14
vsync A16
hsync B15
tms B16
trst C15
aVss A17
gdac_fscale B17
gdac_comp C16
aVdd33 D16
gdac_green C17
gdac_blue A18
gdac_red A19
gdac_cvgg (aVss) C18
aVddx (aVdd18) D17
aVssx (aVss) B19
tdi A20
tck B20
tdo C19
no connection A21
sddata[0] B21
sddata[1] C20
Signal Name Ball
sddata[2] D19
sddata[3] A23
sddqm[0] B22
sddata[4] C21
sddata[5] A24
sddata[6] B23
sddata[7] C22
sddata[8] D21
sddata[9] A25
sddata[10] B24
sddata[11] C23
sddqm[1] D22
sddata[12] D24
sddata[13] B26
sddata[14] C25
sddata[15] E24
sddata[16] D25
sddata[17] D26
sddata[18] E25
sddata[19] F24
sddqm[2] F26
Signal Name Ball
sddata[20] G24
sddata[21] G25
sddata[22] H25
sddata[23] H24
sddata[24] H26
sddata[25] J24
sddata[26] J25
sddata[27] K24
sddqm[3] K26
sddata[28] L24
sddata[29] L25
sddata[30] M25
sddata[31] M24
sdcs_[0] M26
sdcs_[1] N24
sdcs_[2] N25
sdcs_[3] P26
sdrtnclk P24
sdclk R25
sdclk1 R24
sdclk2 T26
Signal Name Ball
sdras_ T25
sdcas_ T24
sdwe_ U25
sdadr[0] U24
sdadr[1] V26
sdadr[2] V24
sdadr[3] W25
sdadr[4] Y26
sdadr[5] W24
sdadr[6] Y25
sdadr[7] Y24
sdadr[8] AA25
sdadr[9] AA24
sdadr[10] AB26
sdadr[11] AD26
sdadr[12] AB24
sdadr[13] AD25
sddata[32] AC24
sddata[33] AB23
aVss AC22
aVssq (aVss) AD23
Signal Name Ball
26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
25
24
23
18
17
22
21
20
19
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
26
25
24
23
18
17
22
21
20
19
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Equator Technologies, Inc. 13
aVddq (aVdd18) AE24
aVdd18 AF25
sdclk_byp_in AC21
pclk AD22
coreclk_byp_in AE23
pci_clk AF24
sddata[34] AD21
sddata[35] AF23
sddqm[4] AF22
sddata[36] AE21
sddata[37] AC19
sddata[38] AD20
sddata[39] AF21
sddata[40] AF20
sddata[41] AC18
sddata[42] AD19
sddata[43] AE19
sddqm[5] AD18
sddata[44] AF19
sddata[45] AE18
sddata[46] AD17
sddata[47] AE17
sddata[48] AF17
sddata[49] AD16
sddata[50] AF16
sddata[51] AC15
sddqm[6] AD15
sddata[52] AE15
sddata[53] AF15
sddata[54] AD14
sddata[55] AE14
sddata[56] AF13
sddata[57] AD13
sddata[58] AF12
sddata[59] AE12
sddqm[7] AD12
sddata[60] AC12
sddata[61] AF11
sddata[62] AD11
sddata[63] AF10
pci_ad[0] AE10
pci_ad[1] AD10
pci_ad[2] AE9
Signal Name Ball
pci_ad[3] AF8
pci_ad[4] AD9
pci_ad[5] AE8
pci_ad[6] AC9
pci_ad[7] AD8
pci_cbe_[0] AF7
pci_ad[8] AF6
pci_ad[9] AD7
pci_ad[10] AC8
pci_ad[11] AE6
pci_ad[12] AF5
pci_ad[13] AF4
pci_ad[14] AD6
pci_ad[15] AF3
pci_cbe_[1] AE4
pci_par AD5
pci_serr_intb_ AC6
pci_stop_ AF2
pci_devsel_ AE3
pci_trdy_ AD4
pci_irdy_ AC5
Vsbb (Vss) AD2
Vsbc (Vdd18) AE1
Vdbb (Vdd18) AC3
Vdbc (Vss) AB3
pci_frame_ AC2
pci_cbe_[2] AC1
pci_ad[16] AB1
pci_ad[17] AA2
pci_ad[18] AA3
pci_ad[19] AA1
pci_ad[20] Y3
pci_ad[21] Y2
pci_ad[22] W1
pci_ad[23] W2
pci_idsel W3
pci_cbe_[3] V1
pci_ad[24] V3
pci_ad[25] U1
pci_ad[26] U4
pci_ad[27] U3
pci_ad[28] U2
pci_ad[29] T3
Signal Name Ball
pci_ad[30] T2
pci_ad[31] R3
pci_req_[0] R2
pci_req_[1] R1
pci_req_[2] P3
pci_gnt_[0] P1
pci_gnt_[1] N1
pci_gnt_[2] N2
pclk_out N3
pci_rst_ M2
pci_inta_ M3
pci_pme_ L1
iic_sda L2
iic_sck L3
ddc_select K1
iis_in_data K3
iis_in_lr J1
iis_in_bclk K4
iis_out_data[0] J2
iis_out_data[1] J3
iis_out_data[2] H2
iis_out_lr G1
iis_out_bclk H3
iec958_in G2
iec958_out G3
rom_cs_ F1
ntsc_out_hsync F3
ntsc_out_vsync E1
ntsc_out_data[0] E2
ntsc_out_data[1] E3
ntsc_out_data[2] C1
audioclk_out C2
pixelclk_out D3
Vdd18 D6
Vdd18 D11
Vdd18 D15
Vdd18 D20
Vdd18 E23
Vdd18 G23
Vdd18 H23
Vdd18 K23
Vdd18 M23
Vdd18 P23
Signal Name Ball
Vdd18 T23
Vdd18 V23
Vdd18 W23
Vdd18 AA23
Vdd18 AC20
Vdd18 AC16
Vdd18 AC11
Vdd18 AC7
Vdd18 AB4
Vdd18 AA4
Vdd18 W4
Vdd18 T4
Vdd18 P4
Vdd18 N4
Vdd18 M4
Vdd18 J4
Vdd18 G4
Vdd18 F4
Vdd33 C3
Vdd33 D4
Vdd33 E4
Vdd33 D10
Vdd33 D18
Vdd33 C24
Vdd33 D23
Vdd33 F23
Vdd33 J23
Vdd33 L23
Vdd33 N23
Vdd33 R23
Vdd33 U23
Vdd33 Y23
Vdd33 AD24
Vdd33 AC23
Vdd33 AC17
Vdd33 AC14
Vdd33 AC13
Vdd33 AC10
Vdd33 AD3
Vdd33 AC4
Vdd33 Y4
Vdd33 V4
Vdd33 R4
Signal Name Ball
Vdd33 L4
Vdd33 H4
Vss A1
Vss B1
Vss B2
Vss A5
Vss B9
Vss A12
Vss A15
Vss B18
Vss A22
Vss A26
Vss B25
Vss C26
Vss E26
Vss F25
Vss G26
Vss J26
Vss K25
Vss L26
Vss N26
Vss P25
Vss R26
Vss U26
Vss V25
Vss W26
Vss AA26
Vss AB25
Vss AC26
Vss AC25
Vss AE26
Vss AE25
Vss AF26
Vss AE22
Vss AE20
Vss AF18
Vss AE16
Vss AF14
Vss AE13
Vss AE11
Vss AF9
Vss AE7
Vss AE5
Signal Name Ball
14 Equator Technologies, Inc.
MAP-CA Data Sheet
Vss AF1
Vss AE2
Vss AD1
Vss AB2
Vss Y1
Vss V2
Vss T1
Vss P2
Vss M1
Vss K2
Vss H1
Vss F2
Vss D1
Vss D2
Signal Name Ball
Equator Technologies, Inc. 15
4. Signal Descriptions
4.1 Processor Clock
7KHUHLVDVLQJOHUHIHUHQFHFORFNVLJQDOZKLFKLV0+]7KUHH3//VDUHXVHGWRJHQHUDWHFORFNVQHHGHGLQWHUQDOO\E\
UHIHUULQJWRWKH0+]FORFN
4.2 PCI Bus
0$3&$SURYLGHVWKH3&,EXVDVWKHSULPDU\V\VWHPLQWHUIDFH,WFDQVXSSRUWXSWRIRXUORDGVRQWKH3&,EXV
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SIGNAL #a
a. Number of pins
I/Ob
b. I: Input; O: output; B: bi-directional.
DESCRIPTION
SFON , 0+]9&;2RVFLOODWRULQSXWLVSURYLGHGWRWKH
&RUH6'5$0SL[HODQGDXGLR3//V,WLV
DOVRDUHIHUHQFHFORFNWR,785%72XWDQG,
&
FRUHFONBE\SBLQ , %\SDVVLQSXWIRUWKHFRUHFORFN
VGFONBE\SBLQ , %\SDVVLQSXWIRUWKH6'5$0FORFN
SL[HOFONBE\SBLQ , %\SDVVLQSXWIRUWKHSL[HOFORFN
DXGLRFONBE\SBLQ , %\SDVVLQSXWIRUWKHDXGLRFORFN
FRUHFONBRXW 2 2XWSXWIRUWKHFRUHFORFN
SL[HOFONBRXW 2 2XWSXWIRUWKHSL[HOFORFN
DXGLRFONBRXW 2 2XWSXWIRUWKHDXGLRFORFN
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SIGNAL # I/O DESCRIPTION
SFLBDG>@  % 3&,PXOWLSOH[HGDGGUHVVDQGGDWDOLQHV7KHDGGUHVVLVGULYHQZKHQSFLBIUDPHBLVILUVWDVVHUWHG'DWD
LVWUDQVIHUUHGRQWKLVEXVLQVXEVHTXHQWFORFNV
SFLBFEHB>@ % )RU3&,F\FOHVWKHEXVFRPPDQGDQGE\WHHQDEOHVDUHXVHGWRWUDQVIHUWKH3&,FRPPDQGGXULQJ
WKHDGGUHVVSKDVHDQGDUHXVHGWRWUDQVIHUE\WHODQHHQDEOHVGXULQJVXEVHTXHQWGDWDSKDVHV
SFLBIUDPHB % 7UDQVDFWLRQIUDPLQJIRU3&,WUDQVIHUV7KHLQLWLDODVVHUWLRQLQGLFDWHVWKHDGGUHVVSKDVHDQGWKHVWDUW
RID3&,WUDQVDFWLRQ&RQWLQXHGDVVHUWLRQGHWHUPLQHVWKHEXUVWVL]HRIWKHWUDQVDFWLRQ
SFLBWUG\B % 7KHWDUJHWUHDG\VLJQDOLVDVVHUWHGZKHQWKH3&,WDUJHWLVUHDG\IRUDGDWDWUDQVIHU
SFLBLUG\B % 7KHLQLWLDWRUUHDG\VLJQDOLVDVVHUWHGZKHQWKH3&,PDVWHULVUHDG\IRUDGDWDWUDQVIHU
SFLBVWRSB % SFLBVWRSBLVDVVHUWHGE\WKHWDUJHWWRUHTXHVWWKHPDVWHUWRVWRSWKHFXUUHQWWUDQVDFWLRQ
SFLBSDU % $VLQJOHSDULW\ELWLVFDOFXODWHGRYHUSFLBDG>@DQGSFLBFBEH>@DQGWUDQVIHUUHGRYHUWKLVVLJQDO
SFLBGHYVHOB %
$WDUJHWDVVHUWVWKHSFLBGHYVHOBVLJQDOOLQHWRLQGLFDWHLWKDVGHFRGHGWKHDGGUHVVRQWKHSFLBDG>@
EXVDQGZLOOSDUWLFLSDWHLQFODLPWKHFXUUHQWWUDQVDFWLRQ7KH3&,EXVPDVWHUPXVWPRQLWRUWKH
SFLBGHYVHOBVLJQDOOLQHWRGHWHUPLQHLIDWDUJHWEXVKDVFODLPHGWKHWUDQVDFWLRQRULID0DVWHU$ERUW
WHUPLQDWLRQZLOOEHH[HFXWHGSFLBGHYVHOBZLOOEHWULVWDWHGIURPWKHOHDGLQJHGJHRISFLBUVWB
SFLBGHYVHOBUHPDLQVWULVWDWHGXQWLOGULYHQE\WKHWDUJHW
SFLBFON , SFLBFONSURYLGHVWLPLQJIRUDOO3&,WUDQVDFWLRQVRQWKH3&,EXV$OORWKHU3&,VLJQDOVDUHVDPSOHG
RQWKHULVLQJHGJHRISFLBFONDQGDOOWLPLQJSDUDPHWHUVDUHGHILQHGZLWKUHVSHFWWRWKLVHGJH
127(7KH0$3&$FRUHFORFNSOOGRHVQRWXVHWKLVFORFNDVDFRUHSOOUHIHUHQFHFORFN
SFLBUVWB , 7KLVVLJQDOLQGLFDWHVDUHVHWRIDOO3&,UHVRXUFHV,QDGGLWLRQWKHLQWHUQDO0$3&$&38FRUHHWF
DUHUHVHWE\WKHDVVHUWLRQRIWKLVVLJQDO3&,SDGFHOOGULYHUVDUHGLVDEOHGE\WKHDVVHUWLRQRIWKLV
VLJQDODVVSHFLILHGLQWKH3&,GRFXPHQW
16 Equator Technologies, Inc.
MAP-CA Data Sheet
4.3 SDRAM
0$3&$VXSSRUWVHLWKHU6'5$0RU6*5$0PHPRU\V\VWHPXVLQJVLJQDOVVKRZQEHORZ$PHPRU\V\VWHPRIELWRU
ELWGDWDZLGWKLVVXSSRUWHG'5$0ZLGWKVRIELWELWRUELWDUHVXSSRUWHG
SFLBLQWDB %
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:KHQWKH0$3&$LVQRWGHVLJQDWHGDVWKH´+267µIRUWKH3&,EXVWKHQWKLVVLJQDOLVWKHRSHQ
GUDLQRXWSXWXVHGWRJHQHUDWHDQDV\QFKURQRXVOHYHOVHQVLWLYHLQWHUUXSWRQWKH3&,EXV7KH0$3
&$SDGFHOOGRHV127FRQWDLQDSXOOXSIRUWKLVVLJQDO
:KHQWKH0$3&$LVGHVLJQDWHGDVWKH´+267µIRUWKH3&,EXVWKHQWKLVVLJQDOLVDQLQWHUUXSW
UHTXHVWLQSXWIURP3&,GHYLFHV7KLVLQWHUUXSWLVVHHQDQGXWLOL]HGE\0$3&$
SFLBLGVHO , 7KHLQLWLDOL]DWLRQGHYLFHVHOHFWLVXVHGDVDVORWDGGUHVVHGFKLSVHOHFWLQSXWGXULQJFRQILJXUDWLRQUHDG
DQGZULWHWUDQVDFWLRQV7KLVVLJQDOLVLQDFWLYHLQDVHOIKRVWHGFRQILJXUDWLRQ
SFLBUHTB>@ % 7KHDVVHUWLRQRISFLBUHTBLQDQRQVHOIKRVWHGFRQILJXUDWLRQLQGLFDWHVWKDW0$3&$GHVLUHVWKHXVH
RIWKH3&,EXV
SFLBJQWB>@ % 7KHDVVHUWLRQRISFLBJQWBLQDQRQVHOIKRVWHGHQYLURQPHQWLQGLFDWHVWKDW0$3&$KDVEHHQ
JUDQWHGWKHXVHRIWKH3&,EXV
SFLBVHUUBLQWEB %
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7KLVRSHQGUDLQRXWSXWFDQHLWKHUEHXVHGWRJHQHUDWHDQDV\QFKURQRXVOHYHOVHQVLWLYHLQWHUUXSWRQ
WKH3&,EXVRURSWLRQDOO\WRVLJQDO6<67(0(55256HHWKH0$3&$FRQILJXUDWLRQFRQWURO
UHJLVWHUIRUWKHFXUUHQWXVHRIWKLVVLJQDO
:KHQ0$3&$LVQRWGHVLJQDWHGDVWKH´+267µIRUWKH3&,EXVWKHQWKLVVLJQDOLVWKHRSHQGUDLQ
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UHTXHVWLQSXWIURP3&,GHYLFHV7KLVLQWHUUXSWLVVHHQDQGXWLOL]HGE\WKH0$3&$
SFLBSPHB %
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FKDQJHLQSRZHUPDQDJHPHQWVWDWH
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SIGNAL # I/O DESCRIPTION
VGDGU>@ 2 $GGUHVVOLQHVLQGLFDWHURZDGGUHVVHVZKHQVGUDVBLVDFWLYHZKLOH$GGUHVVOLQHVLQGLFDWHFROXPQ
DGGUHVVHVZKHQVGFDVBLVDFWLYH
VGGDWD>@  % 'DWD,QSXW2XWSXWOLQHVWUDQVIHUGDWDEHWZHHQWKHPHPRU\DQG0$3&$7KHVHDUHDOVRLQSXWPDVN
ELWVIRU:ULWHSHU%LW:KHQEORFNZULWHLVDFWLYDWHGWKHVHOLQHVSURYLGHFROXPQDGGUHVVPDVN
VGFVB>@ 2 &KLS6HOHFWVLJQDOOLQHVLQGLFDWHWKDWWKHFRPPDQGRQWKHRXWSXWOLQHVLVIRUHDFKPHPRU\FKLS,IWKLV
VLJQDOLVKLJKWKHRXWSXWFRPPDQGVZLOOEHLJQRUHGE\HDFKFRUUHVSRQGLQJPHPRU\FKLS
VGUDVB 2 VGUDVBLVSDUWRIWKHRXWSXWFRPPDQGWRWKH6'*5$0
VGFDVB 2 VGFDVBLVSDUWRIWKHRXWSXWFRPPDQGWRWKH6'*5$0
VGZHB 2 :ULWHHQDEOHVGZHBLVSDUWRIWKHRXWSXWFRPPDQG
VGGTP>@ 2 'XULQJUHDGVGGTP WXUQVRIIWKHRXWSXWEXIIHUVRI6'*5$0'XULQJZULWHVGGTP SUHYHQWV
DZULWHWRWKHFXUUHQWPHPRU\ORFDWLRQ
VGFONVGFONVGFON 2 VGFONVGFONDQGVGFONDUHGULYHQE\WKH0$3&$6'5$0FORFN$OO6'*5$0LQSXWVLJQDOVDUH
VDPSOHGRQWKHSRVLWLYHHGJHRIVGFON
VGUWQFON , VGUWQFONLVGULYHQE\VGFON7KLVVLJQDOLVXVHGIRUODWFKLQJWKHGDWDIURP6'6*5$0
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Equator Technologies, Inc. 17
4.4 Flash ROM
$)ODVK520((3520LQWHUIDFHLVSURYLGHGRQ0$3&$WRDVVLVWLQERRWXS7KH)ODVK520LVDFWLYHGXULQJWKH
ERRWXSSURFHVVDQGPXVWEHGLVDEOHGWKURXJKLWVFKLSVHOHFWVLJQDO
4.5 Analog CRT
$Q5*%PRQLWRUFDQEHGLUHFWO\GULYHQE\0$3&$
4.6 ITU-R BT.601/656 Output
0$3&$KDVDGLUHFW,785%7RXWSXWLQWHUIDFH
.
Note that ntsc_out_data[7:0], ntsc_out_hync, and ntsc_out_vsync are multiplexed over ROM address/data signals. See the Section 4.12,
ROM and Reset Strap.
7
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520
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Name # I/O DESCRIPTION
URPBFVB 2 7KLVSLQLVWKHFKLSHQDEOHVLJQDO
URPBRHB  2 7KLVDFWLYHORZVLJQDOLVDVVHUWHGRQ520UHDGF\FOHV7KLVVLJQDOLVPXOWLSOH[HGZLWKLLVBRXWBGDWD>@
URPBZUWB  2 7KLVDFWLYHORZVLJQDOLVDVVHUWHGRQ520ZULWHF\FOHV7KLVVLJQDOLVPXOWLSOH[HGZLWK
LLVBRXWBGDWD>@
URPBDOH  2 $GGUHVVODWFKHQDEOHURPBDGGU>@DQGURPBDGGU>@DUHODWFKHGRQWKHULVLQJHGJH
URPBDGGU>@DQGURPBDGGU>@DUHODWFKHGRQWKHIDOOLQJHGJH7KLVVLJQDOLVPXOWLSOH[HGZLWK
LLVBRXWBGDWD>@
URPBDGGU>@U
RPBDGGU>@UR
PBDGGU>@  2 7ZR/6%VDQGKLJKRUGHUELWVRIWKH520DGGUHVVDUHDOZD\VGHPX[HG
URPBDGGU>@URPBDGGU>@URPBDGGU>@LVPXOWLSOH[HGZLWKQWVFBRXWBKV\QF
URPBDGGU>@URPBDGGU>@URPBDGGU>@LVPXOWLSOH[HGZLWKQWVFBRXWBYV\QF
URPBDGGU>@URP
BDGGU>@URPB
GDWD>@  ,2 520GDWDDQGDGGUHVVEXV7KLVVLJQDOLVPXOWLSOH[HGZLWKQWVFBRXWBGDWD>@
727$/ 
7
$%/(
&57
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6
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SIGNAL # I/O DESCRIPTION
YV\QF 2 9HUWLFDOV\QFKURQL]DWLRQVLJQDOIRU&57
KV\QF 2 +RUL]RQWDOV\QFKURQL]DWLRQVLJQDOIRU&57
JGDFBIVFDOH $ )XOOVFDOHFXUUHQWDGMXVWLQJUHVLVWHU
JGDFBFRPS $ 9UHIE\SDVVDQGFRPSHQVDWLRQFDSDFLWRU
JGDFBEOXH $ $QDORJEOXHRXWSXW
JGDFBJUHHQ $ $QDORJJUHHQRXWSXW
JGDFBUHG $ $QDORJUHGRXWSXW
727$/
7
$%/(
,785%72
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SIGNAL # I/O DESCRIPTION
WFLDBYGDF 2 9&;2IUHTXHQF\FRQWUROVWUHDP
QWVFBFONBYF[R , 0+],785%7SL[HOFORFNIURPYLGHR9&;2FORFNLQSXW7KLVVLJQDOLV
DFWXDOO\SFON6HH6HFWLRQ3URFHVVRU&ORFN
QWVFBRXWBKV\QF 2 +RUL]RQWDOV\QF
QWVFBRXWBYV\QF 2 9HUWLFDOV\QF
QWVFBRXWBGDWD>@ % ,785%7IRUPDWWHG176&RU3$/RXWSXWGDWD
727$/ 
18 Equator Technologies, Inc.
MAP-CA Data Sheet
4.7 Video Input Ports
0$3&$SURYLGHVWZR9LGHR,QSRUWV(DFKSRUWFDQEHFRQILJXUHGDVHLWKHUD7&,RU,785%7SRUW7KH\
ERWKKDYHWKHVDPHVLJQDOV7KH\DUHPX[HGDVVKRZQEHORZ
4.7.1 Transport Channel Interface (TCI)
0$3&$SURYLGHVWZRSDUDOOHOVHULDO7&,LQWHUIDFHV
7
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257
SIGNAL # I/O
Two Selectable Video Input Ports
Parallel TCI 601 Input
YLGHRBLQD>@ , WFLDBHUUB QWVFBLQDBYV\QF
YLGHRBLQD>@ , WFLDBHQDEOH QWVFBLQDBKV\QF
YLGHRBLQD>@ , WFLDBGDWD>@ QWVFBLQDBGDWD>@
727$/ 
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257
SIGNAL # I/O
Two Selectable Video Input Ports
Parallel TCI 601 Input
YLGHRBLQE>@ , WFLEBHUUB QWVFBLQEBYV\QF
YLGHRBLQE>@ , WFLEBHQDEOH QWVFBLQEBKV\QF
YLGHRBLQE>@ , WFLEBGDWD>@ QWVFBLQEBGDWD>@
727$/ 
7
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SIGNAL # I/O DESCRIPTION
WFLDBGDWD>@  , 7&,GDWDLQSXW
$OOELWVRILQSXWDUHXVHGLQSDUDOOHOPRGH2QO\WFLBGDWD>@LVXVHGLQVHULDOPRGH
WFLDBHQDEOH  , 7UDQVSRUWFKDQQHOHQDEOH
DFFHSWDE\WHRI7&,LQSXW
VWDOO7&,LQSXW
WFLDBLQXVH 2 9LGHRLQSXWSRUWH[WHUQDOPX[VHOHFW VHOHFWWUDQVSRUWVWUHDPIRUYLGHRLQSXWSRUW VHOHFW
,785%7
VWUHDPIRUYLGHRLQSXW&DQDOVREHXVHGDVDJHQHUDOSXUSRVHRXWSXWLI
G\QDPLFYLGHRPX[LQJLVQRWUHTXLUHG
WFLDBV\QF , 'HPRGXODWRU)(&KDVPDUNHGWKHV\QFKURQL]DWLRQSRLQWLQWKH%03(*SDFNHW
WFLDBHUUB  , 7KLVDFWLYHORZVLJQDOLQGLFDWHVWKDWWKH'HPRGXODWRU)(&KDVGHWHFWHGDQXQFRUUHFWDEOHHUURULQ
WKHFXUUHQWSDFNHW
WFLDBFON , 7UDQVSRUWFKDQQHOFORFNFDQDFFHSWLQSXWXSWR0+]IRUSDUDOOHOPRGHDQGXSWR0+]IRU
VHULDOPRGH
WFLDBYGDF 2 6LPXODWHGVLJPDGHOWDRXWSXWSURYLGLQJ9&;2RIIVHWIRUWKHYLGHRFORFNVRXUFH
727$/ 
7
$%/(
6
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6
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SIGNAL # I/O DESCRIPTION
WFLEBGDWD>@  , 7&,GDWDLQSXW
$OOELWVRILQSXWDUHXVHGLQSDUDOOHOPRGH2QO\WFLBGDWD>@LVXVHGLQVHULDOPRGH
WFLEBHQDEOH  , 7UDQVSRUWFKDQQHOHQDEOH
DFFHSWDE\WHRI7&,LQSXW
VWDOO7&,LQSXW
WFLEBLQXVH 2 9LGHRLQSXWSRUWH[WHUQDOPX[VHOHFW VHOHFWWUDQVSRUWVWUHDPIRUYLGHRLQSXWSRUW VHOHFW
,785%7
VWUHDPIRUYLGHRLQSXW&DQDOVREHXVHGDVDJHQHUDOSXUSRVHRXWSXWLI
G\QDPLFYLGHRPX[LQJLVQRWUHTXLUHG
Equator Technologies, Inc. 19
4.7.2 ITU-R BT.601/656 Input
$QDORJYLGHRFDQEHVWUHDPHGLQYLDD176&3$/RU69,'(2GHFRGHUZLWK,785%7IRUPDWWHGLQSXW7KH
SULPDU\DQGVHFRQGDU\,785%7,QSRUWVKDYHWKHVDPHVLJQDOVDVVKRZQEHORZ
4.8 I2S
0$3&$SURYLGHVDQ,6GLJLWDODXGLRLQWHUIDFHDVVKRZQEHORZ
WFLEBV\QF , 'HPRGXODWRU)(&KDVPDUNHGWKHV\QFKURQL]DWLRQSRLQWLQWKH%03(*SDFNHW
WFLEBHUUB , 7KLVDFWLYHORZVLJQDOLQGLFDWHVWKDWWKH'HPRGXODWRU)(&KDVGHWHFWHGDQXQFRUUHFWDEOHHUURULQ
WKHFXUUHQWSDFNHW
WFLEBFON , 7UDQVSRUWFKDQQHOFORFNFDQDFFHSWLQSXWXSWR0+]IRUSDUDOOHOPRGHDQGXSWR0+]IRU
VHULDOPRGH
727$/ 
7
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SIGNAL # I/O DESCRIPTION
QWVFBLQDBFON , 0+]
,785%7
FORFNIURPYLGHRGHFRGHU
QWVFBLQDBKV\QF  , +RUL]RQWDOV\QF
QWVFBLQDBYV\QF  , 9HUWLFDOV\QF
QWVFBLQDBGDWD>@ ,
,785%7
IRUPDWWHG176&RU3$/YLGHR
LQSXWVWUHDP
727$/ 
7
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SIGNAL # I/O DESCRIPTION
QWVFBLQEBFON , 0+]
,785%7
FORFNIURPYLGHRGHFRGHU
QWVFBLQEBKV\QF , +RUL]RQWDOV\QF
QWVFBLQEBYV\QF  , 9HUWLFDOV\QF
QWVFBLQEBGDWD>@ ,
,785%7
IRUPDWWHG176&RU3$/YLGHR
LQSXWVWUHDP
727$/ 
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SIGNAL # I/O DESCRIPTION
LLVBLQBGDWD , 6HULDO7'0LQSXWVWUHDPWRSULPDU\FRGHF
LLVBLQBOU , 6HOHFWOHIWULJKWFKDQQHOLQWKHVHULDOLQSXWOLQH
LLVBLQBEFON , ,
6FORFNWRLQSXWGDWDRQWKHVHULDOLQSXWOLQH
LLVBRXWBGDWD>@ 2 6HULDO7'0RXWSXWVWUHDPWRSULPDU\FRGHF
LLVBRXWBPFON  2 ,
6RXWSXWPDVWHUFORFN7KLVVLJQDOLVDFWXDOO\
DXGLRFONBRXW6HH6HFWLRQ3URFHVVRU&ORFN
LLVBRXWBOU 2 6HOHFWOHIWULJKWFKDQQHOLQDVHULDORXWSXWOLQH
LLVBRXWBEFON 2 ,
6FORFNWRWUDQVIHUGDWDRQGLJLWDODXGLRVHULDOOLQHV
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20 Equator Technologies, Inc.
MAP-CA Data Sheet
4.9 IEC958
0$3&$SURYLGHVDQ,(&LQWHUIDFHDVVKRZQEHORZ
4.10 I2C
MAP-CA provides an I2C interface to communicate with external peripherals such as NTSC decoders, NTSC encoders,
Demodulators, etc. This interface can also be used to control a monitor such as by the DDC for a monitor through software
control (iic_select). The pin description is shown in the following table.
4.11 JTAG
7KH-7$*SLQVRQ0$3&$FRQIRUPWRWKH,(((-7$*VSHFXVHGIRUPDQXIDFWXULQJWHVW
4.12 ROM and Reset Strap
7RVDYHSLQV0$3&$DOORZVDFFHVVWRD)ODVK520RQO\ZKHQWKH9HUVD3RUWSLQVDUHHQDEOHGIRUXVHE\520&21
HJGXULQJERRWDQGWRWKHUHVHWVWUDSVRQO\GXULQJUHVHW7KH520DQG5HVHW6WUDSVLJQDOVVKRXOGEHFRQQHFWHGWR
0$3&$VLJQDOVDVVKRZQEHORZ
7
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SIGNAL # I/O DESCRIPTION
LHFBLQ , 6HULDOLQSXWOLQHIRU,(&GLJLWDODXGLR
LHFBRXW 2 6HULDORXWSXWOLQHIRU,(&GLJLWDODXGLR
727$/
7
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SIGNAL # I/O DESCRIPTION
LLFBVGD % ,
&GDWDOLQH
LLFBVFN % ,
&FORFNOLQH
LLFBVHOHFW 2 3URJUDPPDEOH,2SLQXVHGWRVHOHFWEHWZHHQ,
&DQGDQRWKHUH[WHUQDOEXV
727$/
7
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SIGNAL # I/O DESCRIPTION
WFN , 7HVWFORFNLQSXW
WPV , 7HVWPRGHVHOHFWWRFRQWUROWHVWRSHUDWLRQV
WGL , 7HVWGDWDLQSXWGDWD
WGR 2 7HVWGDWDRXWSXW
WUVW , 7HVWUHVHWVLJQDOWRDV\QFKURQRXVO\UHVHWWKH7$3FRQWUROOHU
727$/
7
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211(&7,216
Signal
Pin #
Signal
Run Time Reset Time Rom Boot Description for Resistor Straps
QWVFBRXWBGDWD>@  VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW
QWVFBRXWBGDWD>@  VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW
QWVFBRXWBGDWD>@  VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW
QWVFBRXWBGDWD>@  VZBVWUDS>@ URPBDGGU>@URPBDGGU>@URPBGDWD>@ 6RIWZDUHVWUDSVIRUERRW
QWVFBRXWBGDWD>@ 
8QXVHG
URPBDGGU>@URPBDGGU>@URPBGDWD>@
QWVFBRXWBGDWD>@ 
8QXVHG
URPBDGGU>@URPBDGGU>@URPBGDWD>@
Equator Technologies, Inc. 21
4.13 Power/Ground Pins
7KHIROORZLQJSRZHUDQGJURXQGSLQVDUHSURYLGHG
Note: There are 4 pins dedicated for grounds and power signals for back bias:
Vsbb (vss) : Back bias supply pin for NMOS.
Vsbc (Vdd18) : Back bias control pin for NMOS.
Vdbb (Vdd18) : Back bias supply pin for PMOS.
Vdbc (Vss) : Back bias control pin for PMOS.
In regular operation, Vsbb and Vdbc are connected to Vss, Vsbc and Vdbb are connected to Vdd.
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LLVBRXWBGDWD>@
8QXVHG
URPBRHB
LLVBRXWBGDWD>@
8QXVHG
URPBZUWB
LLVBRXWBGDWD>@
8QXVHG
URPBDOH
QWVFBRXWBKV\QF
8QXVHG
URPBDGGU>@URPBDGGU>@URPBDGGU>@
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8QXVHG
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Name # DESCRIPTION
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9VV 'LJLWDO9VV
D9GG &OHDQDQDORJ9GG
D9VV &OHDQDQDORJ9VV
D9GG &OHDQDQDORJ9GG
D9GGT &OHDQDQDORJ9GGIRU&RUH3//
D9VVT &OHDQDQDORJ9VVIRU&RUH3//
D9GG[ &OHDQDQDORJ9GGIRU9LGHR'$&
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211(&7,216
22 Equator Technologies, Inc.
MAP-CA Data Sheet
4.14 Signal List Summary
7
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Interface Frequency # Pins Remarks
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Equator Technologies, Inc. 23
4.15 Interface Summary
pci_ad[31:0]
pci_cbe[3:0]
pci_frame#
pci_trdy#
pci_irdy#
pci_stop#
pci_par
pci_devsel#
pci_clk
pci_rst#
pci_inta#
pci_idsel
pci_req#[2:0]
MAP-CA
Processor
Clock
(PLL)
SDRAM
Controller
sdadr[13:0]
sddata[63:0]
sdcs[3:0]#
sdras#
sdcas#
sdwe#
sddqm[7:0]
sdclk
sdclk1
sdclk2
sdrtnclk
pclk/ntsc_clk27_vcxo
coreclk_byp_in
sdclk_byp_in
pixelclk_byp_in
iic_sda
iic_sck
gdac_fscale
gdac_comp
gdac_blue
gdac_green
gdac_red
tck
tms
tdi
tdo
trst
I2C/DDC
CRT
VIDEO
(DRC)
PCI
pixelclk_out
audioclk_out/iis_out_mclk
audioclk_byp_in
coreclk_out
pci_gnt#[2:0]
pci_pme#
pci_serr_intb#
FLASH
ROM
(rom_oe#)/iis_out_data[2]
(rom_wrt#)/iis_out_data[1]
(rom_ale)/iis_out_data[0]
rom_cs#
vsync
hsync
ddc_select
tcia_err# / ntsc_ina_vsync
tcia_enable / ntsc_ina_hsync
tcia_data[7:0] / ntsc_ina_data[7:0]
tcib_err# / ntsc_inb_vsync
tcib_enable / ntsc_inb_hsync
tcib_data[7:0] / ntsc_inb_data[7:0]
VIDEO
INPUT
port0
port1
tcia_inuse
tcia_sync
tcia_clk
tcia_vdac
tcib_inuse
tcib_sync
tcib_clk
ntsc_ina_clk27
ntsc_inb_clk27
JTAG
OUTPUT
iis_in_lr
iis_in_bclk
iis_out_lr
iis_out_bclk
iis_in_data
I2S
iec958_in
IEC958
iec958_out
( ) --- valid during boot-up
< > --- valid during reset
(rom_addr[19]/rom_addr[21]/rom_addr[1])/
<reset_strap[7:0]>/
ntsc_out_data[7:0]
(rom_addr[18]/rom_addr[20]/rom_addr[0])/
ntsc_out_hsync
ntsc_out_vsync
(rom_addr[9:2]/rom_addr[17:10]/rom_data[7:0])/
24 Equator Technologies, Inc.
MAP-CA Data Sheet
5. External Connection Examples
5.1 ROM
5.2 SDRAM
URPBDGGU>@
URPBFV
URPBZU
URPBRH
DGGU>@
URPBDOH
DGGU>@
DGGU>@
URPBGDWD>@
MAP-CA
DGGU>@
FLASH ROM INTERFACE
FLASH ROM
O
D
W
F
K
O
D
W
F
K
O
D
W
F
K
O
D
W
F
K
64-bit, 16MB configuration using x16, 16Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@
.
EDQNV
[ELW
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6*5$0
VGFV>@
.
EDQNV
[ELW
6*5$0
VGGDWD>@
VGGTP>@
.
EDQNV
[ELW
6*5$0
VGFV>@
VGFV>@
1&
1&
VGUWQFON
64-bit, 4MB configuration using x32, 8Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@ VGFV>@
.
EDQNV
[ELW
6'5$0
VGGDWD>@
VGGTP>@
VGFV>@
VGFV>@
1&
1&
VGGDWD>@
VGGTP>@
VGGDWD>@
VGGTP>@
.
EDQNV
[ELW
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EDQNV
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.
EDQNV
[ELW
6'5$0
VGUWQFON
Equator Technologies, Inc. 25
64-bit, 16MB configuration using x8, 16Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@ VGFV>@
0
EDQNV
[ELW
6'5$0
VGGDWD>@
VGGTP>@
VGFV>@
VGFV>@
1&
1&
VGGDWD>@
VGGTP>@
VGGDWD>@
VGGTP>@
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
1&
0
EDQNV
[ELW
6'5$0
VGGTP>@
VGGTP>@
VGGTP>@
VGGTP>@
VGGDWD>@
VGGDWD>@
VGGDWD>@
VGGDWD>@
VGUWQFON
64-bit, 64MB configuration using x16, 64Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@ VGFV>@
0
EDQNV
[ELW
6'5$0
VGGDWD>@
VGGTP>@
VGFV>@ VGFV>@
1& 1&
VGGDWD>@
VGGTP>@
VGGDWD>@
VGGTP>@
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
VGUWQFON
64-bit, 128MB configuration using x16, 64Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@ VGFV>@
0
EDQNV
[ELW
6'5$0
VGGDWD>@
VGGTP>@
VGFV>@ VGFV>@
VGGDWD>@
VGGTP>@
VGGDWD>@
VGGTP>@
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
VGUWQFON
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
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0
EDQNV
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0
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[ELW
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0
EDQNV
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0
EDQNV
[ELW
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0
EDQNV
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64-bit, 64MB configuration using x16, 128Mb parts
VGDGU>@
VGGDWD>@
VGUDV
VGFDV
VGZH
VGGTP>@
VGFON
VGFV>@ VGFV>@
0
EDQNV
[ELW
6'5$0
VGGDWD>@
VGGTP>@
VGFV>@ VGFV>@
1& 1&
VGGDWD>@
VGGTP>@
VGGDWD>@
VGGTP>@
0
EDQNV
[ELW
6'5$0
0
EDQNV
[ELW
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0
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VGUWQFON
26 Equator Technologies, Inc.
MAP-CA Data Sheet
5.3 NTSC Decoder
5.4 NTSC Encoder
5.5 IEC958
NTSC/PAL
SL[HOBFONBRXW
QWVFBLQDBGDWD>@

QWVFBLQDBFON
Decoder
ITU-R BT.656 NTSC/PAL DECODER INTERFACE

QWVFBLQDBKV\QF
Video In Port 0
MAP-CA

QWVFBLQDBYV\QF
MAP-CA
ITU-R BT.656 NTSC/PAL ENCODER INTERFACE
9&;2
0+]
NTSC/PAL
Encoder
QWVFBYF[RBFON
QWVFBRXWBGDWD>@

QWVFBRXWBYV\QF

QWVFBRXWBKV\QF
ITU-R BT.601/656 Output
MAP-CA
IEC958 INTERFACE
IEC958
COUPLER

LHFBLQ

LHFBRXW
IEC958 Interface
Equator Technologies, Inc. 27
5.6 I2S
5.7 I2C/DDC
LLVBRXWBEFON
LLVBRXWBOU
LLVBGDWD>@
LLVBGDWD>@
LLVBGDWD>@
LLVBRXWBPFON
IIS audio
CODEC
IIS audio
DECODE
LLVBLQBOU
LLVBLQBEFON
LLVBLQBGDWD
MAP-CA
I
2
S INTERFACE
IIS audio
DECODE
I
2
S INTERFACE
LLFBVGD
LLFBVFN
GGFBVHOHFW
LLFGDWDOLQH
''&GDWDOLQH
LLFFORFNOLQH
''&FORFNOLQH
MAP-CA
0
8
;
0
8
;
I2C/DDC
I2C/DDC INTERFACE
28 Equator Technologies, Inc.
MAP-CA Data Sheet
5.8 Transport Channel Interface (TCI)
5.9 CRT
SATELLITE/CABLE
(QAM-QPSK)
&
FOWARD ERROR
CORRECTION
MAP-CA
tcia_data
tcia_clk
tcia_enable
tcia_sync
tcia_err#
TRANSPORT CHANNEL INTERFACE
SOURCE DECODER
9&;2
0+]
.
.
X)
X)
U
9
2&
VIDEO IN PORT 0
tcia_inuse
ANALOG CRT INTERFACE
75Ohms
Zl=75Ohms
Zo= 37.5 Ohms
gdac_green
gdac_blue
gdac_red
gdac_comp
gdac_fscale
Vref=1.235V
R=1117Ohms
Note: gdac_blue and gdac_red has the same
connections as those of gdac_green.
C C
L
vsync
hsync
MAP-CA
Equator Technologies, Inc. 29
6. Electrical Specifications
6.1 Absolute Maximum Rating
Operation beyond the limits set forth in this table may impair the life of the device.
6.2 Power Supply Specifications
Maximum total power estimate: 6W @300MHz.
6.3 Operating Parameters
Parameter Min Max Units
Voltage on any pin -0.5 Vdd33+0.5 V
Storage Temperature -65 150 oC
Operating Temperature 0 Tj=85 oC
Power
Supply Nominal Voltage
Voltage
Tolerance
Estimated Max
Steady State Current
Estimated
Max power
Vdd 1.8V +/-5% 2.8A 5W
Vdd33 3.3V +/-5% .25A 0.8W
AVdd 1.8V +/-5% 6mA 10mW
AVdd33 3.3V +/-5% 80mA 0.2W
Avddx 1.8V +/-5% 5mA 10mW
TABLE 1. PCI Signals
Parameter Description Min Max Unit
VIL input low voltage -0.5 0.3Vcc V
VIH input high voltage 0.5Vdd33 Vdd33+0.5 V
VOL output low voltage -0.5 0.1Vdd33 V
VOH output high voltage 2.4 V
ILI input leakage current -10 10 uA
ILO output leakage current -10 10 uA
IOZ tri-state output leakage -10 10 uA
CIN input pin capacitance 10 pF
CIDSEL idsel pin capacitance 8 pF
CCLK pci_clk pin capacitance 5 12 pF
30 Equator Technologies, Inc.
MAP-CA Data Sheet
TABLE 2. Non-PCI Signal
6.4 AC Characteristics
6.4.1 SDRAM Interface Timing
Parameter Description Min Max Unit
VIL input low voltage -0.5 0.2Vdd33 V
VIH input high voltage 2.0 Vdd33+0.5 V
VOL output low voltage -0.5 0.2Vdd33 V
VOH output high voltage 2.4 V
ILI input leakage current -10 10 uA
ILO output leakage current -10 10 uA
IOZ tri-state output leakage -10 10 uA
CIN input pin capacitance 10 pF
CIO input/output pin capacitance 12 pF
ICCOP operating current 3(?) A
Symbol Description Min Max Units Notes
fsdram sdclk frequency 133 MHz
tpd propagation delay of address. data,
control (sdras_, sdcas_, sdwe_, sddqm) 5 ns 1
toh
output hold time of address, data,
control (sdras_, sdcas_, sdwe_, sddqm) 1.5 ns 1
tds input data setup time 1 ns 2, 3
tdh input data hold time 2 ns 2, 3
SDRAM timing measurement conditions
sdclk,sdclk1,2
address, data-out, control
sdrtnclk
data-in
t
ds
t
dh
tpd toh
Equator Technologies, Inc. 31
Notes:
20. The center of the rising edges of sdclk1and sdclk2 is used as the reference point.
21.sdrtnclk is used as the reference clock
22.A matching mechanism is provided to compensate for the propagation delay through circuit board traces to and from the
external SDRAM devices. To optimize read timing margin, sdrtnclk should be connected to sdclk with a dedicated trace,
with an optional lumped RC load attached to the middle, to account for the number of SDRAM devices attached to the
clock line.
23.Correct setup and hold times can be guaranteed through internal delay adjustment, controlled by bit [30:24] of the synchro-
nizer/clock control register in MAP-CA memory block. The SdMrckDly and SdMckDly fields control internal delay cir-
cuits that affect the timing of signals going to and from the SDRAM components. They should be adjusted so that setup and
hold requirements of both the SDRAM’s and the MAP-CA are met.
6.4.2 PCI Bus Timing (66MHz)
clk
output delay
output delay
tri-state
output
Vth
Vrl
Vtest
tfval
Vtfall
trval
Vtrise
ton
toff
PCI Output Timing Measurement Conditions
32 Equator Technologies, Inc.
MAP-CA Data Sheet
TABLE 3. Measurement Condition Parameters
Symbol Description Min Max Units
tcycle clock cycle time 15 30 ns
thigh clock high time 6 ns
tlow clock low time 6 ns
clkslew clock slew rate 1.5 4 V/ns
tsu input set up time to clk, bussed signals 3 ns
tsu(ptp) input set up time to clk, point-to-point signals 5 ns
tval clk to signal valid delay, bussed signals 2 6 ns
tval(ptp) clk to signal valid delay, point to point signal 2 6 ns
ton float to active delay 2 ns
toff active to float delay 14 ns
trst reset active time after power stable 1 ms
trst-clk reset active time after clk stable 100 us
trst-off reset active to output float delay 40 ns
Symbol Value Units
Vth 0.6Vcc V
Vtl 0.2Vcc V
Vtest 0.4Vcc V
Vtrise 0.285Vcc V
Vtfall 0.615Vcc V
Vmax 0.4Vcc V
input signal slew rate 1.5 V/ns
clk
input
Vth
Vtl
Vtest Vtest Vmax
Vth
Vtl
Vtest
tsu th
input valid
PCI Input Timing Measurement Conditions
Equator Technologies, Inc. 33
6.4.3 I
2
C Interface Timing
Note:
Symbol Description
Standard Mode Fast Mode
UnitsMin Max Min Max
fscl iic_sck clock frequency 0 100 0 400 kHz
tbuf
bus free time between a stop
and start condition 4.7 1.3 us
thd_sta
hold time (repeated) start
condition. after this period, the
first clock pulse is generated
4.0 0.6 us
tlow low period of the iic_sck clock 4.7 1.3 us
thigh high period of the I2CSCL
clock 4.0 0.6 us
tsu_sta
setup time for a repeated start
condition 4.7 0.6 us
thd_dat data hold time 0 (*1) 0(*1) 0.9(*2) us
tsu_dat data setup time 250 100 (*3) ns
trrise time for iic_sda, iic_sck 1000 20+0.1Cb
(*4) 300 ns
tffall time for iic_sda, iic_sck 300 20+0.1Cb
(*4) 300 ns
tsu_sto setup time for stop condition 4.0 0.6 us
Cb
capacitive load for each bus
line 400 400 pf
tbuf
thd_sta tsu_dt
tlow
thd_dt
tsu_sta
thd_sta
tsu_sto
iic_sda
iic_sck
tr thigh
I2C Timing Diagram
tf
34 Equator Technologies, Inc.
MAP-CA Data Sheet
1. A device must internally provide a hold time of at least 300ns for the iic_sda signal (referred to the Vihmin of the iic_sck
signal) in order to bridge the undefined region of the falling edge of iic_sck.
2. The maximum thd_dat has only to be met if the device does not stretch the low period (tlow) of the iic_sck signal.
3. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tsu_dat of 250ns must be
met. This will automatically be the case if the device does not stretch the low period of the iic_sck signal, it must output the
next data bit to the iic_sda line t_rmax+tsu_dat=1000+250=1250ns (according to the standard-mode I2C-bus specification)
before the iic_sck line is released.
4. Cab = total capacitance of one bus line in pF.
6.4.4 ITU-R BT.656 Interfaces Timing
Symbol Description Min Max Units
fntsc_in ntsc_ina_clk27p frequency 27 +/- 54+/- MHz
tcyc pclk cycle time 18.5 +/- 37 +/- ns
tHinput hold time for video_ina[7:0], from
cross over of rising clock 0ns
tS
input setup time video_in[7:0], to the
cross over of rising clock 4ns
tmaxdelay maximum delay time 6.5 ns
thold output hold time 2 ns
t
S
t
H
t
hold
pclk
ntsc_out_data[7:0]
video_ina[9:0]
ntsc_ina_clk27
ITU-R. BT656 Signal Timing Diagram
ntsc_out_hsync
ntsc_out_vsync
t
maxdelay
Equator Technologies, Inc. 35
Notes: The ITU timing diagram and table includes information for the primary video input port. Secondary video input signals
have indentical timing relationships and values. Primary video input bus video_ina[9:0] includes the byte-wide data bus (bits
7:0), horizontal sync (bit 8) and vertical sync (bit 9).
6.4.5 Transport Channel Interface Timing
Notes: timing diagram and table are relevant to the primary TCI input port. Timing relationships and input setup and hold
times are identical for the secondary TCI input port. The tci_vdac output is not present on the secondary output port, however.
Inputs video_ina[9:0] include tci_data[7:0] (bits 7:0), tci_enable (bit 8) and tci_err_ (bit 9).
Note: 1. Additionally, VLIW core clock frequency must be > 1.5 times tci_clk frequency (parallel mode).
2: Additionally, VLIW core clock frequency must be > 6/32 times tci_clk frequency (serial mode)
3: for correct tci audio clock counter operation. Audio clock is audioclk_out, coming on on-chip PLL.
4: for correct tci video clock counters operation. Video clock is pclk, driving ntsc_out, PLLs, etc.
TABLE 4.
Symbol Description Min Max Units Note
ftci_clk_p parallel mode TCI clock frequency 30 MHz 1
tHhold time for video_ina[9:0], tci_sync 1 ns
tSsetup time for video_ina[9:0], tci_sync 4 ns
tClk2Q output hold time 2.5 ns 2
fcore/faudio ratio, VLIW core clock/audio clock freq. >4 3
fcore/fvideo ratio, VLIW core clock/video clock freq. >4 4
tci_clk
video_ina[9:0]
tci_sync
pclk
TCI Signal Diagram
t
H
t
S
tci_vdac
t
Clk2Q
36 Equator Technologies, Inc.
MAP-CA Data Sheet
6.4.6 IEC958 Interface Timing
6.4.7 I2S Interface Timing
Symbol Description Min Max Units
tClk2Q output hold time 2.5 ns
audioclk_out
IEC958 Signal Diagram
iec958_out
t
Clk2Q
iis_out_bclk
I2S Output Timing Signal Diagram
iis_out_data[2:0]
t
Clk2Q
iis_out_lr
Equator Technologies, Inc. 37
Symbol Description Min Max Units
tClk2Q output hold time -1 ns
tSS setup time, MAP as bit clock slave 4.5 ns
tHS hold time, MAP as bit clock slave 4.5 ns
tSM setup time, MAP as bit clock master 5 ns
tHM hold time, MAP as bit clock master 5 ns
iis_in_bclk
I2S Input Timing Signal Diagram (MAP as bit clock slave)
iis_in_data, iis_in_lr
t
SS
t
HS
iis_out_bclk
I2S Input Timing Signal Diagram (MAP as bit clock master)
iis_in_data
t
SM
t
HM
38 Equator Technologies, Inc.
MAP-CA Data Sheet
7. Acronyms
Acronyms/names used in the data sheet and their expansion/explanation
Acronyms used in this document
Acronym/name Expansion
DataStreamer High speed DMA engine that operates independent from VLIW core
DRC Display Refresh Controller
DTS Data Transfer Switch - high speed MAP and MAP-CA series internal data bus
I-ALU Integer ALU - performs loads, stores, branches, integer arithmetic, and logical operations.
IG-ALU Integer, Graphics unit - performs integer arithmetic and (partitioned) multimedia operations.
MAP-CA Media Accelerated Processors for Consumer Appliances from Equator Technologies, Inc.
MMU Memory Management Unit
PLC 128-bit Partitioned Local Constant register
PLV 128-bit Partitioned Local Variable register
VLx Co-processor on MAP and MAP-CA series that can accelerate variable length encoding and decoding.