[INTERSIL 1IH5040-1H5051 Family High Level CMOS Analog Gates FEATURES GENERAL DESCRIPTION @ Switches Greater Than 20Vpp Signals With +15V Supplies The 1H5040 family of solid state analog gates are designed Quiescent Current Less Than 1A using an improved, high voltage CMOS monolithic tech- Overvoltage Protection to +25V nology. These devices provide ease-of-use and perform: e k-Before-Mak Senti 00 ance advantages not previously available from solid state Traical ore- Make Switching tots 200 nsec, ton 300 nsec switches. This improved CMOS technology provides input T2L, DTL, CMOS, PMOS Compatible overvoltage capability to +25 volts without damage to the Non.Latching With Supply Turn-Off device, and destructive latch-up of solid state analog gates has been eliminated. Early CMOS gates were destroyed when power supplies were removed with an input signal present. New DPDT & 4PST Configurations The 1H5040 CMOS technology has eliminated this serious Complete Monolithic Construction systems problem. tH5040 through 1H5047 Key: performance advantages of the 5040 series are TTL. " compatibility and ultra low-power operation. The quies- FUNCTIONAL DIAGRAM cent current requirement is less than 1A. Also designed! y into the 5040 is guaranteed Break-Before-Make switching, which is accomplished by extending the ton, time (300 nsec 1 Low rps{on) 358 TYP.) so that it exceeds tors time (200 nsec TYP.). This insures that an ON channel will be turned OFF before an r] OFF channel can turn ON. This eliminates the need for ex- Qa ternal logic required to avoid channel to channel shorting L during switching. x a) Os Many of the 5040 series improve upon and are pin-for-pin 1 1 and electrical replacements for other solid state switches. FUNCTIONAL DESCRIPTION PIN/FUNCTIONAL INTERSIL EQUIVALENT PART NO. TYPE. DS(on) (Note 1) -1H5040 SPST 752 1H5041 Dual SPST 762 . 1H5042 SPDT 762 DG 188AA/BA 1H5043 Dual SPDT 752. DG 191AP/BP 1H5044 DPST 752. 1H5045 Dual: DPST 752. DG 185AP/BP 1H5046 DPDT 752 1H5047 4PST 752 or 1H5048 Dual SPST 352 1H5049 Dual DPST 352 DG 184AP/BP FIGURE 1. TYPICAL DRIVER, GATE 1H5042 1H5050 SPDT 350 DG 187AA/BA 1H5051 Dual SPDT 352 DG 190AP/BP ORDERING INFORMATION NOTE 1, See Switching State diagrams for applicable package iHso40 JE equivalency. cH be Pin Ceramic DIP (Special Order Only) Pin and functional equivalent monolithic versions of the DG181, FE 16-Pin Flatpak DG182, DG187 and DG188 are available. See data sheet for JE 16-Pin CERDIP this and also 1H181 to 1H191. PE t6-Pin Plastic DIP TW TO-99 Metal Can (1H5041/2, 1H5044, 1H5048, 1H5050 Only) Temperature Range M Military -S6C to +425C C Commercial 0C to +70C Basic Part Number 3-1031H5040-1H5051 Family (INTERSIL ABSOLUTE MAXIMUM RATINGS . vtevo <33V Current (Any Terminal) ............--- oo <30mA Vt Vp <30V Storage Temperature ............. -65Ct10+150 C Vp-V- <30V Operating Temperature .......... . -55C to +125C Vp-Vs < 429V Power Dissipation.......... ee eee 450mW VL-V7 <33V (All Leads Soldered to a P.C, Board) VL-VIN <30V Derate 6mW/C Above 70C VL-GND <20V Lead Temperature (Sotdering, 10 sec).......... 300C Vin-GND <20V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (@ 25C, v*= +15, v~ =-15V,VL=+5V) MIN./MAX, LIMITS PER CHANNEL MILITARY COMMERCIAL SYMBOL | CHARACTERISTIC 56C +25C +125C 0 +25C +70C UNITS TEST CONDITIONS WNION) input Logic Current 1 1 1 1 1 1 BA Vin = 24V Note 1 UN(OFF) Input Logic Current 1 1 1 1 1 1 uA Vin = 0.8 V Note 1 'DS(on) | Drain-Source On 75(35) 75135) 150160) BO 145) 80145) 130 (a5) a 11H5048 Thru 1H5051) ts = TMA, Resistance : VaANALOG 710 V to 10 Arosion) | Channel to Channel 28115) 25 115} 25115) 30(15) 3015} 30118) a (1H5048 thru JH50511 Roston) Match ; Ig (Each Channel} = 1 mA, VANALOG | Min. Anatog Signal 11(210) 2191210) 214(210) #101210) 10{2 10} *10(+10} v Ig = 10 mA (1H5048 thru 1H5051) Handting Capability 'ptoFe) Switch OFF Leakage my) wt) 100(100) 515) 5{5) 100(100) nA VANALOG = -10 v to +10.V Current (1H5048 thru {H5051 loton Switch On Leakage 212) 212) 200(200) 10(10} 10110) | 1001200) aA Vp Vg 2-10 Vt0+10V +lsiqn? Current {145048 thru 1HS051) ton Switch ON Time $00(250! 500(3007 ns RUT TK VanaraG * 10V 10 +10 V See Fig. A toft Switch OFF Time 2801150) 2501150) ns RL= UK, Vanacog = 104 10 +10 V See Fig. A {15048 thru [H5051) una) Charge Injection 15 (10) 20 (10) mv See Fig. 8 . (1H6048 thru 1H5051) orRR Min. Off isolation 54 50 08 f= 1MH2, Ry = 10082, Cy SpF + Rejection Ratio See Fig. C Va + Power Supply 1 4 10 190 10 100 wd Quiescent Current 'q Power Supply 1 1 10 10 10 100 BA vt eHISV,.Vo 15 V. Vy = 45 Quiescent Current VL FeV VLa +5 V Supply 1 1 10 10 10 100 BA Switch Duty Cycle + 10% Quiescent Current t Gna Supply 1 1 10 10 10 100 yA GND Quiescent Current cCRR Min. Channel, to 54 50 a8 One Channel Off; Any Other Channel Cross Channel! Switches as per Fig. E Coupting Rejection Ratio FIG. A FIG. B FIG. C ANALOG INPUT 10V ANALOG INPUT TL LOGIC INPUT T) r (NOTE TP Ta Locic Logic INPUT Vout INPUT rope: 1kD mT NOTE 1: Some channels are turned on by high 1 jogic inputs and other channels are turned on by low 0 inputs; however 0.8V to 2.4V describes the min. range for switching property. Refer to logic diagrams to see absolute value of logic input required to produce ON or OFF state. 3-1041H5040-1H5051 Family INTERSIL 'DSton) 8 VANALOG SIGNAL 100 TYPICAL ELECTRICAL CHARACTERISTICS (Per Channel) POWER CHARGE INJECTION vs VanacoG (SEE FIG. B) Cy = 10,000pF "DS(on) S SUPPLY VOLTAGE FREQUENCY (Hz) 40 Hybrid 38 80 - w z g z a yy wn bt a a & S20 40 2 o 45 20 10 Ig = mA 0 @: 16V 0 0 19 -5 -25 0 25 5 75-75 10 -10-7 -5 -25 0 25 $ 75 10 -10-75 5 -26 0 25 5 75 10 Vana_oc V! VANALOG {V) VANALOG !V) FIGURE D CROSS COUPLING C REJECTION vs FREQUENCY OFF | 120 CHANNEL ~~ j = : | rc v 100 | | our _ { 100K S a0 | R | | 2g 60 wu g | ws SL ot 2 LeveLs otf )p-- 20 nee ee SWITCHED L CHANNEL a cern = 20.06 2200rWpP 4 imvVop) ' 10 100 1k TOK 100k IM FREQUENCY {Hz} FIGURE E OFF ISOLATION vs FREQUENCY -120 nr Tr 190 F-+3 oot tee ee bed 2Vvpp sin : @ imc gob... pie ee a g 4 g = = x ooh se ss cot Rs OFF STATE a : DEPENDS ON PART t PF aopeie ee eb fe ee te vi bo Out 20 pee we EL et ng Vout (mpp "T 19082 3 OIRR 20106 SE op ' tHe 10Hz 100H: tk 10k 100k 1M > FIGURE F POWER SUPPLY QUIESCENT CURRENT vs LOGIC FREQUENCY RATE < 1000 3 - * = & S a 100 = 3 ir x F w iF - + +o a Zz a 3 i a i iG Dope 31 peop 1 10 100 tk 10k 100k LOGIC FREQUENCY @10% DUTY CYCLE (Hz) FIGURE G LOGIC IN ever al Loss J L poke 3-1051H5040-1H5051 Family INTERSIL FOR INTERFACING WITH T2L. OPEN COLLECTOR LOGIC. mato tLoaic I | | = LV ITLGATE TYP. EXAMPLE FOR +15V CASE SHOWN FOR USE WITH CMOS LOGIC. poo a7 10% | } | l | - | | 4d ' ! GND vt | t . | | In GND v- | { | y, > I I | | | | CMOS GATE v . jeMoscare J om Wve vt > 5V OV > Vv- 2-15V LOGIC INTERFACING IN ad L LOGIC ~ vt 0 *15V OR Voc iv) TERMINAL! ; 1OK22 3-1061H5040-1H5051 Family INTERSIL THEORY OF OPERATION A. FLOATING BODY CMOS STRUCTURE In a conventional C-MOS structure, the body of the n channel device is tied to the negative supply, thus forming a reverse biased diode between the drain/source and the body (Fig. J}. Under certain conditions this diode can become forward biased; for example, if the supplies are off {at ground) and a negative input is applied to the drain. This can have serious consequences for two reasons. Firstly, the diode has no current limiting and if excessive current flows, the circuit may be permanently damaged. Secondly, this diode forms part of a parasitic SCR in the conventional C-MOS structure. Forward biasing the diode causes the SCR to turn on, giving rise to a latch-up condition. Intersils improved C-MOS process incorporates an addi- tional diode in series with the body (Fig. K). The cathode of this diode is then tied to V+, thus effectively floating the body. The inclusion of this diode not only blocks the excessive current path, but also prevents the SCR from turning on. B. OVERVOLTAGE PROTECTION The floating body construction inherently provides over- voltage protection. {n the conventionalC-MOS process, the body of all N-channel FETs is tied to the most negative power supply and the body of all P-channel devices to the most positive supply (i. e., 15V). Thus, for an overvoltage spike of > +15V, a forward bias condition exists between drain and body of the MOSFET. For example, in Fig. J if the analog signal input is more negative than -15V, the drain to body of the N-channel FET is forward biased and destruction of the device can result. Now by floating the body, using diode D1, the drain to body of the MOSFET is still forward biased, but D1 is reversed biased so no current flows (up to the breakdown of D1 which is => 40V). Thus, negative excursions of the analog signal can go up to.a maximum of -25V. When the signal goes positive (> +15V, D1 is forward biased, but now the drain to body junction is reversed for the. N-channel FET; this allows the signal to go to a maximum of +25V with no appreciable current flow. While the explanation above has been restricted to N-channel devices, the same applies to P-channel FETs and the construction is as shown in Fig. L. Fig. L describes an output stage showing the paralleling of an N and P channel to linearize the rpsion) with signal input. The presence of diodes D1 and D2 effectively floats the bodies and provides over voltage protection to a maximum of +25V. -15V P.MATERIAL ANALOG FIGURE J ANALOG Vout RL Vout AL SIGNAL O INPUT FIGURE K yt ot ANALOG 8 SIGNAL O IN o $s Mu FROM _T ORIVER v2 . FIGURE L Vout 3-1071H5040-1H5051 Family INVERSIL APPLICATIONS IMPROVED SAMPLE & HOLD USING 1H5043 OUTPUT 10,000 pF POLYSTYRENE LOGIC INPUT +3V = > SAMPLE MODE OV => HOLD MODE USING THE CMOS SWITCH TO DRIVE AN R/2R LADDER NETWORK (2 LEGS) *VANALOG acim Loic STROBE ~VANALOG EXAMPLE: If ~Vanacog 7 ~1OVO0C and *Vanarog = t10vOC then Ladder Legs are switched between + 10VDC, depending upon state of Logic Strobe. ra *VANALOG Locic STROBE eTC. . DIGITALLY TUNED LOW POWER ACTIVE FILTER 0KS2 100kR 10,000 pF HI PASS BANDPASS OUTPUT OuTPUT : HO an2t bC) 100kS2 Gi ae Lt [43 * yo0Ks2 ei et sores TK? 6OCKs2 3 B8KI2 R Fa Constant gain, constant Q, variable frequency filter which provides simultaneous Lowpass, Bandpass, and Highpass outputs. With the component values shown, center frequency will be 235Hz and 23.5Hz for high and low logic inputs respectively, Q = 100, and Gain = 100, fry = Center Frequency = 2n AC STROBE 3-1081H5040-1H5051 Family INTERSIL SWITCHING STATE DIAGRAMS ) SWITCH STATES (OUTLINE DWG (OUTLINE DWGS ARE FOR LOGIC 1 INPUT FE-2) DE, JE, PE) (OUTLINE DWG TO-100) vO ye ve ve a a SPST fio g 1H5040 (rpsion) < 752) sot oe so oo ' ! mop! note bn ye Gno v be bv GND ve T OUAL SPST wu ve ve ee 1H5041 (rpsion) < 752) fu , fe $1 Oporto 01 5s ob ors 4-001 1m bof > -! mn, obo > motte -p--) mot > ott _etet oo, 5) of oy 0; chy gr & ve te GND v vy vt SPDT LL ve Pa Rn 1H5042 (ros(on) < 759) Fr 9 s) of oO 51 of; ort to oy ot} of vt 0 02 520 al + f+0 D2 i t wort {p> -4 wots ge be GND vo n 5" GND vw (0G191 EQUIVALENT} DUAL SPDT ne v nN 1H5043 (rpsion) < 752) Sy 1 us 84 $83 by Int Ny INQ S2 'N2 Sa S82 & Se Ca vO Guo vw vu ve DPST ve . ue fu 1H5044 (rps(on) < 782) Je 2 8) fp or th oy a Kho ! 1 $07} _o+ 4 0, 52 Of} ot & f o woh Op -! noti: " 12 ee or GND vw (DG185 EQUIVALENT} DUAL DPST Mu y 5g 12 WW 1H5045 (rpsi(on) < 759) Sy 3 ea 83 83 Dy Ny Ny (Ng 82 ing Sa 82 Db; 3-1091H5040-IH5051 Family INTERSIL SWITCHING STATE DIAGRAMS (Cont.) SWITCH STATES ARE FOR LOGIC t" INPUT FLAT PACKAGE (FD) DIP (DE) PACKAGE TO-100 ML vt M. ve 12 YW 145047 (rpg (ON) <750) oy DPDT 31 9) IH6046 (rps (ON) <752) 5 n Sp Dy 2 2 $3 Dg 83 Oy * Da $4 Oa N GND w GND ov- 4PsT 1H5049 (rpg (ON) <352) Ss S3 ins IN? 82 Sa Dg D3 Oq DUAL SPST Me wt 116048 (rps (ON) <352) Jeo fs $1 O--____or to Dy 8) OP OTE E00 4 Obeof > 4 ws, Obof >? m2 OF} 1 2 0b} 820-4 27 52 2p ott} oo; o o GND vw $3 ao GNO vw (DG184 EQUIVALENT! DUAL DPST 7 8. 2 INp 1H5051 (rpg (ON) <350) & IND Sa GND vw vt (DG187 EQUIVALENT) SPDT ve vt Qu Pn 1H6050 (rpg (ON) <35Q} fo Ps $s: of 01 5-4o 0, Sop ore fio os t Sp of} a} vf S2 o-+ 0 v to Or sb ps not D>! BF Te ono ve bf GND ve (DG190 EQUIVALENT) DUAL SPDT oye 12 W St 1 53 Dy INy IND Sz 02 3-110