CMOS 32-BIT SINGLE CHIP MICROCOMPUTER S1C33401 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2005, All rights reserved. Configuration of product number Devices S1 C 33209 F 00E1 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 33000 H2 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx : Emulation memory for external ROM Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Corresponding model number 33L01: for S1C33L01 Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products S1C33401 Technical Manual I S1C33401 SPECIFICATIONS I I.1 Overview Overview I.2 Block Diagram Block I.3 Pin Description Pin I.4 Power Supply Power I.5 Memory Map MAP I.6 Electrical Characteristics E char I.7 Basic External Wiring Diagram Wiring I.8 Changes from Core/Basic Peripheral Functions Change I.9 Precautions on Mounting Mount II C33 ADV CORE BLOCK II II.1 Preface Preface II.2 CPU CPU II.3 Clock Management Unit (CMU) CMU II.4 High-Speed Bus Control Unit (HBCU) HBCU II.5 Memory Management Unit (MMU) MMU II.6 Cache Control Unit (CCU) CCU II.7 Debug Unit (DBG) DBG III C33 ADV BUS BLOCK III III.1 Preface Preface III.2 Basic Bus Control Unit (BBCU) BBCU III.3 Extended Bus Control Unit (EBCU) EBCU III.4 High-Speed DMA (HSDMA) HSDMA III.5 Intelligent DMA (IDMA) IDMA IV C33 ADV BASIC PERIPHERAL BLOCK IV IV.1 Preface Preface IV.2 Interrupt Controller (ITC) ITC IV.3 OSC3 Oscillator Circuit, PLL, and SSCG OSC3 IV.4 Prescaler (PSC) PSC IV.5 8-Bit Timers (T8) T8 IV.6 16-Bit Timers (T16) T16 IV.7 Watchdog Timer (WDT) WDT IV.8 Serial Interface (SIO) SIO IV.9 Card Interface (CARD) CARD IV.10 General-Purpose I/O Ports (PORT) PORT IV.11 A/D Converter (ADC) ADC V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK V V.1 Preface Preface V.2 Area 6 Settings and Macro Control Register Area 6 V.3 Chip ID ChipID V.4 Pin Control Registers PinCtrl V.5 Real-Time Clock (RTC) RTC Appendix I/O Map APP I/Omap PREFACE Application This manual describes the hardware functions and control registers of the S1C33401 or Seiko Epson's RISC-type 32-bit microcomputer, and precautions to observe when designing the application system for the microcomputer. Since this manual is written for those who design applications and circuits, knowledge of embedded-type microcomputers and the functionality and control of general peripheral circuits is required to understand the contents of this manual. Organization of the Manual I. S1C33401 Specifications This chapter outlines the S1C33401 and describes the pin functions, electrical characteristics, and inherent specifications of the S1C33401 that differ from standard functions of the C33 ADV core/basic peripheral circuits. Also noise protection and other precautions to be taken when mounting the chip on the circuit board are included. II. C33 ADV Core Block The C33 ADV core block is built around the CPU and incorporates various modules to control memory access by the CPU, as listed below. This chapter describes each module. The descriptions given apply to all types of S1C33 microcomputers using the C33 ADV macro. * CPU * Clock Management Unit (CMU) * High-speed Bus Control Unit (HBCU) * Memory Management Unit (MMU) * Cache Control Unit (CCU) * Debug Unit (DBG) III. C33 ADV Bus Block The C33 ADV bus block consists of several modules to control access to the actual internal/external devices, as listed below. This chapter describes each module. Since the descriptions given apply to all types of S1C33 microcomputers using the C33 ADV macro, not all contents may be included in the S1C33401 due to the limited number of pins available, etc. For details of these differences, see Section I.8, "Changes from Core/ Basic Peripheral Functions." * Basic Bus Control Unit (BBCU) * Extended Bus Control Unit (EBCU) * High-speed DMA Controller (HSDMA) * Intelligent DMA Controller (IDMA) IV. C33 ADV Basic Peripheral Block The C33 ADV macro has the following built-in peripheral functions as the basic peripheral block. This chapter describes each function. Since the descriptions given apply to all types of S1C33 microcomputers using the C33 ADV macro, not all contents may be included in the S1C33401 due to the limited number of pins available, etc. For details of these differences, see Section I.8, "Changes from Core/Basic Peripheral Functions." * Interrupt Controller (ITC) * OSC3 Oscillator Circuit, PLL, and SSCG * Prescaler (PSC) * 8-bit Timer (T8) * 16-bit Timer (T16) * Watchdog Timer (WDT) * Serial Interface with FIFO (SIO) * Card Interface (CARD) * Input/Output Ports (PORT) * A/D Converter (ADC) S1C33401 TECHNICAL MANUAL EPSON i PREFACE V. S1C33401 Area 6 Extended Peripheral Block Area 6 of the S1C33401 incorporates the following peripheral functions that are not included in the C33 ADV macro. This chapter describes each function. * Chip ID Register * Pin Control Registers * Real Time Clock (RTC) and OSC1 Oscillator Circuit (OSC1) Appendix Provides a list of control registers built into the S1C33401. Notational Conventions for Control Bits and Addresses This manual describes some control bits as follows: Example: 16-bit timer RUN/STOP control bits PRUNx (D0/0x48186 + 8*x) `x' in this example represents a timer number (0 to 9). Timer 0 to timer 9 have control bits for each timer that have the same functions as other timers. This manual uses `x' to describe two or more control bits (or addresses) in a bit name (or an expression). Therefore, `x' should be substituted with 0 to 9 in this example to obtain the actual bit names and addresses. Timer 0: PRUN0 (D0/0x48186) 0x48186 + 8 x 0 = 0x48186 Timer 1: PRUN1 (D0/0x4818E) 0x48186 + 8 x 1 = 0x4818E Timer 2: PRUN2 (D0/0x48196) Timer 3: PRUN3 (D0/0x4819E) Timer 4: PRUN4 (D0/0x481A6) Timer 5: PRUN5 (D0/0x481AE) Timer 6: PRUN4 (D0/0x481B6) Timer 7: PRUN7 (D0/0x481BE) Timer 8: PRUN8 (D0/0x481C6) Timer 9: PRUN9 (D0/0x481CE) `x' is used for not only timer numbers, but also memory block numbers, A/D converter channel numbers and others. ii EPSON S1C33401 TECHNICAL MANUAL CONTENTS CONTENTS I S1C33401 SPECIFICATIONS I.1 Overview.....................................................................................................................I-1-1 I.2 Block Diagram ...........................................................................................................I-2-1 I.3 Pin Description ..........................................................................................................I-3-1 I.3.1 Pin Arrangement .......................................................................................................... I-3-1 I.3.1.1 QFP Package Pin Arrangement (S1C33401F00A) ........................................ I-3-1 I.3.1.2 PFBGA Package Pin Arrangement (S1C33401B00A) ................................... I-3-2 I.3.2 Pin Functions ............................................................................................................... I-3-3 I.3.3 Switching Over the Multiplexed Pin Functions ............................................................. I-3-8 I.3.3.1 Pin Function Select Bits ................................................................................. I-3-8 I.3.3.2 List of Port Function Select Registers ........................................................... I-3-11 0x40360: P00-P03 Port Function Select Register (pP0_03_CFP) ......................................... I-3-12 0x40361: P04-P07 Port Function Select Register (pP0_47_CFP) ......................................... I-3-13 0x40362: P10-P13 Port Function Select Register (pP1_03_CFP) ......................................... I-3-14 0x40363: P14-P17 Port Function Select Register (pP1_47_CFP) ......................................... I-3-15 0x40364: P20-P23 Port Function Select Register (pP2_03_CFP) ......................................... I-3-16 0x40365: P24-P27 Port Function Select Register (pP2_47_CFP) ......................................... I-3-17 0x40366: P30-P33 Port Function Select Register (pP3_03_CFP) ......................................... I-3-18 0x40368: P40-P43 Port Function Select Register (pP4_03_CFP) ......................................... I-3-19 0x40369: P44-P47 Port Function Select Register (pP4_47_CFP) ......................................... I-3-20 0x4036A: P50-P53 Port Function Select Register (pP5_03_CFP) ......................................... I-3-21 0x4036B: P54-P56 Port Function Select Register (pP5_46_CFP) ......................................... I-3-22 0x4036C: P60-P63 Port Function Select Register (pP6_03_CFP) ......................................... I-3-23 0x4036D: P64-P67 Port Function Select Register (pP6_47_CFP) ......................................... I-3-24 0x4036E: P70-P73 Port Function Select Register (pP7_03_CFP) ......................................... I-3-25 0x40370: P80-P83 Port Function Select Register (pP8_03_CFP) ......................................... I-3-26 0x40371: P84-P87 Port Function Select Register (pP8_47_CFP) ......................................... I-3-27 0x40372: P90-P93 Port Function Select Register (pP9_03_CFP) ......................................... I-3-28 0x40373: P94-P97 Port Function Select Register (pP9_47_CFP) ......................................... I-3-29 I.3.4 Input/Output Cells and Input/Output Characteristics ................................................... I-3-30 I.3.5 Package ...................................................................................................................... I-3-33 I.3.5.1 QFP20-184pin Package ................................................................................ I-3-33 I.3.5.2 PFBGA-160pin Package ............................................................................... I-3-34 I.3.5.3 Thermal Resistance of the Package ............................................................. I-3-35 I.4 Power Supply .............................................................................................................I-4-1 I.4.1 I.4.2 I.4.3 I.4.4 I.4.5 I.4.6 I.4.7 I.4.8 Power Supply Pins ....................................................................................................... I-4-1 Operating Voltage (VDD, VSS) ........................................................................................ I-4-2 Power Supply for PLL (PLLVDD, PLLVSS) ...................................................................... I-4-2 Power Supply for I/O Interface (VDDE) .......................................................................... I-4-2 Power Supply for T16 PWM Output (P1x) Ports (TMVDD) ............................................ I-4-2 Power Supply for Analog Circuits (AVDD) ..................................................................... I-4-2 Power Supply for RTC (RTCVDD) ................................................................................. I-4-2 Precautions on Power Supply ...................................................................................... I-4-3 S1C33401 TECHNICAL MANUAL EPSON iii CONTENTS I.5 Memory Map ..............................................................................................................I-5-1 I.5.1 I.5.2 I.5.3 I.5.4 I.5.5 I.5.6 I.5.7 I.5.8 ROM and Boot Address ............................................................................................... I-5-2 Area 0 (A0RAM) ........................................................................................................... I-5-2 Area 1 (Internal I/O) ..................................................................................................... I-5-3 Area 2 (Debug Area) .................................................................................................... I-5-3 Area 3 (A3RAM) ........................................................................................................... I-5-3 Area 6 (Extended I/O) .................................................................................................. I-5-3 External Memory Area ................................................................................................. I-5-4 Limitations on Areas 0 to 6........................................................................................... I-5-4 I.6 Electrical Characteristics..........................................................................................I-6-1 I.6.1 I.6.2 I.6.3 I.6.4 I.6.5 I.6.6 I.6.7 I.6.8 Absolute Maximum Rating ........................................................................................... I-6-1 Recommended Operating Conditions .......................................................................... I-6-1 DC Characteristics ....................................................................................................... I-6-2 Current Consumption ................................................................................................... I-6-3 A/D Converter Characteristics...................................................................................... I-6-4 Oscillation Characteristics ............................................................................................ I-6-5 PLL Characteristics ...................................................................................................... I-6-6 AC Characteristics ....................................................................................................... I-6-7 I.6.8.1 Symbol Description ........................................................................................ I-6-7 I.6.8.2 AC Characteristics Measurement Condition .................................................. I-6-7 I.6.8.3 BBCU AC Characteristic Tables ..................................................................... I-6-8 I.6.8.4 BBCU AC Characteristic Timing Charts......................................................... I-6-9 I.6.8.5 SDRAM Interface AC Characteristics ........................................................... I-6-13 I.7 Basic External Wiring Diagram ................................................................................I-7-1 I.8 Changes from Core/Basic Peripheral Functions ....................................................I-8-1 I.8.1 Limitations on the BBCU and EBCU ............................................................................ I-8-1 I.8.2 Limitations on the A/D Converter ................................................................................. I-8-2 I.9 Precautions on Mounting .........................................................................................I-9-1 iv EPSON S1C33401 TECHNICAL MANUAL CONTENTS II C33 ADV CORE BLOCK II.1 Preface...................................................................................................................... II-1-1 II.2 CPU ........................................................................................................................... II-2-1 II.2.1 II.2.2 II.2.3 II.2.4 Features ...................................................................................................................... II-2-1 Registers ..................................................................................................................... II-2-3 Instruction Set ............................................................................................................. II-2-4 Address Space and Logical to Physical Address Translation ..............................................II-2-8 II.2.4.1 Overview ....................................................................................................... II-2-8 II.2.4.2 Address Processing ...................................................................................... II-2-9 II.2.4.3 Block Processing ......................................................................................... II-2-11 II.2.4.4 ASID Processing .......................................................................................... II-2-12 II.2.4.5 MMU Processing (Address Translation) ....................................................... II-2-12 II.2.4.6 Mirror Processing ......................................................................................... II-2-13 II.2.4.7 Area Processing .......................................................................................... II-2-13 II.3 Clock Management Unit (CMU) .............................................................................. II-3-1 II.3.1 Overview of the CMU .................................................................................................. II-3-1 II.3.2 Reset Input and Initial Reset ....................................................................................... II-3-2 II.3.2.1 Initial Reset Pins ........................................................................................... II-3-2 II.3.2.2 Cold Reset and Hot Reset ............................................................................ II-3-2 II.3.2.3 Power-on Reset ............................................................................................ II-3-3 II.3.2.4 Boot Address ................................................................................................ II-3-3 II.3.2.5 Precautions to be Taken during Initial Reset ................................................. II-3-4 II.3.3 NMI Input .................................................................................................................... II-3-5 II.3.3.1 NMI Detection Mode ..................................................................................... II-3-5 II.3.3.2 NMI Flag ....................................................................................................... II-3-5 II.3.4 Selecting the System Clock Source ............................................................................ II-3-6 II.3.5 Controlling the Oscillator Circuit .................................................................................. II-3-7 II.3.6 Controlling the PLL...................................................................................................... II-3-8 II.3.6.1 On/Off Control of the PLL ............................................................................. II-3-8 II.3.6.2 Setting the Frequency Multiplication Rate .................................................... II-3-8 II.3.6.3 Other PLL Settings ....................................................................................... II-3-9 II.3.7 Control of the SSCG .................................................................................................. II-3-11 II.3.7.1 Turning the SSCG On/Off ............................................................................ II-3-11 II.3.7.2 Setting SS Modulation Parameters .............................................................. II-3-12 II.3.8 Setting the Core System Clock (CCLK) ..................................................................... II-3-13 II.3.9 Setting the Peripheral Circuit Clock (PCLK) ............................................................... II-3-14 II.3.10 Setting the External Clock Output (CMU_CLK) ....................................................... II-3-15 II.3.11 Controlling Clock Supply .......................................................................................... II-3-16 II.3.11.1 Software Control of Clock Supply .............................................................. II-3-16 II.3.11.2 Automatic Control of Clock Supply ............................................................ II-3-17 II.3.12 Standby Modes ........................................................................................................ II-3-18 II.3.12.1 II.3.12.2 II.3.12.3 II.3.12.4 HALT Mode ................................................................................................ II-3-18 HALT2 Mode .............................................................................................. II-3-18 SLEEP Mode ............................................................................................. II-3-18 Precautions ................................................................................................ II-3-20 S1C33401 TECHNICAL MANUAL EPSON v CONTENTS II.3.13 Clock Setup Procedure ............................................................................................ II-3-21 II.3.13.1 Changing the Clock Source from OSC3 to PLL ......................................... II-3-21 II.3.13.2 Changing the Clock Source from PLL to OSC3, then Turning Off the PLL ...................................................................... II-3-22 II.3.13.3 Changing the Clock Source from OSC3 or PLL to OSC1, then Turning Off OSC3 and PLL .......................................................... II-3-23 II.3.13.4 Changing the Clock Source from OSC1 to OSC3 ..................................... II-3-24 II.3.13.5 Changing the Clock Source from OSC1 to PLL ......................................... II-3-25 II.3.13.6 Turning Off OSC3 during SLEEP ............................................................... II-3-26 II.3.13.7 SLEEP Keeping Oscillation On (without Clock Change) ........................... II-3-27 II.3.13.8 HALT/HALT2 .............................................................................................. II-3-28 II.3.14 Power-Down Control ................................................................................................ II-3-29 II.3.15 Details of Control Registers ..................................................................................... II-3-30 0x40180: Peripheral Clock Control Register 1 (pCMU1_CLKCNTL_0) ...................................II-3-31 0x40181: Peripheral Clock Control Register 2 (pCMU1_CLKCNTL_1) ...................................II-3-32 0x40184: PLL Control Register 1 (pCMU1_PLL_CNTL0) .......................................................II-3-33 0x40185: PLL Control Register 2 (pCMU1_PLL_CNTL1) .......................................................II-3-34 0x40186: PLL Control Register 3 (pCMU1_PLL_CNTL2) .......................................................II-3-35 0x40187: SS Macro Control Register 1 (pCMU1_SS_CNTL0) ...............................................II-3-36 0x40188: SS Macro Control Register 2 (pCMU1_SS_CNTL1) ...............................................II-3-37 0x48360: Core System Clock Control Register (pCMU2_CNTL_CORE) ................................II-3-38 0x48362: Core System Clock On/Off Register (pCMU2_SET)................................................II-3-40 0x48364: Core System Clock Automatic Control Register (pCMU2_AUTO) ...........................II-3-41 0x48366: Peripheral and External Clock Output Control Register (pCMU2_CNTL_PERI) .....II-3-42 0x48368: Clock Option Register (pCMU2_OPT) .....................................................................II-3-43 0x4836A: NMI Flag Register (pCMU2_NMI_FLAG) ................................................................II-3-45 0x4836C: NMI Mode Register (pCMU2_NMI_MODE) ............................................................II-3-46 0x4836E: Clock Control Protect Register (pCMU2_PROTECT)..............................................II-3-47 0x48370: CCLK System Peripheral Clock On/Off Register (pCMU2_CCLK_PERI)................II-3-48 0x48372: CCLK System Peripheral Clock Automatic Control Register (pCMU2_AUTO_CCLK_PERI) ..........................................................................II-3-50 II.3.16 Precautions .............................................................................................................. II-3-52 II.4 High-Speed Bus Control Unit (HBCU) ......................................................................... II-4-1 II.4.1 Overview of the HBCU ............................................................................................... II-4-1 II.4.2 Outline of Address Processing .................................................................................... II-4-2 II.4.3 Managing the Address Space ..................................................................................... II-4-4 II.4.3.1 Contents of Individual Block Settings............................................................ II-4-5 II.4.3.2 Settings for the Entire Address Space .......................................................... II-4-6 II.4.4 Bus Access ................................................................................................................. II-4-7 II.4.4.1 Cache Access ............................................................................................... II-4-7 II.4.4.2 External Memory Access .............................................................................. II-4-7 II.4.4.3 Area 0 Internal Memory Access ................................................................... II-4-7 II.4.5 ASID and Multiple Virtual Spaces ............................................................................... II-4-8 II.4.6 Address ASID and Mirror Processing ......................................................................... II-4-9 II.4.7 Details of Control Registers ....................................................................................... II-4-11 0x48300: Address Control Register (pHBCU_ADR_CNT) ......................................................II-4-12 0x48302-0x48310: Block x Configuration Registers (pHBCU_BLKx) .....................................II-4-13 0x48312: ASID Setup Register (pHBCU_ASID_SETUP) ........................................................II-4-15 0x48314: Logical ASID Setup Register (pHBCU_LOGIC_ASID) ............................................II-4-16 II.4.8 Precautions ................................................................................................................ II-4-17 vi EPSON S1C33401 TECHNICAL MANUAL CONTENTS II.5 Memory Management Unit (MMU) .......................................................................... II-5-1 II.5.1 Overview of the MMU .................................................................................................. II-5-1 II.5.2 Logical and Physical Address Spaces ........................................................................ II-5-2 II.5.2.1 Logical Address Space ................................................................................. II-5-2 II.5.2.2 Physical Address Space ............................................................................... II-5-2 II.5.2.3 Relationship between Logical and Physical Address Spaces ....................... II-5-2 II.5.3 Configuration of the MMU ........................................................................................... II-5-4 II.5.3.1 TAG Part and DATA Part ............................................................................... II-5-4 II.5.3.2 LRU ............................................................................................................... II-5-6 II.5.4 Settings and Operation of the MMU ........................................................................... II-5-7 II.5.4.1 Enabling the MMU ........................................................................................ II-5-7 II.5.4.2 Specifying a Page Size ................................................................................. II-5-7 II.5.4.3 ASID Processing .......................................................................................... II-5-7 II.5.4.4 Address Translation....................................................................................... II-5-8 II.5.5 Setting Up the TLB ..................................................................................................... II-5-11 II.5.5.1 Setting Up the TLB ....................................................................................... II-5-11 II.5.5.2 Confirming the Set Content of the TLB ........................................................ II-5-12 II.5.5.3 Flushing the TLB .......................................................................................... II-5-12 II.5.6 MMU Exceptions ........................................................................................................ II-5-13 II.5.6.1 Types of MMU Exceptions ........................................................................... II-5-13 II.5.6.2 MMU Exception Vector Address and Stack Area ......................................... II-5-14 II.5.6.3 Processing when an MMU Exception Occurs .............................................. II-5-14 II.5.7 Details of the Control Registers ................................................................................. II-5-16 0x48320: MMU Control Register (pMMU_CNTL) ....................................................................II-5-17 0x48322: MMU Entry Register (pMMU_ENTRY) ....................................................................II-5-18 0x48324: MMU 4KB Data Address Register (pMMU_ADR_4K) .............................................II-5-19 0x48326: MMU Common Data Address Register (pMMU_ADR_COM)..................................II-5-19 0x48328: MMU TAG Address Register (pMMU_TAD_ADR) ....................................................II-5-20 0x4832A: MMU Page Setting Register (pMMU_PAGE_SETUP).............................................II-5-21 0x4832C: TLB Control Register (pMMU_TLB_CNTL) .............................................................II-5-23 0x4832E: MMU Exception Status Register (pMMU_EXCP_STAT) .........................................II-5-25 0x48330: MMU Exception Address Register 1 (pMMU_EXP_ADR) .......................................II-5-27 0x48332: MMU Exception Address Register 2 ........................................................................II-5-27 0x48334: MMU LRU Register (pMMU_LRU) ...........................................................................II-5-28 II.5.8 Precautions ................................................................................................................ II-5-29 II.6 Cache Control Unit (CCU) ....................................................................................... II-6-1 II.6.1 Overview of the CCU .................................................................................................. II-6-1 II.6.2 Configuration of the Cache ......................................................................................... II-6-2 II.6.2.1 TAG Part and DATA Part ............................................................................... II-6-2 II.6.2.2 LRU Part ....................................................................................................... II-6-2 II.6.3 Settings and Operation of the Cache .......................................................................... II-6-3 II.6.3.1 Enabling the Cache....................................................................................... II-6-3 II.6.3.2 Address Comparison and Cache Hit/Miss .................................................... II-6-3 II.6.3.3 Read Operation ............................................................................................ II-6-5 II.6.3.4 Write Operation ............................................................................................. II-6-5 II.6.3.5 Flush ............................................................................................................. II-6-6 II.6.3.6 Setting Up the Cache .................................................................................... II-6-7 II.6.3.7 Write-back in Software .................................................................................. II-6-8 II.6.4 Lock Function .............................................................................................................. II-6-9 II.6.5 Lock for Interrupt Processing ..................................................................................... II-6-10 II.6.6 Consistency of the Cache Data.................................................................................. II-6-11 S1C33401 TECHNICAL MANUAL EPSON vii CONTENTS II.6.7 Details of Control Registers ....................................................................................... II-6-12 0x48340: Cache Configuration Register (pCCU_SETUP).......................................................II-6-13 0x48342: Cache Way Number Select Register (pCCU_ENTRY) ............................................II-6-14 0x48344: Cache Entry Control Register (pCCU_ENTRY_CNTL) ...........................................II-6-15 0x48346: Cache Control Register (pCCU_CNTL) ...................................................................II-6-16 0x48348: Cache TAG Address Register 1 (pCCU_ADR) ........................................................II-6-19 0x4834A: Cache TAG Address Register 2 ...............................................................................II-6-20 0x4834C: Cache Data Register 1 (pCCU_DATA) ....................................................................II-6-21 0x4834E: Cache Data Register 2 ............................................................................................II-6-21 0x48350: Interrupt Lock Setup Register (pCCU_LOCK) .........................................................II-6-22 0x48352: Cache LRU Register (pCCU_LRU) ..........................................................................II-6-23 II.6.8 Precautions ................................................................................................................ II-6-24 II.7 Debug Unit (DBG) .................................................................................................... II-7-1 II.7.1 II.7.2 II.7.3 II.7.4 Overview of the DBG .................................................................................................. II-7-1 Input/Output Pins of the DBG...................................................................................... II-7-1 Overview of Functions ................................................................................................. II-7-2 Details of Control Registers ........................................................................................ II-7-3 0x402E8: Debug Signal Output Control Write-Protect Register ...............................................II-7-4 0x402EC: Debug Signal Output Control Register.....................................................................II-7-5 II.7.5 Precautions ................................................................................................................. II-7-6 viii EPSON S1C33401 TECHNICAL MANUAL CONTENTS III C33 ADV BUS BLOCK III.1 Preface.....................................................................................................................III-1-1 III.2 Basic Bus Control Unit (BBCU) .............................................................................III-2-1 III.2.1 III.2.2 III.2.3 III.2.4 III.2.5 Overview of the BBCU .............................................................................................. III-2-1 BBCU Pins ................................................................................................................ III-2-2 General Memory Map ............................................................................................... III-2-3 Internal RAM Area (Areas 0 and 3) ........................................................................... III-2-4 Internal I/O and Debug Areas (Areas 1 and 2).......................................................... III-2-5 III.2.5.1 Internal I/O Area (Area 1) ........................................................................... III-2-5 III.2.5.2 Debug Area (Area 2) ................................................................................... III-2-5 III.2.6 External Memory Area (Areas 4 to 22) ..................................................................... III-2-6 III.2.6.1 External Memory Area and Chip Enable .................................................... III-2-6 III.2.6.2 Area 20 and Boot Mode .............................................................................. III-2-6 III.2.6.3 Extended I/O Area ...................................................................................... III-2-6 III.2.6.4 Summary of Programmable External Memory Access Conditions ............. III-2-7 III.2.6.5 Common Condition Settings ....................................................................... III-2-9 III.2.6.6 Per-Area Condition Settings ...................................................................... III-2-10 III.2.7 Connection of External Devices and Bus Operation ................................................ III-2-18 III.2.7.1 Connecting External Devices .................................................................... III-2-18 III.2.7.2 Data Configuration in Memory ................................................................... III-2-19 III.2.7.3 External Bus Operation.............................................................................. III-2-19 III.2.8 BBCU Operating Clock and Bus Clock .................................................................... III-2-22 III.2.8.1 Operating Clock of the BBCU .................................................................... III-2-22 III.2.8.2 Generation of the Bus Clock ...................................................................... III-2-23 III.2.8.3 External Output of the Bus Clock ............................................................... III-2-23 III.2.9 Bus Access Timing Chart ......................................................................................... III-2-24 III.2.9.1 SRAM Read/Write Timing (with no External WAIT) ................................... III-2-24 III.2.9.2 SRAM Read/Write Timing (with External WAIT) ........................................ III-2-31 III.2.9.3 Burst ROM Page Read Timing ................................................................... III-2-33 III.2.9.4 BCLK Synchronous/Asynchronous Memory Access Timing ..................... III-2-36 III.2.9.5 SRAM Access when Device Size < Data Size ........................................... III-2-37 III.2.10 External Bus Requests and Release of Bus Control.............................................. III-2-38 III.2.11 Control Register Details ......................................................................................... III-2-39 0x48380: BCLK Divide Control Register (pBBCU_BCLK_DIV) .............................................. III-2-40 0x48384: Bus Control Register (pBBCU_BUSCTL) ............................................................... III-2-41 0x48386: Common Cycle Control Register (pBBCU_CM_CYC) ............................................ III-2-42 0x48388-0x483A4: CEx Area Configuration Registers (pBBCU_CExSET)........................... III-2-43 0x4838A-0x483A6: CEx Access Cycle Control Registers (pBBCU_CExACCNT) ................. III-2-46 III.2.12 Precautions ............................................................................................................ III-2-50 III.3 Extended Bus Control Unit (EBCU) ......................................................................III-3-1 III.3.1 Overview of the EBCU .............................................................................................. III-3-1 III.3.2 EBCU Pins ................................................................................................................ III-3-2 III.3.3 Configuration of SDRAM ........................................................................................... III-3-3 III.3.3.1 SDRAM Area .............................................................................................. III-3-3 III.3.3.2 Setting SDRAM Size and Address.............................................................. III-3-3 III.3.3.3 Configuration of SDRAM Chips .................................................................. III-3-6 III.3.3.4 Example Connection of SDRAMs ............................................................... III-3-6 III.3.3.5 Bus Operations of SDRAM ......................................................................... III-3-8 S1C33401 TECHNICAL MANUAL EPSON ix CONTENTS III.3.4 EBCU Operating Clock and SDRAM Clock............................................................... III-3-9 III.3.4.1 Operating Clock of the EBCU .................................................................... III-3-9 III.3.4.2 Generation of SDRAM Clock ..................................................................... III-3-10 III.3.5 Setting SDRAM Access Conditions ......................................................................... III-3-11 III.3.6 Control and Operation of SDRAM Interface ............................................................. III-3-16 III.3.6.1 Initializing SDRAM ..................................................................................... III-3-16 III.3.6.2 Read/Write Operations .............................................................................. III-3-18 III.3.6.3 SDRAM Refresh ........................................................................................ III-3-35 III.3.6.4 SDRAM Refresh Request when External Bus is Released ....................... III-3-38 III.3.7 SDRAM Commands ................................................................................................. III-3-39 III.3.8 Control Register Details ........................................................................................... III-3-40 0x483C0: SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF) ............................... III-3-41 0x483C2: Refresh Counter Register (pEBCU_RFTIM) .......................................................... III-3-42 0x483C4: Refresh Period Register (pEBCU_RFPOD) ........................................................... III-3-43 0x483C6: SDRAM Option Register (pEBCU_SDOPT) .......................................................... III-3-44 0x483C8: SDRAM Access Control Register (pEBCU_SDACR) ............................................. III-3-46 0x483CA: SDRAM Mode Register (pEBCU_SDMOD) ........................................................... III-3-48 0x483CC: Self-refresh Control Register (pEBCU_SLFEX) .................................................... III-3-49 III.3.9 Precautions .............................................................................................................. III-3-50 III.4 High-Speed DMA (HSDMA) ....................................................................................III-4-1 III.4.1 Functional Outline of HSDMA ................................................................................... III-4-1 III.4.2 I/O Pins of HSDMA ................................................................................................... III-4-5 III.4.3 Programming Control Information ............................................................................. III-4-6 III.4.3.1 Standard Mode and Advanced Mode ......................................................... III-4-6 III.4.3.2 Setting the Registers in Dual-Address Mode .............................................. III-4-6 III.4.3.3 Setting the Registers in Single-Address Mode ........................................... III-4-9 III.4.4 Enabling/Disabling DMA Transfer ............................................................................. III-4-12 III.4.5 Trigger Source .......................................................................................................... III-4-13 III.4.6 Operation of HSDMA ............................................................................................... III-4-14 III.4.6.1 Operation in Dual-Address Mode .............................................................. III-4-14 III.4.6.2 Operation in Single-Address Mode ............................................................ III-4-18 III.4.7 Interrupt Function of HSDMA ................................................................................... III-4-22 III.4.8 HSDMA Operating Clock.......................................................................................... III-4-23 III.4.9 Details of Control Registers ..................................................................................... III-4-24 0x48220-0x48250: HSDMA Ch.x Transfer Counter Registers (pHSx_CNT) ......................... III-4-26 0x48222-0x48252: HSDMA Ch.x Control Registers .............................................................. III-4-27 0x48224-0x48254: HSDMA Ch.x Low-Order Source Address Setup Registers (pHSx_SADR)....................................................................................... III-4-28 0x48226-0x48256: HSDMA Ch.x High-Order Source Address Setup Registers ................... III-4-29 0x48228-0x48258: HSDMA Ch.x Low-Order Destination Address Setup Registers (pHSx_DADR) ...................................................................................... III-4-31 0x4822A-0x4825A: HSDMA Ch.x High-Order Destination Address Setup Registers ........... III-4-32 0x4822C-0x4825C: HSDMA Ch.x Enable Registers (pHSx_EN) .......................................... III-4-34 0x4822E-0x4825E: HSDMA Ch.x Trigger Flag Registers (pHSx_TF) ................................... III-4-35 0x48262-0x48292: HSDMA Ch.x Control Registers (pHSx_ADVMODE) for ADV mode....... III-4-36 0x48264-0x48296: HSDMA Ch.x Source Address Setup Registers (pHSx_AD_SADR) for ADV mode ........................................................ III-4-38 0x48268-0x4829A: HSDMA Ch.x Destination Address Setup Registers (pHSx_ADV_DADR) for ADV mode ...................................................... III-4-40 0x4829C: HSDMA STD/ADV Mode Select Register (pHS_CNTLMODE) .............................. III-4-42 III.4.10 Precautions ............................................................................................................ III-4-43 x EPSON S1C33401 TECHNICAL MANUAL CONTENTS III.5 Intelligent DMA (IDMA) ...........................................................................................III-5-1 III.5.1 Functional Outline of IDMA ....................................................................................... III-5-1 III.5.2 Programming Control Information ............................................................................. III-5-3 III.5.2.1 Setting the Base Address ........................................................................... III-5-3 III.5.2.2 Control Information ..................................................................................... III-5-3 III.5.3 IDMA Invocation ........................................................................................................ III-5-8 III.5.4 Operation of IDMA ................................................................................................... III-5-11 III.5.4.1 Single Transfer Mode ................................................................................. III-5-11 III.5.4.2 Successive Transfer Mode ......................................................................... III-5-12 III.5.4.3 Block Transfer Mode .................................................................................. III-5-13 III.5.5 Linking ...................................................................................................................... III-5-15 III.5.6 Interrupt Function of Intelligent DMA........................................................................ III-5-16 III.5.7 Details of Control Registers ..................................................................................... III-5-17 0x48200: IDMA Base Address Register 0 (pIDMABASE) ...................................................... III-5-18 0x48202: IDMA Base Address Register 1 .............................................................................. III-5-18 0x48204: IDMA Start Register (pIDMA_START) .................................................................... III-5-19 0x48205: IDMA Enable Register (pIDMA_EN) ....................................................................... III-5-20 III.5.8 Precautions .............................................................................................................. III-5-21 S1C33401 TECHNICAL MANUAL EPSON xi CONTENTS IV C33 ADV BASIC PERIPHERAL BLOCK IV.1 Preface.................................................................................................................... IV-1-1 IV.2 Interrupt Controller (ITC) ...................................................................................... IV-2-1 IV.2.1 Outline of Interrupt Functions .................................................................................... IV-2-1 IV.2.1.1 Maskable Interrupts .................................................................................... IV-2-1 IV.2.1.2 Causes of Interrupt and Intelligent DMA ..................................................... IV-2-3 IV.2.1.3 Nonmaskable Interrupt (NMI)...................................................................... IV-2-3 IV.2.1.4 Interrupt Processing by the CPU ................................................................ IV-2-4 IV.2.1.5 Clearing Standby Mode by Interrupts ......................................................... IV-2-4 IV.2.2 Trap Table .................................................................................................................. IV-2-6 IV.2.3 ITC Operating Clock .................................................................................................. IV-2-7 IV.2.4 Control of Maskable Interrupts .................................................................................. IV-2-8 IV.2.4.1 Structure of the Interrupt Controller ............................................................ IV-2-8 IV.2.4.2 Processor Status Register (PSR) ............................................................... IV-2-8 IV.2.4.3 Cause-of-Interrupt Flag and Interrupt Enable Register ............................... IV-2-9 IV.2.4.4 Interrupt Priority Register and Interrupt Levels .......................................... IV-2-11 IV.2.5 IDMA Invocation ....................................................................................................... IV-2-12 IV.2.6 HSDMA Invocation ................................................................................................... IV-2-14 IV.2.7 Details of Control Registers ..................................................................................... IV-2-15 0x40260: Port Input 0-1 Interrupt Priority Register (pINT_PR01L) ........................................ IV-2-17 0x40261: Port Input 2-3 Interrupt Priority Register (pINT_PR23L) ........................................ IV-2-18 0x40262: Key Input Interrupt Priority Register (pINT_PK01L) ................................................ IV-2-19 0x40263: HSDMA Ch.0-1 Interrupt Priority Register (pINT_PHSD01L) ................................ IV-2-20 0x40264: HSDMA Ch.2-3 Interrupt Priority Register (pINT_PHSD23L) ................................ IV-2-21 0x40265: IDMA Interrupt Priority Register (pINT_PDM)......................................................... IV-2-22 0x40266: 16-bit Timer 0-1 Interrupt Priority Register (pINT_P16T01) ................................... IV-2-23 0x40267: 16-bit Timer 2-3 Interrupt Priority Register (pINT_P16T23) ................................... IV-2-24 0x40268: 16-bit Timer 4-5 Interrupt Priority Register (pINT_P16T45) ................................... IV-2-25 0x40269: 8-bit Timer, Serial I/F Ch.0 Interrupt Priority Register (pINT_P8T_PSI00) ............. IV-2-26 0x4026A: Serial I/F Ch.1, A/D Interrupt Priority Register (pINT_PSI01_PAD) ....................... IV-2-27 0x4026B: RTC Interrupt Priority Register (pINT_PCTM) ........................................................ IV-2-28 0x4026C: Port Input 4-5 Interrupt Priority Register (pINT_PR45L) ....................................... IV-2-29 0x4026D: Port Input 6-7 Interrupt Priority Register (pINT_PR67L) ....................................... IV-2-30 0x4026E: Serial I/F Ch.2-3 Interrupt Priority Register (pINT_PSI0203) ................................ IV-2-31 0x40270: Key Input, Port Input 0-3 Interrupt Enable Register (pINT_EK01_EP03)............... IV-2-32 0x40271: DMA Interrupt Enable Register (pINT_EDMA) ....................................................... IV-2-33 0x40272: 16-bit Timer 0-1 Interrupt Enable Register (pINT_E16T01) ................................... IV-2-34 0x40273: 16-bit Timer 2-3 Interrupt Enable Register (pINT_E16T23) ................................... IV-2-35 0x40274: 16-bit Timer 4-5 Interrupt Enable Register (pINT_E16T45) ................................... IV-2-36 0x40275: 8-bit Timer 0-3 Interrupt Enable Register (pINT_E8T03) ....................................... IV-2-37 0x40276: Serial I/F Ch.0-1 Interrupt Enable Register (pINT_ESIF01) ................................... IV-2-38 0x40277: Port Input 4-7, RTC, A/D Interrupt Enable Register (pINT_EP47_ECT_EAD)....... IV-2-39 0x40278: 8-bit Timer 4-5 Interrupt Enable Register (pINT_E8T45) ....................................... IV-2-40 0x40279: Serial I/F Ch.2-3 Interrupt Enable Register (pINT_ESIF23) ................................... IV-2-41 0x40280: Key Input, Port Input 0-3 Interrupt Cause Flag Register (pINT_FK01_FP03) ........ IV-2-42 0x40281: DMA Interrupt Cause Flag Register (pINT_FDMA) ................................................ IV-2-44 0x40282: 16-bit Timer 0-1 Interrupt Cause Flag Register (pINT_F16T01) ............................ IV-2-45 0x40283: 16-bit Timer 2-3 Interrupt Cause Flag Register (pINT_F16T23) ............................ IV-2-46 0x40284: 16-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F16T45) ............................ IV-2-47 0x40285: 8-bit Timer 0-3 Interrupt Cause Flag Register (pINT_F8T03) ................................ IV-2-48 0x40286: Serial I/F Ch.0-1 Interrupt Cause Flag Register (pINT_FSIF01)............................ IV-2-49 0x40287: Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (pINT_FP47_FCT_FAD) ... IV-2-50 0x40288: 8-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F8T45) ................................ IV-2-51 0x40289: Serial I/F Ch.2-3 Interrupt Cause Flag Register (pINT_FSIF23)............................ IV-2-52 xii EPSON S1C33401 TECHNICAL MANUAL CONTENTS 0x40290: Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Request Register (pIDMAREQ_RP03_RHS_R16T0) .................................................................. IV-2-53 0x40291: 16-bit Timer 1-4 IDMA Request Register (pIDMAREQ_R16T14) .......................... IV-2-54 0x40292: 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Request Register (pIDMAREQ_R16T5_R8T_RSIF0) .................................................................. IV-2-55 0x40293: Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Request Register (pIDMAREQ_RSIF1_RAD_RP47) ................................................................... IV-2-56 0x40294: Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Enable Register (pIDMAEN_DEP03_DEHS_DE16T0) .............................................................. IV-2-57 0x40295: 16-bit Timer 1-4 IDMA Enable Register (pIDMAEN_DE16T14) ............................. IV-2-58 0x40296: 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Enable Register (pIDMAEN_DE16T5_DE8T_DESIF0).............................................................. IV-2-59 0x40297: Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Enable Register (pIDMAEN_DESIF1_DEAD_DEP47)............................................................... IV-2-60 0x40298: HSDMA Ch.0-1 Trigger Set-up Register (pHSDMA_HTGR1) ................................ IV-2-61 0x40299: HSDMA Ch.2-3 Trigger Set-up Register (pHSDMA_HTGR2) ................................ IV-2-61 0x4029A: HSDMA Software Trigger Register (pHSDMA_HSOFTTGR) ................................. IV-2-63 0x4029B: 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Request Register (pIDMAREQ_R8T45_RSIF23) ......................................................................... IV-2-64 0x4029C: 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Enable Register (pIDMAEN_DE8T45_DESIF23) ....................................................................... IV-2-65 0x4029F: Flag Set/Reset Method Select Register (pRST_RESET) ....................................... IV-2-66 0x402A0: Port Input 8-9 Interrupt Priority Register (pINT_PR89L)........................................ IV-2-67 0x402A1: Port Input 10-11 Interrupt Priority Register (pINT_PR1011L)................................ IV-2-68 0x402A2: Port Input 12-13 Interrupt Priority Register (pINT_PR1213L)................................ IV-2-69 0x402A3: Port Input 14-15 Interrupt Priority Register (pINT_PR1415L)................................ IV-2-70 0x402A4: 16-bit Timer 6-7 Interrupt Priority Register (pINT_P16T67)................................... IV-2-71 0x402A5: 16-bit Timer 8-9 Interrupt Priority Register (pINT_P16T89)................................... IV-2-72 0x402A6: Port Input 8-15 Interrupt Enable Register (pINT_EP815) ...................................... IV-2-73 0x402A7: 16-bit Timer 6-7 Interrupt Enable Register (pINT_E16T67) ................................... IV-2-74 0x402A8: 16-bit Timer 8-9 Interrupt Enable Register (pINT_E16T89) ................................... IV-2-75 0x402A9: Port Input 8-15 Interrupt Cause Flag Register (pINT_FP815) ............................... IV-2-76 0x402AA: 16-bit Timer 6-7 Interrupt Cause Flag Register (pINT_F16T67) ........................... IV-2-77 0x402AB: 16-bit Timer 8-9 Interrupt Cause Flag Register (pINT_F16T89) ........................... IV-2-78 0x402AC: Port Input 8-15 IDMA Request Register (pIDMAREQ_RP815) ............................ IV-2-79 0x402AD: 16-bit Timer 6-9 IDMA Request Register (pIDMAREQ_R16T69) ......................... IV-2-80 0x402AE: Port Input 8-15 IDMA Enable Register (pIDMAEN_DEP815) ............................... IV-2-81 0x402AF: 16-bit Timer 6-9 IDMA Enable Register (pIDMAEN_DE16T69) ............................ IV-2-82 IV.2.8 Precautions .............................................................................................................. IV-2-83 IV.3 OSC3 Oscillator Circuit, PLL, and SSCG ............................................................. IV-3-1 IV.3.1 Overview of the System Clock Generator Unit .......................................................... IV-3-1 IV.3.2 OSC3 Oscillator Circuit ............................................................................................. IV-3-2 IV.3.2.1 Input/Output Pins of the OSC3 Oscillator Circuit ........................................ IV-3-2 IV.3.2.2 Structure of the Oscillator Circuit ................................................................ IV-3-2 IV.3.2.3 Oscillation Control ...................................................................................... IV-3-2 IV.3.3 PLL ............................................................................................................................ IV-3-3 IV.3.3.1 Control of PLL ............................................................................................. IV-3-3 IV.3.3.2 Power Supply for PLL ................................................................................. IV-3-4 IV.3.4 SSCG ........................................................................................................................ IV-3-5 IV.3.5 Precautions ............................................................................................................... IV-3-6 IV.4 Prescaler (PSC)...................................................................................................... IV-4-1 IV.4.1 Configuration of Prescaler ......................................................................................... IV-4-1 IV.4.2 Source Clock ............................................................................................................. IV-4-2 IV.4.3 Selecting Division Ratio and Output Control for Prescaler ............................................ IV-4-3 S1C33401 TECHNICAL MANUAL EPSON xiii CONTENTS IV.4.4 Source Clock Output to 8-Bit Timer ........................................................................... IV-4-4 IV.4.5 PSC_CLK External Output ........................................................................................ IV-4-5 IV.4.6 Details of Control Registers ...................................................................................... IV-4-6 0x40140: 8-bit Timer 4-5 Clock and Port Output Clock Select Register (pCLKSEL_T8_45) .. IV-4-7 0x40141-0x4014C: 16-bit Timer x Clock Control Registers (pCLKCTL_T16_x) ..................... IV-4-8 0x40145: 8-bit Timer 4-5 Clock Control Register (pCLKCTL_T8_45)..................................... IV-4-9 0x40146: 8-bit Timer 0-3 Clock Select Register (pCLKSEL_T8) ........................................... IV-4-10 0x4014D: 8-bit Timer 0-1 Clock Control Register (pCLKCTL_T8_01) ................................... IV-4-11 0x4014E: 8-bit Timer 2-3 Clock Control Register (pCLKCTL_T8_23) ................................... IV-4-12 0x4014F: A/D Clock Control Register (pCLKCTL_AD)........................................................... IV-4-13 IV.4.7 Precautions .............................................................................................................. IV-4-14 IV.5 8-Bit Timers (T8)..................................................................................................... IV-5-1 IV.5.1 IV.5.2 IV.5.3 IV.5.4 IV.5.5 IV.5.6 IV.5.7 IV.5.8 Configuration of 8-bit Timer ....................................................................................... IV-5-1 Output Pins of 8-bit Timers ........................................................................................ IV-5-2 Uses of 8-bit Timers .................................................................................................. IV-5-3 8-bit Timer Operating Clock and Count Clock ........................................................... IV-5-5 Control and Operation of 8-bit Timer ......................................................................... IV-5-6 Control of Underflow Signal and Clock Outputs ........................................................ IV-5-8 8-bit Timer Interrupts and DMA ................................................................................. IV-5-9 Details of Control Registers ..................................................................................... IV-5-11 0x40160-0x40178: 8-bit Timer x Control Registers (pT8_CTLx) ........................................... IV-5-12 0x40161-0x40179: 8-bit Timer x Reload Data Registers (pT8_RLDx) .................................. IV-5-13 0x40162-0x4017A: 8-bit Timer x Counter Data Registers (pT8_PTDx) ................................. IV-5-14 IV.5.9 Precautions .............................................................................................................. IV-5-15 IV.6 16-Bit Timers (T16)................................................................................................. IV-6-1 IV.6.1 IV.6.2 IV.6.3 IV.6.4 IV.6.5 IV.6.6 IV.6.7 IV.6.8 Configuration of 16-bit Timer ..................................................................................... IV-6-1 I/O Pins of 16-bit Timers ............................................................................................ IV-6-3 Uses of 16-bit Timers ................................................................................................ IV-6-4 16-bit Timer Operating Clock and Count Clock ......................................................... IV-6-5 Control and Operation of 16-bit Timer ....................................................................... IV-6-6 Controlling Clock Output .......................................................................................... IV-6-10 16-bit Timer Interrupts and DMA .............................................................................. IV-6-13 Details of Control Registers ..................................................................................... IV-6-16 0x48180-0x481C8: 16-bit Timer x Comparison Data A Setup Registers (pT16_CRxA) ........ IV-6-18 0x48182-0x481CA: 16-bit Timer x Comparison Data B Setup Registers (pT16_CRxB) ....... IV-6-19 0x48184-0x481CC: 16-bit Timer x Counter Data Registers (pT16_TCx) .............................. IV-6-20 0x48186-0x481CE: 16-bit Timer x Control Registers (pT16_CTLx) ...................................... IV-6-21 0x481D0-0x481D6: DA16 Ch.x Registers (pDA16_CRxA) .................................................... IV-6-23 0x481DC: Count Pause Register (pT16_CNT_PAUSE) ......................................................... IV-6-24 0x481DE: 16-bit Timer STD/ADV Mode Select Register (pT16_ADVMODE)......................... IV-6-25 IV.6.9 Precautions .............................................................................................................. IV-6-26 IV.7 Watchdog Timer (WDT).......................................................................................... IV-7-1 IV.7.1 IV.7.2 IV.7.3 IV.7.4 xiv Configuration of the Watchdog Timer ....................................................................... IV-7-1 Input/Output Pins of the Watchdog Timer ................................................................. IV-7-2 Operating Clock of the Watchdog Timer ................................................................... IV-7-3 Control of the Watchdog Timer .................................................................................. IV-7-4 IV.7.4.1 Setting Up the Watchdog Timer .................................................................. IV-7-4 IV.7.4.2 Starting/Stopping the Watchdog Timer ...................................................... IV-7-5 IV.7.4.3 Resetting the Watchdog Timer ................................................................... IV-7-5 IV.7.4.4 Operation in Standby Mode ........................................................................ IV-7-5 IV.7.4.5 Clock Output of the Watchdog Timer ......................................................... IV-7-6 EPSON S1C33401 TECHNICAL MANUAL CONTENTS IV.7.5 Control Register Details ........................................................................................... IV-7-7 0x48160: Watchdog Timer Write-Protect Register (pWD_WP) ............................................... IV-7-8 0x48162: Watchdog Timer Enable Register (pWD_EN) .......................................................... IV-7-9 0x48164: Watchdog Timer Comparison Data Setup Register 0 (pWD_COMP_LOW) ........... IV-7-11 0x48166: Watchdog Timer Comparison Data Setup Register 1 (pWD_COMP_HIGH) .......... IV-7-11 0x48168: Watchdog Timer Count Register 0 (pWD_CNT_LOW) ........................................... IV-7-12 0x4816A: Watchdog Timer Count Register 1 (pWD_CNT_HIGH) .......................................... IV-7-12 0x4816C: Watchdog Timer Control Register (pWD_CNTL).................................................... IV-7-13 IV.7.6 Precautions .............................................................................................................. IV-7-14 IV.8 Serial Interface (SIO) ............................................................................................. IV-8-1 IV.8.1 Configuration of Serial Interfaces .............................................................................. IV-8-1 IV.8.1.1 Features of Serial Interfaces ....................................................................... IV-8-1 IV.8.1.2 I/O Pins of Serial Interface .......................................................................... IV-8-2 IV.8.1.3 Setting Transfer Mode ................................................................................. IV-8-3 IV.8.1.4 Serial Interface Operating Clock ................................................................. IV-8-4 IV.8.1.5 Standard Mode and Advanced Mode ......................................................... IV-8-4 IV.8.2 Clock-Synchronized Interface ................................................................................... IV-8-5 IV.8.2.1 Outline of Clock-Synchronized Interface ..................................................... IV-8-5 IV.8.2.2 Setting Clock-Synchronized Interface ......................................................... IV-8-6 IV.8.2.3 Control and Operation of Clock-Synchronized Transfer .............................. IV-8-8 IV.8.3 Asynchronous Interface............................................................................................ IV-8-15 IV.8.3.1 Outline of Asynchronous Interface ............................................................. IV-8-15 IV.8.3.2 Setting Asynchronous Interface ................................................................. IV-8-16 IV.8.3.3 Control and Operation of Asynchronous Transfer ...................................... IV-8-20 IV.8.4 IrDA Interface ........................................................................................................... IV-8-25 IV.8.4.1 Outline of IrDA Interface............................................................................. IV-8-25 IV.8.4.2 Setting IrDA Interface ................................................................................. IV-8-25 IV.8.4.3 Control and Operation of IrDA Interface..................................................... IV-8-27 IV.8.5 Serial Interface Interrupts and DMA ......................................................................... IV-8-28 IV.8.6 Details of Control Registers ..................................................................................... IV-8-31 0x401E0-0x401F5: Serial I/F Ch.x Transmit Data Registers (pFSIFx_TXD) ......................... IV-8-32 0x401E1-0x401F6: Serial I/F Ch.x Receive Data Registers (pFSIFx_RXD) ......................... IV-8-33 0x401E2-0x401F7: Serial I/F Ch.x Status Registers (pFSIFx_STATUS) ............................... IV-8-34 0x401E3-0x401F8: Serial I/F Ch.x Control Registers (pFSIFx_CTL) .................................... IV-8-36 0x401E4-0x401F9: Serial I/F Ch.x IrDA Registers (pFSIFx_IRDA) ....................................... IV-8-38 0x401FF: Serial I/F STD/ADV Mode Select Register (pFSIF_ADV) ....................................... IV-8-40 IV.8.7 Precautions .............................................................................................................. IV-8-41 IV.9 Card Interface (CARD) ........................................................................................... IV-9-1 IV.9.1 Overview of the Card Interface.................................................................................. IV-9-1 IV.9.2 Card Interface Pins.................................................................................................... IV-9-2 IV.9.3 Card Area .................................................................................................................. IV-9-3 IV.9.3.1 Selecting the Area ...................................................................................... IV-9-3 IV.9.3.2 Setting Area Access Conditions.................................................................. IV-9-3 IV.9.4 Card Interface Control Signals .................................................................................. IV-9-4 IV.9.4.1 SmartMedia Interface ................................................................................. IV-9-4 IV.9.4.2 CompactFlash Interface .............................................................................. IV-9-5 IV.9.4.3 PC Card Interface ....................................................................................... IV-9-5 IV.9.5 Card Interface Operating Clock ................................................................................. IV-9-7 IV.9.6 Details of Control Registers ...................................................................................... IV-9-8 0x40300: Card I/F Area Configuration Register (pCARDSETUP) ........................................... IV-9-8 0x40302: Card I/F Output Port Configuration Register (pCARDFUNCSEL05) ....................... IV-9-9 IV.9.7 Precautions .............................................................................................................. IV-9-10 S1C33401 TECHNICAL MANUAL EPSON xv CONTENTS IV.10 General-Purpose I/O Ports (PORT) ................................................................... IV-10-1 IV.10.1 IV.10.2 IV.10.3 IV.10.4 Structure of I/O Port ............................................................................................... IV-10-1 Selecting the I/O Pin Functions .............................................................................. IV-10-1 I/O Control Register and I/O Modes ....................................................................... IV-10-2 Input Interrupt ......................................................................................................... IV-10-3 IV.10.4.1 Port Input Interrupt ................................................................................... IV-10-3 IV.10.4.2 Key Input Interrupt ................................................................................... IV-10-5 IV.10.4.3 Control Registers of the Interrupt Controller ............................................ IV-10-7 IV.10.5 I/O Port Operating Clock ........................................................................................ IV-10-9 IV.10.6 Details of Control Registers .................................................................................. IV-10-10 0x40340-0x40352: Px Port Data Registers (pPx_PxD) ........................................................ IV-10-11 0x4034E: P7 Port Data Register (pP7_P7D) ......................................................................... IV-10-12 0x40341-0x40353: Px I/O Control Registers (pPx_IOCx) .................................................... IV-10-13 0x40360-0x40373: Pxx Port Function Select Registers (pPx_xx_CFP) ............................... IV-10-14 0x40380: Port Input Interrupt Select Register 1 (pPINTSEL_SPT03) ................................... IV-10-15 0x40381: Port Input Interrupt Select Register 2 (pPINTSEL_SPT47) ................................... IV-10-15 0x40384: Port Input Interrupt Select Register 3 (pPINTSEL_SPT811) ................................. IV-10-15 0x40385: Port Input Interrupt Select Register 4 (pPINTSEL_SPT1215) ............................... IV-10-15 0x40382: Port Input Interrupt Polarity Select Register 1 (pPINTPOL_SPP07)...................... IV-10-17 0x40386: Port Input Interrupt Polarity Select Register 2 (pPINTPOL_SPP815).................... IV-10-17 0x40383: Port Input Interrupt Edge/Level Select Register 1 (pPINTEL_SEPT07) ................ IV-10-18 0x40387: Port Input Interrupt Edge/Level Select Register 2 (pPINTEL_SEPT815) .............. IV-10-18 0x40390: Key Input Interrupt Select Register (pKINTSEL_SPPK01) .................................... IV-10-19 0x40392: Key Input Interrupt (FPK0) Input Comparison Register (pKINTCOMP_SCPK0) ... IV-10-20 0x40393: Key Input Interrupt (FPK1) Input Comparison Register (pKINTCOMP_SCPK1) ... IV-10-20 0x40394: Key Input Interrupt (FPK0) Input Mask Register (pKINTCOMP_SMPK0) ............. IV-10-21 0x40395: Key Input Interrupt (FPK1) Input Mask Register (pKINTCOMP_SMPK1) ............. IV-10-21 IV.10.7 Precautions ........................................................................................................... IV-10-22 IV.11 A/D Converter (ADC) .......................................................................................... IV-11-1 IV.11.1 IV.11.2 IV.11.3 IV.11.4 IV.11.5 IV.11.6 IV.11.7 Features and Structure of A/D Converter ............................................................... IV-11-1 I/O Pins of A/D Converter ....................................................................................... IV-11-2 A/D Converter Operating Clock and Conversion Clock .......................................... IV-11-3 Setting A/D Converter ............................................................................................ IV-11-4 Control and Operation of A/D Conversion .............................................................. IV-11-9 A/D Converter Interrupt and DMA ......................................................................... IV-11-13 Details of Control Registers .................................................................................. IV-11-15 0x48140: A/D Conversion Result Register (pAD_ADD) ........................................................ IV-11-16 0x48142: A/D Trigger/Channel Select Register (pAD_TRIG_CHNL) .................................... IV-11-17 0x48144: A/D Control/Status Register (pAD_EN_SMPL_STAT) ........................................... IV-11-19 0x48146: A/D Channel Status Flag Register (pAD_END) ..................................................... IV-11-22 0x48148-0x48156: A/D Ch.x Conversion Result Buffer Registers (pAD_CHx_BUF) ........... IV-11-23 0x48158: A/D Upper Limit Value Register (pAD_UPPER)..................................................... IV-11-24 0x4815A: A/D Lower Limit Value Register (pAD_LOWER).................................................... IV-11-25 0x4815C: A/D Conversion Complete Interrupt Mask Register (pAD_CH07_INTMASK) ....... IV-11-26 0x4815E: A/D Converter Mode Select/Internal Status Register (pAD_ADVMODE) .............. IV-11-27 IV.11.8 Precautions ........................................................................................................... IV-11-28 xvi EPSON S1C33401 TECHNICAL MANUAL CONTENTS V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK V.1 Preface...................................................................................................................... V-1-1 V.2 Area 6 Settings and Macro Control Register ........................................................ V-2-1 V.2.1 V.2.2 V.2.3 V.2.4 Setting Up the CE6 Area with BBCU Registers ..........................................................V-2-1 Clock Control ............................................................................................................... V-2-2 Setting Wait Cycles for Accessing the RTC................................................................. V-2-3 Control Register Details .............................................................................................. V-2-4 0x300F20: Macro Control Register (pMISC3) ..........................................................................V-2-4 V.3 Chip ID ...................................................................................................................... V-3-1 V.3.1 Chip ID Bits ................................................................................................................. V-3-1 V.3.2 Details of Control Register .......................................................................................... V-3-2 0x300000: Device ID Register (pMISC0)..................................................................................V-3-2 V.4 Pin Control Registers .............................................................................................. V-4-1 V.4.1 Pull-up Control ............................................................................................................ V-4-1 V.4.2 Driving Bus Signals Low ............................................................................................. V-4-1 V.4.3 Details of Control Registers ........................................................................................ V-4-2 0x300F00: Bus Signal Low Drive/Pull-up Control Register (pMISC1) ......................................V-4-3 0x300F04: Port Pull-up Control Register (pMISC2)..................................................................V-4-5 V.4.4 Precautions ................................................................................................................. V-4-7 V.5 Real-Time Clock (RTC) ............................................................................................ V-5-1 V.5.1 Overview of the RTC ................................................................................................... V-5-1 V.5.2 RTC Counters ............................................................................................................. V-5-2 V.5.3 Control of the RTC ...................................................................................................... V-5-5 V.5.3.1 Controlling the Operating Clock .................................................................... V-5-5 V.5.3.2 Initial Sequence of the RTC ..........................................................................V-5-5 V.5.3.3 Selecting 12/24-hour Mode and Setting the Counters ..................................V-5-6 V.5.3.4 Starting, Stopping, and Resetting Counters .................................................V-5-6 V.5.3.5 Counter Hold and Busy Flag .........................................................................V-5-7 V.5.3.6 Reading from and Writing to Counters in Operation .....................................V-5-8 V.5.3.7 30-second Correction....................................................................................V-5-8 V.5.4 RTC Interrupts ............................................................................................................. V-5-9 V.5.5 Standby Mode (#STBY pin) and Power Supply of the RTC ....................................... V-5-10 V.5.6 OSC1 Oscillator Circuit .............................................................................................. V-5-11 V.5.6.1 Input/Output Pins of the OSC1 Oscillator Circuit .........................................V-5-11 V.5.6.2 Structure of the OSC1 Oscillator Circuit ......................................................V-5-11 V.5.6.3 Oscillation Control .......................................................................................V-5-12 V.5.7 Details of Control Registers ....................................................................................... V-5-13 0x301000: RTC Interrupt Status Register (pRTCINTSTAT) .....................................................V-5-14 0x301004: RTC Interrupt Mode Register (pRTCINTMODE) ...................................................V-5-15 0x301008: RTC Control Register (pRTC_CNTL0) ..................................................................V-5-16 0x30100C: RTC Access Control Register (pRTC_CNTL1) .....................................................V-5-18 0x301010: RTC Second Register (pRTCSEC) ........................................................................V-5-19 0x301014: RTC Minute Register (pRTCMIN) ..........................................................................V-5-20 0x301018: RTC Hour Register (pRTCHOUR) .........................................................................V-5-21 0x30101C: RTC Day Register (pRTCDAY) ..............................................................................V-5-22 0x301020: RTC Month Register (pRTCMONTH) ....................................................................V-5-23 0x301024: RTC Year Register (pRTCYEAR) ...........................................................................V-5-24 0x301028: RTC Days of Week Register (pRTCDAYWEEK) ....................................................V-5-25 V.5.8 Precautions ................................................................................................................ V-5-26 S1C33401 TECHNICAL MANUAL EPSON xvii CONTENTS APPENDIX I/O Map............................................................................................................................ APP-1 0x40140-0x4014F 0x40160-0x4017A 0x40180-0x40188 0x401E0-0x401FF 0x40260-0x402AF 0x402E8-0x402EC 0x40300-0x40302 0x40340-0x40395 0x48140-0x4815E 0x48160-0x4816C 0x48180-0x481DE 0x48200-0x48205 0x48220-0x4829C 0x48300-0x48314 0x48320-0x48334 0x48340-0x48352 0x48360-0x48372 0x48380-0x483A6 0x483C0-0x483CC 0x300000-0x300F20 0x301000-0x301028 xviii Prescaler ........................................................................... APP-2 8-bit Timer ......................................................................... APP-6 Clock Management Unit (1) .............................................. APP-8 Serial Interface .................................................................. APP-9 Interrupt Controller ........................................................... APP-13 Debug Unit ....................................................................... APP-22 Card Interface................................................................... APP-23 I/O Ports ........................................................................... APP-24 A/D Converter .................................................................. APP-35 Watchdog Timer ............................................................... APP-38 16-bit Timer ...................................................................... APP-40 Intelligent DMA ................................................................. APP-52 High-Speed DMA ............................................................. APP-53 High-Speed Bus Control Unit ........................................... APP-66 Memory Management Unit ............................................... APP-68 Cache Control Unit ........................................................... APP-71 Clock Management Unit (2) ............................................. APP-73 Basic Bus Control Unit ..................................................... APP-75 Extended Bus Control Unit ............................................... APP-84 Chip ID/Pin Status Control ............................................... APP-86 Real Time Clock ............................................................... APP-87 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 Technical Manual I S1C33401 SPECIFICATIONS I S1C33401 SPECIFICATIONS: OVERVIEW I.1 Overview I Overview The S1C33401 is a 32-bit RISC-type microcomputer originally developed for embedded applications by Seiko Epson. The S1C33401 is built around the C33 ADV core block that includes the CPU, MMU, cache, and modules that allow various external memory and I/O devices to be connected directly, and incorporates a bus block that includes the DMA controller and other control units. In addition to these primary units, the S1C33401 incorporates a basic peripheral circuit block that includes an interrupt controller, timers, serial interfaces, card interfaces, input/output ports, and A/D converter, and an extended peripheral circuit block that includes a chip ID register, RTC, and other components. The S1C33401 is manufactured by a 0.18 m fine-pattern CMOS process, backed by sophisticated clock control functions, and can operate at higher speed with less power than ever before. In addition to its use as an embeddedtype processor in various portable systems, the S1C33401 features a built-in C33 ADV CPU to provide enhanced functionality for multimedia support while retaining upward compatibility with the conventional C33 STD CPU, making it an ideal solution to the requirements of mobile multimedia applications. Table I.1.1 Product Line Model Package S1C33401F00A S1C33401B00A QFP20-184pin PFBGA-160pin The main functions and features of the S1C33401 are outlined below. Core CPU * Original Seiko Epson 32-bit RISC-type CPU - C33 ADV * Internal 32-bit data processing * 4GB address space * Powerful instruction set - Code length: 16 bits per instruction - Number of instructions: 164 - Main instructions executable in 1 cycle (including immediate-extended instructions, each consisting of two to three instructions) - 15.15 ns per instruction (when operating at 66 MHz, max.) * Multimedia support functions - Built-in 32-bit x 16-bit multiplier - 16 x 16, 32 x 16 and 32 x 32-bit multiplication - 16 x 16, 32 x 16 and 32 x 32-bit multiply-accumulate operations - Repeated execution by loop and repeat instructions - Rounding to minimum/maximum values by saturation instruction - ALU instruction execution with post-shift High-speed Bus Control Unit (HBCU) * Controls memory access by the CPU by dividing 4GB logical space into eight 512MB blocks. * Manages MMU, CCU, and ASID processing in each block. * Capable of multiplexing logical space using ASID and mirroring physical space. * Can simultaneously process A0RAM data read/write operations and instruction fetching from cache. S1C33401 TECHNICAL MANUAL EPSON I-1-1 I S1C33401 SPECIFICATIONS: OVERVIEW Memory Management Unit (MMU) * Converts logical space into physical space in page units (4KB or 64KB per page). * Supports 16 entries per way for a total of 64 entries, due to 4-way set associative method. * Can protect memory for each page. * Allows optional selection of using cache for each page. * Supports five causes of MMU exception. Cache Control Unit (CCU) * Physical address-based instruction/data coexisting type of cache * Contains 8KB cache. * Supports 128 entries per way for a total of 512 lines, due to 4-way set associative method (4 words per line). * Allows selection of write-through or write-back mode for writing to cache. * Can lock a specified way and interrupt handler routine. * Forwarding function to allow immediate instruction/data transfer even during refill. Clock Management Unit (CMU) * Controls reset and NMI input. * System clock control - Selects clock source, turns clock on/off, and divides operating clock. - Controls clock according to standby mode (SLEEP, HALT, or HALT2). * Controls clock supply for each module (manual/auto). Debug Unit (DBG) * Supports on-chip trace/break and other debugging functions at the chip level. * Provides an advanced debugging environment in conjunction with the ICD (in-circuit debugger) and debugger. Internal Memory High-speed RAM incorporated in Area 0 (A0RAM) * 32KB * High-speed access with zero wait state RAM incorporated in Area 3 (A3RAM) * 1KB * Access with one wait state * Also usable as IDMA control information table Bus Control Units and DMA Controller Basic Bus Control Unit (BBCU) * Controls external address space by dividing it into 19 areas (Areas 4 to 22). * Allows selection of external/internal access, endian mode, interface mode, device type, device size, and number of access cycles for each area. * Outputs 8 chip-enable signals (#CE4-#CE11) corresponding to each external area. * Supports two interface modes: A0 and BSL (with BSL mode for external memory only). * Allows direct connection of SRAM, ROM, burst ROM, or flash memory to external bus. * Allows insertion of wait state from external #WAIT pin (for SRAM type only). * Arbitrates bus contention with external bus masters. Extended Bus Control Unit (EBCU) * Allows direct connection of SDRAM (in one of Areas 4 to 22 selected). * Data bus width: 16 bits * Bank address: Up to four banks accommodated. * Burst length: Fixed to 1 (with burst read/write executed by issuing successive commands). * CAS latency: 1, 2, or 3 * Write mode: Single write I-1-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: OVERVIEW * Supports self-refresh and auto-refresh. * Programmable refresh cycle * Allows selection of bank active mode (with or without auto-precharge). I Overview High-speed DMA Controller (HSDMA) * Up to four channels * Capable of high-speed DMA transfer because of no need to read/write transfer conditions, etc. from/to memory. * Supports dual-address and single-address transfers. * Activated by DMA request input, interrupt cause, or software trigger. * Can generate interrupt upon completion of transfer. Intelligent DMA Controller (IDMA) * Up to 128 channels * Supports dual-address transfers. * Programmable DMA transfer control information in RAM (except A0RAM) * Activated by a specific interrupt cause or software trigger. * Can be linked from one IDMA channel to another. * Can generate an interrupt upon completion of transfer. Internal Peripheral Circuits OSC3 Oscillator Circuit * Generates the main system clock. * Crystal/ceramic oscillator: 5 MHz (min.) to 33 MHz (max.) * External clock input: 2 MHz (min.) to 33 MHz (max.) PLL * Allows selection of whether to use x1 to x16 OSC3 oscillation frequency. * PLL input frequency: 5 MHz (min.) to 33 MHz (max.) * PLL output frequency: 20 MHz (min.) to 66 MHz (max.) SSCG (Spread Spectrum Clock Generator) * SS-modulation circuit for system source clock (OSC3, PLL, or OSC1) to reduce Electromagnetic Interference (EMI) noise Interrupt Controller (ITC) * Branches to interrupt handling routine via interrupt vector table. * Can activate intelligent DMA. * Handles 9 exceptions: - Reset exception (1) - Divide by zero exception (1) - Address misaligned exception (1) - NMI (1) - Software exceptions (4) - MMU exception (1) * Handles 64 maskable interrupts: - Port/key input interrupts (18) - DMA controller interrupts (5) - 16-bit timer interrupts (20) - 8-bit timer interrupts (6) - Serial interface interrupts (12) - A/D converter interrupts (2) - RTC interrupt (1) S1C33401 TECHNICAL MANUAL EPSON I-1-3 I S1C33401 SPECIFICATIONS: OVERVIEW Prescaler (PSC) * Programmable 8-bit and 16-bit timers, and A/D converter clock settings 8-bit Timer (T8) * 6-channel, 8-bit programmable timers * Can generate an interrupt upon underflow. * Can output the clock generated by underflow to external devices. * Generates serial interface clock as programmed. * Can output a trigger to A/D converter at specified intervals. 16-bit Timer (T16) * 10-channel, 16-bit programmable timers * Can be used as PWM timer. * Supports DA16 mode. * Can generate two interrupts per channel upon underflow or when matching compared value. * Can output clock generated by underflow or when matching compared value to external devices. Watchdog Timer (WDT) * 30-bit watchdog timer capable of generating NMI * Programmable setting of NMI generation cycle Serial Interface (SIO) * 4 channels * Contains 4-byte receive data buffer (FIFO) and 2-byte transmit data buffer (FIFO) for each channel. * Supports full-duplex communication. * Selectable between 8-bit clock-synchronous and 8-bit or 7-bit asynchronous modes. * Supports IrDA 1.0 interface. * Can generate transmit buffer empty, receive buffer full, and receive error interrupts. Card Interface (CARD) * Supports SmartMedia card (NAND flash). * Supports CompactFlash card. * Supports PC card (2 channels). I/O Ports (PORT) * Up to 71 ports * Can be used as general-purpose I/O pins when not used for peripheral functions. * Programmable port input and key input interrupts A/D Converter (ADC) * 4-channel, 10-bit A/D converters * Can generate an interrupt upon completion of conversion. * Can generate an interrupt when converted value is outside specified upper and lower limits. RTC * Contains BCD time (second, minute, and hour) counters and calendar (day, days of the week, month, and year) counters. * Allows selection between 24-hour and 12-hour modes. * Equipped with function for 30-second correction in software. * Can periodically generate interrupts (at intervals of 1/64 or 1 second, 1 minute, or 1 hour). * Powered independently of other modules, and can operate even when system power is turned off. * Contains an OSC1 oscillator circuit to generate 32.768 kHz (typ.) clock. I-1-4 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: OVERVIEW Operating Conditions and Current Consumption I Overview Power Supply Voltage * Core power supply voltages (VDD, PLLVDD, RTCVDD): 1.65 V to 1.95 V (1.8 V 0.15 V) * I/O power supply voltages (VDDE, TMVDD, AVDD): 2.70 V to 3.60 V (3.0/3.3 V 0.3 V) Input Voltage * High-level input voltage: 2.20 V (min.) to VDDE (max.) * Low-level input voltage: VSS (min.) to 0.80 V (max.) Operating Clock Frequency * CPU: 66 MHz (max.) * Bus (BBCU, EBCU): 66 MHz (max.) Operating Temperature -40C to 85C Power Consumption * In SLEEP mode: * In HALT mode: * During operation: 25 W (typ.) 36 mW (typ., 66 MHz) 65 mW (typ., 66 MHz, cache off) Form of Shipment * PFBGA 160-pin plastic package (10 mm x 10 mm x 1.2 mm, 0.65 mm pitch) * QFP20 184-pin plastic package (20 mm x 20 mm x 1.7 mm, 0.40 mm pitch) S1C33401 TECHNICAL MANUAL EPSON I-1-5 I S1C33401 SPECIFICATIONS: OVERVIEW THIS PAGE IS BLANK. I-1-6 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: BLOCK DIAGRAM I.2 Block Diagram I Block S1C33401 C33 ADV Core Block C33 ADV CPU DBG MMU HBCU A0RAM (Area 0 No-Wait RAM) CMU Standard Peripheral Block Prescaler (PSC) A3RAM (Area 3 RAM) Bridge High-speed bus OSC3/PLL Interrupt controller (ITC) CCU 8-bit Timer (T8) Bus Control Block DMA EBCU (SDRAM Controller) BBCU (SRAM Controller) 16-bit Timer/PWM (T16) Extended Peripheral Block Watchdog Timer (WDT) Real Time Clock (RTC) Serial Interface (SIO) Chip ID, Pin control and Misc. registers Card Interface (CARD) (Area 6) I/O Ports (PORT) A/D Converter (ADC) (Area 1) Figure I.2.1 S1C33401 Block Diagram S1C33401 TECHNICAL MANUAL EPSON I-2-1 I S1C33401 SPECIFICATIONS: BLOCK DIAGRAM THIS PAGE IS BLANK. I-2-2 EPSON S1C33401 TECHNICAL MANUAL P95(SOUT3/ASTB/DTD5) P96(#SCLK3/CARD4/DTD6) P97(#SRDY3/CARD5/DTD7) VDDE P82(#DMAEND2/EXCL5/DBT) P83(#DMAEND3/EXCL6/DTS0) P84(PSC_CLK/CARD2/DTS1) P85(CMU_CLK/CARD3/DTS2) VDD P86(TM8/CARD0/DTS3) P87(TM9/CARD1/DTS4) VSS P80(#DMAACK2/T8UF3/EXCL3) P81(#DMAACK3/T8UF4/EXCL4) VDDE N.C. P30(#DMAREQ0/T8UF0/EXCL0) P31(#DMAREQ1/T8UF1/EXCL1) P32(#DMAREQ2/CARD2/EXCL2) P33(#DMAREQ3/CARD3/WDT_CLK) P60(#BUSREQ/CARD4) P61(#BUSACK/CARD5) VSS N.C. VDD N.C. P62(#BUSGET/T8UF2/#ADTRG) CMU_CLK(P63/BCLK/T8UF5) VDDE #CE4(P50/CARD0) #CE5(P51) #CE6(P52) #CE7(P53/CARD1) #CE8(P54) VSS P64(#WAIT) TMVDD P10(TM0) P11(TM1) VDD P12(TM2) P13(TM3) P14(TM4/#DMAEND0) P15(TM5/#DMAEND1) P16(TM6/#DMAACK0) P17(TM7/#DMAACK1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 VSS #CE11(P56) #CE9(P55) #CE10 P27(DQMH/#SRDY3) P26(DQML/#SCLK3) VSS P21(SDCLK/SOUT2) VDD P25(#SDWE/SOUT3) VDDE P24(#SDCAS/SIN3) P23(#SDRAS/#SRDY2) P22(#SDCS/#SCLK2) P20(SDCKE/SIN2) VSS D15 D14 D13 VDDE N.C. VDD N.C. D12 D11 VSS N.C. D10 D9 D8 D7 VDDE D6 VSS D5 D4 D3 VDD D2 D1 VSS VDDE D0 #BSL #WRH #WRL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3 Pin Description RTCVDD #STBY OSC1 OSC2 PLLVDD VCP PLLVSS VDD BURNIN SCANEN OSC3 OSC4 VSS TST0 TST1 VDDE #RESET #NMI P00(SIN0) P01(SOUT0) P02(#SCLK0) VDD N.C. P03(#SRDY0) P04(SIN1) N.C. VSS P05(SOUT1) P06(#SCLK1) P07(#SRDY1) DSIO DST0(P65) DST1(P66) DST2 VDD DPCO(P67) VSS DCLK VDDE N.C. P90(SIN2/EXCL7/DTD0) P91(SOUT2/EXCL8/DTD1) P92(#SCLK2/EXCL9/DTD2) P93(#SRDY2/R/W/DTD3) P94(SIN3/ACST/DTD4) VSS 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 S1C33401 TECHNICAL MANUAL EPSON I I.3.1 Pin Arrangement Pin The S1C33401 comes in a QFP20-184pin or PFBGA-160pin plastic package. I.3.1.1 QFP Package Pin Arrangement (S1C33401F00A) 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 #RD VSS A0 A1 A2 VDDE A3 A4 VSS A5 VDD A6 A7 A8 A9 A10 N.C. VDDE N.C. VSS A11 VDD N.C. A12 A13 A14 A15 A16 A17 VSS A18(P47) VDDE A19(P46) A20(P45) A21(P44) VDD A22(P43) A23(P42) A24(P41) A25(P40) VSS AVDD P73(AIN3) P72(AIN2) P71(AIN1) P70(AIN0) Figure I.3.1.1.1 Pin Arrangement (QFP20-184pin) I-3-1 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.1.2 PFBGA Package Pin Arrangement (S1C33401B00A) Top View 14 13 12 11 10 9 8 7 6 5 4 3 2 1 B C D E F G H J K L M N 3 P90 #SCLK2 EXCL9 N.C. DTD2 A A B C D E F G H J K L MN P 2 P92 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Index A1 Corner 1 Bottom View 4 DCLK SIN2 EXCL7 DTD0 5 6 P NM L K J H G F E D C B A 7 P06 P03 P00 DST1 #SCLK1 #SRDY0 SIN0 10 OSC3 11 VSS 13 OSC1 14 A P93 P91 P67 P65 P05 SOUT3 ASTB DTD5 #SRDY2 R/W DTD3 SOUT2 EXCL8 DTD1 DPCO DST0 SOUT1 P97 P96 VSS P94 DSIO P07 P04 P01 #SRDY3 CARD5 DTD7 #SCLK3 CARD4 DTD6 #SRDY1 SIN1 SOUT0 P84 P83 P82 VSS P02 #RESET PSC_CLK CARD2 DTS1 #DMAEND3 EXCL6 DTS0 #DMAEND2 EXCL5 DBT P86 VSS P85 SIN3 ACST DTD4 VDDE DST2 VDD #NMI TST1 RTCVDD SCANEN VDD #STBY VSS B TST0 BURNIN VCP PLLVDD #CE10 P27 DQMH #SRDY3 VDDE #SCLK0 #CE11 PLLVSS P26 VSS VDD SDCLK SOUT2 #CE9 P25 P24 P55 #SDWE SOUT3 #SDCAS SIN3 VDD P23 D15 P81 P30 P87 P80 #DMAACK3 T8UF4 EXCL4 #DMAREQ0 T8UF0 EXCL0 TM9 CARD1 DTS4 #DMAACK2 T8UF3 EXCL3 P32 P61 P31 P33 P22 #DMAREQ2 CARD2 EXCL2 #BUSACK CARD5 #DMAREQ1 T8UF1 EXCL1 #DMAREQ3 CARD3 WDT_CLK #SDCS #SCLK2 CMU_CLK P62 P60 VDDE P63 BCLK T8UF5 #BUSGET T8UF2 #ADTRG #BUSREQ CARD4 #CE6 #CE5 #CE7 #CE4 P52 P51 P53 CARD1 P50 CARD0 P64 TMVDD VSS #CE8 Top View VDDE E P20 D14 F VDD G VDDE D11 D12 VSS H D8 D9 D10 D7 J VSS D4 D5 D6 P54 K P11 P12 P13 P10 TM1 TM2 TM3 TM0 P14 P16 P17 P15 A23 TM4 #DMAEND0 TM6 #DMAACK0 TM7 #DMAACK1 TM5 #DMAEND1 P42 P70 P71 AVDD A25 A22 A19 AIN0 AIN1 P40 P43 P46 P VDD VSS A16 A21 VDD D3 A4 A6 D1 D2 P44 L VDDE A14 A11 VSS A9 #WRL #WRH #BSL D0 M P72 P73 A24 A20 A18 AIN2 AIN3 P41 P45 P47 A17 A13 VDDE A5 A8 VSS A1 #RD N A15 A12 A3 A7 A10 A2 A0 P N.C. 1 D SDCKE SIN2 #SDRAS #SRDY2 D13 C P21 DQML #SCLK3 P56 CMU_CLK CARD3 DTS2 #WAIT 12 OSC2 N.C. P95 TM8 CARD0 DTS3 9 OSC4 8 P66 A1 Corner N.C. 2 3 4 5 6 7 8 9 10 11 12 13 14 Figure I.3.1.2.1 Pin Arrangement (PFBGA-160pin) I-3-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.2 Pin Functions I Tables I.3.2.1 to I.3.2.5 list the function of each pin on the S1C33401. Table I.3.2.1 Power Supply Pin List Pin name VDD VSS PLLVDD PLLVSS RTCVDD VDDE TMVDD AVDD Pin Pin No. Function PFBGA QFP Power supply (+) for the internal logic circuits (1.65 V to 1.95 V) B7,B11,E4,F11,G14, 9,25,40,57,71,82,101, L5,L12 117,130,146,160,173 12,23,35,52,63,73,84,91,98, A11,B14,C3,D6,D13,E2, Power supply (-); GND 105,113,123,132,138,151, H14,K3,K11,L8,M10,N13 165,175,184 Power supply (+) for the PLL (PLLVDD = VDD) C12 143 Power supply (-) for the PLL (PLLVSS = VSS) D11 145 Power supply (+) for the RTC (RTCVDD = VDD) B12 139 4,15,29,61,75,87,97,107, D4,D9,E14,H4,H11,M6,N11 Power supply (+) for the I/O block (2.7 V to 3.6 V) 119,128,154,177 Power supply (+) for PWM timer outputs (P1x port) (TMVDD = VDDE) K2 37 Power supply (+) for the analog system and AIN0-AIN3 (AVDD = VDDE) N3 51 Table I.3.2.2 External Bus Pin List Pin name D[15:0] #BSL #RD #WRL #WRH A[17:0] A18 P47 A19 P46 A20 P45 A21 P44 A22 P43 A23 P42 A24 P41 A25 P40 #CE11 P56 #CE10 #CE9 P55 #CE8 P54 Pin No. QFP PFBGA 122-120, F13,G13, 115,114, G12,H13, 111-108, H12,J13, 106, J11,J12, 104-102, J14,K13, 100,99, K14,K12, 96 L11,L13, L14,M14 95 M13 92 N14 93 M11 94 M12 64-69, N7,L7, 72, P7,M7, 77-81, N8,P8, 83,85, M8,P9, 86, M9,N9, 88-90 P10,L9, N10,L10, P11,P12, N12,P13 62 P6 I/O Pull-up Function Module I/O 2 Data bus (D15-D0) BBCU EBCU O O O O O 1 1 1 1 1 Bus strobe (low byte) signal in BSL mode Read signal Write (low byte) signal in A0 mode or write signal in BSL mode Write (high byte) signal in A0 mode or Bus strobe (high byte) signal in BSL mode Address bus (A17-A0) BBCU BBCU BBCU BBCU BBCU EBCU I/O 1 A18: Address bus (A18) (default) P47: General-purpose I/O port A19: Address bus (A19) (default) P46: General-purpose I/O port A20: Address bus (A20) (default) P45: General-purpose I/O port A21: Address bus (A21) (default) P44: General-purpose I/O port A22: Address bus (A22) (default) P43: General-purpose I/O port A23: Address bus (A23) (default) P42: General-purpose I/O port A24: Address bus (A24) (default) P41: General-purpose I/O port A25: Address bus (A25) (default) P40: General-purpose I/O port #CE11: Chip enable signal for areas 11 and 12 (default) P56: General-purpose I/O port Chip enable signal for areas 10, 13 and 20 #CE9: Chip enable signal for areas 9 and 22 (default) P55: General-purpose I/O port #CE8: Chip enable signal for areas 8 and 21 (default) P54: General-purpose I/O port BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU PORT BBCU BBCU PORT BBCU PORT 60 N6 I/O 1 59 P5 I/O 1 58 L6 I/O 1 56 N5 I/O 1 55 M5 I/O 1 54 P4 I/O 1 53 N4 I/O 1 137 D10 I/O 1 135 136 C13 E11 I/O I/O 1 1 34 K4 I/O 1 S1C33401 TECHNICAL MANUAL EPSON I-3-3 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Pin name #CE7 P53 CARD1 #CE6 P52 #CE5 P51 #CE4 P50 CARD0 Pin No. Function I/O Pull-up PFBGA QFP J3 33 #CE7: Chip enable signal for areas 7 and 19 (default) 1 I/O P53: General-purpose I/O port CARD1:Card I/F signal 1 output (#SMWR or #CFCE2) J1 32 #CE6: Chip enable signal for areas 6, 17 and 18 (default) 1 I/O P52: General-purpose I/O port J2 31 #CE5: Chip enable signal for areas 5, 15 and 16 (default) 1 I/O P51: General-purpose I/O port J4 30 #CE4: Chip enable signal for areas 4 and 14 (default) 1 I/O P50: General-purpose I/O port CARD0:Card I/F signal 0 output (#SMRD or #CFCE1) Module BBCU PORT CARD BBCU PORT BBCU PORT BBCU PORT CARD Table I.3.2.3 Input/Output Port and Peripheral Circuit Pin List Pin name P00 SIN0 P01 SOUT0 P02 #SCLK0 P03 #SRDY0 P04 SIN1 P05 SOUT1 P06 #SCLK1 P07 #SRDY1 P10 TM0 P11 TM1 P12 TM2 P13 TM3 P14 TM4 #DMAEND0 P15 TM5 #DMAEND1 P16 TM6 #DMAACK0 P17 TM7 #DMAACK1 P20 SDCKE SIN2 P21 SDCLK SOUT2 P22 #SDCS #SCLK2 P23 #SDRAS #SRDY2 P24 #SDCAS SIN3 I-3-4 Pin No. Function I/O Pull-up PFBGA QFP A8 157 P00: General-purpose I/O port (default) 1 I/O SIN0: Serial I/F Ch.0 data input C8 158 P01: General-purpose I/O port (default) 1 I/O SOUT0: Serial I/F Ch.0 data output D7 159 P02: General-purpose I/O port (default) 1 I/O #SCLK0: Serial I/F Ch.0 clock input/output A7 162 P03: General-purpose I/O port (default) 1 I/O #SRDY0: Serial I/F Ch.0 ready signal input/output C7 163 P04: General-purpose I/O port (default) 1 I/O SIN1: Serial I/F Ch.1 data input B6 166 P05: General-purpose I/O port (default) 1 I/O SOUT1: Serial I/F Ch.1 data output A6 167 P06: General-purpose I/O port (default) 1 I/O #SCLK1: Serial I/F Ch.1 clock input/output C6 168 P07: General-purpose I/O port (default) 1 I/O #SRDY1: Serial I/F Ch.1 ready signal input/output L4 38 P10: General-purpose I/O port (default) 1 I/O TM0: 16-bit timer 0 output L1 39 P11: General-purpose I/O port (default) 1 I/O TM1: 16-bit timer 1 output L2 41 P12: General-purpose I/O port (default) 1 I/O TM2: 16-bit timer 2 output L3 42 P13: General-purpose I/O port (default) 1 I/O TM3: 16-bit timer 3 output M1 43 P14: General-purpose I/O port (default) 1 I/O TM4: 16-bit timer 4 output #DMAEND0: HSDMA Ch.0 end-of-transfer signal output M4 44 P15: General-purpose I/O port (default) 1 I/O TM5: 16-bit timer 5 output #DMAEND1: HSDMA Ch.1 end-of-transfer signal output M2 45 P16: General-purpose I/O port (default) 1 I/O TM6: 16-bit timer 6 output #DMAACK0: HSDMA Ch.0 acknowledge signal output M3 46 P17: General-purpose I/O port (default) 1 I/O TM7: 16-bit timer 7 output #DMAACK1: HSDMA Ch.1 acknowledge signal output F14 124 P20: General-purpose I/O port (default) 1 I/O SDCKE: SDRAM clock enable signal output SIN2: Serial I/F Ch.2 data input D14 131 P21: General-purpose I/O port (default) 1 I/O SDCLK: SDRAM clock output SOUT2: Serial I/F Ch.2 data output G11 125 P22: General-purpose I/O port (default) 1 I/O #SDCS: SDRAM chip enable signal output #SCLK2: Serial I/F Ch.2 clock input/output F12 126 P23: General-purpose I/O port (default) 1 I/O #SDRAS: SDRAM row address strobe signal output #SRDY2: Serial I/F Ch.2 ready signal input/output E13 127 P24: General-purpose I/O port (default) 1 I/O #SDCAS: SDRAM column address strobe signal output SIN3: Serial I/F Ch.3 data input EPSON Module PORT SIO PORT SIO PORT SIO PORT SIO PORT SIO PORT SIO PORT SIO PORT SIO PORT T16 PORT T16 PORT T16 PORT T16 PORT T16 HSDMA PORT T16 HSDMA PORT T16 HSDMA PORT T16 HSDMA PORT EBCU SIO PORT EBCU SIO PORT EBCU SIO PORT EBCU SIO PORT EBCU SIO S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Pin name P25 #SDWE SOUT3 P26 DQML #SCLK3 P27 DQMH #SRDY3 P30 #DMAREQ0 T8UF0 EXCL0 P31 #DMAREQ1 T8UF1 EXCL1 P32 #DMAREQ2 CARD2 EXCL2 P33 #DMAREQ3 CARD3 WDT_CLK P60 #BUSREQ CARD4 P61 #BUSACK CARD5 P62 #BUSGET T8UF2 #ADTRG P64 #WAIT P70 AIN0 P71 AIN1 P72 AIN2 P73 AIN3 P80 #DMAACK2 T8UF3 EXCL3 P81 #DMAACK3 T8UF4 EXCL4 P82 #DMAEND2 EXCL5 DBT P83 #DMAEND3 EXCL6 DTS0 P84 PSC_CLK CARD2 DTS1 Pin No. I/O Pull-up Function PFBGA QFP I/O P25: General-purpose I/O port (default) E12 129 1 #SDWE: SDRAM write signal output SOUT3: Serial I/F Ch.3 data output I/O P26: General-purpose I/O port (default) D12 133 1 DQML: SDRAM data (low byte) input/output mask signal output #SCLK3: Serial I/F Ch.3 clock input/output I/O P27: General-purpose I/O port (default) C14 134 1 DQMH: SDRAM data (high byte) input/output mask signal output #SRDY3: Serial I/F Ch.3 ready signal input/output I/O P30: General-purpose I/O port (default) F2 17 1 #DMAREQ0:HSDMA Ch.0 request input T8UF0: 8-bit timer 0 output EXCL0: 16-bit timer 0 event counter input I/O P31: General-purpose I/O port (default) G3 18 1 #DMAREQ1:HSDMA Ch.1 request input T8UF1: 8-bit timer 1 output EXCL1: 16-bit timer 1 event counter input I/O P32: General-purpose I/O port (default) G1 19 1 #DMAREQ2:HSDMA Ch.2 request input CARD2: Card I/F signal 2 output (#IORD or #SMRD) EXCL2: 16-bit timer 2 event counter input I/O P33: General-purpose I/O port (default) G4 20 1 #DMAREQ3:HSDMA Ch.3 request input CARD3: Card I/F signal 3 output (#IOWR or #SMWR) WDT_CLK: Watchdog timer output I/O P60: General-purpose I/O port (default) H3 21 1 #BUSREQ: Bus release request input CARD4: Card I/F signal 4 output (#OE or #CFCE1) I/O P61: General-purpose I/O port (default) G2 22 1 #BUSACK: Bus acknowledge output CARD5: Card I/F signal 5 output (#WE or #CFCE2) I/O P62: General-purpose I/O port (default) H2 27 1 #BUSGET: Bus status monitor signal output T8UF2: 8-bit timer 2 output #ADTRG: A/D converter trigger input I/O P64: General-purpose I/O port (default) K1 36 1 #WAIT: Wait cycle request input I P70: General-purpose I/O port (default) N1 47 1 AIN0: A/D converter Ch.0 input I P71: General-purpose I/O port (default) N2 48 1 AIN1: A/D converter Ch.1 input I P72: General-purpose I/O port (default) P2 49 1 AIN2: A/D converter Ch.2 input I P73: General-purpose I/O port (default) P3 50 1 AIN3: A/D converter Ch.3 input I/O P80: General-purpose I/O port (default) F4 13 1 #DMAACK2: HSDMA Ch.2 acknowledge signal output T8UF3: 8-bit timer 3 output EXCL3: 16-bit timer 3 event counter input I/O P81: General-purpose I/O port (default) F1 14 1 #DMAACK3: HSDMA Ch.3 acknowledge signal output T8UF4: 8-bit timer 4 output EXCL4: 16-bit timer 4 event counter input I/O P82: General-purpose I/O port (default) D3 5 1 #DMAEND2: HSDMA Ch.2 end-of-transfer signal output EXCL5: 16-bit timer 5 event counter input DBT: DBT signal output for debugging I/O P83: General-purpose I/O port (default) 6 D2 1 #DMAEND3: HSDMA Ch.3 end-of-transfer signal output EXCL6: 16-bit timer 6 event counter input DTS0: DTS0 signal output for debugging I/O P84: General-purpose I/O port (default) 7 D1 1 PSC_CLK: Prescaler clock output CARD2: Card I/F signal 2 output (#IORD or #SMRD) DTS1: DTS1 signal output for debugging S1C33401 TECHNICAL MANUAL EPSON Module PORT EBCU SIO PORT EBCU SIO PORT EBCU SIO PORT HSDMA T8 T16 PORT HSDMA T8 T16 PORT HSDMA CARD T16 PORT HSDMA CARD WDT PORT BBCU CARD PORT BBCU CARD PORT BBCU T8 ADC PORT BBCU PORT ADC PORT ADC PORT ADC PORT ADC PORT HSDMA T8 T16 PORT HSDMA T8 T16 PORT HSDMA T16 DBG PORT HSDMA T16 DBG PORT PSC CARD DBG I-3-5 I Pin I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Pin name P85 CMU_CLK CARD3 DTS2 P86 TM8 CARD0 DTS3 P87 TM9 CARD1 DTS4 P90 SIN2 EXCL7 DTD0 P91 SOUT2 EXCL8 DTD1 P92 #SCLK2 EXCL9 DTD2 P93 #SRDY2 R/W DTD3 P94 SIN3 ACST DTD4 P95 SOUT3 ASTB DTD5 P96 #SCLK3 CARD4 DTD6 P97 #SRDY3 CARD5 DTD7 Pin No. I/O Pull-up QFP PFBGA I/O 1 P85: 8 E3 CMU_CLK: CARD3: DTS2: I/O 1 P86: 10 E1 TM8: CARD0: DTS3: I/O 1 P87: 11 F3 TM9: CARD1: DTS4: I/O 1 P90: 179 A3 SIN2: EXCL7: DTD0: I/O 1 P91: 180 B3 SOUT2: EXCL8: DTD1: I/O 1 P92: 181 A2 #SCLK2: EXCL9: DTD2: I/O 1 P93: 182 B2 #SRDY2: R/W: DTD3: I/O P94: 1 183 C4 SIN3: ACST: DTD4: I/O P95: 1 1 B1 SOUT3: ASTB: DTD5: I/O P96: 1 2 C2 #SCLK3: CARD4: DTD6: I/O P97: 1 3 C1 #SRDY3: CARD5: DTD7: Function Module General-purpose I/O port (default) CMU external clock output Card I/F signal 3 output (#IOWR or #SMWR) DTS2 signal output for debugging General-purpose I/O port (default) 16-bit timer 8 output Card I/F signal 0 output (#SMRD or #CFCE1) DTS3 signal output for debugging General-purpose I/O port (default) 16-bit timer 9 output Card I/F signal 1 output (#SMWR or #CFCE2) DTS4 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.2 data input 16-bit timer 7 event counter input DTD0 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.2 data output 16-bit timer 8 event counter input DTD1 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.2 clock input/output 16-bit timer 9 event counter input DTD2 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.2 ready signal input/output Read/Write status output DTD3 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.3 data input Bus access status output DTD4 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.3 data output Address strobe output DTD5 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.3 clock input/output Card I/F signal 4 output (#OE or #CFCE1) DTD6 signal output for debugging General-purpose I/O port (default) Serial I/F Ch.3 ready signal input/output Card I/F signal 5 output (#WE or #CFCE2) DTD7 signal output for debugging PORT CMU CARD DBG PORT T16 CARD DBG PORT T16 CARD DBG PORT SIO T16 DBG PORT SIO T16 DBG PORT SIO T16 DBG PORT SIO BBCU DBG PORT SIO BBCU DBG PORT SIO BBCU DBG PORT SIO CARD DBG PORT SIO CARD DBG Table I.3.2.4 Debug Pin List Pin name DSIO DCLK DST2 DST0 P65 DST1 P66 DPCO P67 I-3-6 Pin No. I/O QFP PFBGA I/O 169 C5 O (H) 176 A4 O (L) 172 D5 I/O 170 B5 (H) I/O 171 A5 (H) I/O 174 B4 (H) Pull-up Pull-up - - 1 1 1 Function Serial input/output for debugging DCLK signal output for debugging DST2 signal output for debugging DST0: DST0 signal output for debugging (default) P65: General-purpose I/O port DST1: DST1 signal output for debugging (default) P66: General-purpose I/O port DPCO: DPCO signal output for debugging (default) P67: General-purpose I/O port EPSON Module DBG DBG DBG DBG PORT DBG PORT DBG PORT S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Table I.3.2.5 Other Pin List OSC1 Pin No. PFBGA QFP A13 141 OSC2 OSC3 142 149 A12 A10 O I OSC4 VCP CMU_CLK P63 BCLK T8UF5 #RESET #NMI TST0 TST1 BURNIN SCANEN #STBY 150 144 28 A9 C11 H1 O O I/O 155 156 152 153 147 148 140 D8 B8 C9 B9 C10 B10 B13 I I I I I I I Pin name I/O I PullFunction up/down Low speed (OSC1) oscillator input - (32 kHz crystal or external clock input with VDD level) Low speed (OSC1) oscillator output - High speed (OSC3) oscillator input - (crystal/ceramic or external clock input with VDD level) High speed (OSC3) oscillator output - PLL analog monitor (used for current monitor) - CMU_CLK: CMU external clock output (default) 1 P63: General-purpose I/O port BCLK: Bus clock output T8UF5: 8-bit timer 5 output Pull-up Initial reset input pin Pull-up NMI request input pin Pull-down Test input pin 0 (Connect to VSS during normal operation) Pull-down Test input pin 1 (Connect to VSS during normal operation) Wafer level burn-in test enable input - Pull-down Scan test enable input Standby input for disabling C33 operation (except RTC) - I Module OSC OSC OSC OSC CMU CMU PORT BBCU T8 CMU CMU - - - - RTC 1: These pins can have pull-ups enabled or disabled by setting the pin control registers. (Pull-ups are enabled by default.) 2: These pins come with a bus hold latch. Notes: * The # prefixed to pin names indicates that input/output signals of the pin are active low. * The pin names and I/O printed in boldface denote the default pin (signal) name and default input/output direction. * (H) and (L) for I/O indicate the default output level. This is only indicated for signals whose level is fixed high or low when the chip is initially reset. * The input level must be VDD only for the OSC1 and OSC3 pins. Input levels for other pins should be VDDE (AVDD, TMVDD) level. S1C33401 TECHNICAL MANUAL EPSON I-3-7 Pin I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.3 Switching Over the Multiplexed Pin Functions I.3.3.1 Pin Function Select Bits Each pin is assigned one to four functions, as listed in Table I.3.3.1.1. When the chip is powered on or cold-reset, each pin defaults to function 0. If any pin must be used for other than this default function, select the desired function by writing data to the corresponding pin function select bits. The pin function selected is not altered by a hot reset. Table I.3.3.1.1 List of Pin Function Select Bits Pin function 0 OSC1 OSC2 OSC3 OSC4 VCP #RESET #NMI DSIO DCLK DST2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 I-3-8 Pin function 1 Pin function 2 Pin function 3 Debug function Function select bit CFP47[1:0] (D[7:6]/0x40369) CFP46[1:0] (D[5:4]/0x40369) CFP45[1:0] (D[3:2]/0x40369) CFP44[1:0] (D[1:0]/0x40369) CFP43[1:0] (D[7:6]/0x40368) CFP42[1:0] (D[5:4]/0x40368) CFP41[1:0] (D[3:2]/0x40368) CFP40[1:0] (D[1:0]/0x40368) P47 P46 P45 P44 P43 P42 P41 P40 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Pin function 0 #RD #WRL #WRH #BSL #CE10 #CE4 #CE5 #CE6 #CE7 #CE8 #CE9 #CE11 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P60 P61 P62 CMU_CLK P64 P65 P66 P67 P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 Pin function 1 Pin function 2 Pin function 3 Debug function I Function select bit Pin P50 P51 P52 P53 P54 P55 P56 SIN0 SOUT0 #SCLK0 #SRDY0 SIN1 SOUT1 #SCLK1 #SRDY1 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 SDCKE SDCLK #SDCS #SDRAS #SDCAS #SDWE DQML DQMH #DMAREQ0 #DMAREQ1 #DMAREQ2 #DMAREQ3 #BUSREQ #BUSACK #BUSGET P63 #WAIT CARD0 CFP50[1:0] (D[1:0]/0x4036A) CFP51[1:0] (D[3:2]/0x4036A) CFP52[1:0] (D[5:4]/0x4036A) CFP53[1:0] (D[7:6]/0x4036A) CFP54[1:0] (D[1:0]/0x4036B) CFP55[1:0] (D[3:2]/0x4036B) CFP56[1:0] (D[5:4]/0x4036B) CFP00[1:0] (D[1:0]/0x40360) CFP01[1:0] (D[3:2]/0x40360) CFP02[1:0] (D[5:4]/0x40360) CFP03[1:0] (D[7:6]/0x40360) CFP04[1:0] (D[1:0]/0x40361) CFP05[1:0] (D[3:2]/0x40361) CFP06[1:0] (D[5:4]/0x40361) CFP07[1:0] (D[7:6]/0x40361) CFP10[1:0] (D[1:0]/0x40362) CFP11[1:0] (D[3:2]/0x40362) CFP12[1:0] (D[5:4]/0x40362) CFP13[1:0] (D[7:6]/0x40362) CFP14[1:0] (D[1:0]/0x40363) CFP15[1:0] (D[3:2]/0x40363) CFP16[1:0] (D[5:4]/0x40363) CFP17[1:0] (D[7:6]/0x40363) CFP20[1:0] (D[1:0]/0x40364) CFP21[1:0] (D[3:2]/0x40364) CFP22[1:0] (D[5:4]/0x40364) CFP23[1:0] (D[7:6]/0x40364) CFP24[1:0] (D[1:0]/0x40365) CFP25[1:0] (D[3:2]/0x40365) CFP26[1:0] (D[5:4]/0x40365) CFP27[1:0] (D[7:6]/0x40365) CFP30[1:0] (D[1:0]/0x40366) CFP31[1:0] (D[3:2]/0x40366) CFP32[1:0] (D[5:4]/0x40366) CFP33[1:0] (D[7:6]/0x40366) CFP60[1:0] (D[1:0]/0x4036C) CFP61[1:0] (D[3:2]/0x4036C) CFP62[1:0] (D[5:4]/0x4036C) CFP63[1:0] (D[7:6]/0x4036C) CFP64[1:0] (D[1:0]/0x4036D) CARD1 #DMAEND0 #DMAEND1 #DMAACK0 #DMAACK1 SIN2 SOUT2 #SCLK2 #SRDY2 SIN3 SOUT3 #SCLK3 #SRDY3 T8UF0 T8UF1 CARD2 CARD3 CARD4 CARD5 T8UF2 BCLK EXCL0 EXCL1 EXCL2 WDT_CLK #ADTRG T8UF5 DST0 DST1 DPCO AIN0 AIN1 AIN2 AIN3 #DMAACK2 #DMAACK3 #DMAEND2 #DMAEND3 PSC_CLK CMU_CLK TM8 TM9 SIN2 SOUT2 S1C33401 TECHNICAL MANUAL T8UF3 T8UF4 EXCL5 EXCL6 CARD2 CARD3 CARD0 CARD1 EXCL7 EXCL8 EXCL3 EXCL4 DBT DTS0 DTS1 DTS2 DTS3 DTS4 DTD0 DTD1 EPSON CFP70[1:0] (D[1:0]/0x4036E) CFP71[1:0] (D[3:2]/0x4036E) CFP72[1:0] (D[5:4]/0x4036E) CFP73[1:0] (D[7:6]/0x4036E) CFP80[1:0] (D[1:0]/0x40370) CFP81[1:0] (D[3:2]/0x40370) CFP82[1:0] (D[5:4]/0x40370) CFP83[1:0] (D[7:6]/0x40370) CFP84[1:0] (D[1:0]/0x40371) CFP85[1:0] (D[3:2]/0x40371) CFP86[1:0] (D[5:4]/0x40371) CFP87[1:0] (D[7:6]/0x40371) CFP90[1:0] (D[1:0]/0x40372) CFP91[1:0] (D[3:2]/0x40372) I-3-9 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Pin function 0 P92 P93 P94 P95 P96 P97 TST0 TST1 BURNIN SCANEN #STBY Pin function 1 #SCLK2 #SRDY2 SIN3 SOUT3 #SCLK3 #SRDY3 Pin function 2 EXCL9 R/W ACST ASTB CARD4 CARD5 Pin function 3 Debug function DTD2 DTD3 DTD4 DTD5 DTD6 DTD7 Function select bit CFP92[1:0] (D[5:4]/0x40372) CFP93[1:0] (D[7:6]/0x40372) CFP94[1:0] (D[1:0]/0x40373) CFP95[1:0] (D[3:2]/0x40373) CFP96[1:0] (D[5:4]/0x40373) CFP97[1:0] (D[7:6]/0x40373) * The set values 0 to 3 of the pin function select bits correspond to functions 0 to 3, respectively. * Pins P65 to P67 operate as debugging pins when the debug function of PC trace is enabled (Enabled by default). Similarly, pins P82 to P97 operate as debugging pins when the debug function of bus trace is enabled (Disabled by default). The functions of these pins are switched to debugging use, regardless of how the function select bits are set. Therefore, while the PC trace function is being used during debugging, the other functions of respective pins cannot be used. The debug function (PC trace, bus trace) can be enabled/disabled using a register in the debug unit. When using the P65 to P67 pins as general-purpose I/O ports, set DPCTOE (D0/0x402EC) to 0 (PC trace output disabled). (It is set at 1 by default) When using the P82 to P97 pins as general-purpose I/O ports or peripheral I/O ports, keep DBTOE (D1/0x402EC) as 0 (bus trace output disabled, default setting). It is necessary to remove write protection of these control bits by writing 0x59 to DBGOUTP[7:0] (D[7:0]/ 0x402E8) before the bit can be altered. After the bit is altered, write a value other than 0x59 to DBGOUTP[7:0] (D[7:0]/0x402E8) to protect address 0x402EC against unnecessary writings. DPCTOE: PC Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D0/0x402EC) DBTOE: Bus Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D1/0x402EC) DBGOUTP[7:0]: Debug Signal Output Control Register Write-Protect flag Bits in the Debug Signal Output Control Write-Protect Register (D[7:0]/0x402E8) * CARD0 to CARD5 are the output pins for card interfaces. The functions of respective pins can be selected according to the card interface used, as listed in Table I.3.3.1.2. Use the Card I/F Output Port Configuration Register (0x40302) to select the functions of these pins. For details of the card interfaces and output signals, see Section IV.9, "Card Interface (CARD)." Table I.3.3.1.2 Relationship between Ports and Card Interface Signals Pin name Function 0 (default) Function 1 Function select bit CARD0 CARD1 CARD2 CARD3 CARD4 CARD5 #SMRD #SMWR #IORD #IOWR #OE #WE #CFCE1 #CFCE2 #SMRD #SMWR #CFCE1 #CFCE2 CARDIO0 (D0/0x40302) CARDIO1 (D1/0x40302) CARDIO2 (D2/0x40302) CARDIO3 (D3/0x40302) CARDIO4 (D4/0x40302) CARDIO5 (D5/0x40302) #SMRD, #SMWR: Output pins for SmartMedia (NAND flash) #CFCE1, #CFCE2: Output pins for CompactFlash #IORD, #IOWR, #OE, #WE: Output pins for PC Card CARDIOx: CARDx Port Function Select Bit in the Card I/F Output Port Configuration Register (Dx/0x40302) I-3-10 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.3.2 List of Port Function Select Registers I Table I.3.3.2.1 List of Port Function Select Registers Address 0x00040360 0x00040361 0x00040362 0x00040363 0x00040364 0x00040365 0x00040366 0x00040368 0x00040369 0x0004036A 0x0004036B 0x0004036C 0x0004036D 0x0004036E 0x00040370 0x00040371 0x00040372 0x00040373 Register name P00-P03 Port Function Select Register (pP0_03_CFP) P04-P07 Port Function Select Register (pP0_47_CFP) P10-P13 Port Function Select Register (pP1_03_CFP) P14-P17 Port Function Select Register (pP1_47_CFP) P20-P23 Port Function Select Register (pP2_03_CFP) P24-P27 Port Function Select Register (pP2_47_CFP) P30-P33 Port Function Select Register (pP3_03_CFP) P40-P43 Port Function Select Register (pP4_03_CFP) P44-P47 Port Function Select Register (pP4_47_CFP) P50-P53 Port Function Select Register (pP5_03_CFP) P54-P56 Port Function Select Register (pP5_46_CFP) P60-P63 Port Function Select Register (pP6_03_CFP) P64-P67 Port Function Select Register (pP6_47_CFP) P70-P73 Port Function Select Register (pP7_03_CFP) P80-P83 Port Function Select Register (pP8_03_CFP) P84-P87 Port Function Select Register (pP8_47_CFP) P90-P93 Port Function Select Register (pP9_03_CFP) P94-P97 Port Function Select Register (pP9_47_CFP) Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Function Selects P00-P03 port pin functions. Selects P04-P07 port pin functions. Selects P10-P13 port pin functions. Selects P14-P17 port pin functions. Selects P20-P23 port pin functions. Selects P24-P27 port pin functions. Selects P30-P33 port pin functions. Selects P40-P43 port pin functions. Selects P44-P47 port pin functions. Selects P50-P53 port pin functions. Selects P54-P56 port pin functions. Selects P60-P63 port pin functions. Selects P64-P67 port pin functions. Selects P70-P73 port pin functions. Selects P80-P83 port pin functions. Selects P84-P87 port pin functions. Selects P90-P93 port pin functions. Selects P94-P97 port pin functions. Pin The following describes each port function select register. The port function select registers are mapped to the 8-bit device area at addresses 0x40360 to 0x40373, and can be accessed in units of bytes. S1C33401 TECHNICAL MANUAL EPSON I-3-11 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40360: P00-P03 Port Function Select Register (pP0_03_CFP) Register name Address Bit Name 0040360 (B) D7 D6 CFP031 CFP030 P03 port extended function D5 D4 CFP021 CFP020 P02 port extended function D3 D2 CFP011 CFP010 P01 port extended function D1 D0 CFP001 CFP000 P00 port extended function P00-P03 port function select register (pP0_03_CFP) Function Setting CFP03[1:0] 1 01 00 CFP02[1:0] 1 01 00 CFP01[1:0] 1 01 00 CFP00[1:0] 1 01 00 Function reserved #SRDY0 P03 Function reserved #SCLK0 P02 Function reserved SOUT0 P01 Function reserved SIN0 P00 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P00 to P03. D[7:6] CFP03[1:0]: P03 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): #SRDY0 00 (R/W): P03 (default) D[5:4] CFP02[1:0]: P02 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): #SCLK0 00 (R/W): P02 (default) D[3:2] CFP01[1:0]: P01 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): SOUT0 00 (R/W): P01 (default) D[1:0] CFP00[1:0]: P00 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): SIN0 00 (R/W): P00 (default) I-3-12 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40361: P04-P07 Port Function Select Register (pP0_47_CFP) Register name Address Bit Name 0040361 (B) D7 D6 CFP071 CFP070 P04-P07 port function select register (pP0_47_CFP) Function P07 port extended function D5 D4 CFP061 CFP060 P06 port extended function D3 D2 CFP051 CFP050 P05 port extended function D1 D0 CFP041 CFP040 P04 port extended function Setting CFP07[1:0] 1 01 00 CFP06[1:0] 1 01 00 CFP05[1:0] 1 01 00 CFP04[1:0] 1 01 00 Function reserved #SRDY1 P07 Function reserved #SCLK1 P06 Function reserved SOUT1 P05 Function reserved SIN1 P04 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P04 to P07. D[7:6] CFP07[1:0]: P07 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): #SRDY1 00 (R/W): P07 (default) D[5:4] CFP06[1:0]: P06 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): #SCLK1 00 (R/W): P06 (default) D[3:2] CFP05[1:0]: P05 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): SOUT1 00 (R/W): P05 (default) D[1:0] CFP04[1:0]: P04 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): SIN1 00 (R/W): P04 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-13 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40362: P10-P13 Port Function Select Register (pP1_03_CFP) Register name Address Bit Name 0040362 (B) D7 D6 CFP131 CFP130 P13 port extended function D5 D4 CFP121 CFP120 P12 port extended function D3 D2 CFP111 CFP110 P11 port extended function D1 D0 CFP101 CFP100 P10 port extended function P10-P13 port function select register (pP1_03_CFP) Function Setting CFP13[1:0] 1 01 00 CFP12[1:0] 1 01 00 CFP11[1:0] 1 01 00 CFP10[1:0] 1 01 00 Function reserved TM3 P13 Function reserved TM2 P12 Function reserved TM1 P11 Function reserved TM0 P10 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P10 to P13. D[7:6] CFP13[1:0]: P13 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): TM3 00 (R/W): P13 (default) D[5:4] CFP12[1:0]: P12 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): TM2 00 (R/W): P12 (default) D[3:2] CFP11[1:0]: P11 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): TM1 00 (R/W): P11 (default) D[1:0] CFP10[1:0]: P10 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): TM0 00 (R/W): P10 (default) I-3-14 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40363: P14-P17 Port Function Select Register (pP1_47_CFP) Register name Address Bit Name 0040363 (B) D7 D6 CFP171 CFP170 P14-P17 port function select register (pP1_47_CFP) Function P17 port extended function D5 D4 CFP161 CFP160 P16 port extended function D3 D2 CFP151 CFP150 P15 port extended function D1 D0 CFP141 CFP140 P14 port extended function Setting CFP17[1:0] 11 10 01 00 CFP16[1:0] 11 10 01 00 CFP15[1:0] 11 10 01 00 CFP14[1:0] 11 10 01 00 Function reserved #DMAACK1 TM7 P17 Function reserved #DMAACK0 TM6 P16 Function reserved #DMAEND1 TM5 P15 Function reserved #DMAEND0 TM4 P14 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P14 to P17. D[7:6] CFP17[1:0]: P17 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #DMAACK1 01 (R/W): TM7 00 (R/W): P17 (default) D[5:4] CFP16[1:0]: P16 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #DMAACK0 01 (R/W): TM6 00 (R/W): P16 (default) D[3:2] CFP15[1:0]: P15 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #DMAEND1 01 (R/W): TM5 00 (R/W): P15 (default) D[1:0] CFP14[1:0]: P14 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #DMAEND0 01 (R/W): TM4 00 (R/W): P14 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-15 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40364: P20-P23 Port Function Select Register (pP2_03_CFP) Register name Address Bit Name 0040364 (B) D7 D6 CFP231 CFP230 P23 port extended function D5 D4 CFP221 CFP220 P22 port extended function D3 D2 CFP211 CFP210 P21 port extended function D1 D0 CFP201 CFP200 P20 port extended function P20-P23 port function select register (pP2_03_CFP) Function Setting CFP23[1:0] 11 10 01 00 CFP22[1:0] 11 10 01 00 CFP21[1:0] 11 10 01 00 CFP20[1:0] 11 10 01 00 Function reserved #SRDY2 #SDRAS P23 Function reserved #SCLK2 #SDCS P22 Function reserved SOUT2 SDCLK P21 Function reserved SIN2 SDCKE P20 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P20 to P23. D[7:6] CFP23[1:0]: P23 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #SRDY2 01 (R/W): #SDRAS 00 (R/W): P23 (default) D[5:4] CFP22[1:0]: P22 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #SCLK2 01 (R/W): #SDCS 00 (R/W): P22 (default) D[3:2] CFP21[1:0]: P21 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): SOUT2 01 (R/W): SDCLK 00 (R/W): P21 (default) D[1:0] CFP20[1:0]: P20 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): SIN2 01 (R/W): SDCKE 00 (R/W): P20 (default) I-3-16 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40365: P24-P27 Port Function Select Register (pP2_47_CFP) Register name Address Bit Name 0040365 (B) D7 D6 CFP271 CFP270 P24-P27 port function select register (pP2_47_CFP) Function P27 port extended function D5 D4 CFP261 CFP260 P26 port extended function D3 D2 CFP251 CFP250 P25 port extended function D1 D0 CFP241 CFP240 P24 port extended function Setting CFP27[1:0] 11 10 01 00 CFP26[1:0] 11 10 01 00 CFP25[1:0] 11 10 01 00 CFP24[1:0] 11 10 01 00 Function reserved #SRDY3 DQMH P27 Function reserved #SCLK3 DQML P26 Function reserved SOUT3 #SDWE P25 Function reserved SIN3 #SDCAS P24 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P24 to P27. D[7:6] CFP27[1:0]: P27 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #SRDY3 01 (R/W): DQMH 00 (R/W): P27 (default) D[5:4] CFP26[1:0]: P26 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): #SCLK3 01 (R/W): DQML 00 (R/W): P26 (default) D[3:2] CFP25[1:0]: P25 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): SOUT3 01 (R/W): #SDWE 00 (R/W): P25 (default) D[1:0] CFP24[1:0]: P24 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): SIN3 01 (R/W): #SDCAS 00 (R/W): P24 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-17 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40366: P30-P33 Port Function Select Register (pP3_03_CFP) Register name Address Bit Name 0040366 (B) D7 D6 CFP331 CFP330 P33 port extended function D5 D4 CFP321 CFP320 P32 port extended function D3 D2 CFP311 CFP310 P31 port extended function D1 D0 CFP301 CFP300 P30 port extended function P30-P33 port function select register (pP3_03_CFP) Function Setting CFP33[1:0] 11 10 01 00 CFP32[1:0] 11 10 01 00 CFP31[1:0] 11 10 01 00 CFP30[1:0] 11 10 01 00 Init. R/W Function WDT_CLK CARD3 #DMAREQ3 P33 Function EXCL2 CARD2 #DMAREQ2 P32 Function EXCL1 T8UF1 #DMAREQ1 P31 Function EXCL0 T8UF0 #DMAREQ0 P30 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P30 to P33. D[7:6] CFP33[1:0]: P33 Port Extended Function Select Bits 11 (R/W): WDT_CLK 10 (R/W): CARD3 01 (R/W): #DMAREQ3 00 (R/W): P33 (default) D[5:4] CFP32[1:0]: P32 Port Extended Function Select Bits 11 (R/W): EXCL2 10 (R/W): CARD2 01 (R/W): #DMAREQ2 00 (R/W): P32 (default) D[3:2] CFP31[1:0]: P31 Port Extended Function Select Bits 11 (R/W): EXCL1 10 (R/W): T8UF1 01 (R/W): #DMAREQ1 00 (R/W): P31 (default) D[1:0] CFP30[1:0]: P30 Port Extended Function Select Bits 11 (R/W): EXCL0 10 (R/W): T8UF0 01 (R/W): #DMAREQ0 00 (R/W): P30 (default) I-3-18 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40368: P40-P43 Port Function Select Register (pP4_03_CFP) Register name Address Bit Name 0040368 (B) D7 D6 CFP431 CFP430 P40-P43 port function select register (pP4_03_CFP) Function P43 port extended function D5 D4 CFP421 CFP420 P42 port extended function D3 D2 CFP411 CFP410 P41 port extended function D1 D0 CFP401 CFP400 P40 port extended function Setting CFP43[1:0] 1 01 00 CFP42[1:0] 1 01 00 CFP41[1:0] 1 01 00 CFP40[1:0] 1 01 00 Function reserved P43 A22 Function reserved P42 A23 Function reserved P41 A24 Function reserved P40 A25 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P40 to P43. D[7:6] CFP43[1:0]: P43 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P43 00 (R/W): A22 (default) D[5:4] CFP42[1:0]: P42 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P42 00 (R/W): A23 (default) D[3:2] CFP41[1:0]: P41 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P41 00 (R/W): A24 (default) D[1:0] CFP40[1:0]: P40 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P40 00 (R/W): A25 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-19 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40369: P44-P47 Port Function Select Register (pP4_47_CFP) Register name Address Bit Name 0040369 (B) D7 D6 CFP471 CFP470 P47 port extended function D5 D4 CFP461 CFP460 P46 port extended function D3 D2 CFP451 CFP450 P45 port extended function D1 D0 CFP441 CFP440 P44 port extended function P44-P47 port function select register (pP4_47_CFP) Function Setting CFP47[1:0] 1 01 00 CFP46[1:0] 1 01 00 CFP45[1:0] 1 01 00 CFP44[1:0] 1 01 00 Function reserved P47 A18 Function reserved P46 A19 Function reserved P45 A20 Function reserved P44 A21 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P44 to P47. D[7:6] CFP47[1:0]: P47 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P47 00 (R/W): A18 (default) D[5:4] CFP46[1:0]: P46 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P46 00 (R/W): A19 (default) D[3:2] CFP45[1:0]: P45 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P45 00 (R/W): A20 (default) D[1:0] CFP44[1:0]: P44 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P44 00 (R/W): A21 (default) I-3-20 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x4036A: P50-P53 Port Function Select Register (pP5_03_CFP) Register name Address Bit Name 004036A (B) D7 D6 CFP531 CFP530 P50-P53 port function select register (pP5_03_CFP) Function P53 port extended function D5 D4 CFP521 CFP520 P52 port extended function D3 D2 CFP511 CFP510 P51 port extended function D1 D0 CFP501 CFP500 P50 port extended function Setting CFP53[1:0] 11 10 01 00 CFP52[1:0] 1 01 00 CFP51[1:0] 1 01 00 CFP50[1:0] 11 10 01 00 Function reserved CARD1 P53 #CE7 Function reserved P52 #CE6 Function reserved P51 #CE5 Function reserved CARD0 P50 #CE4 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P50 to P53. D[7:6] CFP53[1:0]: P53 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD1 01 (R/W): P53 00 (R/W): #CE7 (default) D[5:4] CFP52[1:0]: P52 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P52 00 (R/W): #CE6 (default) D[3:2] CFP51[1:0]: P51 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P51 00 (R/W): #CE5 (default) D[1:0] CFP50[1:0]: P50 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD0 01 (R/W): P50 00 (R/W): #CE4 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-21 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x4036B: P54-P56 Port Function Select Register (pP5_46_CFP) Register name Address P54-P56 port function select register (pP5_46_CFP) Bit Name Function 004036B D7-6 - D5 CFP561 (B) D4 CFP560 reserved P56 port extended function D3 D2 CFP551 CFP550 P55 port extended function D1 D0 CFP541 CFP540 P54 port extended function Setting - CFP56[1:0] 1 01 00 CFP55[1:0] 1 01 00 CFP54[1:0] 1 01 00 Function reserved P56 #CE11 Function reserved P55 #CE9 Function reserved P54 #CE8 Init. R/W Remarks - 0 0 - 0 when being read. R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P54 to P56. D[7:6] Reserved D[5:4] CFP56[1:0]: P56 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P56 00 (R/W): #CE11 (default) D[3:2] CFP55[1:0]: P55 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P55 00 (R/W): #CE9 (default) D[1:0] CFP54[1:0]: P54 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): P54 00 (R/W): #CE8 (default) I-3-22 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x4036C: P60-P63 Port Function Select Register (pP6_03_CFP) Register name Address Bit Name 004036C (B) D7 D6 CFP631 CFP630 P60-P63 port function select register (pP6_03_CFP) Function P63 port extended function D5 D4 CFP621 CFP620 P62 port extended function D3 D2 CFP611 CFP610 P61 port extended function D1 D0 CFP601 CFP600 P60 port extended function Setting CFP63[1:0] 11 10 01 00 CFP62[1:0] 11 10 01 00 CFP61[1:0] 11 10 01 00 CFP60[1:0] 11 10 01 00 Function T8UF5 BCLK P63 CMU_CLK Function #ADTRG T8UF2 #BUSGET P62 Function reserved CARD5 #BUSACK P61 Function reserved CARD4 #BUSREQ P60 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P60 to P63. D[7:6] CFP63[1:0]: P63 Port Extended Function Select Bits 11 (R/W): T8UF5 10 (R/W): BCLK 01 (R/W): P63 00 (R/W): CMU_CLK (default) D[5:4] CFP62[1:0]: P62 Port Extended Function Select Bits 11 (R/W): #ADTRG 10 (R/W): T8UF2 01 (R/W): #BUSGET 00 (R/W): P62 (default) D[3:2] CFP61[1:0]: P61 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD5 01 (R/W): #BUSACK 00 (R/W): P61 (default) D[1:0] CFP60[1:0]: P60 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD4 01 (R/W): #BUSREQ 00 (R/W): P60 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-23 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x4036D: P64-P67 Port Function Select Register (pP6_47_CFP) Register name Address P64-P67 port function select register (pP6_47_CFP) Bit Name 004036D D7-2 - D1 CFP641 (B) D0 CFP640 Function reserved P64 port extended function Setting - CFP64[1:0] 1 01 00 Function reserved #WAIT P64 Init. R/W - 0 0 Remarks - 0 when being read. R/W This register selects the function of port P64. D[7:2] Reserved D[1:0] CFP64[1:0]: P64 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): #WAIT 00 (R/W): P64 (default) I-3-24 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x4036E: P70-P73 Port Function Select Register (pP7_03_CFP) Register name Address Bit Name 004036E (B) D7 D6 CFP731 CFP730 P70-P73 port function select register (pP7_03_CFP) Function P73 port extended function D5 D4 CFP721 CFP720 P72 port extended function D3 D2 CFP711 CFP710 P71 port extended function D1 D0 CFP701 CFP700 P70 port extended function Setting CFP73[1:0] 1 01 00 CFP72[1:0] 1 01 00 CFP71[1:0] 1 01 00 CFP70[1:0] 1 01 00 Function reserved AIN3 P73 Function reserved AIN2 P72 Function reserved AIN1 P71 Function reserved AIN0 P70 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P70 to P73. D[7:6] CFP73[1:0]: P73 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): AIN3 00 (R/W): P73 (default) D[5:4] CFP72[1:0]: P72 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): AIN2 00 (R/W): P72 (default) D[3:2] CFP71[1:0]: P71 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): AIN1 00 (R/W): P71 (default) D[1:0] CFP70[1:0]: P70 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): Reserved 01 (R/W): AIN0 00 (R/W): P70 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-25 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40370: P80-P83 Port Function Select Register (pP8_03_CFP) Register name Address Bit Name 0040370 (B) D7 D6 CFP831 CFP830 P83 port extended function D5 D4 CFP821 CFP820 P82 port extended function D3 D2 CFP811 CFP810 P81 port extended function D1 D0 CFP801 CFP800 P80 port extended function P80-P83 port function select register (pP8_03_CFP) Function Setting CFP83[1:0] 11 10 01 00 CFP82[1:0] 11 10 01 00 CFP81[1:0] 11 10 01 00 CFP80[1:0] 11 10 01 00 Init. R/W Function reserved EXCL6 #DMAEND3 P83 Function reserved EXCL5 #DMAEND2 P82 Function EXCL4 T8UF4 #DMAACK3 P81 Function EXCL3 T8UF3 #DMAACK2 P80 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P80 to P83. D[7:6] CFP83[1:0]: P83 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): EXCL6 01 (R/W): #DMAEND3 00 (R/W): P83 (default) D[5:4] CFP82[1:0]: P82 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): EXCL5 01 (R/W): #DMAEND2 00 (R/W): P82 (default) D[3:2] CFP81[1:0]: P81 Port Extended Function Select Bits 11 (R/W): EXCL4 10 (R/W): T8UF4 01 (R/W): #DMAACK3 00 (R/W): P81 (default) D[1:0] CFP80[1:0]: P80 Port Extended Function Select Bits 11 (R/W): EXCL3 10 (R/W): T8UF3 01 (R/W): #DMAACK2 00 (R/W): P80 (default) I-3-26 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40371: P84-P87 Port Function Select Register (pP8_47_CFP) Register name Address Bit Name 0040371 (B) D7 D6 CFP871 CFP870 P84-P87 port function select register (pP8_47_CFP) Function P87 port extended function D5 D4 CFP861 CFP860 P86 port extended function D3 D2 CFP851 CFP850 P85 port extended function D1 D0 CFP841 CFP840 P84 port extended function Setting CFP87[1:0] 11 10 01 00 CFP86[1:0] 11 10 01 00 CFP85[1:0] 11 10 01 00 CFP84[1:0] 11 10 01 00 Function reserved CARD1 TM9 P87 Function reserved CARD0 TM8 P86 Function reserved CARD3 CMU_CLK P85 Function reserved CARD2 PSC_CLK P84 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P84 to P87. D[7:6] CFP87[1:0]: P87 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD1 01 (R/W): TM9 00 (R/W): P87 (default) D[5:4] CFP86[1:0]: P86 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD0 01 (R/W): TM8 00 (R/W): P86 (default) D[3:2] CFP85[1:0]: P85 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD3 01 (R/W): CMU_CLK 00 (R/W): P85 (default) D[1:0] CFP84[1:0]: P84 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD2 01 (R/W): PSC_CLK 00 (R/W): P84 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-27 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40372: P90-P93 Port Function Select Register (pP9_03_CFP) Register name Address Bit Name 0040372 (B) D7 D6 CFP931 CFP930 P93 port extended function D5 D4 CFP921 CFP920 P92 port extended function D3 D2 CFP911 CFP910 P91 port extended function D1 D0 CFP901 CFP900 P90 port extended function P90-P93 port function select register (pP9_03_CFP) Function Setting CFP93[1:0] 11 10 01 00 CFP92[1:0] 11 10 01 00 CFP91[1:0] 11 10 01 00 CFP90[1:0] 11 10 01 00 Function reserved R/W #SRDY2 P93 Function reserved EXCL9 #SCLK2 P92 Function reserved EXCL8 SOUT2 P91 Function reserved EXCL7 SIN2 P90 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks This register selects the functions of ports P90 to P93. D[7:6] CFP93[1:0]: P93 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): R/W 01 (R/W): #SRDY2 00 (R/W): P93 (default) D[5:4] CFP92[1:0]: P92 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): EXCL9 01 (R/W): #SCLK2 00 (R/W): P92 (default) D[3:2] CFP91[1:0]: P91 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): EXCL8 01 (R/W): SOUT2 00 (R/W): P91 (default) D[1:0] CFP90[1:0]: P90 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): EXCL7 01 (R/W): SIN2 00 (R/W): P90 (default) I-3-28 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION 0x40373: P94-P97 Port Function Select Register (pP9_47_CFP) Register name Address Bit Name 0040373 (B) D7 D6 CFP971 CFP970 P94-P97 port function select register (pP9_47_CFP) Function P97 port extended function D5 D4 CFP961 CFP960 P96 port extended function D3 D2 CFP951 CFP950 P95 port extended function D1 D0 CFP941 CFP940 P94 port extended function Setting CFP97[1:0] 11 10 01 00 CFP96[1:0] 11 10 01 00 CFP95[1:0] 11 10 01 00 CFP94[1:0] 11 10 01 00 Function reserved CARD5 #SRDY3 P97 Function reserved CARD4 #SCLK3 P96 Function reserved ASTB SOUT3 P95 Function reserved ACST SIN3 P94 Init. R/W 0 0 I Remarks R/W Pin 0 0 R/W 0 0 R/W 0 0 R/W This register selects the functions of ports P94 to P97. D[7:6] CFP97[1:0]: P97 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD5 01 (R/W): #SRDY3 00 (R/W): P97 (default) D[5:4] CFP96[1:0]: P96 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): CARD4 01 (R/W): #SCLK3 00 (R/W): P96 (default) D[3:2] CFP95[1:0]: P95 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): ASTB 01 (R/W): SOUT3 00 (R/W): P95 (default) D[1:0] CFP94[1:0]: P94 Port Extended Function Select Bits 11 (R/W): Reserved 10 (R/W): ACST 01 (R/W): SIN3 00 (R/W): P94 (default) S1C33401 TECHNICAL MANUAL EPSON I-3-29 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.4 Input/Output Cells and Input/Output Characteristics Table I.3.4.1 Pin Characteristics Signal name OSC1 OSC2 OSC3 OSC4 VCP #RESET #NMI DSIO DCLK DST2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 (P47) A19 (P46) A20 (P45) A21 (P44) A22 (P43) A23 (P42) A24 (P41) A25 (P40) #RD #WRL #WRH #BSL #CE10 #CE4 (P50/CARD0) #CE5 (P51) #CE6 (P52) I-3-30 I/O I/O cell name Input level IOH/IOL Pull-up/down I O I O O I I I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O LLINY LLOTY LLINY LLOTY LLOTY HIBHP1TY HIBHP1TY HBBH2BP1TY HOB2BTY HOB2BTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBT2BHTY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY transparent - transparent - - Schmitt Schmitt Schmitt - - LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt - - - - - - - 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 2 mA 2 mA 2 mA 2 mA - - - - - 50 k up 50 k up 50 k up - - Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch Bus-hold latch 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up EPSON Power source RTCVDD RTCVDD VDD VDD PLLVDD VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE Remarks note 5 note 5 note 2 note 2 note 6 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Signal name #CE7 (P53/CARD1) #CE8 (P54) #CE9 (P55) #CE11 (P56) P00 (SIN0) P01 (SOUT0) P02 (#SCLK0) P03 (#SRDY0) P04 (SIN1) P05 (SOUT1) P06 (#SCLK1) P07 (#SRDY1) P10 (TM0) P11 (TM1) P12 (TM2) P13 (TM3) P14 (TM4/#DMAEND0) P15 (TM5/#DMAEND1) P16 (TM6/#DMAACK0) P17 (TM7/#DMAACK1) P20 (SDCKE/SIN2) P21 (SDCLK/SOUT2) P22 (#SDCS/#SCLK2) P23 (#SDRAS/#SRDY2) P24 (#SDCAS/SIN3) P25 (#SDWE/SOUT3) P26 (DQML/#SCLK3) P27 (DQMH/#SRDY3) P30 (#DMAREQ0/T8UF0/EXCL0) P31 (#DMAREQ1/T8UF1/EXCL1) P32 (#DMAREQ2/CARD2/EXCL2) P33 (#DMAREQ3/CARD3/WDT_CLK) P60 (#BUSREQ/CARD4) P61 (#BUSACK/CARD5) P62 (#BUSGET/T8UF2/#ADTRG) CMU_CLK (P63/BCLK/T8UF5) P64 (#WAIT) DST0 (P65) DST1 (P66) DPCO (P67) P70 (AIN0) P71 (AIN1) P72 (AIN2) P73 (AIN3) P80 (#DMAACK2/T8UF3/EXCL3) P81 (#DMAACK3/T8UF4/EXCL4) P82 (#DMAEND2/EXCL5/DBT) P83 (#DMAEND3/EXCL6/DTS0) P84 (PSC_CLK/CARD2/DTS1) P85 (CMU_CLK/CARD3/DTS2) P86 (TM8/CARD0/DTS3) P87 (TM9/CARD1/DTS4) P90 (SIN2/EXCL7/DTD0) P91 (SOUT2/EXCL8/DTD1) P92 (#SCLK2/EXCL9/DTD2) P93 (#SRDY2/R/W/DTD3) P94 (SIN3/ACST/DTD4) P95 (SOUT3/ASTB/DTD5) P96 (#SCLK3/CARD4/DTD6) P97 (#SRDY3/CARD5/DTD7) TST0 TST1 BURNIN SCANEN #STBY S1C33401 TECHNICAL MANUAL I/O I/O cell name Input level IOH/IOL Pull-up/down I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH2AP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH1BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HIBASP2TY HIBASP2TY HIBASP2TY HIBASP2TY HBBH1BP2TY HBBH1BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY HBBH2BP2TY LITST1Y HIBHD1TY HIBHY HIBHD1TY LIBHY Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt LVCMOS LVCMOS LVCMOS LVCMOS Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt LVCMOS Schmitt Schmitt Schmitt LVCMOS 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 4 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 2 mA 4 mA 4 mA 4 mA - - - - 2 mA 2 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA - - - - - 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 100 k up 60 k down 50 k down - 50 k down - EPSON Power source VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE TMVDD TMVDD TMVDD TMVDD TMVDD TMVDD TMVDD TMVDD VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE AVDD AVDD AVDD AVDD VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE VDDE Remarks note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1, 4 note 1, 4 note 1, 4 note 1, 4 note 1, 4 note 1, 4 note 1, 4 note 1, 4 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1, 3 note 1, 3 note 1, 3 note 1, 3 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 I-3-31 I Pin I S1C33401 SPECIFICATIONS: PIN DESCRIPTION Notes: 1 Pull-ups can be enabled or disabled by setting the pin control registers. (Pull-ups are enabled by default.) 2 This pin must be used in input voltage range 0 V VIN VDD. 3 This pin must be used in input voltage range 0 V VIN AVDD. 4 This pin must be used in input voltage range 0 V VIN TMVDD. 5 This pin must be used in input voltage range 0 V VIN RTCVDD. 6 This pin must be used in input voltage range 0 V VIN PLLVDD. I-3-32 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.5 Package I I.3.5.1 QFP20-184pin Package Pin 220.4 200.1 138 93 139 220.4 200.1 92 INDEX 184 47 1 1.40.1 +0.05 46 0.16-0.03 +0.05 0.125-0.025 0 10 0.50.2 0.1 1.7max 0.4 1 Figure I.3.5.1.1 QFP20-184pin Package Dimensions S1C33401 TECHNICAL MANUAL EPSON I-3-33 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.5.2 PFBGA-160pin Package Top View D A1 Corner E Index S A1 y A S ZD x SD b e M Bottom View ZE e SE P N M L K J H G F E D C B A A1 Corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol D E A A1 e b X Y SD SE ZD ZE Dimension in Millimeters Min Max Nom 9.8 10.2 10.0 9.8 10.2 10.0 1.20 0.17 0.27 0.22 0.65 0.27 0.37 0.32 0.08 0.10 0.325 0.325 0.775 0.775 Figure I.3.5.2.1 PFBGA-160pin Package Dimensions I-3-34 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PIN DESCRIPTION I.3.5.3 Thermal Resistance of the Package I The chip temperature of LSI devices tends to increase with the power consumed on the chip. The chip temperature when encapsulated in a package is calculated from its ambient temperature (Ta), the thermal resistance of the package (), and power dissipation (PD). Pin Chip temperature (Tj) = Ta + (PD x ) [C] When used under normal operating conditions, make sure that the chip temperature (Tj) is 100C or less. Thermal resistance of the QFP20-184pin package 1. When mounted on a board (windless condition) Thermal resistance (j-a) = 33.3C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114 x 76 x 1.6 mm thick, FR4/4 layered board). 2. When suspended alone (windless condition) Thermal resistance = 90-100C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. Thermal resistance of the PFBGA-160pin package 1. When mounted on a board (windless condition) Thermal resistance (j-a) = 30C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114.5 x 101.5 x 1.6 mm thick, FR4/4 layered board). 2. When suspended alone (windless condition) Thermal resistance = 165C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. Note: The thermal resistance of the package varies significantly depending on how it is mounted on the board and whether forcibly air-cooled. S1C33401 TECHNICAL MANUAL EPSON I-3-35 I S1C33401 SPECIFICATIONS: PIN DESCRIPTION THIS PAGE IS BLANK. I-3-36 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: POWER SUPPLY I.4 Power Supply I This section explains the operating voltage of the S1C33401. Power I.4.1 Power Supply Pins The S1C33401 has the power supply pins shown in Table I.4.1.1. Table I.4.1.1 Power Supply Pins Pin name VDD VSS PLLVDD PLLVSS RTCVDD VDDE TMVDD AVDD Pin No. Function QFP PFBGA Power supply (+) for the internal logic circuits (1.65 V to 1.95 V) 9,25,40,57,71,82,101, B7,B11,E4,F11,G14, 117,130,146,160,173 L5,L12 12,23,35,52,63,73,84,91,98, A11,B14,C3,D6,D13,E2, Power supply (-); GND 105,113,123,132,138,151, H14,K3,K11,L8,M10,N13 165,175,184 Power supply (+) for the PLL (PLLVDD = VDD) 143 C12 Power supply (-) for the PLL (PLLVSS = VSS) 145 D11 Power supply (+) for the RTC (RTCVDD = VDD) 139 B12 4,15,29,61,75,87,97,107, D4,D9,E14,H4,H11,M6,N11 Power supply (+) for the I/O block (2.7 V to 3.6 V) 119,128,154,177 Power supply (+) for PWM timer outputs (P1x port) (TMVDD = VDDE) 37 K2 Power supply (+) for the analog system and AIN0-AIN3 (AVDD = VDDE) 51 N3 1.65 to 1.95 V GND VDD VSS 1.65 to 1.95 V PLLVDD GND PLLVSS 2.70 to 3.60 V 2.70 to 3.60 V CPU core OSC3 oscillator Internal logic circuits PLL VDDE I/O interface circuit TMVDD I/O interface circuit (P1x) 2.70 to 3.60 V AVDD 1.65 to 1.95 V RTCVDD Analog circuits (A/D converter) OSC1 oscillator RTC Figure I.4.1.1 Power Supply System S1C33401 TECHNICAL MANUAL EPSON I-4-1 I S1C33401 SPECIFICATIONS: POWER SUPPLY I.4.2 Operating Voltage (VDD, VSS) The core CPU and internal logic circuits operate with a voltage supplied between the VDD and VSS pins. The following operating voltage can be used: VDD = 1.65 V to 1.95 V (1.8 V 0.15 V, VSS = GND) Note: The S1C33401 QFP package has 12 VDD pins and 18 VSS pins; the PFBGA package has 7 VDD pins and 12 VSS pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. I.4.3 Power Supply for PLL (PLLVDD, PLLVSS) The PLL power supply pins (PLLVDD, PLLVSS) are provided separately from the VDD and VSS pins in order that the digital circuits do not affect the PLL circuit. Supply the same voltage level as the VDD to the PLLVDD pin. PLLVDD = VDD, PLLVSS = VSS Noise on the PLL power lines decrease the PLL output precision, so use a stabilized power supply and make the board pattern with consideration given to that. I.4.4 Power Supply for I/O Interface (VDDE) The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33401, the VDDE voltage is used as high level and the VSS voltage as low level. The VSS pin is used for the ground common with VDD. The following voltage is enabled for VDDE: VDDE = 2.70 V to 3.60 V (3.0/3.3 V 0.3 V, VSS = GND) Notes: * The S1C33401 QFP package has 12 VDDE pins; the PFBGA package has 7 VDDE pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. * When an external clock is input to the OSC3 pin, the clock signal level must be VDD. I.4.5 Power Supply for T16 PWM Output (P1x) Ports (TMVDD) The P1x port power supply pin (TMVDD) is provided separately from the VDDE pins. Supplying the AVDD voltage, which is isolated from the power supply for other I/O signals, to the TMVDD pin as well as the AVDD pin allows noise reduction in the audio signals output from 16-bit timers (PWM). Supply the same voltage level as the VDDE to the TMVDD pin. TMVDD = VDDE (VSS = GND) I.4.6 Power Supply for Analog Circuits (AVDD) The analog power supply pin (AVDD) is provided separately from the VDD and VDDE pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AVDD pin is used to supply an analog power voltage and the VSS pin is used as the analog ground. The following voltage is enabled for AVDD: AVDD = 2.70 V to 3.60 V (3.0/3.3 V 0.3 V, VSS = GND) Note: Be sure to supply VDDE to the AVDD pin when the analog circuit is not used. Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. I.4.7 Power Supply for RTC (RTCVDD) The RTC has a power supply pin (RTCVDD) provided independently of other blocks of the system. When the RTC is supplied with continuous power from this pin, it is assured of continued timekeeping operation even when all other power supplies are turned off. Supply the same voltage level as the VDD to the RTCVDD pin. RTCVDD = VDD (VSS = GND) I-4-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: POWER SUPPLY I.4.8 Precautions on Power Supply I Power-on sequence In order to operate the device normally, supply power in accordance with the following timing. Power VDDE, TMVDD, AVDD VDD min. VDD, PLLVDD OSC3 tSTA3 tPLL tVDD PLL tRST #RESET Figure I.4.8.1 Power-On Sequence (1) tVDD: Elapsed time until the power supply stabilizes after power-on Supply power in the following sequence (or simultaneously). Power-on: VDD and PLLVDD (Internal) VDDE, TMVDD and AVDD (I/O) Apply the input signal (2) tSTA3: Time at which OSC3 oscillation starts (3) tPLL: Time at which PLL locks up (4) tRST: Minimum reset pulse width Time at which the clock supplied to the C33 ADV core CPU stabilizes plus at least six clocks; Keep the #RESET signal low. Power-off sequence Shut off the power supply in the following sequence (or simultaneously). Power-off: Turn off the input signal AVDD, TMVDD and VDDE (I/O) PLLVDD and VDD (Internal) Latch-up The CMOS device may be in the latch-up condition. This is the phenomenon caused by conduction of the parasitic PNPN junction (thyristor) contained in the CMOS IC, resulting in a large current between VDD and VSS and leading to breakage. Latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows into the internal element, or when the voltage at the VDD pin exceeds the rated value and the internal element is in the breakdown condition. In the latter case, even if the application of a voltage exceeding the rated value is instantaneous, the current remains high between VDD and VSS once the device is in the latch-up condition. As this may result in heat generation or smoking, the following points must be taken into consideration: (1) The voltage level at the input / output must not exceed the range specified in the electrical characteristics. In other words, it must be below the power-supply voltage and above VSS. The power-on timing should also be taken into consideration. (2) Abnormal noise must not be applied to the device. (3) The potential at the unused input should be fixed at VDD, VDDE, TMVDD, AVDD, or VSS. (4) No outputs should be shorted. S1C33401 TECHNICAL MANUAL EPSON I-4-3 I S1C33401 SPECIFICATIONS: POWER SUPPLY THIS PAGE IS BLANK. I-4-4 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: MEMORY MAP I.5 Memory Map I Figure I.5.1 shows a memory map of the entire physical address space of the S1C33401. Figure I.5.2 shows a memory map of internal memory and the internal I/O space of the S1C33401. Internal Areas Area 22 Area 21 Area 20 Area 19 Area 7 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF Area 6 0x0040 0000 0x003F FFFF Area 16 Area 15 Area 14 Area 13 Area 12 Area 11 Area 10 Area 9 Area 8 Area 5 Area 4 Area 3 Area 2 Area 1 Area 0 External Memory 2G bytes (Reserved) External Memory 1G bytes (Reserved) External Memory 512M bytes (Reserved) External Memory 256M bytes #CE8 0x2000 0000 0x1FFF FFFF 0x0200 0x01FF 0x0180 0x017F 0x0100 0x00FF 0x00C0 0x00BF 0x0080 0x007F 0x0060 0x005F Area 17 (Reserved) 0x4000 0000 0x3FFF FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0x0030 0x002F 0x0020 0x001F 0x0010 0x000F 0x0008 0x0007 0x0006 0x0005 0x0002 0x0001 0x0000 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 MAP #CE9 0x8000 0000 0x7FFF FFFF 0x1000 0x0FFF 0x0C00 0x0BFF 0x0800 0x07FF 0x0600 0x05FF 0x0400 0x03FF 0x0300 0x02FF Area 18 External Areas 0xFFFF FFFF External Memory 64M bytes External Memory 64M bytes External Memory 32M bytes External Memory 32M bytes External Memory 16M bytes External Memory 16M bytes External Memory 8M bytes External Memory 8M bytes External Memory 4M bytes External Memory 4M bytes External Memory 2M bytes External Memory 2M bytes (Reserved for extended I/O) External Memory 1M bytes External Memory 1M bytes (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Extended I/O (RTC, etc.) (Reserved) (Reserved) #CE10 #CE7 #CE6 #CE6 #CE5 #CE5 #CE4 Usable as memory space for SmartMedia (NAND flash), CompactFlash, or PC Card. #CE10 #CE11 #CE11 #CE10 #CE9 #CE8 #CE7 #CE6 #CE5 #CE4 Internal RAM area Reserved for debugging Internal I/O 256K bytes Internal RAM area Figure I.5.1 General Memory Map S1C33401 TECHNICAL MANUAL EPSON I-5-1 I S1C33401 SPECIFICATIONS: MEMORY MAP Internal Areas Area 6 0x003F FFFF 0x0030 2000 0x0030 10FF 0x0030 0000 Area 3 0x000F FFFF 0x0008 0400 0x0008 03FF Area 2 Area 1 0x0008 0x0007 0x0006 0x0005 0000 FFFF 0000 FFFF 0x0004 9000 0x0004 8FFF 0x0004 8000 0x0004 7FFF 0x0004 2000 0x0004 1FFF 0x0004 1000 0x0004 0FFF 0x0004 0000 0x0003 FFFF 0x0003 0000 0x0002 FFFF Area 0 0x0002 0x0001 0x0000 0x0000 0x0000 0000 FFFF 8000 7FFF 0000 (Reserved) Extended I/O (Reserved) A3RAM (1KB) Reserved for debugging (Reserved) 16-bit I/O (4KB) (Reserved) Mirror of 16-bit I/O (4KB) 8-bit I/O (4KB) Mirror of internal I/O (0x40000-0x4FFFF) (Reserved) (Reserved) Extended I/O 0x00301000-0x00301028 Real Time Clock 0x00300000-0x00300F20 Chip ID/Pin Status Control 16-bit I/O 0x000483C0-0x400083CC 0x00048380-0x000483A6 0x00048360-0x00048372 0x00048340-0x00048352 0x00048320-0x00048334 0x00048300-0x00048314 0x00048220-0x0004829C 0x00048200-0x00048205 0x00048180-0x000481DE 0x00048160-0x0004816C 0x00048140-0x0004815E Extended Bus Control Unit Basic Bus Control Unit Clock Management Unit (2) Cache Control Unit Memory Management Unit High-Speed Bus Control Unit High-Speed DMA Intelligent DMA 16-bit Timer Watchdog Timer A/D Converter 8-bit I/O 0x00040340-0x00040395 0x00040300-0x00040302 0x000402E0-0x000402F4 0x00040260-0x000402AF 0x000401E0-0x000401FF 0x00040180-0x00040188 0x00040160-0x0004017A 0x00040140-0x0004014F I/O Ports Card Interface Debug Unit Interrupt Controller Serial Interface Clock Management Unit (1) 8-bit Timer Prescaler A0RAM (32KB) Figure I.5.2 Internal Area Map The following describes the area configuration of the S1C33401. For details of the logical space, address processing, and cache operation, see the description of the HBCU, MMU, and CCU in Chapter II. For details of area settings and accesses, see the description of the BBCU in Chapter III. I.5.1 ROM and Boot Address The S1C33401 does not contain ROM. When the chip is powered on or cold-reset, the boot address is set to 0x20000000 (initial value of TTBR). Therefore, use external ROM or flash memory in Area 20. I.5.2 Area 0 (A0RAM) Area 0 contains built-in 32KB high-speed RAM (A0RAM). Its location address ranges from 0x0 to 0x7FFF. Since A0RAM is accessed directly from the HBCU without BBCU intervention, no wait cycles are inserted. A0RAM is accessed in one cycle (with no wait cycle), regardless of whether accessed in units of bytes, half-words, or words. Moreover, due to a Harvard architecture, A0RAM can be accessed simultaneously with the fetching of instructions from external memory (cache). I-5-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: MEMORY MAP Notes: * A0RAM cannot contain IDMA control words or be specified as the source or destination of DMA transfer. I * Even when setting up the HBCU to enable the use of low-order 1GB mirror areas, Area 0 is not mirrored. * The addresses listed below are reserved for special purposes. If the function of any reserved area is used, the user program must be prohibited from accessing that area. 0x0-0xF: Reserved for use as MON33 debugging area 0x10-0x1F: Reserved for use as MMU exception area 0x10: MMU exception vector address 0x18: Area in which PC is saved when MMU exception occurs 0x1C: Area in which R0 is saved when MMU exception occurs I.5.3 Area 1 (Internal I/O) Area 1 is allocated for the basic internal peripheral circuits of the C33 ADV. Addresses 0x40000 to 0x4FFFF are used for the control registers, etc.; Addresses 0x30000 to 0x3FFFF are used to mirror said addresses. The internal I/O area is divided into 4KB of the 8-bit device area (consisting of 0x40000 to 0x40FFF) and 4KB of the 16-bit device area (consisting of 0x48000 to 0x48FFF). Furthermore, addresses 0x41000 to 0x41FFF are configured as the mirror of the 16-bit device area. By using this mirror with the base address be set to 0x40000, the entire internal I/O areas that contains both the 8-bit and 16-bit device areas can be accessed with two instructions (one basic instruction with one ext instruction). Area 1 is accessed in at least four cycles. For details of the basic internal peripheral circuits mapped to this area, see Chapter IV, "C33 ADV Basic Peripheral Block." For details of a control register list, see "I/O Map" in the Appendix. I.5.4 Area 2 (Debug Area) Area 2 is a debugging-only area allocated for debugging resources. This area can only be accessed for write in debug mode. Make sure this area is not accessed from the user program or debugger. I.5.5 Area 3 (A3RAM) Area 3 contains built-in 1KB RAM (A3RAM). Its location address ranges from 0x80000 to 0x803FF. A3RAM is accessed in two cycles (with one wait state, for random access) or one cycle (with no wait states, for continuous access) from the dedicated interface on the high-speed bus without BBCU intervention. A3RAM can contain IDMA control words and may also be specified as the source and destination of DMA transfer. I.5.6 Area 6 (Extended I/O) Area 6 is allocated for the chip ID register, pin control registers, and RTC. For details of how to set up the BBCU to use these registers or functions, see Chapter V, "S1C33401 Area 6 Extended Peripheral Block." Area 6 must be set for use as an internal device (by setting up the BBCU) before it can be accessed for these functions. By switching the settings of this area between internal and external devices, the area may be used for a combination of said functions and external devices. S1C33401 TECHNICAL MANUAL EPSON I-5-3 MAP I S1C33401 SPECIFICATIONS: MEMORY MAP I.5.7 External Memory Area Areas 4 to 20 can be used for external memory and other external devices. Set up the BBCU or EBCU according to specifications of the devices connected. Although the internal address and internal data buses of the S1C33401 are both 32 bits wide, the maximum external data bus width is 16 bits (D[15:0]) and maximum external address bus width is 26 bits (A[25:0]) due to the limited number of pins available. I.5.8 Limitations on Areas 0 to 6 Areas 0 to 6 are subject to the following usage limitations: * Area 0 cannot contain IDMA control words or be specified as the source or destination of DMA transfer. * Even when setting up the HBCU to enable the use of low-order 1GB mirror areas, Area 0 is not mirrored. * Access to Areas 0 to 6 cannot be cached. * Areas 0 to 6 are normally not the target of address conversion by the MMU. However, this 4MB space can be forcibly made the target of MMU operation as other areas by setting UMDMEN (D1/0x48300) to 1. UMDMEN: MMU Forced Enable Bit in the Address Control Register (D1/0x48300) * Areas 0 to 6 are normally not the target of multiplexing operation by using ASID. However, this 4MB space can be forcibly made the target of multiplexing operation as other areas by setting UMDAEN (D2/0x48300) to 1. UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300) I-5-4 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6 Electrical Characteristics I I.6.1 Absolute Maximum Rating Symbol Item Internal logic power voltage PLL power voltage RTC power voltage I/O power voltage P1x I/O power voltage Analog power voltage Input voltage Analog input voltage High-level output current VDD PLLVDD RTCVDD VDDE TMVDD AVDD VI AVIN IOH Low-level output current IOL Storage temperature TSTG Condition (VSS=PLLVSS=0V) Unit V V V V V V V V mA mA mA mA C Rated value -0.3 to +2.5 -0.3 to +2.5 -0.3 to +2.5 -0.3 to +4.0 -0.3 to +4.0 -0.3 to +4.0 -0.3 to VDDE+0.5 -0.3 to AVDD+0.3 -10 -40 10 40 -65 to +150 1 pin Total of all pins 1 pin Total of all pins I.6.2 Recommended Operating Conditions Item Internal logic power voltage PLL power voltage RTC power voltage I/O power voltage P1x I/O power voltage Analog power voltage Input voltage Analog input voltage CPU operating clock frequency Bus operating clock frequency OSC3 oscillation frequency OSC3 external input clock frequency OSC1 oscillation frequency Operating temperature Input rise time (normal input) Input fall time (normal input) Input rise time (Schmitt input) Input fall time (Schmitt input) S1C33401 TECHNICAL MANUAL Condition Symbol Min. 1.65 1.65 1.65 2.70 2.70 2.70 VSS VSS VSS - - 5 2 - -40 - - - - VDD PLLVDD RTCVDD VDDE TMVDD AVDD HVI LVI AVIN fCPU fBUS fOSC3 fECLK3 fOSC1 Ta tri tfi tri tfi EPSON (VSS=PLLVSS=0V) Max. Unit 1.80 V 1.95 1.80 V 1.95 1.80 V 1.95 - V 3.60 - V 3.60 - V 3.60 - V VDDE - V VDD - V AVDD - MHz 66 - MHz 66 - MHz 33 - MHz 33 32.768 kHz - 25 C 85 - ns 50 - ns 50 - ms 5 - ms 5 Typ. I-6-1 E char I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.3 DC Characteristics (Unless otherwise specified: VDDE=TMVDD=2.7V to 3.6V, VDD=1.65V to 1.95V, Ta=-40C to +85C) Min. Symbol Typ. Max. Unit Condition Input leakage current -5 ILI - 5 A Off-state leakage current -5 IOZ - 5 A High-level output voltage VDD VOH - - IOH=-1.7mA (2mA Type), V -0.4 IOH=-3.5mA (4mA Type), VDD=Min. Low-level output voltage - VOL - 0.4 IOL=1.7mA (2mA Type), V IOL=3.5mA (4mA Type), VDD=Min. High-level input voltage 2.0 VIH - - LVTTL level, VDDE=Max. V Low-level input voltage - VIL - 0.7 LVTTL level, VDDE=Min. V Positive trigger input voltage 1.2 VT+ - 2.7 LVCMOS Schmitt V Negative trigger input voltage 0.5 VT- 1.8 LVCMOS Schmitt V Hysteresis voltage 0.2 VH - - LVCMOS Schmitt V Pull-up resistor 50 RPU 100 288 VI=0V 100k Type k 25 50 144 50k Type k Pull-down resistor 60 RPD 120 346 VI=VDDE 120k Type k 25 50 144 50k Type k High-level latching current - - IBHH -20 Pins with bus-hold latch, VI=1.9V, VDDE=Min. A Low-level latching current - IBHL - 17 Pins with bus-hold latch, VI=0.8V, VDDE=Min. A High-level reversal current IBHHO Pins with bus-hold latch, VI=0.8V, VDDE=Max. -350 - - A Low-level reversal current 300 - IBHLO Pins with bus-hold latch, VI=1.9V, VDDE=Max. - A Input pin capacitance - CI - 8 f=1MHz, VDDE=0V pF Output pin capacitance - CO - 8 f=1MHz, VDDE=0V pF I/O pin capacitance - CIO - 8 f=1MHz, VDDE=0V pF Item Note: See Section I.3.4, "Input/Output Cells and Input/Output Characteristics," for pin characteristics. I-6-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.4 Current Consumption I Operating current Symbol Item Current consumption during CPU running (cache off) IDD1 Current consumption during CPU running (cache on) IDD2 Current consumption in HALT mode IDD3 Current consumption in HALT2 mode IDD4 (Unless otherwise specified: VDDE=3.3V, VDD=1.8V, VSS=0V, Ta=25C) Min. Typ. Condition Max. Unit - 16 30MHz mA 1 - - 27 50MHz - - 36 66MHz - - 31 30MHz mA 2 - - 51 50MHz - - 68 66MHz - - 9 30MHz mA 3 - - 15 50MHz - - 20 66MHz - - 7 30MHz mA 4 - - 11 50MHz - - 15 66MHz - Current consumption measurement condition: VIH=VDDE, VIL=0V, output pins are open, VDD power current only Typ. value measurement condition: VDDE=AVDD=3.3V, VDD=1.8V, Ta=25C Typ. sample note) No. 1 2 3 4 Other peripheral circuits OSC3 OSC1 CPU On On On On Off Off Off Off Normal operation 1 Normal operation 1 HALT mode HALT2 mode Cache off, peripheral circuits off/PCLK supply off Cache on, peripheral circuits off/PCLK supply off Peripheral circuits off/PCLK supply off Peripheral circuits off/PCLK supply off 1: The values of current consumption while the CPU is operating were measured when a JPEG encode program was being executed in an external SRAM. The following shows the number of external SRAM access cycles corresponding to each operating frequency: 30MHz: 3 cycles (100ns) 50MHz: 5 cycles (100ns) 66MHz: 7 cycles (105ns) Current consumption in SLEEP mode Item Symbol VDD current consumption IDDSL in SLEEP mode VDDE + AVDD current consumption IDDSE in SLEEP mode (Unless otherwise specified: VDDE=3.3V, VDD=1.8V, VSS=0V, Ta=25C) Max. Unit Condition Typ. Min. - A Ta=25C 5 - - Ta=85C 50 - - A Ta=25C 5 - - Ta=85C 15 - Current consumption measurement condition: VIH=VDDE, VIL=0V, output pins are open Typ. value measurement condition: VDDE=AVDD=3.3V, VDD=1.8V, Ta=25C Typ. sample Peripheral circuit operating currents (Unless otherwise specified: VDDE=AVDD=3.3V, VDD=RTCVDD=PLLVDD=1.8V, VSS=0V, Ta=25C) Symbol Max. Unit Condition Typ. Min. RTC operating current IRTC - A 5 OSC1 oscillation: 32kHz 1 - A/D converter operating current IAD - A 6 When A/D converter is enabled 300 - OSC3 operating current IOSC3 OSC3 oscillation: 33MHz - mA 7 0.6 - PLL operating current IPLL - mA 8 PLL output clock: 50MHz 1 - SSCG operating current ISSCG SSCG input clock: 50MHz - mA 7 0.4 - Item note 5) 6) 7) 8) RTCVDD power current consumption AVDD power current consumption VDD power current consumption PLLVDD power current consumption S1C33401 TECHNICAL MANUAL EPSON I-6-3 E char I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.5 A/D Converter Characteristics (Unless otherwise specified: VDDE=AVDD=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40C to +85C, ST[1:0]=11) Min. Typ. Condition Unit Max. Symbol Item - 10 bit - - Resolution 10 - s 1 1250 - Conversion time -2 - LSB 2 EZS Zero scale error -2 - LSB 2 EFS Full scale error -3 - LSB 3 EL Integral linearity error -3 - LSB 3 ED Differential linearity error - - k 5 Permissible signal source impedance - - - pF 45 - Analog input capacitance note 1) Indicates the minimum value when A/D clock = 2MHz. Indicates the maximum value when A/D clock = 16kHz. A/D conversion error V[001]h V'[001]h V[3FF]h V'[3FF]h = Ideal voltage at zero-scale point (=0.5LSB) = Actual voltage at zero-scale point = Ideal voltage at full-scale point (=1022.5LSB) = Actual voltage at full-scale point AVDD - VSS 210 - 1 V'[3FF]h - V'[001]h 1LSB' = 210 - 2 1LSB = Zero scale error Digital output (hex) 004 Ideal conversion characteristic 003 002 V[001]h (=0.5LSB) Actual conversion characteristic Zero scale error EZS = 001 (V'[001]h - 0.5LSB') - (V[001]h - 0.5LSB) [LSB] 1LSB V'[001]h 000 VSS Analog input Full scale error Digital output (hex) 3FF V[3FF]h (=1022.5LSB) V'[3FF]h 3FE Full scale error EFS = 3FD 3FC 3FB (V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB) [LSB] 1LSB Actual conversion characteristic Ideal conversion characteristic AVDD Analog input Integral linearity error 3FF Digital output (hex) 3FE V'[3FF]h 3FD Integral linearity error EL = VN 003 VN' VN' - VN [LSB] 1LSB' Actual conversion characteristic 002 Ideal conversion characteristic 001 000 VSS V'[001]h Analog input AVDD Differential linearity error Digital output (hex) N+1 Ideal conversion characteristic N Actual conversion characteristic N-1 N-2 V'[N]h Differential linearity error ED = V'[N-1]h V'[N]h - V'[N-1]h - 1 [LSB] 1LSB' Analog input I-6-4 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.6 Oscillation Characteristics I Oscillation characteristics change depending on conditions such as components used (oscillator, Rf, Rd, CG, CD) and board pattern. Use the following characteristics as reference values. In particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (Rf, Rd) and capacitor (CG, CD) values are finally decided. OSC1 crystal oscillation Item Oscillation start time E char (Unless otherwise specified: RTCVDD=1.65V to 1.95V, VSS=0V, Ta=25C) Symbol Max. Unit Condition Typ. Min. tSTA1 3 s OSC3 crystal/ceramic oscillation Note: A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit. Item Oscillation start time Symbol tSTA3 (Unless otherwise specified: VDD=1.65V to 1.95V, VSS=0V, Ta=25C) Max. Unit Condition Typ. Min. 25 ms Recommended OSC3 ceramic resonators Frequency Ceramic resonator [MHz] product number (SMD type) Recommended component values CG2 [pF] CD2 [pF] Rf [] Rd [] 5 10 20 33 CSTCR5M00G55-R0 (39) (39) 1M 22 CSTCE10M0G55-R0 (33) (33) 1M 22 CSTCE20M0V53-R0 (15) (15) 1M 22 CSTCG33M0V51-R0 (5) (5) 1M 22 CSTCW33M0X51-R0 (6) (6) 33k 22 note) CST indicates the product that has built-in load capacitances (CG2, CD2). S1C33401 TECHNICAL MANUAL EPSON Remarks Ceramic resonators manufactured by Murata Manufacturing Co., Ltd. I-6-5 I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.7 PLL Characteristics Item Input frequency Output frequency Multiplying factor Output stabilization time I-6-6 (Unless otherwise specified: PLLVDD=1.65V to 1.95V, PLLVSS=0V, Ta=-40C to +85C) Min. Typ. Condition Unit Max. Symbol 5 MHz 33 fPLLIN 20 MHz 66 fPLLOUT 1 times 16 s 200 tPLL EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.8 AC Characteristics I I.6.8.1 Symbol Description tCYC: Bus-clock cycle time Indicates the cycle time of the bus clock. E char I.6.8.2 AC Characteristics Measurement Condition Signal detection level: Input signal High level VIH = VDDE - 0.4 V Low level VIL = 0.4 V Output signal High level VOH = 1/2 VDDE Low level VOL = 1/2 VDDE The following applies when OSC3 is external clock input: Input signal High level VIH = 1/2 VDD Low level VIL = 1/2 VDD Input signal waveform: Rise time (10% 90% VDD) Fall time (90% 10% VDD) 5 ns 5 ns Output load capacitance: Pins other than SDCLK: CL = 50 pF SDCLK pin: CL = 20 pF S1C33401 TECHNICAL MANUAL EPSON I-6-7 I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.8.3 BBCU AC Characteristic Tables External clock input characteristics (Note) These AC characteristics apply to input signals from outside the IC. The OSC3 input clock must be within VDD to VSS voltage range. (Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40C to +85C) Min. Unit Max. Symbol Item 30 ns 500 tC3 High-speed clock cycle time 45 % 55 tC3ED OSC3 clock input duty ns 5 tIF OSC3 clock input rise time ns 5 tIR OSC3 clock input fall time ns 25 tCD1 BCLK high-level output delay time ns 25 tCD2 BCLK low-level output delay time BCLK clock output characteristics (Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used. (Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40C to +85C) Min. Unit Max. Symbol Item 40 % 60 tCBD BCLK clock output duty Bus access cycle (Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40C to +85C) Min. Unit Max. Symbol Item - ns 1 10 tAD Address delay time - ns 10 tCE1 #CEx delay time (1) - ns 10 tCE2 #CEx delay time (2) 18 ns - tWTS Wait setup time 0 ns - tWTH Wait hold time ns 2 10 tRDD1 Read signal delay time (1) ns 10 tRDD2 Read signal delay time (2) 18 ns tRDS Read data setup time 0 ns tRDH Read data hold time ns 3 10 tWRD1 Write signal delay time (1) ns 4 10 tWRD2 Write signal delay time (2) ns 10 tWDD1 Write data delay time (1) 0 ns tWDH Write data hold time note 1) 2) 3) 4) This applies to the #BSH and #BSL timings. When the RD start state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge. When the WR start state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge. When the WR end state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge. External bus master (Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40C to +85C) Item Symbol Max. Unit Min. #BUSREQ signal setup time tBRQS ns 18 #BUSREQ signal hold time tBRQH ns 0 #BUSACK signal output delay time tBAKD 10 ns I-6-8 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.8.4 BBCU AC Characteristic Timing Charts I Clock (1) When an external clock is input: tC3 tC3H tC3ED = tC3H/tC3 OSC3 (High-speed clock) tIF tCD1 tIR tC3 (tCYC) tCD2 BCLK (Clock output) (2) When the high-speed oscillation circuit is used for the operating clock: tCYC tCBH tCBD = tCBH/tCYC BCLK (Clock output) S1C33401 TECHNICAL MANUAL EPSON I-6-9 E char I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS SRAM read cycle [Condition] Access cycle multiply-by factor: x1 CE cycle: 3 clocks RD start state: 1 clock RD end state: 1 clock tCYC Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled BCLK tAD tAD valid A[31:0] tCE2 tCE1 #CEx tRDD2 tRDD1 #RD valid D[31:0] tRDS tRDH #RDWR ASTB tWTS tWTH tWTS tWTH #WAIT RD start Wait cycle RD end Access disable Output disable CE cycle SRAM write cycle [Condition] Access cycle multiply-by factor: x1 CE cycle: 3 clocks WR start state: 1 clock WR end state: 1 clock Access-disable cycle: 1 clock WR start state -0.5 clock option: Disabled WR end state -0.5 clock option: Disabled tCYC BCLK tAD tAD valid A[31:0] tCE2 tCE1 #CEx tWRD2 tWRD1 #WR tWDD1 tWDH valid D[31:0] #RDWR ASTB tWTS tWTH tWTS tWTH #WAIT WR start Wait cycle WR end Access disable CE cycle I-6-10 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS Burst ROM read cycle [Condition] I Access cycle multiply-by factor: x1 CE cycle: 3 clocks RD start state: 1 clock RD end state: 1 clock Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled tCYC BCLK tAD tAD E char valid A[31:4] tAD tAD tAD 00 A[3:2] tAD 01 tAD 10 11 tCE1 tCE2 #CEx tRDD1 tRDD2 #RD tRDS tRDS valid D[31:0] tRDS valid tRDH tRDS valid tRDH valid tRDH tRDH 1 #RDWR ASTB RD start Page read cycle Page read cycle Page read cycle RD end Access disable Output disable CE cycle 1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[31:0] signals. S1C33401 TECHNICAL MANUAL EPSON I-6-11 I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS #BUSREQ, #BUSACK timing BCLK tBRQS tBRQH #BUSREQ Valid input tBAKD #BUSACK I-6-12 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS I.6.8.5 SDRAM Interface AC Characteristics I SDRAM access cycle (Unless otherwise specified: VDDE=3.0V to 3.6V, VDD=1.65V to 1.95V, Ta=-40C to +85C) Min. Unit Max. Symbol 4 ns - tSS Command, address, write data setup time 2.5 ns - tSH Command, address, write data hold time 8.5 ns 1 - tRDS1 Read data setup time (1) 12 ns 2 - tRDS2 Read data setup time (2) 0 ns - tRDH Read data hold time Item note 1) When SDCLK = CCLK x 1/1 2) When SDCLK = CCLK x 1/2, 1/4, or 1/8 S1C33401 TECHNICAL MANUAL EPSON I-6-13 E char I-6-14 EPSON H tSH tSH tSH 0xF RASa tSS RASa tSS tSS tSS tSS tSS ACT tSH tSH tSH tSH tSS tSS tSS tSH 0x0 CAS tSH BANK0 (read) tSS READA Read cycle CAS latency = 2, Single read/write tSS tRDS1 tRDS2 valid tRDH tSH tSH tSH tSH tSH tSS tSS tSS 1 0xF tSH tSH tSH RASa tSS RASa tSS tSS tSS tSS tSS ACT tSH tSH tSH tSH tSS tSS 0x0 CAS tSH tSH BANK1 tSS valid tSS (write) tSS tSS tSH tSH tSH tSH tSH tSH tSH WRITA Write cycle tSS tSS tSS tSS 1 1: SDRAM internal precharge 0xF ACT * Also when other SDRAM control commands including refresh are output, the output signals will be effective during the periods from the setup time tSS before the SDCLK rising edge to the hold time tSH after the SDCLK rising edge. D[15:0] DQM[3:0] A[:0] A10/AP BS[1:0] #SDWE #SDCAS #SDRAS #SDCS SDCKE Command SDCLK [Condition] I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: BASIC EXTERNAL WIRING DIAGRAM I.7 Basic External Wiring Diagram 1.8 V + VDD PLLVDD RTCVDD VDDE TMVDD AVDD 3.0/3.3 V + #STBY #RESET X'tal2 or CE CG2 OSC3 Rf2 CD2 Rd2 X'tal1 CG1 OSC4 A[25:0] D[15:0] #RD #WRL #WRH #BSL #CExx #WAIT #BUSREQ #BUSACK #BUSGET ACST ASTB R/W CMU_CLK/BCLK PSC_CLK WDT_CLK #NMI External Bus SDCLK SDCKE DQMH DQML #SDCS #SDRAS #SDCAS #SDWE SDRAM #SMRD #SMWR #IOWR #IORD #OE #WE #CFCE1 #CFCE2 Card OSC1 Rf1 CD1 Rd1 OSC2 S1C33401 TST0 TST1 SCANEN BURNIN VSS [The potential of the substrate (back of the chip) is VSS.] DSIO DCLK DPCO DST[2:0] (DBT) (DTS[4:0]) (DTD[7:0]) Debug interface #DMAREQx #DMAACKx #DMAENDx HSDMA Serial I/O #ADTRG AINx A/D input Pxx Crystal oscillator Gate capacitor Drain capacitor Feedback resistor Drain resistor Crystal oscillator Ceramic oscillator Gate capacitor Drain capacitor Feedback resistor Drain resistor Wiring SINx SOUTx #SCLKx #SRDYx EXCLx TMx T8UFx X'tal1 CG1 CD1 Rf1 Rd1 X'tal2 CE CG2 CD2 Rf2 Rd2 I Timer input/output I/O 32.768 kHz 10 pF 10 pF 10 M 0 33 MHz (Max.) 33 MHz (Max.) 10 pF 10 pF 1 M 0 Note: The above table is simply an example, and is not guaranteed to work. S1C33401 TECHNICAL MANUAL EPSON I-7-1 I S1C33401 SPECIFICATIONS: BASIC EXTERNAL WIRING DIAGRAM THIS PAGE IS BLANK. I-7-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: CHANGES FROM CORE/BASIC PERIPHERAL FUNCTIONS I.8 Changes from Core/Basic Peripheral Functions In the S1C33401, some standard functions incorporated in the C33 ADV macro are limited or changed as described in this section. The contents of this manual described in Chapter II, "C33 ADV Core Block," Chapter III, "C33 ADV Bus Block," and Chapter IV, "C33 ADV Basic Peripheral Block," commonly apply to the S1C33-series microcomputers incorporating the C33 ADV macro. Therefore, be sure to understand the limitations or changes specific to the S1C33401 described in this section before designing application systems. I.8.1 Limitations on the BBCU and EBCU Bus width The C33 ADV supports 32-bit address and 32-bit data buses. In the S1C33401, the bus widths have been changed due to the limited number of pins available, as shown below. Internal address bus: 32 bits (not changed) Internal data bus: 32 bits (not changed) External address bus: Up to 26 bits A0 to A17 are the dedicated address bus pins, whereas A18 to A25 are shared with I/O ports (P47 to P40). (These pins are set for use as address bus pins by default.) External data bus: 16 bits Data bus pins D0 to D15 are available. Therefore, the external devices that can be connected to the chip are limited to a maximum data width of 16 bits. BBCU bus control signals Since the external data bus is 16 bits wide, the pins listed below are nonexistent. The signals, however, are used for accessing internal devices. Nonexistent pins: #WRHL, #WRHH EBCU SDRAM control signals Since the external data bus is 16 bits wide, the pins listed below are nonexistent. Nonexistent pins: DQM3, DQM2 S1C33401 TECHNICAL MANUAL EPSON I-8-1 I Change I S1C33401 SPECIFICATIONS: CHANGES FROM CORE/BASIC PERIPHERAL FUNCTIONS I.8.2 Limitations on the A/D Converter The A/D converter of the C33 ADV macro can handle analog inputs on up to eight channels. In the S1C33401, however, only four channels (AIN0-AIN3) are supported. Although the control registers and control circuits for eight channels are incorporated, conversion results on AIN4 to AIN7 have no effect. Control registers AVDD AIN2 AIN3 (AIN4) (AIN5) (AIN6) (AIN7) Analog input decoder Analog block Successive approximation block Ch0-Ch7 conversion result buffers Control circuit Comparator VSS Out of range #ADTRG 8-bit timer 0 16-bit timer 0 Conversion completed Upper-limit/ lower-limit value registers Internal data bus Data register AIN0 AIN1 Interrupt control circuit A/D converter input clock Prescaler CMU Interrupt request Can be used in advanced mode Figure I.8.2.1 A/D Converter in the S1C33401 Invalid control bits The control bits shown below are ineffective. OWE[7:4] (D[15:12]/0x48146) ADF[7:4] (D[7:4]/0x48146) AD4BUF[9:0] (D[9:0]/0x48150) AD5BUF[9:0] (D[9:0]/0x48152) AD6BUF[9:0] (D[9:0]/0x48154) AD7BUF[9:0] (D[9:0]/0x48156) Note: The control bits below are used to mask interrupts on each channel individually. To avoid unnecessary interrupts from nonexistent channels, be sure to set these bits to 0 (initially set to 1). INTMASK[7:4] (D[7:4]/0x4815C) = 0b0000 Control bits whose settings are limited The control bits below are used to specify channel numbers. Although numbers 0 to 7 can be specified, only numbers 0 to 3 are effective in the S1C33401. If numbers 4 to 7 are specified, the conversion results are not effective. CE[2:0] (D[13:11]/0x48142) CS[2:0] (D[10:8]/0x48142) ADCMP[2:0] (D[14:12]/0x48144) I-8-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING I.9 Precautions on Mounting I The following shows the precautions when designing the board and mounting the IC. Oscillation Circuit * Oscillation characteristics change depending on conditions such as components used (oscillator, Rf, Rd, CG, CD) and board pattern. In particular, when a ceramic or crystal oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (Rf, Rd) and capacitor (CG, CD) values are finally decided. * Disturbances of the oscillation clock due to noise may cause a malfunction. To prevent this, the following points should be taken into consideration. In particular, the latest devices are more sensitive to noise, as they are more finely processed. The measures against noise for the OSC2 pin, and the components and lines connected to this pin is most essential, and similar measures must also be taken for the OSC1 pin. The measures for the OSC1 and OSC2 pins are described below. We recommend taking measures similar to those for the high-speed oscillation system, including the OSC3 and OSC4 pins and the components and lines connected to these pins. (1) Components that are connected to the OSC1 and OSC2 pins, such as oscillators, resistors, and capacitors, should be connected in the shortest line. (2) Whenever possible, configure digital signal lines with at least three millimeters clearance from the OSC1 and OSC2 pins and the components and lines connected to these pins. In particular, signals that are switched frequently must not be placed near these pins, components, and lines. The same applies to all layers on the multi-layered board as the distance between the layers is around 0.1 to 0.2 mm. Furthermore, do not configure digital signal lines in parallel with these components and lines when arranging them on the same or another layer of the board. Such an arrangement is strictly prohibited, even with clearance of three millimeters or more. Also, avoid arranging digital signal lines across these components and signal lines. (3) Shield the OSC1 and OSC2 pins and lines connected to those pins as well as the adjacent layers of the board using VSS. As shown in the figure on the right, shield the wired layers as much as possible. Whenever possible, make the whole adjacent layers the ground layers, or ensure there is adequate shielding to a radius of five millimeters around the above pins and lines. As described in (2), do not configure digital signal lines in parallel with components and lines even if such precautionary measures are taken, and avoid configuring signal lines that are switched frequently across components and lines on other layers. Sample VSS pattern OSC1 and OSC2 OSC2 OSC1 VSS (4) When an external clock is supplied to the OSC1 or OSC3 pin, the clock source should be connected to the OSC1 or OSC3 pin in the shortest line. Furthermore, do not connect anything else to the OSC2 or OSC4 pin. (5) After taking the above precautions, check the output clock waveform while operating the actual application program in the actual device. To do this, measure the output of the CMU_CLK pins with an oscilloscope. Check the waveform quality at the OSC3 or PLL output clock by measuring the CMU_CLK output. Ensure that the frequencies are as designed and that there is no noise or jitters. Check the waveform quality at the OSC1 clock by measuring the CMU_CLK output (after switching the system clock source to OSC1). Scale up the ranges around the rising and falling edges of the clock pulse to ensure that there is no noise, such as clock and spike, in the 100 ns ranges. S1C33401 TECHNICAL MANUAL EPSON I-9-1 Mount I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING If conditions (1) to (3) are not satisfied, the OSC3 or PLL output may be jittery and the OSC1 output may be noisy. When the OSC3 or PLL output is jittery, the operating frequency will be lowered. When the OSC1 output is noisy, operation of the timer using the OSC1 clock and the CPU core after the system clock is switched to the OSC1 pin will be unstable. Reset Circuit * The power-on reset signal which is input to the #RESET pin changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. * In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the #RESET pin in the shortest line. Power Supply Circuit * Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD, VDDE, VSS, AVDD, TMVDD, RTCVDD, PLLVDD and PLLVSS pins with patterns as short and large as possible. In particular, the power supply for AVDD affects A/D conversion precision. (2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS A/D Converter * When the A/D converter is not used, the power supply pin AVDD for the analog system should be connected to VDDE. Arrangement of Signal Lines * In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input unit. * When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a highspeed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit. Prohibited pattern P70 (AIN0) OSC2, OSC4 OSC1, OSC3 Large current signal line High-speed signal line VSS Large current signal line High-speed signal line I-9-2 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING Noise-Induced Erratic Operations I If erratic IC operations appear to be attributable to noise, consider the following five points. (1) TST0 and TST1 pins If these pins are exposed to high-level noise, the entire IC enters test mode or a high-impedance state and becomes inoperable. In such cases, the IC will not be restored, even when the pin is returned to a low level. Therefore, always make sure the TST0 and TST1 pins are connected to GND on the circuit board. Although the IC contains internal pull-down resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k). (2) DSIO pin Exposure of this pin to low-level noise causes the IC to enter debug mode. In debug mode, the clock is output from the DCLK pin and the DST2 pin is high, indicating that the IC is in debug mode. In product versions, it is recommended that the DSIO pin be pulled high by connecting it directly to VDD or through a resistor of 10 k or less. Although the IC contains internal pull-up resistors, it is susceptible to noise because these resistors are high impedance (approximately 50 to 100 k). For details, refer to the "S1C33 Family Application Note." (3) #RESET pin Low-level noise on this pin resets the IC. However, the IC may not always be reset normally, depending on the input waveform. Due to circuit design, this situation tends to occur when the reset input is in the high state, with high impedance. For details, refer to the "S1C33 Family Application Note." (4) #NMI pin Low-level noise on this pin causes an NMI interrupt. Due to the circuit design, this situation tends to occur when the #NMI pin is in the high state, with high impedance. Lower the impedance of #NMI when it is held high, or incorporate corrective measures into the software to protect against erratic operations. (5) VDD, VSS, and VDDE power supplies If noise lower than the rated voltage enters one of these power-supply lines, the IC may operate erratically. Take corrective measures in board design; for example, by using solid patterns for power supply lines, adding decoupling capacitors to eliminate noise, or incorporating surge/noise counteracting devices into the power supply lines. To confirm the above, use an oscilloscope capable of observing higher-frequency waveforms of 200 MHz. The generation of fast noise may not be observed with a low-frequency oscilloscope. If potential noise-induced erratic operations are detected through waveform observations using an oscilloscope, connect the suspected pin to the GND or power supply with low impedance (1 k or less) and check once again. If erratic operations are no longer detected or occur at reduced frequency, or if different symptoms of erratic operations are observed, said pin may with reasonably certainty be considered to be the source of the erratic operations. The TST0, TST1, DSIO, #RESET, and #NMI input circuits described above are designed to detect the edges of the input signal (#NMI can be changed to level sense mode), so that even spike noise may result in erratic operations. Among the digital signal circuits, these pins are most susceptible to noise. In the design of the circuit board, take the following two points into consideration to protect the signal from noise. (A) The most important measure is to lower the signal-driving impedance, as described in each item above. Connect pins to the power supply or GND, with impedance of 1 k or less, preferably 0 . In addition, limit the length of the connected signal lines to approximately 5 cm. (B) Parallel routing of said signal lines with other digital lines on the board is undesirable, since the noise generated when the signal changes from high to low or vice versa may adversely affect signals. The signal may be subject to the most noise when signal lines are laid between multiple signal lines whose states change simultaneously. Take corrective measures by shortening the parallel distance (to several cm) or separating signal lines (2 mm or more). S1C33401 TECHNICAL MANUAL EPSON I-9-3 Mount I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING Reference Refer to Chapter 4, "The Basic S1C33 Chip Board Circuit," in the "S1C33 Family Application Note" for more detailed precautions on the power supply, oscillation, reset, memory, port, and debug. Other The 0.18 m fine-pattern process is employed to manufacture this series of products. Although the product is designed to meet EIAJ and MIL standards regarding basic IC reliability, please pay careful attention to the following points when actually mounting the chip on a board. Since all OSC pins are constructed to use the internal 0.18 m transistors directly, the pins are susceptible to mechanical damage during the board-mounting process. Moreover, the pins may also be susceptible to electrical damage caused by such disturbances (listed below) whose electrical strength, varying gradually with time, could exceed the absolute maximum rated voltage (2.5 V) of the IC: (1) Electromagnetic induction noise from the utility power supply in the reflow process during board-mounting, rework process after board-mounting, or individual characteristic evaluation (experimental confirmation), and (2) Electromagnetic induction noise from the tip of a soldering iron Especially when using a soldering iron, make sure that the IC GND and soldering iron GND are at the same potential before soldering. I-9-4 EPSON S1C33401 TECHNICAL MANUAL I II S1C33401 Technical Manual II C33 ADV CORE BLOCK II C33 ADV CORE BLOCK: PREFACE II.1 Preface I The C33 ADV Core Block consists of seven unit blocks. S1C33 Microcomputer C33 ADV Core Block C33 ADV CPU II Preface DBG MMU HBCU CCU A0RAM (Area 0 No-Wait RAM) CMU Oscillators/PLL A3RAM (Area 3 RAM) Bus Control Block DMA EBCU (SDRAM Controller) Bridge BBCU (SRAM Controller) Peripheral module Peripheral module Peripheral module Peripheral Block Peripheral module Extended Peripheral Block Figure II.1.1 C33 ADV Core Block S1C33401 TECHNICAL MANUAL EPSON II-1-1 II C33 ADV CORE BLOCK: PREFACE CPU 32-bit RISC-type CPU C33 ADV CMU Clock Management Unit Controls the oscillator circuit, PLL, and SSCG to generate the operating clock for the core block and peripheral circuits, and an external bus clock. It also controls per-module clock supply on/off, external reset/NMI input, and standby mode. HBCU High-speed Bus Control Unit Connected directly to the CPU; controls the MMU, CCU, internal memory (A0RAM), and internal high-speed bus of the chip. MMU Memory Management Unit When the CPU accesses logical address space, this unit translates it into physical address at high speed. CCU Cache Control Unit Controls the 8KB instruction/data mixed-type cache. DBG Debug Unit This circuit is provided for debugging programs using the S5U1C33000H/S5U1C33001H (In-Circuit Debugger for the S1C33 Family). A0RAM Area 0 No-Wait RAM For the standard S1C33 ADV models, a high-speed RAM is embedded in area 0. The RAM can be accessed with no wait cycle inserted. II-1-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU II.2 CPU I The C33 ADV Core CPU is a high-end RISC computer in the S1C33 series of Seiko Epson 32-bit microcomputers featuring the extended functionality of the instruction set, with new instructions added, low power consumption, and high processing speed. The C33 ADV Core CPU includes as standard features the multiplier and the multiply-accumulate instructions that conventionally were available as options in the S1C33 series. Combined with the newly added instructions, they will help to accomplish multimedia-related processing easily. What's more, when the C33 ADV Core CPU is combined with a Memory Management Unit (MMU) and a Cache Control Unit (CCU) to configure the CPU core, even faster and more advanced processing will be made possible. As the C33 ADV Core CPU is upward object-code compatible with the C33 STD Core CPU, the software assets of the user that have been amassed in the past can be effectively utilized. II.2.1 Features CPU Processor type * Seiko Epson original 32-bit RISC CPU * 32-bit internal data processing * Contains a 32-bit x 16-bit multiplier Operating-clock frequency * DC to 66 MHz (depending on the processor model) Instruction set * Instruction set useful for multimedia processing * Code length 16-bit fixed length * Number of instructions 164 * Execution cycle Main instructions executed in one cycle Two to three instructions (including immediate-extended instructions) can be executed in one clock cycle * Extended immediate instructions Immediate extended up to 32 bits Multimedia features * Multiplication instructions Multiplications for 16 x 16, 32 x 16, and 32 x 32 bits supported * Multiply-accumulate instructions Step/continuous multiply-accumulate operations for 16 x 16, 32 x 16, and 32 x 32 bits supported * Loop instruction Specified range executed repeatedly * Repeat instruction One instruction executed repeatedly * Saturation instruction Rounded to minimum/maximum values * Postshift function ALU instruction execution with postshift supported Register set * 32-bit general-purpose registers 16 * 32-bit special registers 15 * 32-bit multiply-accumulate operation registers 2 (included in the above special registers) Memory space and external bus * Instruction, data, and I/O coexisting linear space * Up to 4G bytes of memory space * Little endian format (can be switched to big endian) S1C33401 TECHNICAL MANUAL II EPSON II-2-1 II C33 ADV CORE BLOCK: CPU Interrupts * Reset, NMI, and 128 external interrupts supported * Four software exceptions * Two instruction execution exceptions * Direct branching from vector table to interrupt handler routine * MMU exception Reset * Cold reset (all internal circuits reset) * Hot reset (CPU TTBR register and port statuses retained) Power-down mode * HALT mode (only the ADV core turned off) * HALT2 mode (ADV core, BBCU, EBCU, and DMA turned off) * SLEEP mode (circuits other than RTC turned off) Other * MMU supported * Caches supported II-2-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU II.2.2 Registers I The C33 ADV Core CPU contains 16 general-purpose registers and 15 special registers. Special registers bit 31 #15 #14 #13 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 General-purpose registers bit 0 PC SSP USP DBBR IDIR DP TTBR SOR LEA LSA LCO AHR ALR SP PSR bit 31 #15 #14 #13 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 bit 0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 (AHR) R4 (ALR) R3 R2 R1 R0 II CPU Figure II.2.2.1 Registers Table II.2.2.1 Register Access Rights Register symbol PC SSP USP DBBR IDIR DP TTBR SOR LEA LSA LCO AHR ALR SP PSR 1 1 1 1 1 1 1 1 1 1 2 Supervisor mode Name Program counter Supervisor stack pointer User stack pointer Debug base register CPU identification register Data pointer Trap table base register Shift out register Loop end address register Loop start address register Loop count register Arithmetic-operation high register Arithmetic-operation low register Stack pointer Processor status register R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W User mode R R R/W R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W 3 1 New registers added to the C33 ADV Core CPU 2 When the SP register is referenced, either SSP or USP is referenced. 3 Some bits in the PSR cannot be accessed for writing in user mode. S1C33401 TECHNICAL MANUAL EPSON II-2-3 II C33 ADV CORE BLOCK: CPU II.2.3 Instruction Set Table II.2.3.1 S1C33-Series-Compatible Instructions Classification Arithmetic operation add adc sub sbc cmp Branch II-2-4 mlt.h mltu.h mlt.w mltu.w div0s div0u div1 div2s div3s jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d jp jp.d call call.d Mnemonic %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,imm6 %sp,imm10 %rd,%rs %rd,%rs %rd,sign6 %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rs %rs %rs %rs %rs sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 sign8 %rb sign8 %rb Function Addition between general-purpose registers Addition of a general-purpose register and immediate Addition of SP and immediate (with immediate zero-extended) Addition with carry between general-purpose registers Subtraction between general-purpose registers Subtraction of general-purpose register and immediate Subtraction of SP and immediate (with immediate zero-extended) Subtraction with carry between general-purpose registers Arithmetic comparison between general-purpose registers Arithmetic comparison of general-purpose register and immediate (with immediate zero-extended) Signed integer multiplication (16 bits x 16 bits 32 bits) Unsigned integer multiplication (16 bits x 16 bits 32 bits) Signed integer multiplication (32 bits x 32 bits 64 bits) Unsigned integer multiplication (32 bits x 32 bits 64 bits) First step in signed integer division First step in unsigned integer division Execution of step division Data correction for the result of signed integer division 1 Data correction for the result of signed integer division 2 PC relative conditional jump Branch condition: !Z & !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: !(N ^ V) Delayed branching possible PC relative conditional jump Branch condition: N ^ V Delayed branching possible PC relative conditional jump Branch condition: Z | N ^ V Delayed branching possible PC relative conditional jump Branch condition: !Z & !C Delayed branching possible PC relative conditional jump Branch condition: !C Delayed branching possible PC relative conditional jump Branch condition: C Delayed branching possible PC relative conditional jump Branch condition: Z | C Delayed branching possible PC relative conditional jump Branch condition: Z Delayed branching possible PC relative conditional jump Branch condition: !Z Delayed branching possible PC relative jump Delayed branching possible Absolute jump Delayed branching possible Delayed call possible PC relative subroutine call Absolute subroutine call Delayed call possible EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU Classification Branch Data transfer Mnemonic ret ret.d reti retd int brk ld.b ld.ub ld.h ld.uh ld.w imm2 %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%sp+imm6] [%rb],%rs [%rb]+,%rs [%sp+imm6],%rs %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%sp+imm6] %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%sp+imm6] [%rb],%rs [%rb]+,%rs [%sp+imm6],%rs %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%sp+imm6] %rd,%rs %rd,sign6 %rd,[%rb] %rd,[%rb]+ %rd,[%sp+imm6] [%rb],%rs [%rb]+,%rs [%sp+imm6],%rs System control nop halt slp Immediate extension ext Bit manipulation btst bclr bset bnot Other swap mirror mac pushn popn S1C33401 TECHNICAL MANUAL imm13 [%rb],imm3 [%rb],imm3 [%rb],imm3 [%rb],imm3 %rd,%rs %rd,%rs %rs %rs %rd Function Subroutine return Delayed return possible Return from interrupt or exception handling Return from the debug processing routine Software exception Debug exception General-purpose register (byte) general-purpose register (sign-extended) Memory (byte) general-purpose register (sign-extended) Postincrement possible Stack (byte) general-purpose register (sign-extended) General-purpose register (byte) memory Postincrement possible General-purpose register (byte) stack General-purpose register (byte) general-purpose register (zero-extended) Memory (byte) general-purpose register (zero-extended) Postincrement possible Stack (byte) general-purpose register (zero-extended) General-purpose register (halfword) general-purpose register (sign-extended) Memory (halfword) general-purpose register (sign-extended) Postincrement possible Stack (halfword) general-purpose register (sign-extended) General-purpose register (halfword) memory Postincrement possible General-purpose register (halfword) stack General-purpose register (halfword) general-purpose register (zero-extended) Memory (halfword) general-purpose register (zero-extended) Postincrement possible Stack (halfword) general-purpose register (zero-extended) General-purpose register (word) general-purpose register Immediate general-purpose register (sign-extended) Memory (word) general-purpose register Postincrement possible Stack (word) general-purpose register General-purpose register (word) memory Postincrement possible General-purpose register (word) stack No operation HALT SLEEP Extend operand in the following instruction Test a specified bit in memory data Clear a specified bit in memory data Set a specified bit in memory data Invert a specified bit in memory data Bytewise swap on byte boundary in word Bitwise swap every byte in word Multiply-accumulate operation 16 bits x 16 bits + 64 bits 64 bits Push general-purpose registers %rs-%r0 onto the stack Pop data for general-purpose registers %rd-%r0 off the stack EPSON II-2-5 I II CPU II C33 ADV CORE BLOCK: CPU Table II.2.3.2 Function Extended Instructions Classification Logical operation and Mnemonic %rd,%rs %rd,sign6 or %rd,%rs scan0 %rd,%rs Logical OR of general-purpose register and immediate Exclusive OR between general-purpose registers Exclusive OR of general-purpose register and immediate Logical inversion between general-purpose registers (1's complement) Logical inversion of general-purpose register and immediate (1's complement) Logical shift to the right (Bits 0-31 shifted as specified by the register) Logical shift to the right (Bits 0-31 shifted as specified by immediate) Logical shift to the left (Bits 0-31 shifted as specified by the register) Logical shift to the left (Bits 0-31 shifted as specified by immediate) Arithmetic shift to the right (Bits 0-31 shifted as specified by the register) Arithmetic shift to the right (Bits 0-31 shifted as specified by immediate) Arithmetic shift to the left (Bits 0-31 shifted as specified by the register) Arithmetic shift to the left (Bits 0-31 shifted as specified by immediate) Rotate to the right (Bits 0-31 rotated as specified by the register) Rotate to the right (Bits 0-31 rotated as specified by immediate) Rotate to the left (Bits 0-31 rotated as specified by the register) Rotate to the left (Bits 0-31 rotated as specified by immediate) Special register (word) general-purpose register General-purpose register (word) special register Search for bits whose value = 0 scan1 %rd,%rs Search for bits whose value = 1 %rd,sign6 xor %rd,%rs %rd,sign6 not %rd,%rs %rd,sign6 Shift and rotate srl %rd,%rs %rd,imm5 sll %rd,%rs %rd,imm5 sra %rd,%rs %rd,imm5 sla %rd,%rs %rd,imm5 rr %rd,%rs %rd,imm5 rl %rd,%rs %rd,imm5 Data transfer ld.w %rd,%ss %sd,%rs Other II-2-6 Extended function Function Mode in which the V flag is Logical AND between general-purpose cleared after instruction registers execution has been added. Logical AND of general-purpose register and immediate Logical OR between general-purpose registers EPSON For rotate/shift operation, it has been made possible to shift 9-31 bits. The number of special registers that can be used to load data has been increased. The number of bits that can be scanned has been increased to 32 bits. S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU Table II.2.3.3 Instructions Added to the C33 ADV Core CPU Classification Arithmetic operation Branch Data transfer System control Multifunction extension Coprocessor control Other add mlt.hw mac.hw mac.w mac1.h mac1.hw mac1.w div.w divu.w jpr jpr.d retm ld.b ld.ub ld.h ld.uh ld.w ld.b ld.h ld.w psrset psrclr ext ext ext ext ld.c ld.c do.c ld.cf macclr swaph push pop pushs pops sat.b sat.ub sat.h sat.uh sat.w sat.uw loop Mnemonic %rd,%dp %rd,%rs %rs %rs %rd,%rs %rd,%rs %rd,%rs %rs %rs %rb %rd,[%dp+imm6] %rd,[%dp+imm6] %rd,[%dp+imm6] %rd,[%dp+imm6] %rd,[%dp+imm6] [%dp+imm6],%rs [%dp+imm6],%rs [%dp+imm6],%rs imm5 imm5 %rb cond op,imm2 %rb,op,imm2 %rd,imm4 imm4,%rs imm6 %rd,%rs %rs %rd %ss %sd %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rc,%ra %rc,imm4 repeat imm4,imm4 %rc imm4 S1C33401 TECHNICAL MANUAL I Function Addition of DP register Signed integer multiplication 32 bits x 16 bits 64 bits Multiply-accumulate operation 32 bits x 16 bits + 64 bits 64 bits Multiply-accumulate operation 32 bits x 32 bits + 64 bits 64 bits Single multiply-accumulate operation 16 bits x 16 bits + 64 bits 64 bits Single multiply-accumulate operation 32 bits x 16 bits + 64 bits 64 bits Single multiply-accumulate operation 32 bits x 32 bits + 64 bits 64 bits Signed integer division 32 bits / 32 bits 16 bits ... 16 bits Unsigned integer division 32 bits / 32 bits 16 bits ... 16 bits PC relative jump Delayed branching possible Return from MMU exception handler routine Memory indirect (byte) general-purpose register (sign-extended) Memory indirect (byte) general-purpose register (zero-extended) Memory indirect (halfword) general-purpose register (sign-extended) Memory indirect (halfword) general-purpose register (zero-extended) Memory indirect (word) general-purpose register General-purpose register (byte) memory indirect (sign-extended) General-purpose register (halfword) memory indirect (sign-extended) General-purpose register (word) memory indirect Set a specified bit in PSR Clear a specified bit in PSR Execute following instructions for 3 operands Conditional execution Postshift 3 operands execution + postshift Load data from coprocessor Store data in coprocessor Execute coprocessor Load C, V, Z, and N flags from coprocessor Clear ALR and AHR registers and MO flag to 0 Bytewise swap on halfword boundary in word Push single general-purpose register Pop single general-purpose register Push special registers %ss-ALR onto the stack Pop data for special registers %sd-ALR off the stack Signed saturation processing of general-purpose register (byte) Unsigned saturation processing of general-purpose register (byte) Signed saturation processing of general-purpose register (halfword) Unsigned saturation processing of general-purpose register (halfword) Signed saturation processing of general-purpose register (word) Unsigned saturation processing of general-purpose register (word) Execute specified range (general-purpose register) the specified number of times (general-purpose register) Execute specified range (immediate) the specified number of times (generalpurpose register) Execute specified range (immediate) the specified number of times (immediate) Execute following instructions (as many times as specified by the generalpurpose register) Execute following instructions (as many times as specified by the immediate) EPSON II-2-7 II CPU II C33 ADV CORE BLOCK: CPU II.2.4 Address Space and Logical to Physical Address Translation II.2.4.1 Overview The C33 ADV Core CPU supports a 4GB address space. Addresses output from the CPU can be translated into other predefined addresses by the HBCU and MMU, so the CPU does not need to output the addresses that are assigned to the actual ROM, RAM, and I/O devices. In other words, the CPU can access a 4GB linear logical address space (virtual space) that is able to build with free memory configuration. The HBCU translates the logical address output from the CPU into a physical address using the MMU and it sends the translated address to the BBCU, which manages the physical address space, to access the actual device. The 4GB physical address space is divided into 23 areas by the BBCU, and different memory or I/O devices can be mapped into each area. The logical address output from the CPU is subjected to the five processes listed below by the HBCU, MMU, and BBCU to finally generate the physical address. 1. Block process 2. ASID process 3. Address translation process 4. Mirroring process 5. Area process Block 7 (512M bytes) Block 6 (512M bytes) Block 5 (512M bytes) Block 4 (512M bytes) Block 3 (512M bytes) Block 2 (512M bytes) Block 1 (512M bytes) Block 0 (512M bytes) Logical space 0xFFFF FFFF : : 0xE000 0000 0xDFFF FFFF : : 0xC000 0000 0xBFFF FFFF : : 0xA000 0000 0x9FFF FFFF : : 0x8000 0000 0x7FFF FFFF : : 0x6000 0000 0x5FFF FFFF : : 0x4000 0000 0x3FFF FFFF : : 0x2000 0000 0x1FFF FFFF : : 0x0000 0000 Physical space HBCU, MMU, BBCU Area 22 2G bytes Block processing ASID processing Address translation processing Area 21 1G bytes Mirroring processing Area processing Area 20 512M bytes Areas 19-0 512M bytes Figure II.2.4.1.1 Relationship between Logical and Physical Address Spaces The following sections explain the outline of the address processing. For details of each process, see the HBCU, MMU, and BBCU sections. II-2-8 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU II.2.4.2 Address Processing I Address processing modules Figure II.2.4.2.1 shows the functional modules that process addresses output from the CPU. HBCU CPU * Outputs logical addresses to access a 4GB linear address space. * Divides the logical space into 8 blocks and sets the attribute for each block. * Configures multiple virtual spaces using ASID. MMU CCU BBCU * Physical address cache after mirror processing * Performs mirror processing. * Translates logical addresses into physical addresses. * Decodes physical addresses to decide areas (chip enable) to access. * Outputs the physical address with the generated chip enable to the external bus. Memories and I/O devices II CPU Figure II.2.4.2.1 Functional Modules for Address Processing Address processing flow Logical address CPU output Block processing ASID processing Block 7 (0.5GB) 63 (64MB) 62 (64MB) Physical address When MMU is not used Physical address cache Block 6 (0.5GB) Address translation (when MMU is used) Block 5 (0.5GB) CPU 1M/64K (4KB/64KB) Block 4 (0.5GB) Area 21 (1GB) Block 2 (0.5GB) Block 0 (0.5GB) Output of a logical address to access a 4GB linear address space Setting use or not use attributes for MMU, ASID, instruction cache, data cache, and write-back mode HBCU Area 22 (2GB) Mirroring Block 3 (0.5GB) Block 1 (0.5GB) Area processing Mirror processing 3 (64MB) 2 (64MB) 1 (64MB) 0 (64MB) Multiplexing 64 spaces using 6 bits of ASID HBCU 3 (4KB/64KB) 2 (4KB/64KB) 1 (4KB/64KB) 0 (4KB/64KB) 1GB Map 4KB or 64KB of pages to any desired physical addresses Setting the highorder 3GB as the mirror areas of the low-order 1GB MMU HBCU Area 20 (512MB) Areas 19-0 (512MB) Control of the #CE signal, wait cycles, and other access conditions for each area BBCU Figure II.2.4.2.2 Contents of Address Processing S1C33401 TECHNICAL MANUAL EPSON II-2-9 II C33 ADV CORE BLOCK: CPU Address processing for internal peripheral circuits and internal memories CPU Area 0 A0RAM Other than areas 0-3 Internal bus Areas 1, 2, and 3 Block processing ASID processing MMU processing Areas 1-3 peripherals/ memories BBCU Mirror processing External bus Cache Peripherals/ memories in area 6, etc. Figure II.2.4.2.3 Differences on Accesses to Internal Areas and External Areas Addresses that are mainly output to the external bus to access areas other than areas 0-6 are subject to the address processing described above. Normally, ASID and MMU are disabled to use in areas 0-6. Furthermore, these areas are not mirrored. Therefore, the address processing for areas 0-6 is different from the above description. A high-speed RAM (A0RAM) is mapped to area 0 and is accessed with no wait cycle using addresses output from the CPU directly. Areas 1, 2, and 3 are dedicated to the internal peripheral circuits and memories and block processing to mirror processing are not performed. Addresses from the CPU pass through the internal bus and directly access the internal modules mapped to areas 1-3. Areas 4, 5, and 6 are external memory areas, note, however, that normally block processing to mirror processing are not performed as in areas 1-3. Addresses from the CPU are directly passed to the BBCU and are output to the external bus. Area 6 is often used for embedded modules (model-specific circuits and extension peripheral circuits/ memories) other than the standard peripheral circuits mapped to area 1. Also in this case, addresses from the CPU are directly passed to the BBCU to access area 6. Areas 0-6 can be enabled to process their addresses with ASID and MMU by setting the HBCU in user mode only. Note that these areas cannot be mirrored even in this case. II-2-10 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU II.2.4.3 Block Processing I The HBCU divides the 4GB logical address space into eight 0.5GB blocks and manages the attributes shown below (can be set with software) in each block. 1. MMU (address translation) Used/not used 2. ASID Used/not used 3. Instruction cache Used/not used 4. Data cache Used/not used 5. Write-back mode for cache Used/not used When the CPU outputs a logical address, the HBCU controls the address processing according to the attributes in the block that includes the address. Block 7 (512M bytes) Block 6 (512M bytes) Block 5 (512M bytes) Block 4 (512M bytes) Block 3 (512M bytes) Block 2 (512M bytes) Block 1 (512M bytes) Block 0 (512M bytes) Logical address space 0xFFFF FFFF Block 7 : attribute 0xE000 0000 0xDFFF FFFF Block 6 : attribute 0xC000 0000 0xBFFF FFFF Block 5 : attribute 0xA000 0000 0x9FFF FFFF Block 4 : attribute 0x8000 0000 0x7FFF FFFF Block 3 : attribute 0x6000 0000 0x5FFF FFFF Block 2 : attribute 0x4000 0000 0x3FFF FFFF Block 1 : attribute 0x2000 0000 0x1FFF FFFF Block 0 : attribute 0x0000 0000 II Physical address space Area 22 2G bytes CPU Area 21 1G bytes Area 20 512M bytes Areas 19-0 512M bytes * MMU Used/Not used * ASID Used/Not used * Instruction cache Used/Not used * Data cache Used/Not used * Data cache write back Used/Not used Block attribute (selectable in each block) Figure II.2.4.3.1 Division of Logical Address Space into Blocks S1C33401 TECHNICAL MANUAL EPSON II-2-11 II C33 ADV CORE BLOCK: CPU II.2.4.4 ASID Processing The 6 high-order bits of the logical address is replaced with an ASID that can be specified with software to create 64MB x 64 multiple virtual spaces. When the block has the "ASID not used" attribute, this processing is bypassed. Logical address 0x1FFF FFFF 0x1C00 0000 0x1B0F FFFF 0x1800 0x17FF 0x1400 0x13FF 0x1000 0x0FFF 0x0C00 0x0B0F 0x0800 0x07FF 0x0400 0x03FF 0x0000 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 V[25:0] 0x03FF FFFF 0x0000 0000 Block 0 Blocks 1, 2, 3, 4, 5, 6 Logical address 0xFFFF FFFF 0xFC00 0000 0xFB0F FFFF 0xF800 0000 0xF7FF FFFF 0xF400 0000 0xF3FF FFFF 0xF000 0000 0xEFFF FFFF 0xEC00 0000 0xEB0F FFFF Process 7 64MB Process 6 64MB Process 5 64MB Process 4 64MB Process 3 64MB Process 2 64MB Process 1 64MB Process 0 64MB * ASID = 0x0 ASID = 0x1 ASID = 0x2 Process 0 Process 1 Process 2 * * * * * 0xE800 0xE7FF 0xE400 0xE3FF 0xE000 0000 FFFF 0000 FFFF 0000 Block 7 Process 63 64MB Process 62 64MB Process 61 64MB Process 60 64MB Process 59 64MB Process 58 64MB Process 57 64MB Process 56 64MB ASID = 0x3F Process 63 ***** Figure II.2.4.4.1 Multiple Virtual Spaces using the ASID II.2.4.5 MMU Processing (Address Translation) The logical address is translated to a physical address in page (4KB or 64KB selectable) units. The 20 high-order bits of the logical address for 4KB per page or the 16 high-order bits of logical address for 64KB per page can be translated into a desired physical address. The MMU hardware contains a 64-entry TLB that can be used as an address translation table for translating up to 1M pages in 4KB per page or 64K pages in 64KB per page. The software (OS) manages the contents of the translation table. When the block has the "MMU not used" attribute, this processing is bypassed. Logical address Physical address : : : : : : : (Page 2) : : (Page 0) Page 2 Page 1 Page 0 4KB or 64KB per page (Page 1) Logical addresses are mapped to physical addresses in page units. Figure II.2.4.5.1 Address Translation II-2-12 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CPU II.2.4.6 Mirror Processing I After the physical address has been decided, a mirror processing that creates 3 mirror areas of low-order 1GB by replacing the 2 high-order bits of the address can be performed. A physical address area can be accessed with different logical addresses, it makes it possible to use different block attributes. The physical address cache in the CCU reads/writes data from/to the memory using the address after mirror processing. 0xFFFF FFFF Blocks 6 and 7 (1G bytes) Mirror area Non-mirror area Blocks 4 and 5 (1G bytes) Logical address 0xC010 0xC00F 0xC000 0xBFFF 0000 FFFF 0000 FFFF 0x8010 0x800F 0x8000 0x7FFF 0000 FFFF 0000 FFFF II Mirror area Non-mirror area Blocks 2 and 3 (1G bytes) CPU Share physical addresses 0x100000 to 0x3FFFFFFF Mirror area Non-mirror area Blocks 0 and 1 (1G bytes) Effective area 0x4010 0000 0x400F FFFF 0x4000 0000 0x3FFF FFFF 0x0010 0000 0x0000 0000 Figure II.2.4.6.1 Address Space when Mirrors Area Set II.2.4.7 Area Processing The BBCU allows each area in the physical address space to be configured with connecting device type, bus access timing parameters, and other conditions. Areas 4 to 22 are enabled to output the addresses externally to access external devices. Area 13 Area 12 Area 11 Area 10 Area 9 Area 8 Area 7 Area 6 Area 5 Area 4 Area 3 Area 2 Area 1 Area 0 0x02FF FFFF 0x0200 0x01FF 0x0180 0x017F 0x0100 0x00FF 0x00C0 0x00BF 0x0080 0x007F 0x0060 0x005F 0x0040 0x003F 0x0030 0x002F 0x0020 0x001F 0x0010 0x000F 0x0008 0x0007 0x0006 0x0005 0x0002 0x0001 0x0000 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 External Memory 16M bytes External Memory 8M bytes External Memory 8M bytes External Memory 4M bytes External Memory 4M bytes External Memory 2M bytes External Memory 2M bytes External Memory 1M bytes External Memory 1M bytes External Memory 1M bytes Internal RAM 512K bytes For debugging 128K bytes Internal I/O 256K bytes Internal RAM 128K bytes Area 22 0xFFFF FFFF Area 21 0x8000 0000 0x7FFF FFFF Area 20 0x4000 0000 0x3FFF FFFF Area 19 0x2000 0000 0x1FFF FFFF Area 18 Area 17 Area 16 Area 15 Area 14 0x1000 0x0FFF 0x0C00 0x0BFF 0x0800 0x07FF 0x0600 0x05FF 0x0400 0x03FF 0x0300 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 External Memory 2G bytes External Memory 1G bytes External Memory 512M bytes External Memory 256M bytes External Memory 64M bytes External Memory 64M bytes External Memory 32M bytes External Memory 32M bytes External Memory 16M bytes Figure II.2.4.7.1 Area Layout in Physical Address Space S1C33401 TECHNICAL MANUAL EPSON II-2-13 II C33 ADV CORE BLOCK: CPU THIS PAGE IS BLANK. II-2-14 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3 Clock Management Unit (CMU) I II.3.1 Overview of the CMU The Clock Management Unit (CMU) controls the operating clock supplied to each functional block. The main functions of the CMU are outlined below. * Controls reset and NMI inputs * Selects the system clock source (OSC3, PLL, or OSC1) * Controls on/off of the OSC3 and OSC1 oscillator circuits * Controls on/off and frequency multiplication rate of the PLL * Controls SSCG * Clock control corresponding to standby modes (SLEEP, HALT, and HALT2) * Selects divide ratios of the core clock and peripheral circuit clock * Selects an external bus clock * Controls on/off of clock supply for each function block (manual/auto) Through system clock selection, oscillator circuit, and PLL control, and core/peripheral circuit clock divide ratio selection and clock on/off control for each functional block (with automatic control also possible), the CMU enables the most suitable operating clock frequency to be selected for the processing involved, as well as to turn off unnecessary clock supply, which combined with standby mode, helps to significantly reduce power consumption on the chip. OSC3 oscillator OSC/PLL control and selector OSC1 oscillator PLL CMU Divider (1/1, 1/2, 1/4, 1/8) Core system clock (CCLK) selector Core system CCLK clock On/Off control Peripheral system clock (PCLK) selector Peripheral PCLK system clock On/Off control To core and bus control blocks To peripheral block External bus clock (CMU_CLK) selector CMU_CLK Power-down control Reset/NMI control External NMI External Reset NMI RESET Figure II.3.1.1 CMU Block Diagram Note: The clock automatic supply control function for each functional block is effective only when the operating frequency is 50 MHz or lower. Do not use the clock automatic supply control function when the operating frequency exceeds 50 MHz. S1C33401 TECHNICAL MANUAL EPSON II-3-1 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.2 Reset Input and Initial Reset The CMU also has a function to generate an internal reset signal from external reset input (#RESET). II.3.2.1 Initial Reset Pins Table II.3.2.1.1 lists the pins used to initially reset the chip. Table II.3.2.1.1 Initial Reset Pins Pin name Function I/O #RESET I #NMI I Initial reset input pin (Low active) Low: Resets the CPU. NMI request input pin This pin is also used for selecting a reset method. High: Cold start Low: Hot start The S1C33 chip is reset by the low state (= 0) on the #RESET input pin, and starts operating when the reset signal is released back to high (= 1). The core CPU and internal peripheral circuits are initialized while the reset signal is kept low. II.3.2.2 Cold Reset and Hot Reset One of two reset methods (cold reset or hot reset) can be used to start the S1C33 chip. The #RESET and #NMI pins are also used to specify either method. Table II.3.2.2.1 shows the differences between cold reset and hot reset. Table II.3.2.2.1 Differences between Cold Reset and Hot Reset Hot reset Cold reset Setup contents Reset condition CPU: TTBR CPU: PC CPU: PSR CPU: Other registers CPU: Operating clock Oscillation circuit I/O pin status (0x40340-0x40395) Other peripheral circuit #RESET = low & #NMI = high #RESET = low & #NMI = low Initialized to 0x20000000 Status is retained. The vector at the TTBR boot address is loaded to the PC. All the PSR bits are reset to 0. Undefined The CPU operates with the OSC3 clock. Both the OSC1 and OSC3 circuits start oscillating. Initialized Status is retained. Initialized or undefined Cold reset initializes the CPU and all internal peripheral circuits, and is therefore useful for power-on reset. Hot reset initializes the CPU and internal peripheral circuits, but does not initialize the input/output ports and TTBR of the CPU. Therefore, hot reset is useful when the chip must be reset while operating, with the input/output port status retained. Note, however, that the input signal to the #NMI pin used to specify a reset method should be applied at the timing shown in Figure II.3.2.2.1. Cold reset is generated (#RESET = low & #NMI = high) Hot reset is generated (#RESET = low & #NMI = low) #NMI #NMI #RESET #RESET #NMI must be set to high longer than the reset pulse width. #NMI must be set to low longer than the reset pulse width. (1) Cold reset (2) Hot reset Figure II.3.2.2.1 Settings of #RESET and #NMI Pins Note: Even if the #RESET pin is pulled low (= 0), the chip may not be reset unless supplied with a clock. To confirm that the chip is reset, #RESET should be held low for at least 10 OSC3 clock cycles. However, the input/output port pins are initialized by cold reset regardless of whether the chip is supplied with a clock. II-3-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.2.3 Power-on Reset I When turning on the power for the chip, always be sure to cold reset the chip to ensure that it will start operating normally. Since the #RESET pin is a gate input, a power-on reset circuit should be configured external to the chip. Initial reset (#RESET = 0) causes the high-speed (OSC3) oscillator circuit to start oscillating, and when the reset signal is released back high, the CPU starts operating with the OSC3 clock. The high-speed (OSC3) oscillator circuit requires a finite time until its oscillation stabilizes after it starts operating. To confirm that the CPU is started, the initial reset can only be deasserted after this oscillation stabilization time elapses. Note: The oscillation start time of the high-speed (OSC3) oscillator circuit varies with the device used, board patterns, and operating environment. Therefore, sufficient time should be provided before the reset signal is deasserted. II Power-on sequence To ensure that the chip will operate normally, observe the timing requirements given below when turning on the power for the chip. I/O power voltage VDDE, AVDD Internal power voltage VDD, PLLVDD OSC3 VDD min. tSTA3 tRST tVDD #RESET Figure II.3.2.3.1 Power-on Sequence (1) tVDD: The time until the power supply for the chip stabilizes after being turned on. Turn on the power supplies in order of the following (or at the same time): Internal core power supply (e.g., VDD, PLLVDD) I/O power supply (e.g., VDDE, AVDD) input signal applied (2) tSTA3: OSC3 oscillation start time (3) tRST: Minimum reset pulse width Make sure #RESET is held low (= 0) for at least 10 clock cycles after the OSC3 clock supplied to the CMU has stabilized. II.3.2.4 Boot Address When the #RESET pin is released back high (= 1) after the reset period, the core CPU reads the reset vector (program start address) from the boot address (0x20000000 set in the TTBR register at cold reset) and sets it in the Program Counter (PC). The core CPU starts executing the program from that address. The trap table that contains trap vectors for interrupts, etc., also begins by default with this boot address. (Refer to the S1C33 Family C33 ADV Core CPU Manual.) The base address of the trap table is set in TTBR, and can be changed to any 1KB boundary address. S1C33401 TECHNICAL MANUAL EPSON II-3-3 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.2.5 Precautions to be Taken during Initial Reset Core CPU When initially reset, all internal registers of the core CPU (except PSR) become unstable. Therefore, these registers must be initialized in a program. In particular, the Stack Pointer (SP) should always be initialized before accessing the stack. Note that NMI requests are masked in hardware until data is written to the SP after initial reset, to prevent erratic operation. Internal RAM The content of internal RAM becomes unstable when initially reset. Internal RAM must be initialized as required. High-speed (OSC3) oscillator circuit When initially reset, the high-speed (OSC3) oscillator circuit starts oscillating, and when the reset signal is deasserted, the CPU starts operating with the OSC3 clock. To prevent erratic operation due to an instable clock when the chip is reset at power-on or while the high-speed (OSC3) oscillator circuit is idle, the reset signal should not be deasserted until after oscillation stabilizes. Low-speed (OSC1) oscillator circuit When the chip is reset at power-on or while the low-speed (OSC1) oscillator circuit is idle, the low-speed (OSC1) oscillator circuit also starts oscillating. The low-speed (OSC1) oscillator circuit requires a longer time for oscillation to stabilize than the high-speed (OSC3) oscillator circuit. (See the electrical characteristics table.) To prevent erratic operation due to an instable clock, the OSC1 clock should not be used until after this stabilization time elapses. Input/output ports and input/output pins Cold reset initializes the control and data registers of the input/output ports. When the chip is hot reset, the control registers and pins retain the status held before the reset. However, if these pins are set for use as input/output pins for the internal peripheral circuit, the control registers of the peripheral circuit are initialized or made unstable by initial reset and must, therefore, be set up back again in a program. Other internal peripheral circuits The control and data registers of other peripheral circuits are initialized or made unstable by initial reset, regardless of the reset method (cold or hot reset). Therefore, these registers should be set up as required in a program. For details on how peripheral circuits are initialized by initial reset, see each I/O map or circuit description. II-3-4 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.3 NMI Input I The external NMI signal is input from the #NMI pin to the CMU, then forwarded to the CPU. For details about NMI exception handling by the CPU, refer to the S1C33 Family C33 ADV Core CPU Manual. II.3.3.1 NMI Detection Mode The method of detecting whether to recognize NMI input by a falling edge or low level can be selected by using NMIMD (D8/0x4836C). NMIMD: NMI Detection Mode Select Bit in the NMI Mode Register (D8/0x4836C) When initially reset, NMIMD (D8/0x4836C) is set to 0, with falling edge detection mode selected. When NMI input must be recognized by level, set NMIMD (D8/0x4836C) to 1. Note: At least a 3-system clock width of low pulse is required to generate NMI even if falling edge detection mode has been selected. After the NMI signal falls, maintain it at a low level for 3 or more clock cycles. II.3.3.2 NMI Flag When an NMI request is detected by a falling edge or low level as selected above, the NMIF flag (D12/0x4836A) is set to 1. NMIF: NMI Flag in the NMI Flag Register (D12/0x4836A) This signal is forwarded to the CPU for generating an NMI exception. Writing a 1 to the bit (D12/0x4836A) resets the previously set NMIF flag. Notes: * The NMIF flag (D12/0x4836A) should always be reset by writing a 1 in the NMI exception handler routine. Otherwise, an NMI exception may be generated again when the NMI exception handler routine is terminated by the reti instruction. * NMI cannot be nested. The CPU keeps NMI input masked out until the reti instruction is executed after an NMI exception occurred. S1C33401 TECHNICAL MANUAL EPSON II-3-5 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.4 Selecting the System Clock Source The CMU has the following three clock inputs, one of which can be selected as the source clock (OSC) for the system (core clock, peripheral circuit clock, and external bus clock). 1. OSC3 clock This clock is generated by the OSC3 oscillator circuit or supplied from an external source through the OSC3 pin. The oscillation frequency/input frequency varies with each S1C33 model. For details about the OSC3 oscillator circuit, see "OSC3 Oscillator Circuits, PLL and SSCG" in Chapter IV, "C33 ADV Basic Peripheral Block." The CMU control registers can be used for on/off control of the OSC3 oscillator circuit (see Section II.3.5). 2. OSC1 clock This is the source clock (32.768 kHz, typ.) for the Real Time Clock (RTC). When high-speed operation is unnecessary, this low-speed clock may be used to operate the system, thus helping to reduce power consumption on the chip. For details about the OSC1 oscillator circuit, see "Real Time Clock (RTC)" in Chapter V, "Extension Peripheral Circuit Block." The CMU control registers can be used for on/off control of the OSC1 oscillator circuit (see Section II.3.5). 3. PLL clock This is the clock output by the PLL. The PLL multiplies the OSC3 clock frequency by a given value to generate a clock for high-speed operation. The frequency multiplication rate that can be set depends on the upper-limit operating clock frequency of each S1C33 model and the OSC3 oscillation frequency. For details about the PLL, see "OSC3 Oscillator Circuits, PLL and SSCG" in Chapter IV, "C33 ADV Basic Peripheral Block." The CMU control registers can be used for on/off control of the PLL and to set the frequency multiplication rate (see Section II.3.6). The clock source can be selected as shown in Table II.3.4.1 by using OSCSEL[1:0] (D[3:2]/0x48360). OSCSEL[1:0]: OSC Clock Select Bits in the Core System Clock Control Register (D[3:2]/0x48360) Table II.3.4.1 Selection of the System Clock Source OSCSEL1 OSCSEL0 1 1 0 0 1 0 1 0 Clock source PLL OSC3 OSC1 OSC3 (Default: 0b00 = OSC3) The clock source changed here is not reflected until after the CPU returns from SLEEP mode. Therefore, the slp instruction must be executed once after setting OSCSEL[1:0] (D[3:2]/0x48360). Although the CPU returns from SLEEP mode to normal operation by an external interrupt from a port, for example, several functions are provided for use in clock source changes, thus automatically returning the CPU from SLEEP mode a certain time after slp instruction execution or leaving the OSC3 oscillator circuit turned on during SLEEP mode. Section II.3.12, "Standby Modes," describes these methods of control in detail. Notes: * The Core System Clock Control Register (0x48360) is write-protected. Before this and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. * When clock sources are changed, the CMU control registers must be set so that the CMU is supplied with a clock from the selected clock source upon returning from SLEEP mode immediately after the change. Otherwise, the chip does not restart after the return from SLEEP mode. II-3-6 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.5 Controlling the Oscillator Circuit I The SOSC3 (D1/0x48360) bit used for on/off control of OSC3 oscillation and the SOSC1 (D0/0x48360) bit for on/off control of OSC1 oscillation are provided in the CMU control register. However, since the OSC3 and OSC1 oscillator circuits are not incorporated in the core block, see "OSC3 Oscillator Circuits, PLL and SSCG" in Chapter IV, "C33 ADV Basic Peripheral Block," for details of the OSC3 oscillator circuit, and "Real Time Clock (RTC)" in Chapter V, "Extension Peripheral Circuit Block," for details of the OSC1 oscillator circuit. SOSC3: High-speed Oscillation (OSC3) On/Off Bit in the Core System Clock Control Register (D1/0x48360) SOSC1: Low-speed Oscillation (OSC1) On/Off Bit in the Core System Clock Control Register (D0/0x48360) Setting these bits to 0 turns off the respective oscillator circuits. Setting these bits to 1 turns on the respective oscillator circuits for initiating clock output. When initially reset, both control bits are set to 1, with the oscillators oscillating. Notes: * The Core System Clock Control Register (0x48360) is write-protected. Before this and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. * When SOSC3 (D1/0x48360) or SOSC1 (D0/0x48360) is set from 0 to 1, thus initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes. Moreover, to prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses. S1C33401 TECHNICAL MANUAL EPSON II-3-7 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.6 Controlling the PLL The PLL multiplies the OSC3 clock frequency by a given value to generate a source clock for high-speed operation. PLL input clock frequency: 5 to 150 MHz PLL output clock frequency: 20 to 200 MHz Frequency-multiplication rate: 1 to 16 times The PLL control bits are provided in the CMU control registers. However, since the PLL is not incorporated in the core block, see "OSC3 Oscillator Circuits, PLL and SSCG" in Chapter IV, "C33 ADV Basic Peripheral Block," for details about the PLL. II.3.6.1 On/Off Control of the PLL PLLPOWR (D0/0x40184) can be used to turn the PLL on or off. PLLPOWR: PLL On/Off Control Bit in PLL Control Register 1 (D0/0x40184) Setting PLLPOWR (D0/0x40184) to 1 initiates PLL operation. When initially reset, PLLPOWR (D0/0x40184) is set to 0 (power-down mode), with the PLL turned off. Note: Immediately after the PLL is started by setting PLLPOWR (D0/0x40184) to 1, an output clock stabilization wait time is required (e.g., 200 s in the S1C33401). When the clock source for the system is switched over to the PLL, allow for this wait time after the PLL has turned on. II.3.6.2 Setting the Frequency Multiplication Rate The PLL frequency multiplication rate can be specified as shown in Table II.3.6.2.1 by using PLLN[3:0] (D[7:4]/ 0x40184). PLLN[3:0]: PLL Multiplication Rate Setup Bits in PLL Control Register 1 (D[7:4]/0x40184) Table II.3.6.2.1 PLL Frequency Multiplication Rates PLLN3 PLLN2 PLLN1 PLLN0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Multiplication rate x16 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 (Default: 0b0000 = x1) PLL output clock frequency = PLL input clock frequency (OSC3) x multiplication rate Notes: * The frequency multiplication rate that can be set depends on the upper-limit operating clock frequency of each S1C33 model and the OSC3 oscillation frequency. When setting the frequency multiplication rate, be sure not to exceed the upper-limit operating clock frequency. * The frequency multiplication rate can only be set when the PLL is turned off (PLLPOWR (D0/ 0x40184) = 0) and the clock source is other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0 -2). If the frequency multiplication rate is changed while the system is operating with the PLL clock, the system may operate erratically. II-3-8 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.6.3 Other PLL Settings I V-Divider To ensure that frequency fVCO obtained by <output frequency x W> falls within the range of 100 to 400 MHz, set the proper W value by using PLLV[1:0] (D[3:2]/0x40184). Lower value is better for low power consumption. PLLV[1:0]: PLL V-Divider Setup Bits in PLL Control Register 1 (D[3:2]/0x40184) Table II.3.6.3.1 Settings of the W Value PLLV1 PLLV0 1 1 0 0 1 0 1 0 W 8 4 2 Not allowed (Default: 0b01 = 2) II VCO Kv constant (VC value) CMU According to the range of fVCO frequencies obtained by <output frequency x W>, set the VCO Kv circuit constant (VC value) by using PLLVC[3:0] (D[7:4]/0x40185). PLLVC[3:0]: PLL VCO Kv Setup Bits in PLL Control Register 2 (D[7:4]/0x40185) Table II.3.6.3.2 Settings of the VC Value PLLVC3 PLLVC2 PLLVC1 PLLVC0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Other fVCO [MHz] 360 < fVCO 400 320 < fVCO 360 280 < fVCO 320 240 < fVCO 280 200 < fVCO 240 160 < fVCO 200 120 < fVCO 160 100 fVCO 120 Not allowed (Default: 0b0001) LPF resistance value (RS value) According to the input clock (OSC3) frequency, set the LPF resistance value (RS value) of the PLL by using PLLRS[3:0] (D[3:0]/0x40185). PLLRS[3:0]: PLL LPF Resistance Setup Bits in PLL Control Register 2 (D[3:0]/0x40185) Table II.3.6.3.3 Settings of the RS Value PLLRS3 PLLRS2 PLLRS1 PLLRS0 1 1 0 0 1 0 0 0 Other fREFCK [MHz] 5 fREFCK < 20 20 fREFCK 150 Not allowed (Default: 0b1000) LPF capacitance value (CS value) Bits to set the LPF capacitance value (CS value) is provided in the CMU control registers, PLLCS[1:0]/(D[7:6]/ 0x40186). However, do not alter the value of these bits, and leave them as initially set (0b00). PLLCS[1:0]: PLL LPF Capacitance Setup Bits in PLL Control Register 3 (D[7:6]/0x40186) Charge pump current value (CP value) Bits to set the charge pump current value (CP value) is provided in the CMU control registers, PLLCP[4:0]/ (D[4:0]/0x40186). However, do not alter the value of these bits, and leave them as initially set (0b10000). PLLCP[4:0]: PLL Charge Pump Current Setup Bits in PLL Control Register 3 (D[4:0]/0x40186) S1C33401 TECHNICAL MANUAL EPSON II-3-9 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) Table II.3.6.3.4 Example PLL Settings PLL input clock (OSC3) PLL output clock PLLN[3:0] PLLV[1:0] PLLVC[3:0] PLLRS[3:0] 5 MHz 65 MHz 60 MHz 40 MHz 60 MHz 40 MHz 60 MHz 40 MHz 66 MHz x13, 0b1100 x12, 0b1011 x8, 0b0111 x6, 0b0101 x4, 0b0011 x3, 0b0010 x2, 0b0001 x2, 0b0001 0b01 0b01 0b10 0b01 0b10 0b01 0b10 0b01 0b0010 0b0001 0b0010 0b0001 0b0010 0b0001 0b0010 0b0010 0b1010 0b1010 0b1010 0b1010 0b1010 0b1000 0b1000 0b1000 10 MHz 20 MHz 33 MHz Notes: * The PLL can only be set up when the PLL is turned off (PLLPOWR (D0/0x40184) = 0) and the clock source is other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0-2). If settings are changed while the system is operating with the PLL clock, the system may operate erratically. * The PLL control registers are write-protected. Before these and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. II-3-10 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.7 Control of the SSCG I The Spread Spectrum Clock Generator (SSCG) is a circuit used to reduce Electromagnetic Interference (EMI) noise by spreading the spectrum (or performing SS modulation) for the PLL output clock signal. The SS modulation is effective for all operating clocks for the core and peripheral circuits (except the RTC that uses the OSC1 clock) when the PLL output clock has been selected as the system clock source and only this case has the effect of reducing noise. Note: When the OSC3 or OSC1 clock is selected as the system clock source, SS modulation is not performed for the operating clock (system clock). About spectrum spread (SS modulation) The SSCG performs SS modulation by adjusting the width of the high section of the input clock. This adjustment is made by increasing or reducing the set value of the internal delay adjust circuit of the SSCG. The maximum width within which the set value is changed constitutes the maximum frequency change width. The relevant control register is used to set the upper-limit value of this width. In the SSCG, an interval timer adjusts the interval at which the set value changes. The relevant control register is also used to set this interval (frequency change cycle). + Input clock cycle Maximum frequency change width 0 - Frequency change cycle Figure II.3.7.1 SS Modulation The SSCG control bits are provided in the control registers of the CMU. Note, however, that the SSCG is not built into the core block. For details of the clock generator unit that includes the SSCG, see the description of the OSC3 oscillator circuit, PLL, and SSCG in Chapter IV, "C33 ADV Basic Peripheral Block." II.3.7.1 Turning the SSCG On/Off The SSCG can be turned on or off by using SSMCON (D0/0x40187). SSMCON: SS Macro On/Off Control Bit in the SS Macro Control Register 1 (D0/0x40187) Setting SSMCON (D0/0x40187) to 1 causes the SSCG to start operating. When initially reset, SSMCON (D0/ 0x40187) is initialized to 0, with the SSCG turned off (bypassed). Note: The SSCG is effective only when the PLL is selected as the system clock source. Furthermore, the SSCG control registers cannot be set when the PLL is inactive. S1C33401 TECHNICAL MANUAL EPSON II-3-11 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.7.2 Setting SS Modulation Parameters As described in "About spectrum spread (SS modulation)" above, it is necessary to set the upper-limit value of the maximum frequency change width and the frequency change cycle. The maximum frequency change width should be set to the appropriate value according to the system clock frequency as shown in Table II.3.7.2.1 using SSMCIDT[3:0] (D[3:0]/0x40188). The maximum frequency change width will be about 2% of the system clock by setting the appropriate value. SSMCIDT[3:0]: SS Macro Maximum Frequency Change Width Setting Bits in the SS Macro Control Register 2 (D[3:0]/0x40188) Table II.3.7.2.1 Maximum Frequency Change Width Settings System clock frequency f [MHz] SSMCIDT3 SSMCIDT2 SSMCIDT1 20.5 < f 21.7 21.7 < f 23.0 23.0 < f 24.5 24.5 < f 26.1 26.1 < f 28.0 28.0 < f 30.3 30.3 < f 32.8 32.8 < f 35.9 35.9 < f 39.6 39.6 < f 44.2 44.2 < f 49.9 49.9 < f 57.4 57.4 < f 66.0 - - - 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SSMCIDT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (Default: 0b0000) SSMCITM[3:0] (D[7:4]/0x40188) is used to set the frequency change cycle. However, always set it to 0b0001. SSMCITM[3:0]: SS Macro Interval Timer Setting Bits in the SS Macro Control Register 2 (D[7:4]/0x40188) Notes: * The SS macro control registers are write-protected. Write protection for these registers and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360- 0x48372 could cause the system to operate erratically, make sure that the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. * SSMCIDT[3:0] (D[3:0]/0x40188) must be set according to the system clock frequency as shown in Table II.3.7.2.1. Using the SSCG with an improper setting may cause a malfunction of the IC. II-3-12 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.8 Setting the Core System Clock (CCLK) I CCLK is the operating clock for the CPU, core block (HBCU, MMU, CCU, and DBG), and modules connecting to the high-speed bus (DMA, BBCU, EBCU, and internal RAM). The source clock OSC for the system (selected by OSCSEL[1:0] (D[3:2]/0x48360)) is divided by 1 to 8 by a clock frequency divider, generating four kinds of clocks. Select CCLK from those four clocks by using CCLKSEL[1:0] (D[9:8]/0x48360). CCLKSEL[1:0]: Core Clock (CCLK) Select Bits in the Core System Clock Control Register (D[9:8]/0x48360) Table II.3.8.1 Selecting CCLK CCLKSEL1 CCLKSEL0 1 1 0 0 1 0 1 0 CCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b00 = OSC*1/1) II CCLK can be selected at any time. However, since the clocks are switched over internally in the chip when all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are required before the clocks are actually changed after altering the register values. Notes: * The Core System Clock Control Register (0x48360) is write-protected. Before this and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. * When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after returning from SLEEP mode. S1C33401 TECHNICAL MANUAL EPSON II-3-13 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.9 Setting the Peripheral Circuit Clock (PCLK) PCLK is the operating clock for peripheral circuits. All modules except those clocked by CCLK basically use this PCLK clock. The ITC, prescaler, A/D converter, serial interface, 16/8-bit timers, card interface, and input/output ports all operate with the PCLK clock. Note that the RTC operates with only the 32-kHz OSC1 clock. As for CCLK, select PCLK from the four clocks derived from the OSC by using PCLKSEL[1:0] (D[1:0]/0x48366). PCLKSEL[1:0]: Peripheral Clock (PCLK) Select Bits in the Peripheral and External Clock Output Control Register (D[1:0]/0x48366) Table II.3.9.1 Selecting PCLK PCLKSEL1 PCLKSEL0 1 1 0 0 1 0 1 0 PCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b00 = OSC*1/1) PCLK can be selected at any time. However, since the clocks are switched over internally in the chip when all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are required before the clocks are actually changed after altering the register values. Notes: * The Peripheral and External Clock Output Control Register (0x48366) is write-protected. Before this and other CMU control registers at addresses 0x40180-0x40188 and 0x48360- 0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. * When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after returning from SLEEP mode. II-3-14 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.10 Setting the External Clock Output (CMU_CLK) I CMU_CLK is an external output clock. This clock is used by functions other than the C33 ADV Core on the chip or those external to the chip. CMU_CLK can be selected from four clocks derived from OSC as for CCLK and PCLK, or can be the clock input directly from the system clock source. Use CMUCLK[2:0] (D[10:8]/0x48366) to select a clock for CMU_CLK. CMUCLK[2:0]: External Clock Output (CMU_CLK) Select Bits in the Peripheral and External Clock Output Control Register (D[10:8]/0x48366) Table II.3.10.1 Selecting CMU_CLK CMUCLK2 CMUCLK1 CMUCLK0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CMU_CLK PLL OSC1 OSC3 CCLK (before clock tree) OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b000 = OSC*1/1) II CMU CMU_CLK can be selected at any time. However, switching over the clocks creates hazards. When CMU_CLK must be output to external devices, it is also necessary to select a port function. For details on how to control clock output and the port to be used, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." Note: The Peripheral and External Clock Output Control Register (0x48366) is write-protected. Before this and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. S1C33401 TECHNICAL MANUAL EPSON II-3-15 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.11 Controlling Clock Supply To reduce power consumption on the chip, a function is provided to turn off clock supply independently for each functional block. In addition to manual control in software, an automatic control function implemented in hardware is also available. II.3.11.1 Software Control of Clock Supply Table II.3.11.1.1 lists the register bits used for on/off control of CCLK clock supply to the core system modules. Table II.3.11.1.2 lists the register bits used for on/off control of PCLK clock supply to peripheral modules. Table II.3.11.1.1 CCLK Clock Supply Control Bits Module clock DBG NOSTOP clock DBG clock HBCU clock MMU clock CCU clock CPU clock BBCU, EBCU NOSTOP clock BBCU HB I/F clock BBCU SRAM clock BBCU DBG I/F clock EBCU HB I/F clock EBCU SDRAM clock A3RAM clock DMA clock SAPB12C clock SAPB1P clock Control bit DBGNCLK DBGCLK HBCUCLK MMUCLK CCUCLK CPUCLK BBEBNCLK BBHBIFCLK BBSRAMCLK BBDBGIFCLK EBCUHBCLK EBCUSDCLK A3RAMCLK DMACLK SAPB12CCLK SAPB1PCLK Control register (D15) (D8) (D3) (D2) (D1) (D0) (D11) (D10) (D9) (D8) (D5) (D4) (D3) (D2) (D1) (D0) Core System Clock On/Off Register (0x48362) CCLK System Peripheral Clock On/Off Register (0x48370) Table II.3.11.1.2 PCLK Clock Supply Control Bits Module clock Prescaler clock A/D converter clock Serial I/F clock 16-bit timer clock 8-bit timer clock ITC clock Interrupt generation clock Watchdog timer clock Card I/F clock Port clock Control bit PSCCLK ADCCLK SIOCLK T16CLK T8CLK ITCCLK INTCLK WDTCLK CARDCLK POT1CLK Control register (D7) (D6) (D4) (D3) (D2) (D0) (D4) (D3) (D2) (D0) Peripheral Clock Control Register 1 (0x40180) Peripheral Clock Control Register 2 (0x40181) When initially reset, these control bits are set to 1, with clocks supplied to each module. If any module is unused, set the corresponding control bit to 0, thus turning the clock for that module off. II-3-16 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.11.2 Automatic Control of Clock Supply I The CCLK clock supply to the core system modules listed in Table II.3.11.2.1 can be automatically controlled in hardware. Table II.3.11.2.1 CCLK Clock Supply Automatic Control Enable Bits Module clock DBG clock HBCU clock MMU clock CCU clock CPU clock BBCU HB I/F clock BBCU SRAM clock BBCU DBG I/F clock EBCU HB I/F clock EBCU SDRAM clock A3RAM clock DMA clock SAPB12C clock SAPB1P clock Control register Control bit DBGAUTO HBCUAUTO MMUAUTO CCUAUTO CPUAUTO BBHBIFAUTO BBSRAMAUTO BBDBGIFAUTO EBCUHBAUTO EBCUSDAUTO A3RAMAUTO DMAAUTO SAPB12CAUTO SAPB1PAUTO (D8) (D3) (D2) (D1) (D0) (D10) (D9) (D8) (D5) (D4) (D3) (D2) (D1) (D0) Core System Clock Automatic Control Register (0x48364) CCLK System Peripheral Clock Automatic Control Register (0x48372) II CMU The automatic control function for any core system module can be enabled by setting the corresponding control bit to 1, in which case clock supply for that module is turned on or off by hardware according to the module's usage condition. When initially reset, the automatic control function for only the DBG module is enabled (= 1), with the automatic control function for all other modules disabled (= 0). This automatic control function is enabled when the corresponding software control bit listed in Table II.3.11.1.1 is set to 1 (clock supply turned on). When the software control bit for any module is 0 (clock supply turned off), clock supply for that module is stopped regardless of how automatic control is set. Notes: * The Core System Clock Control Registers (0x48362, 0x48364, 0x48370, and 0x48372) are write-protected. Before these and other CMU control registers at addresses 0x40180-0x40188 and 0x48360-0x48372 can be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. * The clock supply to any module can only be stopped when the module is not operating or unused. If clock supply to any module is stopped when the module is not operating or unused, the chip may hang. * The clock automatic control function is effective only when the operating frequency is 50 MHz or less. Do not use the function when the chip is operating with a clock higher than 50 MHz. * SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block. SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop these clocks as the register read/write operation cannot be performed. S1C33401 TECHNICAL MANUAL EPSON II-3-17 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.12 Standby Modes The C33 ADV supports three standby modes: HALT, HALT2, and SLEEP. Power consumption on the chip can be greatly reduced by placing the CPU in one of these standby modes. Moreover, the CPU must be placed in SLEEP mode before clock sources for the system (OSC3, OSC1, or PLL) are switched over. II.3.12.1 HALT Mode When HALTMD (D1/0x48368) is set to 0 (default), the CPU suspends program execution upon executing the halt instruction and enters HALT mode. HALTMD: HALT Mode Select Bit in the Clock Option Register (D1/0x48368) In HALT mode, the CPU, CCU, MMU, HBCU, and A0RAM (area 0 no-wait RAM) all stop operating. The other internal peripheral circuits remain in the state (idle or operating) held when the halt instruction was executed. The CPU is released from HALT mode by initial reset, an NMI or other interrupt, or a forcible break from the debugger. II.3.12.2 HALT2 Mode When HALTMD (D1/0x48368) is set to 1, the CPU suspends program execution upon executing the halt instruction and enters HALT2 mode. In HALT2 mode, the BBCU, EBCU, and DMA also stop operating, in addition to the CPU, CCU, MMU, HBCU, and A0RAM. The other internal peripheral circuits remain in the state (idle or operating) held when the halt instruction was executed. The CPU is released from HALT2 mode by initial reset, an NMI or other interrupt, or a forcible break from the debugger. HALT and HALT2 modes are effective in reducing power consumption on the chip when running the CPU is unnecessary, such as when waiting for external input or responses from peripheral circuits. When the CPU is released from HALT/HALT2 mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the address for the instruction next to halt is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches to the instruction next to halt. The CPU is released from HALT/HALT2 mode when the interrupt controller (ITC) asserts the interrupt signal to be sent to the CPU. In other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the interrupt enable bits in the ITC is set to 1, the CPU can be released from HALT/HALT2 mode even if the PSR is set to disable interrupts. However, in this case the CPU does not execute the interrupt handling routine. The #NMI signal releases the CPU from HALT/HALT2 mode when it goes low level even if the NMI detection mode has been set to edge detection mode. II.3.12.3 SLEEP Mode The CPU suspends program execution upon executing the slp instruction and enters SLEEP mode. In SLEEP mode, the CPU stops operating and the CMU stops supplying a clock to each functional block. Therefore, all peripheral circuits (except the oscillator circuit and RTC) stop operating. Note that before the CMU actually stops clock output after initiating processing to enter SLEEP mode, up to 8 clock cycles of the source clock (OSC) then selected are required. The CPU is reawaken from SLEEP mode by initial reset, RTC interrupt, NMI, or other interrupt from an external device (when WAKEUPWT = 1). When the CPU is reawaken from SLEEP mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches to the instruction next to slp. Cause-of-interrupt flags in the interrupt controller (ITC) cannot be set in SLEEP mode as the clock is not supplied to the ITC in SLEEP mode. II-3-18 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) Therefore, when the clock is not supplied to the ITC, the interrupt signals from the interrupt sources that have been enabled to generate an interrupt are input to the CMU through the ITC and used to wake up the CPU from a standby mode. In this case, the cause-of-interrupt flag is set after the clock has started supplying to the ITC. The CPU can wake up from SLEEP mode by a cause of interrupt as described above even if the PSR is set to disable interrupts, note however, that the CPU does not execute the interrupt handling routine. The #NMI signal releases the CPU from SLEEP mode when it goes low level even if the NMI detection mode has been set to edge detection mode. Note: In SLEEP mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the ITC, so a delay will occur until the interrupt controller (ITC) sets the cause-of-interrupt flag. Therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the ITC, as the cause-of-interrupt flag in the ITC is not set. Furthermore, additional time is needed for the CPU to accept the interrupt request from the ITC, the CPU may execute a few instructions that follow the slp instruction before it starts the interrupt processing. The same problem may occur when the CPU wakes up from SLEEP mode by NMI. No interrupt will occur if the #NMI signal is deasserted before the clock is supplied, as the NMI flag is not set. Stopping OSC3 oscillation and waiting for oscillation stabilization at wakeup By default, neither the low-speed (OSC1) oscillator circuit nor the high-speed (OSC3) oscillator circuit stops operating when in SLEEP mode. OSC3 oscillation can be made to stop during SLEEP mode by setting OSC3OFF (D3/0x48368). OSC3OFF: OSC3 Disable During SLEEP in the Clock Option Register (D3/0x48368) Setting OSC3OFF (D3/0x48368) to 1 causes OSC3 oscillation to stop during SLEEP mode. In this case, the OSC3 oscillator circuit starts oscillating when the CPU is reawaken from SLEEP mode. However, since the CPU may operate erratically if it starts operating with the OSC3 or PLL clock before the oscillation stabilizes, an OSC oscillation start wait timer is provided to keep the CPU waiting a while before it starts operating. The wait time can be set by using OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368). OSCTM[7:0]: OSC Oscillation Stabilization-Wait Timer in the Clock Option Register (D[15:8]/0x48368) TMHSP: Stabilization-Wait Timer High-Speed Mode Select Bit in the Clock Option Register (D2/0x48368) Table II.3.12.3.1 Oscillation Stabilization Wait Time at Wakeup TMHSP OSCTM[7:0] Number of clocks Time 1 0x0 0 0 0x1 800 ns 16 0x2 1.6 s 32 : : : 0xFF 0.204 ms 4080 0 0x0 0 0 0x1 0.409 ms 8192 0x2 0.819 ms 16384 : : : 0xFF 104.5 ms 2M (The time shown here is an example when operating with a 20 MHz OSC3.) SLEEP control when clock sources are switched over When the CPU reawakes from SLEEP mode, the clock sources (OSC3, OSC1, or PLL) also are switched over depending on how OSCSEL[1:0] (D[3:2]/0x48360) is set. Before the clock sources can be switched over, the CPU must be placed once in SLEEP mode, then released. Therefore, a function is provided that automatically reawakes the CPU from SLEEP mode without using an interrupt, etc. To use this function, set WAKEUPWT (D0/0x48368) to 0. (By default, it is set to 1.) WAKEUPWT: Wakeup-Wait Function Enable Bit in the Clock Option Register (D0/0x48368) When the slp instruction is executed with WAKEUPWT (D0/0x48368) set to 0, the CPU automatically reawakes from SLEEP mode several 10 clock cycles after that time, then restarts with the source clock selected by OSCSEL[1:0] (D[3:2]/0x48360) after the oscillation stabilization time described above has elapsed. S1C33401 TECHNICAL MANUAL EPSON II-3-19 I II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) The OSC oscillation start wait timer configured using OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/ 0x48368) is effective even if WAKEUPWT (D0/0x48368) is 0. To restart the CPU in the shortest time possible, set OSCTM[7:0] (D[15:8]/0x48368) to 0x0 and TMHSP (D2/0x48368) to 1. When WAKEUPWT (D0/0x48368) is set to 1, the CPU is reawaken from SLEEP mode by initial reset, RTC interrupt, NMI, or other interrupt from an external device. For details about clock switchover and SLEEP control procedures, see Section II.3.13, "Clock Setup Procedure." II.3.12.4 Precautions Interrupt The standby mode is released by an interrupt from the ITC, NMI, or reset. Note that the ITC must be configured so that the interrupt to be used for releasing the standby mode can be generated to the CPU. When the clock has not been supplied to the ITC, the interrupt signal from the interrupt source that has been enabled to interrupt is passed through the ITC and is input to the CMU. This signal is used to release the standby mode and to start supplying clocks. The ITC can operate with the supplied clock in HALT or HALT2 mode, so the cause-ofinterrupt flag is set immediately after the interrupt source asserts the interrupt signal and the ITC requests an interrupt to the CPU without a delay. In SLEEP mode, the ITC will be able to set the cause-of-interrupt flag and to request an interrupt to the CPU after the CMU starts supplying the clock to the ITC. Therefore, the delay in the interrupt request to the CPU after waking up from SLEEP mode may cause the CPU to execute a few instructions that follows the slp instruction before the CPU executes the interrupt processing. Moreover, if the interrupt source deasserts the interrupt signal before the CMU starts supplying the clock to the ITC, an interrupt does not occur since the cause-of-interrupt flag is not set. The IE and IL[3:0] bits in the CPU's PSR register do not affect the releasing of standby mode by an interrupt. For example, by setting the ITC to enable the interrupt used for releasing and setting the IE bit to disable interrupts, the CPU can wake up from SLEEP mode without an interrupt processing. Oscillator circuits When OSC3 oscillation is set to stop during SLEEP mode, the OSC3 oscillator circuit starts oscillating upon exiting SLEEP mode. This is because the high-speed (OSC3) oscillator circuit requires a finite time before its oscillation stabilizes after starting operation. To restart the CPU using the OSC3 or PLL as the source clock, OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368) must be properly set so that the CPU starts operating after this oscillation stabilization time elapses. When using the PLL, note that the PLL requires a lock-in time (e.g., 200 s in the S1C33401) after OSC3 oscillation has stabilized. The oscillation start time of the high-speed (OSC3) oscillator circuit varies with the device used, board patterns, and operating environment. Therefore, the set time above should have a sufficient allowance. Bus and DMA When in standby mode, the bus control unit stops operating after the bus cycle in progress is completed. All chip enable signals become inactive. In HALT mode, the BBCU is active, so the bus clock signals can be output and the DMA can also be run. In HALT2 and SLEEP modes, BBCU is inactive, so no bus clock signals are output, nor is the DMA active. Be sure to disable the HSDMA and IDMA before setting the chip in SLEEP mode (executing the slp instruction). HALT and HALT2 mode can be set even if the HSDMA and/or IDMA are enabled. Switching over the clock sources Use the automatic SLEEP cancellation function when executing the slp instruction for switching over the clock sources. When the SLEEP mode is cancelled, the OSC oscillation start wait timer that has been configured using OSCTM[7:0] (D[15:8]/0x48368) starts operating with the clock source after switch over. Use the switched clock frequency for calculating the oscillation wait time. Other The status of the core CPU registers and input/output ports are retained even during standby mode. The contents of the control and data registers in internal peripheral circuits are also basically retained, but some contents are altered upon entering SLEEP mode. See the description of each peripheral circuit. When placing the CPU in SLEEP mode (with WAKEUPWT (D0/0x48368) = 1), be sure to set CCLK and PCLK to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after returning from SLEEP mode. II-3-20 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13 Clock Setup Procedure I This section describes the procedure for setting up clocks or altering clock settings. When initially reset, the clocks are set to the following states: OSC3 oscillator circuit: On PLL: Off OSC1 oscillator circuit: On System clock source: OSC3 CCLK: OSC3 divided by 1 PCLK: OSC3 divided by 1 CMU_CLK: OSC3 divided by 1 II.3.13.1 Changing the Clock Source from OSC3 to PLL II 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. CMU 2. PLLPOWR (D0/0x40184) = 0 Turn off the PLL. 3. Setting PLL Control Register 1 (0x40184) * PLLN[3:0] (D[7:4]) = 0b0000-0b1111 Set the frequency multiplication rate of the PLL (x1 to x16). * PLLV[1:0] (D[3:2]) = 0b01-0b11 Set the W value of the PLL (2, 4 or 8). 4. Setting PLL Control Register 2 (0x40185) * PLLVC[3:0] (D[7:4]) = 0b0001-0b1000 Set the VCO Kv circuit constant. * PLLRS[3:0] (D[3:0]) = 0b1000 or 0b1010 Set the LPF resistance value. 5. PLLPOWR (D0/0x40184) = 1 Turn on the PLL. 6. OSCSEL[1:0] (D[3:2]/0x48360) = 0b11 Select the PLL for the clock source. 7. Setting the Clock Option Register (0x48368) Set appropriate values so that the wait timer exceeds the stabilization time * OSCTM[7:0] (D[15:8]) = * OSC3OFF (D3) = 0 of the PLL output clock (e.g. 200 s in the S1C33401). Be aware that the * TMHSP (D2) = wait timer operates with the PLL clock. For details about the PLL output * HALTMD (D1) = 0 or 1 stabilization time, see "Electrical Characteristics." * WAKEUPWT (D0) = 0 This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed without waiting for an interrupt. 8. Stop any peripheral circuits that are operating, except the RTC. 9. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using the PLL as the clock source. 10. Newly setting the clock control registers again Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required. 11. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. S1C33401 TECHNICAL MANUAL EPSON II-3-21 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.2 Changing the Clock Source from PLL to OSC3, then Turning Off the PLL 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. OSCSEL[1:0] (D[3:2]/0x48360) = 0b00 Select OSC3 for the clock source. 3. Setting the Clock Option Register (0x48368) * OSCTM[7:0] (D[15:8]) = 0x0 * OSC3OFF (D3) = 0 * TMHSP (D2) = 1 * HALTMD (D1) = 0 or 1 * WAKEUPWT (D0) = 0 This setting causes the CPU to automatically exit SLEEP mode and restart in the shortest time possible (several 10 clock cycles) without waiting an interrupt. 4. Stop any peripheral circuits that are operating, except the RTC. 5. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakes from SLEEP mode several 10 clock cycles after the slp instruction is executed, and restarts using OSC3 as the clock source. 6. PLLPOWR (D0/0x40184) = 0 Turn off the PLL. 7. Newly setting the clock control registers again Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required. 8. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. II-3-22 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.3 Changing the Clock Source from OSC3 or PLL to OSC1, then Turning Off OSC3 and PLL I 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. SOSC1 (D0/0x48360) = 1 Turn on the OSC1 oscillator circuit if turned off. 3. OSCSEL[1:0] (D[3:2]/0x48360) = 0b01 Select OSC1 for the clock source. 4. Setting the Clock Option Register (0x48368) Set appropriate values so that the wait timer exceeds the stabilization time * OSCTM[7:0] (D[15:8]) = * OSC3OFF (D3) = 0 of OSC1 oscillation (e.g., 3 seconds in the S1C33401). Be aware that the * TMHSP (D2) = wait timer operates with the OSC1 clock. For details about the OSC1 * HALTMD (D1) = 0 or 1 oscillation start time, see "Electrical Characteristics." * WAKEUPWT (D0) = 0 This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed without waiting for an interrupt. 5. Stop any peripheral circuits that are operating. 6. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using OSC1 as the clock source. 7. PLLPOWR (D0/0x40184) = 0 Turn off the PLL. 8. SOSC3 (D1/0x48360) = 0 Turn off the OSC3 oscillator circuit. 9. Newly setting the clock control registers again Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required. 10. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. S1C33401 TECHNICAL MANUAL EPSON II-3-23 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.4 Changing the Clock Source from OSC1 to OSC3 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. SOSC3 (D1/0x48360) = 1 Turn on the OSC3 oscillator circuit if turned off. 3. OSCSEL[1:0] (D[3:2]/0x48360) = 0b00 Select OSC3 for the clock source. 4. Setting the Clock Option Register (0x48368) Set appropriate values so that the wait timer exceeds the stabilization time * OSCTM[7:0] (D[15:8]) = * OSC3OFF (D3) = 0 of OSC3 oscillation (e.g., 25 ms in the S1C33401). Be aware that the * TMHSP (D2) = wait timer operates with the OSC3 clock. For details about the OSC3 * HALTMD (D1) = 0 or 1 oscillation start time, see "Electrical Characteristics." * WAKEUPWT (D0) = 0 This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed without waiting for an interrupt. 5. Stop any peripheral circuits that are operating, except the RTC. 6. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using OSC3 as the clock source. 7. Newly setting the clock control registers again Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers newly again, as required. 8. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. II-3-24 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.5 Changing the Clock Source from OSC1 to PLL I 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. SOSC3 (D1/0x48360) = 1 Turn on the OSC3 oscillator circuit if turned off. 3. Wait until OSC3 oscillation stabilizes (only when OSC3 has been turned on; e.g., 25 ms in the S1C33401). For details about the OSC3 oscillation start time, see "Electrical Characteristics." 4. PLLPOWR (D0/0x40184) = 0 Turn off the PLL. 5. Setting PLL Control Register 1 (0x40184) * PLLN[3:0] (D[7:4]) = 0b0000-0b1111 Set the frequency multiplication rate of the PLL (x1 to x16). * PLLV[1:0] (D[3:2]) = 0b01-0b11 Set the W value of the PLL (2, 4 or 8). II CMU 6. Setting PLL Control Register 2 (0x40185) * PLLVC[3:0] (D[7:4]) = 0b0001-0b1000 Set the VCO Kv circuit constant. * PLLRS[3:0] (D[3:0]) = 0b1000 or 0b1010 Set the LPF resistance value. 7. PLLPOWR (D0/0x40184) = 1 Turn on the PLL. 8. OSCSEL[1:0] (D[3:2]/0x48360) = 0b11 Select PLL for the clock source. 9. Setting the Clock Option Register (0x48368) Set appropriate values so that the wait timer exceeds the stabilization time * OSCTM[7:0] (D[15:8]) = * OSC3OFF (D3) = 0 of the PLL output clock (e.g. 200 s in the S1C33401). Be aware that the * TMHSP (D2) = wait timer operates with the PLL clock. For details about the PLL output * HALTMD (D1) = 0 or 1 stabilization time, see "Electrical Characteristics." * WAKEUPWT (D0) = 0 This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed without waiting for an interrupt. 10. Stop any peripheral circuits that are operating, except the RTC. 11. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using the PLL as the clock source. 12. Newly setting the clock control registers again Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required. 13. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. S1C33401 TECHNICAL MANUAL EPSON II-3-25 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.6 Turning Off OSC3 during SLEEP To turn off OSC3 oscillation during SLEEP mode when operating with OSC3 or PLL as the clock source, follow the control procedure described below. 1. If the current clock source is PLL, it must be changed to OSC3 and the PLL turned off (see note below). See Section II.3.13.2, "Changing the Clock Source from PLL to OSC3, then Turning Off the PLL," for the procedure to change the clock source. Stop PLL even if the current clock source is OSC3. 2. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 3. Setting the Clock Option Register (0x48368) * OSCTM[7:0] (D[15:8]) and TMHSP (D2) Set the wait time until the oscillation stabilizes after exiting SLEEP mode. Example: TMHSP = 1, OSCTM[7:0] = 0x40 (wait time = about 26 ms when OSC3 = 20 MHz) * OSC3OFF (D3/0x48368) = 1 Turn off OSC3 oscillation when in SLEEP mode. * WAKEUPWT (D0/0x48368) = 1 Set the CPU to awake from SLEEP mode by using an RTC interrupt, NMI, or other interrupt from an external device. 4. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. 5. Stop any peripheral circuits that are operating, except the RTC. 6. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU is reawaken from SLEEP mode by an RTC interrupt, forced break from the debugger, NMI, or other interrupt from an external device. After the set oscillation start wait time elapses, the CPU restarts using the same clock source (OSC3) that was selected before entering SLEEP mode. 7. If the application needs PLL as the clock source, change the clock source to PLL after the CPU wakes up with the OSC3 clock (see note below). See Section II.3.13.1, "Changing the Clock Source from OSC3 to PLL," for the procedure to change the clock source. Note: To turn the OSC3 oscillation off in SLEEP mode, the conditions shown below must be satisfied before entering SLEEP mode and at wakeup from SLEEP mode. * The CPU operates with OSC3 as the clock source. * The PLL has been turned off. If both OSC3 and PLL turn on at wakeup from SLEEP mode and the CPU starts operating with PLL as the clock source, the PLL operation may become unstable. Therefore, to set PLL as the clock source, steps 1 and 7 above are required. II-3-26 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.7 SLEEP Keeping Oscillation On (without Clock Change) I To enter SLEEP mode without a clock source change and turning off the oscillation, follow the control procedure described below. This is the control to reduce power consumption as much as possible by stopping the core and peripheral functions, with no restart time penalty. 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. Setting the Clock Option Register (0x48368) * OSCTM[7:0] (D[15:8]) = 0x0 * OSC3OFF (D3) = 0 * TMHSP (D2) = 1 * HALTMD (D1) = 0 or 1 * WAKEUPWT (D0) = 1 This setting causes the CPU to exit SLEEP mode using an RTC interrupt, NMI, or other interrupt from an external device, and to restart in the shortest time possible (several 10 clock cycles). 3. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. 4. Stop any peripheral circuits that are operating, except the RTC. 5. Execute the slp instruction. The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU is brought out of SLEEP mode by an RTC interrupt, forced break from the debugger, NMI, or other interrupt from an external device, and it restarts using the clock source selected with OSCSEL[1:0] (D[3:2]/ 0x48360). S1C33401 TECHNICAL MANUAL EPSON II-3-27 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.13.8 HALT/HALT2 To enter HALT/HALT2 mode, follow the control procedure described below. This is the control to reduce power consumption by stopping the core. 1. Clock Control Protect Register (0x4836E) = 0x96 Disable write protection of the clock control registers. 2. Setting the Clock Option Register (0x48368) * HALTMD (D1) = 0 Specifies HALT mode that stops the CPU, CCU, MMU, HBCU, and A0RAM. = 1 Specifies HALT2 mode that stops DMA, BBCU, and EBCU as well as the modules above. OSCTM[7:0] (D[15:8]), OSC3OFF (D3), TMHSP (D2), and WAKEUPWT (D0) are irrelevant to HALT/ HALT2 mode. 3. Clock Control Protect Register (0x4836E) = other than 0x96 Reenable write protection of the clock control registers. 4. Execute the halt instruction. The chip enters HALT or HALT2 mode according to the setting of HALTMD (D1/0x48368). The CPU exits from HALT/HALT2 mode by an interrupt, forced break from the debugger or NMI. II-3-28 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.14 Power-Down Control I The amount of current consumed on the chip varies significantly with the CPU operation mode, operating clock frequency, and peripheral circuit to be operated. The following summarizes points on how to reduce power consumption on the chip. 1. Reducing the operating clock frequency as much as possible The CMU allows one of the three available clock sources to be selected, and the clock frequency to be set independently for the core and peripheral circuit. (See II.3.4 to II.3.10.) Reduce the operating clock frequency to as low a frequency as permitted for the intended processing content of the system. * When the OSC1 clock can suffice, turn off the PLL and OSC3, and use only OSC1 to operate the system. * When the OSC3 clock can suffice (although high-speed processing is needed), turn off the PLL and use OSC3 to operate the system. II * When the PLL is needed, use it with as small a frequency multiplication rate as possible. * The divide ratios with which to generate CCLK and PCLK from the source clock can be selected separately. Select the lowest divide ratios permitted for the intended processing content. For example, PCLK may be fixed to 20 MHz for use in serial communication, whereas CCLK may be dynamically changed to 66 MHz when used for multimedia processing or 10 MHz when used for key input processing. However, if the CPU is to be placed in SLEEP mode, CCLK and PCLK should be set to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after returning from SLEEP mode. * Some peripheral circuits may use the prescaler, while others have an exclusive clock control function incorporated in the module. For details, refer to the description of each peripheral circuit. 2. Turning off unnecessary clock supply The CMU allows CCLK and PCLK supplies to be turned on or off independently for each functional block. (See II.3.9.) * Turn off clock supplies for unused functional blocks. * Some peripheral circuits may use the prescaler, while others have an exclusive clock control function incorporated in the module. For details, refer to the description of each peripheral circuit. * The function used to automatically control clock supply to each block should be turned on while in use as much as possible. However, this function is subject to limitations on operating clock frequency. It can only be turned on when CCLK is 50 MHz or less. 3. Placing the CPU in standby mode Place the CPU in standby mode by executing the halt or slp instruction as much as possible when, for example, waiting for key input. (See II.3.12.) * Optimum power saving effects may be obtained by placing the CPU in SLEEP mode whenever OSC3 oscillation is turned off. In such case, however, basically only the RTC can be used without other peripheral circuits. * To wake CPU quickly from SLEEP mode with no oscillation stabilization time inserted, enter SLEEP mode after setting OSC3 so that it does not stop in SLEEP mode. The core and peripheral circuits other than RTC and OSC3 cell unit enter power-down state. * When peripheral circuits must be operated, use the halt instruction to place the CPU in HALT mode (HALTMD (D1/0x48368) = 0) or HALT2 mode (HALTMD (D1/0x48368) = 1). In HALT mode, the CPU, CCU, MMU, HBCU, and A0RAM all stop operating. In HALT2 mode, the BBCU, EBCU, and DMA also stop operating, in addition to the above. When the BBCU, EBCU, and DMA can be stopped, use HALT2 mode to obtain better power saving effects. 4. Turning off unnecessary external port pull-ups When input ports are driven to low level, their pull-up resistors consume some amount of current. Use the pullup control register provided for each S1C33 model to turn off unnecessary pull-ups. However, care should be taken to prevent the input ports from becoming left open (floating state). S1C33401 TECHNICAL MANUAL EPSON II-3-29 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.15 Details of Control Registers Table II.3.15.1 List of CMU Registers Address 0x00040180 0x00040181 0x00040184 0x00040185 0x00040186 0x00040187 0x00040188 0x00048360 0x00048362 0x00048364 0x00048366 0x00048368 0x0004836A 0x0004836C 0x0004836E 0x00048370 0x00048372 Register name Peripheral Clock Control Register 1 (pCMU1_CLKCNTL_0) Peripheral Clock Control Register 2 (pCMU1_CLKCNTL_1) PLL Control Register 1 (pCMU1_PLL_CNTL0) PLL Control Register 2 (pCMU1_PLL_CNTL1) PLL Control Register 3 (pCMU1_PLL_CNTL2) SS Macro Control Register 1 (pCMU1_SS_CNTL0) SS Macro Control Register 2 (pCMU1_SS_CNTL1) Core System Clock Control Register (pCMU2_CNTL_CORE) Core System Clock On/Off Register (pCMU2_SET) Core System Clock Automatic Control Register (pCMU2_AUTO) Peripheral and External Bus Clock Control Register (pCMU2_CNTL_PERI) Clock Option Register (pCMU2_OPT) NMI Flag Register (pCMU2_NMI_FLAG) NMI Mode Register (pCMU2_NMI_MODE) Clock Control Protect Register (pCMU2_PROTECT) CCLK System Peripheral Clock On/Off Register (pCMU2_CCLK_PERI) CCLK System Peripheral Clock Automatic Control Register (pCMU2_AUTO_CCLK_PERI) Size Function 8 Control clock supply for peripheral circuit modules 1 8 Control clock supply for peripheral circuit modules 2 8 8 8 8 8 16 Set PLL constant 1, on/off control Set PLL constant 2 Set PLL constant 3 Control SSCG on and off Set SSCG parameters Set core system clock 16 16 Control clock supply for core block modules Automatically control clock supply for core block modules 16 Set peripheral circuit and external bus clocks 16 16 16 16 16 Configure standby mode NMI status Set NMI detection mode Enable/disable write protection of clock control registers Control clock supply for CCLK system peripheral modules Automatically control clock supply for CCLK system peripheral modules 16 The following describes each CMU control register. Addresses 0x40180 through 0x40188 are mapped to the 8-bit device area, and can be accessed in units of bytes. Addresses 0x48360 through 0x48372 are mapped to the 16-bit device area, and can be accessed in units of halfwords or bytes. Note: The CMU registers (0x40180-0x40188, 0x48360-0x4836C, 0x48370, and 0x48372) are writeprotected. Before these register can be rewritten, write protection must be removed by writing data 0x96 to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses 0x40180-0x40188 and 0x48360-0x48372 could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU control registers must be rewritten. II-3-30 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40180: Peripheral Clock Control Register 1 (pCMU1_CLKCNTL_0) Register name Address Bit Name 0040180 (B) D7 D6 D5 D4 D3 D2 D1 D0 PSCCLK ADCCLK - SIOCLK T16CLK T8CLK - ITCCLK Peripheral clock control register 1 (pCMU1 _CLKCNTL_0) Protected Function Prescaler clock control A/D converter clock control reserved Serial I/F clock control 16-bit timer clock control 8-bit timer clock control reserved ITC clock control Setting 1 1 1 1 1 1 1 1 On On 1 On On On 1 On 0 0 0 0 0 0 0 0 Init. R/W Off Off 0 Off Off Off 0 Off 1 1 1 1 1 1 1 1 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Note: Although the clock control functions implemented by this register are incorporated, not all peripheral circuits may be incorporated in some S1C33 models. D7 PSCCLK: Prescaler Clock Control Bit Controls clock (PCLK) supply to the prescaler. 1 (R/W): On (default) 0 (R/W): Off D6 ADCCLK: A/D Converter Clock Control Bit Controls clock (PCLK) supply to the A/D converter. 1 (R/W): On (default) 0 (R/W): Off D5 Reserved D4 SIOCLK: Serial Interface Clock Control Bit Controls clock (PCLK) supply to the serial interface. 1 (R/W): On (default) 0 (R/W): Off D3 T16CLK: 16-bit Timer Clock Control Bit Controls clock (PCLK) supply to the 16-bit timer. 1 (R/W): On (default) 0 (R/W): Off D2 T8CLK: 8-bit Timer Clock Control Bit Controls clock (PCLK) supply to the 8-bit timer. 1 (R/W): On (default) 0 (R/W): Off D1 Reserved D0 ITCCLK: ITC Clock Control Bit Controls clock (PCLK) supply to the ITC. 1 (R/W): On (default) 0 (R/W): Off S1C33401 TECHNICAL MANUAL EPSON II CMU II-3-31 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40181: Peripheral Clock Control Register 2 (pCMU1_CLKCNTL_1) Bit Name Function Setting D7-5 D4 D3 D2 D1 D0 - INTCLK WDTCLK CARDCLK - POT1CLK reserved Interrupt generation clock control Watchdog timer clock control Card I/F clock control reserved Port clock control - Register name Address Peripheral clock control register 2 (pCMU1 _CLKCNTL_1) Protected 0040181 (B) 1 1 1 1 1 On On On 1 On 0 0 0 0 0 Init. R/W - 1 1 1 1 1 Off Off Off 0 Off Remarks - 0 when being read. R/W R/W R/W R/W R/W Note: Although the clock control functions implemented by this register are incorporated, not all peripheral circuits may be incorporated in some S1C33 models. D[7:5] Reserved D4 INTCLK: Interrupt Generation Clock Control Bit Controls clock (PCLK) supply to the interrupt generation function module. 1 (R/W): On (default) 0 (R/W): Off D3 WDTCLK: Watchdog Timer Clock Control Bit Controls clock (PCLK) supply to the watchdog timer. 1 (R/W): On (default) 0 (R/W): Off D2 CARDCLK: Card Interface Clock Control Bit Controls clock (PCLK) supply to the card interface. 1 (R/W): On (default) 0 (R/W): Off D1 Reserved D0 POT1CLK: Port Clock Control Bit Controls clock (PCLK) supply to the input/output port. 1 (R/W): On (default) 0 (R/W): Off II-3-32 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40184: PLL Control Register 1 (pCMU1_PLL_CNTL0) Name Register name Address Bit 0040184 (B) D7 D6 D5 D4 PLLN3 PLLN2 PLLN1 PLLN0 PLL multiplication rate setup D3 D2 PLLV1 PLLV0 PLL V-divider setup D1 D0 - reserved PLLPOWR PLL on/off control PLL control register 1 (pCMU1_PLL _CNTL0) Function Protected Setting PLLN[3:0] 1111 1110 : 0001 0000 PLLV[1:0] 11 10 01 00 1 On Multiplication rate x16 x15 : x2 x1 W 8 4 2 Not allowed - 0 Off I Init. R/W Remarks 0 0 0 0 R/W 0 1 R/W - 0 - 0 when being read. R/W Note: When D[7:2] in this register must be altered, turn off the PLL (PLLPOWR (D0) = 0) before changing the bits. D[7:4] PLLN[3:0]: PLL Multiplication Rate Setup Bits Sets the frequency multiplication rate of the PLL. (Default: 0b0000 = x1) PLL frequency multiplication rate = PLLN[3:0] + 1 (x1 to x16) D[3:2] PLLV[1:0]: PLL V-Divider Setup Bits Sets the W value so that the fVCO frequency obtained by <output clock frequency x W> falls within the range of 100 to 400 MHz. CMU Table II.3.15.2 Settings of the W Value PLLV1 PLLV0 1 1 0 0 1 0 1 0 D1 Reserved D0 PLLPOWR: PLL On/Off Control Bit Turns the PLL on or off. 1 (R/W): On 0 (R/W): Off (default) W 8 4 2 Not allowed (Default: 0b01 = 2) Up to 200 s is required before the output clock of the PLL stabilizes after PLLPOWR is set to 1. Provide this wait time in a program before changing the clock source for the system to the PLL. When not using the PLL, turn off the PLL (power-down mode) to reduce the amount of current consumed on the chip. S1C33401 TECHNICAL MANUAL EPSON II II-3-33 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40185: PLL Control Register 2 (pCMU1_PLL_CNTL1) Register name Address Bit Name 0040185 (B) D7 D6 D5 D4 PLLVC3 PLLVC2 PLLVC1 PLLVC0 PLL VCO Kv setup D3 D2 D1 D0 PLLRS3 PLLRS2 PLLRS1 PLLRS0 PLL LPF resistance setup PLL control register 2 (pCMU1_PLL _CNTL1) Function Setting Protected PLLVC[3:0] 1000 0111 0110 0101 0100 0011 0010 0001 Other PLLRS[3:0] 1010 1000 Other Init. R/W fVCO [MHz] 360 < fVCO 400 320 < fVCO 360 280 < fVCO 320 240 < fVCO 280 200 < fVCO 240 160 < fVCO 200 120 < fVCO 160 100 fVCO 120 Not allowed fREFCK [MHz] 5 fREFCK < 20 20 fREFCK 150 Not allowed 0 0 0 1 R/W 1 0 0 0 R/W Remarks Note: When this register must be altered, turn off the PLL (PLLPOWR (D0/0x40184) = 0) before changing the bits. D[7:4] PLLVC[3:0]: PLL VCO Kv Setup Bits Sets the VCO Kv circuit constant (VC value) according to the range of fVCO frequencies obtained by <output clock frequency x W>. Table II.3.15.3 Settings of the VC Value PLLVC3 PLLVC2 PLLVC1 PLLVC0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 Other D[3:0] fVCO [MHz] 360 < fVCO 400 320 < fVCO 360 280 < fVCO 320 240 < fVCO 280 200 < fVCO 240 160 < fVCO 200 120 < fVCO 160 100 fVCO 120 Not allowed (Default: 0b0001) PLLRS[3:0]: PLL LPF Resistance Setup Bits Sets the LPF resistance value of the PLL (RS value) according to the input clock (OSC3) frequency. Table II.3.15.4 Settings of the RS Value PLLRS3 PLLRS2 PLLRS1 PLLRS0 1 1 0 0 1 0 0 0 Other fREFCK [MHz] 5 fREFCK < 20 20 fREFCK 150 Not allowed (Default: 0b1000) Table II.3.15.5 Example PLL Settings PLL input clock (OSC3) PLL output clock PLLN[3:0] PLLV[1:0] PLLVC[3:0] PLLRS[3:0] 5 MHz 65 MHz 60 MHz 40 MHz 60 MHz 40 MHz 60 MHz 40 MHz 66 MHz x13, 0b1100 x12, 0b1011 x8, 0b0111 x6, 0b0101 x4, 0b0011 x3, 0b0010 x2, 0b0001 x2, 0b0001 0b01 0b01 0b10 0b01 0b10 0b01 0b10 0b01 0b0010 0b0001 0b0010 0b0001 0b0010 0b0001 0b0010 0b0010 0b1010 0b1010 0b1010 0b1010 0b1010 0b1000 0b1000 0b1000 10 MHz 20 MHz 33 MHz II-3-34 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40186: PLL Control Register 3 (pCMU1_PLL_CNTL2) Register name Address Bit Name 0040186 (B) D7 D6 D5 D4 D3 D2 D1 D0 PLLCS1 PLLCS0 PLLBYP PLLCP4 PLLCP3 PLLCP2 PLLCP1 PLLCP0 PLL control register 3 (pCMU1_PLL _CNTL2) Protected Function PLL LPF capacitance setup PLL bypass mode setup PLL Charge Pump current setup Setting Fixed at "00" (default) Fixed at "0" (default) Fixed at "10000" (default) I Init. R/W 0 0 0 1 0 0 0 0 Remarks R/W R/W R/W Note: This register should be left as at initial reset, without altering its settings while in use. D[7:6] PLLCS[1:0]: PLL LPF Capacitance Setup Bits Sets the LPF capacitance value (CS value). (Default: 0b00) D5 PLLBYP: PLL Bypass Mode Setup Bit Sets PLL bypass mode. (Default: 0) D[4:0] PLLCP[4:0]: PLL Charge Pump Current Setup Bits Sets the charge pump current value (CP value). (Default: 0b10000) S1C33401 TECHNICAL MANUAL EPSON II CMU II-3-35 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40187: SS Macro Control Register 1 (pCMU1_SS_CNTL0) Register name Address 0040187 SS macro (B) control register 1 (pCMU1_SS_CNTL0) Protected Name Bit D7-1 - D0 SSMCON Function Setting reserved - SS macro On/Off 1 On D[7:1] Reserved D0 SSMCON: SS Macro On/Off Control Bit This bit turns the SSCG on or off. 1 (R/W): On 0 (R/W): Off (default) 0 Off Init. R/W - - 0 R/W Remarks 0 when being read. Setting this bit to 1 causes the SSCG to start operating. Setting this bit to 0 causes the SSCG to stop, so that the clock generator bypasses the SSCG. II-3-36 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x40188: SS Macro Control Register 2 (pCMU1_SS_CNTL1) Register name Address Bit Name 0040188 SS macro (B) control register 2 (pCMU1_SS_CNTL1) D7 D6 D5 D4 D3 D2 D1 D0 SSMCITM3 SSMCITM2 SSMCITM1 SSMCITM0 SSMCIDT3 SSMCIDT2 SSMCIDT1 SSMCIDT0 Protected D[7:4] D[3:0] Function Setting SS macro interval timer (ITM) setting 0 to 0xF SS macro maximum frequency change width setting 0 to 0xF I Init. R/W 1 1 1 1 0 0 0 0 Remarks R/W R/W SSMCITM[3:0]: SS Macro Interval Timer Setting Bits These bits set the frequency change cycle in SS modulation of the SSCG. (See Section II.3.7, "Control of the SSCG.") Always set these bits to 0b0001. (Default: 0b1111) SSMCIDT[3:0]: SS Macro Maximum Frequency Change Width Setting Bits These bits set the maximum frequency change width in SS modulation of the SSCG. (See Section II.3.7, "Control of the SSCG.") Table II.3.15.6 Maximum Frequency Change Width Settings System clock frequency f [MHz] SSMCIDT3 SSMCIDT2 SSMCIDT1 20.5 < f 21.7 21.7 < f 23.0 23.0 < f 24.5 24.5 < f 26.1 26.1 < f 28.0 28.0 < f 30.3 30.3 < f 32.8 32.8 < f 35.9 35.9 < f 39.6 39.6 < f 44.2 44.2 < f 49.9 49.9 < f 57.4 57.4 < f 66.0 - - - 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SSMCIDT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (Default: 0b0000) Note: SSMCIDT[3:0] must be set according to the system clock frequency as shown in Table II.3.15.6. Using the SSCG with an improper setting may cause a malfunction of the IC. S1C33401 TECHNICAL MANUAL EPSON II-3-37 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48360: Core System Clock Control Register (pCMU2_CNTL_CORE) Register name Address Core system clock control register (pCMU2_CNTL _CORE) Bit Name Function reserved 0048360 D15-11 - D10 - reserved (HW) D9 CCLKSEL1 Core clock (CCLK) selection D8 CCLKSEL0 Protected D7-4 - D3 OSCSEL1 D2 OSCSEL0 D1 D0 SOSC3 SOSC1 Setting Init. R/W - - CCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 CCLKSEL[1:0] 11 10 01 00 reserved OSC clock selection - OSCSEL[1:0] 11 10 01 00 High-speed oscillation (OSC3) On/Off 1 On Low-speed oscillation (OSC1) On/Off 1 On Clock source PLL OSC3 OSC1 OSC3 0 Off 0 Off Remarks - 0 0 0 - 0 when being read. - Writing 1 not allowed. R/W - 0 0 - 0 when being read. R/W 1 1 R/W R/W D[15:11] Reserved D10 Reserved (writing 1 to this bit prohibited) D[9:8] CCLKSEL[1:0]: Core Clock (CCLK) Select Bits CCLK is the operating clock for the CPU, core blocks (HBCU, MMU, CCU, and DBG), and modules connecting to the high-speed bus (DMA, BBCU, EBCU, and internal RAM). It is derived from the system's source clock OSC (selected using OSCSEL[1:0] (D[3:2])) by dividing its frequency by a given value. Use CCLKSEL[1:0] to select this clock divide ratio. Table II.3.15.7 Selecting CCLK CCLKSEL1 CCLKSEL0 1 1 0 0 1 0 1 0 CCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b00) CCLK can be selected at any time. However, since the clocks are switched over when internally in the chip, all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, and up to 8 clock cycles are required before the clocks are actually changed after altering the register values. D[7:4] Reserved D[3:2] OSCSEL[1:0]: OSC Clock Select Bits Selects the clock source for the system (OSC). Table II.3.15.8 Selecting the System Clock Source OSCSEL1 OSCSEL0 1 1 0 0 1 0 1 0 Clock source PLL OSC3 OSC1 OSC3 (Default: 0b00) The clock sources changed here are not switched over immediately, but are actually switched over upon returning from SLEEP mode. Therefore, the CPU must be placed in SLEEP mode after setting up OSCSEL[1:0]. Note: When clock sources are changed, the clock control registers must be set so that the CMU is supplied with a clock from the selected clock source upon returning from SLEEP mode immediately after the change. Otherwise, the chip does not restart after return from SLEEP mode. II-3-38 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) D1 SOSC3: High-speed Oscillation (OSC3) On/Off Bit Turns the OSC3 oscillator circuit on or off. 1 (R/W): On (default) 0 (R/W): Off D0 SOSC1: Low-speed Oscillation (OSC1) On/Off Bit Turns the OSC1 oscillator circuit on or off. 1 (R/W): On (default) 0 (R/W): Off I Note: When SOSC3 (D1) or SOSC1 (D0) is set from 0 to 1 for initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes. To prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses. II CMU S1C33401 TECHNICAL MANUAL EPSON II-3-39 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48362: Core System Clock On/Off Register (pCMU2_SET) Register name Address Core system clock On/Off register (pCMU2_SET) Protected Bit 0048362 D15 D14-9 (HW) D8 D7-4 D3 D2 D1 D0 Name DBGNCLK - DBGCLK - HBCUCLK MMUCLK CCUCLK CPUCLK Function DBG NOSTOP clock On/Off reserved DBG clock On/Off reserved HBCU clock On/Off MMU clock On/Off CCU clock On/Off CPU clock On/Off D15 DBGNCLK: DBG NOSTOP Clock On/Off Bit Controls clock (NOSTOP) supply to the debug unit. 1 (R/W): On (default) 0 (R/W): Off D[14:9] Reserved D8 DBGCLK: DBG Clock On/Off Bit Controls clock (CCLK) supply to the debug unit. 1 (R/W): On (default) 0 (R/W): Off D[7:4] Reserved D3 HBCUCLK: HBCU Clock On/Off Bit Controls clock (CCLK) supply to the HBCU. 1 (R/W): On (default) 0 (R/W): Off D2 MMUCLK: MMU Clock On/Off Bit Controls clock (CCLK) supply to the MMU. 1 (R/W): On (default) 0 (R/W): Off D1 CCUCLK: CCU Clock On/Off Bit Controls clock (CCLK) supply to the CCU. 1 (R/W): On (default) 0 (R/W): Off D0 CPUCLK: CPU Clock On/Off Bit Controls clock (CCLK) supply to the CPU. 1 (R/W): On (default) 0 (R/W): Off Setting 1 On 0 Off - 1 On 0 Off - 1 On 0 Off Init. R/W 1 - 1 - 1 1 1 1 Remarks R/W - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W Note: Setting CPUCLK to 0 causes the CPU to stop operating, in which case the CPU can only be restarted by initial reset. II-3-40 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48364: Core System Clock Automatic Control Register (pCMU2_AUTO) Register name Address Bit Name Function reserved 0048364 D15-9 - Core system D8 DBGAUTO DBG clock automatic control clock automatic (HW) reserved D7-4 - control register D3 HBCUAUTO HBCU clock automatic control (pCMU2_AUTO) D2 MMUAUTO MMU clock automatic control D1 CCUAUTO CCU clock automatic control Protected D0 CPUAUTO CPU clock automatic control Setting - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled Init. R/W - 1 - 0 0 0 0 I Remarks - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W D[15:9] Reserved D8 DBGAUTO: DBG Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the debug unit. 1 (R/W): Enable (default) 0 (R/W): Disable II D[7:4] Reserved CMU D3 HBCUAUTO: HBCU Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the HBCU. 1 (R/W): Enable 0 (R/W): Disable (default) D2 MMUAUTO: MMU Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the MMU. 1 (R/W): Enable 0 (R/W): Disable (default) D1 CCUAUTO: CCU Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the CCU. 1 (R/W): Enable 0 (R/W): Disable (default) D0 CPUAUTO: CPU Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the CPU. 1 (R/W): Enable 0 (R/W): Disable (default) Note: Do not use the clock automatic control function when the operating frequency exceeds 50 MHz. S1C33401 TECHNICAL MANUAL EPSON II-3-41 II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48366: Peripheral and External Clock Output Control Register (pCMU2_CNTL_PERI) Register name Address Name Bit Function Setting Init. R/W reserved Peripheral and 0048366 D15-11 - - D10 CMUCLK2 External clock output (CMU_CLK) CMUCLK[2:0] (HW) CMU_CLK external clock D9 CMUCLK1 selection 111 PLL output control D8 CMUCLK0 110 OSC1 register 101 OSC3 (pCMU2_CNTL 100 CCLK(*) _PERI) 011 CCLK*1/8 010 CCLK*1/4 Protected 001 CCLK*1/2 000 CCLK*1/1 D7-2 - reserved - D1 PCLKSEL1 Peripheral clock (PCLK) selection PCLKSEL[1:0] PCLK D0 PCLKSEL0 11 OSC*1/8 10 OSC*1/4 01 OSC*1/2 00 OSC*1/1 - 0 0 0 Remarks - 0 when being read. R/W before clock tree - 0 0 - 0 when being read. R/W D[15:11] Reserved D[10:8] CMUCLK[2:0]: External Clock Output (CMU_CLK) Select Bits CMU_CLK is the clock for the external bus. It can be selected from the eight clocks listed in Table II.3.15.9. Table II.3.15.9 Selecting CMU_CLK CMUCLK2 CMUCLK1 CMUCLK0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CMU_CLK PLL OSC1 OSC3 CCLK (before clock tree) OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b000) CMU_CLK can be selected at any time. However, switching over the clocks creates hazards. When CMU_CLK must be output to external devices, it is also necessary to select a port function. For details on how to control clock output and about the port to be used, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." D[7:2] Reserved D[1:0] PCLKSEL[1:0]: Peripheral Clock (PCLK) Select Bits PCLK is the operating clock for peripheral circuits. It is derived from the system's source clock OSC (OSCSEL[1:0] (D[3:2]/0x48360)) by dividing its frequency by a given value. Use PCLKSEL[1:0] to select this clock divide ratio. Table II.3.15.10 Selecting PCLK PCLKSEL1 PCLKSEL0 1 1 0 0 1 0 1 0 PCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 (Default: 0b00) PCLK can be selected at any time. However, since the clocks are switched over internally in the chip when all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are required before the clocks are actually changed after altering the register values. II-3-42 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48368: Clock Option Register (pCMU2_OPT) Clock option register (pCMU2_OPT) Protected D[15:8] 0048368 (HW) I Bit Name Function Setting D15 D14 D13 D12 D11 D10 D9 D8 D7-4 D3 D2 D1 D0 OSCTM7 OSCTM6 OSCTM5 OSCTM4 OSCTM3 OSCTM2 OSCTM1 OSCTM0 - OSC3OFF TMHSP HALTMD WAKEUPWT OSC oscillation stabilization-wait timer 0 to 255 Register name Address reserved OSC3 disable during SLEEP Wait-timer high-speed mode HALT mode selection Wakeup-wait function enable 1 1 1 1 - 0 Stop High speed 0 HALT2 0 Wait interrupt 0 Init. R/W Run Normal HALT No wait 0 0 0 0 0 0 0 0 - 0 0 0 0 Remarks R/W - 0 when being read. R/W R/W R/W R/W OSCTM[7:0]: OSC Oscillation Stabilization-Wait Timer Sets an oscillation stabilization wait time during which the CPU is kept waiting before it starts operating upon returning from SLEEP mode. This wait time can be set in increments of 16 OSC clock cycles when TMHSP (D2) = 1, or 8,192 clock cycles when TMHSP (D2) = 0. (Default: 0b00 = no wait time) Table II.3.15.11 Oscillation Stabilization Wait Time at Wakeup TMHSP OSCTM[7:0] Number of clocks Time 1 0x0 0 0 0x1 800 ns 16 0x2 1.6 s 32 : : : 0xFF 0.204 ms 4080 0 0x0 0 0 0x1 0.409 ms 8192 0x2 0.819 ms 16384 : : : 0xFF 104.5 ms 2M (The time shown here is an example when operating with a 20 MHz OSC3.) When the OSC3 oscillation is to be turned off during SLEEP mode, make sure the wait time set by these bits is equal to or greater than the OSC3 oscillation start time stipulated in the electrical characteristics table. Note: The OSC oscillation start wait timer operates with the operating clock activated after the SLEEP mode is released. Therefore, use the switched clock frequency for calculating the oscillation wait time to be set to OSCTM[7:0] when executing the slp instruction for switching over the clock sources. D[7:4] Reserved D3 OSC3OFF: OSC3 Disable During SLEEP Selects whether to turn off the OSC3 oscillator circuit during SLEEP mode. 1 (R/W): Stop 0 (R/W): Operating (default) Continue operating OSC3 when entering SLEEP mode to switch over the clock sources (OSC), or turn it off when entering SLEEP mode for power-down purposes. D2 TMHSP: Stabilization-Wait Timer High-Speed Mode Select Bit Sets count mode for the oscillation stabilization wait timer (OSCTM[7:0]). 1 (R/W): High-speed mode 0 (R/W): Normal mode (default) The oscillation stabilization wait timer counts from 0 to 2M in units of 8,192 OSC clock cycles during normal mode, or from 0 to 4,080 in units of 16 OSC clock cycles during high-speed mode. Select either mode in which the OSC3 oscillation start time can be secured with the OSC frequency used. S1C33401 TECHNICAL MANUAL EPSON II-3-43 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) D1 HALTMD: HALT Mode Select Bit Selects the standby mode entered into by the halt instruction. 1 (R/W): HALT2 mode 0 (R/W): HALT mode (default) In HALT mode, the CPU, CCU, MMU, HBCU, and A0RAM all stop operating. In HALT2 mode, the BBCU, EBCU, and DMA also stop operating, in addition to the above. The other internal peripheral circuits remain in the state (idle or operating) held when the halt instruction was executed. D0 WAKEUPWT: Wakeup-Wait Function Enable Bit Enables the SLEEP mode wakeup-wait function used for switching over the clocks. 1 (R/W): Wait an interrupt 0 (R/W): No wait (default) When the slp instruction is executed while WAKEUPWT is set to 0, the CPU automatically reawakes from SLEEP mode several 10 clock cycles after instruction execution, and restarts with the source clock selected by OSCSEL[1:0] (D[3:2]/0x48360). Since even in this case the oscillation stabilization wait time set by OSCTM[7:0] (D[15:8]) is effective, OSCTM[7:0] should be set to 0x0 when clocks must be switched over in the shortest time possible. When WAKEUPWT is set to 1, the CPU can only be reawaken from SLEEP mode by an interrupt such as initial reset, RTC interrupt, forced break from the debugger, NMI, and other interrupt from an external source. II-3-44 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x4836A: NMI Flag Register (pCMU2_NMI_FLAG) Register name Address Bit Name NMI flag register 004836A D15-13 - D12 NMIF (pCMU2_NMI_FLAG) (HW) D11-0 - Protected Function reserved NMI flag reserved Setting - 1 NMI occurred 0 Not occurred - I Init. R/W - 0 0 Remarks - 0 when being read. R/W Reset by writing 1. - Writing 1 not allowed. D[15:13] Reserved D12 NMIF: NMI Flag Indicates the status of whether NMI has occurred. 1 (R): NMI occurred 0 (R): No NMI occurred (default) 1 (W): 0 (W): Clear the flag (0) Has no effect II When an NMI request is detected at the #NMI pin, NMIF is set to 1 and an NMI exception is generated. Writing a 1 resets the NMIF thus set. Note: NMIF should always be reset by writing a 1 in the NMI exception handler routine. Otherwise, an NMI exception may be generated again when the NMI exception handler routine is terminated by the reti instruction. D[11:0] Reserved (writing a 1 to these bits prohibited) S1C33401 TECHNICAL MANUAL EPSON II-3-45 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x4836C: NMI Mode Register (pCMU2_NMI_MODE) Register name Address Bit Name 004836C D15-9 - NMI mode D8 NMIMD (HW) register D7-0 - (pCMU2_NMI_MODE) Protected Function reserved NMI detection mode reserved Setting Init. R/W - 1 Low level 0 Falling edge - - 0 0 Remarks - 0 when being read. R/W - Writing 1 not allowed. D[15:9] Reserved D8 NMIMD: NMI Detection Mode Select Bit Selects the method of detecting whether to recognize NMI request input to #NMI by a falling edge or low level. 1 (R/W): Low level 0 (R/W): Falling edge (default) D[7:0] Reserved (writing a 1 to these bits prohibited) II-3-46 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x4836E: Clock Control Protect Register (pCMU2_PROTECT) Register name Address Bit Name Clock control 004836E D15-8 - D7 CLGP7 (HW) protect register D6 CLGP6 (pCMU2_PROTECT) D5 CLGP5 D4 CLGP4 D3 CLGP3 D2 CLGP2 D1 CLGP1 D0 CLGP0 Function Setting - reserved Clock control register protect flag Writing 10010110 (0x96) removes the write protection of the clock control registers (0x40180-0x40188, 0x48360- 0x4836A, 0x48370, 0x48372). Writing another value set the write protection. Init. R/W - 0 0 0 0 0 0 0 0 I Remarks - 0 when being read. R/W D[15:8] Reserved D[7:0] CLGP[7:0]: Clock Control Register Protect Flag Enables/disables write protection of the clock control registers (0x40180-0x40188, 0x48360-0x4836A and 0x48370-0x48372). 0x96 (R/W): Disable write protection Other than 0x96 (R/W): Write-protect the register (default: 0x0) Before altering any clock control register, write data 0x96 to the register to disable write protection. If this register is set to other than 0x96, even if an attempt is made to alter any clock control register by executing a write instruction, the content of said register will not be altered even though the instruction may have been executed without a problem. Once this register is set to 0x96, the clock control registers can be rewritten any number of times until being reset to other than 0x96. When rewriting the clock control registers has finished, this register should be set to other than 0x96 to prevent accidental writing to the clock control registers. S1C33401 TECHNICAL MANUAL EPSON II-3-47 II CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48370: CCLK System Peripheral Clock On/Off Register (pCMU2_CCLK_PERI) Register name Address CCLK system peripheral clock On/Off register (pCMU2_CCLK _PERI) Protected Bit Name 0048370 D15-12 - D11 BBEBNCLK (HW) D10 BBHBIFCLK D9 BBSRAMCLK D8 BBDBGIFCLK D7-6 - D5 EBCUHBCLK D4 EBCUSDCLK D3 A3RAMCLK D2 DMACLK D1 SAPB12CCLK D0 SAPB1PCLK Function reserved BBCU, EBCU NOSTOP On/Off BBCU HB I/F clock On/Off BBCU SRAM clock On/Off BBCU DBG I/F clock On/Off reserved EBCU HB I/F clock On/Off EBCU SDRAM clock On/Off A3RAM clock On/Off DMA clock On/Off SAPB12C clock On/Off SAPB1P clock On/Off Setting - 1 On 0 Off - 1 On 0 Off Init. R/W - 1 1 1 1 - 1 1 1 1 1 1 Remarks - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W D[15:12] Reserved D11 BBEBNCLK: BBCU, EBCU NOSTOP Clock Control Bit Controls clock (NOSTOP) supply to the BBCU and EBCU. 1 (R/W): On (default) 0 (R/W): Off D10 BBHBIFCLK: BBCU HB Interface Clock Control Bit Controls clock (CCLK) supply to the BBCU HB interface. 1 (R/W): On (default) 0 (R/W): Off D9 BBSRAMCLK: BBCU SRAM Clock Control Bit Controls clock (CCLK) supply to the BBCU SRAM interface. 1 (R/W): On (default) 0 (R/W): Off D8 BBDBGIFCLK: BBCU DBG Interface Clock Control Bit Controls clock (CCLK) supply to the BBCU DBG interface. 1 (R/W): On (default) 0 (R/W): Off D[7:6] Reserved D5 EBCUHBCLK: EBCU HB Interface Clock Control Bit Controls clock (CCLK) supply to the EBCU HB interface. 1 (R/W): On (default) 0 (R/W): Off D4 EBCUSDCLK: EBCU SDRAM Interface Clock Control Bit Controls clock (CCLK) supply to the EBCU SDRAM interface. 1 (R/W): On (default) 0 (R/W): Off D3 A3RAMCLK: A3RAM Clock Control Bit Controls clock (CCLK) supply to internal RAM in area 3. 1 (R/W): On (default) 0 (R/W): Off II-3-48 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) D2 DMACLK: DMA Clock Control Bit Controls clock (CCLK) supply to the DMA block. 1 (R/W): On (default) 0 (R/W): Off D1 SAPB12CCLK: SAPB12C Clock Control Bit Controls SAPB12C clock supply. 1 (R/W): On (default) 0 (R/W): Off D0 SAPB1PCLK: SAPB1P Clock Control Bit Controls SAPB1P clock supply. 1 (R/W): On (default) 0 (R/W): Off I II Note: SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block. SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop these clocks as the register read/write operation cannot be performed. S1C33401 TECHNICAL MANUAL EPSON II-3-49 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) 0x48372: CCLK System Peripheral Clock Automatic Control Register (pCMU2_AUTO_CCLK_PERI) Register name Address Bit Name Function reserved CCLK system 0048372 D15-11 - 1 Enabled D10 BBHBIFAUTO BBCU HB I/F clock auto control (HW) peripheral D9 BBSRAMAUTO BBCU SRAM clock auto control clock automatic D8 BBDBGIFAUTO BBCU DBG I/F clock auto control control register reserved D7-6 - (pCMU2_AUTO D5 EBCUHBAUTO EBCU HB I/F clock auto control 1 Enabled _CCLK_PERI) D4 EBCUSDAUTO EBCU SDRAM clock auto control D3 A3RAMAUTO A3RAM clock auto control Protected DMA clock auto control D2 DMAAUTO D1 SAPB12CAUTO SAPB12C clock auto control D0 SAPB1PAUTO SAPB1P clock auto control Setting - 0 Disabled - 0 Disabled Init. R/W - 0 0 0 - 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W D[15:11] Reserved D10 BBHBIFAUTO: BBCU HB Interface Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the BBCU HB interface. 1 (R/W): Enable 0 (R/W): Disable (default) D9 BBSRAMAUTO: BBCU SRAM Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the BBCU SRAM interface. 1 (R/W): Enable 0 (R/W): Disable (default) D8 BBDBGIFAUTO: BBCU DBG Interface Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the BBCU DBG interface. 1 (R/W): Enable 0 (R/W): Disable (default) D[7:6] Reserved D5 EBCUHBAUTO: EBCU HB Interface Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the EBCU HB interface. 1 (R/W): Enable 0 (R/W): Disable (default) D4 EBCUSDAUTO: EBCU SDRAM Interface Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the EBCU SDRAM interface. 1 (R/W): Enable 0 (R/W): Disable (default) D3 A3RAMAUTO: A3RAM Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to internal RAM in area 3. 1 (R/W): Enable 0 (R/W): Disable (default) II-3-50 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) D2 DMAAUTO: DMA Clock Automatic Control Bit Enables/disables the hardware function used to automatically control clock (CCLK) supply to the DMA block. 1 (R/W): Enable 0 (R/W): Disable (default) D1 SAPB12CAUTO: SAPB12C Clock Automatic Control Bit Enables/disables the hardware function used to automatically control SAPB12C clock supply. 1 (R/W): Enable 0 (R/W): Disable (default) D0 SAPB1PAUTO: SAPB1P Clock Automatic Control Bit Enables/disables the hardware function used to automatically control SAPB1P clock supply. 1 (R/W): Enable 0 (R/W): Disable (default) II Notes: * Do not use the clock automatic control function when the operating frequency exceeds 50 MHz. * SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block. SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop these clocks as the register read/write operation cannot be performed. S1C33401 TECHNICAL MANUAL EPSON I II-3-51 CMU II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU) II.3.16 Precautions Precautions regarding clock control * The clock control registers (0x40180-0x40188, 0x48360-0x4836A and 0x48370-0x48372) are write-protected. Before these registers can be rewritten, write protection must be removed by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Once write protection is removed, the clock control registers can be written to any number of times until the protect register is reset to other than 0x0096 (HW). Note that since unnecessary rewriting of the clock control registers could lead to erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless the clock control registers must be rewritten. * When clock sources are changed, the clock control registers must be set so that the CMU is supplied with a clock from the selected clock source upon returning from SLEEP mode immediately after the change. Otherwise, the chip may not restart after return from SLEEP mode. Furthermore, note that the timer, which generates an oscillation stabilization wait time after the SLEEP mode is released, operates with the clock after switching over. Be sure to use the correct clock frequency for calculating the wait time to be set to OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368). * When SOSC3 (D1/0x48360) or SOSC1 (D0/0x48360) is set from 0 to 1 for initiating oscillation by the oscillator, a finite time is required until the oscillation stabilizes (e.g., 25 ms for OSC3 and 3 seconds for OSC1 in the S1C33401). To prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics table elapses. * Immediately after the PLL is started by setting PLLPOWR (D0/0x40184) to 1, an output clock stabilization wait time is required (e.g., 200 s in the S1C33401). When the clock source for the system is switched over to the PLL, allow for this wait time after the PLL has turned on. * The frequency multiplication rate of the PLL that can be set depends on the upper-limit operating clock frequency of each S1C33 model and the OSC3 oscillation frequency. When setting the frequency multiplication rate, be sure not to exceed the upper-limit operating clock frequency. * The PLL can only be set up when the PLL is turned off (PLLPOWR (D0/0x40184) = 0) and the clock source is other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0-2). If settings are changed while the system is operating with the PLL clock, the system may operate erratically. * When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after returning from SLEEP mode. Precautions regarding reset input * Even if the #RESET pin is pulled low (= 0), the chip may not be reset unless supplied with a clock. To reset the chip for sure, #RESET should be held low for at least 10 OSC3 clock cycles. However, the input/output port pins will be initialized by cold reset regardless of whether the chip is supplied with a clock. * The oscillation start time of the high-speed (OSC3) oscillator circuit varies with the device used, board patterns, and operating environment. Therefore, a sufficient time should be provided before the reset signal is deasserted. Precautions regarding NMI input * The NMIF flag (D12/0x4836A) set by an NMI request should always be reset by writing a 1 in the NMI exception handler routine. Otherwise, an NMI exception may be generated again when the NMI exception handler routine is terminated by the reti instruction. * NMI cannot be nested. The CPU keeps NMI input masked out until the reti instruction is executed after an NMI exception occurred. Precautions regarding CCLK clock automatic control Do not use the CCLK clock automatic control function that can be set using the registers at 0x48364 and 0x48372 when the operating frequency exceeds 50 MHz. Precautions regarding SSCG control * When using the SSCG, always set SSMCITM[3:0] (D[7:4]/0x40188) to 0b0001. * SSMCIDT[3:0] (D[3:0]/0x40188) must be set according to the system clock frequency as shown in Table II.3.7.2.1. Using the SSCG with an improper setting may cause a malfunction of the IC. * The SSCG is effective only when the PLL is selected as the system clock source. Furthermore, the SSCG control registers cannot be set when the PLL is inactive. II-3-52 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4 High-Speed Bus Control Unit (HBCU) I II.4.1 Overview of the HBCU The High-speed Bus Control Unit (HBCU), which is connected directly to the CPU core, mainly controls the Cache Control Unit (CCU), Memory Management Unit (MMU), Area 0 Internal No-wait RAM (A0RAM), and bus modules as it fetches instructions or read/writes data. The following summarizes the main functions and features of the HBCU. * Arbitrates bus access requests from the CPU for the cache, A0RAM or other area 0 internal memory, and bus module. II * Manages a 4GB logical space by dividing it into eight 512MB blocks. Whether to use the cache and MMU, selecting cache write-back or write-through, and whether to use ASID can be set independently for each block. * Connected directly to the CPU via a 32-bit data bus, and operating with the same clock as the CPU (basically nowait), the HBCU supports high-speed data transfer between the CPU and the cache or A0RAM. Note that two instructions can be fetched in one clock cycle. * Capable of mirroring in 1GB units within the 4GB physical space and address processing for replacing the 6 high-order bits with ASID. * Can read and write data to and from A0RAM at the same time while fetching instructions from the cache, for high-speed processing. * Can create 64MB x 64 multiple virtual spaces in the logical address space by using a 6-bit ASID. S1C33 Microcomputer C33 ADV CPU MMU CCU HBCU Bus module (BBCU, etc.) External memory A0RAM (Area 0 No-Wait RAM) Figure II.4.1.1 HBCU S1C33401 TECHNICAL MANUAL EPSON II-4-1 HBCU II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.2 Outline of Address Processing Address processing modules Figure II.4.2.1 shows the functional modules that process addresses output from the CPU. HBCU CPU * Outputs logical addresses to access a 4GB linear address space. * Divides the logical space into 8 blocks and sets the attribute for each block. * Configures multiple virtual spaces using ASID. MMU CCU BBCU * Physical address cache after mirror processing * Performs mirror processing. * Translates logical addresses into physical addresses. * Decodes physical addresses to decide areas (chip enable) to access. * Outputs the physical address with the generated chip enable to the external bus. Memories and I/O devices Figure II.4.2.1 Functional Modules for Address Processing Address processing flow Logical address CPU output Block processing ASID processing Block 7 (0.5GB) 63 (64MB) 62 (64MB) Physical address When MMU is not used Physical address cache Block 6 (0.5GB) Address translation (when MMU is used) Block 5 (0.5GB) CPU 1M/64K (4KB/64KB) Block 4 (0.5GB) Area 21 (1GB) Block 2 (0.5GB) Block 0 (0.5GB) Output of a logical address to access a 4GB linear address space Setting use or not use attributes for MMU, ASID, instruction cache, data cache, and write-back mode HBCU Area 22 (2GB) Mirroring Block 3 (0.5GB) Block 1 (0.5GB) Area processing Mirror processing 3 (64MB) 2 (64MB) 1 (64MB) 0 (64MB) Multiplexing 64 spaces using 6 bits of ASID HBCU Area 20 (512MB) Areas 19-0 (512MB) 3 (4KB/64KB) 2 (4KB/64KB) 1 (4KB/64KB) 0 (4KB/64KB) 1GB Map 4KB or 64KB of pages to any desired physical addresses Setting the highorder 3GB as the mirror areas of the low-order 1GB MMU HBCU Control of the #CE signal, wait cycles, and other access conditions for each area BBCU Figure II.4.2.2 Contents of Address Processing II-4-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) Address processing for internal peripheral circuits and internal memories I CPU Area 0 A0RAM Other than areas 0-3 Internal bus Areas 1, 2, and 3 Block processing ASID processing MMU processing Areas 1-3 peripherals/ memories BBCU Mirror processing External bus II Cache Peripherals/ memories in area 6, etc. HBCU Figure II.4.2.3 Differences on Accesses to Internal Areas and External Areas Addresses that are mainly output to the external bus to access areas other than areas 0-6 are subject to the address processing described above. Normally, ASID and MMU are disabled to use in areas 0-6. Furthermore, these areas are not mirrored. Therefore, the address processing for areas 0-6 is different from the above description. A high-speed RAM (A0RAM) is mapped to area 0 and is accessed with no wait cycle using addresses output from the CPU directly. Areas 1, 2, and 3 are dedicated to the internal peripheral circuits and memories and block processing to mirror processing are not performed. Addresses from the CPU pass through the internal bus and directly access the internal modules mapped to areas 1-3. Areas 4, 5, and 6 are external memory areas, note, however, that normally block processing to mirror processing are not performed as in areas 1-3. Addresses from the CPU are directly passed to the BBCU and are output to the external bus. Area 6 is often used for embedded modules (model-specific circuits and extension peripheral circuits/ memories) other than the standard peripheral circuits mapped to area 1. Also in this case, addresses from the CPU are directly passed to the BBCU to access area 6. Areas 0-6 can be enabled to process their addresses with ASID and MMU by setting the HBCU in user mode only. Note that these areas cannot be mirrored even in this case. S1C33401 TECHNICAL MANUAL EPSON II-4-3 II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.3 Managing the Address Space The C33 ADV CPU has a 4GB address space (logical address space) based on the 32-bit internal address bus. Conversely, the physical address space has actual devices mapped into it and is accessed by the #CE signal and an external address bus. When the MMU is not used, the logical address equals the physical address. When the MMU is used, access to a logical address not equal to the physical address is allowed. For example, selecting whether to use the MMU collectively for the entire 4GB space may not always be effective depending on usage conditions. Therefore, the HBCU divides this 4GB of logical space into eight 512MB blocks from block 0 to block 7 (as shown in Figure II.4.3.1) for management purposes, thus allowing conditions to be set individually for each block. Block 7 (512M bytes) Block 6 (512M bytes) Block 5 (512M bytes) Block 4 (512M bytes) Block 3 (512M bytes) Block 2 (512M bytes) Block 1 (512M bytes) Block 0 (512M bytes) Logical address space 0xFFFF FFFF Block 7 : attribute 0xE000 0000 0xDFFF FFFF Block 6 : attribute 0xC000 0000 0xBFFF FFFF Block 5 : attribute 0xA000 0000 0x9FFF FFFF Block 4 : attribute 0x8000 0000 0x7FFF FFFF Block 3 : attribute 0x6000 0000 0x5FFF FFFF Block 2 : attribute 0x4000 0000 0x3FFF FFFF Block 1 : attribute 0x2000 0000 0x1FFF FFFF Block 0 : attribute 0x0000 0000 Physical address space Area 22 2G bytes Area 21 1G bytes Area 20 512M bytes Areas 19-0 512M bytes * MMU Used/Not used * ASID Used/Not used * Instruction cache Used/Not used * Data cache Used/Not used * Data cache write back Used/Not used Block attribute (selectable in each block) Figure II.4.3.1 Divided Logical Space and Relationship with Physical Space (when not using the MMU, ASID, and mirror functions) II-4-4 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.3.1 Contents of Individual Block Settings I The following settings can be made for each block individually by using the HBCU control registers. 1. Specifying whether to use the MMU Whether to use the MMU can be specified for each block individually. When MMUENx (x = 0-7) is set to 1, the MMU is used when accessing block `x', with its logical address translated into the physical address. When MMUENx = 0 (default), the logical address of block `x' is used directly as the physical address to access the corresponding device there. MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2*x) 2. Specifying whether to use the ASID Whether to use the ASID can be specified for each block individually. When ASIDENx (x = 0-7) is set to 1, the 6 high-order bits of the logical address are replaced with ASID[5:0] (D[5:0]/0x48312) when accessing block `x', thereby creating multiple virtual spaces. When ASIDENx = 0 (default), the logical address of block `x' is used directly as is. ASIDENx: Block x ASID Enable Bit in the Block x Configuration Register (D5/0x48302 + 2*x) HBCU The ASID and logical ASID values (used for comparison with the CPU address) also can be set by using the respective bits in the HBCU registers, ASID[5:0] (D[5:0]/0x48312) and ASID_VA[5:0] (D[5:0]/0x48314). ASID[5:0]: ASID Bits in the ASID Setup Register (D[5:0]/0x48312) ASID_VA[5:0]: Logical ASID Bits in the Logical ASID Setup Register (D[5:0]/0x48314) Moreover, if the cause of an ASID exception occurs, the selection of whether to generate an exception can be set. Set AEXPEN (D4/0x48300) to 1 to generate an ASID exception; set it to 0 to not generate an exception. AEXPEN: ASID Exception Enable Bit in the Address Control Register (D4/0x48300) 3. Specifying whether to use the instruction cache Whether to use the instruction cache can be specified for each block individually. When ICx (x = 0-7) is set to 1, the CCU is used to fetch instructions in block `x'. When ICx = 0 (default), all instructions in block `x' are fetched from an external device without using the cache. ICx: Block x Instruction Cache Enable Bit in the Block x Configuration Register (D0/0x48302 + 2*x) 4. Specifying whether to use the data cache Whether to use the data cache can be specified for each block individually. When DCx (x = 0-7) is set to 1, the CCU is used to read/write data in block `x'. When DCx = 0 (default), all data in block `x' is read/written to and from an external device without using the cache. DCx: Block x Data Cache Enable Bit in the Block x Configuration Register (D1/0x48302 + 2*x) 5. Selecting between write-back and write-through during cache write Data cache write mode can be specified for each block individually. When using the data cache with WRMDx (x = 0-7) set to 1, data write to block `x' is performed in write-back mode. When WRMDx = 0 (default), data write to block `x' is performed in write-through mode. However, before write-back mode can be selected, WBEN (D4/0x48340) in the CCU must be set to 1. When WBEN (D4/0x48340) = 0, all cache write operations are performed in write-through mode, regardless of how WRMDx is set. WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2*x) WBEN: Write-Back Enable Bit in the Cache Configuration Register (D4/0x48340) In write-back mode, data is only written to the cache, and memory is only updated when data in the cache is replaced. In write-through mode, data is written to both the cache and memory. Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are excluded from use of the MMU, ASID, and cache. For details about the MMU and ASID, see Section II.5, "Memory Management Unit (MMU)." For details about the cache, see Section II.6, "Cache Control Unit (CCU)." S1C33401 TECHNICAL MANUAL EPSON II II-4-5 II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.3.2 Settings for the Entire Address Space The following settings can be made for the entire 4GB address space. 1. Setting of a 1GB low-order mirror area As shown in Figure II.4.3.2.1, a 1GB block consisting of blocks 2 and 3, blocks 4 and 5, or blocks 6 and 7 (for which the two high-order address bits are set to 0) can each be used as a mirror area of blocks 0 and 1. However, the areas from 0x0 to 0x3FFFFF (areas 0 to 6) cannot be mirrored. Blocks 6 and 7 (1G bytes) 0xFFFF FFFF Mirror area Non-mirror area Blocks 4 and 5 (1G bytes) Logical address 0000 FFFF 0000 FFFF Mirror area Non-mirror area Blocks 2 and 3 (1G bytes) 0xC040 0xC03F 0xC000 0xBFFF 0x8040 0000 0x803F FFFF 0x8000 0000 0x7FFF FFFF Share physical addresses 0x400000 to 0x3FFFFFFF Mirror area Non-mirror area Blocks 0 and 1 (1G bytes) Effective area 0x4040 0000 0x403F FFFF 0x4000 0000 0x3FFF FFFF 0x0040 0000 0x0000 0000 Figure II.4.3.2.1 Address Space when Mirrors Area Set To use blocks 2 and 7 as a mirror area, set MIR (D0/0x48300) to 1. When not using any mirror areas, set MIR (D0/0x48300) to 0 (default). MIR: Mirroring Enable Bit in the Address Control Register (D0/0x48300) 2. Forcible use of the MMU in user mode Although selecting whether to use the MMU can be set individually for each block as described earlier, it is possible to specify the forcible use of the MMU in the entire 4GB space during user mode by setting UMDMEN (D1/0x48300) to 1. UMDMEN: MMU Forced Enable Bit in the Address Control Register (D1/0x48300) Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are normally excluded from use of the MMU. However, when UMDMEN (D1/0x48300) is set to 1, the MMU is forcibly used in that 4MB space as well. 3. Forcible use of the ASID in user mode Although selecting whether to use the ASID can be set individually for each block as for the MMU, it is possible to specify the forcible use of the ASID in the entire 4GB space during user mode by setting UMDAEN (D2/0x48300) to 1. UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300) Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are normally excluded from use of the ASID. However, when UMDAEN (D2/0x48300) is set to 1, the ASID is forcibly used in that 4MB space as well. II-4-6 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.4 Bus Access I The HBCU controls the MMU, CCU, A0RAM, and bus module according to bus access requests from the CPU, and arbitrates bus contention for those requests. When a bus access request is output from the CPU, the HBCU decodes the 3 high-order address bits (VA[31:29]) to identify the target block (one of blocks 0 to 7). Next, the HBCU determines the following content of processing from the register settings of said block, and sends a bus access request to the target unit. * Cache access not using the MMU * Cache access using the MMU * External bus access not using the MMU * External bus access using the MMU * Internal memory access II II.4.4.1 Cache Access When the instruction or data resides in the cache (a hit), reading is completed in one cycle (with address translation performed at the same time when using the MMU), and writing is completed in two cycles. When accessed for write, TAG memory of the CCU is read for comparison with the logical address from the CPU in the first cycle (with address translation performed at the same time when using the MMU). When it is a hit, data is written in the next cycle. II.4.4.2 External Memory Access When accessing external memory, the HBCU outputs a bus access request to the bus module. When use of the MMU is enabled, the HBCU first uses the MMU to translate the address, then outputs a bus access request to the bus module along with the translated address in the next cycle. II.4.4.3 Area 0 Internal Memory Access Access to internal memory in area 0 such as A0RAM (no-wait RAM in area 0) is completed in one cycle for both read and write. S1C33401 TECHNICAL MANUAL EPSON II-4-7 HBCU II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.5 ASID and Multiple Virtual Spaces The HBCU supports multiple virtual spaces configured by using an ASID (6-bit address space identifier). The normal method of memory usage (single virtual space) handles 4GB of memory as one contiguous address space, so that when a specific address in memory is accessed for read/write operation, data is always read from or written to the same location (except when address translation information changes). This means that multiple processes cannot be located in parallel in the same area unless using a time-multiplexed or similar other transfer method. Conversely, multiple virtual spaces supported by the HBCU can be considered to consist of up to 64 instances of 64MB spaces (i.e., processes) located in parallel in the same area. The ASID makes this possible. Before a logical address is input to the MMU when using the ASID, its 6 high-order bits are replaced with an ASID. Therefore, even when accessing the same address in memory, you can access another process by simply changing the ASID that is specifiable in a register. In other words, the ASID serves as a process number representing one of multiple 64MB processes. Figure II.4.5.1 shows the conceptual diagram of a logical address space where the ASID is used. Logical address 0x1FFF FFFF 0x1C00 0x1B0F 0x1800 0x17FF 0x1400 0x13FF 0x1000 0x0FFF 0x0C00 0x0B0F 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0x0800 0x07FF 0x0400 0x03FF 0x0000 0000 FFFF 0000 FFFF 0000 V[25:0] 0x03FF FFFF 0x0000 0000 Block 0 Blocks 1, 2, 3, 4, 5, 6 Process 7 64MB Process 6 64MB Process 5 64MB Process 4 64MB Process 3 64MB Process 2 64MB Process 1 64MB Process 0 64MB * ASID = 0x0 ASID = 0x1 ASID = 0x2 Process 0 Process 1 Process 2 * * * * * Logical address 0xFFFF FFFF 0xFC00 0xFB0F 0xF800 0xF7FF 0xF400 0xF3FF 0xF000 0xEFFF 0xEC00 0xEB0F 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0xE800 0xE7FF 0xE400 0xE3FF 0xE000 0000 FFFF 0000 FFFF 0000 Block 7 Process 63 64MB Process 62 64MB Process 61 64MB Process 60 64MB Process 59 64MB Process 58 64MB Process 57 64MB Process 56 64MB ASID = 0x3F Process 63 ***** Figure II.4.5.1 Multiple Virtual Spaces using the ASID To use the ASID, the ASID should be enabled for each block. To use the ASID in block `x' (x = 0-7), set the ASIDENx bit in the Block x Configuration Register to 1. ASIDENx: Block x ASID Enable Bit in the Block x Configuration Register (D5/0x48302 + 2*x) Also set the ASIDUSE bit in the TAG part of the TLB in the MMU to 1 (see Section II.5 for details). Although whether to use the ASID can be specified for each block independently, UMDAEN (D2/0x48300) may be set to 1 to specify forcible use of the ASID for the entire 4GB space in user mode. UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300) Of the 4GB space, area 0 to area 6 in block 0 (0x0 to 0x3FFFFF) are normally excluded from ASID use. However, when UMDAEN (D2/0x48300) is set to 1, the ASID is forcibly used in that 4MB space as well. The ASID and logical ASID values (used for comparison with the CPU address) can also be set by using ASID[5:0] (D[5:0]/0x48312) and ASID_VA[5:0] (D[5:0]/0x48314), respectively. ASID[5:0]: ASID Bits in the ASID Setup Register (D[5:0]/0x48312) ASID_VA[5:0]: Logical ASID Bits in the Logical ASID Setup Register (D[5:0]/0x48314) Setting AEXPEN (D4/0x48300) to 1 enables to generate an MMU exception if a space other than 64MB (0x0- 0x3FFFFFF) is accessed when ASID is used. AEXPEN: ASID Exception Enable Bit in the Address Control Register (D4/0x48300) II-4-8 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.6 Address ASID and Mirror Processing I Before it outputs an address, the HBCU performs two kinds of processing according to register settings as follows: 1. When UMDAEN (D2/0x48300) or the ASIDENx (D5/0x48302 + 2*x) for block `x' (x = 0-7) to access is set to 1, the HBCU replaces the 6 high-order address bits output by the CPU with the 6 ASID bits set in ASID[5:0] (D[5:0]/0x48312). 2. When MIR (D0/0x48300) is set to 1, the HBCU sets the 2 high-order address bits to 0b00 for enabling the 1GB mirroring function. The block to access is determined by the 3 high-order address bits output by the CPU. When ASIDENx (D5/0x48302 + 2*x) and MIR (D0/0x48300) are both set to 1, the 6 high-order address bits output by the CPU are replaced with ASID bits before setting the 2 high-order address bits to 0b00. II Mirror processing is applied to physical addresses. Therefore, the address from the CPU is mirrored directly when not using the MMU (or the ASID-replaced address when using the ASID). When using the MMU, the logical address is translated into the physical address before being mirrored. The address processing described in this section does not affect the discrimination of the block (0-7) in the logical address space since block discrimination is performed immediately after the CPU output the logical address. Figure II.4.6.1 shows the flow of processing from when the HBCU receives an address from the CPU until it outputs an address to the relevant unit. S1C33401 TECHNICAL MANUAL EPSON II-4-9 HBCU II-4-10 EPSON Internal memory (A0RAM) access yes Area 0 yes no (Area 1-6) Cache access yes IC/DC used in target block no Mirror processing no MMU used in target block no ASID used in target block no Area 6-0 no no yes yes yes yes MMU forcibly enabled in user mode no yes ASID forcibly enabled in user mode yes no no Mirror processing VA[31:26] replaced with ASID[5:0] yes Area 6-0 Figure II.4.6.1 Flow of Address Processing in the HBCU High-speed bus (bus module) access VA[31:30] forcibly set to `00' VA[31:30] forcibly set to `00' VA[31:26] replaced with ASID[5:0] Analyze CPU output address * get the block configuration register value from VA[31:29] * judge the area number as 6 or less (VA[31:22]=0) from VA[31:22] yes no Mirror processing MMU access no IC/DC used in target block no Area 6-0 no ASID used in target block yes yes yes VA[31:30] forcibly set to `00' MMU and cache access () VA[31:26] replaced with ASID[5:0] yes MMU forcibly enabled in user mode When mirroring is enabled, mirror processing is applied only to the address to be sent to the cache. no II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.7 Details of Control Registers I Table II.4.7.1 List of HBCU Registers Address 0x00048300 0x00048302 0x00048304 0x00048306 0x00048308 0x0004830A 0x0004830C 0x0004830E 0x00048310 0x00048312 0x00048314 Register name Address Control Register (pHBCU_ADR_CNT) Block 0 Configuration Register (pHBCU_BLK0) Block 1 Configuration Register (pHBCU_BLK1) Block 2 Configuration Register (pHBCU_BLK2) Block 3 Configuration Register (pHBCU_BLK3) Block 4 Configuration Register (pHBCU_BLK4) Block 5 Configuration Register (pHBCU_BLK5) Block 6 Configuration Register (pHBCU_BLK6) Block 7 Configuration Register (pHBCU_BLK7) ASID Setup Register (pHBCU_ASID_SETUP) Logical ASID Setup Register (pHBCU_LOGIC_ASID) Size 16 16 16 16 16 16 16 16 16 16 16 Function Set mirror, protect and forcible use of ASID/MMU, etc. Set block 0 Set block 1 Set block 2 Set block 3 Set block 4 Set block 5 Set block 6 Set block 7 Set ASID Set logical ASID II The following describes each HBCU control register. The HBCU control registers are mapped in the 16-bit device area from 0x48300 to 0x48314, and can be accessed in units of half-words or bytes. Note: When setting the HBCU control registers, be sure to write a 0, and not a 1, for all "reserved bits." S1C33401 TECHNICAL MANUAL EPSON II-4-11 HBCU II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) 0x48300: Address Control Register (pHBCU_ADR_CNT) Register name Address Bit Name Address 0048300 D15-6 - D5 HRUWP control register (HW) D4 AEXPEN (pHBCU_ADR D3 - _CNT) D2 UMDAEN D1 UMDMEN D0 MIR Function Setting reserved HBCU register user write protect ASID exception enable reserved ASID forced enable (user mode) MMU forced enable (user mode) Mirroring enable - 1 Protect 1 Enabled Init. R/W 0 Write enabled 0 Disabled - 1 Enabled 1 Enabled 1 Mirrored D[15:6] Reserved D5 HRUWP: HBCU Register User-Write-Protect Bit Sets write protection of the HBCU registers. 1 (R/W): Write protect 0 (R/W): Write enable (default) 0 Disabled 0 Disabled 0 Not mirrored - 0 0 - 0 0 0 Remarks - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W When this bit is set to 1, all HBCU registers (including this bit itself) are write-protected and cannot be accessed for write operation in user mode. Setting this bit in supervisor mode to 0 removes write protection. D4 AEXPEN: ASID Exception Enable Bit Enables the generation of ASID exceptions. The ASID exception is an MMU exception that occurs when an address outside the 64MB space (0x0-0x3FFFFFF) is accessed. 1 (R/W): Enable 0 (R/W): Disable (default) When this bit is set to 0, no exceptions are generated even when the cause of an ASID exception occurs. D3 Reserved D2 UMDAEN: ASID Forced Enable Bit Selects whether to forcibly use the ASID in user mode for the entire 4GB logical space (including loworder 4MB areas 0 to 6). 1 (R/W): Enable ASID 0 (R/W): Disable ASID (default) When this bit is 0, the ASID enable/disable setting of each block is effective. D1 UMDMEN: MMU Forced Enable Bit Selects whether to forcibly use the MMU in user mode for the entire 4GB logical space (including loworder 4MB areas 0 to 6). 1 (R/W): Enable MMU 0 (R/W): Disable MMU (default) When this bit is 0, the MMU enable/disable setting of each block is effective. D0 MIR: Mirroring Enable Bit Sets blocks 2 and 3, blocks 4 and 5, or blocks 6 and 7 as a 1GB mirror area of blocks 0 and 1 by setting the address A[31:30] to 0b00. However, the low-order 4MB space (areas 0 to 6) in block 0 is not mirrored. 1 (R/W): Set mirror area 0 (R/W): Normal area (default) For details about the MMU, see Section II.5, "Memory Management Unit (MMU)." II-4-12 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) 0x48302-0x48310: Block x Configuration Registers (pHBCU_BLKx) Register name Address Block x configuration register (pHBCU_BLKx) Bit Name 0048302 D15-6 - D5 ASIDENx | D4 MMUENx 0048310 D3 - (HW) D2 WRMDx D1 DCx D0 ICx Function reserved Block x ASID enable Block x MMU enable reserved Block x write-mode select Block x data cache enable Block x instruction cache enable Setting - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used Init. R/W - 0 0 - 0 0 0 I Remarks - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W Note: The letter `x' in bit names, etc., denotes a block number from 0 to 7. 0x48302 0x48304 0x48306 0x48308 0x4830A 0x4830C 0x4830E 0x48310 Block 0 Configuration Register (pHBCU_BLK0) Block 1 Configuration Register (pHBCU_BLK1) Block 2 Configuration Register (pHBCU_BLK2) Block 3 Configuration Register (pHBCU_BLK3) Block 4 Configuration Register (pHBCU_BLK4) Block 5 Configuration Register (pHBCU_BLK5) Block 6 Configuration Register (pHBCU_BLK6) Block 7 Configuration Register (pHBCU_BLK7) D[15:6] Reserved D5 ASIDENx: Block x ASID Enable Bit Enables the ASID for use when accessing block `x'. 1 (R/W): Enable ASID 0 (R/W): Disable ASID (default) II HBCU When this bit is set to 1, the 6 high-order bits of the logical address output by the CPU to access block `x' are replaced with the 6-bit ASID specified by ASID[5:0] (D[5:0]/0x48312). For block 0, however, even if its ASID is enabled (ASIDEN0 = 1), the ASID is not used when accessing the low-order 4MB space (areas 0 to 6), except when UMDAEN (D2/0x48300) = 1. D4 MMUENx: Block x MMU Enable Bit Enables the MMU for use when accessing block `x'. 1 (R/W): Enable MMU 0 (R/W): Disable MMU (default) When this bit is set to 1, the logical address output by the CPU to access block `x' is translated into the physical address by the MMU before being output from the HBCU. For block 0, however, even if its MMU is enabled (MMUEN0 = 1), the MMU is not used when accessing the low-order 4MB space (areas 0 to 6), except when UMDMEN (D1/0x48300) = 1. D3 Reserved D2 WRMDx: Block x Write-Mode Select Bit Selects write mode (write-through or write-back) when writing to the data cache. 1 (R/W): Write-back mode 0 (R/W): Write-through mode (default) In write-through mode, data is written to external memory at the same time it is written to the data cache. In write-back mode, data is only written to the data cache, and when data in the cache is replaced at a subsequent cache miss, the data is written to external memory. This setting is effective only when the data cache is enabled for use in block `x'. Also note that before using this bit to select write-back mode, WBEN (D4/0x48340) in the CCU must be set to 1 to enable the write-back function. S1C33401 TECHNICAL MANUAL EPSON II-4-13 II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) D1 DCx: Block x Data Cache Enable Bit Selects whether to use the data cache when accessing block `x'. 1 (R/W): Use cache 0 (R/W): Do not use (default) D0 ICx: Block x Instruction Cache Enable Bit Selects whether to use the instruction cache when fetching instructions from block `x'. 1 (R/W): Use cache 0 (R/W): Do not use (default) For details about the MMU, see Section II.5, "Memory Management Unit (MMU)." For details about the cache, see Section II.6, "Cache Control Unit (CCU)." II-4-14 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) 0x48312: ASID Setup Register (pHBCU_ASID_SETUP) Register name Address ASID setup register (pHBCU_ASID _SETUP) Bit Name 0048312 D15-6 - D5 ASID5 (HW) D4 ASID4 D3 ASID3 D2 ASID2 D1 ASID1 D0 ASID0 Function Setting - 0x0 to 0x3F reserved ASID I Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W D[15:6] Reserved D[5:0] ASID[5:0]: ASID Sets a 6-bit ASID (address space identifier). (Default: 0x0) When ASID is enabled, the 6 high-order bits of the logical address output by the CPU are replaced with the ASID specified by this register. Use of the ASID allows multiple virtual spaces (processes) to be configured in 64MB units, where the ASID is used as a process number. II HBCU S1C33401 TECHNICAL MANUAL EPSON II-4-15 II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) 0x48314: Logical ASID Setup Register (pHBCU_LOGIC_ASID) Register name Address Logical ASID setup register (pHBCU_LOGIC _ASID) Bit Name 0048314 D15-6 - D5 ASID_VA5 (HW) D4 ASID_VA4 D3 ASID_VA3 D2 ASID_VA2 D1 ASID_VA1 D0 ASID_VA0 Function Setting reserved Logical ASID (compared with VA[31:26] output from the CPU) - 0x0 to 0x3F Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W D[15:6] Reserved D[5:0] ASID_VA[5:0]: Logical ASID Sets a 6-bit logical ASID. (Default: 0x0) When using ASID-based multiple virtual spaces, use these bits to set the 6 high-order bits of the logical address of each process. The HBCU compares the 6 high-order address bits output by the CPU with ASID_VA[5:0] before ASID processing, and if the bits do not match, generates an ASID exception. However, this ASID exception is generated only when AEXPEN (D4/0x48300) is set to 1. II-4-16 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) II.4.8 Precautions I * During MMU exception handling, the MMU is disabled. During debug exception handling, MMU enable/disable and MMU exception generation conditions depend on the settings in the debug unit. When the MMU is disabled, even if the MMU exception handler routine is located in an area where the MMU is enabled for use, no address translation is performed. Note that addresses are handled as physical addresses. * To use the MMU for the entire 4GB space, set UMDMEN (D1/0x48300) to 1. To use the MMU for accessing a specific block, set MMUENx (D4/0x48302 + 2*x) for that block to 1. Also be sure to set MEN (D0/0x48320) in the MMU control register to 1. For the MMU to be used, both the HBCU and MMU must be set. For details about the MMU, see Section II.5, "Memory Management Unit (MMU)." * Mirror processing is applied to physical addresses. When the MMU is used, the physical address translated by the MMU is processed for mirroring. When mirroring, MMU, and cache are enabled, mirror processing is applied only to the address to be sent to the cache. In this case, the cache TAG address is compared with the address that has been processed for mirroring after translating into a physical address by the MMU. * When forcible use of the MMU in user mode is enabled, setting of the ASIDEN0 (D5) in the Block 0 Configuration Register (0x48302) is applied to areas 6 to 0. S1C33401 TECHNICAL MANUAL EPSON II-4-17 II HBCU II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU) THIS PAGE IS BLANK. II-4-18 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5 Memory Management Unit (MMU) I II.5.1 Overview of the MMU The Memory Management Unit (MMU) uses the internal Translation Lookaside Buffer (TLB) to translate the logical addresses supplied from the CPU via the HBCU into physical addresses. Consequently, programs and data in physical memory can be assumed to be located in a given virtual memory space when executed or accessed. Address translation is managed in units of pages, with the page size selectable from 4KB or 64KB. The main features of the MMU are outlined below. * With a 4-way set-associative method adopted, the MMU supports 16 entries per way for a total of 64 entries in the TLB. II * Divides the 4GB logical address space into eight 512MB blocks, allowing the MMU to be enabled or disabled for use in each block. * Manages the logical address space in units of pages. The page size can be selected from 4KB or 64KB. * Allows memory protection one page at a time by employing individual page protection or a user mode access protection facility. * Allows individual pages of the cache to be enabled or disabled simultaneously. * Supports six distinct causes of MMU exceptions. S1C33401 TECHNICAL MANUAL EPSON II-5-1 MMU II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.2 Logical and Physical Address Spaces The C33 ADV CPU has a 4GB memory space based on the 32-bit internal address bus. II.5.2.1 Logical Address Space With the MMU being used, the CPU can access virtual space to which actual devices are logically assigned. Therefore, the 4GB memory space handled by the CPU is called the "logical address space." The 4GB logical address space is managed separately in eight 512MB divided blocks by the HBCU connected directly to the CPU. Normally, the selection of whether to use the MMU is set in units of blocks. In this case, the MMU cannot be enabled for use in the lower 4MB part of the address space (areas 0 to 6). However, setting up the HBCU as required can forcibly enable MMU use in the entire 4GB space. In such case, the MMU is used for access to this lower 4MB part of address space (areas 0 to 6). II.5.2.2 Physical Address Space Separate from the logical address space is a space (where actual devices are mapped) comprised of the BBCU address bus and #CE signal. This is called the "physical address space." The physical address space is divided into 23 areas (areas 0 to 22). Areas 0 to 3 comprise an internal area (e.g., internal memory, internal I/O, debug area), whereas areas 4 and later comprise an external area that has external #CE output. For details about the physical address space, see the section in Chapter III, "C33 ADV Bus Block," that describes the BBCU. II.5.2.3 Relationship between Logical and Physical Address Spaces Figure II.5.2.3.1 shows the relationship between the logical and physical address spaces. Block 7 (512M bytes) Block 6 (512M bytes) Block 5 (512M bytes) Block 4 (512M bytes) Block 3 (512M bytes) Block 2 (512M bytes) Block 1 (512M bytes) Block 0 (512M bytes) Logical space 0xFFFF FFFF : : 0xE000 0000 0xDFFF FFFF : : 0xC000 0000 0xBFFF FFFF : : 0xA000 0000 0x9FFF FFFF : : 0x8000 0000 0x7FFF FFFF : : 0x6000 0000 0x5FFF FFFF : : 0x4000 0000 0x3FFF FFFF : : 0x2000 0000 0x1FFF FFFF : : 0x0000 0000 HBCU, MMU, BBCU Physical space Area 22 2G bytes Block processing ASID processing Address translation processing Area 21 1G bytes Mirroring processing Area processing Area 20 512M bytes Areas 19-0 512M bytes Figure II.5.2.3.1 Relationship between Logical and Physical Address Spaces II-5-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) The logical address output from the CPU is subjected to the five processes listed below by the HBCU, MMU, and BBCU to finally generate the physical address. 1. Block process 2. ASID process 3. Address translation process 4. Mirroring process 5. Area process The MMU is used for step 3 (address translation process). If the CPU accesses a logical block that has the "MMU used" attribute, the MMU translates the logical addresses into physical addresses in units of pages (4KB or 64KB). The 20 high-order bits of the logical address for 4KB per page or the 16 high-order bits of logical address for 64KB per page can be translated into a desired physical address. The MMU hardware contains a 64-entry TLB that can be used as an address translation table for translating up to 1M pages in 4KB per page or 64K pages in 64KB per page. The software (OS) manages the contents of the translation table. When the block has the "MMU not used" attribute, this processing is bypassed. Logical address Physical address : : : : : : : : : (Page 0) (Page 1) Logical addresses are mapped to physical addresses in page units. Figure II.5.2.3.2 Address Translation For example, assume that the 64KB page size is selected and addresses 0x2000 are to be converted to 0xC0. When the CPU accesses 64KB located at the beginning of block 1 (0x20000000-0x2000FFFF), the 64KB located at the beginning of area 10 (0xC00000-0xC0FFFF) is accessed for read/write operation. (Address translation is described in detail later.) S1C33401 TECHNICAL MANUAL EPSON II MMU (Page 2) Page 2 Page 1 Page 0 4KB or 64KB per page I II-5-3 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.3 Configuration of the MMU The MMU incorporated in the C33 ADV Core Block uses a 4-way set-associative method. The TLB is 4-way configured, having 16 entries per way. Therefore, the TLB has a total of 64 entries. Figure II.5.3.1 shows the general configuration of the MMU. DATA TAG LRU Entry 0 Entry 1 Entry 2 Entry 3 Entry 4 Entry 5 Entry 6 Entry 7 Entry 8 Entry 9 Entry 10 Entry 11 Entry 12 Entry 13 Entry 14 Entry 15 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Figure II.5.3.1 General Configuration of the MMU II.5.3.1 TAG Part and DATA Part The TLB consists of a TAG part and a DATA part, whose respective contents vary with the page size selected. Figure II.5.3.1.1 shows the configuration of the TAG and DATA parts of the TLB. For 4KB/page TAG DATA CVA[31:16] AU WP UP AP CE V A CA[31:12] D 16 bits 24 bits 20 bits For 64KB/page TAG DATA CVA[31:20] invalid 12 bits 4 bits AU WP UP AP CE V A D 24 bits CA[31:16] invalid 16 bits 4 bits 20 bits CVA[31:16/20] : Comparison logical address CA[31:12/16] : Conversion physical address AU WP UP AP CE V A D ASIDUSE WRP UMP ACP CE VLD ACC DTY : Use of ASID bit : Write-protect bit : User-protect bit : Access-protect bit : Cache enable bit : Valid bit : Access bit : Dirty bit 0 = Not used 0 = Not protected 0 = Not protected 0 = Not protected 0 = Disabled 0 = Invalid 0 = Not accessed 0 = Not written 1 = Used 1 = Protected 1 = Protected 1 = Protected 1 = Enabled 1 = Valid 1 = Accessed 1 = Written Initial value = Undefined Initial value = Undefined Initial value = Undefined Initial value = Undefined Initial value = Undefined Initial value = Undefined Initial value = 0 Initial value = 0 Figure II.5.3.1.1 Configuration of the TLB II-5-4 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) TAG part I The TAG part consists of the information shown below. The CVA (comparison address) can be confirmed and set using the MMU TAG Address Register (0x48328). Other bits can be confirmed and set using the MMU Page Setting Register (0x4832A). CVA (comparison address) This is the address compared with the logical address supplied from the HBCU. The compared address bits vary with the page size selected by the MMU. For 4KB per page, 16 CVA bits or CVA[31:16] are compared with the 16 high-order bits of the logical address. For 64KB per page, 12 CVA bits or CVA[31:20] are compared with the 12 high-order bits of the logical address. Depending on whether the logical address and this comparison address match (a hit) or do not match (a miss), the MMU performs the appropriate processing. II ASIDUSE (ASID use) bit This bit specifies whether to use the ASID when translating addresses of the page specified in a TLB entry. The MMU uses ASID when this bit is set to 1. The HBCU should also be set up accordingly for the ASID to be used. WRP (write protect) bit This bit is used to write-protect the content of the page specified in a TLB entry. When this bit is set to 1, the page is write-protected and its content cannot be altered regardless of whether the CPU is operating in supervisor mode or user mode. The page can be accessed for read operation, however. UMP (user mode access protect) bit This bit protects the page specified in a TLB entry against access in user mode. When this bit is set to 1, the page is disabled against read/write operation in user mode. The page can be accessed for read/write operation in supervisor mode, however. ACP (access protect) bit This bit protects the page specified in a TLB entry against access. When this bit is set to 1, the page is disabled against read/write operation in both supervisor mode and user mode. CE (cache enable) bit This bit specifies whether to use the CCU (cache) to access the page specified in a TLB entry. The MMU uses the cache when this bit is set to 1. The HBCU and CCU should also be set up accordingly for the cache to be used. VLD (valid) bit This bit indicates whether the content of the TAG part is valid. The content is valid when VLD = 1. ACC (access) bit This bit indicates whether the page specified in a TLB entry has been accessed for read/write operation. When this bit is 1, it means that the page has been accessed. DTY (dirty) bit This bit indicates whether data has been written to the page specified in a TLB entry. When this bit is 1, it means that data has been written to the page. S1C33401 TECHNICAL MANUAL EPSON II-5-5 MMU II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) DATA part The DATA part is where the physical address is saved. The address bits saved in this part vary with the page size selected. For 4KB per page, the 20 high-order bits of the physical address (CA[31:12]) are saved. For 64KB per page, the 16 high-order bits of the physical address (CA[31:16]) are saved. The 12 low-order bits (for 4KB per page) or 16 low-order bits (for 64KB per page) of the physical address consist of the same bit content as that of the logical address. The content of the DATA part can be confirmed and set using the MMU 4KB Data Address Register (0x48324) and MMU Common Data Address Register (0x48326). II.5.3.2 LRU Due to its 4-way configuration, the MMU can have up to four items of address translation information with the same entry number. In case of an MMU miss, the address information contained in the MMU must be replaced with one of the four ways selected. The LRU part holds that way number. Although LRU (Least Recently Used) is the algorithm used to select the way that was least recently accessed, a pseudo-LRU algorithm with a simplified circuit configuration is adopted for the MMU in the C33 ADV Core. In case of an MMU hit, the LRU information held by the accessed entry is automatically updated. II-5-6 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.4 Settings and Operation of the MMU I II.5.4.1 Enabling the MMU When initially reset, use of the MMU is disabled. To use the MMU, the following settings are required: 1. Setting up the HBCU The HBCU manages the 4GB logical address space separately in eight 512MB blocks. Whether to use the MMU can be selected for each block individually. To use the MMU in block `x' (x = 0-7), set the MMUENx bit (D4) in the Block x Configuration Register of the HBCU to 1 (= enable). MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2*x) II For details about the HBCU, see Section II.4, "High-Speed Bus Control Unit (HBCU)." 2. Setting up the MMU To use the MMU, MEN (D0/0x48320) in the MMU should also be set to 1. MEN: MMU Enable Bit in the MMU Control Register (D0/0x48320) The MMU is enabled for use by the two settings above. Note, however, that the MMU is disabled during MMU exception handling (PSR register ME bit = 1). Even if the MMU exception handler routine is located in a block where the MMU is enabled for use, no address translation is performed and logical addresses are handled directly as physical addresses. When initially reset, all MMU registers are write-protected in user mode. The registers can only be read in user mode, but can be both read and written to in supervisor mode. To set up the MMU registers in user mode, reset MRUWP (D12/0x48320) by writing a 0 in supervisor mode to enable the registers for write operation in user mode. MRUWP: MMU Register User Write Protect Bit in the MMU Control Register (D12/0x48320) II.5.4.2 Specifying a Page Size Use 64KMD (D8/0x48320) to specify the page size of the MMU. 64KMD: Page Size Select Bit in the MMU Control Register (D8/0x48320) The page size is 4KB when 64KMD (D8/0x48320) = 0 or 64KB when 64KMD (D8/0x48320) = 1. II.5.4.3 ASID Processing The ASID is used for two purposes: for using multiple virtual spaces, and generating entry numbers. Using multiple virtual spaces When an accessed block has been enabled for using the MMU and ASID in the HBCU, the HBCU replaces the 6 high-order bits (VA[31:26]) of the logical address (hereafter the VA) output by the CPU with ASID[5:0] (D[5:0]/0x48312) before forwarding it to the MMU. Because the 6 high-order bits VA[31:26] are replaced with ASID, processes are handled as multiple virtual spaces (where the ASID is handled as a process ID). In the HBCU, these bits are compared with the logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) before the 6 high-order bits VA[31:26] are replaced with ASID[5:0]. A mismatch means that access will be made to a different process other than the one whose process ID is specified by the ASID. Therefore, an ASID exception (one cause of an MMU exception) is generated. Generating an entry number When ASIDMIX (D4/0x48320) is set to 1, the 4-bit field in the logical address that indicates an entry number (i.e., VA[15:12] for 4KB per page, VA[19:16] for 64KB per page) is combined with ASID to generate an entry number. ASIDMIX: Entry Number Generation Mode Bit in the MMU Control Register (D4/0x48320) The purpose of this operation is to prevent a reduction in the TLB hit rate when a specific entry is used for two or more processes in multiple virtual spaces. Compared to the entry number generated from VA, the one generated here is another entry number that includes ASID information. Distributed entries help to increase the hit rate. S1C33401 TECHNICAL MANUAL EPSON II-5-7 MMU II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.4.4 Address Translation Figure II.5.4.4.1 shows the flow of 4KB-per-page address translation. Figure II.5.4.4.2 shows the flow of 64KBper-page address translation. 31 0 Logical address VA[31:0] from the CPU VA[31:0] ASID processing (when ASIDENx = 1) 31 When ASID is used 26 25 VA[11:0] VA[31:16] VA[15:12] VA[11:0] Comparison address Entry No. VA[25:16] ASID[5:0] When ASID is not used ASID processing (when ASIDMIX = 1) 16 15 12 11 Entry[3:0] 0 ASID enable/disable information DATA TAG LRU Entry 0 Entry 1 Entry 2 : : Entry 15 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 CMP0 CMP1 CMP2 CMP3 Way selection MUX Hit Final physical address PA[31:0] CA[31:12] VA[11:0] Note: CA denotes the translated address contained in the DATA part of the TLB. Figure II.5.4.4.1 Flow of Address Translation (4KB Per Page) 31 0 Logical address VA[31:0] from the CPU VA[31:0] ASID processing (when ASIDENx = 1) 31 When ASID is used When ASID is not used 26 25 ASID[5:0] ASID processing (when ASIDMIX = 1) 20 19 16 15 Entry[3:0] VA[25:20] VA[31:20] VA[19:16] Comparison address Entry No. 0 VA[15:0] VA[15:0] ASID enable/disable information DATA TAG LRU Entry 0 Entry 1 Entry 2 : : Entry 15 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 CMP0 CMP1 CMP2 CMP3 Way selection MUX Hit Final physical address PA[31:0] VA[15:0] CA[31:16] Note: CA denotes the translated address contained in the DATA part of the TLB. Figure II.5.4.4.2 Flow of Address Translation (64KB Per Page) II-5-8 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) When the CPU accesses a block where the MMU is enabled for use, the block's logical address is translated into a physical address according to the procedure described below. I 1. When ASID has been enabled for use in the HBCU, ASID processing is applied to the logical address VA from the CPU as described above. Prior to ASID processing, VA[31:16] and ASID_VA[5:0] (D[5:0]/0x48314) are compared, and if they do not match, an MMU exception is generated. When ASID is disabled against use, the logical address from the CPU is translated directly as is. 2. The TAG part and DATA part information for 4 ways of TLB is read from the target entry. When the page size is set to 4KB per page, VA[15:12] is the TLB entry number; for 64KB per page, VA[19:16] is the TLB entry number. 3. The comparison address read from the TAG part is compared with the logical address received from the CPU. For 4KB per page, comparison is made between CVA[31:16] and VA[31:16] from the CPU; for 64KB per page, comparison is made between CVA[31:20] and VA[31:20]. Moreover, the ASID enable/disable information received from the HBCU is compared with the ASIDUSE bit in the TAG part. Even when the compared addresses match, an MMU miss is assumed if the ASID enable/disable information and ASIDUSE do not match. 4. When the compared addresses and ASID enable/disable information and ASIDUSE both match in one of four ways, and the intended access does not violate the page protect information in the TAG part, an MMU hit is assumed. Thus, the translated address (hereafter CA) read from the DATA part of the way that made a hit is selected. For 4KB per page, CA[31:12] + VA[11:0] is the final physical address; for 64KB per page, CA[31:16] + VA[15:0] is the final physical address. 5. When the final physical address is determined, that address information is passed to the HBCU for use as the address to access physical memory. If no matching way is found in the address comparison in step 3, an MMU miss is assumed and an MMU exception generated to the CPU. Even when a matching way is found in both address and ASID enable/disable comparisons, if a page protect violation is found in step 4, an MMU exception is generated to the CPU. If an MMU exception occurs, information about the cause of MMU exception, the way that generated the exception, the ways to be replaced, logical address, etc. are set in respective registers. For details, see Section II.5.6, "MMU Exceptions." Figure II.5.4.4.3 shows an example of address translation in cases where the MMU, CCU, ASID, and mirror processing are used in combination. S1C33401 TECHNICAL MANUAL EPSON II-5-9 II MMU II-5-10 EPSON Disabled Disabled Disabled Disabled Disabled Disabled 1 0 Disabled Disabled Enabled 2 Enabled Enabled Enabled 4 Disabled Disabled Enabled Enabled Enabled Enabled 5 3 Disabled Enabled Disabled Cache 6 MMU Disabled Enabled Disabled ASID 7 Block Pro4 Pro1 Pro2 Pro3 Pro5 CPU address Pro5 Pro2 Pro1 as is as is as is Physical address Pro1 Pro2 Figure II.5.4.4.3 Example of Address Translation Logical address Pro1 Pro2 Cache Cache Cache Pro2 Pro1 Cache Pro3 Pro4 Pro5 Pro2 Pro1 Pro5 Pro3 Pro4 Pro5 Pro3 Pro4 Pro2 Pro1 as is Pro5 Pro3 Pro4 Pro3 and Pro4 used separately by changing ASID with a tact switch Mirror processing A[31:30] = 00 Pro4 Pro3 Pro5 Address translation processing Pro3 Pro4 as is ASID processing Area 14 Area 10 Area 20 (512MB) Physical Memory II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.5 Setting Up the TLB I The content of the TLB can be set and confirmed using the MMU registers. When initially reset, all MMU registers are write-protected in user mode. The registers can only be read in user mode, but can be both read and written to in supervisor mode. To set up the MMU registers in user mode, reset MRUWP (D12/0x48320) by writing a 0 in supervisor mode to enable the registers for write operation in user mode. MRUWP: MMU Register User Write Protect Bit in the MMU Control Register (D12/0x48320) Note: TLB initialization or alteration of TLB content pursuant to the occurrence of an MMU exception should always be performed in an area where the MMU is not used. II.5.5.1 Setting Up the TLB II Follow the method described below to set the TLB content. 1. Specifying the TLB to be set or altered Specify the TLB entry number and way number to be set or altered by using ENT[3:0] (D[7:4]/0x48322) and WAY[3:0] (D[3:0]/0x48322), respectively. MMU ENT[3:0]: Entry Number Setting Bits in the MMU Entry Register (D[7:4]/0x48322) WAY[3:0]: Way Number Setting Bits in the MMU Entry Register (D[3:0]/0x48322) The WAY0 to WAY3 bits correspond to ways 0 to 3, respectively. Always be sure to set one bit at a time. If two or more bits are set, two or more ways will be altered at the same time. 2. Setting write information Set the page setup information and comparison address to be written to the TAG part, and the translation address to be written to the DATA part in each register as described below. TAG part page setup information The page setup information refers to the page protection setup, cache enable/disable, and other related information in the TAG part. For the content of each bit, see Section II.5.3, "Configuration of the MMU." The MMU Page Setting Register (0x4832A) contains the control bits corresponding to each item of page setup information. Use these bits to set the contents to be written to the TAG part. TAG part comparison address The TAG part comparison address should be set in the MMU TAG Address Register (0x48328). The D[15:0] bits in this register correspond to CVA[31:16] of the comparison address. For 4KB per page, set all 16 bits in CVA[31:16]. For 64KB per page, only CVA[31:20] (D[15:4]) are effective, with the 4 low-order bits ignored. DATA part translation address The DATA part translation address should be set in the MMU Common Data Address Register (0x48326). This register corresponds to the 16 high-order address bits (CA[31:16]). For 64KB per page, this register alone can be used to set the translation address. For 4KB per page, set the 16 high-order bits in this register and the remaining 4 low-order bits (CA[15:12]) in D[15:12] of the MMU 4KB Data Address Register (0x48324). 3. Writing to the TLB To write to the TLB, use the available control bits separately for the TAG part and DATA part. Writing to the TAG part Write a 1 to TAGWR (D4/0x4832C). Then the page setup information and comparison address set in step 2 will be written to the TAG part in the entry and way specified in step 1. TAGWR: TAG Entry Write Bit in the TLB Control Register (D4/0x4832C) S1C33401 TECHNICAL MANUAL EPSON II-5-11 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) Writing to the DATA part Write a 1 to DATWR (D0/0x4832C). Then the translation address set in step 2 will be written to the DATA part in the entry and way specified in step 1. DATWR: DATA Entry Write Bit in the TLB Control Register (D0/0x4832C) When the TAG part and DATA part must be set at the same time as when initializing the TLB, it is possible to write a 1 to both TAGWR (D4/0x4832C) and DATWR (D0/0x4832C) at the same time. Writing a 0 to these bits has no effect. II.5.5.2 Confirming the Set Content of the TLB The content of the TLB can be confirmed by following the method described below. 1. Specifying the TLB to confirm Specify the TLB entry number and way number to confirm by using ENT[3:0] (D[7:4]/0x48322) and WAY[3:0] (D[3:0]/0x48322), respectively. ENT[3:0]: Entry Number Setting Bits in the MMU Entry Register (D[7:4]/0x48322) WAY[3:0]: Way Number Setting Bits in the MMU Entry Register (D[3:0]/0x48322) The WAY0 to WAY3 bits correspond to ways 0 to 3, respectively. Always be sure to set one bit at a time. If two or more bits are set, a way cannot be specified correctly. 2. Reading out the TLB information To read out the TLB information, use the control bits available separately for the TAG part and DATA part. Reading out the TAG part Write a 1 to TAGRD (D5/0x4832C). TAGRD: TAG Entry Read Bit in the TLB Control Register (D5/0x4832C) As a result, the TAG part comparison address and page setup information in the entry/way specified in step 1 will be loaded in the MMU TAG Address Register (0x48328) and MMU Page Setting Register (0x4832A), respectively. Reading out the DATA part Write a 1 to DATRD (D1/0x4832C). DATRD: DATA Entry Read Bit in the TLB Control Register (D1/0x4832C) As a result, the 16 high-order bits (CA[31:16]) and 4 low-order bits (CA[15:12]) in the entry/way specified in step 1 will be loaded in the MMU Common Data Address Register (0x48326) and D[15:12] of the MMU 4KB Data Address Register (0x48324), respectively. For 64KB per page, only the MMU Common Data Address Register (0x48326) is effective. The MMU 4KB Data Address Register (0x48324) is used for 4KB per page. After the operation above, read the respective registers to confirm the TLB information. If necessary, the TAG part and DATA part information can be loaded in the respective registers at one time by writing a 1 to both TAGRD (D5/0x4832C) and DATRD (D1/0x4832C) at the same time. Writing a 0 to these bits has no effect. II.5.5.3 Flushing the TLB Flush means invalidating entries in the TLB. When the TLB is flushed, all VLD (valid), ACC (access), and DTY (dirty) bits in the TAG part and the LRU are initialized to invalidate the TLB. The contents of the DATA part are not cleared. To flush the TLB, write a 1 to FLUSH (D8/0x4832C). FLUSH: TLB Flush Control Bit in the TLB Control Register (D8/0x4832C) Before flushing the TLB, always be sure to set MEN (D0/0x48320) to 0 to disable the MMU. MEN: MMU Enable Bit in the MMU Control Register (D0/0x48320) II-5-12 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.6 MMU Exceptions I II.5.6.1 Types of MMU Exceptions There are six distinct causes of MMU exceptions for the C33 ADV Core as outlined below. 1. MMU access protect exception This exception occurs for a violation of page protection when an attempt is made to read or write to an accessprotected page (TAG part ACP bit = 1). Since this exception is generated prior to memory access, no data is read or written to the page in question. When this exception occurs, exception status bit EXPACP (D5/0x4832E) is set to 1. EXPACP: MMU Access-Protect Exception Status Bit in the MMU Exception Status Register (D5/0x4832E) II 2. MMU user mode protect exception This exception occurs for a violation of page protection when an attempt is made to read or write to a user mode-protected page (TAG part UMP bit = 1) in user mode. Since this exception is generated prior to memory access, no data is read or written to the page in question. When this exception occurs, exception status bit EXPUMP (D6/0x4832E) is set to 1. EXPUMP: MMU User-Mode-Protect Exception Status Bit in the MMU Exception Status Register (D6/0x4832E) 3. MMU write protect exception This exception occurs for a violation of page protection when an attempt is made to write to a write-protected page (TAG part WRP bit = 1). Since this exception is generated prior to memory access, no data is written to the page. When this exception occurs, exception status bit EXPWRP (D7/0x4832E) is set to 1. EXPWRP: MMU Write-Protect Exception Status Bit in the MMU Exception Status Register (D7/0x4832E) 4. ASID exception This exception occurs for a violation of process protection when using ASID-based multiple virtual spaces in a process to access an address space exceeding the 64MB boundary. Specifically, this exception occurs when the logical address VA[31:26] and logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) do not match as compared before VA[31:26] is replaced with ASID. Therefore, no data is read or written to the said address. When this exception occurs, exception status bit EXPASID (D4/0x4832E) is set to 1. EXPASID: ASID Exception Status Bit in the MMU Exception Status Register (D4/0x4832E) A request to the CPU for processing this exception is generated only when AEXPEN (D4/0x48300) in the HBCU is set to 1 (default = 0). However, EXPASID (D4/0x4832E) is set to 1 whenever this exception occurs, regardless of whether AEXPEN (D4/0x48300) is set. 5. MMU multi-hit exception This exception occurs when multiple ways make a hit in address comparison. Since this exception is generated prior to memory access, no data is read or written. When this exception occurs, exception status bit EXPMLT (D3/0x4832E) is set to 1. EXPMLT: MMU Multi-Hit Exception Status Bit in the MMU Exception Status Register (D3/0x4832E) The ways that made a hit can be confirmed using HITWAY[3:0] (D[11:8]/0x48322). HITWAY[3:0]: Hit Way Number Bits in the MMU Entry Register (D[11:8]/0x48322) S1C33401 TECHNICAL MANUAL EPSON II-5-13 MMU II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 6. MMU miss exception This exception occurs due to one of the conditions listed below. * A way matched in address comparison is not found * The VLD bit in the TAG part has been set to 0. * ASID enable/disable information in the HBCU is different from the ASIDUSE bit status in the TAG part. In such case, the TLB must be replaced (i.e., set up its content again). When this exception occurs, exception status bit EXPMISS (D2/0x4832E) is set to 1. EXPMISS: MMU Miss Exception Status Bit in the MMU Exception Status Register (D2/0x4832E) The ways that require replacement can be confirmed using REPWAY[3:0] (D[15:12]/0x48322). REPWAY[3:0]: Replace Way Number Bits in the MMU Entry Register (D[15:12]/0x48322) One signal line is available to forward MMU exception processing requests to the CPU. Therefore, this signal line is commonly used for the above six causes of MMU exceptions. If any MMU exception occurs, read the MMU Exception Status Register (0x4832E) in the MMU exception handler routine to determine the cause of occurrence. II.5.6.2 MMU Exception Vector Address and Stack Area Internal RAM addresses 0x00000010 through 0x0000001F in area 0 are reserved for use in case of MMU exceptions. 0x00000010: MMU exception vector address is saved here (4 bytes). 0x00000018: PC is saved here at MMU exception occurrence (4 bytes). 0x0000001C: R0 is saved here at MMU exception occurrence (4 bytes). To use the MMU, always be sure to set the vector address at 0x00000010 before enabling the MMU. Moreover, because the internal RAM addresses in area 0 above are reserved for MMU use, do not use this internal RAM area for any other purpose. II.5.6.3 Processing when an MMU Exception Occurs When an MMU exception occurs, the MMU sends an MMU exception request to the CPU, and simultaneously sets the MMU exception occurrence status in each register as described below. * The cause of the MMU exception that occurred is set in the MMU Exception Status Register (0x4832E). * The logical address that caused the MMU exception to occur is set in the MMU Exception Address Registers 1 and 2 (0x48330 and 0x48332). * The following items are set in the MMU Entry Register (0x48322): - The entry number that caused the MMU exception to occur is set in ENT[3:0] (D[7:4]). - One of the HITWAY[3:0] (D[11:8]) bits corresponding to the way number that caused the MMU exception to occur is set. In case of multiple hits, the bits corresponding to all "hit" ways are set. - If the cause of MMU exception is an MMU miss, the way number to be replaced is set in REPWAY[3:0] (D[15:12]) and WAY[3:0] (D[3:0]). When an MMU exception occurs, first read the MMU Exception Status Register (0x4832E) in the MMU exception handling routine to confirm what caused the MMU exception to occur. The MMU exception status bits are not automatically cleared. Always be sure to clear all status bits in MMU exception handling. If these bits remain set when returning from the MMU exception handler routine, the same exception will reoccur. Next, inspect the TLB information held when the exception occurred. The TLB should be altered to the appropriate content. To return from the MMU exception handler routine, execute the retm instruction. Figure II.5.6.3.1 shows the flow of processing performed when an MMU exception occurs. II-5-14 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) MMU exception occurs I Set MMU exception information in each register Send an MMU exception request to the CPU Switch to supervisor mode Processing in hardware Save the PC to address 0x00000018 Save R0 to address 0x0000001C II Fetch the MMU exception vector from address 0x00000010 Jump to the vector address Read the MMU register to confirm the cause of exception MMU Clear all MMU exception status bits Processing in software Alter the TLB content Execute the retm instruction Restore R0 from address 0x0000001C Restore the PC from address 0x00000018 Processing in hardware Return to previous operating mode Jump to the PC address Figure II.5.6.3.1 Processing Flow when MMU Exception Occurs S1C33401 TECHNICAL MANUAL EPSON II-5-15 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.7 Details of the Control Registers Table II.5.7.1 List of MMU Registers Address 0x00048320 0x00048322 0x00048324 0x00048326 0x00048328 0x0004832A 0x0004832C 0x0004832E 0x00048330 0x00048332 0x00048334 Size Register name Function 16 Controls the entire MMU MMU Control Register (pMMU_CNTL) 16 Specifies way and entry numbers, and indicates status MMU Entry Register (pMMU_ENTRY) 16 Specifies DATA part translation address MMU 4KB Data Address Register (pMMU_ADR_4K) (used only for 4KB per page) 16 Specifies DATA part translation address MMU Common Data Address Register (pMMU_ADR_COM) (common to 4KB/64KB per page) 16 Sets TAG part comparison address MMU TAG Address Register (pMMU_TAD_ADR) MMU Page Setting Register (pMMU_PAGE_SETUP) 16 Specifies TAG part control bits 16 Controls TLB read/write TLB Control Register (pMMU_TLB_CNTL) 16 MMU exception status MMU Exception Status Register (pMMU_EXCP_STAT) 16 16 low-order logical address bits MMU Exception Address Register 1 (pMMU_EXP_ADR) when MMU exception occurred 16 16 high-order logical address bits MMU Exception Address Register 2 when MMU exception occurred 16 6-bit LRU data MMU LRU Register (pMMU_LRU) The following describes each MMU control register. The MMU control registers are mapped into the 16-bit device area from 0x48320 to 0x48334, and can be accessed in units of half-words or bytes. Note: When setting the MMU control registers, be sure to write a 0, and not a 1, for all "reserved bits." II-5-16 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48320: MMU Control Register (pMMU_CNTL) Register name Address MMU control register (pMMU_CNTL) Bit Name 0048320 D15-13 - D12 MRUWP (HW) D11-9 - D8 64KMD D7-5 - D4 ASIDMIX D3-1 - D0 MEN Function reserved MMU register user write protect reserved Page size select reserved Entry number generation mode reserved MMU enable I Setting - 1 Protect 0 Write enabled - 1 64KB 0 4KB - 1 ASID mixed 0 VA only - 1 Enabled 0 Disabled Init. R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. D[15:13] Reserved D12 MRUWP: MMU Register User Write Protect Bit Enables/disables write to the MMU registers in user mode. 1 (R/W): Disable write 0 (R/W): Enable write (default) II Even if this bit is 1, the MMU registers can always be accessed for write operation in supervisor mode. To set up the MMU registers in user mode, reset this bit by writing a 0 in supervisor mode. D[11:9] Reserved D8 64KMD: Page Size Select Bit Sets a page size. 1 (R/W): 64KB per page 0 (R/W): 4KB per page (default) D[7:5] Reserved D4 ASIDMIX: Entry Number Generation Mode Bit Specifies whether to combine the address and ASID to generate an entry number. 1 (R/W): Combine 0 (R/W): Do not combine (default) MMU When this bit is set to 1, the 4-bit field in the logical address that indicates an entry number (i.e., VA[15:12] for 4KB per page, VA[19:16] for 64KB per page) is combined with ASID to generate an entry number. This method helps increase the hit rate when using multiple virtual spaces. When this bit is 0, only VA is used to generate an entry number. D[3:1] Reserved D0 MEN: MMU Enable Bit Enables the MMU. 1 (R/W): Enable 0 (R/W): Disable (default) To use the MMU, set this bit to 1. At the same time, the MMUENx bit in the HBCU register that sets block `x' (x = 0-7) in which the MMU is used must also be set to 1. MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2*x) S1C33401 TECHNICAL MANUAL EPSON II-5-17 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48322: MMU Entry Register (pMMU_ENTRY) Register name Address Bit Name 0048322 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 REPWAY3 REPWAY2 REPWAY1 REPWAY0 HITWAY3 HITWAY2 HITWAY1 HITWAY0 ENT3 ENT2 ENT1 ENT0 WAY3 WAY2 WAY1 WAY0 MMU entry register (pMMU_ENTRY) Function Replace Way number Hit Way number Setting 1 1 1 1 1 1 1 1 Way 3 Way 2 Way 1 Way 0 Way 3 Way 2 Way 1 Way 0 Entry number setting Way number setting 1 1 1 1 Way 3 Way 2 Way 1 Way 0 Init. R/W 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 to 15 0 0 0 0 - - - - 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R R R/W R/W D[15:12] REPWAY[3:0]: Replace Way Number Bits Indicates the way to be replaced as determined from the LRU value. (Default: 0b0001) The four bits REPWAY3 to REPWAY0 correspond to ways 3 through 0, respectively, with the bit for the way to be replaced set to 1. If an MMU miss exception occurs, read these four bits to confirm the way to be replaced. Writing to these four bits has no effect. D[11:8] HITWAY[3:0]: Hit Way Number Bits Indicates the way that made a hit when any cause of MMU exception occurs. (Default: 0b0000) The four bits HITWAY3 to HITWAY0 correspond to ways 3 through 0, respectively, with the bit for the way that made a hit set to 1. For a multi-hit exception, the bits for all ways that made a hit are set to 1. Writing to these four bits has no effect. D[7:4] ENT[3:0]: Entry Number Setting Bits When setting or reading the content of the TLB, these bits are used to set the entry number (0 to 15) in the TLB. (Default: 0b0000) If any cause of exception occurs, the entry that was accessed at that point is automatically set. However, these bits have no effect for ASID exceptions. D[3:0] WAY[3:0]: Way Number Setting Bits When setting or reading the content of the TLB, these bits are used to set the way number in the TLB. (Default: 0b0000) If any cause of exception occurs, the way to be replaced (same information as REPWAY[3:0]) is set. If there is no cause of exception that occurred, the content set in these bits is read out directly as is. The four bits WAY3 to WAY0 correspond to ways 3 through 0, respectively. When specifying any way, always be sure to set one bit at a time. If two or more bits are set before writing to the TLB, the same information will be written to all specified ways. II-5-18 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48324: MMU 4KB Data Address Register (pMMU_ADR_4K) 0x48326: MMU Common Data Address Register (pMMU_ADR_COM) Register name Address MMU 4KB data address register (pMMU_ADR_4K) 0048324 (HW) Name Bit D15 D14 D13 D12 D11-0 MMU common 0048326 D15 D14 (HW) data address D13 register D12 (pMMU_ADR_COM) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CA15 CA14 CA13 CA12 - CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 Function Setting Translation physical address A[15:12] (effective in 4KB/page mode) 0x0 to 0xF reserved Translation physical address A[31:16] - 0x0 to 0xFFFF Init. R/W 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I Remarks R/W - 0 when being read. R/W II MMU These two registers are used to save the translation address to be written to or read from the DATA part of the TLB. (Default: 0x00000) To set up the DATA part of the TLB, write the physical address derived from translation to these registers and set DATWR (D0/0x4832C) to 1. To confirm the DATA part of the TLB, set DATRD (D1/0x4832C) to 1 and read the physical address loaded in these registers. The entry/way set in the MMU Entry Register (0x48322) is the target from or to which the address is read or written. D[15:12]/0x48324 CA[15:12]: Translation Physical Address A[15:12] Contains the 4 low-order bits of the physical address. These four bits are only used for 4KB per page, and have no effect for 64KB per page. D[15:0]/0x48326 CA[31:16]: Translation Physical Address A[31:16] Contains the 16 high-order bits of the physical address. These 16 bits are used for both 4KB per page and 64KB per page. S1C33401 TECHNICAL MANUAL EPSON II-5-19 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48328: MMU TAG Address Register (pMMU_TAD_ADR) Register name Address Bit 0048328 MMU TAG (HW) address register (pMMU_TAD_ADR) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D[15:0] Name CVA31 CVA30 CVA29 CVA28 CVA27 CVA26 CVA25 CVA24 CVA23 CVA22 CVA21 CVA20 CVA19 CVA18 CVA17 CVA16 Function Comparison address A[31:16] in TAG Setting 0x0 to 0xFFFF Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W CVA[19:16] is not effective in 64KB/page mode CVA[31:16]: Comparison Address These bits are used to save the comparison address to be written to or read from the TAG part of the TLB. (Default: 0x0000) This is the address compared with the logical address (or ASID + logical address) sent from the HBCU. For 64KB per page, CVA[19:16] (D[3:0]) has no effect. To set up the TAG part of the TLB, write the comparison address to this register and information on the page control bits to the MMU Page Setting Register (0x4832A), then set TAGWR (D4/0x4832C) to 1. To confirm the comparison address set in the TAG part of the TLB, set TAGRD (D5/0x4832C) to 1, then read the comparison address loaded in this register. The entry/way set in the MMU Entry Register (0x48322) is the target from or to which the address is read or written. II-5-20 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x4832A: MMU Page Setting Register (pMMU_PAGE_SETUP) Register name Address Bit Name 004832A D15-9 - MMU page D8 ASIDUSE (HW) setting register D7 - (pMMU_PAGE D6 WP _SETUP) D5 UMP D4 ACP D3 CE D2 VLD D1 ACC D0 DTY Function reserved Use of ASID reserved Write protect User mode access protect Access protect Cache enable TLB entry valid bit Page access bit Dirty bit Setting Init. R/W - 1 Used 0 Not used - 1 1 1 1 1 1 1 Protected Protected Protected Enabled Valid Accessed Written 0 0 0 0 0 0 0 Enabled Enabled Enabled Disabled Invalid Not accessed Not written - 0 - 0 0 0 0 0 0 0 I Remarks - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W This register is used to save the status of page control bits to be written to or read from the TAG part of the TLB. To set up the TAG part of the TLB, write information on the page control bits to this register and the comparison address to the MMU TAG Address Register (0x48328), then set TAGWR (D4/0x4832C) to 1. To confirm the status of page control bits in the TAG part of the TLB, set TAGRD (D5/0x4832C) to 1, then read the status of each bit set in this register. The entry/way set in the MMU Entry Register (0x48322) is the target from or to which status is read or written. D[15:9] Reserved D8 ASIDUSE: Use of ASID Bit This bit is used to set or confirm the ASIDUSE bit in the TAG part of the TLB. 1 (R/W): Use ASID 0 (R/W): Do not use ASID (default) MMU ASID processing is controlled by the control bits in the HBCU. The ASIDUSE bit in the TAG part of the TLB is used to confirm whether this bit is consistent with the ASID enable/disable information sent from the HBCU. If inconsistent, even when the compared addresses match, an MMU miss is assumed. D7 Reserved D6 WP: Write-Protect Bit This bit is used to set or confirm the WP bit in the TAG part of the TLB. 1 (R/W): Write protect 0 (R/W): Write enable (default) The WP bit specifies to write-protect a page. When the WP bit in the TAG part is set to 1, the relevant page is protected against write operation in both supervisor and user modes, so that an attempt to write to said page generates an MMU write protect exception. D5 UMP: User Mode Access-Protect Bit This bit is used to set or confirm the UMP bit in the TAG part of the TLB. 1 (R/W): Disable access in user mode 0 (R/W): Enable access in user mode (default) The UMP bit sets a supervisor mode-only page. When the UMP bit in the TAG part is set to 1, the relevant page is disabled against access in user mode (for both read and write), so that an attempt to access said page generates an MMU user mode protect exception. D4 ACP: Access-Protect Bit This bit is used to set or confirm the ACP bit in the TAG part of the TLB. 1 (R/W): Disable access 0 (R/W): Enable access (default) The ACP bit specifies to protect a page. When the ACP bit in the TAG part is set to 1, the relevant page is disabled against access in both supervisor and user modes (for both read and write), so that an attempt to access said page generates an MMU access protect exception. S1C33401 TECHNICAL MANUAL II EPSON II-5-21 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) D3 CE: Cache Enable Bit This bit is used to set or confirm the CE bit in the TAG part of the TLB. 1 (R/W): Use cache 0 (R/W): Do not use cache (default) When the CE bit in the TAG part is set to 1 with the cache enabled in both HBCU and CCU, the HBCU uses the cache when accessing a page for read/write operation. D2 VLD: TLB Entry Valid Bit This bit is used to set or confirm the VLD bit in the TAG part of the TLB. 1 (R/W): Valid entry 0 (R/W): Invalid entry (default) When the VLD bit in the TAG part is set to 1, the relevant entry is used as valid. When the VLD bit is 0, the entry is not used. D1 ACC: Page Access Bit This bit is used to set or confirm the ACC bit in the TAG part of the TLB. 1 (R/W): Accessed 0 (R/W): Not accessed (default) The ACC bit in the TAG part is set to 1 when the relevant page is accessed (for read or write). It can be set to 0 or 1 by this bit as required. D0 DTY: Dirty Bit This bit is used to set or confirm the DTY bit in the TAG part of the TLB. 1 (R/W): Written to page 0 (R/W): Not written to page (default) The DTY bit in the TAG part is set to 1 when data is written to the relevant page. It can be set to 0 or 1 by this bit as required. II-5-22 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x4832C: TLB Control Register (pMMU_TLB_CNTL) Register name Address Bit Name 004832C D15-14 - TLB control D13 LRURD (HW) register D12 LRUWR (pMMU_TLB_CNTL) D11-9 - D8 FLUSH D7-6 - D5 TAGRD D4 TAGWR D3-2 - D1 DATRD D0 DATWR Function Setting - reserved LRU entry read LRU entry write reserved TLB-flush control reserved TAG entry read TAG entry write reserved DATA entry read DATA entry write 1 Read 1 Write 0 Invalid 0 Invalid - 1 Clear V bits 0 - 1 Read 0 1 Write 0 - 1 Read 0 1 Write 0 I Init. R/W Invalid Invalid Invalid Invalid Invalid - 0 0 - 0 - 0 0 - 0 0 - W W - W - W W - W W Remarks 0 when being read. This register is used to set up and read out the TLB and LRU. Before read/write control by this register can be exercised, the following settings are required: II 1. Specifying the entry/way (when reading or writing) Use the MMU Entry Register (0x48322) to specify. 2. Setting the content to be written to the TLB in the registers below (when writing TLB) TAG part comparison address: MMU TAG Address Register (0x48328) TAG part page control bits: MMU Page Setting Register (0x4832A) DATA part physical address: MMU 4KB Data Address Register (0x48324) For 4KB per page only MMU Common Data Address Register (0x48326) MMU When reading the TLB, read information is loaded in these registers. 3. Setting the content to be written to the LRU in the register below (when writing LRU information) 6-bit LRU data: MMU LRU Register (0x48334) When reading the LRU, read information is loaded in this register. Note: TLB/LRU initialization or the alteration of TLB/LRU content pursuant to the occurrence of an MMU exception should always be performed in an area where the MMU is not used. D[15:14] Reserved D13 LRURD: LRU Entry Read Bit Reads LRU information from the specified entry. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the LRU information in the entry specified in 1 above is read out, and set in the MMU LRU Register (0x48334). D12 LRUWR: LRU Entry Write Bit Writes LRU information to the specified entry. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the information set in the MMU LRU Register (0x48334) in 3 above is written to the entry specified in 1 above. D[11:9] Reserved S1C33401 TECHNICAL MANUAL EPSON II-5-23 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) D8 FLUSH: TLB Flush Control Bit Clears all VLD (Valid) bits to invalidate the entire TLB. 1 (W): Clear all VLD bits in entire TLB 0 (W): Has no effect 0 (R): Always 0 when read (default) D[7:6] Reserved D5 TAGRD: TAG Entry Read Bit Reads out information from the TAG part of the TLB. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the TAG part information in the entry/way specified in 1 above is read out and set in the TAG part register listed in 2 above. D4 TAGWR: TAG Entry Write Bit Writes information to the TAG part of the TLB. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the information set in the TAG part register in 2 above is written to the TAG part in the entry/way specified in 1 above. D[3:2] Reserved D1 DATRD: DATA Entry Read Bit Reads information from the DATA part of the TLB. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the DATA part information in the entry/way specified in 1 above is read out, and set in the DATA part register listed in 2 above. D0 DATWR: DATA Entry Write Bit Writes information to the DATA part of the TLB. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When this bit is set by writing a 1, the information set in the DATA part register in 2 above is written to the DATA part in the entry/way specified in 1 above. II-5-24 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x4832E: MMU Exception Status Register (pMMU_EXCP_STAT) Register name Address Bit Name MMU exception 004832E D15-13 - D12 ASMIR (HW) status register D11 ASRDWR (pMMU_EXCP D10 ASSVM _STAT) D9 ASIRDA D8 ASASID D7 EXPWRP D6 EXPUMP D5 EXPACP D4 EXPASID D3 EXPMLT D2 EXPMISS D1 - D0 EXP Function reserved Mirrored access status Read/write status Supervisor/user mode status Instruction fetch/data R/W status ASID status MMU write-protect exception MMU user-mode-protect exception MMU access-protect exception ASID exception MMU multi-hit exception MMU miss exception reserved MMU exception (all causes) Setting Init. R/W - 1 1 1 1 1 1 1 1 1 1 1 Mirrored Read Supervisor Instruction Used Occurred Occurred Occurred Occurred Occurred Occurred 0 0 0 0 0 0 0 0 0 0 0 Not mirrored Write User Data Not used Not occurred Not occurred Not occurred Not occurred Not occurred Not occurred - 1 Occurred 0 Not occurred - 0 0 0 0 0 0 0 0 0 0 0 - 0 I Remarks - 0 when being read. R R R R R R/W R/W R/W R/W R/W R/W - 0 when being read. R/W II D[15:13] Reserved D12 ASMIR: Mirrored Access Status Bit Indicates whether the latest MMU access was made in a mirroring-enabled state. 1 (R): Mirrored 0 (R): Not mirrored (default) 1/0 (W): Has no effect MMU D11 ASRDWR: Read/Write Status Bit Indicates whether read or write operation was performed in the latest MMU access. 1 (R): Read 0 (R): Write (default) 1/0 (W): Has no effect D10 ASSVM: Supervisor/User Mode Status Bit Indicates whether supervisor or user mode was used for the latest MMU access made. 1 (R): Supervisor mode 0 (R): User mode (default) 1/0 (W): Has no effect D9 ASIRDA: Instruction Fetch/ Data Read-Write Status Bit Indicates whether instruction fetch or data read/write operation was performed in the latest MMU access. 1 (R): Instruction fetch 0 (R): Data read/write (default) 1/0 (W): Has no effect D8 ASASID: ASID Status Bit Indicates whether ASID was used in the latest MMU access. 1 (R): ASID used 0 (R): ASID not used (default) 1/0 (W): Has no effect D7 EXPWRP: MMU Write-Protect Exception Status Bit Indicates the status of whether an MMU write protect exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set when an attempt was made to write to a write-protected page (TAG part WRP bit = 1). S1C33401 TECHNICAL MANUAL EPSON II-5-25 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) D6 EXPUMP: MMU User-Mode-Protect Exception Status Bit Indicates the status of whether an MMU user mode protect exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set when an attempt was made to read or write to a user mode-protected page (TAG part UMP bit = 1) in user mode. D5 EXPACP: MMU Access-Protect Exception Status Bit Indicates the status of whether an MMU access protect exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set when an attempt was made to read or write to an access-protected page (TAG part ACP bit = 1) in either supervisor or user mode. D4 EXPASID: ASID Exception Status Bit Indicates the status of whether an ASID exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This exception is provided (when using multiple virtual spaces) to detect whether a process has accessed an address space exceeding the 64KB boundary. This bit is set when the logical address VA[31:26] and the logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) do not match as compared before VA[31:26] is replaced with ASID. D3 EXPMLT: MMU Multi-Hit Exception Status Bit Indicates the status of whether an MMU multi-hit exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set when two or more ways make a hit in address comparison. D2 EXPMISS: MMU Miss Exception Status Bit Indicates the status of whether an MMU miss exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set when no matching ways are found in address comparison. D1 Reserved D0 EXP: MMU Exception Status Bit Indicates that an MMU exception occurred. 1 (R/W): Occurred 0 (R/W): Not occurred (default) This bit is set to 1 when one of exception status bits in D[7:2] was set to 1. Conversely, when this bit is 0, D[7:2] has no effect. Notes: * The exception status bits (D[7:2] and D0) are not automatically cleared. Always be sure to clear all status bits by writing a 0 in the exception handling routine. If these bits remain set when the exception handler routine is terminated by the retm instruction, the MMU exception will reoccur. * There is only one signal line to forward MMU exception processing requests to the CPU. Therefore, this signal line is commonly used for the six causes of exceptions. If any MMU exception occurs, read the exception status bits in this register (D[7:2] and D0) to determine the cause of the exception that occurred. If two or more causes of exceptions occur at the same time, all corresponding status bits are set to 1. * The MMU is disabled during MMU exception handling (PSR register ME bit = 1). Even if the MMU exception handler routine is located in a block where the MMU is enabled for use, no address translation is performed and logical addresses are handled directly as physical addresses. II-5-26 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48330: MMU Exception Address Register 1 (pMMU_EXP_ADR) 0x48332: MMU Exception Address Register 2 Register name Address Bit MMU exception 0048330 (HW) address register 1 (pMMU_EXP_ADR) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MMU exception 0048332 (HW) address register 2 Name EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0 EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 Function Exception occurred logical address (low-order 16 bits) Exception occurred logical address (high-order 16 bits) Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I Remarks R II R MMU These registers are used to save the logical address being sent from the HBCU (while being accessed by the CPU) when an exception occurred. (Default: 0x00000000) D[15:0]/0x48330 EA[15:0]: Exception Occurred Logical Address (low-order 16 bits) These are the 16 low-order bits of the logical address, equivalent to address[15:0] output by the HBCU. D[15:0]/0x48332 EA[31:16]: Exception Occurred Logical Address (high-order 16 bits) These are the 16 high-order bits of the logical address, equivalent to address[31:16] output by the HBCU. S1C33401 TECHNICAL MANUAL EPSON II-5-27 II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) 0x48334: MMU LRU Register (pMMU_LRU) Register name Address MMU LRU register (pMMU_LRU) Bit Name 0048334 D15-6 - D5 LRU5 (HW) D4 LRU4 D3 LRU3 D2 LRU2 D1 LRU1 D0 LRU0 Function reserved LRU information Setting - Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W D[15:6] Reserved D[5:0] LRU[5:0]: LRU Information These bits are used to save the LRU information to be written to or read from the specified entry. (Default: 0x0000) To set LRU information, write the information to this register, then set LRUWR (D12/0x4832C) to 1. To confirm the LRU information set in an entry, set LRURD (D13/0x4832C) to 1, then read the data loaded in this register. The entry set in the MMU Entry Register (0x48322) is the target from or to which the LRU information is read or written. When an MMU exception occurs, the LRU information of the entry in which the exception occurs is loaded to this register. II-5-28 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) II.5.8 Precautions I * To use the MMU in block `x' (x = 0-7), the corresponding MMUENx bit (D4) in the Block x Configuration Register (0x48302 + 2*x) or UMDMEN bit (D1) in the Address Control Register (0x48300) in the HBCU must be set to 1. Moreover, the MEN bit (D0) of the MMU Control Register (0x48320) in the MMU must also be set to 1. Before the MMU can be used, the HBCU and MMU should both be set. After writing data to the register, read the register to make sure that the contents have been set properly. * To use the MMU in combination with the cache, TLB setup in the MMU is also required, in addition to the settings above. To enable use of the cache for a page, set the corresponding CE bit (cache enable) in the TAG part of the TLB to 1. When the MMU is to be used, the CE bit for the relevant page is checked to determine whether the cache is enabled. Whether the cache is enabled in the CCU and HBCU is then checked. II * TLB initialization or the alteration of TLB content pursuant to occurrence of an MMU exception should always be performed in an area where the MMU is not used. * The MMU is disabled during MMU exception handling (PSR register ME bit = 1). Note that even if the MMU exception handler routine is located in a block where the MMU is enabled for use, no address translation is performed and logical addresses are handled directly as physical addresses. * When setting up the TLB, make sure that no physical addresses derived from address translation will fall within the lower 4MB (i.e., areas 0 to 6). Moreover, when mirroring is enabled in the HBCU (by setting MIR (D0/0x48300) to 1), the upper 3GB (1GB x 3) in the 4GB space becomes a mirror area of each corresponding lower 1GB. In this case, also make sure that no physical addresses derived from address translation by the TLB will fall within the lower 4MB in each 1GB area. Note that the lower 4MB in each 1GB mirror are excluded from the object of mirroring and cannot be mirrored. For details about mirroring, see Section II.4, "High-Speed Bus Control Unit (HBCU)." * Be aware that external access is performed if the physical address translated by the MMU is an address in the internal RAM area (area 0/3), internal I/O area (area 1), or debug area (area 2). The internal area will not be accessed. For example, if the physical address translated by the MMU is address 0x0, the internal RAM is not accessed and external access to address 0x0 is performed. S1C33401 TECHNICAL MANUAL EPSON II-5-29 MMU II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU) THIS PAGE IS BLANK. II-5-30 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6 Cache Control Unit (CCU) I II.6.1 Overview of the CCU The C33 ADV Core Block contains a Cache Control Unit (CCU) that includes an 8KB cache by physical addresses. The CCU is a mixed type of instruction/data cache, and uses a 4-way set-associative method. The following outlines the main features of the CCU. * Physical address cache * Uses a 4-way set-associative method, with 128 entries per way, for a total of 512 lines supported. II * Each line is comprised of 4 words (16 bytes). * With the 4GB logical address space divided into eight 512MB blocks, instruction and data caches can be enabled or disabled independently for each block. * The method of writing to the cache can be selected from write-back and write-through modes. * A function to lock a specified way is provided. CCU * The interrupt handler routine can be locked according to interrupt priority level. * A forwarding function is included to transfer necessary instructions or data immediately to the CPU even during refill. * A unit of memory area in the cache is called a line; a set of four lines sharing address [10:4] is called an entry. Four lines in one entry are physically referenced by Ways 0 to 3, whereas four words in one line are referenced by W0-3. S1C33401 TECHNICAL MANUAL EPSON II-6-1 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.2 Configuration of the Cache The cache in the C33 ADV Core Block is a 4-way, set-associative cache. The cache has 128 entries, with four lines (ways) per entry. Since 16 bytes (4 words) of data can be saved in one line, the cache has a maximum storage capacity of 8KB. Figure II.6.2.1 shows the general configuration of the cache. TAG LRU DATA Entry 0 Entry 1 Entry 2 Entry 3 : : W3 : : W2 W1 W0 : : Entry 126 Entry 127 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Figure II.6.2.1 General Configuration of the Cache II.6.2.1 TAG Part and DATA Part Each line consists of a TAG part and a DATA part, as shown in Figure II.6.2.1.1. The TAG part consists of 24 bits, and includes a 21-bit comparison address, D (dirty) bit, V (valid) bit, and L (lock) bit. D bit: Set to 1 by writing to the cache. However, this is effective only when writing to the cache is performed in write-back mode, so that if the cache is written to in write-through mode, the D bit remains 0. V bit: Set to 1 (valid) when the cache is refilled, and reset to 0 (invalid) when flushed. L bit: Set to 1 when the entry is locked. A locked entry is not refilled. The DATA part is comprised of 4 words (16 bytes). When only the instruction cache is enabled in the Cache Configuration Register (0x48340), only instructions are saved in the DATA part. Conversely, when only the data cache is enabled, only data is saved in the DATA part. Instruction and data caches can both be enabled at the same time. TAG L V D DATA CPA[31:11] W3 W2 W1 W0 21 bits 32 bits 32 bits 32 bits 32 bits 24 bits L V D Lock bit Valid bit Dirty bit 0 (default) = Not locked 0 (default) = Invalid 0 (default) = Not updated 128 bits 1 = Locked (The L bit is provided only for Ways 1 and 3.) 1 = Valid 1 = Updated CPA[31:11] Comparison physical address Word (32-bit) data. 4 words/line W3-W0 Figure II.6.2.1.1 Structure of Cache Lines II.6.2.2 LRU Part Since the cache is a 4-way configuration, there are four lines of 4-word data with the same entry number. In case of a cache miss, one of the four ways of cache must be selected and replaced. The LRU part holds the number of the way to be replaced. Although LRU (Least Recently Used) is the algorithm used to select the way that was least recently accessed, a pseudo-LRU algorithm with a simplified circuit configuration is adopted for the cache in the C33 ADV Core. II-6-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.3 Settings and Operation of the Cache I II.6.3.1 Enabling the Cache When initially reset, the cache is disabled. To use the cache, the following settings are required: 1. Setting up the HBCU The HBCU manages the 4GB logical address space separately in eight 512MB blocks. Either or both the instruction and data caches can be enabled or disabled for each block individually. To use the data cache in block `x', set the DCx bit (D1) in the HBCU Block x Configuration Register to 1 (= enable). To use the instruction cache, set the ICx bit (D0) in the same register to 1. II DCx: Block x Data Cache Enable Bit in the Block x Configuration Register (D1/0x48302 + 2*x) ICx: Block x Instruction Cache Enable Bit in the Block x Configuration Register (D0/0x48302 + 2*x) For details about the HBCU, see Section II.4, "High-Speed Bus Control Unit (HBCU)." Even though either or both caches are enabled in the CCU, the caches cannot be used unless enabled in the HBCU as described above. 2. Setting up the CCU To use the data and instruction caches, set the DC (D1/0x48340) and IC (D0/0x48340) in the CCU to 1, respectively. DC: Data Cache Enable Bit in the Cache Configuration Register (D1/0x48340) IC: Instruction Cache Enable Bit in the Cache Configuration Register (D0/0x48340) 3. Setting up the MMU (only when using the MMU) To use the MMU in combination with the cache, the TLB in the MMU must also be set up, in addition to the settings in 1 and 2 above. When setting up the TLB for a page requiring cache use, set the CE bit (cache enable) in the TAG part to 1. CE: Cache Enable Bit in the MMU Page Setting Register (D3/0x4832A) II.6.3.2 Address Comparison and Cache Hit/Miss Since the cache in the C33 ADV Core Block is a physical cache, the addresses handled by the cache are physical addresses, and not logical addresses. Seven bits of PA[10:4] in the physical address (hereafter PA) represent an entry number. PA[31:11] contains the comparison address to be compared with the physical address for comparison use (CPA[31:11]) set in the TAG part for four ways of cache in the entry selected by PA[10:4]. For cache access performed by using the MMU in combination with the cache, the logical address received from the CPU is translated into a physical address (hereafter MPA) by the MMU before being compared. Two bits of PA[3:2] are a block offset used to select one of four words in the DATA part. S1C33401 TECHNICAL MANUAL EPSON II-6-3 CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) Physical address PA[31:0] from the HBCU 31 11 10 PA[31:11] PA[10:4] Comparison address Entry No. WO BO WO: Word offset BO : Byte offset DATA TAG LRU W3 Entry 0 Entry 1 Entry 2 : : Entry 127 W1 W2 W0 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 MUX Address from MMU 4 3 2 1 0 PA[3:2] PA[1:0] CMP0 CMP1 CMP2 CMP3 Way selection MUX Hit D[31:0] Hit data Figure II.6.3.2.1 Operation of the Entire Cache The following describes cache operation until a cache hit or miss can be determined. 1. An entry number (0 to 127) is generated from PA[10:4]. 2. Information on four ways of cache are read from the TAG part of the selected entry. At the same time, the word data indicated by the block offset PA[3:2] (i.e., one of W0 to W3) for four ways of cache are read from the DATA part. 3. When not using the MMU CPA[31:11] in the TAG part for each way of cache and PA[31:11] are compared. When using the MMU CPA[31:11] is compared with the address derived from translation by the MMU, instead of PA[31:11] output by the CPU. The compared address varies depending on page settings in the MMU, as shown below. For 4KB per page: CPA[31:11] and MPA[31:12] + PA11 are compared. For 64KB per page: CPA[31:11] and MPA[31:16] + PA[15:11] are compared. 4. When a matching way is found in step 3 and the V bit in the TAG part is 1 (= valid), a cache hit is assumed. The way that made the hit is determined here. When no matching ways are found in step 3, a cache miss is assumed. For example, when PA[10:4] = 0b0000010 and PA[3:2] = 0b10, and Way 0 is a hit, W2 in Way 0 in entry 2 is accessed for read or write operation. II-6-4 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.3.3 Read Operation I The following describes cache operation when a cache hit or miss occurs during read operation. For a cache hit The 32-bit data in the "hit" way is transferred to the CPU, with LRU information in the relevant entry being updated at the same time. For a cache miss No instructions or data are transferred to the CPU. In case of a cache miss, the way of cache to be replaced (i.e., least recently accessed way) is determined from the current LRU information. Updating the DATA part for the way of cache thus determined is called "refill." A refill is performed in units of 4 words (16 bytes), with the target instruction or data read out from relevant external memory and written to the cache. At the same time, the target instruction or data is transferred to the CPU, with the LRU information updated. Although a refill is performed for all 4 words, the instruction or data needed by the CPU is transferred to the CPU immediately after being read out (before refill is completed). (This is called the "forwarding" function.) When the D bit in the TAG part is 1 in write-back mode, it means that data is being written to the cache. In this case, a write-back operation is inserted to synchronize cache and memory contents because said contents are not synchronous. II.6.3.4 Write Operation There are two write operation modes: write-through and write-back. These write modes are selected to set the WBEN bit (D4/0x48340) in the CCU and the WRMDx bit provided for each block in the HBCU. WBEN: Write-Back Enable Bit in the Cache Configuration Register (D4/0x48340) WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2*x) Table II.6.3.4.1 Write Mode Settings WBEN WRMDx Write mode 1 1 0 0 1 0 1 0 Write-back mode Write-through mode Write-through mode Write-through mode Write operation and the write modes are only effective for the data cache, and have no effect on the instruction cache. Write-through mode In write-through mode, data is written to the cache when a cache write occurs, and at the same time written to the relevant external memory. Therefore, data integrity between the cache and memory is always guaranteed. For a cache hit A write cycle is issued for both cache and external memory. The LRU information is also updated. For a cache miss In case of a cache miss, data is not written to the cache, but only written to external memory. In this case, the LRU information is not updated because no data is written to the cache. Also a refill operation is not performed. S1C33401 TECHNICAL MANUAL EPSON II-6-5 II CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) Write-back mode In write-back mode, data is only written to the cache when a cache write occurs, and not written to the relevant external memory. Therefore, high-speed execution is possible because only the cache is accessed for a data write operation. When data is written to the cache in write-back mode, the D bit in the TAG part of the relevant entry is set to 1, indicating that the cache and relevant external memory are not synchronous. For a cache hit Data is only written to the cache, and the D bit in the TAG part for the "hit" way of cache is set to 1. The LRU information is also updated. For a cache miss In case of a cache miss, the way of cache to be replaced is first determined from the current LRU information and the D bit in the TAG part for that way examined. When the D bit = 0, a refill operation is performed directly on the cache since data in that way of cache is consistent with external memory. When the D bit = 1, refill and write-back operations are performed since the cache data is inconsistent with the external memory. The cache has a dedicated 4-word buffer for write-back use, and a write-back operation is performed in the manner described below. 1. The 4-word data to be written back (one to be replaced) is transferred to the dedicated buffer. 2. The way of cache to be replaced is refilled. At this time, the data read out from external memory is replaced with the write data before being written to the cache. 3. The content of the dedicated write-back buffer is written back to external memory. In step 3 (after completing step 2 above), the cache is ready for use. Therefore, the cache can be accessed while data is written from the buffer back to external memory. II.6.3.5 Flush Flush means invalidating a cache entry. There are two types: cache flush and lock flush. For details about lock flush, see Section II.6.4, "Lock Function." Cache flush In this type of flush, the V and D bits in the TAG part for all valid lines of the cache are cleared to 0 to invalidate the lines and initialize the LRU in all entries. Even if there is any line whose D bit = 1, no data is written back. The L bit in the TAG part is cleared to 0, so that all lines are unlocked. The content of the DATA part is not cleared. To execute a cache flush, write a 1 to CFLSH (D8/0x48346). CFLSH: Cache-Flush Control Bit in the Cache Control Register (D8/0x48346) Before flushing the cache, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable the cache. The D bits are also cleared by a cache flush. Therefore, when the cache is used in write-back mode, always be sure to check the D bit status of all entries and perform a software write-back operation (described later) before flushing the cache. II-6-6 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.3.6 Setting Up the Cache I The cache can be set up or read out via the CCU control registers. Therefore, it is possible to flush only a specific entry of the cache. TAG part For read The TAG part in a specific cache entry can be read out following the procedure described below. 1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way. For reading the TAG part, WO[1:0] (D[3:2]/0x48348) that specifies a word offset is ignored. ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348) WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342) II 2. Write a 1 to TAGRD (D5/0x48346). TAGRD: TAG Entry Read Bit in the Cache Control Register (D5/0x48346) As a result, information on the TAG part in the specified cache entry will be loaded into the Cache Entry Control Register (0x48344) and Cache TAG Address Registers 1 and 2 (0x48348 and 0x4834A). 3. Read the Cache Entry Control Register (0x48344) and Cache TAG Address Registers 1 and 2 (0x48348 and 0x4834A) to get information on the TAG part in the specified cache entry. Setting up (altering settings) The procedure described below allows the settings of the TAG part in a specific cache entry to be set up or altered. 1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way. For setting the TAG part, WO[1:0] (D[3:2]/0x48348) that specifies a word offset is ignored. 2. Write the information to be set or altered with to the Cache Entry Control Register (0x48344) and Cache TAG Address Registers 1 and 2 (0x48348 and 0x4834A). 3. Write a 1 to TAGWR (D4/0x48346). TAGWR: TAG Entry Write Bit in the Cache Control Register (D4/0x48346) As a result, the TAG part in the specified cache entry will be set up or altered. DATA part For read The DATA part in a specific cache entry can be read out following the procedure described below. 1. Use ENT[6:0] (D[10:4]/0x48348), WAY[1:0] (D[1:0]/0x48342), and WO[1:0] (D[3:2]/0x48348) to specify an entry, a way, and a word offset. ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348) WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342) WO[1:0]: Word Offset in the Cache TAG Address Register 1 (D[3:2]/0x48348) 2. Write a 1 to DATRD (D1/0x48346). DATRD: DATA Entry Read Bit in the Cache Control Register (D1/0x48346) As a result, the specified word data information in the specified cache entry will be loaded in Cache Data Registers 1 and 2 (0x4834C and 0x4834E). 3. Read Cache Data Registers 1 and 2 (0x4834C and 0x4834E) to get the specified word data information in the specified cache entry. S1C33401 TECHNICAL MANUAL EPSON II-6-7 CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) Setting up (altering settings) The procedure described below allows the settings of the DATA part in a specific cache entry to be set up or altered. 1. Use ENT[6:0] (D[10:4]/0x48348), WAY[1:0] (D[1:0]/0x48342), and WO[1:0] (D[3:2]/0x48348) to specify an entry, a way, and a word offset. 2. Write the information to be set or altered with to Cache Data Registers 1 and 2 (0x4834C and 0x4834E). 3. Write a 1 to the cache control register DATWR bit (D0/0x48346). DATWR: DATA Entry Write Bit in the Cache Control Register (D0/0x48346) As a result, the specified word in the specified cache entry will be updated to the set (or altered) data. II.6.3.7 Write-back in Software A specific entry in the cache can be written back to memory in software. When written back in software, the D bit in a specified entry does not matter. Cache content is written back even when the D bit = 0. Therefore, when cache content must be written back in software, always be sure to read out the TAG part to check D bit status and specify an entry whose D bit = 1 before performing a write-back operation. The following describes how to write back in software. 1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way. ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348) WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342) 2. Write a 1 to WB (D9/0x48346). WB: Write-Back Control Bit in the Cache Control Register (D9/0x48346) The above causes the specified entry in the cache to be written back to memory. When the cache is flushed, all entries are flushed regardless of the D bit status of any entry. Therefore, before flushing the cache, always be sure to check the D bit status of all entries and write back only those entries whose D bit = 1. For write-back in software, WBSTAT (D15/0x48346) may be checked to confirm whether a write-back operation is being performed. WBSTAT: Write-Back Status Bit in the Cache Control Register (D15/0x48346) When WBSTAT (D15/0x48346) = 1, it means that a write-back operation is underway; when 0, it means that a write-back operation has been completed. This bit is only effective for write-back in software. When other cache entries must be written back in succession, always be sure to monitor the status of WBSTAT (D15/0x48346) and wait until it is cleared to 0 before writing a 1 to the WB bit. Note: Be sure to disable the cache before performing a write-back operation in software. II-6-8 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.4 Lock Function I The cache in the C33 ADV Core Block has a lock function. The lock function refers to protecting a specified way in the cache where a specific program or data has been loaded (Way 1 or 3 selectable by register) against replacement in case of a cache miss. This function may be used, for example, when a specific program must be left intact as cached in the cache, without ever being replaced. The following describes the procedure for controlling the lock function. 1. Use LKWAY (D12/0x48340) to specify a way of the cache to be locked. LKWAY: Lock Way Select Bit in the Cache Configuration Register (D12/0x48340) Way 3 is selected when LKWAY (D12/0x48340) = 0; Way 1 is selected when LKWAY (D12/0x48340) = 1. 2. Specify the type of lock (instruction lock or data lock). Set IRLK (D8/0x48340) to 1 for instruction lock; set DLK (D9/0x48340) to 1 for data lock. II IRLK: Instruction-Lock Enable Bit in the Cache Configuration Register (D8/0x48340) DLK: Data-Lock Enable Bit in the Cache Configuration Register (D9/0x48340) Regardless of whether cached with instruction lock or data lock, the program or data can be used in both instruction and data caches. For example, after placing a program in the cache as data with data lock, it is possible to use the cached data as instruction cache. A dedicated lock function is provided for interrupt processing. For details, see Section II.6.5, "Lock for Interrupt Processing." 3. Write a 1 to LKSTART (D11/0x48346) to start the locking sequence. LKSTART: Lock-Start Control Bit in the Cache Control Register (D11/0x48346) Then, if the target program or data does not make a hit before the locking sequence ends, a miss is assumed and the specified way (Way 3 or 1) refilled. (When a hit is made, operation is executed without a refill.) While the specified way is being accessed, the L (lock) bit in the TAG part of the accessed entry is set to 1. When access to the same entry is attempted a number of times, the entry is overwritten, so that only the information accessed last is effective. Moreover, if the D bit in the TAG part is 1 when refilling the way, the way is written back as well. 4. When the entire program or all data to be locked has been taken into the cache, write a 0 to LKSTART (D11/ 0x48346) to end the locking sequence. After that, cache entries whose L bit = 1 are excluded from the object to be replaced due to a cache miss, and are thus protected against replacement. To unlock a locked cache entry, perform a lock flush (as described later). In the locking sequence start and end states, the specified locked way is handled internally in the chip as described below. In the lock start state: Only the locked way is the object of replacement. (In case of a cache miss, only the locked way is replaced.) In the lock end state: The locked way is excluded from the object of replacement. (In case of a cache miss, all ways but the locked way are replaced.) When any cache entry whose lock bit = 1 is accessed again during lock start, resulting in a cache miss, the locked way of the cache is replaced. In other words, the L bit has no effect during lock start. Lock flush For all cache lines whose TAG part L bit = 1, the L bit is cleared to 0 to unlock the lines. The V and D bits are not altered. Nor is the LRU initialized. To execute a lock flush, write a 1 to LKFLSH (D10/0x48346). LKFLSH: Lock-Flush Control Bit in the Cache Control Register (D10/0x48346) Before performing a lock flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable the cache. S1C33401 TECHNICAL MANUAL EPSON II-6-9 CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.5 Lock for Interrupt Processing To support control of cache operation for interrupt processing, a dedicated register called the Interrupt Lock Setup Register (0x48350) is provided. This register allows controlling whether to lock the interrupt handler routine by interrupt priority level. Each bit in LKIL[15:0] (D[15:0]) of the Interrupt Lock Setup Register (0x48350) corresponds to one interrupt priority level. For example, LKIL15 corresponds to interrupt priority level 15 (IL[3:0] = 15). To lock any interrupt priority level, set the corresponding bit in this register to 1. However, before this can be achieved, the area where the interrupt routine is located must be enabled for cache use. If the area is disabled against cache use, this function has no effect. Although only Way 1 and both the instruction and data caches can be locked for interrupt processing, this interrupt processing lock function is functionally the same as the lock function described in the preceding section. This function does not need to control LKWAY (D12/0x48340), IRLK (D8/0x48340), DLK (D9/0x48340), and LKSTART (D11/0x48346). The interrupt processing lock function works according to the following rules: * The function is in the interrupt lock start state when the value of the PSR register IL[3:0] bits and LKIL[15:0] (D[15:0]) in the Interrupt Lock Setup Register (0x48350) match. During interrupt lock start, only Way 1 is the object of replacement. If the target program or data does not make a hit, Way 1 is refilled and the TAG part L bit set to 1. (When a hit is made, operation is executed without a refill.) * If the IL[3:0] value and LKIL[15:0] (D[15:0]/0x48350) do not match, the function enters the interrupt lock end state. In this state, Way 1 in the locked entry is excluded from the object of replacement, and thus protected against subsequent replacement. When this function is used, the interrupt routine is limited to Way 1 and ordinary programs can only use the three other ways of the cache. Use of this function for the following purposes will yield a high rate of performance. 1. To prevent ordinary programs from becoming replaced due to a cache miss occurring in the interrupt routine Since the interrupt routine is limited to Way 1, which only is refilled in case of a cache miss, ordinary programs in the cache can be protected against a refill that would otherwise be applied. For example, when all interrupt routines in use are set to be locked, Ways 0, 2, and 3 of the cache can all be occupied by ordinary programs that do not include any interrupt routine, thus maintaining high performance with an improved hit rate. 2. To protect a frequently used interrupt routine by placing it in the cache This method of use is the same as using Way 1 of the cache as an interrupt routine-only, 2KB sized, instruction/ data-coexisting direct mapped cache. When the interrupt handling routine thus protected is small in terms of program size (e.g., 2KB or less) and has interrupts generated at a high frequency, high performance can be maintained because the interrupt routine and ordinary programs coexist in the cache. Moreover, this function can also be applied to main routines, and not just interrupt routines. In such case, the parts of a main routine that must be locked or not locked can be set respectively by using IL[3:0]. By setting up the Interrupt Lock Setup Register (0x48350), any desired program in the main routine can be locked the same way as for the lock function described in the preceding section by simply altering the PSR register IL[3:0] bits. II-6-10 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.6 Consistency of the Cache Data I The CCU in the C33 ADV Core Block does not have a snoop function (to maintain consistency between data in the cache and data in external memory). Therefore, if the data is shared with bus masters other than the CPU, data consistency should be guaranteed in software. Especially for data transfers performed using the internal DMA controller of the chip, note that the MMU and cache are not supported for DMA. In data transfers by the DMA controller, the cache enable register settings in the HBCU and CCU are ignored, and data is always transferred to and from physical memory. Therefore, it should be guaranteed in software that DMA transfer will not be performed to or from cacheable physical memory. Otherwise, if DMA transfer must be performed to or from a cached area, always be sure to "flush" the cache. Especially when the cache operates in write-back mode, perform write-back and cache-flush processing after disabling the cache before starting DMA transfer. When DMA transfer is completed, reenable the cache to guarantee data consistency. Furthermore, consistency between the instructions in the cache and in external memory cannot be maintained when the instruction cache only is enabled and the CPU rewrites an instruction area by a data access. Perform a cache flush also in this case. Write 1 to CFLSH (D8/0x48346) to flush the cache. II CCU S1C33401 TECHNICAL MANUAL EPSON II-6-11 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.7 Details of Control Registers Table II.6.7.1 List of CCU Registers 0x00048346 0x00048348 Register name Cache Configuration Register (pCCU_SETUP) Cache Way Number Select Register (pCCU_ENTRY) Cache Entry Control Register (pCCU_ENTRY_CNTL) Cache Control Register (pCCU_CNTL) Cache TAG Address Register 1 (pCCU_ADR) 0x0004834A 0x0004834C 0x0004834E 0x00048350 0x00048352 Cache TAG Address Register 2 Cache Data Register 1 (pCCU_DATA) Cache Data Register 2 Interrupt Lock Setup Register (pCCU_LOCK) Cache LRU Register (pCCU_LRU) Address 0x00048340 0x00048342 0x00048344 Size Function 16 Controls the entire cache 16 Specifies way numbers 16 TAG part control bit 16 16 Flushes the cache or reads/writes entries Specifies 5 low-order bits of TAG part comparison address, entry number, and word offset 16 high-order bits of TAG part comparison address 16 low-order bits of specified word in DATA part 16 high-order bits of specified word in DATA part Specifies the interrupt lock level 3-bit LRU data 16 16 16 16 16 The following describes each CCU control register. The CCU control registers are mapped into the 16-bit device area from 0x48340 to 0x48352, and can be accessed in units of half-words or bytes. Note: When setting the CCU control registers, be sure to write a 0, and not a 1, for all "reserved bits." II-6-12 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48340: Cache Configuration Register (pCCU_SETUP) Register name Address Cache configuration register (pCCU_SETUP) Bit Name 0048340 D15-13 - D12 LKWAY (HW) D11-10 - D9 DLK D8 IRLK D7-5 - D4 WBEN D3-2 - D1 DC D0 IC Function reserved Lock way select reserved Data-lock enable Instruction-lock enable reserved Write-back enable reserved Data cache enable Instruction cache enable Setting - 1 Way 1 0 Way 3 - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 0 Write through - 1 Enabled 1 Enabled 0 Disabled 0 Disabled I Init. R/W - X - 0 0 - 0 - 0 0 - R/W - R/W R/W - R/W - R/W R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. D[15:13] Reserved D12 II LKWAY: Lock-Way Select Bit Selects the way of the cache to lock. (Default: indeterminate) 1 (R/W): Way 1 0 (R/W): Way 3 D[11:10] Reserved D9 DLK: Data-Lock Enable Bit Enables the function for locking the cache against data access. 1 (R/W): Enable 0 (R/W): Disable (default) D8 IRLK: Instruction-Lock Enable Bit Enables the function for locking the cache against instruction fetch. 1 (R/W): Enable 0 (R/W): Disable (default) D[7:5] Reserved D4 WBEN: Write-Back Enable Bit Enables write-back mode. 1 (R/W): Write-back mode 0 (R/W): Write-through mode (default) CCU In write-through mode, data is written to the cache and external memory at the same time. In write-back mode, data is only written to the cache, but not written to external memory unless the written data must be replaced for a subsequent cache miss. For the cache to be used in write-back mode, WBEN should be set to 1 and the WRMDx bit provided separately in the HBCU block should also be set to 1. When WBEN = 0, the operation mode is fixed to write-through mode and WRMDx = 1 has no effect. WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2*x) D[3:2] Reserved D1 DC: Data Cache Enable Bit Enables the data cache. To use a cached area as the data cache, set this bit to 1. The data cache can be used concurrently as an instruction cache. 1 (R/W): Enable 0 (R/W): Disable (default) D0 IC: Instruction Cache Enable Bit Enables the instruction cache. To use a cached area as the instruction cache, set this bit to 1. The instruction cache can be used concurrently as a data cache. 1 (R/W): Enable 0 (R/W): Disable (default) S1C33401 TECHNICAL MANUAL EPSON II-6-13 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48342: Cache Way Number Select Register (pCCU_ENTRY) Register name Address Cache way number select register (pCCU_ENTRY) Bit Name 0048342 D15-2 - (HW) D1 WAY1 D0 WAY0 Function reserved Way number Setting Init. R/W - - - 0 to 3 Way 0 to Way 3 0 0 R/W Remarks 0 when being read. D[15:2] Reserved D[1:0] WAY[1:0]: Way Number Specifies the way number in which to read or set up the TAG or DATA part of the cache. Table II.6.7.2 Specifying Way Numbers II-6-14 WAY1 WAY0 1 1 0 0 1 0 1 0 Way Way 3 Way 2 Way 1 Way 0 (Default: 0b00 = Way 0) EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48344: Cache Entry Control Register (pCCU_ENTRY_CNTL) Register name Address Bit Name 0048344 D15-3 - Cache entry D2 LK (HW) control register D1 VLD (pCCU_ENTRY D0 DTY _CNTL) Function reserved Lock bit control/status Valid bit control/status Dirty bit control/status Setting - 1 Locked 1 Valid 1 Updated 0 Unlocked 0 Invalid 0 Unchanged Init. R/W - 0 0 0 I Remarks - 0 when being read. R/W R/W R/W D[15:3] Reserved D2 LK: Lock Bit Control/Status Bit When reading out an entry in the cache, this bit indicates the status of the TAG part L (lock) bit. When setting up an entry in the cache, the value of this bit is set in the L bit. 1 (R/W): Entry in locked state 0 (R/W): Entry ready for refill (default) When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part L bit is set to the value of LK. When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of LK is set in the TAG part L bit. D1 VLD: Valid Bit Control/Status Bit When reading out an entry in the cache, this bit indicates the status of the TAG part V (valid) bit. When setting up an entry in the cache, the value of this bit is set in the V bit. 1 (R/W): Entry valid 0 (R/W): Entry invalid (default) When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part V bit is set to the value of VLD. When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of VLD is set in the TAG part V bit. D0 DTY: Dirty Bit Control/Status Bit When reading out an entry in the cache, this bit indicates the status of the TAG part D (dirty) bit. When setting up an entry in the cache, the value of this bit is set in the D bit. 1 (R/W): Data in entry updated 0 (R/W): Data in entry not updated (default) When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part D bit is set to the value of DTY. When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of DTY is set in the TAG part D bit. S1C33401 TECHNICAL MANUAL EPSON II-6-15 II CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48346: Cache Control Register (pCCU_CNTL) Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7-6 D5 D4 D3-2 D1 D0 WBSTAT - LRURD LRUWR LKSTART LKFLSH WB CFLSH - TAGRD TAGWR - DATRD DATWR Register name Address Cache control register (pCCU_CNTL) D15 0048346 (HW) Function Write-back status reserved LRU entry read LRU entry write Lock-start control Lock-flush control Write-back control Cache-flush control reserved TAG entry read TAG entry write reserved DATA entry read DATA entry write Setting 1 Underway 1 1 1 1 1 1 1 1 1 1 Init. R/W 0 Completed - 0 Read Write 0 Lock start 0 Lock flush 0 Write back 0 Cache flush 0 - 0 Read Write 0 - Read 0 0 Write Invalid Invalid Lock end Invalid Invalid Invalid Invalid Invalid Invalid Invalid 0 - 0 0 0 0 - 0 0 - 0 0 Remarks R - 0 when being read. W W R/W W 0 when being read. W W - W W - W W WBSTAT: Write-Back Status Bit Indicates whether software-controlled write-back operation is being executed. This bit is effective only for software write-back control. 1 (R): Write-back underway 0 (R): Write-back completed (default) 1/0 (W): Has no effect This bit is set to 1 when starting a write-back operation by writing a 1 to the WB bit (D9) in this register, and is cleared to 0 when the operation is completed. D14 Reserved D13 LRURD: LRU Entry Read Bit Reads LRU information from the specified cache entry. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When LRURD is set to 1, LRU information is read from the entry of the cache specified by the Cache TAG Address Register 1 (0x48348). The information read is loaded in the Cache LRU Register (0x48352). D12 LRUWR: LRU Entry Write Bit Writes LRU information to the specified cache entry. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When LRUWR is set to 1, the LRU information set in the Cache LRU Register (0x48352) is written to the entry of the cache specified by the Cache TAG Address Register 1 (0x48348). D11 LKSTART: Lock-Start Control Bit Controls lock start and lock end. 1 (R/W): Lock start 0 (R/W): Lock end/ normal operation (default) Writing a 1 to LKSTART starts the locking sequence. Then, if the target program or data does not make a hit until the locking sequence ends, the way (Way 3 or 1) specified by LKWAY (D12/0x48340) is refilled. (When a hit is made, operation is executed without a refill.) When the specified way is accessed, the L (lock) bit in the TAG part of the accessed entry is set to 1. Then, when LKSTART is set to 0, the entry for which the L bit is set for the specified way is protected against replacement in case of a cache miss. All entries in other ways and entries for which the L bit is not set for the specified way are replaced normally as required. To unlock, use LKFLSH (D10) to clear the L bit. II-6-16 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) D10 LKFLSH: Lock-Flush Control Bit Performs a lock flush. 1 (W): Execute lock flush 0 (W): Has no effect 0 (R): Always 0 when read (default) I Writing a 1 to LKFLSH clears (initializes) the L (lock) bit of all entries. Before executing a lock flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable the cache. D9 WB: Write-Back Control Bit Writes back the cache to memory. 1 (W): Execute write-back 0 (W): Has no effect 0 (R): Always 0 when read (default) II When WB is set to 1, the cache entry specified by Cache TAG Address Register 1 (0x48348) and the Cache Way Number Select Register (0x48342) is written back to memory. When other entries of the cache must be written back in succession, always be sure to monitor the status of WBSTAT (D15) and wait until it is cleared to 0 before writing a 1 to the WB bit. D8 CCU CFLSH: Cache-Flush Control Bit Performs a cache flush. 1 (W): Flush the cache 0 (W): Has no effect 0 (R): Always 0 when read (default) Writing a 1 to CFLSH clears (initializes) the V (valid) bit, D (dirty) bit, L (lock) bit, and LRU in all cache entries. Data in the cache is retained. Before executing a cache flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable the cache. Also note that since a cache flush causes entries whose D bit = 1 to be flushed along with other "clean" entries, always be sure to check the D bit status in all entries and use WB (D9) to write back the entries whose D bit = 1 to memory. D[7:6] Reserved D5 TAGRD: TAG Entry Read Bit Reads information from the TAG part in a specified cache entry. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). The information read is loaded in the Cache Entry Control Register and Cache TAG Address Registers 1 and 2. D4 TAGWR: TAG Entry Write Bit Writes information to the TAG part in a specified cache entry. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When TAGWR is set to 1, the TAG information set in the Cache Entry Control Register and Cache TAG Address Registers 1 and 2 is written to the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). D[3:2] Reserved S1C33401 TECHNICAL MANUAL EPSON II-6-17 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) D1 DATRD: DATA Entry Read Bit Reads information from the DATA part in a specified cache entry. 1 (W): Read 0 (W): Has no effect 0 (R): Always 0 when read (default) When DATRD is set to 1, information is read from the DATA part in the way/entry/word offset of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). The information read is loaded in the Cache Data Registers 1 and 2. D0 DATWR: DATA Entry Write Bit Writes information to the DATA part in a specified cache entry. 1 (W): Write 0 (W): Has no effect 0 (R): Always 0 when read (default) When DATWR is set to 1, the DATA information set in the Cache Data Registers 1 and 2 is written to the DATA part in the way/entry/word offset of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). II-6-18 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48348: Cache TAG Address Register 1 (pCCU_ADR) Register name Address Cache TAG address register 1 (pCCU_ADR) 0048348 (HW) Name Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1-0 Function TA15 TA14 TA13 TA12 TA11 ENT6 ENT5 ENT4 ENT3 ENT2 ENT1 ENT0 WO1 WO0 - Setting Comparison address in cache TAG (5 low-order bits) Entry number (ENT[6:0] = PA[10:4]) Word offset 0 to 127 Entry 0 to Entry 127 0 to 3 W0 to W3 - reserved I Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - Remarks R/W R/W R/W - 0 when being read. D[15:11] TA[15:11]: Comparison Address in Cache TAG (CPA[15:11]) Used along with Cache TAG Address Register 2 (0x4834A) to read or set the TAG part comparison address. (Default: 0x00) TA[15:11] corresponds to the 5 low-order bits of CPA[31:11] (CPA[15:11]). When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and this register, with the comparison address in it loaded into this bit field. When a comparison address is set in this bit field and TAGWR is set to 1, the address is written to the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and this register. D[10:4] ENT[6:0]: Entry Number Specifies the entry in which to read or set up the TAG or DATA part of the cache. (Default: 0x00) The data 0-127 set here specifies the entry number represented by PA[10:4]. D[3:2] WO[1:0]: Word Offset Specifies a word offset in the DATA part to be read or set up. Table II.6.7.3 Specifying Word Offsets D[1:0] WO1 WO0 1 1 0 0 1 0 1 0 Word offset W3 W2 W1 W0 (Default: 0b00 = W0) Reserved S1C33401 TECHNICAL MANUAL EPSON II-6-19 II CCU II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x4834A: Cache TAG Address Register 2 Register name Address Bit 004834A (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Cache TAG address register 2 D[15:0] II-6-20 Name TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 TA23 TA22 TA21 TA20 TA19 TA18 TA17 TA16 Function Comparison address in cache TAG (16 high-order bits) Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W TA[31:16]: Comparison Address in Cache TAG (CPA[31:16]) Used along with Cache TAG Address Register 1 (0x48348) to read or set the TAG part comparison address. (Default: 0x0000) Cache TAG Address Register 2 corresponds to the 16 high-order bits of CPA[31:11] (CPA[31:16]). When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348), with the comparison address in it loaded into this bit field. When a comparison address is set in this bit field and TAGWR is set to 1, the address is written to the TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x4834C: Cache Data Register 1 (pCCU_DATA) 0x4834E: Cache Data Register 2 Register name Address Bit 004834C (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Cache data register 1 (pCCU_DATA) Cache data register 2 004834E (HW) Name CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CD31 CD30 CD29 CD28 CD27 CD26 CD25 CD24 CD23 CD22 CD21 CD20 CD19 CD18 CD17 CD16 Function Cache data (16 low-order bits) Cache data (16 high-order bits) I Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W II R/W CCU D[15:0]/0x4834C CD[15:0]: Cache Data (16 low-order bits) D[15:0]/0x4834E CD[31:16]: Cache Data (16 high-order bits) Used to read or set word data in the DATA part. (Default: 0x00000000) Cache Data Registers 1 and 2 correspond to the 16 low-order bits and 16 high-order bits of word data, respectively. When DATRD is set to 1, the word data set in the way/entry/word offset specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348) is read out to these registers. When DATWR is set to 1, the data set in these registers is written to the way/entry/word offset specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348). S1C33401 TECHNICAL MANUAL EPSON II-6-21 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48350: Interrupt Lock Setup Register (pCCU_LOCK) Register name Address Bit 0048350 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Interrupt lock setup register (pCCU_LOCK) D[15:0] II-6-22 Name LKIL15 LKIL14 LKIL13 LKIL12 LKIL11 LKIL10 LKIL9 LKIL8 LKIL7 LKIL6 LKIL5 LKIL4 LKIL3 LKIL2 LKIL1 LKIL0 Function Interrupt handler lock level (compared with IL[3:0] in PSR) Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W LKIL[15:0] Set the bit corresponding to the interrupt level for the interrupt handler routine to be locked to 1. (Default: 0x0000) Each bit in LKIL[15:0] corresponds to one interrupt priority level determined by the value of the PSR register IL[3:0]. If an interrupt of the set priority level occurs and a cache miss is encountered while being processed by the interrupt routine, the cache is only refilled in Way 1 and subsequently locked. In hardware, the locking sequence starts when the PSR register IL[3:0] and LKIL[15:0] match, and ends when interrupt levels do not match. The locked entry is excluded from the object of replacement and protected in the cache. EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) 0x48352: Cache LRU Register (pCCU_LRU) Register name Address Cache LRU register (pCCU_LRU) Bit Name 0048352 D15-3 - D2 LRU2 (HW) D1 LRU1 D0 LRU0 Function reserved LRU information I Setting - Init. R/W - 0 0 0 Remarks - 0 when being read. R/W D[15:3] Reserved D[2:0] LRU[2:0]: LRU Information These bits are used to save the LRU information to be written to or read from the specified entry. (Default: 0x0000) To set LRU information, write the information to this register, then set LRUWR (D12/0x48346) to 1. To confirm the LRU information set in an entry, set LRURD (D13/0x48346) to 1, then read the data loaded in this register. The entry set in the Cache TAG Address Register 1 (0x48348) is the target from or to which the LRU information is read or written. II CCU S1C33401 TECHNICAL MANUAL EPSON II-6-23 II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU) II.6.8 Precautions * To use the cache in block `x' (x = 0-7), set the corresponding DCx bit (D1) or ICx bit (D0) in the HBCU Block x Configuration Register (0x48302 + 2*x) to 1. Moreover, set the DC bit (D1) or IC bit (D0) in the CCU Cache Configuration Register (0x48340) to 1. When the cache is enabled in both the HBCU and CCU, the cache is made usable. For example, to enable the instruction and data caches for block 0 and to use them in write-back mode, 1. Set the Block 0 Configuration Register (0x48302) to 0x0007, 2. Perform a cache flush by writing 0x0100 to the Cache Control Register (0x48346), 3. Set the Cache Configuration Register (0x48340) to 0x0013. These settings activate the instruction and data caches in write-back mode. Usage like this, enabling both the instruction and data caches and set them in write-back mode, is the most effective to increase the cache performance. * To use the MMU in combination with the cache, the TLB in the MMU must also be set up, in addition to the settings above. When setting up the TLB for a page involving cache use, set the CE bit (cache enable) in the TAG part to 1. * When the lock function is used and lock control by LKSTART (D11/0x48346) and lock by interrupt level overlap, Way 1 (supported for interrupt lock) takes preference over other locked ways. In this case, the specification by LKWAY (D12/0x48340) = 1 (Way 3) has no effect. * When the cache must be written back successively in software, always be sure to monitor the status of WBSTAT (D15/0x48346) and wait until it is cleared to 0 before writing a 1 to the WB bit (D9/0x48346). * Cache write mode (write-back or write-through mode) should be set by using both WRMDx (D2/0x48302 + 2*x, x = block numbers 0 to 7) provided for each block in the HBCU and WBEN (D4/0x48340) provided in the CCU. To use the cache in write-back mode, set both to 1 (= write-back mode). When WBEN in the CCU = 0, the cache is fixed to write-through mode. This means that before WRMDx in the HBCU can be used to select write-back or write-through mode for each block individually, WBEN must be set to 1 (= write-back mode). II-6-24 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) II.7 Debug Unit (DBG) I II.7.1 Overview of the DBG The C33 ADV Core Block incorporates a Debug Unit (DBG) that supports the program debug function for on-chip trace, break, and other operations. The Debug Unit has debug pins that can be used to connect an ICD, thus facilitating an advanced software development environment using a debugger on a PC. Note: The DBG is not normally activated during device operation. To achieve a DBG-based software development environment, the S5U1C33001H (In-Circuit Debugger for S1C33 Family) Ver. 4 or later and S5U1C33001C (S1C33 Family C Compiler Package, GNU Version) Ver. 2.0 or later are required separately in addition to an S1C33 target board. II II.7.2 Input/Output Pins of the DBG The DBG has 20 ports for input/output signals to and from the debugger, and most of these input/output pins are shared with general-purpose input/output ports. DBG Table II.7.2.1 List of Debug Signal Input/Output Pins Pin name DSIO DCLK DST2 DST[1:0] DPCO DBT DTS[4:0] DTD[7:0] Function I/O I/O O O O O O O O Serial input/output for debugging (with pull-up) Clock output for debugging Debug status output Debug status output PC output for debugging Break trigger output for bus trace Bus trace data status output Bus trace data output III Essential/ Optional Essential Essential Essential Option for PC trace Option for PC trace Option for bus trace Option for bus trace Option for bus trace For details about general-purpose input/output ports that share the debugging signal pins, see the pin description in Chapter I (specifications by model). Notes: * During debugging, these pins should never be connected to other than the ICD. * When a falling edge is detected on the DSIO pin, the CPU enters debug mode. To prevent the CPU from becoming inadvertently placed in debug mode by false low pulse input when the chip is reset or operating normally, the DSIO pin should be protected against noise. S1C33401 TECHNICAL MANUAL EPSON II-7-1 II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) II.7.3 Overview of Functions The DBG operates in conjunction with development tools to support the functions described below. For details about the debugging method, refer to the user's manuals for the S5U1C33001H (In-Circuit Debugger for S1C33 Family) and the S5U1C33001C (S1C33 Family C Compiler Package, GNU Version). 1. Forcible break A forcible beak allows the CPU to be placed in debug mode when the device is reset or executing a program. 2. Single step The program is executed one instruction at a time. However, an undividable set of instructions (e.g., ext or delayed branch instructions) are executed collectively. 3. Register read/write 4. Memory read/write 5. Flash memory erase/program 6. Software PC break Implemented by embedded break instructions. This break is applied to the instructions in RAM. 7. Hardware PC break An access address on the CPU instruction bus causes a break in the program. For prefetch, there is no break in the program until immediately before execution. Three hardware PC break channels are included. One is used for single-stepping C sources and temporary break of the go command by the ICD; the other two channels are only usable by the user. When a range of addresses is specified for PC trace, both channels are used for triggering the trace. 8. Data address break An access address on the CPU data bus causes a break in the program. One such break is usable. A break actually occurs after data is accessed. 9. PC trace The output data on the DST and DPCO pins are saved on the ICD, with the PC trace information displayed in soft analysis by the debugger. The following describes the newly incorporated functions, beginning with the C33 ADV Core CPU. 10. Area break Break and no-break can be set for each area in the physical memory space (areas 1 to 22) separately managed by the BBCU. The bus master and R/W conditions can be selected using the internal functions of the chip. 11. Bus break Access attempted via the CPU instruction or data bus, or BBCU bus causes a break in the program. An address, data/instruction bit pattern (with bits maskable), R/W condition, and pass counter up to 2G counts can be set as break conditions. For the BBCU, a bus master can also be specified. 12. Bus trace The information listed below that is output using the bus trace pins is saved on the ICD, then displayed after being analyzed by the debugger. * Bus information about CPU instruction and data buses, and the BBCU bus * Address * Data/instruction pattern * R/W * Access size * Bus master (for the BBCU) 13. Supervisor mode, MMU Operation mode can be switched between supervisor mode and user mode. The MMU state can be switched between active and inactive. II-7-2 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) II.7.4 Details of Control Registers I Table II.7.4.1 List of DBG Registers Address 0x000402E8 Register name Debug Signal Output Control Write-Protect Register 0x000402EC Debug Signal Output Control Register Size Function 8 Removes write protection for the Debug Signal Output Control Register. 8 Controls trace signal outputs. The following describes each DBG control register. The DBG control registers are mapped in the 8-bit device area from 0x402E0 to 0x402F4, and can be accessed in units of bytes. Notes: * This section describes only the registers (0x402E8, 0x402EC) that are used to switch the debug pins to I/O port pins. Make sure that other registers are not accessed from the application program. II * When setting the DBG control registers, be sure to write a 0, and not a 1, for all "reserved bits." DBG III S1C33401 TECHNICAL MANUAL EPSON II-7-3 II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) 0x402E8: Debug Signal Output Control Write-Protect Register Register name Address Bit 00402E8 (B) D7 D6 D5 D4 D3 D2 D1 D0 Debug signal output control write-protect register D[7:0] Name Function DBGOUTP7 Debug signal output control DBGOUTP6 register write-protect flag DBGOUTP5 DBGOUTP4 DBGOUTP3 DBGOUTP2 DBGOUTP1 DBGOUTP0 Setting Init. R/W Remarks Writing 01011001 (0x59) X W 0 when being read. removes the write protection of X the Debug signal output control X register (0x402EC). X Writing another value set the X write protection. X X X DBGOUTP[7:0]: Debug Signal Output Control Write-Protect Flag Removes write protection of the Debug Signal Output Control Register (0x402EC). 0x59 (W): Remove write protection Other than 0x59 (W): Write-protect the register 0x00 (R): Always 0 when read Before altering the Debug Signal Output Control Register (0x402EC), write 0x59 to this register for removing write protection. If the register remains write-protected, its content is not altered even though a write instruction may have been executed without causing any problem. When rewriting the Debug Signal Output Control Register (0x402EC) has finished, this register should be set to other than 0x59 to prevent accidental writing. II-7-4 EPSON S1C33401 TECHNICAL MANUAL II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) 0x402EC: Debug Signal Output Control Register Register name Address Debug signal output control register Bit Name 00402EC D7-2 - D1 DBTOE (B) D0 DPCTOE Function reserved Bus trace signal output enable PC trace signal output enable I Setting - 1 Enabled 1 Enabled 0 Disabled 0 Disabled Init. R/W - 0 1 Remarks - 0 when being read. R/W R/W Note: This register is write protected. Before this register can be rewritten, write protection must be removed by writing data 0x59 to the Debug Signal Output Control Write-Protect Register (0x402E8). The Debug Signal Output Control Write-Protect Register (0x402E8) should be set to other than 0x59 unless this register must be rewritten. D[7:2] reserved D1 DBTOE: Bus Trace Signal Output Enable Bit Enables bus trace signal output. 1 (R/W): Enable 0 (R/W): Disable (default) II Setting this bit to 1 enables DBT, DTD[7:0], and DTS[4:0] signal output. This is necessary when using ICD3 (S5U1C33001H) to perform a bus trace. When using the P82 to P97 pins as general-purpose I/O ports or peripheral I/O ports, do not alter this bit to 0. D0 DPCTOE: PC Trace Signal Output Enable Bit Enables PC trace signal output. 1 (R/W): Enable (default) 0 (R/W): Disable III Setting this bit to 1 enables DPCO and DST[2:0] signal output. This is necessary when using ICD2/3 (S5U1C33000H/S5U1C33001H) to perform a debug operation. When using the P65 to P67 pins as general-purpose I/O ports, set this bit to 0. S1C33401 TECHNICAL MANUAL EPSON DBG II-7-5 II C33 ADV CORE BLOCK: DEBUG UNIT (DBG) II.7.5 Precautions * The DBG control registers are mapped to addresses 0x402E0 through 0x402F4 in area 1. Make sure that the application program does not access registers other than 0x402E8 and 0x402EC. * Addresses 0x60000 through 0x7FFFF in area 2 are reserved for the debug functions. This area is write-protected when no break occurs, and enabled for write operation when a break occurs. Be careful not to write to area 2 from the debugger during a beak. II-7-6 EPSON S1C33401 TECHNICAL MANUAL S1C33401 Technical Manual III C33 ADV BUS BLOCK III III C33 ADV BUS BLOCK: PREFACE III.1 Preface The C33 ADV Bus Block consists of three bus modules connected to the high-speed bus controlled by the HBCU of the C33 ADV Core Block. C33 ADV CPU A0RAM MMU HBCU A3RAM CCU High-speed bus BBCU (SRAM Controller) DMAC EBCU (SDRAM Controller) III Preface Bus Control Block Extended internal modules External memories External I/O devices Figure III.1.1 C33 ADV Bus Block BBCU: Basic Bus Control Unit Controls access to internal/external devices mapped to any of 19 divided areas in the physical memory space. SRAM, ROM, burst ROM, or flash memory may be directly connected to the BBCU. EBCU: Extended Bus Control Unit Used to extend the BBCU functions, this module incorporates an SDRAM controller. DMAC: DMA Controller Controls DMA transfers. The DMAC in the C33 ADV consists of high-speed DMA (HSDMA) and intelligent DMA (IDMA) units as in the C33 STD, but these units have more useful functions than in the predecessor. S1C33401 TECHNICAL MANUAL EPSON III-1-1 III C33 ADV BUS BLOCK: PREFACE THIS PAGE IS BLANK. III-1-2 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2 Basic Bus Control Unit (BBCU) III.2.1 Overview of the BBCU The Basic Bus Control Unit (BBCU) is one of three bus modules connected to the high-speed bus controlled by the HBCU. The BBCU manages the external memory space by dividing it into 19 areas. This module controls external bus signals according to bus conditions set for each area as it accesses the connected memory or I/O device. The BBCU functions and features are outlined below. * Supports a 32-bit address bus and data bus. * Controls external memory space as 19 divided areas (Areas 4 to 22). * Allows various conditions (e.g., external/internal access, endian mode, interface mode, device type, device size, number of access cycles) to be set for each area. * Outputs 8 chip-enable signals (#CE4 to #CE11) corresponding to each external area. * Supports two interface modes: A0 and BSL (with BSL mode for external memory only). * Allows SRAM, ROM, burst ROM, or flash memory to be connected directly to the external bus. * Allows wait states to be inserted from the external #WAIT pin (for SRAM type only). * Arbitrates bus contention with external bus masters. III BBCU S1C33401 TECHNICAL MANUAL EPSON III-2-1 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.2 BBCU Pins Table III.2.2.1 lists the pins used by the BBCU. Table III.2.2.1 BBCU Pin List Pin name A[31:0] D[31:0] #CE11 #CE10 #CE9 #CE8 #CE7 #CE6 #CE5 #CE4 #RD #BSLL (#BSL*) #WRLL (#WRL*)/ #WR #WRLH (#WRH*)/ #BSLH (#BSH*) #WRHL/ #BSHL #WRHH/ #BSHH #BUSREQ #BUSACK #BUSGET BCLK #WAIT ACST ASTB EA10MD B32MD I/O Function O I/O O O O O O O O O O O O Address signal output pins (external address bus) Data signal input/output pins (external data bus) Area 11/12 chip enable signal output pin Area 10/13/20 chip enable signal output pin Area 9/22 chip enable signal output pin Area 8/21 chip enable signal output pin Area 7/19 chip enable signal output pin Area 6/17/18 chip enable signal output pin Area 5/15/16 chip enable signal output pin Area 4/14 chip enable signal output pin Read signal output pin Least significant byte bus strobe signal output pin (when accessing BSL interfaced area) Least significant byte write signal output pin (when accessing A0 interfaced area) / Write signal output pin (when accessing BSL interfaced area) 2nd byte write signal output pin (when accessing A0 interfaced area) / 2nd byte bus strobe signal output pin (when accessing BSL interfaced area) 3rd byte write signal output pin (when accessing A0 interfaced area) / 3rd byte bus strobe signal output pin (when accessing BSL interfaced area) Most significant byte write signal output pin (when accessing A0 interfaced area) / Most significant byte bus strobe signal output pin (when accessing BSL interfaced area) Bus request signal input pin Bus request-acknowledge signal output pin Bus status monitor signal output pin BBCU clock output pin External wait request input pin Bus access status signal output pin Address strobe signal output pin Area 20 boot mode select pin (1: external ROM boot mode, 0: internal ROM boot mode) X32 boot select pin (1: X32 boot, 0: normal boot) * Signal names when only 16 data bus pins are available O O O I O O O I O O I I Notes: * The above lists the input/output pins that can be accommodated by the BBCU. Depending on the C33 ADV model used, the BBCU may have a different pin configuration. - Address bus A[31:0] may consist of less than 32 pins. - Data bus D[31:0] may only have 16 pins, D[15:0]. - All control signal pins may not be available for some C33 ADV models. - Pin names may differ for some C33 ADV models. For details of the pin configuration in each C33 ADV model, see Section I.3, "Pin Description." * Some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state may be set to other than the BBCU. Before the BBCU signals assigned to these pins can be used, the functions of these pins must be switched for the BBCU by setting each corresponding Port Function Select Register. For details on how to switch over the pin functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." * The bus control signals can be pulled high or forcibly driven low in software. For details on how to control, see Section V.4, "Pin Control Registers." III-2-2 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.3 General Memory Map The C33 ADV supports 4GB of physical address space, which is divided into 23 areas as shown in Figure III.2.3.1. Area 13 Area 12 Area 11 Area 10 Area 9 Area 8 Area 7 Area 6 Area 5 Area 4 Area 3 Area 2 Area 1 Area 0 0x02FF 0x0200 0x01FF 0x0180 0x017F 0x0100 0x00FF 0x00C0 0x00BF 0x0080 0x007F 0x0060 0x005F 0x0040 0x003F 0x0030 0x002F 0x0020 0x001F 0x0010 0x000F 0x0008 0x0007 0x0006 0x0005 0x0002 0x0001 0x0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 External Memory 16M bytes External Memory 8M bytes External Memory 8M bytes External Memory 4M bytes External Memory 4M bytes External Memory 2M bytes External Memory 2M bytes External Memory 1M bytes External Memory 1M bytes External Memory 1M bytes Internal RAM 512K bytes For debugging 128K bytes Internal I/O 256K bytes Internal RAM 128K bytes Area 22 0xFFFF FFFF Area 21 0x8000 0000 0x7FFF FFFF Area 20 0x4000 0000 0x3FFF FFFF Area 19 0x2000 0000 0x1FFF FFFF Area 18 Area 17 Area 16 Area 15 Area 14 0x1000 0x0FFF 0x0C00 0x0BFF 0x0800 0x07FF 0x0600 0x05FF 0x0400 0x03FF 0x0300 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 External Memory 2G bytes External Memory 1G bytes External Memory 512M bytes External Memory 256M bytes External Memory 64M bytes External Memory 64M bytes External Memory 32M bytes External Memory 32M bytes External Memory 16M bytes III BBCU Figure III.2.3.1 Physical Address Space of the C33 ADV Areas 0 to 3 are internal areas of the chip. Areas 4 to 22 are external memory areas (or modules built into the chip) accessed by #CEx signals output by the BBCU. When the Memory Management Unit (MMU) is used, the HBCU uses the MMU to convert logical addresses output by the CPU into the physical addresses above before it sends the address to the BBCU. With initial settings, the CPU must use the addresses above to access Areas 0 to 6 because the MMU cannot be used for these areas. (The HBCU can be set up to make the entire area address-convertible by the MMU in user mode.) When the MMU is not used, addresses output by the CPU are forwarded directly to the BBCU. For details of the HBCU and MMU, see Section II.4, "High-Speed Bus Control Unit (HBCU)," and Section II.5, "Memory Management Unit (MMU)." S1C33401 TECHNICAL MANUAL EPSON III-2-3 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.4 Internal RAM Area (Areas 0 and 3) Areas 0 and 3 are allocated to the internal RAM. Area 3 0x000F FFFF Internal RAM area (1 wait in random access) (1 wait, 32-bit bus) 512K bytes 0x0008 0000 Area 0 0x0001 FFFF I/F Highspeed bus HBCU Internal high-speed RAM area (no-wait access) 128K bytes (No wait, 32-bit bus) 0x0000 0000 Figure III.2.4.1 Areas 0 and 3 Area 0 is a 128KB space where high-speed RAM is located. This area is directly accessed from the HBCU in one cycle (with no wait states), and transparent to the BBCU. Consequently, there are no access condition setup items for this area. Note: IDMA control words cannot be placed in Area 0. Furthermore, Area 0 may not be specified as the source or destination of DMA transfer. Area 3 is a 512KB space accessed directly from a dedicated interface on the high-speed bus, transparent to the BBCU. There are no access condition setup items for this area. Area 3 is accessed in two cycles (with one wait state, for random access) or one cycle (with no wait states, for continuous access). IDMA control words can be placed in Area 3, which may also be specified as the source or destination of DMA transfer. For details of the size and address of RAM actually built into the chip, see Section I.5, "Memory Map." III-2-4 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.5 Internal I/O and Debug Areas (Areas 1 and 2) III.2.5.1 Internal I/O Area (Area 1) Area 1 contains the basic internal peripheral circuits of the C33 ADV. Addresses 0x40000 to 0x4FFFF are used for control registers; addresses 0x30000 to 0x3FFFF are the mirror of that area. The internal I/O area is divided into an 8-bit device area comprised of 4KB from addresses 0x40000 to 0x40FFF and a 16-bit device area comprised of 4KB from addresses 0x48000 to 0x48FFF. Furthermore, addresses 0x41000 to 0x41FFF are configured as the mirror of the 16-bit device area. By using this mirror with the base address set to 0x40000, the entire internal I/O area that contains both the 8-bit and 16-bit device areas can be accessed with two instructions (one basic instruction with one ext instruction). Area 1 0x0005 FFFF Unused 0x0005 0000 0x0004 FFFF 0x0004 9000 0x0004 8FFF 0x0004 0x0004 0x0004 0x0004 8000 7FFF 2000 1FFF 0x0004 1000 0x0004 0FFF 0x0004 0000 0x0003 FFFF Unused 16-bit device area Unused III 16-bit device area (mirror) 8-bit device area BBCU Mirror area 0x0003 0000 0x0002 FFFF Unused 0x0002 0000 Figure III.2.5.1.1 Configuration of Area 1 For details of the basic internal peripheral circuits mapped to this area, see Chapter IV, "C33 ADV Basic Peripheral Block." For a list of control registers, see the Appendix, "I/O Map." III.2.5.2 Debug Area (Area 2) Area 2 is a debug-only area allocated for debugging resources. This area cannot be accessed for write operation except in debug mode. Accessing this area from user programs or debuggers is prohibited. S1C33401 TECHNICAL MANUAL EPSON III-2-5 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.6 External Memory Area (Areas 4 to 22) Areas 4 to 22 comprise an external memory area accessible from the BBCU, to which external memory devices may be connected. The device type and size, access timing conditions, and other information may be set for each of these areas to be accessed. Aside from external devices, the user logic to be incorporated in the chip and other extension circuits may be located in these areas. III.2.6.1 External Memory Area and Chip Enable The BBCU supports up to 32 bits of external address bus and 32 bits of an external data bus, allowing access to the 4GB address space. The number of pins that are available on the chip is not always the same, with less than 32 address pins or only 16 data pins available for some C33 ADV models. See Section I.3, "Pin Description," for confirmation. Areas to which internal devices are mapped can basically use a 32-bit address bus and data bus. Eight chip-enable pins (#CE4 to #CE11) are provided for external access. Two or more areas are assigned to each chip-enable signal. Table III.2.6.1.1 shows the relationship between the chip-enable pins and corresponding areas. Table III.2.6.1.1 Relationship between Chip-Enable Pins and Corresponding Areas #CE pin Corresponding area #CE4 #CE5 #CE6 #CE7 #CE8 #CE9 #CE10 #CE11 Areas 4, 14 Areas 5, 15, 16 Areas 6, 17, 18 Areas 7, 19 Areas 8, 21 Areas 9, 22 Areas 10, 13, 20 Areas 11, 12 Area Usable size of area in continuous address range Size Area Size Area Area 4 Area 5 Area 6 Area 7 Area 8 Area 9 Area 10 Area 11+12 1MB 1MB 1MB 2MB 2MB 4MB 4MB 16MB Area 14 Area 15+16 Area 17+18 Area 19 Area 21 Area 22 Area 13 - 16MB 64MB 128MB 256MB 1GB 2GB 16MB - - - - - - - Area 20 - Size - - - - - - 512MB - The #CEx signal also becomes active when an address in any corresponding area is accessed. III.2.6.2 Area 20 and Boot Mode Area 20 (CE10 area) is an external memory area that includes a cold reset boot address (0x20000000). This area supports two boot modes: Internal ROM boot and External ROM boot. The boot mode is selected depending on the EA10MD pin status when the chip is reset, as shown below. Table III.2.6.2.1 Area 20 Boot Mode Selection EA10MD Area 20 boot mode 1 0 External ROM boot mode Internal ROM boot mode Internal ROM boot mode The CPU boots from internal ROM mapped to Area 20. This ROM starts from address 0x20000000 and can be read in one cycle. External ROM boot mode The CPU boots from external memory (e.g., ROM, flash, SRAM). External memory is accessed according to the content of the CE10 area setup register. Programs for internal ROM can be developed in external ROM boot mode. Note that X32 boot can also be activated by setting external pin B32MD_R to 1 when reset. Note: The EA10MD and B32MD pins are only available for C33 ADV models with built-in ROM. Moreover, these pins may have different names for some C33 ADV models. III.2.6.3 Extended I/O Area All C33 ADV models in the S1C33 Family basically contain the basic peripheral circuits mapped to Area 1. Other peripheral circuits may be mapped to one external memory area for extending functions. Normally, Area 6 is used for this extended I/O area. For details of the extended peripheral circuits, see Chapter V. III-2-6 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.6.4 Summary of Programmable External Memory Access Conditions The following lists the parameters for external memory access that can be set/selected in the BBCU. See Sections III.2.6.5 and III.2.6.6 for detailed information. Common condition settings The parameters listed below can be set up with software. * ASTB pulse width (1 or 2 clocks) * WAIT input control (enable or disable) * Burst ROM page read cycle (1 to 16 clocks) (Selectable only for the areas that support burst ROM) Figure III.2.6.4.1 <1> Figure III.2.6.4.1 <2> Figure III.2.6.4.4 <3> Per-area condition settings The parameters listed below can be set up in each area independently. * Access to external device or internal device * Endian mode (little endian or big endian) * Interface mode (A0 mode or BSL mode) * Device type (SRAM (BBCU) or SDRAM (EBCU)) * Burst ROM selection (CE10, CE8, CE5 areas only) * Device size (8, 16, or 32 bit) * Bus clock synchronization (synchronous or asynchronous) Figure III.2.6.4.1 <4> (Bus access starts at the rising edge of BCLK in synchronous mode.) Figure III.2.6.4.1 <5> * Access cycle multiplication CExMLT (1, 2, or 4) (This parameter defines the basic cycle time. Almost all programmable parameters are set up as CExMLT x CCLK cycles.) * CE cycle (1 to 16) Figures III.2.6.4.2 and III.2.6.4.3 <6> * RD start state (1 to 4) Figure III.2.6.4.2 <7> * RD start state option (-0.5 or 0 clocks) Figure III.2.6.4.2 <8> * RD end state (0 to 3) Figure III.2.6.4.2 <9> * WR start state (1 to 4) Figure III.2.6.4.3 <10> * WR start state option (-0.5 or 0 clocks) Figure III.2.6.4.3 <11> * WR end state (0 to 3) Figure III.2.6.4.3 <12> * WR end state option (-0.5 or 0 clocks) Figure III.2.6.4.3 <13> * Access disable cycle (0 to 3) Figures III.2.6.4.2 and III.2.6.4.3 <14> * Output disable cycle (0 to 3) Figure III.2.6.4.2 <15> CCLK <5> CCLK x CExMLT <4> BCLK 1 A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) <1> ASTB <2> #WAIT RD end RD start Wait cycle CE cycle Access disable Output disable 1: In BCLK synchronous mode, the #CEx and A[31:0] signals are output preceding the rising edge of BCLK. Other signal outputs and the bus access start at the rising edge of BCLK. (Access cycle multiply-by factor (CExMLT): x2, BCLK: CCLK*1/4, Bus synchronization: enabled) Figure III.2.6.4.1 SRAM Read Cycle Timing Parameters (a) EPSON S1C33401 TECHNICAL MANUAL III-2-7 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) CCLK A[31:0] valid #CEx #RD D[31:0] 1 1 <8> 1 valid RD end state <9> RD start state <7> CE cycle <6> Access disable cycle Output disable cycle <14> <15> 1: When RD start state option (-0.5 clock) is enabled Figure III.2.6.4.2 SRAM Read Cycle Timing Parameters (b) CCLK A[31:0] valid #CEx #WR 1 2 1 D[31:0] valid <11> 1 <13> 2 WR end state <12> WR start state <10> Access disable cycle CE cycle <6> <14> 1: When WR start state option (-0.5 clock) is enabled 2: When WR end state option (-0.5 clock) is enabled Figure III.2.6.4.3 SRAM Write Cycle Timing Parameters CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD 1 1 D[31:0] valid (1) 1 RD start state valid (4) valid (3) valid (2) Page read Page read Page read access access access <3> <3> <3> RD end state Inserted page read cycles Access disable cycle Output disable cycle CE cycle 1: When RD start state option (-0.5 clock) is enabled Figure III.2.6.4.4 Burst ROM Read Cycle Timing Parameters III-2-8 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.6.5 Common Condition Settings The BBCU control registers are used to set external bus access conditions. This section describes the parameters that are commonly set in all areas and the relevant control bits. The BBCU control registers are initialized by an initial reset. These registers should be set up back again in software to suit the external device configuration or specification as required. For details of bus cycle operations, see Section III.2.9, "Bus Access Timing Chart." Table III.2.6.5.1 Common Parameter Settings WAIT enable ASTB pulse width Burst ROM page read cycle Control bit settings Content Setup item Enable external WAIT input Disable external WAIT input 2 clocks x (CExMLT) 1 clock x (CExMLT) 1 clock x (CExMLT) : 16 clocks x (CExMLT) WAITEN (D0/0x48384) = 1 WAITEN (D0/0x48384) = 0 (default) ASTBW (D2/0x48384) = 1 ASTBW (D2/0x48384) = 0 (default) PGRD_CYC[3:0] (D[3:0]/0x48386) = 0 : PGRD_CYC[3:0] (D[3:0]/0x48386) = 15 (default) CExMLT in the table above (where x = numeric values 4 to 11 corresponding to #CE4 to #CE11) is an integer multiple (x1, x2 or x4) set for each area to extend access cycles. WAIT enable Wait requests from external devices using the external #WAIT pin can be enabled or disabled by setting WAITEN (D0/0x48384) = 1 or 0. When enabled, wait cycles are inserted while the #WAIT signal remains active (low) during access to external devices. This wait cycle is effective only when accessing an area whose device type is selected as SRAM, and is not inserted when accessing burst ROM or SDRAM. Even for chips with an SRAM-type extension module mapped to any external memory area, this setting applies to the internal #WAIT signal, allowing wait cycles to be inserted. WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384) ASTB pulse width The BBCU generates an address strobe (ASTB) pulse at the start of external bus access. The pulse width can be set to one or two clocks (extended x1, x2 or x4 as set for each area) by using ASTBW (D2/0x48384). The ASTB pulse can be output externally by setting up the relevant port. For details of port assignments and how to switch over the port functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." ASTBW: ASTB Pulse Width Bit in the Bus Control Register (D2/0x48384) Burst ROM page read cycle Burst ROM may be connected to the CE5, CE8, and CE10 areas. A page read cycle occurs when any of these areas receives a refill request from the cache or read request from the DMAC. You can set the number of page read cycles from 1 to 16 clocks (extended x1, x2 or x4 as set for each area) by using PGRD_CYC[3:0] (D[3:0]/ 0x48386). PGRD_CYC[3:0]: Number of Page Read Cycle Bits in the Common Cycle Control Register (D[3:0]/0x48386) S1C33401 TECHNICAL MANUAL EPSON III-2-9 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.6.6 Per-Area Condition Settings Bus access conditions can be set by area for each #CEx signal. Therefore, the same conditions for two or more areas accommodated by the respective #CEx signals will be set. This section describes the parameters to be set individually for each area and the relevant control bits. The BBCU control registers are initialized by an initial reset. These registers should be set up back again in software to suit the external device configuration or specification as required. For details of bus cycle operation, see Section III.2.9, "Bus Access Timing Chart." Note: The control register and control bit configurations are the same for all CE4 to CE11 areas. The control bit names begin with CE4 to CE11 to indicate the relevant areas, which in the description below are commonly represented by CEx for all areas. Table III.2.6.6.1 Per-area Parameter Settings Setup item Control bit settings Content Access internal device Access external device Big endian Endian mode Little endian BSL mode Interface mode A0 mode EBCU device (SDRAM) Device type BBCU device (SRAM) Use Burst ROM Burst ROM selection (CE10, CE8, CE5 areas only) Do not use Burst ROM 32 bits Device size 16 bits (connect to 16 high-order data bus bits) 16 bits (connect to 16 low-order data bus bits) 8 bits Synchronous Bus clock synchronization Asynchronous Multiplied by 4 Access cycle multiplication Multiplied by 2 Multiplied by 1 16 clocks x (CExMLT) CE cycle : 8 clocks x (CExMLT) : 1 clock x (CExMLT) 4 clocks x (CExMLT) RD start state 3 clocks x (CExMLT) 2 clocks x (CExMLT) 1 clock x (CExMLT) Enable RD start state option Disable (-0.5 clock) 3 clocks x (CExMLT) RD end state 2 clocks x (CExMLT) 1 clock x (CExMLT) 0 clocks x (CExMLT) 4 clocks x (CExMLT) WR start state 3 clocks x (CExMLT) 2 clocks x (CExMLT) 1 clock x (CExMLT) Enable WR start state option Disable (-0.5 clock) 3 clocks x (CExMLT) WR end state 2 clocks x (CExMLT) 1 clock x (CExMLT) 0 clocks x (CExMLT) Enable WR end state option Disable (-0.5 clock) External/internal access III-2-10 EPSON CExIO (D13/REG_A) = 1 CExIO (D13/REG_A) = 0 (default) CExBIG (D12/REG_A) = 1 CExBIG (D12/REG_A) = 0 (default) CExBSL (D11/REG_A) = 1 CExBSL (D11/REG_A) = 0 (default) CExEBCU (D10/REG_A) = 1 CExEBCU (D10/REG_A) = 0 (default) BROM_CEx (D[6:4]/0x48384) = 1 BROM_CEx (D[6:4]/0x48384) = 0 (default) CExDVSZ[1:0] (D[9:8]/REG_A) = 11 CExDVSZ[1:0] (D[9:8]/REG_A) = 10 CExDVSZ[1:0] (D[9:8]/REG_A) = 01 (default) CExDVSZ[1:0] (D[9:8]/REG_A) = 00 CExBCKSYN (D5/REG_A) = 1 (default) CExBCKSYN (D5/REG_A) = 0 CExMLT[1:0] (D[15:14]/REG_B) = 10 or 11 (default) CExMLT[1:0] (D[15:14]/REG_B) = 01 CExMLT[1:0] (D[15:14]/REG_B) = 00 CExCE[3:0] (D[3:0]/REG_B) = 1111 : CExCE[3:0] (D[3:0]/REG_B) = 0111 (default) : CExCE[3:0] (D[3:0]/REG_B) = 0000 CExRDSTAC[1:0] (D[7:6]/REG_B) = 11 CExRDSTAC[1:0] (D[7:6]/REG_B) = 10 CExRDSTAC[1:0] (D[7:6]/REG_B) = 01 (default) CExRDSTAC[1:0] (D[7:6]/REG_B) = 00 CExRSTHCK (D2/REG_A) = 1 CExRSTHCK (D2/REG_A) = 0 (default) CExRDENDC[1:0] (D[5:4]/REG_B) = 11 CExRDENDC[1:0] (D[5:4]/REG_B) = 10 (default) CExRDENDC[1:0] (D[5:4]/REG_B) = 01 CExRDENDC[1:0] (D[5:4]/REG_B) = 00 CExWRSTAC[1:0] (D[11:10]/REG_B) = 11 CExWRSTAC[1:0] (D[11:10]/REG_B) = 10 CExWRSTAC[1:0] (D[11:10]/REG_B) = 01 (default) CExWRSTAC[1:0] (D[11:10]/REG_B) = 00 CExWSTHCK (D4/REG_A) = 1 CExWSTHCK (D4/REG_A) = 0 (default) CExWRENDC[1:0] (D[9:8]/REG_B) = 11 CExWRENDC[1:0] (D[9:8]/REG_B) = 10 (default) CExWRENDC[1:0] (D[9:8]/REG_B) = 01 CExWRENDC[1:0] (D[9:8]/REG_B) = 00 CExWEDHCK (D3/REG_A) = 1 CExWEDHCK (D3/REG_A) = 0 (default) S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Control bit settings Content Setup item 3 clocks x (CExMLT) 2 clocks x (CExMLT) 1 clock x (CExMLT) 0 clocks x (CExMLT) 3 clocks x (CExMLT) 2 clocks x (CExMLT) 1 clock x (CExMLT) 0 clocks x (CExMLT) Access disable cycle Output disable cycle CExADISC[1:0] (D[13:12]/REG_B) = 11 (default) CExADISC[1:0] (D[13:12]/REG_B) = 10 CExADISC[1:0] (D[13:12]/REG_B) = 01 CExADISC[1:0] (D[13:12]/REG_B) = 00 CExODISC[1:0] (D[1:0]/REG_A) = 11 (default) CExODISC[1:0] (D[1:0]/REG_A) = 10 CExODISC[1:0] (D[1:0]/REG_A) = 01 CExODISC[1:0] (D[1:0]/REG_A) = 00 REG_A: CEx Area Configuration Register (0x48388 + 4*(x - 4)) REG_B: CEx Access Cycle Control Register (0x4838A + 4*(x - 4)) (where x = numeric values 4 to 11 corresponding to #CE4 to #CE11) External/internal access Any extension modules incorporated in the chip may be assigned an external memory area. Before an internal device can be accessed, control bit CExIO (D13/0x48388 + 4*(x - 4)) for the assigned CEx area must be set to 1. This control bit is initially set to 0 for external devices to be accessed. CExIO: External/Internal Access Setting Bit in the CEx Area Configuration Register (D13/0x48388 + 4*(x - 4)) Note: If a C33 ADV model with built-in ROM in CE10 area is started after setting external pin EA10MD to 0, CE10IO (D13/0x483A0) defaults to 0 and internal ROM is accessed. (For EA10MD, see Section III.2.6.2, "Area 20 and Boot Mode.") Endian mode III The halfword and word data in memory are accessed in little endian mode by default. When any external device must be accessed in big endian mode, set CExBIG (D12/0x48388 + 4*(x - 4)) to 1. CExBIG: Endian Mode Select Bit in the CEx Area Configuration Register (D12/0x48388 + 4*(x - 4)) For details of the data size and endian mode-dependent bus operation, see Section III.2.7.3, "External Bus Operation." Interface mode The BBCU incorporates an SRAM-type bus interface, allowing A0 (default) or BSL to be selected as the interface mode. To use the BSL-mode interface in the CEx area, set CExBSL (D11/0x48388 + 4*(x - 4)) to 1. CExBSL: External Interface Mode Select Bit in the CEx Area Configuration Register (D11/0x48388 + 4*(x - 4)) Table III.2.6.6.2 lists the bus control signal pins used in each interface mode. Table III.2.6.6.2 Bus Control Signal Pins Used in A0 and BSL Modes Pin name #CEx #RD #BSLL(#BSL) #WRLL(#WRL) #WRLH(#WRH) #WRHL #WRHH BSL mode A0 mode (default) #CEx #RD Unused #WRLL(#WRL) #WRLH(#WRH) #WRHL #WRHH Little endian Big endian #CEx #RD #BSLL(#BSL) #WR #BSLH(#BSH) #BSHL #BSHH #CEx #RD #BSLH(#BSH) #WR #BSLL(#BSL) #BSHH #BSHL Device type The device type (interface) to be connected can be selected for each CE area. Initially, the device type is selected as SRAM type (BBCU SRAM interface) for all areas. To use SDRAM (EBCU SDRAM interface) in the CEx area, set CExEBCU (D10/0x48388 + 4*(x - 4)) to 1. CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4*(x - 4)) Burst ROM may be used in the CE5, CE8, and CE10 areas. To use burst ROM in the CE10 area, for example, set CE10EBCU (D10/0x483A0) to 0 and BROM_CE10 (D6/0x48384) to 1. BROM_CEx: CEx Area Burst ROM Select Bit in the Bus Control Register (D6/0x48384 for CE10, D5 for CE8, D4 for CE5) S1C33401 TECHNICAL MANUAL EPSON III-2-11 BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Table III.2.6.6.3 lists a combination of control bits and selected device types. Table III.2.6.6.3 Selection of Device Types CExEBCU BROM_CEx * Device type 1 0 0 X 1 0 SDRAM Burst ROM * SRAM Burst ROM may only be selected for the CE5, CE8, and CE10 areas. Device size Use CExDVSZ[1:0] (D[9:8]/0x48388 + 4*(x - 4)) to select a device size. CExDVSZ[1:0]: Device Size Select Bits in the CEx Area Configuration Register (D[9:8]/0x48388 + 4*(x - 4)) Table III.2.6.6.4 Selection of Device Sizes CExDVSZ1 CExDVSZ0 1 1 0 0 1 0 1 0 Connected data bus Device size D[31:0] (Note) D[31:16] (Note) D[15:0] D[7:0] 32 bits 16 bits (16 high-order data bus bits) 16 bits (16 low-order data bus bits) 8 bits At an initial reset, the device size is initialized to 16 bits (16 low-order data bus bits). Note: For C33 ADV models with 16 external data bus pins, D[15:0], 32 bits or 16 bits (16 high-order data bus bits) may be selected for the device size only when using an internal device. Bus clock synchronization With initial settings, the read/write signals are output synchronized with BCLK. When external devices are clocked by BCLK, use this setting. In this setting, bus access starts synchronously with the rising edge of BCLK. When CExBCKSYN (D5/0x48388 + 4*(x - 4)) is set to 0, read/write signals are output asynchronously with BCLK. This setting helps reduce the bus cycle. The BBCU generates bus control signals synchronously with CCLK. See Figures III.2.6.4.1 and III.2.6.4.2 for differences between BCLK synchronous mode and BCLK asynchronous mode. CExBCKSYN: Bus Clock Synchronization Select Bit in the CEx Area Configuration Register (D5/0x48388 + 4*(x - 4)) Access cycle multiplication The number of bus access-related cycles can be set for each area. These values are specified in terms of core clock CCLK counts. However, to accommodate low-speed devices, the number of cycles set by the respective control bits may be multiplied by 4 or 2. To specify this multiply-by factor, use CExMLT[1:0] (D[15:14]/ 0x4838A + 4*(x - 4)). See Figure III.2.6.4.1 for a timing example. CExMLT[1:0]: Access Cycle Multiple Mode Select Bits in the CEx Access Cycle Control Register (D[15:14]/0x4838A + 4*(x - 4)) Table III.2.6.6.5 Access Cycle Multiply-by Factors CExMLT1 CExMLT0 Multiply-by factor 1 0 0 X 1 0 x4 x2 x1 At an initial reset, the access cycle multiply-by factors are initialized to x4 for all areas. III-2-12 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Timing parameters that can be set by control bits Before how to set each timing parameter is described below, the following diagram shows the relationship between these parameters and positioning in the bus cycle. (Example for BCLK asynchronous operation) CCLK A[31:0] valid #CEx #RD 1 1 D[31:0] valid 1 RD start state RD end state CE cycle Output disable cycle Access disable cycle 1: When RD start state option (-0.5 clock) is enabled Figure III.2.6.6.1 SRAM Read Cycle Timing Parameters CCLK A[31:0] valid #CEx #WR 1 2 1 D[31:0] III valid 1 WR start state 2 WR end state Access disable cycle CE cycle BBCU 1: When WR start state option (-0.5 clock) is enabled 2: When WR end state option (-0.5 clock) is enabled Figure III.2.6.6.2 SRAM Write Cycle Timing Parameters CCLK A[31:4] valid A[3:2] 00 01 10 11 #CEx #RD 1 1 D[31:0] valid (1) 1 RD start state valid (2) valid (3) valid (4) Page read Page read Page read access access access Inserted page read cycles RD end state Access disable cycle Output disable cycle CE cycle 1: When RD start state option (-0.5 clock) is enabled Figure III.2.6.6.3 Burst ROM Read Cycle Timing Parameters Each timing parameter is detailed below. Confirm that the parameters are set suited to specifications of the connected devices. Notes: * All bus control signals are generated while synchronized with CCLK even if BCLK synchronous mode is selected. In BCLK synchronous mode, only the read/write signal is asserted synchronously with the rising edge of BCLK and BCLK does not affect other timings. * The CExMLT bit multiplies the number of cycles of only the timing parameters shown below by 1, 2, or 4. CE cycle, RD start state, RD end state, WR start state, WR end state (0 to 3), access disable cycle, and output disable cycle S1C33401 TECHNICAL MANUAL EPSON III-2-13 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) CE cycle The CE cycle is the period of time during which the #CEx signal is asserted (low) in one access made. Use CExCE[3:0] (D[3:0]/0x4838A + 4*(x - 4)) to specify the number of CCLK clocks. CExCE[3:0]: CE Cycle Setup Bits in the CEx Access Cycle Control Register (D[3:0]/0x4838A + 4*(x - 4)) Table III.2.6.6.6 CE Cycle Settings CExCE3 CExCE2 CExCE1 CExCE0 CE cycle 1 1 : 0 : 0 0 1 1 : 1 : 0 0 1 1 : 1 : 0 0 1 0 : 1 : 1 0 16 clocks 15 clocks : 8 clocks : 2 clocks 1 clock The actual CE cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/ 0x4838A + 4*(x - 4)). Note: The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in CCLK clock units) minus the number of RD/WR start and end state clocks (read/write pulse width) is equal to or less than 0, device operation for that cycle cannot be guaranteed. Furthermore, the number of CE cycles must be set to two or more clocks (one clock cannot be specified). RD/WR start state and -0.5 cycle option The timing at which read and write signals are asserted can be set by using CExRDSTAC[1:0] (D[7:6]/0x4838A + 4*(x - 4)) and CExWRSTAC[1:0] (D[11:10]/0x4838A + 4*(x - 4)), respectively. CExRDSTAC[1:0]: Read Start State Setup Bits in the CEx Access Cycle Control Register (D[7:6]/0x4838A + 4*(x - 4)) CExWRSTAC[1:0]: Write Start State Setup Bits in the CEx Access Cycle Control Register (D[11:10]/0x4838A + 4*(x - 4)) Table III.2.6.6.7 RD/WR Start State Settings CExRDSTAC1 CExWRSTAC1 CExRDSTAC0 CExWRSTAC0 RD/WR start state 1 1 0 0 1 0 1 0 4 clocks 3 clocks 2 clocks 1 clock This setting selects the number of CCLK clocks until the read/write signal becomes active (goes low). The starting point of the RD/WR start state varies depending on the bus clock synchronization mode selected by CExBCKSYN (D5/0x48388 + 4*(x - 4)). When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 0), this setting indicates the number of CCLK clocks from the first rise of BCLK (after the #CEx signal is asserted) to when the read/write signal becomes active (goes low). When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 1), this setting indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when the read/write signal becomes active (goes low). At an initial reset, the RD/WR start state is initialized to two clocks. The actual RD/WR start state equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). III-2-14 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Moreover, an option available for the RD/WR start state allows the read/write signal to be asserted 0.5 cycle before the set timing. To specify this option, set CExRSTHCK (D2/0x48388 + 4*(x - 4)) to 1 for read; set CExWSTHCK (D4/0x48388 + 4*(x - 4)) to 1 for write. At an initial reset, these bits are initialized to 0, so that the option is not effective. CExRSTHCK: RD Start State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register (D2/0x48388 + 4*(x - 4)) CExWSTHCK: WR Start State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register (D4/0x48388 + 4*(x - 4)) Notes: * The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)) does not apply to the RD/WR start state option (-0.5 clock). * When the CCLK frequency is 49 MHz or higher, do not enable the RD/WR start state option (-0.5 clock). * If the WR start state option is specified when the actual WR start state is one clock, valid write data will not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock period is required before write data can be set up after #CE is asserted. RD/WR end state and -0.5 cycle option The timing at which read and write signals are deasserted can be set by using CExRDENDC[1:0] (D[5:4]/ 0x4838A + 4*(x - 4)) and CExWRENDC[1:0] (D[9:8]/0x4838A + 4*(x - 4)), respectively. CExRDENDC[1:0]: Read End State Setup Bits in the CEx Area Cycle Control Register (D[5:4]/0x4838A + 4*(x - 4)) CExWRENDC[1:0]: Write End State Setup Bits in the CEx Area Cycle Control Register (D[9:8]/0x4838A + 4*(x - 4)) Table III.2.6.6.8 RD/WR End State Settings CExRDENDC1 CExWRENDC1 CExRDENDC0 CExWRENDC0 RD/WR end state 1 1 0 0 1 0 1 0 3 clocks 2 clocks 1 clock 0 clocks BBCU This sets the number of clocks (in CCLK clock units) at which time the read/write signal becomes inactive (goes high) before a separately specified CE cycle ends. At an initial reset, the RD/WR end state is initialized to two clocks. The actual RD/WR end state equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). Moreover, an option available for the WR end state allows the write signal to be deasserted 0.5 cycle after the set timing. To specify this option, set CExWEDHCK (D3/0x48388 + 4*(x - 4)) to 1. At an initial reset, this bit is initialized to 0, so that the option is not effective. CExWEDHCK: WR End State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register (D3/0x48388 + 4*(x - 4)) Notes: * The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)) does not apply to the WR end state option (-0.5 clock). * When the CCLK frequency is 49 MHz or higher, do not enable the WR end state option (-0.5 clock). * If the number of WR end state cycles is set to 0 clock by CExWRENDC[1:0] (D[9:8]/0x4838A + 4*(x - 4)), the WR end state option (-0.5 clock) is ignored. S1C33401 TECHNICAL MANUAL EPSON III III-2-15 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Access-disable cycle To accommodate low-speed devices, an access-disable cycle can be inserted before the next CE cycle starts after a data access (after the end of the preceding CE cycle). Use CExADISC[1:0] (D[13:12]/0x4838A + 4*(x - 4)) to make this setting. CExADISC[1:0]: Access Disable State Setup Bits in the CEx Access Cycle Control Register (D[13:12]/0x4838A + 4*(x - 4)) Table III.2.6.6.9 Access-Disable Cycle Settings CExADISC1 CExADISC0 Access disable cycle 1 1 0 0 1 0 1 0 3 clocks 2 clocks 1 clock 0 clocks The access-disable cycle set here is inserted before the next CE cycle or an output-disable cycle starts after a separately specified CE cycle ends. At an initial reset, the access-disable cycle is initialized to three clocks. The actual access-disable cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). The following shows the conditions under which the access-disable cycle is inserted. * The access-disable cycle is always inserted when accessing the CE area for either read or write access. * The access-disable cycle is inserted immediately after a CE cycle (or any set RD/WR end state). * The access-disable cycle is also inserted when accessing the same area successively (including when data size > device size). * For page read access to burst ROM, the access-disable cycle is inserted immediately after a CE cycle that includes a series of page read cycles (or after any set RD end state). * For burst transfer to other than burst ROM (four or eight consecutive words), the access-disable cycle is inserted for every four or eight words transferred. Output-disable cycle To accommodate devices for which output takes a long time, an output-disable cycle can be inserted before the next CE cycle starts after a data read operation. Use CExODISC[1:0] (D[1:0]/0x48388 + 4*(x - 4)) to make this setting. CExODISC[1:0]: Output-Disable Cycle Configuration Bits in the CEx Area Configuration Register (D[1:0]/0x48388 + 4*(x - 4)) Table III.2.6.6.10 Output-Disable Cycle Settings CExODISC1 CExODISC0 Output disable cycle 1 1 0 0 1 0 1 0 3 clocks 2 clocks 1 clock 0 clocks The output-disable cycle specified here is inserted before the next CE cycle starts after a separately specified access-disable cycle ends (or after the end of the preceding CE cycle if no access-disable cycles are inserted). At an initial reset, the output-disable cycle is initialized to three clocks. The actual output-disable cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). III-2-16 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) The following shows the conditions under which the output-disable cycle is inserted. * The output-disable cycle is always inserted during read access. * The output-disable cycle is inserted immediately after an access-disable cycle (or immediately after a CE cycle if no access-disable cycles are set). * For read access where data size > device size, the output-disable cycle is only inserted during the last access. * For page read access to burst ROM and a burst read from other than burst ROM (four consecutive words), the output-disable cycle is inserted in the last access made. * No output-disable cycle is inserted during write access. * No output-disable cycle is inserted during consecutive accesses to the same area. III BBCU S1C33401 TECHNICAL MANUAL EPSON III-2-17 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.7 Connection of External Devices and Bus Operation III.2.7.1 Connecting External Devices The following shows an example of connecting the S1C33 chip and SRAM. A[n:0] D[7:0] #CEx #RD #WRLL SRAM S1C33 SRAM S1C33 A[n:0] I/O[7:0] A[n:0] D[15:8] A[n:0] I/O[7:0] #CE #OE #WE #CEx #RD #WRLH #CE #OE #WE <Big endian method> <Little endian method> Figure III.2.7.1.1 Example of 8-bit SRAM Connection with 8-bit Device Size SRAM S1C33 SRAM S1C33 A[n:1] D[15:0] A[n-1:0] I/O[15:0] A[n:1] D[15:0] A[n-1:0] I/O[15:0] #CEx #RD #WRLL #WRLH #CE #OE #WEL #WEH #CEx #RD #WR #BSLL #BSLH #CE #OE #WE #LB #UB <BSL mode, 16-bit SRAM> <A0 mode, 16-bit SRAM> Figure III.2.7.1.2 Example of 16-bit SRAM Connection with 16-bit (lower) Device Size S1C33 SRAM A[n:2] D[15:0] D[31:16] A[n-2:0] I/O[15:0] #CEx #RD #WRLL #WRLH #WRHL #WRHH #CE #OE #WEL #WEH S1C33 SRAM A[n:2] D[15:0] D[31:16] #CEx #RD #WR #BSLL #BSLH #BSHL #BSHH A[n-2:0] I/O[15:0] #CE #OE #WEL #WEH A[n-2:0] I/O[15:0] #CE #OE #WE #LB #UB A[n-2:0] I/O[15:0] #CE #OE #WE #LB #UB <A0 mode, 16-bit SRAM x 2> <BSL mode, 16-bit SRAM x 2> Figure III.2.7.1.3 Example of 16-bit SRAM Connection with 32-bit Device Size III-2-18 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.7.2 Data Configuration in Memory The C33 ADV system handles byte (8-bit), halfword (16-bit), and word (32-bit) data. To access data in memory, addresses aligned to the boundary of the data size must be specified. Specifying other addresses generates address misaligned exceptions. Instructions (e.g., stack manipulating and branch instructions) that rewrite the content of the Stack Pointer (SP) or Program Counter (PC) forcibly alter the address specified to a boundary address to prevent address misaligned exceptions. For details of address misaligned exceptions, refer to the C33 ADV Core CPU Manual. Table III.2.7.2.1 shows where each type of data is located in memory. Table III.2.7.2.1 Data Locations in Memory Data type Byte Halfword Word Location Byte boundary (all addresses) Halfword boundary (A[0] = 0) Word boundary (A[1:0] = 0b00) All halfword and word data in memory are accessed in little endian mode by default. You can switch little endian mode to big endian mode for each CE area by setting CExBIG (D12/0x48388 + 4*(x - 4)) to 1. CExBIG: Endian Mode Select Bit in the CEx Area Configuration Register (D12/0x48388 + 4*(x - 4)) To increase memory efficiency, try locating the same type of data at contiguous addresses to reduce blank areas created by positioning at boundary addresses as much as possible. III III.2.7.3 External Bus Operation The external data bus size in the C33 ADV is 32 bits. Note, however, that standard S1C33 models have 16 external bus pins D[15:0]. Depending on the device size and data size of the instruction executed, two or more bus operations may occur. Table III.2.7.3.1 shows bus operation in A0 mode; Table III.2.7.3.2 shows bus operation in BSL mode. For details on how to connect memory, see Section III.2.7.1, "Connecting External Devices." S1C33401 TECHNICAL MANUAL EPSON III-2-19 BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Table III.2.7.3.1 Bus Operation in A0 Mode Device size Data size 8 bits Byte Half word R/W A1 A0 W R W R Word W R 16 bits (lower) Byte W R Half word Word W R W R 16 bits (higher) Byte W R Half word Word W R W R 32 bits Byte W R Half word W R Word III-2-20 W R 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Little endian Valid D[31:24] D[23:16] D[15:8] D[7:0] pins signal pins pins pins - #WRLL - - D[7:0] - #RD - - D[7:0] - #WRLL - - D[7:0] - - - D[15:8] - #RD - - D[7:0] - - - D[15:8] - #WRLL - - D[7:0] - - - D[15:8] - - - D[23:16] - - - D[31:24] - #RD - - D[7:0] - - - D[15:8] - - - D[23:16] - - - D[31:24] - #WRLL - - D[7:0] - #WRLH - D[7:0] - - #RD - - D[7:0] - - D[7:0] - - #WRL - D[15:0] - #RD - D[15:0] - #WRL - D[15:0] - - D[31:16] - #RD - D[15:0] - - D[31:16] - #WRLL D[7:0] - - #WRLH D[7:0] - - - - #RD D[7:0] - - D[7:0] - - - #WRL - - D[15:0] #RD - - D[15:0] #WRL - - D[15:0] - - D[31:16] #RD - - D[15:0] - - D[31:16] - #WRLL - - D[7:0] - #WRLH - D[7:0] - - #WRHL D[7:0] - - #WRHH D[7:0] - - - - #RD - - D[7:0] - - D[7:0] - - D[7:0] - - D[7:0] - - - - #WRL - D[15:8] D[7:0] #WRH D[15:8] D[7:0] - - - #RD - D[15:8] D[7:0] D[15:8] D[7:0] - - #WR D[31:0] #RD D[31:0] EPSON Big endian Valid D[31:24] D[23:16] D[15:8] D[7:0] signal pins pins pins pins #WRLH - - D[7:0] - #RD - - D[7:0] - #WRLH - - D[15:8] - - - D[7:0] - #RD - - D[15:8] - - - D[7:0] - #WRLH - - D[31:24] - - - D[23:16] - - - D[15:8] - - - D[7:0] - #RD - - D[31:24] - - - D[23:16] - - - D[15:8] - - - D[7:0] - #WRLH - - D[7:0] - #WRLL - - - D[7:0] #RD - - D[7:0] - - - - D[7:0] D[15:0] #WRL - - D[15:0] #RD - - D[31:16] #WRL - - D[15:0] - - D[31:16] #RD - - D[15:0] - - #WRLH D[7:0] - - - #WRLL - D[7:0] - - #RD D[7:0] - - - - D[7:0] - - #WRL D[15:0] - - #RD D[15:0] - - #WRL D[31:16] - - D[15:0] - - #RD D[31:16] - - D[15:0] - - #WRLH D[7:0] - - - #WRLL - D[7:0] - - #WRHH - - D[7:0] - #WRHL - - - D[7:0] #RD D[7:0] - - - - D[7:0] - - - - D[7:0] - - - - D[7:0] #WRH D[15:8] D[7:0] - - #WRL - - D[15:8] D[7:0] #RD D[15:8] D[7:0] - - - - D[15:8] D[7:0] D[31:0] #WR D[31:0] #RD Access count 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 1st 2nd 1 1 S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Table III.2.7.3.2 Bus Operation in BSL Mode Device size Data size 8 bits Byte Half word R/W A1 A0 W R W R Word W R 16 bits (lower) Byte W R Half word Word W R W R 16 bits (higher) Byte W R Half word Word W R W R 32 bits Byte W R Half word W R Word W R 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S1C33401 TECHNICAL MANUAL Little endian Valid D[31:24] D[23:16] D[15:8] D[7:0] signal pins pins pins pins #BSLL - D[7:0] - - #RD - D[7:0] - - #BSLL - D[7:0] - - - D[15:8] - - #RD - D[7:0] - - - D[15:8] - - #BSLL - D[7:0] - - - D[15:8] - - - D[23:16] - - - D[31:24] - - #RD - D[7:0] - - - D[15:8] - - - D[23:16] - - - D[31:24] - - #BSLL - D[7:0] - - #BSLH - - D[7:0] - #RD - D[7:0] - - - - D[7:0] - #BSL D[15:0] - - #RD D[15:0] - - #BSL D[15:0] - - D[31:16] - - #RD D[15:0] - - D[31:16] - - #BSLL - - - D[7:0] #BSLH D[7:0] - - - #RD - - - D[7:0] D[7:0] - - - #BSL D[15:0] - - #RD D[15:0] - - #BSL D[15:0] - - D[31:16] - - #RD D[15:0] - - D[31:16] - - #BSLL - D[7:0] - - #BSLH - - D[7:0] - #BSHL - - - D[7:0] #BSHH D[7:0] - - - #RD - D[7:0] - - - - D[7:0] - - - - D[7:0] D[7:0] - - - #BSL - D[15:8] D[7:0] - #BSH D[15:8] D[7:0] - - #RD - D[15:8] D[7:0] - D[15:8] D[7:0] - - #BS D[31:0] #RD D[31:0] EPSON Big endian Valid D[31:24] D[23:16] D[15:8] D[7:0] signal pins pins pins pins #BSLH - - D[7:0] - #RD - - D[7:0] - #BSLH - - D[15:8] - - - D[7:0] - #RD - - D[15:8] - - - D[7:0] - #BSLH - - D[31:24] - - - D[23:16] - - - D[15:8] - - - D[7:0] - #RD - - D[31:24] - - - D[23:16] - - - D[15:8] - - - D[7:0] - #BSLH - - D[7:0] - #BSLL - - - D[7:0] #RD - - D[7:0] - - - - D[7:0] D[15:0] #BSL - - D[15:0] #RD - - D[31:16] #BSL - - D[15:0] - - D[31:16] #RD - - D[15:0] - - #BSLH D[7:0] - - - #BSLL - D[7:0] - - #RD D[7:0] - - - - D[7:0] - - D[15:0] #BSL - - D[15:0] #RD - - D[31:16] #BSL - - D[15:0] - - D[31:16] #RD - - D[15:0] - - #BSLH D[7:0] - - - #BSLL - D[7:0] - - #BSHH - - D[7:0] - #BSHL - - - D[7:0] #RD D[7:0] - - - - D[7:0] - - - - D[7:0] - - - - D[7:0] #BSH D[15:8] D[7:0] - - #BSL - - D[15:8] D[7:0] #RD D[15:8] D[7:0] - - - - D[15:8] D[7:0] D[31:0] #BS D[31:0] #RD Access count 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 1st 2nd 1 1 III-2-21 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.8 BBCU Operating Clock and Bus Clock III.2.8.1 Operating Clock of the BBCU The BBCU is clocked by the core system clock (CCLK) generated by the CMU. The bus control signals are generated synchronously with CCLK. For details on how to set CCLK and control the clock, see Section II.3, "Clock Management Unit (CMU)." Controlling supply of the BBCU operating clock CCLK is supplied to the BBCU with default settings. There are four ways of supplying CCLK to the BBCU by the CMU as detailed below. Use the respective control bits to turn off any unnecessary clock supplies to reduce the amount of power consumed on the chip. Automatic control may also be applied for clock supplies 2 to 4. 1. BBCU, EBCU NOSTOP clock This clock is used for controlling the entire high-speed bus. Turn this clock on when using any of the blocks connected to the high-speed bus (e.g., the BBCU). The clock supply can be controlled by BBEBNCLK (D11/0x48370). BBEBNCLK: BBCU, EBCU NOSTOP Control Bit in the CCLK System Peripheral Clock On/Off Register (D11/0x48370) 2. BBCU HB interface clock This clock is used for interfacing SRAM to the BBCU. Turn this clock on when using the SRAM interface, regardless of whether external or internal (e.g., area 6). The clock supply can be controlled by BBHBIFCLK (D10/0x48370). Use BBHBIFAUTO (D10/0x48372) to enable or disable the automatic control function. BBHBIFCLK: BBCU HB Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D10/0x48370) BBHBIFAUTO: BBCU HB Interface Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D10/0x48372) 3. BBCU SRAM clock Like clock supply 2 above, this clock is used for interfacing SRAM to the BBCU. Turn this clock on when using the SRAM interface. The clock supply can be controlled by BBSRAMCLK (D9/0x48370). Use BBSRAMAUTO (D9/0x48372) to enable or disable the automatic control function. BBSRAMCLK: BBCU SRAM Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D9/0x48370) BBSRAMAUTO: BBCU SRAM Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D9/0x48372) 4. BBCU DBG interface clock This clock is used for ICD-based debugging operation. Turn this clock on when debugging is performed using an ICD. The clock supply can be controlled by BBDBGIFCLK (D8/0x48370). Use BBDBGIFAUTO (D8/0x48372) to enable or disable the automatic control function. BBDBGIFCLK: BBCU DBG Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D8/0x48370) BBDBGIFAUTO: BBCU DBG Interface Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D8/0x48372) Setting any of the above clock control bits (initially 1) to 0 turns off the corresponding clock supply to the BBCU. III-2-22 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) Setting both the clock control bit and automatic control bit (initially 0) for any clock supply to 1 enables the automatic control function for that clock supply. If the BBCU enters the IDLE state with the automatic control function enabled, clock-enable signal input to the CMU is negated. Accordingly, the CMU stops clock supply to the BBCU. This state is called the power-down mode of the BBCU. When an operation request to the BBCU is generated by any block, the BBCU immediately reasserts the clock-enable signal. Clock supply from the CMU resumes one clock after the clock-enable signal becomes active. Note: The clock supply should be automatically controlled to reduce the amount of power consumed on the chip. Note that some limits are imposed on the supported operating clock frequency, etc. For details, see Section II.3, "Clock Management Unit (CMU)." Clock state in standby mode The supply of CCLK stops depending on the type of standby mode. HALT mode: CCLK is supplied the same way as in normal mode. HALT2 mode: The supply of CCLK stops. SLEEP mode: The supply of CCLK stops. Therefore, the BBCU also stops operating when in HALT2 or SLEEP mode. III.2.8.2 Generation of the Bus Clock The BBCU divides CCLK by a specified number to generate the bus clock (BCLK). This divide-by ratio is set by using BCLKD[1:0] (D[1:0]/0x48380). BCLKD[1:0]: BCLK Setup Bits in the BCLK Divide Control Register (D[1:0]/0x48380) BBCU Table III.2.8.2.1 BCLK (CCLK Divide-by Ratio) Settings BCLKD1 BCLKD0 BCLK frequency 1 1 0 0 1 0 1 0 CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 When initially reset, the BCLK clock is set to CCLK*1/8. III.2.8.3 External Output of the Bus Clock Standard specifications of the S1C33 series categorize BCLK output as an extended port function. Therefore, before BCLK can be output to external devices, the pin function must be switched for BCLK output by using the Function Select Register for the corresponding port. For details of the pins assigned to the BCLK output function and how to switch the pin functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." S1C33401 TECHNICAL MANUAL EPSON III III-2-23 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.9 Bus Access Timing Chart Note: Except for Figure III.2.9.4.2 in Section III.2.9.4, "BCLK Synchronous/Asynchronous Memory Access Timing," all timing charts shown here are for BCLK asynchronous access. III.2.9.1 SRAM Read/Write Timing (with no External WAIT) 1. SRAM read timings with different CExMLT settings [Example settings 1] CE cycle: 6 clocks RD start state: 2 clocks RD end state: 2 clocks Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Enabled CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable Output disable Figure III.2.9.1.1 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x1) CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable Output disable Figure III.2.9.1.2 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x2) CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable Output disable Figure III.2.9.1.3 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x4) III-2-24 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 2. SRAM read timings in A0 and BSL modes [Example settings 2] Access cycle multiply-by factor: x2 CE cycle: 3 clocks RD start state: 1 clock RD end state: 1 clock Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled CCLK A[31:0] valid (1) valid (2) #CEx #RD D[31:16] D[15:0] invalid valid (2) valid (1) invalid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable RD start RD end CE cycle Access disable Output disable Figure III.2.9.1.4 SRAM Read Timing in Example Settings 2 (for A0 Mode Halfword Read) III CCLK BBCU A[31:0] valid (1) valid (2) #CEx #BSH #BSL #RD D[31:16] D[15:0] invalid valid (2) valid (1) invalid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable RD start RD end CE cycle Access disable Output disable Figure III.2.9.1.5 SRAM Read Timing in Example Settings 2 (for BSL Mode Halfword Read) S1C33401 TECHNICAL MANUAL EPSON III-2-25 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 3. SRAM read timings with access disable or output disable cycle [Example settings 3] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 2 clocks RD end state: 1 clock Access-disable cycle: 2 clocks Output-disable cycle: 0 clocks RD start state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Access disable Figure III.2.9.1.6 SRAM Read Timing in Example Settings 3 [Example settings 4] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 2 clocks RD end state: 1 clock Access-disable cycle: 0 clocks Output-disable cycle: 2 clocks RD start state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx Another #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Output disable Figure III.2.9.1.7 SRAM Read Timing in Example Settings 4 III-2-26 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 4. SRAM read timings with different parameter combinations [Example settings 5] Access cycle multiply-by factor: x2 CE cycle: 7 clocks RD start state: 2 clocks RD end state: 1 clock Access-disable cycle: 0 clocks Output-disable cycle: 0 clocks RD start state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start RD end CE cycle Figure III.2.9.1.8 SRAM Read Timing in Example Settings 5 [Example settings 6] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 1 clock RD end state: 0 clocks III Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Enabled BBCU CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB RD start CE cycle Access disable Output disable Figure III.2.9.1.9 SRAM Read Timing in Example Settings 6 S1C33401 TECHNICAL MANUAL EPSON III-2-27 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 5. SRAM write timings with different CExMLT settings [Example settings 7] CE cycle: 6 clocks WR start state: 2 clocks WR end state: 2 clocks Access-disable cycle: 2 clocks WR start state -0.5 clock option: Enabled WR end state -0.5 clock option: Enabled CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB WR start WR end CE cycle Access disable Figure III.2.9.1.10 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x1) CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB WR start WR end CE cycle Access disable Figure III.2.9.1.11 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x2) CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB WR start WR end CE cycle Access disable Figure III.2.9.1.12 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x4) III-2-28 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 6. SRAM write timings in A0 and BSL modes [Example settings 8] Access cycle multiply-by factor: x2 CE cycle: 4 clocks WR start state: 1 clock WR end state: 1 clock Access-disable cycle: 1 clock WR start state -0.5 clock option: Disabled WR end state -0.5 clock option: Disabled CCLK A[31:0] valid (1) valid (2) invalid valid (2) valid (1) invalid #CEx #WRH #WRL D[31:16] D[15:0] #RDWR (internal signal) ASTB WR start WR end CE cycle Access disable WR end WR start CE cycle Access disable III Figure III.2.9.1.13 SRAM Write Timing in Example Settings 8 (for A0 Mode Halfword Write) CCLK BBCU A[31:0] valid (1) valid (2) invalid valid (2) valid (1) invalid #CEx #BSH #BSL #WR D[31:16] D[15:0] #RDWR (internal signal) ASTB WR start WR end CE cycle Access disable WR start WR end CE cycle Access disable Figure III.2.9.1.14 SRAM Write Timing in Example Settings 8 (for BSL Mode Halfword Write) S1C33401 TECHNICAL MANUAL EPSON III-2-29 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 7. SRAM write timings with different parameter combinations [Example settings 9] Access cycle multiply-by factor: x2 CE cycle: 7 clocks WR start state: 2 clocks WR end state: 2 clocks Access-disable cycle: 0 clocks WR start state -0.5 clock option: Enabled WR end state -0.5 clock option: Enabled CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB WR start WR end CE cycle Figure III.2.9.1.15 SRAM Write Timing in Example Settings 9 [Example settings 10] Access cycle multiply-by factor: x2 CE cycle: 4 clocks WR start state: 2 clocks WR end state: 0 clocks Access-disable cycle: 2 clocks WR start state -0.5 clock option: Disabled WR end state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB WR start CE cycle Access disable Figure III.2.9.1.16 SRAM Write Timing in Example Settings 10 III-2-30 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.9.2 SRAM Read/Write Timing (with External WAIT) A wait cycle can be inserted from external pin #WAIT only when the selected device type is SRAM, with WAITEN (D0/0x48384) set to 1 (enabled). WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384) The external #WAIT signal is sampled on the rising edges of CCLK at one clock (CCLK) before the read or write signal goes high. A wait state is entered while the #WAIT signal is sampled active (low), and subsequent operation resumes when the #WAIT signal is sampled inactive (high). Note: Within the BBCU, the #WAIT signal is sampled synchronously with the core system clock (CCLK). Therefore, if the #WAIT signal is derived from BCLK, a wait request may not be input in time during the sampling period, resulting in no wait cycles being inserted (especially with BCLK asynchronous), depending on the relationship between CCLK and BCLK. 1. SRAM read timings with external WAIT input [Example settings 11] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 1 clock RD end state: 1 clock Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled CCLK III A[31:0] valid BBCU #CEx #RD D[31:0] valid #RDWR (internal signal) ASTB #WAIT RD end RD start Wait cycle CE cycle Access disable Output disable Figure III.2.9.2.1 SRAM Read Timing in Example Settings 11 S1C33401 TECHNICAL MANUAL EPSON III-2-31 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 2. SRAM write timings with external WAIT input [Example settings 12] Access cycle multiply-by factor: x2 CE cycle: 4 clocks WR start state: 1 clock WR end state: 1 clock Access-disable cycle: 1 clock WR start state -0.5 clock option: Disabled WR end state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB #WAIT WR end WR start Wait cycle CE cycle Access disable Figure III.2.9.2.2 SRAM Write Timing in Example Settings 12 [Example settings 13] Access cycle multiply-by factor: x2 CE cycle: 4 clocks WR start state: 1 clock WR end state: 1 clock Access-disable cycle: 1 clock WR start state -0.5 clock option: Disabled WR end state -0.5 clock option: Enabled CCLK A[31:0] valid #CEx #WR D[31:0] valid #RDWR (internal signal) ASTB #WAIT WR start WR end Wait cycle CE cycle Access disable Figure III.2.9.2.3 SRAM Write Timing in Example Settings 13 III-2-32 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.9.3 Burst ROM Page Read Timing A page read cycle occurs when the CE5, CE8, or CE10 area is set to burst ROM and accessed for either a "refill request from the cache" or "load instruction from the DMAC." Note that 16-bit and 32-bit types of burst ROM (flash) are supported. When the device type is set to burst ROM, be sure to set a device size of either 16 bits or 32 bits. 1. Burst ROM read timings with different CExMLT settings [Example settings 14] CE cycle: 6 clocks RD start state: 2 clocks Page read cycle: 1 clock RD end state: 2 clocks Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Enabled CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD D[31:0] valid (1) valid (3) valid (2) valid (4) #RDWR (internal signal) ASTB III Page read access RD start Page read access Page read access RD end Access disable Output disable BBCU CE cycle Figure III.2.9.3.1 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x1) CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD D[31:0] valid (1) valid (3) valid (2) valid (4) #RDWR (internal signal) ASTB Page read access RD start Page read access Page read access RD end Access disable Output disable CE cycle Figure III.2.9.3.2 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x2) CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD D[31:0] valid (1) valid (2) valid (3) valid (4) #RDWR (internal signal) ASTB RD start Page read access Page read access Page read access RD end Access disable Output disable CE cycle Figure III.2.9.3.3 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x4) S1C33401 TECHNICAL MANUAL EPSON III-2-33 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 2. Burst ROM read timings with access disable or output disable cycle [Example settings 15] Access cycle multiply-by factor: x2 CE cycle: 3 clocks RD start state: 1 clock Page read cycle: 1 clock RD end state: 1 clock Access-disable cycle: 2 clocks Output-disable cycle: 0 clocks RD start state -0.5 clock option: Disabled CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD D[31:0] valid (1) valid (3) valid (2) valid (4) #RDWR (internal signal) ASTB Page read access RD start Page read access Page read access RD end Access disable CE cycle Figure III.2.9.3.4 Page Read Timing in Example Settings 15 [Example settings 16] Access cycle multiply-by factor: x2 CE cycle: 3 clocks RD start state: 1 clock Page read cycle: 1 clock RD end state: 1 clock Access-disable cycle: 0 clocks Output-disable cycle: 2 clocks RD start state -0.5 clock option: Disabled CCLK A[31:4] valid A[3:2] 00 01 10 11 #CEx #RD D[31:0] valid (1) valid (2) valid (3) valid (4) #RDWR (internal signal) ASTB RD start Page read access Page read access Page read access RD end Output disable CE cycle Figure III.2.9.3.5 Page Read Timing in Example Settings 16 III-2-34 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 3. Burst ROM read timings with different parameter combinations [Example settings 17] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 1 clock Page read cycle: 2 clocks RD end state: 1 clock Access-disable cycle: 0 clocks Output-disable cycle: 0 clocks RD start state -0.5 clock option: Disabled CCLK A[31:4] valid A[3:2] 11 10 01 00 #CEx #RD D[31:0] valid (1) valid (4) valid (3) valid (2) #RDWR (internal signal) ASTB Page read access RD start Page read access Page read access RD end CE cycle Figure III.2.9.3.6 Page Read Timing in Example Settings 17 [Example settings 18] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 2 clocks Page read cycle: 1 clock III BBCU RD end state: 0 clocks Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Enabled CCLK A[31:4] valid A[3:2] 00 01 10 11 #CEx #RD D[31:0] valid (1) valid (2) valid (3) valid (4) #RDWR (internal signal) ASTB RD start CE cycle Page read access Page read access Page read access Access disable Output disable Figure III.2.9.3.7 Page Read Timing in Example Settings 18 S1C33401 TECHNICAL MANUAL EPSON III-2-35 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.9.4 BCLK Synchronous/Asynchronous Memory Access Timing [Example settings 19] Access cycle multiply-by factor: x2 CE cycle: 4 clocks RD start state: 1 clock RD end state: 1 clock Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) BCLK RD start RD end CE cycle Access disable Output disable Figure III.2.9.4.1 BCLK Asynchronous Read Access (CExBCKSYN = 0) CCLK A[31:0] valid #CEx #RD D[31:0] valid #RDWR (internal signal) BCLK RD start (Note) RD end CE cycle Access disable Output disable Figure III.2.9.4.2 BCLK Synchronous Read Access (CExBCKSYN = 1) CExBCKSYN: Bus Clock Synchronization Select Bit in the CEx Area Configuration Register (D5/0x48388 + 4*(x - 4)) Note: Although the address, #CEx, and other signals become active asynchronously with the rising edges of BCLK for BCLK synchronous access, the actual access cycle starts from the rising edge of BCLK. III-2-36 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.9.5 SRAM Access when Device Size < Data Size [Example settings 20] Access cycle multiply-by factor: x1 CE cycle: 4 clocks RD start state: 1 clock RD end state: 1 clock Access-disable cycle: 1 clock Output-disable cycle: 1 clock RD start state -0.5 clock option: Disabled Device size: 16 bits Data size: 32 bits 1. 32-bit data read from 16-bit SRAM device CCLK A[31:0] valid A valid A + 2 #CEx #RD D[15:0] valid valid Figure III.2.9.5.1 32-bit Data Read from 16-bit SRAM Device In the diagram above, a 16-bit SRAM device connected to the bus is accessed in units of words (in 32 bits). For example, the HBCU supplies address "valid A" to the BBCU, which accesses internal SRAM twice in units of 16 bits to compose 32-bit data before the data is passed to the HBCU. Each 16-bit access timing is the same as the normal read/write timing. 2. 32-bit data read from 16-bit burst ROM CCLK A[31:0] valid A valid A + 2 #CEx #RD D[15:0] valid valid Figure III.2.9.5.2 32-bit Data Read from 16-bit Burst ROM The timing chart above shows a case where data is read from 16-bit burst ROM by a single, 32-bit read operation. Although instructions from the HBCU, etc. are for a single transfer, when the target device is burst ROM, 16-bit data is read twice by a page read operation to compose 32-bit data. S1C33401 TECHNICAL MANUAL EPSON III-2-37 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.10 External Bus Requests and Release of Bus Control Although the BBCU and EBCU (SDRAMC) normally manage the external bus in the C33 ADV, the C33 ADV allows bus control to be released to external bus masters. Setting EBUSMST (D1/0x48384) to 1 enables this function (since it is disabled by default). EBUSMST: External Bus Master Enable Bit in the Bus Control Register (D1/0x48384) The #BUSREQ and #BUSACK pins are used to control the release of bus control to external bus masters. The following shows the sequence in which bus control is released. 1. The external bus master device requesting bus control drives the #BUSREQ pin low. 2. The BBCU always monitors the #BUSREQ pin status, so that when the pin is driven low, the BBCU drives the #BUSACK pin low after completion of the bus cycle being executed to let the EBCU (SDRAMC) terminate the bus cycle being executed. The BBCU also places the signals shown below in the high-impedance state. A[31:0], D[31:0], #CE4-#CE11, #RD, #WRLL(#WRL), #WRLH(#WRH), #WRHL, #WRHH 3. One cycle after the #BUSACK pin is driven low, the external bus master starts its own bus cycle. The external bus master must hold the #BUSREQ pin low until its bus cycle is completed. 4. After completion of the required bus cycle, the external bus master places the bus in the high-impedance state to return the #BUSREQ pin back high. 5. The BBCU drives the #BUSACK pin back high two cycles after detecting the return of the #BUSREQ pin to high, and resumes processing after the elapse of one clock period. CCLK Sync #BUSREQ Sync #BUSACK The S1C33 The external bus master terminates the bus cycle being executed. 1 cycle 1 cycle controls bus cycles. 2 cycles The S1C33 1 cycle controls bus cycles. D[31:0] A[31:0] #RD, #WR Figure III.2.10.1 External Bus Release Timing When bus control must be returned to the BBCU or EBCU while an external bus master retains bus control (e.g., SDRAM refresh request for the EBCU), the BBCU or EBCU drives the #BUSGET pin high. External bus masters should always monitor the #BUSGET pin status, and when the #BUSGET pin is detected high, the external bus master concerned should terminate the bus cycle and return the #BUSREQ pin to high. When required processing is completed and the #BUSGET pin returns to low, external bus masters can request bus control again. For reference information, see the bus release sequence for when SDRAM refresh occurs, as described in Section III.3.6.4, "SDRAM Refresh Request when External Bus is Released." Note: The #BUSREQ, #BUSACK, and #BUSGET pins are shared with general-purpose input/output ports or other peripheral circuit input/output pins. In the initial state, these pins are normally set for other than the bus request function. Before the #BUSREQ, #BUSACK, and #BUSGET signals can be used, the pin functions must be switched over by using the Port Function Select Register for the respective pins. For details about the pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." III-2-38 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.11 Control Register Details Table III.2.11.1 BBCU Register List Address 0x00048380 0x00048384 Register name BCLK Divide Control Register (pBBCU_BCLK_DIV) Bus Control Register (pBBCU_BUSCTL) 0x00048386 0x00048388 0x0004838A 0x0004838C 0x0004838E 0x00048390 0x00048392 0x00048394 0x00048396 0x00048398 0x0004839A 0x0004839C 0x0004839E 0x000483A0 0x000483A2 0x000483A4 0x000483A6 Common Cycle Control Register (pBBCU_CM_CYC) CE4 Area Configuration Register (pBBCU_CE4SET) CE4 Access Cycle Control Register (pBBCU_CE4ACCNT) CE5 Area Configuration Register (pBBCU_CE5SET) CE5 Access Cycle Control Register (pBBCU_CE5ACCNT) CE6 Area Configuration Register (pBBCU_CE6SET) CE6 Access Cycle Control Register (pBBCU_CE6ACCNT) CE7 Area Configuration Register (pBBCU_CE7SET) CE7 Access Cycle Control Register (pBBCU_CE7ACCNT) CE8 Area Configuration Register (pBBCU_CE8SET) CE8 Access Cycle Control Register (pBBCU_CE8ACCNT) CE9 Area Configuration Register (pBBCU_CE9SET) CE9 Access Cycle Control Register (pBBCU_CE9ACCNT) CE10 Area Configuration Register (pBBCU_CE10SET) CE10 Access Cycle Control Register (pBBCU_CE10ACCNT) CE11 Area Configuration Register (pBBCU_CE11SET) CE11 Access Cycle Control Register (pBBCU_CE11ACCNT) Size Function 16 Sets BCLK. 16 Selects burst ROM and enables external bus master and external WAIT. 16 Sets page read cycle. 16 Sets CE4 area device information. 16 Sets CE4 area access timing conditions. 16 Sets CE5 area device information. 16 Sets CE5 area access timing conditions. 16 Sets CE6 area device information. 16 Sets CE6 area access timing conditions. 16 Sets CE7 area device information. 16 Sets CE7 area access timing conditions. 16 Sets CE8 area device information. 16 Sets CE8 area access timing conditions. 16 Sets CE9 area device information. 16 Sets CE9 area access timing conditions. 16 Sets CE10 area device information. 16 Sets CE10 area access timing conditions. 16 Sets CE11 area device information. 16 Sets CE11 area access timing conditions. Each BBCU control register is described below. The BBCU control registers are mapped to the 16-bit device area at addresses 0x48380 to 0x483A6, and can be accessed in units of halfwords or bytes. S1C33401 TECHNICAL MANUAL EPSON III-2-39 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 0x48380: BCLK Divide Control Register (pBBCU_BCLK_DIV) Register name Address Bit Name 0048380 D15-2 - BCLK divide D1 BCLKD1 (HW) control register D0 BCLKD0 (pBBCU_BCLK _DIV) Function Setting reserved BCLK setup (CCLK division ratio) - BCLKD[1:0] 11 10 01 00 Init. R/W BCLK CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 0 1 1 Remarks - Writing 1 not allowed. R/W D[15:2] Reserved D[1:0] BCLKD[1:0]: BCLK Setup Bits BCLK is the clock for external buses and generated from the core system clock (CCLK) by being divided by a specified number. BCLKD[1:0] is used to select this divide-by ratio. Table III.2.11.2 Selection of BCLK III-2-40 BCLKD1 BCLKD0 1 1 0 0 1 0 1 0 BCLK frequency CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 (Default: 0b11 = CCLK*1/8) EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 0x48384: Bus Control Register (pBBCU_BUSCTL) Register name Address Bit Name Function reserved BUS control 0048384 D15-7 - D6 BROM_CE10 CE10 area burst ROM select register (HW) D5 BROM_CE8 CE8 area burst ROM select (pBBCU_BUSCTL) D4 BROM_CE5 CE5 area burst ROM select D3 - reserved D2 ASTBW ASTB pulse width D1 EBUSMST External bus master enable D0 WAITEN Wait enable Setting - 1 Used 1 Used 1 Used 0 Not used 0 Not used 0 Not used - 1 2 clocks 1 Enabled 1 Enabled 0 1 clock 0 Disabled 0 Disabled Init. R/W 0 0 0 0 0 0 0 0 Remarks - Writing 1 not allowed. R/W R/W R/W - Writing 1 not allowed. R/W R/W R/W D[15:7] Reserved D6 BROM_CE10: CE10 Area Burst ROM Select Bit Note 1 This bit specifies the use of burst ROM in the CE10 area (Areas 10, 13, 20). This setting is only effective when CE10EBCU (D10/0x483A0) = 0. 1 (R/W): Use burst ROM 0 (R/W): Do not use burst ROM (default) D5 BROM_CE8: CE8 Area Burst ROM Select Bit Note 1 This bit specifies the use of burst ROM in the CE8 area (Areas 8, 21). This setting is only effective when CE8EBCU (D10/0x48398) = 0. 1 (R/W): Use burst ROM 0 (R/W): Do not use burst ROM (default) D4 BROM_CE5: CE5 Area Burst ROM Select Bit Note 1 This bit specifies the use of burst ROM in the CE5 area (Areas 5, 15, 16). This setting is only effective when CE5EBCU (D10/0x4838C) = 0. 1 (R/W): Use burst ROM 0 (R/W): Do not use burst ROM (default) Note 1: Write-accessing the area for which burst ROM is the device type selected by BROM_CE10, BROM_CE8, or BROM_CE5 executes an SRAM-type write cycle. In this case, wait control by the #WAIT signal is effective. D3 Reserved D2 ASTBW: ASTB Pulse Width Bit This bit selects the pulse width of the address strobe (ASTB) output by the BBCU when starting external bus access. 1 (R/W): 2 clocks 0 (R/W): 1 clock (default) The ASTB pulse can be externally output by setting the relevant port as required. For details about port assignments and how to switch over the port functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." Note: The actual pulse width equals this selected number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). D1 EBUSMST: External Bus Master Enable Bit This bit enable/disables the function to release bus control to external bus masters. 1 (R/W): Enable 0 (R/W): Disable (default) D0 WAITEN: Wait Enable Bit This bit enables or disables wait control exercised using the #WAIT signal (#WAIT pin input) by external/internal devices. 1 (R/W): Enable 0 (R/W): Disable (default) S1C33401 TECHNICAL MANUAL EPSON III-2-41 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 0x48386: Common Cycle Control Register (pBBCU_CM_CYC) Register name Address Bit Name Function Setting reserved Common cycle 0048386 D15-4 - D3 PGRD_CYC3 Number of read cycles in page (HW) control register D2 PGRD_CYC2 mode (pBBCU_CM_CYC) D1 PGRD_CYC1 D0 PGRD_CYC0 Init. R/W - PGRD_CYC[3:0] # of clocks 1111 16 x (CExMLT) : : 0000 1 x (CExMLT) 0 1 1 1 1 Remarks - Writing 1 not allowed. R/W D[15:4] Reserved D[3:0] PGRD_CYC[3:0]: Number of Page Read Cycle Bits These bits set the number of clocks that comprise a page read cycle for read operation from burst ROM connected to the CE5, CE8, or CE10 area. A page read cycle occurs when a refill request from the cache or read request from the DMAC is received. Table III.2.11.3 Page Read Cycle Settings PGRD_CYC3 PGRD_CYC2 PGRD_CYC1 PGRD_CYC0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Page read cycle 16 clocks 15 clocks 14 clocks 13 clocks 12 clocks 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b1111 = 16 clocks) Note: The actual cycle equals this selected number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). III-2-42 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 0x48388-0x483A4: CEx Area Configuration Registers (pBBCU_CExSET) Register name Address Name Bit Function 0048388 D15-14 - CEx area D13 CExIO | configuration 00483A4 D12 CExBIG register D11 CExBSL (HW) (pBBCU_CExSET) D10 CExEBCU D9 CExDVSZ1 D8 CExDVSZ0 D7-6 D5 D4 D3 D2 D1 D0 - CExBCKSYN CExWSTHCK CExWEDHCK CExRSTHCK CExODISC1 CExODISC0 Setting reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Init. R/W - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CExDVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 0 Disabled 1 Enabled RD start state option (-0.5 clk) 1 Enabled 0 Disabled Output disable cycle configuration CExODISC[1:0] # of clocks 11 3 x (CExMLT) 10 2 x (CExMLT) 01 1 x (CExMLT) 00 0 clocks Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W Note: The letter `x' in bit names, etc. denotes the CE area number (4 to 11). 0x48388 0x4838C 0x48390 0x48394 0x48398 0x4839C 0x483A0 0x483A4 CE4 Area Configuration Register (pBBCU_CE4SET) CE5 Area Configuration Register (pBBCU_CE5SET) CE6 Area Configuration Register (pBBCU_CE6SET) CE7 Area Configuration Register (pBBCU_CE7SET) CE8 Area Configuration Register (pBBCU_CE8SET) CE9 Area Configuration Register (pBBCU_CE9SET) CE10 Area Configuration Register (pBBCU_CE10SET) CE11 Area Configuration Register (pBBCU_CE11SET) III BBCU D[15:14] Reserved D13 CExIO: External/Internal Access Setting Bit This bit selects use of the CEx area for an external device or internal device. 1 (R/W): Internal device 0 (R/W): External device (default) D12 CExBIG: Endian Mode Select Bit This bit selects endian mode for the CEx area. 1 (R/W): Big endian 0 (R/W): Little endian (default) D11 CExBSL: External Interface Mode Select Bit This bit selects interface mode (A0 or BSL) for the CEx area. 1 (R/W): BSL mode 0 (R/W): A0 mode (default) Table III.2.11.4 Bus Control Signal Pin Functions in A0/BSL Mode Pin name #CEx #RD #BSLL(#BSL) #WRLL(#WRL) #WRLH(#WRH) #WRHL #WRHH S1C33401 TECHNICAL MANUAL BSL mode A0 mode (default) #CEx #RD Unused #WRLL(#WRL) #WRLH(#WRH) #WRHL #WRHH Little endian Big endian #CEx #RD #BSLL(#BSL) #WR #BSLH(#BSH) #BSHL #BSHH #CEx #RD #BSLH(#BSH) #WR #BSLL(#BSL) #BSHH #BSHL EPSON III-2-43 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) D10 CExEBCU: Device Type Select Bit This bit selects the device type for the CEx area. 1 (R/W): EBCU device (SDRAM) 0 (R/W): BBCU device (SRAM, default) Burst ROM can be selected as the device type for the CE5, CE8, or CE10 area by setting this bit to 0 and BROM_CEx (D[6:4]/0x48384) to 1. Table III.2.11.5 Selection of Device Type CExEBCU BROM_CEx * Device type 1 0 0 X 1 0 SDRAM Burst ROM * SRAM Burst ROM can only be selected for the CE5, CE8, and CE10 areas. D[9:8] CExDVSZ[1:0]: Device Size Select Bits This bit selects the device size for the CEx area. Table III.2.11.6 Selection of Device Size CExDVSZ1 CExDVSZ0 1 1 0 0 1 0 1 0 Device size Connected data bus D[31:0] (Note) 32 bits D[31:16] (Note) 16 bits (16 high-order data bus bits) D[15:0] 16 bits (16 low-order data bus bits) D[7:0] 8 bits (Default: 0b01 = 16 bits (16 low-order data bus bits)) Note: For C33 ADV models with 16 external data bus pins, D[15:0], 32 bits or 16 bits (16 high-order data bus bits) may be selected for the device size only when using an internal device. D[7:6] Reserved D5 CExBCKSYN: Bus Clock Synchronization Select Bit This bit selects whether read/write signals are to be output synchronously with BCLK. 1 (R/W): Synchronous (default) 0 (R/W): Asynchronous With initial settings, read/write signals are output synchronously with BCLK. Be sure to use external devices connected to the system and clocked by BCLK with this setting. When this bit is set to 0, read/write signals are output asynchronously with BCLK. This setting may result in reduced bus cycles. In the BBCU, bus control signals are generated synchronously with CCLK. D4 CExWSTHCK: WR Start State Option (-0.5 clock) Select Bit This bit selects the WR start state option. When this option is selected, the write signal is asserted 0.5 cycle before the set timing. 1 (R/W): Enable the option 0 (R/W): Disable the option (default) Notes: * If this option is specified when the actual WR start state is one clock, valid write data will not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock period is required before write data can be set up after #CE is asserted. * The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)) does not apply to the WR start state option (-0.5 clock). * When the CCLK frequency is 49 MHz or higher, do not enable the WR start state option (-0.5 clock). III-2-44 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) D3 CExWEDHCK: WR End State Option (-0.5 clock) Select Bit This bit selects the WR end state option. When this option is selected, the write signal is asserted 0.5 cycle after the set timing. 1 (R/W): Enable the option 0 (R/W): Disable the option (default) Notes: * The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)) does not apply to the WR end state option (-0.5 clock). * When the CCLK frequency is 49 MHz or higher, do not enable the WR end state option (-0.5 clock). * If the number of WR end state cycles is set to 0 clock by CExWRENDC[1:0] (D[9:8]/0x4838A + 4*(x - 4)), the WR end state option (-0.5 clock) is ignored. D2 CExRSTHCK: RD Start State Option (-0.5 clock) Select Bit This bit selects the RD start state option. When this option is selected, the read signal is asserted 0.5 cycle before the set timing. 1 (R/W): Enable the option 0 (R/W): Disable the option (default) Notes: * The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)) does not apply to the RD start state option (-0.5 clock). * If the CCLK frequency is 49 MHz or higher, do not enable the RD start state option (-0.5 clock). D[1:0] CExODISC[1:0]: Output-Disable Cycle Configuration Bits These bits set the number of output-disable cycles to be inserted before the next CE cycle begins after data read operation. Table III.2.11.7 Output-Disable Cycle Settings CExODISC1 CExODISC0 1 1 0 0 1 0 1 0 Output disable cycle 3 clocks 2 clocks 1 clock 0 clocks (Default: 0b11 = 3 clocks) The output-disable cycle specified here is inserted before the next CE cycle starts after completion of a separately specified access-disable cycle (or after the end of the preceding CE cycle if no access-disable cycles are inserted). The following shows the conditions when the output-disable cycle is inserted. * The output-disable cycle is always inserted during read access. * The output-disable cycle is inserted immediately after an access-disable cycle (or immediately after a CE cycle if no access-disable cycles are set). * For read access where data size > device size, the output-disable cycle is only inserted during the last access. * For page read access to burst ROM and burst read access from other than burst ROM (four consecutive words), the output-disable cycle is inserted in the last access made. * No output-disable cycle is inserted during write access. * No output-disable cycle is inserted during consecutive access to the same area. Note: The actual cycle equals this selected number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). S1C33401 TECHNICAL MANUAL EPSON III-2-45 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) 0x4838A-0x483A6: CEx Access Cycle Control Registers (pBBCU_CExACCNT) Register name Address Bit Name 004838A | 00483A6 (HW) D15 D14 CExMLT1 CExMLT0 D13 D12 CExADISC1 Access disable state setup CExADISC0 D11 D10 CExWRSTAC1 Write start state setup CExWRSTAC0 D9 D8 CExWRENDC1 Write end state setup CExWRENDC0 D7 D6 CExRDSTAC1 Read start state setup CExRDSTAC0 D5 D4 CExRDENDC1 Read end state setup CExRDENDC0 D3 D2 D1 D0 CExCE3 CExCE2 CExCE1 CExCE0 CEx access cycle control register (pBBCU _CExACCNT) Function Access cycle multiple mode select CE cycle setup Setting Init. R/W CExMLT[1:0] Multiple mode 1 x4 01 x2 00 x1 CExADISC[1:0] # of clocks 11 3 x (CExMLT) 10 2 x (CExMLT) 01 1 x (CExMLT) 00 0 clocks CExWRSTAC[1:0] # of clocks 4 x (CExMLT) 11 3 x (CExMLT) 10 2 x (CExMLT) 01 1 x (CExMLT) 00 CExWRENDC[1:0] # of clocks 11 3 x (CExMLT) 10 2 x (CExMLT) 01 1 x (CExMLT) 00 0 clocks CExRDSTAC[1:0] # of clocks 11 4 x (CExMLT) 10 3 x (CExMLT) 01 2 x (CExMLT) 00 1 x (CExMLT) CExRDENDC[1:0] # of clocks 11 3 x (CExMLT) 10 2 x (CExMLT) 01 1 x (CExMLT) 00 0 clocks CExCE[3:0] # of clocks 1111 16 x (CExMLT) : : 0000 1 x (CExMLT) 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W Remarks Note: The letter `x' in bit names, etc. denotes the CE area number (4 to 11). 0x4838A 0x4838E 0x48392 0x48396 0x4839A 0x4839E 0x483A2 0x483A6 CE4 Access Cycle Control Register (pBBCU_CE4ACCNT) CE5 Access Cycle Control Register (pBBCU_CE5ACCNT) CE6 Access Cycle Control Register (pBBCU_CE6ACCNT) CE7 Access Cycle Control Register (pBBCU_CE7ACCNT) CE8 Access Cycle Control Register (pBBCU_CE8ACCNT) CE9 Access Cycle Control Register (pBBCU_CE9ACCNT) CE10 Access Cycle Control Register (pBBCU_CE10ACCNT) CE11 Access Cycle Control Register (pBBCU_CE11ACCNT) D[15:14] CExMLT[1:0]: Access Cycle Multiple Mode Select Bits These bits set the multiply-by factor applied to the number of clocks that specify various access cycle timings. Various cycles specified by a number of clocks for each area are specified in terms of core clock CCLK counts. The duration of respective cycles can be multiplied by 1, 2, or 4. Table III.2.11.8 Access Cycle Multiply-by Factors III-2-46 CExMLT1 CExMLT0 1 0 0 X 1 0 Multiply-by factor x4 x2 x1 (Default: 0x11 = x4) EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) D[13:12] CExADISC[1:0]: Access Disable State Setup Bits Note 1 These bits set the access-disable cycle inserted before the next CE cycle begins after data access (after the end of the preceding CE cycle). Table III.2.11.9 Access-Disable Cycle Settings CExADISC1 CExADISC0 1 1 0 0 1 0 1 0 Access disable cycle 3 clocks 2 clocks 1 clock 0 clocks (Default: 0b11 = 3 clocks) The access-disable cycle set here is inserted before the next CE cycle or an output-disable cycle starts after completion of a separately specified CE cycle. The following shows the conditions when the access-disable cycle is inserted. * The access-disable cycle is always inserted when accessing the CE area for either read or write. * The access-disable cycle is inserted immediately after a CE cycle (or after any RD/WR end state set). * The access-disable cycle is also inserted when accessing the same area successively (including when data size > device size). * For page read access to burst ROM, the access-disable cycle is inserted immediately after a CE cycle that includes a series of page read cycles (or after any RD end state set). * For burst transfer to other than burst ROM (four or eight consecutive words), the access-disable cycle is inserted for every four or eight words transferred. D[11:10] CExWRSTAC[1:0]: Write Start State Setup Bits Note 1 These bits set the timing at which the write signal is asserted. BBCU Table III.2.11.10 WR Start State Settings CExWRSTAC1 CExWRSTAC0 1 1 0 0 1 0 1 0 WR start state 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b01 = 2 clocks) This setting selects the number of CCLK clocks until the write signal becomes active (goes low). The starting point of the WR start state varies depending on the bus clock synchronization mode selected by CExBCKSYN (D5/0x48388 + 4*(x - 4)). When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 0), this setting indicates the number of CCLK clocks from the first rise of BCLK after assertion of the #CEx signal to when the write signal becomes active (goes low). When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 1), this setting indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when the write signal becomes active (goes low). The write signal can be asserted 0.5 cycle before the set timing by setting CExWSTHCK (D4/0x48388 + 4*(x - 4)) to 1. Note that if this option is specified when the actual WR start state is one clock, valid write data will not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock period is required before write data can be set up after #CE is asserted. S1C33401 TECHNICAL MANUAL EPSON III III-2-47 III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) D[9:8] CExWRENDC[1:0]: Write End State Setup Bits Note 1 These bits set the timing at which the write signal is deasserted. Table III.2.11.11 WR End State Settings CExWRENDC1 CExWRENDC0 1 1 0 0 1 0 1 0 WR end state 3 clocks 2 clocks 1 clock 0 clocks (Default: 0b10 = 2 clocks) Set the number of clocks (in CCLK clock units) during which the write signal becomes inactive (goes high) before a separately specified CE cycle ends. The write signal can be deasserted 0.5 cycle after the set timing by setting CExWEDHCK (D3/0x48388 + 4*(x - 4)) to 1. D[7:6] CExRDSTAC[1:0]: Read Start State Setup Bits Note 1 These bits set the timing at which the read signal is asserted. Table III.2.11.12 RD Start State Settings CExRDSTAC1 CExRDSTAC0 1 1 0 0 1 0 1 0 RD start state 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b01 = 2 clocks) This setting selects the number of CCLK clocks until the read signal becomes active (goes low). The starting point of the RD start state varies depending on the bus clock synchronization mode selected by CExBCKSYN (D5/0x48388 + 4*(x - 4)). When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 0), this setting indicates the number of CCLK clocks from the first rise of BCLK after assertion of the #CEx signal to when the read signal becomes active (goes low). When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4*(x - 4)) = 1), this setting indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when the read signal becomes active (goes low). The read signal can be asserted 0.5 cycle before the set timing by setting CExRSTHCK (D2/0x48388 + 4*(x - 4)) to 1. D[5:4] CExRDENDC[1:0]: Read End State Setup Bits Note 1 These bits set the timing at which the read signal is deasserted. Table III.2.11.13 RD End State Settings CExRDENDC1 CExRDENDC0 1 1 0 0 1 0 1 0 RD end state 3 clocks 2 clocks 1 clock 0 clocks (Default: 0b10 = 2 clocks) Set the number of clocks (in CCLK clock units) during which the read signal becomes inactive (goes high) before a separately specified CE cycle ends. III-2-48 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) D[3:0] CExCE[3:0]: CE Cycle Setup Bits Notes 1 and 2 These bits specify the CE cycle or period during which the #CEx signal is asserted (low) in one access by the number of CCLK clocks. Table III.2.11.14 CE Cycle Settings CExCE3 CExCE2 CExCE1 CExCE0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CE cycle 16 clocks 15 clocks 14 clocks 13 clocks 12 clocks 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b0111 = 8 clocks) The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in CCLK clock units) minus the number of RD/WR start and end state clocks (read/write pulse width) is equal to or less than 0, device operation for that cycle cannot be guaranteed. Note 1: The actual cycle equals this selected number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4*(x - 4)). Note 2: Do not set the number of CE cycles to one clock (CExCE[3:0] = 0b0000). It must be set to two or more clocks. S1C33401 TECHNICAL MANUAL EPSON III-2-49 III BBCU III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU) III.2.12 Precautions * Although various access timings are set by specifying the number of clocks using the registers common to all areas and registers for specific areas, the actual number of cycles applied to the access performed equals this specified number of clocks multiplied by the factor set by the CExMLT bit provided for each area. Note that when the RD/WR start state and WR end state -0.5 clock options are enabled, the access timing is only adjusted by 0.5 clock, regardless of what multiplying factor is set by the CExMLT bit. * Note that in a system where A0 and BSL-mode SRAMs coexist in the memory map, executing write or read access in BSL mode followed by write access in A0 mode (with access-disable and output-disable cycles for the BSL-mode area both set to 0 clock) may corrupt the data in A0-mode SRAM. If such access is likely to occur, make sure the access-disable cycle for the BSL-mode area is set to 1 or more. * When the CCLK frequency is 49 MHz or higher, do not enable the RD/WR start state and WR end state options (-0.5 clock). * If the WR start state option is specified when the actual WR start state is one clock, valid write data will not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock period is required before write data can be set up after #CE is asserted. * The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in CCLK clock units) minus the number of RD/WR start and end state clocks (read/write pulse width) is equal to or less than 0, device operation for that cycle cannot be guaranteed. Furthermore, do not set the number of CE cycles to one clock (CExCE[3:0] = 0b0000). It must be set to two or more clocks. III-2-50 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3 Extended Bus Control Unit (EBCU) I III.3.1 Overview of the EBCU The Extended Bus Control Unit (EBCU) is one of the bus modules connected to the high-speed bus controlled by the HBCU, with a built-in SDRAM controller. When accessing an "EBCU device" area selected in the BBCU, the EBCU's SDRAM interface is used as the external bus interface. The functions and features of the EBCU are outlined below. * SDRAM directly connected interface * SDRAM supported area: Can be mapped to one of areas 4 to 22 (CE areas CE4 to CE11). * Data bus width: 16 or 32 bits * Bank address: Up to four banks are accommodated (with BS[1:0] output possible). * Burst length: Fixed to 1 (Burst read/write is performed by issuing commands successively.) * CAS latency: 1, 2 or 3 * Wrap type: Sequential wrap supported * Write mode: Single write operation supported III * Switchable row/column address multiplexed widths * Capable of self-refresh and auto-refresh * Programmable refresh period EBCU * Programmable timing conditions (precharge time, active command period, write recovery time, and RAS-CAS delay time) using control registers * Write in units of bytes via DQM pin possible * Selectable bank active modes (with or without auto-precharge) * Selectable SDRAM clock output (always or only at access) HBCU BBCU (SRAM Controller) Internal bus arbiter Port EBCU (SDRAM Controller) External bus SDRAM control signals DMA controller Figure III.3.1.1 Relationship between the EBCU and BBCU S1C33401 TECHNICAL MANUAL EPSON III-3-1 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.2 EBCU Pins Table III.3.2.1 lists the pins used by the EBCU. Table III.3.2.1 EBCU Pin List Pin name I/O Function A[17:0] D[31:0] SDCKE SDCLK #SDCS #SDRAS #SDCAS #SDWE DQM0(DQML*) DQM1(DQMH*) DQM2 DQM3 O I/O O O O O O O O O O O Bank select and address signal output pins (external address bus) Data signal input/output pins (external data bus) SDRAM clock-enable signal output pin SDRAM clock output pin SDRAM chip select signal output pin SDRAM row address strobe signal output pin SDRAM column address strobe signal output pin SDRAM write signal output pin SDRAM data (to select least significant byte) input/output mask signal output pin SDRAM data (to select second byte) input/output mask signal output pin SDRAM data (to select third byte) input/output mask signal output pin SDRAM data (to select most significant byte) input/output mask signal output pin * Signal names when only 16 data bus pins are available Notes: * The list above indicates the input/output pins that the EBCU can accommodate. Depending on the C33 ADV model used, the EBCU may have a different pin configuration as follows: - Address bus A[17:0] may consist of less than 18 pins. - Data bus D[31:0] may only have 16 pins, D[15:0]. - All control signal pins may not be available for some C33 ADV models. - Pin names may be different for some C33 ADV models. For details of the pin configuration of each C33 ADV model, see Section I.3, "Pin Description." * Some control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state may be set to other than the EBCU. Before the EBCU signals assigned to these pins can be used, the functions of these pins must be switched for the EBCU by setting each corresponding Port Function Select Register. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." III-3-2 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.3 Configuration of SDRAM I III.3.3.1 SDRAM Area The EBCU requires that SDRAM be located in only one of the CE4 to CE11 areas to ensure proper control. The BBCU manages the memory areas of the C33 ADV, so that before SDRAM can be used, it must be enabled for use by setting the relevant BBCU register. Since the device type can be selected for each CE area by register bit CExEBCU (D10/0x48388 + 4*(x - 4)) of the BBCU, set the corresponding CExEBCU (D10/0x48388 + 4*(x - 4)) to 1 for the area where SDRAM is to be used. CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4*(x - 4)) With initial settings, SRAM type (SRAM interface of the BBCU) is selected as the device type for all areas. For details of the areas, see Section III.2, "Basic Bus Control Unit (BBCU)." Note: Since SDRAM can only be used in one area, do not set CExEBCU (D10/0x48388 + 4*(x - 4)) to 1 for other areas. Furthermore, an external SRAM device cannot be mapped to the area configured for SDRAM. III.3.3.2 Setting SDRAM Size and Address The table below lists the conditions related to SDRAM size and address that the EBCU can accommodate. Table III.3.3.2.1 SDRAM Size/Address Related Setup Items Setup item Device size Bank address Column address width Row address width Endian mode Content III Control bit settings 32 bits 16 bits (connect to the 16 highorder data bus bits) 16 bits (connect to the 16 loworder data bus bits) Up to four banks can be accommodated 11 bits (2K) 10 bits (1K) 9 bits (512) 8 bits (256) 14 bits (16K) 13 bits (8K) 12 bits (4K) 11 bits (2K) Big endian Little endian DVSIZ[1:0] (D[13:12]/0x483C6) = 11 DVSIZ[1:0] (D[13:12]/0x483C6) = 10 DVSIZ[1:0] (D[13:12]/0x483C6) = 01 (default) EBCU - CAW[1:0] (D[9:8]/0x483C6) = 11 CAW[1:0] (D[9:8]/0x483C6) = 10 CAW[1:0] (D[9:8]/0x483C6) = 01 (default) CAW[1:0] (D[9:8]/0x483C6) = 00 RAW[1:0] (D[11:10]/0x483C6) = 11 RAW[1:0] (D[11:10]/0x483C6) = 10 RAW[1:0] (D[11:10]/0x483C6) = 01 (default) RAW[1:0] (D[11:10]/0x483C6) = 00 BIG (D15/0x483C6) = 1 BIG (D15/0x483C6) = 0 (default) Device size The SDRAM device size (data bit width) can be selected from 16 or 32 bits by using DVSIZ[1:0] (D[13:12]/ 0x483C6). 8-bit devices cannot be used. DVSIZ[1:0]: SDRAM Device Size Select Bits in the SDRAM Option Register (D[13:12]/0x483C6) Table III.3.3.2.2 Selection of SDRAM Device Size DVSIZ1 DVSIZ0 1 1 0 0 1 0 1 0 Device size 32 bits 16 bits (16 high-order data bus bits) 16 bits (16 low-order data bus bits) Settings prohibited Connected data bus D[31:0] (Note) D[31:16] (Note) D[15:0] - Note: For C33 ADV models with 16 external data bus pins, D[15:0], neither "32 bits" nor "16 bits (16 high-order data bus bits)" can be selected as the device size of external SDRAM. When initially reset, the device size is initialized to 16 bits (16 low-order data bus bits). Although the BBCU registers also have control bits CExDVSZ[1:0] (D[9:8]/0x48388 + 4*(x - 4)) to select the device size for each area, this control bit for the area for which EBCU type (SDRAM) is selected as the device type is disabled. S1C33401 TECHNICAL MANUAL EPSON III-3-3 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) SDRAM address configuration The following shows the relationship between the CPU addresses and the bank, column, and row addresses. When 16-bit SDRAM is selected (DVSIZ[1:0] (D[13:12]/0x483C6) = 01 or 10) A(m+n+2) A(m+n+1) Bank address A(m+n) ***** A(m+1) Row address A(m) ***** A1 Column address A0 DQM When 32-bit SDRAM is selected (DVSIZ[1:0] (D[13:12]/0x483C6) = 11) A(m+n+3) A(m+n+2) A(m+n+1) ***** A(m+2) Bank address Row address A(m+1) ***** A2 Column address A1 A0 DQM m: Column address size (in bits) n: Row address size (in bits) Figure III.3.3.2.1 SDRAM Addresses All high-order address bits not used due to memory size are fixed to 0. Bank address The SDRAM interface of the EBCU supports up to four banks of SDRAM. The 2 high-order bits of the SDRAM address are used as the bank address, as shown in Figure III.3.3.2.1, "SDRAM Addresses." Column address width The column address width is set by CAW[1:0] (D[9:8]/0x483C6). CAW[1:0]: Column Address Width Bits in the SDRAM Option Register (D[9:8]/0x483C6) Table III.3.3.2.3 Column Address Width Settings CAW1 CAW0 Column address width 1 1 0 0 1 0 1 0 11 bits (2K) 10 bits (1K) 9 bits (512) 8 bits (256) When initially reset, the column address width is initialized to 9 bits (512). Figure III.3.3.2.2 shows the different column address output formats due to selected device size and column address width. Device size (DVSIZ) = 16 bits Pin A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CAW = 8 bits AP 0 0 a8 a7 a6 a5 a4 a3 a2 a1 0 CAW = 9 bits AP 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 0 CAW = 10 bits AP a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 0 CAW = 11 bits a11 AP a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 0 Device size (DVSIZ) = 32 bits Pin A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CAW = 8 bits AP 0 0 a9 a8 a7 a6 a5 a4 a3 a2 0 0 CAW = 9 bits AP 0 a10 a9 a8 a7 a6 a5 a4 a3 a2 0 0 CAW = 10 bits AP a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 0 0 CAW = 11 bits a12 AP a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 0 0 The set value of BACTMD (D4/0x483C6) is reflected in AP, with precharge and read/write operation controlled as shown below. <Precharge> AP = 0: Single bank precharge, AP = 1: All bank precharge <Read/write> AP = 0: Read/write without auto-precharge, AP = 1: Read/write with auto-precharge Figure III.3.3.2.2 Column Address Output Formats III-3-4 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Row address width I The row address width is set by RAW[1:0] (D[11:10]/0x483C6). RAW[1:0]: Row Address Width Bits in the SDRAM Option Register (D[11:10]/0x483C6) Table III.3.3.2.4 Row Address Width Settings RAW1 RAW0 Row address width 1 1 0 0 1 0 1 0 14 bits (16K) 13 bits (8K) 12 bits (4K) 11 bits (2K) When initially reset, the row address width is initialized to 12 bits (4K). Figure III.3.3.2.3 shows the different row address output formats due to selected device size, column address width, and row address width. Device size (DVSIZ) = 16 bits Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 CAW = 8 bits CAW = 9 bits RAW = 11 bits | RAW = 14 bits A2 A1 A0 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 0 RAW = 11 bits | RAW = 14 bits CAW = 9 bits CAW = 10 bits CAW = 11 bits RAW = 11 bits | RAW = 14 bits RAW = 11 bits | RAW = 14 bits RAW = 11 bits | RAW = 14 bits A5 A4 A3 a9 0 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 0 | a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 III | RAW = 11 bits | RAW = 14 bits RAW = 11 bits | RAW = 14 bits A6 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 0 | a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 Device size (DVSIZ) = 32 bits Pin A17 A16 A15 A14 A13 A12 A11 A10 A9 CAW = 8 bits A7 | RAW = 11 bits CAW = 10 bits | RAW = 14 bits CAW = 11 bits A8 A8 A7 A6 A5 A4 A3 A2 0 A1 A0 0 0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 0 0 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 0 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 0 0 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 0 0 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 0 0 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 0 0 0 0 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 | | | | a28 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 Figure III.3.3.2.3 Row Address Output Formats Endian mode The half-word and word data in SDRAM are accessed in little endian mode by default. When SDRAM must be accessed in big endian mode, set BIG (D15/0x483C6) to 1. BIG: Endian Mode Select Bit in the SDRAM Option Register (D15/0x483C6) Although the BBCU registers also have control bits CExBIG (D12/0x48388 + 4*(x - 4)) to select endian mode for each area, this control bit for the area for which EBCU type (SDRAM) is selected as the device type is disabled. For bus operations in each data size and endian mode, see Section III.3.3.5, "Bus Operations of SDRAM." S1C33401 TECHNICAL MANUAL EPSON III-3-5 EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.3.3 Configuration of SDRAM Chips Table III.3.3.3.1 shows the configuration of SDRAM chips determined by settings made above. Table III.3.3.3.1 Example Configuration of SDRAM Chips Device size (DVSIZ[1:0] value) Column address width / size (CAW[1:0] value) Row address width / size (RAW[1:0] value) SDRAM configuration Memory size 32 bits (11) 16 bits (01 or 10) 16 bits (01 or 10) 16 bits (01 or 10) 16 bits (01 or 10) 16 bits (01 or 10) 16 bits (01 or 10) 8 bits / 256 (00) 8 bits / 256 (00) 8 bits / 256 (00) 9 bits / 512 (01) 10 bits / 1K (10) 11 bits / 2K (11) 11 bits / 2K (11) 12 bits / 4K (01) 12 bits / 4K (01) 12 bits / 4K (01) 13 bits / 8K (10) 13 bits / 8K (10) 13 bits / 8K (10) 14 bits / 16K (11) 1M x 8 bits x 4 banks x 4 1M x 16 bits x 4 banks x 1 1M x 8 bits x 4 banks x 2 4M x 16 bits x 4 banks x 1 8M x 16 bits x 4 banks x 1 16M x 16 bits x 4 banks x 1 32M x 16 bits x 4 banks x 1 16M bytes 8M bytes 8M bytes 32M bytes 64M bytes 128M bytes 256M bytes III.3.3.4 Example Connection of SDRAMs A few examples of how to connect SDRAMs are shown below. S1C33 SDRAM A[15:14] A[13:1] D[15:0] A[14:13] (BS[1:0]) A[12:0] DQ[15:0] SDCLK SDCKE #SDCS #SDRAS #SDCAS #SDWE DQM1(DQMH) DQM0(DQML) CLK CKE #CS #RAS #CAS #WE DQMU DQML 32M x 16 bits (4 banks) (RAS: 13 bits, CAS: 10 bits) Figure III.3.3.4.1 Example of Connecting 64-MB SDRAM (16-bit Bus Width) S1C33 A[14:13] A[12:1] D[15:0] SDCLK SDCKE #SDCS #SDRAS #SDCAS #SDWE DQM1(DQMH) DQM0(DQML) SDRAM A[13:12] (BS[1:0]) A[11:0] DQ[15:0] CLK CKE #CS #RAS #CAS #WE DQMU DQML SDRAM S1C33 A[13:12] (BS[1:0]) A[11:0] DQ[7:0] A[14:13] A[12:1] D[15:8] D[7:0] SDCLK SDCKE #SDCS #SDRAS #SDCAS #SDWE DQM1(DQMH) DQM0(DQML) CLK CKE #CS #RAS #CAS #WE DQM A[13:12] (BS[1:0]) A[11:0] DQ[7:0] 4M x 16 bits (4 banks) (RAS: 12 bits, CAS: 8 bits) CLK CKE #CS #RAS #CAS #WE DQM 4M x 8 bits (4 banks) x 2 (RAS: 12 bits, CAS: 8 bits) Figure III.3.3.4.2 Example of Connecting 8-MB SDRAM (16-bit Bus Width) III-3-6 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) SDRAM S1C33 A[15:14] A[13:2] D[31:24] D[23:16] D[15:8] D[7:0] A[13:12] (BS[1:0]) A[11:0] DQ[7:0] SDCLK SDCKE #SDCS #SDRAS #SDCAS #SDWE DQM3 DQM2 DQM1 DQM0 CLK CKE #CS #RAS #CAS #WE DQM I A[13:12] (BS[1:0]) A[11:0] DQ[7:0] CLK CKE #CS #RAS #CAS #WE DQM III A[13:12] (BS[1:0]) A[11:0] DQ[7:0] CLK CKE #CS #RAS #CAS #WE DQM EBCU A[13:12] (BS[1:0]) A[11:0] DQ[7:0] CLK CKE #CS #RAS #CAS #WE DQM 1M x 8 bits (4 banks) x 4 (RAS: 12 bits, CAS: 8 bits) Figure III.3.3.4.3 Example of Connecting 16-MB SDRAM (32-bit Bus Width) S1C33401 TECHNICAL MANUAL EPSON III-3-7 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.3.5 Bus Operations of SDRAM The external data bus of the C33 ADV is 32 bits wide. (External pins for some C33 ADV models may be 16 bits, D[15:0].) Depending on the device size and data size of the instruction executed, two or more bus operations may occur. Table III.3.3.5.1 shows bus operations in the SDRAM area. Table III.3.3.5.1 Bus Operations Device size Data size 16 bits (lower) Byte R/W A1 A0 W R Half word Word W R W R 16 bits (higher) Byte W R Half word Word W R W R 32 bits Byte W R Half word W R Word III-3-8 W R 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Little endian Valid D[31:24] D[23:16] D[15:8] D[7:0] pins pins signal pins pins D[7:0] - DQM0 - - - D[7:0] DQM1 - - D[7:0] - Read - - - D[7:0] - - DQM[1:0] - - D[15:0] Read - - D[15:0] DQM[1:0] - - D[15:0] - - D[31:16] Read - - D[15:0] - - D[31:16] - - DQM2 D[7:0] - - - DQM3 - D[7:0] - - Read D[7:0] - - - - D[7:0] - - DQM[3:2] D[15:0] - - Read D[15:0] - - DQM[3:2] D[15:0] - - D[31:16] - - Read D[15:0] - - D[31:16] D[7:0] - DQM0 - - - D[7:0] DQM1 - - - - DQM2 D[7:0] - - - DQM3 - D[7:0] D[7:0] - Read - - - D[7:0] - - - - D[7:0] - - - - D[7:0] D[15:8] D[7:0] DQM[1:0] - - - - DQM[3:2] D[15:8] D[7:0] D[15:8] D[7:0] Read - - - - D[15:8] D[7:0] DQM[3:0] D[31:0] Read D[31:0] EPSON Big endian Valid D[31:24] D[23:16] D[15:8] D[7:0] pins pins pins pins signal D[7:0] - - - DQM0 - - - D[7:0] DQM1 D[7:0] - - - Read - - - D[7:0] - - DQM[1:0] D[15:0] - - Read D[15:0] - - DQM[1:0] D[31:16] - - D[15:0] - - Read D[31:16] - - D[15:0] - - D[7:0] - DQM3 - D[7:0] - - DQM2 - - D[7:0] - Read - D[7:0] - - - - DQM[3:2] D[15:0] - - Read D[15:0] - - DQM[3:2] D[31:16] - - D[15:0] - - Read D[31:16] - - D[15:0] - - D[7:0] - DQM3 - D[7:0] - - DQM2 D[7:0] - - - DQM1 - - - D[7:0] DQM0 - - D[7:0] - Read - D[7:0] - - D[7:0] - - - - - - D[7:0] - - DQM[3:2] D[15:8] D[7:0] D[15:8] D[7:0] - - DQM[1:0] - D[15:8] D[7:0] - Read D[15:8] D[7:0] - - DQM[3:0] D[31:0] Read D[31:0] Access count 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 1st 2nd 1 1 1st 2nd 1st 2nd 1st 2nd 3rd 4th 1st 2nd 3rd 4th 1st 2nd 1st 2nd 1 1 S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.4 EBCU Operating Clock and SDRAM Clock I III.3.4.1 Operating Clock of the EBCU The EBCU is clocked by the core system clock (CCLK) generated by the CMU. For details on how to set CCLK and control the clock, see Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the EBCU operating clock CCLK is supplied to the EBCU with default settings. There are three ways that the CMU supplies CCLK to the EBCU. Turn off any unnecessary means of clock supply by using the respective control bits to reduce the amount of power consumed on the chip. Moreover, automatic control may be applied for clock supplies 2 and 3. 1. BBCU, EBCU NOSTOP clock This clock is used for overall control of the high-speed bus. Turn this clock on when using any of the blocks (e.g., BBCU or EBCU) connected to the high-speed bus. The clock supply can be controlled by BBEBNCLK (D11/0x48370). BBEBNCLK: BBCU, EBCU NOSTOP Control Bit in the CCLK System Peripheral Clock On/Off Register (D11/0x48370) 2. EBCU HB interface clock This clock is used for interfacing SDRAM to the EBCU. Turn this clock on to use the SDRAM interface. The clock supply can be controlled by EBCUHBCLK (D5/0x48370). Use EBCUHBAUTO (D5/0x48372) to enable or disable the automatic control function. EBCUHBCLK: EBCU HB Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D5/0x48370) EBCUHBAUTO: EBCU HB Interface Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D5/0x48372) 3. EBCU SDRAM clock Like clock supply 2 above, this clock is used for interfacing SDRAM to the EBCU. Turn this clock on to use the SDRAM interface. The clock supply can be controlled by EBCUSDCLK (D4/0x48370). Use EBCUSDAUTO (D4/0x48372) to enable or disable the automatic control function. EBCUSDCLK: EBCU SDRAM Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D4/0x48370) EBCUSDAUTO: EBCU SDRAM Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D4/0x48372) Setting any of the clock control bits above (initially 1) to 0 turns off the corresponding clock supply to the EBCU. Setting both the clock control bit and automatic control bit (initially 0) to 1 for any clock supply enables the automatic control function for that clock supply. If the EBCU enters the IDLE state while the automatic control function is enabled, clock-enable signal input to the CMU is negated. As a result, the CMU stops supplying a clock to the EBCU. This state is called powerdown mode of the EBCU. When any block generates an operation request to the EBCU, the EBCU immediately reasserts the clock-enable signal. Clock supply from the CMU is resumed one clock after the clock-enable signal becomes active. Note: The clock supply should be automatically controlled to reduce the amount of power consumed on the chip. However, limitations are imposed on the supported operating clock frequency, etc. For details, see Section II.3, "Clock Management Unit (CMU)." Clock state in standby mode The supply of CCLK stops depending on type of standby mode. HALT mode: CCLK is supplied the same way as in normal mode. HALT2 mode: The supply of CCLK stops. SLEEP mode: The supply of CCLK stops. Therefore, the EBCU also stops operating when in HALT2 and SLEEP modes. Because clock output to SDRAM is turned off, make sure SDRAM is set to self-refresh mode before entering these modes. S1C33401 TECHNICAL MANUAL EPSON III-3-9 III EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.4.2 Generation of SDRAM Clock The EBCU divides CCLK by a specific number to generate the SDRAM clock (SDCLK). This divide-by ratio is set by using SDCLKD[1:0] (D[1:0]/0x483C0). SDCLKD[1:0]: SDCLK Setup Bits in the SDCLK Divide and Refresh Mode Register (D[1:0]/0x483C0) Table III.3.4.2.1 SDCLK (CCLK Divide-by Ratio) Settings SDCLKD1 SDCLKD0 SDCLK frequency 1 1 0 0 1 0 1 0 CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 When initially reset, the SDCLK frequency is set to CCLK*1/8. The SDCLK thus generated is output from the SDCLK pin. Normally, SDCLK output is an extended port function. Therefore, before SDCLK can be output, the pin function must be switched for SDCLK output by using the Function Select Register for the relevant port. For details of which pins are assigned the SDCLK output function and how to switch over the pin functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." SDCLK is always output to SDRAM, not just during SDRAM access. SDCLK output can be turned off when not accessing SDRAM by writing 1 to SDCLKS (D4/0x483C0). SDCLKS: SDCLK Output Control Bit in the SDCLK Divide and Refresh Mode Register (D4/0x483C0) III-3-10 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.5 Setting SDRAM Access Conditions I The SDRAM interface allows the following access conditions to be selected. For details of settings related to SDRAM size and address, see Section III.3.3, "Configuration of SDRAM." Table III.3.5.1 SDRAM Access Conditions Setup item Content Command hold time Bank active mode CAS latency Burst length tRCD (RAS-CAS delay time) tWR (Write recovery time) tRP (Precharge time) tRFC (Auto-refresh cycle time) Control bit settings 3 clocks (CCLK) 2 clocks 1 clock 0 clocks Enable (full bank active) Disable 3 2 1 Fixed at 1 4 clocks (SDCLK) 3 clocks 2 clocks 1 clock 4 clocks (SDCLK) 3 clocks 2 clocks 1 clock 4 clocks (SDCLK) 3 clocks 2 clocks 1 clock 12 clocks (SDCLK) : 8 clocks : 1 clock CMDHLD[1:0] (D[1:0]/0x483C6) = 11 CMDHLD[1:0] (D[1:0]/0x483C6) = 10 CMDHLD[1:0] (D[1:0]/0x483C6) = 01 CMDHLD[1:0] (D[1:0]/0x483C6) = 00 (default) BACTMD (D4/0x483C6) = 1 BACTMD (D4/0x483C6) = 0 (default) CL[2:0] (D[6:4]/0x483CA) = 011 CL[2:0] (D[6:4]/0x483CA) = 010 (default) CL[2:0] (D[6:4]/0x483CA) = 001 - TRCD[1:0] (D[1:0]/0x483C8) = 11 TRCD[1:0] (D[1:0]/0x483C8) = 10 TRCD[1:0] (D[1:0]/0x483C8) = 01 (default) TRCD[1:0] (D[1:0]/0x483C8) = 00 TWR[1:0] (D[5:4]/0x483C8) = 11 TWR[1:0] (D[5:4]/0x483C8) = 10 TWR[1:0] (D[5:4]/0x483C8) = 01 TWR[1:0] (D[5:4]/0x483C8) = 00 (default) TRP[1:0] (D[9:8]/0x483C8) = 11 TRP[1:0] (D[9:8]/0x483C8) = 10 TRP[1:0] (D[9:8]/0x483C8) = 01 (default) TRP[1:0] (D[9:8]/0x483C8) = 00 TRFC[3:0] (D[15:12]/0x483C8) = 1011 : TRFC[3:0] (D[15:12]/0x483C8) = 0111 (default) : TRFC[3:0] (D[15:12]/0x483C8) = 0000 III EBCU Command hold time The command hold time refers to the period from the rise time of SDCLK after command output to when command output is negated. This is specified by a number of CCLK clocks using CMDHLD[1:0] (D[1:0]/ 0x483C6). CMDHLD[1:0]: Command Hold Time Setup Bits in the SDRAM Option Register (D[1:0]/0x483C6) Table III.3.5.2 Command Hold Time CMDHLD1 CMDHLD0 Command hold time (in units of CCLK clocks) 1 1 0 0 1 0 1 0 3 clocks 2 clocks 1 clock 0 clocks CCLK*1/8 (11) SDCLK (SDCLKD[1:0] setting) CCLK*1/4 (10) CCLK*1/2 (01) x x x CCLK*1/1 (00) x x x : Settings accepted; x: Settings prohibited When initially reset, the command hold time is initialized to 0 clock. S1C33401 TECHNICAL MANUAL EPSON III-3-11 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) CCLK SDCLK CMDHLD[1:0] = 00 Command output CMDHLD[1:0] = 01 CMDHLD[1:0] = 10 CMDHLD[1:0] = 11 ACT READA ACT READA ACT ACT Command hold time READA READA (When SDCLK is set as CCLK*1/8) Figure III.3.5.1 Command Hold Time Delaying command outputs in the CCLK clock cycle units using this function helps easy timing adjustment between the SDCLK clock and command output including the printed circuit board conditions. Note that adjustment of the command hold time does not affect the data receive timing in the C33 ADV. The values that can be set for the command hold time are subject to limitations depending on the relationship between CCLK and SDCLK, as shown in Table III.3.5.2. Bank active mode SDRAM in the C33 ADV supports read/write commands with and without auto-precharge. With initial settings, a read/write command (READA/WRITA) with auto-precharge is issued and banks are precharged internally in SDRAM after the read/write cycle. Writing 1 to BACTMD (D4/0x483C6) enables bank active mode, so that a read/write command (READ/WRIT) without auto-precharge can be issued. In this case, banks are not precharged after the read/write cycle and remain active. Therefore, when accessing the same row address in the same bank, a READ/WRIT command is issued directly, without issuing an active (ACTV) command. To access a different row address in the same bank, a precharge (PRE) command is issued, followed by an ACTV command, then a READ/WRIT command. In bank active mode, therefore, banks are only precharged when a different row address is accessed or SDRAM refreshed. BACTMD: SDRAM Bank Active Mode Select Bit in the SDRAM Option Register (D4/0x483C6) III-3-12 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) SDRAM timing parameters that can be set by control bits I Before describing how to set each timing parameter, the following diagram shows the relationship between these parameters and positions in the bus cycle. SDRAM read/write cycle Write cycle Read cycle SDCLK Command ACT 1 READA SDCKE ACT 1 WRITA tRP <4> ACT tRP <4> #SDCS #SDRAS tRCD <2> tRCD <2> #SDCAS #SDWE BS[1:0] BANK0 A10/AP RASa A[:0] RASa DQM[3:0] BANK1 RASa 0xF 0xF 0x0 D[31:0] CAS RASa CAS 0xF 0x0 tWR <3> valid valid CAS latency <1> 1: SDRAM internal precharge III SDRAM burst read/write cycle Read cycle Write cycle SDCLK Command ACT 1 READ READ READ READA SDCKE ACT WRIT WRIT WRIT WRITA EBCU 1 tRP <4> tRP <4> #SDCS #SDRAS tRCD <2> tRCD <2> #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] 0xF D[31:0] BANK# RAS CAS#1 CAS#2 CAS#3 RAS CAS#4 0x0 CAS#1 0x0 0xF valid valid valid valid CAS#2 CAS#3 CAS#4 0xF valid valid valid valid CAS latency <1> tWR <3> 1: SDRAM internal precharge Auto-refresh cycle Refresh cycle SDCLK Command REFA SDCKE ACT tRFC <5> #SDCS #SDRAS #SDCAS #SDWE Figure III.3.5.2 SDRAM Timing Parameters Each timing parameter is detailed below. Be sure to set parameters as suited for specifications of the connected device. S1C33401 TECHNICAL MANUAL EPSON III-3-13 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) CAS latency (Figure III.3.5.2 <1>) CAS latency refers to the number of SDCLK clocks until data is output from SDRAM after issuing a read (READ/READA) command. For the EBCU's SDRAM interface, CAS latency can be set from 1 to 3 by using CL[2:0] (D[6:4]/0x483CA). CL[2:0]: CAS Latency Setting Bits in the SDRAM Mode Register (D[6:4]/0x483CA) Table III.3.5.3 CAS Latency Settings CL2 CL1 CL0 CAS latency 1 0 0 0 0 1 1 0 0 1 0 1 0 Reserved 3 2 1 Reserved When initially reset, CAS latency is initialized to 2. tRCD (RAS-CAS delay time) (Figure III.3.5.2 <2>) tRCD refers to the time (in units of SDCLK clocks) before a read/write command is issued after an active (ACTV) command issuance. tRCD can be set from 1 to 4 clocks by using TRCD[1:0] (D[1:0]/0x483C8). TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8) Table III.3.5.4 tRCD Settings TRCD1 TRCD0 1 1 0 0 1 0 1 0 tRCD 4 clocks 3 clocks 2 clocks 1 clock When initially reset, tRCD is initialized to 2 clocks. tWR (write recovery time) (Figure III.3.5.2 <3>) tWR refers to the time (in units of SDCLK clocks) until banks are precharged after a write cycle. tWR can be set from 1 to 4 clocks by using TWR[1:0] (D[5:4]/0x483C8). TWR[1:0]: tWR Setup Bits in the SDRAM Access Control Register (D[5:4]/0x483C8) Table III.3.5.5 tWR Settings TWR1 TWR0 1 1 0 0 1 0 1 0 tWR 4 clocks 3 clocks 2 clocks 1 clock When initially reset, tWR is initialized to 1 clock. tRP (precharge time) (Figure III.3.5.2 <4>) tRP refers to the time (in units of SDCLK clocks) until an active (ACTV) command is issued after precharge. tRP can be set from 1 to 4 clocks by using TRP[1:0] (D[9:8]/0x483C8). TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8) Table III.3.5.6 tRP Settings TRP1 TRP0 1 1 0 0 1 0 1 0 tRP 4 clocks 3 clocks 2 clocks 1 clock When initially reset, tRP is initialized to 2 clocks. III-3-14 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) tRFC (auto-refresh cycle time) (Figure III.3.5.2 <5>) I tRFC refers to the time (in units of SDCLK clocks) until the next command is issued after issuing an auto-refresh command. tRFC can be set from 1 to 12 clocks by using TRFC[3:0] (D[15:12]/0x483C8). TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8) Table III.3.5.7 tRFC Settings TRFC3 TRFC2 TRFC1 TRFC0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 tRFC Reserved 12 clocks 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock When initially reset, tRFC is initialized to 8 clocks. Note: The refresh period (RFPOD[7:0] (D[7:0]/0x483C4)) should be longer than tRFC + 1. Otherwise the bus will be fully occupied by the auto-refresh cycle, so neither read nor write cycles can be inserted. RFPOD[7:0]: Refresh Period Setup Bits in the Refresh Period Register (D[7:0]/0x483C4) S1C33401 TECHNICAL MANUAL EPSON III EBCU III-3-15 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.6 Control and Operation of SDRAM Interface III.3.6.1 Initializing SDRAM To use SDRAM, it must be initialized by following the procedure below after switching power on. 1. Setting SDRAM interface pins Switch over the pins shared with general-purpose input/output ports or other peripheral functions for SDRAM use by setting the relevant Port Function Select Register. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." 2. Setting up the BBCU (for selection of device type) Select EBCU type (SDRAM) as the device type of the CEx area (x = 4 to 11) to which SDRAM is connected by writing 1 to CExEBCU (D10/0x48388 + 4*(x - 4)). CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4*(x - 4)) 3. Initializing the EBCU registers Set up the EBCU registers in the following order: (1) Refresh Period Register (0x483C4) Set the auto-refresh cycle. (2) Refresh Counter Register (0x483C2) Set the initial value of the auto-refresh counter. (3) SDRAM Option Register (0x483C6) Set SDRAM size/address-related parameters. (4) SDRAM Access Control Register (0x483C8) Set SDRAM access timing parameters. (5) SDCLK Divide and Refresh Mode Register (0x483C0) Set SDCLK. 4. Wait after SDRAM power-on After the power to SDRAM is turned on, the NOP state (#SDCS = 1) must be maintained for a certain time (e.g., 100 s) or more. Because this time varies with each SDRAM, refer to the specifications of SDRAM being used. 5. Executing an SDRAM initial sequence Execute an initial sequence for SDRAM by writing to INISQC (D15) while setting a CAS latency value in CL[2:0] (D[6:4]) in the SDRAM Mode Register (0x483CA). For other bits in the SDRAM Mode Register (0x483CA), be sure to set the values specified in the I/O map. INISQC: Initial Sequence Control Bit in the SDRAM Mode Register (D15/0x483CA) CL[2:0]: CAS Latency Setting Bits in the SDRAM Mode Register (D[6:4]/0x483CA) Normally, write 1 to INISQC (D15/0x483CA). In this case, the following commands are sent to SDRAM to execute the initial sequence: (1) PALL: All bank precharge command (2) REFA: Refresh command (8 times) (3) MRS: Mode register set command III-3-16 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Initial sequence I SDCLK Command REFA PALL REFA MRS SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] valid A10/AP valid A[:0] valid DQM[3:0] 0xF 0xF D[31:0] III 8 refresh commands are executed Figure III.3.6.1.1 SDRAM Initial Sequence Writing 0 to INISQC (D15/0x483CA) has a different effect whereby only the MRS command is sent to SDRAM. Executing the MRS command completes SDRAM initialization so that SDRAM is ready for read/write operations. Note: Do not read data from the SDRAM immediately after the MRS command is executed as it may cause a malfunction. S1C33401 TECHNICAL MANUAL EPSON III-3-17 EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.6.2 Read/Write Operations Read cycle The SDRAM interface of the EBCU supports burst read and single read operations. However, since the burst length is fixed to 1, 4-word transfer instructions or data bus widths smaller than the access size (e.g., cache refill or IDMA load instructions) are accommodated by outputting the #SDCAS and address signals successively. Read commands with and without auto-precharge are both supported. For read operation with auto-precharge (when BACTMD (D4/0x483C6) = 0), a READA command is issued and banks are automatically precharged internally in SDRAM after the read cycle. BACTMD: SDRAM Bank Active Mode Select Bit in the SDRAM Option Register (D4/0x483C6) For read operation without auto-precharge (when BACTMD (D4/0x483C6) = 1), a READ command is issued, but banks are not precharged after the read cycle. Consequently, the banks remain active, and to access the same row address in the same bank, a READ command is issued directly, without issuing the ACTV (active) command. To access a different row address in the same bank, a PRE (single bank precharge) command is issued, followed by the ACTV command, then a READ command. For read operation without precharge, banks are precharged only when a different row address in the same bank is accessed or SDRAM refreshed. The following symbols represent the cycles used in SDRAM read timing charts: Tr: ACTV command cycle Tcw: ACTV-READ/READA commands interval wait cycle 1 Tc: READ/READA command cycle Tlat: CAS latency cycle Tp(c): Precharge (SDRAM internal precharge)-ACTV commands interval cycle 2 Tidle: Idle cycle *1: Set by TRCD[1:0] (D[1:0]/0x483C8). A Tcw cycle is inserted when TRCD[1:0] is set to 2 or more clocks. TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8) *2: Set by TRP[1:0] (D[9:8]/0x483C8). No commands can be issued to the same SDRAM during this period. TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8) The following shows the timings of read cycles. III-3-18 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single read cycle with auto-precharge (32-bit data read through 32-bit bus) I Example of single read cycle 1 Auto-precharge: Included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tcw Tr Tc Tlat Tpc Tidle Tlat SDCLK Command 1 READA ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] CAS 0xF III 0xF 0x0 D[31:0] valid EBCU 1: SDRAM internal precharge Figure III.3.6.2.1 Single Read Cycle (1) Example of single read cycle 2 Auto-precharge: Included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tpc Tidle SDCLK Command ACT 1 READA SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] 0xF CAS 0xF 0x0 D[31:0] valid 1: SDRAM internal precharge Figure III.3.6.2.2 Single Read Cycle (2) S1C33401 TECHNICAL MANUAL EPSON III-3-19 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single read cycle with auto-precharge (32-bit data read through 16-bit bus) Example of single read cycle 3 Auto-precharge: Included CAS latency: 2 Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Tlat Tlat Tpc Tidle SDCLK Command 1 READ READA ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] CAS#2 CAS#1 11 11 00 D[15:0] valid valid 1: SDRAM internal precharge Figure III.3.6.2.3 Single Read Cycle (3) Example of single read cycle 4 Auto-precharge: Included CAS latency: 1 Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc2 Tc1 Tlat Tpc Tidle SDCLK Command ACT READ READA 1 SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] 11 CAS#2 CAS#1 11 00 D[15:0] valid valid 1: SDRAM internal precharge Figure III.3.6.2.4 Single Read Cycle (4) III-3-20 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single read cycle without auto-precharge (32-bit data read through 32-bit bus) I Example of single read cycle 5 Auto-precharge: Not included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tlat Tidle SDCLK Command ACT READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] III CAS 0xF 0xF 0x0 D[31:0] valid EBCU Figure III.3.6.2.5 Single Read Cycle (5) Example of single read cycle 6 Auto-precharge: Not included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tidle SDCLK Command READ ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] 0xF CAS 0xF 0x0 D[31:0] valid Figure III.3.6.2.6 Single Read Cycle (6) S1C33401 TECHNICAL MANUAL EPSON III-3-21 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single read cycle without auto-precharge (32-bit data read through 16-bit bus) Example of single read cycle 7 Auto-precharge: Not included CAS latency: 2 Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Tlat Tlat Tidle SDCLK Command ACT READ READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] CAS#2 CAS#1 11 00 11 D[15:0] valid valid Figure III.3.6.2.7 Single Read Cycle (7) Example of single read cycle 8 Auto-precharge: Not included CAS latency: 1 Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Tlat Tidle SDCLK Command ACT READ READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] CAS#2 CAS#1 11 00 D[15:0] 11 valid valid Figure III.3.6.2.8 Single Read Cycle (8) III-3-22 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Successive single read from different banks I Example of single read cycle 9 Auto-precharge: Included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tcw Tr Tc Tlat Tpc Tidle Tlat Tr Tcw Tlat Tc Tpc Tidle Tlat SDCLK Command 1 READA ACT ACT 1 READA SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] A10/AP RAS A[:0] RAS DQM[3:0] BANK# BANK# RAS RAS CAS 0xF 0xF 0x0 D[31:0] III CAS 0x0 0xF valid valid EBCU 1: SDRAM internal precharge Figure III.3.6.2.9 Single Read Cycle (9) Example of single read cycle 10 Auto-precharge: Included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tpc Tidle Tlat Tr Tcw Tc Tlat Tpc Tidle SDCLK Command ACT 1 READA ACT 1 READA SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] A10/AP RAS A[:0] RAS DQM[3:0] D[31:0] BANK# BANK# 0xF RAS RAS CAS 0xF 0x0 CAS 0x0 valid 0xF valid 1: SDRAM internal precharge Figure III.3.6.2.10 Single Read Cycle (10) S1C33401 TECHNICAL MANUAL EPSON III-3-23 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Successive single read from same row address in same bank Example of single read cycle 11 Auto-precharge: Not included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tlat Tidle Tidle Tc Tlat Tlat Tidle SDCLK Command ACT READ READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#1 A10/AP RAS A[:0] RAS DQM[3:0] BANK#1 CASa 0xF CASb 0x0 0xF D[31:0] 0xF 0x0 valid valid Figure III.3.6.2.11 Single Read Cycle (11) Example of single read cycle 12 Auto-precharge: Not included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tidle Tidle Tc Tlat Tidle SDCLK Command ACT READ READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#1 A10/AP RAS A[:0] RAS DQM[3:0] D[31:0] 0xF BANK#1 CASa CASb 0x0 0xF 0x0 valid 0xF valid Figure III.3.6.2.12 Single Read Cycle (12) III-3-24 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Successive single read from different row addresses in same bank I Example of single read cycle 13 Auto-precharge: Not included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tlat Tidle Tp Tpc Tr Tcw Tc Tlat Tlat Tidle SDCLK Command ACT READ ACT PRE READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#1 A10/AP RASa A[:0] RASa DQM[3:0] BANK#1 RASb CAS 0xF 0x0 0x0 0xF D[31:0] III CAS RASb 0xF valid valid EBCU Figure III.3.6.2.13 Single Read Cycle (13) Example of single read cycle 14 Auto-precharge: Not included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Tlat Tidle Tp Tpc Tr Tcw Tc Tlat Tidle SDCLK Command ACT READ ACT PRE READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#1 A10/AP RASa A[:0] RASa DQM[3:0] D[31:0] 0xF BANK#1 RASb CAS RASb 0x0 0xF valid CAS 0x0 0xF valid Figure III.3.6.2.14 Single Read Cycle (14) S1C33401 TECHNICAL MANUAL EPSON III-3-25 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Burst read cycle with auto-precharge Example of burst read cycle 1 (For cache refill and loading from IDMA instruction) Auto-precharge: Included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tcw Tr Tc2 Tc1 Tc3 Tc4 Tlat Tpc Tidle Tlat SDCLK Command 1 READ READ READ READA ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] CAS#1 CAS#2 CAS#3 0xF CAS#4 0xF 0x0 D[31:0] valid valid valid valid 1: SDRAM internal precharge Figure III.3.6.2.15 Burst Read Cycle (1) Example of burst read cycle 2 (For cache refill and loading from IDMA instruction) Auto-precharge: Included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc1 Tc3 Tc2 Tc4 Tlat Tpc Tidle SDCLK Command ACT READ READ READ READA 1 SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] D[31:0] 0xF CAS#1 CAS#2 CAS#3 CAS#4 0x0 0xF valid valid valid valid 1: SDRAM internal precharge Figure III.3.6.2.16 Burst Read Cycle (2) III-3-26 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Burst read cycle without auto-precharge I Example of burst read cycle 3 (For cache refill and loading from IDMA instruction) Auto-precharge: Not included CAS latency: 2 Data bus width: 32 bits Access: 32-bit data Tcw Tr Tc1 Tc3 Tc2 Tc4 Tlat Tlat Tidle SDCLK Command READ READ READ READ ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] CAS#1 CAS#2 CAS#3 0xF III CAS#4 0xF 0x0 D[31:0] valid valid valid valid EBCU 1: SDRAM internal precharge Figure III.3.6.2.17 Burst Read Cycle (3) Example of burst read cycle 4 (For cache refill and loading from IDMA instruction) Auto-precharge: Not included CAS latency: 1 Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc1 Tc3 Tc2 Tc4 Tlat Tidle SDCLK Command ACT READ READ READ READ SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] D[31:0] CAS#1 CAS#2 CAS#3 0xF CAS#4 0x0 0xF valid valid valid valid 1: SDRAM internal precharge Figure III.3.6.2.18 Burst Read Cycle (4) S1C33401 TECHNICAL MANUAL EPSON III-3-27 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Write cycle The SDRAM interface of the EBCU supports burst write and single write operations. However, since the burst length is fixed to 1, 4-word transfer instructions or data bus widths smaller than the access size (e.g., cache write-back or IDMA store instructions) are accommodated by outputting the #SDCAS and address signals successively. Write commands with and without auto-precharge are both supported. For write operation with auto-precharge (when BACTMD (D4/0x483C6) = 0), a WRITA command is issued and banks are automatically precharged internally in SDRAM after the write cycle. For write operation without auto-precharge (when BACTMD (D4/0x483C6) = 1), a WRIT command is issued, but banks are not precharged after the write cycle. Consequently, the banks remain active, and to access the same row address in the same bank, a WRIT command is issued directly, without issuing the ACTV (active) command. To access a different row address in the same bank, a PRE (single bank precharge) command is issued, followed by the ACTV command, then a WRIT command. For write operation without precharge, banks are precharged only when a different row address in the same bank is accessed or SDRAM refreshed. The following symbols represent the cycles used in SDRAM write timing charts: Tr: ACTV command cycle Tcw: ACTV-WRIT/WRITA commands interval wait cycle 1 Tc: WRIT/WRITA command cycle Twrc: Write recovery cycle 2 Tp(c): Precharge (SDRAM internal precharge)-ACTV commands interval cycle 3 Tidle: Idle cycle 1: Set by TRCD[1:0] (D[1:0]/0x483C8). A Tcw cycle is inserted when TRCD[1:0] is set to 2 or more clocks. TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8) 2: Set by TWR[1:0] (D[5:4]/0x483C8). No commands can be issued to the same bank during this period. TWR[1:0]: tWR Setup Bits in the SDRAM Access Control Register (D[5:4]/0x483C8) 3: Set by TRP[1:0] (D[9:8]/0x483C8). No commands can be issued to the same SDRAM during this period. TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8) The following shows the timings of write cycles. III-3-28 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single write cycle with auto-precharge (32-bit data write through 32-bit bus) I Example of single write cycle 1 Auto-precharge: Included Data bus width: 32 bits Access: 32-bit data Tcw Tr Tc Twrc Tpc Tidle SDCLK Command 1 WRITA ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] CAS 0xF D[31:0] III 0xF 0x0 valid 1: SDRAM internal precharge EBCU Figure III.3.6.2.19 Single Write Cycle (1) Single write cycle with auto-precharge (32-bit data write through 16-bit bus) Example of single write cycle 2 Auto-precharge: Included Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Twrc Tpc Tidle SDCLK Command ACT WRIT WRITA 1 SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] D[15:0] 11 CAS#1 CAS#2 00 11 valid valid 1: SDRAM internal precharge Figure III.3.6.2.20 Single Write Cycle (2) S1C33401 TECHNICAL MANUAL EPSON III-3-29 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Single write cycle without auto-precharge (32-bit data write through 32-bit bus) Example of single write cycle 3 Auto-precharge: Not included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Twrc Tidle SDCLK Command ACT WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] CAS 0xF 0xF 0x0 D[31:0] valid Figure III.3.6.2.21 Single Write Cycle (3) Single write cycle without auto-precharge (32-bit data write through 16-bit bus) Example of single write cycle 4 Auto-precharge: Not included Data bus width: 16 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Twrc Tidle SDCLK Command ACT WRIT WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[1:0] D[15:0] 11 CAS#1 CAS#2 00 11 valid valid Figure III.3.6.2.22 Single Write Cycle (4) III-3-30 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Successive single write to different banks I Example of single write cycle 5 (For successive single write operations) Auto-precharge: Included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Twrc Tpc Tidle Tc Tcw Tr Twrc Tpc Tidle SDCLK Command 1 WRITA ACT ACT WRITA 1 SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS DQM[3:0] BANK# RAS CAS 0xF RAS 0x0 D[31:0] 0xF III CAS 0xF 0x0 valid valid EBCU 1: SDRAM internal precharge Figure III.3.6.2.23 Single Write Cycle (5) Successive single write to same row address in same bank Example of single write cycle 6 Auto-precharge: Not included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Twrc Tc Twrc Tidle SDCLK Command ACT WRIT WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#0 A10/AP RAS A[:0] RAS DQM[3:0] D[31:0] 0xF BANK#0 CASa 0x0 valid CASb 0xF 0x0 0xF valid Figure III.3.6.2.24 Single Write Cycle (6) S1C33401 TECHNICAL MANUAL EPSON III-3-31 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Successive single write to different row addresses in same bank Example of single write cycle 7 Auto-precharge: Not included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc Twrc Tp Tpc Tr Tcw Tc Twrc Tidle SDCLK Command ACT WRIT PRE ACT WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK#1 A10/AP RASa A[:0] RASa DQM[3:0] BANK#1 RASb CAS 0xF RASb 0x0 D[31:0] CAS 0xF 0x0 valid 0xF valid Figure III.3.6.2.25 Single Write Cycle (7) Burst write cycle with auto-precharge Example of burst write cycle 1 (For cache write-back and store from IDMA instruction) Auto-precharge: Included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Tc3 Tc4 Twrc Tpc Tidle SDCLK Command ACT WRIT WRIT WRIT WRITA 1 SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS CAS#1 CAS#2 CAS#3 CAS#4 DQM0 D[7:0] valid valid valid valid 1: SDRAM internal precharge Figure III.3.6.2.26 Burst Write Cycle (1) III-3-32 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Burst write cycle without auto-precharge I Example of burst write cycle 2 (For cache write-back and store from IDMA instruction) Auto-precharge: Not included Data bus width: 32 bits Access: 32-bit data Tr Tcw Tc1 Tc2 Tc3 Tc4 Twrc Tidle SDCLK Command ACT WRIT WRIT WRIT WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] BANK# A10/AP RAS A[:0] RAS CAS#1 III CAS#2 CAS#3 CAS#4 DQM0 D[7:0] valid valid valid valid EBCU Figure III.3.6.2.27 Burst Write Cycle (2) S1C33401 TECHNICAL MANUAL EPSON III-3-33 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Combination cycle The following shows the timing of a read/write combination cycle. Example of read/write cycle with precharge Bank 0 read cycle Tcw Tr Tlat Tc Bank 0 read cycle Bank 1 write cycle Tlat Tpc Tidle Tr Tcw Tc Twrc Tpc Tidle Tr Tcw Tlat Tlat Tc Tpc Tidle SDCLK Command 1 READA ACT 1 WRITA ACT 1 READA ACT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] A10/AP RAS A[:0] RAS DQM[3:0] BANK#0 BANK#1 BANK#0 RAS RAS 0xF 0xF 0x0 D[31:0] RAS CAS RAS CAS CAS 0xF 0x0 0xF 0x0 valid valid valid 1: SDRAM internal precharge Figure III.3.6.2.28 Read/Write Cycle with Precharge Example of read/write cycle without precharge Tcw Tlat Tc Bank 1 read cycle Bank 1 write cycle Bank 0 read cycle Tr Tr Tlat Tidle Tc Tcw Twrc Tc Tlat Tlat Tidle Bank 0 write cycle Tp Tpc Tr Tcw Tc Twrc Tidle SDCLK Command ACT ACT READ WRIT ACT PRE READ WRIT SDCKE #SDCS #SDRAS #SDCAS #SDWE BS[1:0] A10/AP RASa A[:0] RASa DQM[3:0] D[31:0] BANK#1 BANK#0 0xF BANK#0 BANK#1 RASc RASb RASb CAS 0xF 0x0 valid CAS RASc CAS 0x0 0xF 0xF 0x0 valid Same row address in bank 1 CAS 0x0 0xF valid valid Another row address in bank 0 Figure III.3.6.2.29 Read/Write Cycle without Precharge III-3-34 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.6.3 SDRAM Refresh I The EBCU contains an SDRAM refresh controller that supports auto-refresh and self-refresh operations. Setting RFSH (D8/0x483C0) to 1 enables the SDRAM refresh function. Moreover, RFSHMD (D9/0x483C0) selects whether to perform auto-refresh (RFSHMD = 0) or self-refresh (RFSHMD = 1). RFSH: Refresh Enable Bit in the SDCLK Divide and Refresh Mode Register (D8/0x483C0) RFSHMD: Refresh Mode Select Bit in the SDCLK Divide and Refresh Mode Register (D9/0x483C0) Auto-refresh Auto-refresh is the function used to refresh SDRAM by periodically issuing PALL (all bank precharge) and REFA (auto refresh) commands. The refresh controller incorporates an 8-bit refresh counter and a register to set a refresh period, thus enabling programmable refresh period settings. Setting up auto-refresh To perform auto-refresh, the following settings are required: 1. Setting the refresh counter Set RCKS (D10/0x483C0) to select the clock with which to run the refresh counter. RCKS = 1: SDCLK*1/16 RCKS = 0: SDCLK*1/1 (default) RCKS: Refresh Counter Clock Select Bit in the SDCLK Divide and Refresh Mode Register (D10/0x483C0) As an approximate guide for clock selection, select SDCLK*1/1 when SDCLK is 10 MHz or less; select SDCLK*1/16 when SDCLK exceeds 10 MHz. 2. Setting a refresh period Set a refresh period (value to compare with the refresh counter) in RFPOD[7:0] (D[7:0]/0x483C4). EBCU RFPOD[7:0]: Refresh Period Setup Bits in the Refresh Period Register (D[7:0]/0x483C4) The set value of RFPOD[7:0] (D[7:0]/0x483C4) is calculated as follows: RFPOD[7:0] = refresh period (s) / refresh counter clock cycle (s) For example, when the maximum refresh period of SDRAM used is 64 ms and the number of refresh cycles (row address size) is 4,096, then one cycle (64 ms/4,096) equals 15.625 s. When the refresh counter clock frequency is 10 MHz, the clock period is 0.1 s. RFPOD[7:0] = 15.625 (s) / 0.1 (s) = 156.25 Therefore, the value to be set in RFPOD[7:0] (D[7:0]/0x483C4) is 156 or less. To ensure that the refresh requirements of SDRAM are always met, subtract a margin from the calculated value when setting a refresh period in the register. 3. Starting an auto-refresh cycle Set RFSHMD (D9/0x483C0) to 0 and RFSH (D8/0x483C0) to 1. Auto-refresh operation The following describes the operation of the SDRAM refresh controller. 1. When values 0 and 1 are written to RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0), respectively, the controller starts an auto-refresh cycle. 2. The 8-bit refresh counter starts counting synchronously with the refresh counter clock set by RCKS (D10/ 0x483C0). Because the content of the refresh counter is not cleared at this time, the counter starts counting from the current value (initially set to 0). 3. The refresh counter value is compared with the value of RFPOD[7:0] (D[7:0]/0x483C4) and when both match, the controller issues PALL and REFA commands to refresh SDRAM. The refresh counter is cleared at this time, and restarts counting from 0. S1C33401 TECHNICAL MANUAL EPSON III III-3-35 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 4. If the refresh counter overflows before its value matches that of RFPOD[7:0] (D[7:0]/0x483C4) as when it starts counting from a value larger than that of RFPOD[7:0] (D[7:0]/0x483C4), the counter is simply reset to 0 and starts counting all over again. In this case, SDRAM is not refreshed. 5. When value 0 is written to RFSH (D8/0x483C0) or value 1 is written to RFSHMD (D9/0x483C0), the refresh counter stops and the auto-refresh cycle is aborted. Reading and initializing the refresh counter The value of the refresh counter can be read out from RFCTR[7:0] (D[7:0]/0x483C2). Moreover, the refresh counter can be set to any desired value by writing to RFCTR[7:0] (D[7:0]/0x483C2). In this way, the first period after starting an auto-refresh cycle can be reduced to any desired length. When refresh commands must be sent to SDRAM immediately, set the smallest value approximating that of RFPOD[7:0] (D[7:0]/0x483C4) in RFCTR[7:0] (D[7:0]/0x483C2) before starting auto-refresh. RFCTR[7:0]: Refresh Counter Bits in the Refresh Counter Register (D[7:0]/0x483C2) Note: Before writing the initial value to RFCTR[7:0] (D[7:0]/0x483C2), be sure to stop the counter by writing 0 to RFSH (D8/0x483C0). Otherwise, values may not be correctly written to the count register while the counter is operating. Timing chart Figure III.3.6.3.1 shows the timing of an auto-refresh cycle. The following symbols represent the cycles used in timing charts: Tp(c): Precharge-ACTV/REFA commands interval cycle 1 Trfa: REFA command cycle Taw: REFA-ACTV/REFA commands interval cycle 2 1: Set by TRP[1:0] (D[9:8]/0x483C8). TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8) 2: Set by TRFC[3:0] (D[15:12]/0x483C8). TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8) Tp Tpc Trfa Taw Taw Taw SDCLK Command PAL/PRE REFA SDCKE #SDCS #SDRAS #SDCAS #SDWE Figure III.3.6.3.1 Auto-Refresh Cycle Self-refresh Self-refresh is a kind of standby mode where the refresh timing and refresh address are generated internally in SDRAM. When self-refresh mode is entered, SDCLK output to SDRAM can be turned off, helping to reduce the amount of current consumed on the chip. Select this mode when SDRAM is to be placed in a standby state. When the chip is to be set in HALT2 or SLEEP mode with the clock turned off, always be sure to select selfrefresh mode for SDRAM. III-3-36 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) Starting self-refresh operation To perform self-refresh, the following settings are required: I 1. Enabling self-refresh Set RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0) both to 1. 2. Issuing a self-refresh command Write 1 to SELF (D0/0x483CC). SELF: Self-refresh Entry/Exit Control Bit in the Self-refresh Control Register (D0/0x483CC) As a result, the SDCKE signal goes low (= 0) and SDRAM enters self-refresh mode. SDRAM cannot be accessed while in self-refresh mode. Stopping self-refresh Follow the procedure below to disable self-refresh. This control must be executed in other than SDRAM. 1. Turning SDCLK output on If SDCLK output to SDRAM was turned off during self-refresh, turn it back on again. 2. Stopping self-refresh Write 0 to SELF (D0/0x483CC). 3. Starting auto-refresh Start auto-refresh by following the procedure above. For the initial auto-refresh to be performed after stopping self-refresh, set the smallest value approximating that of RFPOD[7:0] (D[7:0]/0x483C4) in RFCTR[7:0] (D[7:0]/0x483C2) to ensure that SDRAM will be refreshed immediately. Note that command issuance to SDRAM is disabled, however, for the interval time set by TRFC[3:0] (D[15:12]/0x483C8) after self-refresh has stopped. Note: Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF (D0/0x483CC) to 1 when already 1 or setting 0 when already 0 is prohibited because such bit manipulation may cause the SDRAM controller to operate erratically. Timing chart Figure III.3.6.3.2 shows the timing of a self-refresh cycle. The following symbols represent the cycles used in timing charts: Tp(c): Precharge-ACTV/REFA commands interval cycle 1 Tref: REFS command cycle Taw: REFA-ACTV/REFA commands interval cycle 2 1: Set by TRP[1:0] (D[9:8]/0x483C8). TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8) 2: Set by TRFC[3:0] (D[15:12]/0x483C8). TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8) Tp Tpc Tref Idle Texit Taw Idle SDCLK Command SDCKE #SDCS #SDRAS #SDCAS #SDWE Figure III.3.6.3.2 Self-Refresh Cycle S1C33401 TECHNICAL MANUAL EPSON III-3-37 III EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.6.4 SDRAM Refresh Request when External Bus is Released Although the BBCU and EBCU (SDRAMC) normally manage external buses in the C33 ADV, the C33 ADV allows bus control to be released to external bus masters. For details, see Section III.2.10, "External Bus Requests and Release of Bus Control." The following describes how SDRAM refresh requests are processed when bus control is released to external bus masters. Refresh requests from the SDRAM refresh controller have higher priority than requests from external bus masters for bus control. For this reason, if a refresh request is made while an external bus master has bus control, the external bus master must release bus control. The following shows the bus control release sequence followed at such time. 1. A refresh request is made. 2. The EBCU drives the #BUSGET pin low one clock after a refresh request is generated by the SDRAM refresh controller. 3. The external bus master with bus control always monitors the #BUSGET pin status, so that when #BUSGET is detected low, the bus master terminates the bus cycle in progress and drives the #BUSREQ pin back high. 4. The EBCU returns the #BUSGET pin high two cycles after detecting that the #BUSREQ pin is high. 5. For the external bus master to request bus control again, it must confirm that the #BUSGET pin is high before sending a request to the BBCU/EBCU. CCLK SDRAM refresh request #BUSGET SDRAM refresh request generated 1 cycle Bus release request to external bus master #BUSREQ 2 cycles 1 cycle Sync #BUSACK The external bus master controls bus cycles. The external bus master terminates the bus cycle being executed. Bus control being released SDRAM refresh Figure III.3.6.4.1 External Bus Release Timing III-3-38 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.7 SDRAM Commands I The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals. Table III.3.7.1 lists the commands output by the SDRAM controller. Table III.3.7.1 List of the Supported SDRAM Commands Command Function Deselect No Operation Bank Active Read without Auto-Precharge Read with Auto-Precharge Write without Auto-Precharge Write with Auto-Precharge Single Bank Precharge Precharge All Auto Refresh Self Refresh Mode Register Set Pins Symbol SDCKE #SDCS DESL NOP ACTV READ READA WRIT WRITA PRE PALL REFA REFS MRS H H H H H H H H H H L H H L L L L L L L L L L L #SDRAS #SDCAS #SDWE BA[1:0] A10 Axx X X X X X X X X H X H H V V L Row H H V L H Column L H V H H Column L H V L H Column L L V H H Column L L V L L X H L X H L X H L X X L X L H X X L X L H V V L V L L V = valid, X = don't care, L = low level, H = high level III EBCU S1C33401 TECHNICAL MANUAL EPSON III-3-39 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.8 Control Register Details Table III.3.8.1 EBCU Register List Address 0x000483C0 0x000483C2 0x000483C4 0x000483C6 0x000483C8 0x000483CA 0x000483CC Register name SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF) Refresh Counter Register (pEBCU_RFTIM) Refresh Period Register (pEBCU_RFPOD) SDRAM Option Register (pEBCU_SDOPT) SDRAM Access Control Register (pEBCU_SDACR) SDRAM Mode Register (pEBCU_SDMOD) Self-refresh Control Register (pEBCU_SLFEX) Size 16 16 16 16 16 16 16 Function Sets SDCLK and refresh mode. Refresh counter Sets refresh period. Sets SDRAM. Sets SDRAM access timing parameters. Sets SDRAM operation mode. Controls self-refresh. The following describes each EBCU control register. The EBCU control registers are mapped to the 16-bit device area at addresses 0x483C0 to 0x483CC, and can be accessed in units of half-words or bytes. III-3-40 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483C0: SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF) Register name Address SDCLK divide and refresh mode register (pEBCU_DIVRF) Name Bit 00483C0 D15-11 - D10 RCKS (HW) D9 RFSHMD D8 RFSH D7-5 - D4 SDCLKS D3-2 - D1 SDCLKD1 D0 SDCLKD0 Function reserved Refresh counter clock select Refresh mode select Refresh enable reserved SDCLK output during idle reserved SDCLK setup (CCLK division ratio) Setting - 1 SDCLK*1/16 0 SDCLK*1/1 1 Self-refresh 0 Auto-refresh 1 Enabled 0 Disabled - 1 Stopped 0 Output - SDCLKD[1:0] SDCLK 11 CCLK*1/8 10 CCLK*1/4 01 CCLK*1/2 00 CCLK*1/1 Init. R/W - 0 0 0 - 0 - 1 1 I Remarks - 0 when being read. R/W R/W R/W - 0 when being read. R/W - 0 when being read. R/W D[15:11] Reserved D10 RCKS: Refresh Counter Clock Select Bit This bit sets the count clock for the refresh counter (0x483C2). 1 (R/W): SDCLK*1/16 0 (R/W): SDCLK*1/1 (default) As an approximate guide for clock selection, select SDCLK*1/1 when SDCLK is 10 MHz or less; select SDCLK*1/16 when SDCLK exceeds 10 MHz. D9 RFSHMD: Refresh Mode Select Bit This bit selects refresh mode. 1 (R/W): Self-refresh 0 (R/W): Auto-refresh (default) III Select auto-refresh while using SDRAM. To execute auto-refresh, set a refresh period in the Refresh Period Register (0x483C4) and set this bit to 0 and RFSH (D8) to 1, respectively. Before the chip can be set to HALT2 or SLEEP mode (where SDCLK output is turned off), SDRAM must be set to self-refresh mode. To select self-refresh mode for SDRAM, set this bit and RFSH (D8) both to 1 and write 1 to SELF (D0/0x483CC). D8 RFSH: Refresh Enable Bit This bit enables the refresh function. 1 (R/W): Enable 0 (R/W): Disable (default) Setting this bit to 1 enables the SDRAM refresh controller, so that the refresh operation set by RFSHMD (D9) can be controlled. D[7:5] Reserved D4 SDCLKS: SDCLK Output Control Bit This bit selects whether to output SDCLK to SDRAM when it is not being accessed. 1 (R/W): Do not output 0 (R/W): Output (default) D[3:2] Reserved D[1:0] SDCLKD[1:0]: SDCLK Setup Bits SDCLK is the clock for SDRAM, and is generated from the core system clock (CCLK) by dividing it by a given number. Use SDCLKD[1:0] to select this divide-by ratio. Table III.3.8.2 Selection of SDCLK SDCLKD1 SDCLKD0 1 1 0 0 1 0 1 0 S1C33401 TECHNICAL MANUAL SDCLK frequency CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 (Default: 0b11 = CCLK*1/8) EPSON III-3-41 EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483C2: Refresh Counter Register (pEBCU_RFTIM) Register name Address Refresh counter register (pEBCU_RFTIM) Bit Name 00483C2 D15-8 - D7 RFCTR7 (HW) D6 RFCTR6 D5 RFCTR5 D4 RFCTR4 D3 RFCTR3 D2 RFCTR2 D1 RFCTR1 D0 RFCTR0 Function Setting - 0 to 0xFF reserved Refresh counter Init. R/W - 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W D[15:8] Reserved D[7:0] RFCTR[7:0]: Refresh Counter Bits These bits allow the refresh counter value to be read and its initial value set. (Default: 0x00) When an auto-refresh cycle is started by writing 0 to RFSHMD (D9/0x483C0) and 1 to RFSH (D8/ 0x483C0), the refresh counter starts counting synchronously with the refresh counter clock set by RCKS (D10/0x483C0). When the refresh counter value matches the value of RFPOD[7:0] (D[7:0]/0x483C4), the SDRAM controller issues PALL and REFA commands to refresh SDRAM. The refresh counter is cleared at this time, and restarts counting from 0. If the refresh counter overflows before its value matches that of RFPOD[7:0] (D[7:0]/0x483C4) as when counting is started from a value greater than that of RFPOD[7:0] (D[7:0]/0x483C4), the counter is simply reset to 0 and starts counting all over again. In this case, SDRAM is not refreshed. When value 0 is written to RFSH (D8/0x483C0) or value 1 is written to RFSHMD (D9/0x483C0), the refresh counter stops and the auto-refresh cycle is aborted. If the first refresh period must be reduced, set the smallest value approximating that of RFPOD[7:0] (D[7:0]/0x483C4) in this register before starting auto-refresh. Note: Before writing the initial value to RFCTR[7:0] (D[7:0]/0x483C2), be sure to stop the counter by writing 0 to RFSH (D8/0x483C0). Values may not be correctly written to the count register while the counter is operating. III-3-42 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483C4: Refresh Period Register (pEBCU_RFPOD) Name Function Refresh period 00483C4 D15-8 - D7 RFPOD7 (HW) register D6 RFPOD6 (pEBCU_RFPOD) D5 RFPOD5 D4 RFPOD4 D3 RFPOD3 D2 RFPOD2 D1 RFPOD1 D0 RFPOD0 reserved Refresh period setup (number of cycles) Register name Address Bit Setting - 0 to 0xFF I Init. R/W - 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W D[15:8] Reserved D[7:0] RFPOD[7:0]: Refresh Period Setup Bits These bits set a refresh period. (Default: 0x00) The value set in these bits is compared with the refresh counter and when both values match, refresh commands are sent to SDRAM. The refresh counter is cleared at this time, and restarts counting from 0. See the description of the Refresh Counter Register (0x483C2) for details. Calculate the set value (maximum value) from the equation below and subtract a margin from the calculated value before writing a refresh period to this register. RFPOD[7:0] = refresh period (s) / refresh counter clock cycle (s) III EBCU S1C33401 TECHNICAL MANUAL EPSON III-3-43 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483C6: SDRAM Option Register (pEBCU_SDOPT) Name Register name Address Bit SDRAM option 00483C6 (HW) register (pEBCU_SDOPT) D15 D14 D13 D12 BIG - DVSIZ1 DVSIZ0 Endian mode select reserved SDRAM device size select D11 D10 RAW1 RAW0 Row address width D9 D8 CAW1 CAW0 Column address width - BACTMD - CMDHLD1 CMDHLD0 reserved - SDRAM bank active mode select 1 Full bank 0 No bank reserved - Command hold time setup # of clocks CMDHLD[1:0] (number of CCLK clocks) 3 clocks 11 2 clocks 10 1 clock 01 0 clocks 00 D7-5 D4 D3-2 D1 D0 D15 Function Setting 1 Big endian Init. R/W 0 Little endian - DVSIZ[1:0] 11 10 01 00 RAW[1:0] 11 10 01 00 CAW[1:0] 11 10 01 00 Size 32 bits 16 bits (upper) 16 bits (lower) reserved Size 14 bits (16K) 13 bits (8K) 12 bits (4K) 11 bits (2K) Size 11 bits (2K) 10 bits (1K) 9 bits (512) 8 bits (256) Remarks 0 - 0 1 R/W - 0 when being read. R/W 0 1 R/W 0 1 R/W - 0 - 0 0 - 0 when being read. R/W - 0 when being read. R/W BIG: Endian Mode Select Bit This bit selects endian mode in which to access SDRAM. 1 (R/W): Big endian 0 (R/W): Little endian (default) Note that endian mode selected for the same area by the BBCU register is not effective. D14 Reserved D[13:12] DVSIZ[1:0]: SDRAM Device Size Select Bits These bits select the device size (data bus width) of SDRAM. Table III.3.8.3 Selection of SDRAM Device Size DVSIZ1 DVSIZ0 1 1 0 0 1 0 1 0 Device size Connected data bus D[31:0] (Note) 32 bits D[31:16] (Note) 16 bits (16 high-order data bus bits) D[15:0] 16 bits (16 low-order data bus bits) - Settings prohibited (Default: 0b01 = 16 bits (16 low-order data bus bits)) Note: For C33 ADV models with 16 external data bus pins, D[15:0], neither "32 bits" nor "16 bits (16 high-order data bus bits)" can be selected as the device size of external SDRAM. D[11:10] RAW[1:0]: Row Address Width Bits These bits set the row address width. Table III.3.8.4 Row Address Width Settings III-3-44 RAW1 RAW0 1 1 0 0 1 0 1 0 Row address width 14 bits (16K) 13 bits (8K) 12 bits (4K) 11 bits (2K) (Default: 0b01 = 12 bits) EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) D[9:8] CAW[1:0]: Column Address Width Bits These bits set the column address width. I Table III.3.8.5 Column Address Width Settings CAW1 CAW0 1 1 0 0 1 0 1 0 Column address width 11 bits (2K) 10 bits (1K) 9 bits (512) 8 bits (256) (Default: 0b01 = 9 bits) D[7:5] Reserved D4 BACTMD: SDRAM Bank Active Mode Select Bit This bit selects bank active mode (whether to perform auto-precharge). 1 (R/W): Without auto-precharge 0 (R/W): With auto-precharge (default) Setting this bit to 0 issues a read/write command with auto-precharge (READA/WRITA), so that banks are precharged internally in SDRAM after the read/write cycle. Setting this bit to 1 issues a read/write command without auto-precharge (READ/WRIT). In this case, banks are not precharged after the read/write cycle and remain active. Therefore, when accessing the same row address in the same bank, a READ/WRIT command is issued directly, without issuing an active (ACTV) command. When accessing a different row address in the same bank, a precharge (PRE) command is issued, followed by an ACTV command, then a READ/WRIT command. D[3:2] Reserved D[1:0] CMDHLD[1:0]: Command Hold Time Setup Bits These bits set the command hold time in units of CCLK clocks. The command hold time refers to the time from the rise of SDCLK after command output to when command output is negated. The selection of values here is subject to limitations imposed by the settings of SDCLKD[1:0] (D[1:0]/0x483C0). Table III.3.8.6 Command Hold Time CMDHLD1 CMDHLD0 Command hold time (in units of CCLK clocks) 1 1 0 0 1 0 1 0 3 clocks 2 clocks 1 clock 0 clocks CCLK*1/8 (11) SDCLK (SDCLKD[1:0] setting) CCLK*1/4 (10) CCLK*1/2 (01) x x x CCLK*1/1 (00) x x x : Settings accepted; x: Settings prohibited (Default: 0b00 = 0 clocks) S1C33401 TECHNICAL MANUAL EPSON III-3-45 III EBCU III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483C8: SDRAM Access Control Register (pEBCU_SDACR) Register name Address Bit SDRAM access 00483C8 control register (HW) (pEBCU_SDACR) D15 D14 D13 D12 Name TRFC3 TRFC2 TRFC1 TRFC0 D11-10 - D9 TRP1 D8 TRP0 Function Setting tRFC (auto-refresh cycle time) setup (number of SDCLK clocks) TRFC[3:0] 11 1011 : 0111 : 0000 reserved tRP (precharge time) setup (number of SDCLK clocks) Init. R/W # of clocks reserved 12 clocks : 8 clocks : 1 clock - TRP[1:0] 11 10 01 00 D7-6 - D5 TWR1 D4 TWR0 reserved tWR (write-recovery time) setup (number of SDCLK clocks) D3-2 - D1 TRCD1 D0 TRCD0 reserved tRCD (RAS-CAS delay time) setup (number of SDCLK clocks) # of clocks 4 clocks 3 clocks 2 clocks 1 clock - TWR[1:0] 11 10 01 00 # of clocks 4 clocks 3 clocks 2 clocks 1 clock - TRCD[1:0] 11 10 01 00 # of clocks 4 clocks 3 clocks 2 clocks 1 clock Remarks 0 1 1 1 R/W - 0 1 - 0 when being read. R/W - 0 0 - 0 when being read. R/W - 0 1 - 0 when being read. R/W D[15:12] TRFC[3:0]: tRFC Setup Bits These bits set tRFC (auto-refresh cycle time). tRFC refers to the time (in units of SDCLK clocks) until the next command is issued after issuing an auto-refresh command. Table III.3.8.7 tRFC Settings TRFC3 TRFC2 TRFC1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 tRFC Reserved 12 clocks 1 11 clocks 0 10 clocks 1 9 clocks 0 8 clocks 1 7 clocks 0 6 clocks 1 5 clocks 0 4 clocks 1 3 clocks 0 2 clocks 1 1 clock 0 (Default: 0b0111 = 8 clocks) TRFC0 D[11:10] Reserved D[9:8] TRP[1:0]: tRP Setup Bits These bits set tRP (precharge time). tRP refers to the time (in units of SDCLK clocks) until the active command is issued after precharge. Table III.3.8.8 tRP Settings D[7:6] III-3-46 TRP1 TRP0 1 1 0 0 1 0 1 0 tRP 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b01 = 2 clocks) Reserved EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) D[5:4] TWR[1:0]: tWR Setup Bits These bits set tWR (write recovery time). tWR refers to the time (in units of SDCLK clocks) until banks are precharged after a write cycle. I Table III.3.8.9 tWR Settings TWR1 TWR0 1 1 0 0 1 0 1 0 tWR 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b00 = 1 clock) D[3:2] Reserved D[1:0] TRCD[1:0]: tRCD Setup Bits These bits set tRCD (RAS-CAS delay time). tRCD refers to the time (in units of SDCLK clocks) before a read/write command is issued after issuing the active command. Table III.3.8.10 tRCD Settings TRCD1 TRCD0 1 1 0 0 1 0 1 0 tRCD 4 clocks 3 clocks 2 clocks 1 clock (Default: 0b01 = 2 clocks) III EBCU S1C33401 TECHNICAL MANUAL EPSON III-3-47 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483CA: SDRAM Mode Register (pEBCU_SDMOD) Register name Address Bit Name SDRAM mode 00483CA D15 INISQC (HW) D14-10 - register D9 WMODE (pEBCU_SDMOD) D8-7 - D6 CL2 D5 CL1 D4 CL0 D3 D2 D1 D0 D15 BT BL2 BL1 BL0 Function Initial sequence control reserved reserved reserved CAS latency reserved reserved Setting Init. R/W 1 Init. sequence 0 MRS only - Fixed at 1 - CL[2:0] CAS latency 1 reserved 011 3 010 2 001 1 000 reserved Fixed at 0 Fixed at 000 0 - - - 0 1 0 - - - - Remarks R/W - 0 when being read. R - 0 when being read. R/W R R INISQC: Initial Sequence Control Bit This bit executes the initial sequence after SDRAM power is turned on. 1 (R/W): Execute initial sequence 0 (R/W): Only execute MRS command (default) After turning SDRAM power on, normally maintain the NOP state (#SDCS = 1) for a certain time (e.g., 100 s) or more before writing 1 to this bit to execute the initial sequence. When this bit is set to 1, the following commands are sent to SDRAM: (1) PALL: All bank precharge command (2) REFA: Refresh command (8 times) (3) MRS: Mode register set command When the MRS command is executed, SDRAM initialization is completed to ready SDRAM for read/ write operations. Writing 0 to this bit has a different effect, whereby only the MRS command is sent to SDRAM. D[14:10] Reserved D9 WMODE: Reserved Do not set this bit to other than 1. D[8:7] Reserved D[6:4] CL[2:0]: CAS Latency Setting Bits These bits set CAS latency. CAS latency refers to the number of SDCLK clocks until data is output from SDRAM after issuing a read (READ/READA) command. Table III.3.8.11 CAS Latency Settings CL2 CL1 CL0 1 0 0 0 0 1 1 0 0 1 0 1 0 D3 BT: Reserved Do not set this bit to other than 0. D[2:0] BL[2:0]: Reserved Do not set these bits to other than 0b000. III-3-48 CAS latency Reserved 3 2 1 Reserved (Default: 0b010 = 2 clocks) EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) 0x483CC: Self-refresh Control Register (pEBCU_SLFEX) Register name Address Bit Name 00483CC D15-1 - Self-refresh D0 SELF control register (HW) (pEBCU_SLFEX) Function reserved Self-refresh entry/exit control Setting - 1 Entry D[15:1] Reserved D0 SELF: Self-refresh Entry/Exit Control Bit This bit controls the entry into and exit from self-refresh mode. 1 (R/W): Start self-refresh 0 (R/W): Stop self-refresh (default) 0 Exit I Init. R/W - 0 Remarks - 0 when being read. R/W Do not set 1 to 1 or 0 to 0. To place SDRAM in self-refresh mode, set RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0) both to 1 to enable refresh command issuance, then write 1 to this bit. As a result, the SDCKE signal goes low (= 0) and SDRAM enters self-refresh mode. SDRAM cannot be accessed while in self-refresh mode. To stop self-refresh, write 0 to this bit. Start auto-refresh after stopping self-refresh. Note that command issuance to SDRAM is disabled, however, for the interval time set by TRFC[3:0] (D[15:12]/0x483C8) after self-refresh stops. Note: Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF (D0/0x483CC) to 1 when already 1 or setting 0 when already 0 is prohibited because such bit manipulation may cause the SDRAM controller to operate erratically. III EBCU S1C33401 TECHNICAL MANUAL EPSON III-3-49 III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU) III.3.9 Precautions * Clock output to SDRAM is turned off in HALT2 or SLEEP mode. Therefore, before entering these modes, be sure to set SDRAM to self-refresh mode. * Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF (D0/0x483CC) to 1 when already 1 or setting 0 when already 0 is prohibited because such bit manipulation may cause the SDRAM controller to operate erratically. III-3-50 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4 High-Speed DMA (HSDMA) I III.4.1 Functional Outline of HSDMA The C33 ADV Bus Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address transfer and single-address transfer methods. Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer can be responded to instantaneously. Note: Channels 0 to 3 are configured in the same way and have the same functionality. Signal and control bit names are assigned channel numbers 0 to 3 to distinguish them from other channels. In this manual, however, channel numbers 0 to 3 are designated with an `x' except where they must be distinguished, as the explanation is the same for all channels. Dual-address transfer In this method, a source address and a destination address for DMA transfer can be specified and a DMA transfer is performed in two phases. The first phase reads data at the source address into the on-chip temporary register. The second phase writes the temporary register data to the destination address. Unlike IDMA (Intelligent DMA), which has transfer information in memory, this DMA method does not support a DMA link function but allows high-speed data transfers because it is not necessary to read transfer information from a memory. HSDMA Ch.0 Ch.1 Ch.2 Ch.3 DMA address bus BBCU/ EBCU Data bus DMA data transfer request signal Data transfer (1) (2) DMA data transfer acknowledge signal Transfer count end signal #DMAENDx Hardware/software trigger HSDMA Memory, I/O Memory, I/O Destination Source End of DMA ITC #DMAREQx DMA request (1) Transfer data is read from the source memory or I/O device. (2) Transfer data is written to the destination memory or I/O device. Figure III.4.1.1 Dual-Address Transfer Method The features of dual-address transfer are outlined below. * * * * Source Destination Transfer data size Trigger * Transfer mode * Transfer address control * #DMAEND output External memory and internal memory except Area 0 (including peripheral area) External memory and internal memory except Area 0 (including peripheral area) 8, 16, or 32 bits 1. Software trigger (register control) 2. Hardware trigger (external trigger input, causes of interrupts) 1. Single transfer (one unit of data is transferred by one trigger) 2. Successive transfer (specified number of data are transferred by one trigger) 3. Block transfer (data block of the specified size is transferred by one trigger) The source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. In successive or block transfers, the address can be reset to the initial value upon completion of transfer. Goes low at the last access of data transfer by each trigger. Note: A0RAM (no-wait RAM built into area 0) cannot be specified as the source or destination for DMA transfer. A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) can be used for dual-address transfer. S1C33401 TECHNICAL MANUAL III Address bus EPSON III-4-1 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Timing chart of dual-address mode (1) SRAM Address Read cycle Write cycle Source address Destination address #CE(src) #CE(dst) #RD #WR #DMAEND Figure III.4.1.2 #DMAEND Signal Output Timing (SRAM, standard settings) (2) SDRAM Read cycle Write cycle SDCLK Address RAS CAS RAS CAS #SDCS(src) #SDCS(dst) #SDRAS #SDCAS #SDWE #DMAEND ACT ACT READ WRIT Figure III.4.1.3 #DMAEND Signal Output Timing (SDRAM, standard settings) Notes: * Two or more access cycles are generated when the device size of the external memory is smaller than the transfer data size. In this case, the #DMAEND signal is asserted over these cycles. * The #DMAEND signal is not asserted when a peripheral I/O register located in area 1 is specified as the destination of transfer. III-4-2 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Single-address transfer I In this method, data transfers that are normally accomplished by executing data read and write operations backto-back are executed on the external bus collectively at one time, thus further speeding up the transfer operation. The #DMAACKx and #DMAENDx signals are used to control data transfer. Unlike dual-address transfer, this method does not allow memory to memory data transfer but data transfers can be performed in minimum cycles. Bus control signals BBCU HSDMA Ch.0 Ch.1 Ch.2 Ch.3 DMA address bus Address bus Data bus DMA data transfer request signal Data transfer DMA data transfer acknowledge signal External I/O #RD/#WR Transfer count end signal #DMAENDx #DMAACKx Hardware/software trigger External memory, external or internal I/O ITC #DMAREQx End of DMA DMA reception DMA request Figure III.4.1.4 Single-Address Transfer Method III The features of single-address transfer are outlined below. * Source/destination * Transfer data size * Trigger * Transfer mode * Transfer address control * #DMAEND output * #DMAACK output 1. Between an external I/O and an external memory (except SDRAM) 2. Between an external I/O and another external I/O 3. Between an external I/O and an internal I/O (except peripheral block in area 1) 8, 16, or 32 bits 1. Software trigger (register control) 2. Hardware trigger (external trigger input, causes of interrupts) 1. Single transfer (one unit of data is transferred by one trigger) 2. Successive transfer (specified number of data are transferred by one trigger) 3. Block transfer (data block of the specified size is transferred by one trigger) The source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. In successive or block transfers, the address can be reset to the initial value upon completion of transfer. Goes low at the last access of data transfer by each trigger. Output for accessing the external I/O in every cycle during transfer. Notes: * A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) cannot be used for single-address transfer. * Single-address mode does not allow data transfer between memory devices. An external logic circuit is required to perform single-address transfer between memory devices. * Single-address mode does not support the external memory area that is configured for SDRAM. S1C33401 TECHNICAL MANUAL EPSON III-4-3 HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Timing chart of single-address mode (1) SRAM Read/write cycle Address Memory address #CE #RD #WR #DMAACK #DMAEND Figure III.4.1.5 #DMAACK/#DMAEND Signal Output Timing (SRAM, standard settings) (2) SDRAM The single-address mode does not support SDRAM. III-4-4 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.2 I/O Pins of HSDMA I Table III.4.2.1 lists the I/O pins used for HSDMA. Table III.4.2.1 I/O Pins of HSDMA Pin name #DMAREQ0 #DMAREQ1 #DMAREQ2 #DMAREQ3 #DMAACK0 #DMAACK1 #DMAACK2 #DMAACK3 #DMAEND0 #DMAEND1 #DMAEND2 #DMAEND3 I/O I I I I O O O O O O O O Function DMA transfer request input pin for HSDMA Ch.0 DMA transfer request input pin for HSDMA Ch.1 DMA transfer request input pin for HSDMA Ch.2 DMA transfer request input pin for HSDMA Ch.3 DMA acknowledge signal output pin for HSDMA Ch.0 DMA acknowledge signal output pin for HSDMA Ch.1 DMA acknowledge signal output pin for HSDMA Ch.2 DMA acknowledge signal output pin for HSDMA Ch.3 End-of-transfer signal output pin for HSDMA Ch.0 End-of-transfer signal output pin for HSDMA Ch.1 End-of-transfer signal output pin for HSDMA Ch.2 End-of-transfer signal output pin for HSDMA Ch.3 #DMAREQx (DMA request input pin) This pin is used to input a DMA request signal from an external peripheral circuit. One data transfer operation is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). The #DMAREQ0 to #DMAREQ3 pins correspond to channel 0 to channel 3, respectively. In addition to this external input, software trigger or a cause of interrupt can be selected for the HSDMA trigger source using the register in the interrupt controller. III #DMAACKx (DMA acknowledge signal output pin for single-address mode) This signal is output to indicate that a DMA request has been acknowledged by the DMA controller. In single-address mode, the I/O device that is the source or destination of transfer outputs data to the external bus or takes in data from the external data synchronously with this signal. The #DMAACK0 to #DMAACK3 pins correspond to channel 0 to channel 3, respectively. This signal is not output in dual-address mode. See Figure III.4.1.5 for the waveform of the #DMAACKx signal. #DMAENDx (End-of-transfer signal output pin) This signal is output to indicate that the number of data transfer operations that is set in the control register have been completed. The #DMAEND0 to #DMAEND3 pins correspond to channel 0 to channel 3, respectively. The waveform of the #DMAENDx signal is the same as the #CEx signal. Notes: * The list above indicates the input/output pins that the HSDMA can accommodate. All control signal pins may not be available for some C33 ADV models. For details of the pin configuration of each C33 ADV model, see Section I.3, "Pin Description." * The control pins above are shared with general-purpose input/output ports or other peripheral circuit input/output pins, so that functionality in the initial state may be set to other than the HSDMA. Before the HSDMA signals assigned to these pins can be used, the functions of these pins must be switched for the HSDMA by setting each corresponding Port Function Select Register. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." S1C33401 TECHNICAL MANUAL EPSON III-4-5 HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.3 Programming Control Information The HSDMA operates according to the control information set in the registers. Note that some control bits change their functions according to the address mode. The following explains how to set the contents of control information. Before using HSDMA, make each the settings described below. III.4.3.1 Standard Mode and Advanced Mode The HSDMA in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV HSDMA has two operating modes, the standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table III.4.3.1.1 shows differences between standard mode and advanced mode. Table III.4.3.1.1 Differences between Standard Mode and Advanced Mode Function Source/destination address bit width Word (32-bit) data transfer Address decrement function with initialization Standard mode Advanced mode 28 bits Unavailable Unavailable 32 bits Available Available To configure the HSDMA in advanced mode, set HSDMAADV (D0/0x4829C) to 1. The control registers (0x48262 -0x4829A) for the extended functions are enabled to write after this setting. At initial reset, HSDMAADV (D0/ 0x4829C) is set to 0 and the HSDMA enters standard mode. HSDMAADV: Standard/Advanced Mode Select Bit in the HSDMA STD/ADV Mode Select Register (D0/0x4829C) The following descriptions unless otherwise specified are common contents for both modes. The extended functions in advanced mode are explained assuming that HSDMAADV (D0/0x4829C) has been set to 1. Notes: * Be sure to use the control registers for advanced mode when the HSDMA is set to advanced mode. * The standard or advanced mode currently set is applied to all the HSDMA channels. It cannot be selected for each channel individually. III.4.3.2 Setting the Registers in Dual-Address Mode Make sure that the HSDMA channel is disabled (HSx_EN (D0/0x4822C + 0x10*x) = 0) before setting the control information. HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) Address mode The address mode select bit DUALMx (D15/0x48222 + 0x10*x) should be set to 1 (dual-address mode). This bit is set to 0 (single-address mode) at initial reset. DUALMx: Ch.x Address Mode Select Bit in the HSDMA Ch.x Control Register (D15/0x48222 + 0x10*x) Transfer mode A transfer mode should be set using DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x). DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup Register (D[15:14]/0x4822A + 0x10*x) The following three transfer modes are available: Single transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) = 00, default) In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the specified size. If data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. III-4-6 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Successive transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) = 01) In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 each time data is transferred. I Block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) = 10) In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). If a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. Transfer data size Standard mode (HSDMAADV (D0/0x4829C) = 0, default) DATSIZEx (D14/0x48226 + 0x10*x) is used to set the unit size of data to be transferred. A half-word size (16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup Register (D14/0x48226 + 0x10*x) Advanced mode (HSDMAADV (D0/0x4829C) = 1) In advanced mode, WORDSIZEx (D0/0x48262 + 0x10*x) is provided to select word size (32 bits) in addition to half-word size and byte size that can be selected using DATSIZEx (D14/0x48226 + 0x10*x). WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode (D0/0x48262 + 0x10*x) III Table III.4.3.2.1 Transfer Data Size Selectable in Advanced Mode WORDSIZEx DATSIZEx Transfer data size 1 0 0 X 1 0 Word (32 bits) Half-word (16 bits) Byte (8 bits) HSDMA Block length When using block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) = 10), the data block length (in units of the selected transfer data size) should be set using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register (D[7:0]/0x48220 + 0x10*x) Note: When performing data transfer in block transfer mode, the block size must not be set to 0. In single transfer and successive transfer modes, BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) is used as bits 7-0 of the transfer counter. Transfer counter Block transfer mode In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] (D[15:8]/0x48220 + 0x10*x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10*x). TCx_L[7:0]: Ch.x Transfer Counter [7:0] Bits in the HSDMA Ch.x Transfer Counter Register (D[15:8]/0x48220 + 0x10*x) TCx_H[7:0]: Ch.x Transfer Counter [15:8] Bits in the HSDMA Ch.x Control Register (D[7:0]/0x48222 + 0x10*x) Single transfer and successive transfer modes In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10 * x), TCx_L[7:0] (D[15:8]/0x48220 + 0x10 * x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10*x). Note: The transfer count thus set is decremented according to the transfers performed. If the transfer count is set to 0, it is decremented to all Fs by the first transfer performed. This means that you have set the maximum value that is determined by the number of bits available. S1C33401 TECHNICAL MANUAL EPSON III-4-7 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Source and destination addresses Standard mode (HSDMAADV (D0/0x4829C) = 0, default) In standard mode, a 28-bit source address and a 28-bit destination address for DMA transfer can be specified using SxADRL[15:0] (D[15:0]/0x48224 + 0x10*x), SxADRH[11:0] (D[11:0]/0x48226 + 0x10*x), DxADRL[15:0] (D[15:0]/0x48228 + 0x10*x) and DxADRH[11:0] (D[11:0]/0x4822A + 0x10*x). SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register (D[15:0]/0x48224 + 0x10*x) SxADRH[11:0]: Ch.x Source Address[27:16] in the HSDMA Ch.x High-Order Source Address Setup Register (D[11:0]/0x48226 + 0x10*x) DxADRL[15:0]: Ch.x Destination Address[15:0] in the HSDMA Ch.x Low-Order Destination Address Setup Register (D[15:0]/0x48228 + 0x10*x) DxADRH[11:0]: Ch.x Destination Address[27:16] in the HSDMA Ch.x High-Order Destination Address Setup Register (D[11:0]/0x4822A + 0x10*x) Advanced mode (HSDMAADV (D0/0x4829C) = 1) In advanced mode, a 32-bit source address and a 32-bit destination address for DMA transfer can be specified using SxADRL[15:0] (D[15:0]/0x48264 + 0x10*x), SxADRH[15:0] (D[15:0]/0x48266 + 0x10*x), DxADRL[15:0] (D[15:0]/0x48268 + 0x10*x) and DxADRH[15:0] (D[15:0]/0x4826A + 0x10*x). SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register for ADV mode (D[15:0]/0x48264 + 0x10*x) SxADRH[15:0]: Ch.x Source Address[31:16] in the HSDMA Ch.x High-Order Source Address Setup Register for ADV mode (D[15:0]/0x48266 + 0x10*x) DxADRL[15:0]: Ch.x Destination Address[15:0] in the HSDMA Ch.x Low-Order Destination Address Setup Register for ADV mode (D[15:0]/0x48268 + 0x10*x) DxADRH[15:0]: Ch.x Destination Address[31:16] in the HSDMA Ch.x High-Order Destination Address Setup Register for ADV mode (D[15:0]/0x4826A + 0x10*x) Note: In advanced mode, be sure to use the control registers for advanced mode to set source/ destination addresses. Address increment/decrement control Standard mode (HSDMAADV (D0/0x4829C) = 0, default) The source and/or destination addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) (for source address) and DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) (for destination address) are used to set this function. SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x48226 + 0x10*x) DxIN[1:0]: Ch.x Destination Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x4822A + 0x10*x) SxIN[1:0]/DxIN[1:0] = 00: address fixed (default) The address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read/write from/to the same address. SxIN[1:0]/DxIN[1:0] = 01: address decremented without initialization The address is decremented by an amount equal to the specified data size when one data transfer is completed. The address that has been decremented during transfer does not return to the initial value. SxIN[1:0]/DxIN[1:0] = 10: address incremented with initialization The address is incremented by an amount equal to the specified data size when one data transfer is completed. In single transfer mode, the address that has been incremented during transfer does not return to the initial value. In successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the incremented address returns to the initial value when the block transfer is completed. SxIN[1:0]/DxIN[1:0] = 11: address incremented without initialization The address is incremented by an amount equal to the specified data size when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. III-4-8 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Advanced mode (HSDMAADV (D0/0x4829C) = 1) The address control conditions set using SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) and DxIN[1:0] (D[13:12]/ 0x4822A + 0x10*x) are effective in advanced mode. Furthermore, advanced mode allows selection of "Address decremented with initialization." This condition can be selected using the SxID (D4/0x48262 + 0x10*x) and DxID (D5/0x48262 + 0x10*x). I SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D4/0x48262 + 0x10*x) DxID: Ch.x Destination Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D5/0x48262 + 0x10*x) When SxID (D4/0x48262 + 0x10*x) and/or DxID (D5/0x48262 + 0x10*x) are set to 0 (default), the conditions selected using SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) and/or DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) are effective. When SxID (D4/0x48262 + 0x10*x) and/or DxID (D5/0x48262 + 0x10*x) are set to 1, "Address decremented with initialization" is selected. SxID/DxID = 1: address decremented with initialization The address is decremented by an amount equal to the specified data size when one data transfer is completed. In single transfer mode, the address that has been decremented during transfer does not return to the initial value. In successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the decremented address returns to the initial value when the block transfer is completed. III.4.3.3 Setting the Registers in Single-Address Mode III Make sure that the HSDMA channel is disabled (HSx_EN (D0/0x4822C + 0x10*x) = 0) before setting the control information. HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) HSDMA Address mode The address mode select bit DUALMx (D15/0x48222 + 0x10*x) should be set to 0 (single-address mode). This bit is set to 0 at initial reset. DUALMx: Ch.x Address Mode Select Bit in the HSDMA Ch.x Control Register (D15/0x48222 + 0x10*x) Transfer mode A transfer mode should be set using DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x). DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup Register (D[15:14]/0x4822A + 0x10*x) Table III.4.3.3.1 Transfer Mode DxMOD1 DxMOD0 1 1 0 0 1 0 1 0 Mode Invalid Block transfer mode Successive transfer mode Single transfer mode Refer to the explanation in Section III.4.3.2, "Setting the Registers in Dual-Address Mode." Direction of transfer The direction of data transfer should be set using DxDIR (D14/0x48222 + 0x10*x). DxDIR: Ch.x Transfer Direction Control Bit in the HSDMA Ch.x Control Register (D14/0x48222 + 0x10*x) Memory write operations (data transfer from I/O device to memory) are specified by writing 1 and memory read operations (data transfer from memory to I/O device) are specified by writing 0. S1C33401 TECHNICAL MANUAL EPSON III-4-9 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Transfer data size Standard mode (HSDMAADV (D0/0x4829C) = 0, default) DATSIZEx (D14/0x48226 + 0x10*x) is used to set the unit size of data to be transferred. A half-word size (16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default). DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup Register (D14/0x48226 + 0x10*x) Advanced mode (HSDMAADV (D0/0x4829C) = 1) In advanced mode, WORDSIZEx (D0/0x48262 + 0x10*x) is provided to select a word size (32 bits) in addition to a half-word size and byte size that can be selected using DATSIZEx (D14/0x48226 + 0x10*x). WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode (D0/0x48262 + 0x10*x) Table III.4.3.3.2 Transfer Data Size Selectable in Advanced Mode WORDSIZEx DATSIZEx Transfer data size 1 0 0 X 1 0 Word (32 bits) Half-word (16 bits) Byte (8 bits) DATSIZEx (D14/0x48226 + 0x10*x) and WORDSIZEx (D0/0x48262 + 0x10*x) are used to set the unit size of data to be transferred. Block length When using block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) = 10), the data block length (in units of the selected transfer data size) should be set using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register (D[7:0]/0x48220 + 0x10*x) In single transfer and successive transfer modes, BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) are used as bits 7- 0 of the transfer counter. Note: When performing data transfer in block transfer mode, the block size must not be set to 0. Transfer counter Block transfer mode In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] (D[15:8]/0x48220 + 0x10*x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10*x). TCx_L[7:0]: Ch.x Transfer Counter [7:0] Bits in the HSDMA Ch.x Transfer Counter Register (D[15:8]/0x48220 + 0x10*x) TCx_H[7:0]: Ch.x Transfer Counter [15:8] Bits in the HSDMA Ch.x Control Register (D[7:0]/0x48222 + 0x10*x) Single transfer and successive transfer modes In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10 * x), TCx_L[7:0] (D[15:8]/0x48220 + 0x10 * x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10*x). Memory address Standard mode (HSDMAADV (D0/0x4829C) = 0, default) In standard mode, SxADRL[15:0] (D[15:0]/0x48224 + 0x10*x) and SxADRH[11:0] (D[11:0]/0x48226 + 0x10*x) are used to specify a 28-bit memory address. SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register (D[15:0]/0x48224 + 0x10*x) SxADRH[11:0]: Ch.x Source Address[27:16] in the HSDMA Ch.x High-Order Source Address Setup Register (D[11:0]/0x48226 + 0x10*x) III-4-10 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Advanced mode (HSDMAADV (D0/0x4829C) = 1) In advanced mode, SxADRL[15:0] (D[15:0]/0x48264 + 0x10*x) and SxADRH[15:0] (D[15:0]/0x48266 + 0x10 *x) are used to specify a 32-bit memory address. I SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register for ADV mode (D[15:0]/0x48264 + 0x10*x) SxADRH[15:0]: Ch.x Source Address[31:16] in the HSDMA Ch.x High-Order Source Address Setup Register for ADV mode (D[15:0]/0x48266 + 0x10*x) Note: In advanced mode, be sure to use the control registers for advanced mode to set a memory address. In single-address mode, data transfer is performed between the memory connected to the system interface and an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to specify an address. DxADRL[15:0] (D[15:0]/0x48268 + 0x10*x) and DxADRH[15:0] (D[11:0]/0x4826A + 0x10*x) are not used in single-address mode. Address increment/decrement control Standard mode (HSDMAADV (D0/0x4829C) = 0, default) The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) is used to set this function. SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x48226 + 0x10*x) III Table III.4.3.3.3 Address Control SxIN1 SxIN0 1 1 0 0 1 0 1 0 Address control Increment without initialization Increment with initialization Decrement without initialization Fixed HSDMA Advanced mode (HSDMAADV (D0/0x4829C) = 1) The address control condition set using SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) is effective in advanced mode. Furthermore, advanced mode allows selection of "Address decremented with initialization." This condition can be selected using the SxID (D4/0x48262 + 0x10*x). SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D4/0x48262 + 0x10*x) When SxID (D4/0x48262 + 0x10*x) is set to 0 (default), the condition selected using SxIN[1:0] (D[13:12]/ 0x48226 + 0x10*x) is effective. When SxID (D4/0x48262 + 0x10*x) is set to 1, "Address decremented with initialization" is selected. Refer to the explanation in Section III.4.3.2, "Setting the Registers in Dual-Address Mode." DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) and DxID (D5/0x48262 + 0x10*x) are not used in single-address mode. S1C33401 TECHNICAL MANUAL EPSON III-4-11 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.4 Enabling/Disabling DMA Transfer The HSDMA transfer is enabled by writing 1 to HSx_EN (D0/0x4822C + 0x10*x). HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) However, the control information must always be set correctly before enabling a DMA transfer. Note that the control information cannot be set when HSx_EN (D0/0x4822C + 0x10*x) = 1. When HSx_EN (D0/0x4822C + 0x10*x) is set to 0, HSDMA requests are no longer accepted. When a DMA transfer is completed (transfer counter = 0), HSx_EN (D0/0x4822C + 0x10*x) is reset to 0 to disable the following trigger inputs. III-4-12 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.5 Trigger Source I A HSDMA trigger source for each channel can be selected from among 15 types using HSDxS[3:0] (D[7:0]/0x40298, D[7:0]/0x40299). This function is supported by the interrupt controller. HSD0S[3:0]: Ch.0 Trigger Set-Up Bits in the HSDMA Ch.0-1 Trigger Set-Up Register (D[3:0]/0x40298) HSD1S[3:0]: Ch.1 Trigger Set-Up Bits in the HSDMA Ch.0-1 Trigger Set-Up Register (D[7:4]/0x40298) HSD2S[3:0]: Ch.2 Trigger Set-Up Bits in the HSDMA Ch.2-3 Trigger Set-Up Register (D[3:0]/0x40299) HSD3S[3:0]: Ch.3 Trigger Set-Up Bits in the HSDMA Ch.2-3 Trigger Set-Up Register (D[7:4]/0x40299) Table III.4.5.1 shows the setting value and the corresponding trigger source. Table III.4.5.1 HSDMA Trigger Source Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Ch.0 trigger source Software trigger #DMAREQ0 input (falling edge) #DMAREQ0 input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Port 8 input Port 12 input Ch.1 trigger source Software trigger #DMAREQ1 input (falling edge) #DMAREQ1 input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Port 9 input Port 13 input Ch.2 trigger source Software trigger #DMAREQ2 input (falling edge) #DMAREQ2 input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 6 compare B 16-bit timer 6 compare A Serial I/F Ch.2 Rx buffer full Serial I/F Ch.2 Tx buffer empty A/D conversion completion Port 10 input Port 14 input Ch.3 trigger source Software trigger #DMAREQ3 input (falling edge) #DMAREQ3 input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 7 compare B 16-bit timer 7 compare A Serial I/F Ch.3 Rx buffer full Serial I/F Ch.3 Tx buffer empty A/D conversion completion Port 11 input Port 15 input By selecting a cause of interrupt with the HSDMA trigger set-up register, the HSDMA channel is invoked when the selected interrupt factor occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable register, IDMA request register, interrupt priority register) do not affect this invocation. The cause of interrupt that invokes HSDMA sets the cause-of-interrupt flag. and HSDMA does not reset the flag. Consequently, when the DMA transfer is completed (even if the transfer counter is not 0), an interrupt request to the CPU will be generated if the interrupt has been enabled. To generate an interrupt only when the transfer counter reaches 0, disable the interrupt by the cause of interrupt that invokes HSDMA and use the HSDMA transfer completion interrupt. When software trigger is selected, the HSDMA channel can be invoked by writing 1 to HSTx (Dx/0x4029A). HSTx: Ch.x Software Trigger Bit in the HSDMA Software Trigger Register (Dx/0x4029A) When the selected trigger occurs, the trigger flag is set to 1 to invoke the HSDMA channel. The HSDMA starts a DMA transfer if it has been enabled and the trigger flag is cleared by the hardware at the same time. This makes it possible to queue the HSDMA triggers that have been generated. The trigger flag can be read and cleared using HSx_TF (D0/0x4822E + 0x10*x). HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10*x) By writing 1 to this bit, the set trigger flag can be cleared if the DMA transfer has not been started. When this bit is read, 1 indicates that the flag is set and 0 indicates that the flag is cleared. Note: The following shows the priority order of channels when DMA triggers with the same interrupt level occur in two or more HSDMA and IDMA channels. Priority Channel High Low HSDMA Ch.0 > Ch.1 > Ch.2 > Ch.3 > IDMA software trigger > IDMA hardware trigger S1C33401 TECHNICAL MANUAL EPSON III-4-13 III HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.6 Operation of HSDMA An HSDMA channel starts data transfer by the selected trigger source. Make sure that transfer conditions and a trigger source are set and the HSDMA channel is enabled before starting a DMA transfer. III.4.6.1 Operation in Dual-Address Mode In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by the BBCU and EBCU. HSDMA has three transfer modes, in each of which data transfer operates differently. The following describes the operation of HSDMA in each transfer mode. Single transfer mode (dual-address mode) The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 00 operates in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x). If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup Register (D[15:14]/0x4822A + 0x10*x) DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup Register (D14/0x48226 + 0x10*x) WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode (D0/0x48262 + 0x10*x) The operation of HSDMA in single transfer mode is shown by the flow chart in Figure III.4.6.1.1. START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte, 1 half word or 1 word) Data write to destination (1 byte, 1 half word or 1 word) : according to SxIN/DxIN or SxID/DxID settings Increment/decrement address Transfer counter - 1 Transfer counter = 0 N Y Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.1.1 Operation Flow in Single Transfer Mode III-4-14 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared and then data of the size set in the control information is read from the source address. I HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10*x) (2) The read data is written to the destination address. (3) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10* x)/DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) or SxID (D4/0x48262 + 0x10*x)/DxID (D5/0x48262 + 0x10*x) settings. 1 SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x48226 + 0x10*x) DxIN[1:0]: Ch.x Destination Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x4822A + 0x10*x) SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D4/0x48262 + 0x10*x) DxID: Ch.x Destination Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D5/0x48262 + 0x10*x) (4) The transfer counter is decremented. (5) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) 1: In standard mode, SxID (D4/0x48262 + 0x10*x) and DxID (D5/0x48262 + 0x10*x) are both fixed at 0. III HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-15 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Successive transfer mode (dual-address mode) The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 01 operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 by one transfer executed. The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure III.4.6.1.2. START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte, 1 half word or 1 word) Data write to destination (1 byte, 1 half word or 1 word) Increments/decrements address : according to SxIN/DxIN or SxID/DxID settings Transfer counter - 1 N Transfer counter = 0 Y Restores initial values to address : according to SxIN/DxIN or SxID/DxID settings Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.1.2 Operation Flow in Successive Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared and then data of the size set in the control information is read from the source address. (2) The read data is written to the destination address. (3) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10* x)/DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) or SxID (D4/0x48262 + 0x10*x)/DxID (D5/0x48262 + 0x10*x) settings. 1 (4) The transfer counter is decremented. (5) Steps (1) to (4) are repeated until the transfer counter reaches 0. (6) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10*x)/DxIN[1:0] (D[13:12]/ 0x4822A + 0x10*x) is 10 or SxID (D4/0x48262 + 0x10*x)/DxID (D5/0x48262 + 0x10*x) is 1. 1 (7) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. 1: In standard mode, SxID (D4/0x48262 + 0x10*x) and DxID (D5/0x48262 + 0x10*x) are both fixed at 0. III-4-16 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Block transfer mode (dual-address mode) I The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 10 operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of HSDMA in block transfer mode is shown by the flow chart in Figure III.4.6.1.3. BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register (D[7:0]/0x48220 + 0x10*x) START Clear trigger flag HSx_TF to accept next trigger Data read from source (1 byte, 1 half word or 1 word) Data write to destination (1 byte, 1 half word or 1 word) : according to SxIN/DxIN or SxID/DxID settings Increments/decrements address Block size - 1 III Block size = 0 N 1-block transfer Y : according to SxIN/DxIN or SxID/DxID settings Restores initial values to block size and address HSDMA Transfer counter - 1 Transfer counter = 0 N Y Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.1.3 Operation Flow in Block Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared and then data of the size set in the control information is read from the source address. (2) The read data is written to the destination address. (3) The address is incremented or decremented and BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) is decremented. (4) Steps (1) to (3) are repeated until BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) reaches 0. (5) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10*x)/DxIN[1:0] (D[13:12]/ 0x4822A + 0x10*x) is 10 or SxID (D4/0x48262 + 0x10*x)/DxID (D5/0x48262 + 0x10*x) is 1. 1 (6) The transfer counter is decremented. (7) Steps (1) to (6) are repeated until the transfer counter reaches 0. (8) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. 1: In standard mode, SxID (D4/0x48262 + 0x10*x) and DxID (D5/0x48262 + 0x10*x) are both fixed at 0. S1C33401 TECHNICAL MANUAL EPSON III-4-17 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.6.2 Operation in Single-Address Mode In single-address mode, data read/write operations are performed simultaneously. The data transfer direction (read from I/O device write to memory or read from memory write to I/O device) is set using DxDIR (D14/0x48222 + 0x10*x) DxDIR: Ch.x Transfer Direction Control Bit in the HSDMA Ch.x Control Register (D14/0x48222 + 0x10*x) Single-address mode has three transfer modes, in each of which data transfer operates differently. The following describes the operation of HSDMA in single-transfer mode. #DMAACKx signal output and bus operation When the HSDMA circuit accepts the DMA request, it outputs a low-level pulse from the #DMAACKx pin and starts bus operation for the memory at the same time. The contents of this bus operation are as follows: * Data transfer from I/O device to memory (DxDIR (D14/0x48222 + 0x10*x) = 1) The address that has been set in the memory address register is output to the address bus. A write operation is performed under the interface conditions set on the area to which the memory at the destination of transfer belongs. The data bus is left floating. The external I/O device outputs the transfer data onto the data bus using the #DMAACKx signal as the read signal. The memory takes in this data using the write signal. * Data transfer from memory to an I/O device (DxDIR (D14/0x48222 + 0x10*x) = 0, default) The address that has been set in the memory address register is output to the address bus. A read operation is performed under the interface conditions set on the area to which the memory at the source of transfer belongs. The memory outputs the transfer data onto the data bus using the read signal. The external I/O device takes in the data from the data bus using the #DMAACKx signal as the write signal. The number of bus operations for a DMA transfer is decided according to the transfer data size and I/O device size as shown in the table below. Table III.4.6.2.1 Number of Bus Operations Per DMA Transfer Transfer data size I/O device size Number of bus operations 32 bits 32 bits 16 bits 8 bits 16 bits 8 bits 4 2 2 1 Other Notes: * A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) cannot be used for single-address transfer. * Single-address mode does not allow data transfer between memory devices. An external logic circuit is required to perform single-address transfer between memory devices. * Single-address mode does not support the external memory area that is configured for SDRAM. #DMAENDx signal output When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating that a specified number of transfers has been completed. At the same time, the cause-of-interrupt (completion of HSDMA) is generated. III-4-18 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Single transfer mode (single address mode) I The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 00 operates in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x). If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup Register (D[15:14]/0x4822A + 0x10*x) DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup Register (D14/0x48226 + 0x10*x) WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode (D0/0x48262 + 0x10*x) The operation of HSDMA in single transfer mode is shown by the flow chart in Figure III.4.6.2.1. START Clear trigger flag HSx_TF to accept next trigger Data read from source and data write to destination (1 byte, 1 half word or 1 word) Increment/decrement address : according to SxIN or SxID settings III Transfer counter - 1 Transfer counter = 0 N HSDMA Y Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.2.1 Operation Flow in Single Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared. Data of the size set in the control information is read from the external memory or I/O device according to the specified direction and is written to the I/O device or external memory. 1 HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10*x) (2) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) or SxID (D4/0x48262 + 0x10*x) settings. 2 SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup Register (D[13:12]/0x48226 + 0x10*x) SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode (D4/0x48262 + 0x10*x) (3) The transfer counter is decremented. (4) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) S1C33401 TECHNICAL MANUAL EPSON III-4-19 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the external memory read/write address is delivered from the memory address registers in the control information SxADRL and SxADRH. SxADRL: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register (STD mode: D[15:0]/0x48224 + 0x10*x, ADV mode: D[15:0]/0x48264 + 0x10*x) SxADRH: Ch.x Source Address (high-order bits) in the HSDMA Ch.x High-Order Source Address Setup Register (STD mode: D[11:0]/0x48226 + 0x10*x, ADV mode: D[15:0]/0x48266 + 0x10*x) 2: In standard mode, SxID (D4/0x48262 + 0x10*x) is fixed at 0. Successive transfer mode (single address mode) The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 01 operates in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 by one transfer executed. The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure III.4.6.2.2. START Clear trigger flag HSx_TF to accept next trigger Data read from source and data write to destination (1 byte, 1 half word or 1 word) Increments/decrements address : according to SxIN or SxID settings Transfer counter - 1 Transfer counter = 0 N Y Restores initial values to address : according to SxIN or SxID settings Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.2.2 Operation Flow in Successive Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared. Data of the size set in the control information is read from the external memory or I/O device according to the specified direction and is written to the I/O device or external memory. 1 (2) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) or SxID (D4/0x48262 + 0x10*x) settings. 2 (3) The transfer counter is decremented. (4) Steps (1) to (3) are repeated until the transfer counter reaches 0. (5) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) is 10 or SxID (D4/0x48262 + 0x10*x) is 1. 2 (6) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. 1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the external memory read/write address is delivered from the memory address registers in the control information SxADRL and SxADRH. 2: In standard mode, SxID (D4/0x48262 + 0x10*x) is fixed at 0. III-4-20 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Block transfer mode (single address mode) I The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10*x) in control information is set to 10 operates in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of HSDMA in block transfer mode is shown by the flow chart in Figure III.4.6.2.3. BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register (D[7:0]/0x48220 + 0x10*x) START Clear trigger flag HSx_TF to accept next trigger Data read from source and data write to destination (1 byte, 1 half word or 1 word) : according to SxIN or SxID settings Increments/decrements address Block size - 1 Block size = 0 N III 1-block transfer Y : according to SxIN or SxID settings Restores initial values to block size and address HSDMA Transfer counter - 1 Transfer counter = 0 N Y Clear HSDMA enable bit HSx_EN Set cause-of-interrupt flag FHDMx END Figure III.4.6.2.3 Operation Flow in Block Transfer Mode (1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10*x) is cleared. Data of the size set in the control information is read from the external memory or I/O device according to the specified direction and is written to the I/O device or external memory. 1 (2) The address is incremented or decremented and BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) is decremented. (3) Steps (1) to (2) are repeated until BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x) reaches 0. (4) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) is 10 or SxID (D4/0x48262 + 0x10*x) is 1. 2 (5) The transfer counter is decremented. (6) Steps (1) to (5) are repeated until the transfer counter reaches 0. (7) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10*x) is cleared and HSDMA cause-of-interrupt flag in ITC is set when the transfer counter reaches 0. 1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the external memory read/write address is delivered from the memory address registers in the control information SxADRL and SxADRH. 2: In standard mode, SxID (D4/0x48262 + 0x10*x) is fixed at 0. S1C33401 TECHNICAL MANUAL EPSON III-4-21 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.7 Interrupt Function of HSDMA The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0. Furthermore, channels 0 and 1 can invoke IDMA using their cause of interrupt. Control registers of the interrupt controller Table III.4.7.1 shows the control registers of the interrupt controller that are provided for each channel. Table III.4.7.1 Control Registers of Interrupt Controller Channel Cause-of-interrupt flag Interrupt enable register Interrupt priority register FHDM0(D0/0x40281) FHDM1(D1/0x40281) FHDM2(D2/0x40281) FHDM3(D3/0x40281) EHDM0(D0/0x40271) EHDM1(D1/0x40271) EHDM2(D2/0x40271) EHDM3(D3/0x40271) PHSD0L[2:0](D[2:0]/0x40263) PHSD1L[2:0](D[6:4]/0x40263) PHSD2L[2:0](D[2:0]/0x40264) PHSD3L[2:0](D[6:4]/0x40264) Ch. 0 Ch. 1 Ch. 2 Ch. 3 The HSDMA controller sets the HSDMA cause-of-interrupt flag to 1 when the transfer counter reaches 0 after completing a series of HSDMA transfers. If the corresponding bit of the interrupt enable register is set to 1 at this time, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit set to 0. The HSDMA cause-of-interrupt flag is always set to 1 when the data transfer in each channel is completed no matter what value the interrupt enable register bit is set to. (This is true even when it is set to 0.) The interrupt priority register sets an interrupt priority level (0 to 7). An interrupt request to the CPU is accepted only when there is no other interrupt request of higher priority. Furthermore, it is only when the PSR's IE bit = 1 (interrupt enable) and the set value of IL is smaller than the HSDMA interrupt level which is set in the interrupt priority register that the CPU actually accepts a HSDMA interrupt. For details about the interrupt control register and for the device operation when an interrupt occurs, refer to Section IV.2, "Interrupt Controller (ITC)." Intelligent DMA Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt source of channels 0 and 1 of HSDMA. The following shows the IDMA channels set in HSDMA: IDMA channel Channel 0 end-of-transfer interrupt: 0x05 Channel 1 end-of-transfer interrupt: 0x06 Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must be set to 1. Settings of transfer conditions on the IDMA side are also required. Table III.4.7.2 Control Bits for IDMA Transfer Channel IDMA request bit IDMA enable bit Ch. 0 Ch. 1 RHDM0(D4/0x40290) RHDM1(D5/0x40290) DEHDM0(D4/0x40294) DEHDM1(D5/0x40294) If the IDMA request and enable bits are set to 1, IDMA is invoked through generation of a cause of interrupt. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." Trap vector The trap vector addresses for causes of interrupt in each channel are set by default as follows: Channel 0 end-of-transfer interrupt: 0x20000058 Channel 1 end-of-transfer interrupt: 0x2000005C Channel 2 end-of-transfer interrupt: 0x20000060 Channel 3 end-of-transfer interrupt: 0x20000064 Note that the trap table base address can be modified using the TTBR register. III-4-22 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.8 HSDMA Operating Clock I The HSDMA circuit is clocked by the core system clock (CCLK) generated by the CMU. For details on how to set CCLK and control the clock, see Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the HSDMA operating clock CCLK is supplied to the DMA controller with default settings. When DMA transfer is not performed, the clock supply can be turned off using DMACLK (D2/0x48370) to reduce the amount of power consumed on the chip. Moreover, the clock automatic control function may be enabled using DMAAUTO (D2/0x48372). DMACLK: DMA Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D2/0x48370) DMAAUTO: DMA Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control Register (D2/0x48372) Setting DMACLK (D2/0x48370) to 0 (initially 1) turns off the corresponding clock supply to the DMA controller. Setting both the clock control bit and automatic control bit (initially 0) to 1 enables the automatic control function for the clock supply. If the DMA controller enters the IDLE state while the automatic control function is enabled, clock-enable signal input to the CMU is negated. As a result, the CMU stops supplying a clock to the DMA controller. This state is called power-down mode of the DMA controller. When any block generates an operation request to the DMA controller, the DMA controller immediately reasserts the clock-enable signal. Clock supply from the CMU is resumed one clock after the clock-enable signal becomes active. III Note: The clock supply should be automatically controlled to reduce the amount of power consumed on the chip. However, limitations are imposed on the supported operating clock frequency, etc. For details, see Section II.3, "Clock Management Unit (CMU)." Clock state in standby mode HSDMA The supply of CCLK stops depending on type of standby mode. HALT mode: CCLK is supplied the same way as in normal mode. HALT2 mode: The supply of CCLK stops. SLEEP mode: The supply of CCLK stops. Therefore, the DMA controller also stops operating when in HALT2 and SLEEP modes. S1C33401 TECHNICAL MANUAL EPSON III-4-23 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.9 Details of Control Registers Table III.4.9.1 List of HSDMA Registers Address 0x00048220 0x00048222 0x00048224 0x00048226 0x00048228 0x0004822A 0x0004822C 0x0004822E 0x00048230 0x00048232 0x00048234 0x00048236 0x00048238 0x0004823A 0x0004823C 0x0004823E 0x00048240 0x00048242 0x00048244 0x00048246 0x00048248 0x0004824A 0x0004824C 0x0004824E 0x00048250 0x00048252 0x00048254 0x00048256 0x00048258 0x0004825A 0x0004825C 0x0004825E III-4-24 Size Function 16 Sets Ch.0 low-order transfer counter data and block length. 16 Sets Ch.0 address mode and high-order transfer HSDMA Ch.0 Control Register counter data. HSDMA Ch.0 Low-Order Source Address Setup Register 16 Sets Ch.0 low-order source address. (pHS0_SADR) 16 Sets Ch.0 high-order source address, transfer data HSDMA Ch.0 High-Order Source Address Setup Register size, and source address inc/dec condition. 16 Sets Ch.0 low-order destination address. HSDMA Ch.0 Low-Order Destination Address Setup Register (pHS0_DADR) 16 Sets Ch.0 high-order destination address, transfer HSDMA Ch.0 High-Order Destination Address Setup Register mode, and destination address inc/dec condition. 16 Enables Ch.0 DMA transfer. HSDMA Ch.0 Enable Register (pHS0_EN) 16 Ch.0 trigger status HSDMA Ch.0 Trigger Flag Register (pHS0_TF) 16 Sets Ch.1 low-order transfer counter data and block HSDMA Ch.1 Transfer Counter Register (pHS1_CNT) length. 16 Sets Ch.1 address mode and high-order transfer HSDMA Ch.1 Control Register counter data. HSDMA Ch.1 Low-Order Source Address Setup Register 16 Sets Ch.1 low-order source address. (pHS1_SADR) 16 Sets Ch.1 high-order source address, transfer data HSDMA Ch.1 High-Order Source Address Setup Register size, and source address inc/dec condition. 16 Sets Ch.1 low-order destination address. HSDMA Ch.1 Low-Order Destination Address Setup Register (pHS1_DADR) 16 Sets Ch.1 high-order destination address, transfer HSDMA Ch.1 High-Order Destination Address Setup Register mode, and destination address inc/dec condition. 16 Enables Ch.1 DMA transfer. HSDMA Ch.1 Enable Register (pHS1_EN) 16 Ch.1 trigger status HSDMA Ch.1 Trigger Flag Register (pHS1_TF) 16 Sets Ch.2 low-order transfer counter data and block HSDMA Ch.2 Transfer Counter Register (pHS2_CNT) length. 16 Sets Ch.2 address mode and high-order transfer HSDMA Ch.2 Control Register counter data. HSDMA Ch.2 Low-Order Source Address Setup Register 16 Sets Ch.2 low-order source address. (pHS2_SADR) 16 Sets Ch.2 high-order source address, transfer data HSDMA Ch.2 High-Order Source Address Setup Register size, and source address inc/dec condition. 16 Sets Ch.2 low-order destination address. HSDMA Ch.2 Low-Order Destination Address Setup Register (pHS2_DADR) 16 Sets Ch.2 high-order destination address, transfer HSDMA Ch.2 High-Order Destination Address Setup Register mode, and destination address inc/dec condition. 16 Enables Ch.2 DMA transfer. HSDMA Ch.2 Enable Register (pHS2_EN) 16 Ch.2 trigger status HSDMA Ch.2 Trigger Flag Register (pHS2_TF) 16 Sets Ch.3 low-order transfer counter data and block HSDMA Ch.3 Transfer Counter Register (pHS3_CNT) length. 16 Sets Ch.3 address mode and high-order transfer HSDMA Ch.3 Control Register counter data. HSDMA Ch.3 Low-Order Source Address Setup Register 16 Sets Ch.3 low-order source address. (pHS3_SADR) 16 Sets Ch.3 high-order source address, transfer data HSDMA Ch.3 High-Order Source Address Setup Register size, and source address inc/dec condition. 16 Sets Ch.3 low-order destination address. HSDMA Ch.3 Low-Order Destination Address Setup Register (pHS3_DADR) 16 Sets Ch.3 high-order destination address, transfer HSDMA Ch.3 High-Order Destination Address Setup Register mode, and destination address inc/dec condition. 16 Enables Ch.3 DMA transfer. HSDMA Ch.3 Enable Register (pHS3_EN) 16 Ch.3 trigger status HSDMA Ch.3 Trigger Flag Register (pHS3_TF) Register name HSDMA Ch.0 Transfer Counter Register (pHS0_CNT) EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Address 0x00048262 0x00048264 0x00048266 0x00048268 0x0004826A 0x00048272 0x00048274 0x00048276 0x00048278 0x0004827A 0x00048282 0x00048284 0x00048286 0x00048288 0x0004828A 0x00048292 0x00048294 0x00048296 0x00048298 0x0004829A 0x0004829C Function Register name Size HSDMA Ch.0 Control Register (pHS0_ADVMODE) for 16 Selects Ch.0 ADV mode functions. ADV mode HSDMA Ch.0 Low-Order Source Address Setup Register 16 Sets Ch.0 low-order source address for ADV mode. (pHS0_AD_SADR) for ADV mode HSDMA Ch.0 High-Order Source Address Setup 16 Sets Ch.0 high-order source address for ADV mode. Register for ADV mode HSDMA Ch.0 Low-Order Destination Address Setup 16 Sets Ch.0 low-order destination address for ADV mode. Register (pHS0_ADV_DADR) for ADV mode HSDMA Ch.0 High-Order Destination Address Setup 16 Sets Ch.0 high-order destination address for ADV mode. Register for ADV mode HSDMA Ch.1 Control Register (pHS1_ADVMODE) for 16 Selects Ch.1 ADV mode functions. ADV mode HSDMA Ch.1 Low-Order Source Address Setup Register 16 Sets Ch.1 low-order source address for ADV mode. (pHS1_AD_SADR) for ADV mode HSDMA Ch.1 High-Order Source Address Setup 16 Sets Ch.1 high-order source address for ADV mode. Register for ADV mode HSDMA Ch.1 Low-Order Destination Address Setup 16 Sets Ch.1 low-order destination address for ADV mode. Register (pHS1_ADV_DADR) for ADV mode HSDMA Ch.1 High-Order Destination Address Setup 16 Sets Ch.1 high-order destination address for ADV mode. Register for ADV mode HSDMA Ch.2 Control Register (pHS2_ADVMODE) for 16 Selects Ch.2 ADV mode functions. ADV mode HSDMA Ch.2 Low-Order Source Address Setup Register 16 Sets Ch.2 low-order source address for ADV mode. (pHS2_AD_SADR) for ADV mode HSDMA Ch.2 High-Order Source Address Setup 16 Sets Ch.2 high-order source address for ADV mode. Register for ADV mode HSDMA Ch.2 Low-Order Destination Address Setup 16 Sets Ch.2 low-order destination address for ADV mode. Register (pHS2_ADV_DADR) for ADV mode HSDMA Ch.2 High-Order Destination Address Setup 16 Sets Ch.2 high-order destination address for ADV mode. Register for ADV mode HSDMA Ch.3 Control Register (pHS3_ADVMODE) for 16 Selects Ch.3 ADV mode functions. ADV mode HSDMA Ch.3 Low-Order Source Address Setup Register 16 Sets Ch.3 low-order source address for ADV mode. (pHS3_AD_SADR) for ADV mode HSDMA Ch.3 High-Order Source Address Setup 16 Sets Ch.3 high-order source address for ADV mode. Register for ADV mode HSDMA Ch.3 Low-Order Destination Address Setup 16 Sets Ch.3 low-order destination address for ADV mode. Register (pHS3_ADV_DADR) for ADV mode HSDMA Ch.3 High-Order Destination Address Setup 16 Sets Ch.3 high-order destination address for ADV mode. Register for ADV mode HSDMA STD/ADV Mode Select Register 16 Selects standard or advanced mode. (pHS_CNTLMODE) The following describes each HSDMA control register. The HSDMA control registers are mapped in the 16-bit device area from 0x48220 to 0x4829C, and can be accessed in units of half-words or bytes. Note: When setting the HSDMA control registers, be sure to write a 0, and not a 1, for all "reserved bits." S1C33401 TECHNICAL MANUAL EPSON III-4-25 I III HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48220-0x48250: HSDMA Ch.x Transfer Counter Registers (pHSx_CNT) Register name Address Bit Name 0048220 | 0048250 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TCx_L7 TCx_L6 TCx_L5 TCx_L4 TCx_L3 TCx_L2 TCx_L1 TCx_L0 BLKLENx7 BLKLENx6 BLKLENx5 BLKLENx4 BLKLENx3 BLKLENx2 BLKLENx1 BLKLENx0 HSDMA Ch.x transfer counter register (pHSx_CNT) Function Setting Ch.x transfer counter[7:0] (block transfer mode) Ch.x transfer counter[15:8] (single/successive transfer mode) Ch.x block length (block transfer mode) Ch.x transfer counter[7:0] (single/successive transfer mode) Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48220 0x48230 0x48240 0x48250 HSDMA Ch.0 Transfer Counter Register (pHS0_CNT) HSDMA Ch.1 Transfer Counter Register (pHS1_CNT) HSDMA Ch.2 Transfer Counter Register (pHS2_CNT) HSDMA Ch.3 Transfer Counter Register (pHS3_CNT) D[15:8] TCx_L[7:0]: Ch.x Transfer Counter Bits Set the data transfer count. (Default: 0x00) In block transfer mode, TCx_L[7:0] is bits[7:0] of the transfer counter. In single or successive transfer mode, TCx_L[7:0] is bits[15:8] of the transfer counter. This counter is decremented each time a DMA transfer in the corresponding channel is performed. When the counter reaches 0, a cause of interrupt is generated. In single-address mode, the end-oftransfer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a DMA request is accepted and the counter is decremented to 0xFFFF (or 0xFFFFFF). Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing and reading to and from the counter. D[7:0] BLKLENx[7:0]: Ch.x Block Length Bits In block transfer mode, these bits are used to specify a transfer block size. (Default: 0x00) A transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx[7:0]. In single or successive transfer mode, these bits are used to specify the 8 low-order bits of the transfer counter. Note: When performing data transfer in block transfer mode, the block size must not be set to 0. III-4-26 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48222-0x48252: HSDMA Ch.x Control Registers Register name Address Bit Name HSDMA Ch.x 0048222 D15 DUALMx D14 DxDIR control register | 0048252 Note: D13-8 - (HW) D) Dual address D7 TCx_H7 mode D6 TCx_H6 S) Single D5 TCx_H5 address D4 TCx_H4 mode D3 TCx_H3 D2 TCx_H2 D1 TCx_H1 D0 TCx_H0 Function Ch.x address mode selection D) Invalid S) Ch.x transfer direction control reserved Ch.x transfer counter[15:8] (block transfer mode) Setting 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.x transfer counter[23:16] (single/successive transfer mode) I Init. R/W 0 - 0 - 0 0 0 0 0 0 0 0 Remarks R/W - R/W - 0 when being read. R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48222 0x48232 0x48242 0x48252 D15 HSDMA Ch.0 Control Register HSDMA Ch.1 Control Register HSDMA Ch.2 Control Register HSDMA Ch.3 Control Register DUALMx: Ch.x Address Mode Select Bit Select an address mode. 1 (R/W): Dual-address mode 0 (R/W): Single-address mode (default) III When 1 is written to DUALMx, the HSDMA channel enters dual-address mode that allows specification of source and destination addresses. When 0 is written, the HSDMA channel enters single-address mode for high-speed data transfer between the external memory and an I/O device. D14 HSDMA DxDIR: Ch.x Transfer Direction Control Bit Control the direction of data transfer in single-address mode. 1 (R/W): Memory write 0 (R/W): Memory read (default) Data transfer from an external I/O device to external memory (or an external/internal I/O) is performed by writing 1 to DxDIR. Data transfer from external memory (or an external/internal I/O) to an external I/O is performed by writing 0. This bit is effective only in single-address mode. D[13:8] Reserved D[7:0] TCx_H[7:0]: Ch.x Transfer Counter Bits Set the data transfer count. (Default: 0x00) In block transfer mode, TCx_H[7:0] is bits[15:8] of the transfer counter. In single or successive transfer mode, TCx_H[7:0] is bits[23:16] of the transfer counter. This counter is decremented each time a DMA transfer in the corresponding channel is performed. When the counter reaches 0, a cause of interrupt is generated. In single-address mode, the end-oftransfer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a DMA request is accepted and the counter is decremented to 0xFFFF (or 0xFFFFFF). Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing and reading to and from the counter. S1C33401 TECHNICAL MANUAL EPSON III-4-27 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48224-0x48254: HSDMA Ch.x Low-Order Source Address Setup Registers (pHSx_SADR) Register name Address Bit 0048224 HSDMA Ch.x | low-order source address 0048254 (HW) setup register (pHSx_SADR) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: D) Dual address mode S) Single address mode Name Function Setting SxADRL15 D) Ch.x source address[15:0] SxADRL14 S) Ch.x memory address[15:0] SxADRL13 SxADRL12 SxADRL11 SxADRL10 SxADRL9 SxADRL8 SxADRL7 SxADRL6 SxADRL5 SxADRL4 SxADRL3 SxADRL2 SxADRL1 SxADRL0 Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48224 0x48234 0x48244 0x48254 D[15:0] HSDMA Ch.0 Low-Order Source Address Setup Register (pHS0_SADR) HSDMA Ch.1 Low-Order Source Address Setup Register (pHS1_SADR) HSDMA Ch.2 Low-Order Source Address Setup Register (pHS2_SADR) HSDMA Ch.3 Low-Order Source Address Setup Register (pHS3_SADR) SxADRL[15:0]: Ch.x Source Address[15:0] (for standard mode) In dual-address mode, these bits are used to specify a source address. In single-address mode, an external memory address at the destination or source of transfer is specified. Use SxADRL[15:0] to set the 16 low-order bits of the address. Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing or reading to and from these registers. The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) or SxID (D4/0x48262 + 0x10*x)) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. Notes: * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if they are located in the area for which the MMU is enabled for use. * The following areas cannot be used for DMA transfer: Dual-address mode: Area 0 (A0RAM), Area 2 Single-address mode: Area 0 (A0RAM), Area 1 (peripherals), Area 2, Area 3 (A3RAM) * Single-address mode does not allow data transfer between memory devices. * Single-address mode does not support the external memory area that is configured for SDRAM. * Use SxADRL[15:0] (D[15:0]/0x48264 + 0x10*x) and SxADRH[15:0] (D[15:0]/0x48266 + 0x10*x) for specifying an address in advanced mode. III-4-28 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48226-0x48256: HSDMA Ch.x High-Order Source Address Setup Registers Register name Address Bit Name Function Setting 0048226 HSDMA Ch.x | high-order source address 0048256 (HW) setup register D15 D14 D13 D12 - DATSIZEx SxIN1 SxIN0 reserved Ch.x transfer data size D) Ch.x source address control S) Ch.x memory address control - D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SxADRH11 D) Ch.x source address[27:16] SxADRH10 S) Ch.x memory address[27:16] SxADRH9 SxADRH8 SxADRH7 SxADRH6 SxADRH5 SxADRH4 SxADRH3 SxADRH2 SxADRH1 SxADRH0 Note: D) Dual address mode S) Single address mode 1 Half word SxIN[1:0] 11 10 01 00 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W I Remarks - 0 0 0 - 0 when being read. R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48226 0x48236 0x48246 0x48256 HSDMA Ch.0 High-Order Source Address Setup Register HSDMA Ch.1 High-Order Source Address Setup Register HSDMA Ch.2 High-Order Source Address Setup Register HSDMA Ch.3 High-Order Source Address Setup Register D15 Reserved D14 DATSIZEx: Ch.x Transfer Data Size Select Bit Select the data size to be transferred. 1 (R/W): Half-word 0 (R/W): Byte (default) III HSDMA The transfer data size is set to 16 bits by writing 1 to DATSIZEx and set to 8 bits by writing 0. Note: In advanced mode, this bit is effective when WORDSIZEx (D0/0x48262 + 0x10*x) = 0. The setting of this bit is ignored when WORDSIZEx (D0/0x48262 + 0x10*x) = 1 and the transfer data size is set to 32 bits. In standard mode, this bit is always effective regardless of the WORDSIZEx (D0/0x48262 + 0x10*x) setting. D[13:12] SxIN[1:0]: Ch.x Source Address Control Bits Control the incrementing or decrementing of the memory address. Table III.4.9.2 Address Control SxIN1 SxIN0 Address control 1 1 0 0 1 0 1 0 Increment without initialization Increment with initialization Decrement without initialization Fixed (Default: 0b00) In dual-address mode, this setting applies to the source address. In single-address mode, this setting applies to the external memory address. When "Fixed" (00) is selected, the source address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read from the same address. When "Increment without initialization" (11) is selected, the source address is incremented by an amount equal to the data size set by DATSIZEx (D14) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. S1C33401 TECHNICAL MANUAL EPSON III-4-29 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) When "Decrement without initialization" (01) is selected, the source address is decremented in the same way. When "Increment with initialization" (10) is selected, the source address is incremented by an amount equal to the data size set by DATSIZEx (D14) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. In single transfer mode, the address that has been incremented during transfer does not return to the initial value. In successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the incremented address returns to the initial value when the block transfer is completed. Note: In advanced mode, these bits are effective when SxID (D4/0x48262 + 0x10*x) = 0. The setting of these bits is ignored when SxID (D4/0x48262 + 0x10*x) = 1 and "Decrement with initialization" is selected. In standard mode, this bit is always effective regardless of the SxID (D4/0x48262 + 0x10*x) setting. D[11:0] III-4-30 SxADRH[11:0]: Ch.x Source Address[27:16] (for standard mode) In dual-address mode, these bits are used to specify 12 high-order bits of source address. In singleaddress mode, 12 high-order bits of external memory address at the destination or source of transfer is specified. See SxADRL[15:0] (D[15:0]/0x48224 + 0x10*x) for more information. EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48228-0x48258: HSDMA Ch.x Low-Order Destination Address Setup Registers (pHSx_DADR) Register name Address Bit 0048228 | 0048258 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HSDMA Ch.x low-order destination address setup register (pHSx_DADR) Note: D) Dual address mode S) Single address mode Name Function Setting DxADRL15 D) Ch.x destination address[15:0] DxADRL14 S) Invalid DxADRL13 DxADRL12 DxADRL11 DxADRL10 DxADRL9 DxADRL8 DxADRL7 DxADRL6 DxADRL5 DxADRL4 DxADRL3 DxADRL2 DxADRL1 DxADRL0 Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I Remarks R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48228 0x48238 0x48248 0x48258 D[15:0] HSDMA Ch.0 Low-Order Destination Address Setup Register (pHS0_DADR) HSDMA Ch.1 Low-Order Destination Address Setup Register (pHS1_DADR) HSDMA Ch.2 Low-Order Destination Address Setup Register (pHS2_DADR) HSDMA Ch.3 Low-Order Destination Address Setup Register (pHS3_DADR) III DxADRL[15:0]: Ch.x Destination Address[15:0] (for standard mode) In dual-address mode, these bits are used to specify a destination address. Use DxADRL[15:0] to set the 16 low-order bits of the address. Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing or reading to and from these registers. The address is incremented or decremented (as set by DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) or DxID (D5/0x48262 + 0x10*x)) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. Notes: * In single-address mode, these bits are not used. * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in the area for which the MMU is enabled to use. * The following areas cannot be specified for destination addresses: Area 0 (A0RAM), Area 2 * Use DxADRL[15:0] (D[15:0]/0x48268 + 0x10*x) and DxADRH[15:0] (D[15:0]/0x4826A + 0x10*x) for specifying an address in advanced mode. S1C33401 TECHNICAL MANUAL EPSON III-4-31 HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x4822A-0x4825A: HSDMA Ch.x High-Order Destination Address Setup Registers Register name Address Bit Name 004822A | 004825A (HW) D15 D14 DxMOD1 DxMOD0 Ch.x transfer mode D13 D12 DxIN1 DxIN0 D) Ch.x destination address control S) Invalid D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DxADRH11 D) Ch.x destination DxADRH10 address[27:16] DxADRH9 S) Invalid DxADRH8 DxADRH7 DxADRH6 DxADRH5 DxADRH4 DxADRH3 DxADRH2 DxADRH1 DxADRH0 HSDMA Ch.x high-order destination address setup register Note: D) Dual address mode S) Single address mode Function Setting DxMOD[1:0] 11 10 01 00 DxIN[1:0] 11 10 01 00 Init. R/W Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed 0 0 R/W 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W Remarks Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x4822A 0x4823A 0x4824A 0x4825A HSDMA Ch.0 High-Order Destination Address Setup Register HSDMA Ch.1 High-Order Destination Address Setup Register HSDMA Ch.2 High-Order Destination Address Setup Register HSDMA Ch.3 High-Order Destination Address Setup Register D[15:14] DxMOD[1:0]: Ch.x Transfer Mode Select Bits Select a transfer mode. Table III.4.9.3 Transfer Mode DxMOD1 DxMOD0 Mode 1 1 0 0 1 0 1 0 Invalid Block transfer mode Successive transfer mode Single transfer mode (Default: 0b00) In single transfer mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x). In successive transfer mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. In block transfer mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10*x). D[13:12] DxIN[1:0]: Ch.x Destination Address Control Bits Control the incrementing or decrementing of the memory address. Table III.4.9.4 Address Control DxIN1 DxIN0 Address control 1 1 0 0 1 0 1 0 Increment without initialization Increment with initialization Decrement without initialization Fixed (Default: 0b00) In dual-address mode, this setting applies to the destination address. When "Fixed" (00) is selected, the destination address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always written to the same address. III-4-32 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) When "Increment without initialization" (11) is selected, the destination address is incremented by an amount equal to the data size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. When "Decrement without initialization" (01) is selected, the destination address is decremented in the same way. When "Increment with initialization" (10) is selected, the destination address is incremented by an amount equal to the data size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. In single transfer mode, the address that has been incremented during transfer does not return to the initial value. In successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the incremented address returns to the initial value when the block transfer is completed. I In single-address mode, these bits are not used. Note: In advanced mode, these bits are effective when DxID (D5/0x48262 + 0x10*x) = 0. The setting of these bits is ignored when DxID (D5/0x48262 + 0x10*x) = 1 and "Decrement with initialization" is selected. In standard mode, this bit is always effective regardless of the DxID (D5/0x48262 + 0x10*x) setting. D[11:0] DxADRH[11:0]: Ch.x Destination Address[27:16] (for standard mode) In dual-address mode, these bits are used to specify 12 high-order bits of destination address. See DxADRL[15:0] (D[15:0]/0x48228 + 0x10*x) for more information. III In single-address mode, these bits are not used. HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-33 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x4822C-0x4825C: HSDMA Ch.x Enable Registers (pHSx_EN) Register name Address Bit Name 004822C D15-1 - HSDMA Ch.x | enable register D0 HSx_EN 004825C (pHSx_EN) (HW) Function Setting - reserved Ch.x enable 1 Enable 0 Disable Init. R/W - - 0 R/W Remarks 0 when being read. Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x4822C 0x4823C 0x4824C 0x4825C HSDMA Ch.0 Enable Register (pHS0_EN) HSDMA Ch.1 Enable Register (pHS1_EN) HSDMA Ch.2 Enable Register (pHS2_EN) HSDMA Ch.3 Enable Register (pHS3_EN) D[15:1] Reserved D0 HSx_EN: Ch.x Enable Bit Enable a DMA transfer. 1 (R/W): Enable 0 (R/W): Disable (default) DMA transfer is enabled by writing 1 to this bit. HSDMA is placed in a state ready to accept a DMA request from the #DMAREQx pin or by the selected trigger source. DMA transfer is disabled by writing 0 to this bit. When DMA transfers are completed (transfer counter = 0), HSx_EN is cleared by the hardware. Be sure to disable DMA transfers (HSx_EN = 0) before setting the transfer condition. III-4-34 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x4822E-0x4825E: HSDMA Ch.x Trigger Flag Registers (pHSx_TF) Register name Address HSDMA Ch.x trigger flag register (pHSx_TF) Bit Name 004822E D15-1 - | D0 HSx_TF 004825E (HW) Function Setting - reserved Ch.x trigger flag clear (writing) Ch.x trigger flag status (reading) 1 Clear 1 Set 0 No operation 0 Cleared Init. R/W - - 0 R/W I Remarks 0 when being read. Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x4822E 0x4823E 0x4824E 0x4825E HSDMA Ch.0 Trigger Flag Register (pHS0_TF) HSDMA Ch.1 Trigger Flag Register (pHS1_TF) HSDMA Ch.2 Trigger Flag Register (pHS2_TF) HSDMA Ch.3 Trigger Flag Register (pHS3_TF) D[15:1] Reserved D0 HSx_TF: Ch.x Trigger Flag Clear/Status Bit These bits are used to check and clear the trigger flag status. 1 (R): Trigger flag has been set 0 (R): Trigger flag has been cleared (default) 1 (W): Clear trigger flag 0 (W): Has no effect The trigger flag is set when a trigger is input to the HSDMA channel and is cleared when the HSDMA channel starts a data transfer. By reading HSx_TF, the flag status can be checked. Writing 1 to HSx_TF clears the trigger flag if the DMA transfer has not been started. III HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-35 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48262-0x48292: HSDMA Ch.x Control Registers (pHSx_ADVMODE) for ADV mode Register name Address Bit Name Function Setting 0048262 D15-6 - HSDMA Ch.x D5 DxID | control register (pHSx_ADVMODE) 0048292 D4 SxID (HW) for ADV mode Note: D) Dual mode S) Single mode - reserved D) Ch.x destination address control 1 Decrement 0 S) Invalid (with init.) D) Ch.x source address control 1 Decrement 0 S) Ch.x memory address control (with init.) - D3-1 - reserved D0 WORDSIZEx Ch.x transfer data size 0 1 Word Init. R/W DxIN[1:0] setting SxIN[1:0] setting DATSIZEx setting Remarks - 0 - 0 when being read. R/W 0 R/W - 0 - 0 when being read. R/W Notes: * This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1). * The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48262 0x48272 0x48282 0x48292 HSDMA Ch.0 Control Register (pHS0_ADVMODE) HSDMA Ch.1 Control Register (pHS1_ADVMODE) HSDMA Ch.2 Control Register (pHS2_ADVMODE) HSDMA Ch.3 Control Register (pHS3_ADVMODE) D[15:6] Reserved D5 DxID: Ch.x Destination Address Control Bit Enable the address decrement function with initialization for destination address. 1 (R/W): Decrement with initialization 0 (R/W): DxIN[1:0] setting is effective (default) When this bit is set to 1 in dual-address mode, the destination address decrement function with initialization is enabled. The destination address is decremented by an amount equal to the data size set by DATSIZEx (D14/0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. In single transfer mode, the address that has been decremented during transfer does not return to the initial value. In successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the decremented address returns to the initial value when the block transfer is completed. When this bit is set to 0, the condition set by DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) is effective. In single-address mode, this bit is not used. D4 SxID: Ch.x Source Address Control Bit Enable the address decrement function with initialization for source address. 1 (R/W): Decrement with initialization 0 (R/W): SxIN[1:0] setting (default) In dual-address mode, this setting applies to the source address. In single-address mode, this setting applies to the external memory address. When this bit is set to 1, the address decrement function with initialization is enabled. The source/ external memory address is decremented by an amount equal to the data size set by DATSIZEx (D14/ 0x48226 + 0x10*x) or WORDSIZEx (D0/0x48262 + 0x10*x) when one data transfer is completed. In single transfer mode, the address that has been decremented during transfer does not return to the initial value. In successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed. In block transfer mode, the decremented address returns to the initial value when the block transfer is completed. When this bit is set to 0, the condition set by SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) is effective. D[3:1] III-4-36 Reserved EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) D0 WORDSIZEx: Ch.x Transfer Data Size Select Bit Select the data size to be transferred. 1 (R/W): Word 0 (R/W): DATSIZEx setting is effective (default) I The transfer data size is set to 32 bits by writing 1 to this bit. When this bit is set to 0, the size set by DATSIZEx (D14/0x48226 + 0x10*x) is effective. III HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-37 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48264-0x48296: HSDMA Ch.x Source Address Setup Registers (pHSx_AD_SADR) for ADV mode Register name Address Bit Name 0048264 HSDMA Ch.x | low-order source address 0048294 (HW) setup register (pHSx_AD_SADR) for ADV mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SxADRL15 SxADRL14 SxADRL13 SxADRL12 SxADRL11 SxADRL10 SxADRL9 SxADRL8 SxADRL7 SxADRL6 SxADRL5 SxADRL4 SxADRL3 SxADRL2 SxADRL1 SxADRL0 SxADRH15 SxADRH14 SxADRH13 SxADRH12 SxADRH11 SxADRH10 SxADRH9 SxADRH8 SxADRH7 SxADRH6 SxADRH5 SxADRH4 SxADRH3 SxADRH2 SxADRH1 SxADRH0 Note: D) Dual address mode S) Single address mode 0048266 HSDMA Ch.x | high-order source address 0048296 (HW) setup register for ADV mode Note: D) Dual address mode S) Single address mode Function Setting Init. R/W D) Ch.x source address[15:0] S) Ch.x memory address[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D) Ch.x source address[31:16] S) Ch.x memory address[31:16] Remarks R/W R/W Notes: * This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1). * The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48264 HSDMA Ch.0 Low-Order Source Address Setup Register (pHS0_AD_SADR) 0x48266 HSDMA Ch.0 High-Order Source Address Setup Register for ADV mode 0x48274 HSDMA Ch.1 Low-Order Source Address Setup Register (pHS1_AD_SADR) 0x48276 HSDMA Ch.1 High-Order Source Address Setup Register for ADV mode 0x48284 HSDMA Ch.2 Low-Order Source Address Setup Register (pHS2_AD_SADR) 0x48286 HSDMA Ch.2 High-Order Source Address Setup Register for ADV mode 0x48294 HSDMA Ch.3 Low-Order Source Address Setup Register (pHS3_AD_SADR) 0x48296 HSDMA Ch.3 High-Order Source Address Setup Register for ADV mode D[15:0]/0x48264-0x48294 SxADRL[15:0]: Ch.x Low-Order Source Address[15:0] D[15:0]/0x48266-0x48296 SxADRH[15:0]: Ch.x High-Order Source Address[31:16] In dual-address mode, these bits are used to specify a 32-bit source address. In single-address mode, a 32-bit external memory address at the destination or source of transfer is specified. Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing or reading to and from these registers. The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x48226 + 0x10*x) or SxID (D4/0x48262 + 0x10*x)) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. III-4-38 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Notes: * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in the area for which the MMU is enabled to use. I * The following areas cannot be used for DMA transfer: Dual-address mode: Area 0 (A0RAM), Area 2 Single-address mode: Area 0 (A0RAM), Area 1 (peripherals), Area 2, Area 3 (A3RAM) * Single-address mode does not allow data transfer between memory devices. * Single-address mode does not support the external memory area that is configured for SDRAM. * Use SxADRL[15:0] (D[15:0]/0x48224 + 0x10*x) and SxADRH[11:0] (D[11:0]/0x48226 + 0x10*x) for specifying an address in standard mode. III HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-39 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x48268-0x4829A: HSDMA Ch.x Destination Address Setup Registers (pHSx_ADV_DADR) for ADV mode Register name Address Bit Name Function 0048268 HSDMA Ch.x | low-order 0048298 destination (HW) address setup register (pHSx_ADV_DADR) for ADV mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DxADRL15 DxADRL14 DxADRL13 DxADRL12 DxADRL11 DxADRL10 DxADRL9 DxADRL8 DxADRL7 DxADRL6 DxADRL5 DxADRL4 DxADRL3 DxADRL2 DxADRL1 DxADRL0 DxADRH15 DxADRH14 DxADRH13 DxADRH12 DxADRH11 DxADRH10 DxADRH9 DxADRH8 DxADRH7 DxADRH6 DxADRH5 DxADRH4 DxADRH3 DxADRH2 DxADRH1 DxADRH0 D) Ch.x destination address[15:0] S) Invalid Note: D) Dual address mode S) Single address mode HSDMA Ch.x high-order destination address setup register for ADV mode Note: D) Dual address mode S) Single address mode 004826A | 004829A (HW) Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D) Ch.x destination address[31:16] S) Invalid Remarks R/W R/W Notes: * This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1). * The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x48268 HSDMA Ch.0 Low-Order Destination Address Setup Register (pHS0_ADV_DADR) 0x4826A HSDMA Ch.0 High-Order Destination Address Setup Register for ADV mode 0x48278 HSDMA Ch.1 Low-Order Destination Address Setup Register (pHS1_ADV_DADR) 0x4827A HSDMA Ch.1 High-Order Destination Address Setup Register for ADV mode 0x48288 HSDMA Ch.2 Low-Order Destination Address Setup Register (pHS2_ADV_DADR) 0x4828A HSDMA Ch.2 High-Order Destination Address Setup Register for ADV mode 0x48298 HSDMA Ch.3 Low-Order Destination Address Setup Register (pHS3_ADV_DADR) 0x4829A HSDMA Ch.3 High-Order Destination Address Setup Register for ADV mode D[15:0]/0x48268-0x48298 DxADRL[15:0]: Ch.x Destination Address[15:0] D[15:0]/0x4826A-0x4829A DxADRH[15:0]: Ch.x Destination Address[31:16] In dual-address mode, these bits are used to specify a 32-bit destination address. Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10*x) = 0) before writing or reading to and from these registers. The address is incremented or decremented (as set by DxIN[1:0] (D[13:12]/0x4822A + 0x10*x) or DxID (D5/0x48262 + 0x10*x)) according to the transfer data size each time a DMA transfer in the corresponding channel is performed. III-4-40 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) Notes: * In single-address mode, these bits are not used. I * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in the area for which the MMU is enabled to use. * The following areas cannot be specified for destination addresses: Area 0 (A0RAM), Area 2 * Use DxADRL[15:0] (D[15:0]/0x48228 + 0x10*x) and DxADRH[11:0] (D[11:0]/0x4822A + 0x10*x) for specifying an address in standard mode. III HSDMA S1C33401 TECHNICAL MANUAL EPSON III-4-41 III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) 0x4829C: HSDMA STD/ADV Mode Select Register (pHS_CNTLMODE) Register name Address Bit Name Function reserved 004829C D15-1 - HSDMA (HW) STD/ADV mode D0 HSDMAADV Standard mode/advanced mode select register select (pHS_CNTLMODE) Setting Init. R/W - 1 Advanced mode D[15:1] Reserved D0 HSDMAADV: Standard/Advanced Mode Select Bit Select standard or advanced mode. 1 (R/W): Advanced mode 0 (R/W): Standard mode (default) 0 Standard mode - - 0 R/W Remarks 0 when being read. The HSDMA in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV HSDMA has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table III.4.9.5 shows differences between standard mode and advanced mode. Table III.4.9.5 Differences between Standard Mode and Advanced Mode Function Source/destination address bit width Word (32-bit) data transfer Address decrement function with initialization Standard mode Advanced mode 28 bits Unavailable Unavailable 32 bits Available Available To configure the HSDMA in advanced mode, set this bit to 1. The control registers (0x48262-0x4829A) for the extended functions are enabled to write after this setting. Notes: * Be sure to use the control registers for advanced mode when the HSDMA is set to advanced mode. * Standard or advanced mode currently set is applied to all the HSDMA channels. It cannot be selected for each channel individually. III-4-42 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) III.4.10 Precautions I * When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN (D0/0x4822C + 0x10*x) = 0). HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10*x) * After an initial reset, the cause-of-interrupt flag (FHDMx (Dx/0x40281)) becomes indeterminate. Always be sure to reset the flag to prevent interrupts or IDMA requests from being generated inadvertently. FHDMx: HSDMA Ch.x Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (Dx/0x40281) * To prevent an interrupt from being generated repeatedly for the same source, be sure to reset the cause-ofinterrupt flag before setting up the PSR again or executing the reti instruction. * HSDMA is given higher priority over IDMA (intelligent DMA) and the CPU. However, since HSDMA and IDMA share the same circuit, HSDMA cannot gain the bus ownership while an IDMA transfer is under way. Requests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the IDMA transfer is completed. A request for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are accepted after completion of the HSDMA transfer. * In dual-address mode, A0RAM (no-wait RAM built into area 0) cannot be specified as the source or destination for DMA transfer. A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) can be used for dual-address transfer. * In single-address mode, A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) cannot be used for DMA transfer. * Single-address mode does not allow data transfer between memory devices. An external logic circuit is required to perform single-address transfer between memory devices. * Single-address mode does not support the external memory area that is configured for SDRAM. * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if they are located in the area for which the MMU is enabled for use. * Be sure to disable the HSDMA before setting the chip in SLEEP mode (executing the slp instruction). HALT and HALT2 mode can be set even if the HSDMA is enabled. S1C33401 TECHNICAL MANUAL EPSON III-4-43 III HSDMA III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA) THIS PAGE IS BLANK. III-4-44 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5 Intelligent DMA (IDMA) III.5.1 Functional Outline of IDMA The C33 ADV Bus Block contains an intelligent DMA (IDMA), a function that allows control information to be programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by a cause of interrupt that occurs in some internal peripheral circuit. Although an additional overhead for loading and storing control information in RAM may be incurred, this intelligent DMA supports such functions as successive transfers, block transfers, and linking to another IDMA. IDMA is invoked by a cause of interrupt that occurs in some internal peripheral circuit or a software trigger, thereby performing a data transfer according to the control information in RAM. When the transfer is completed, IDMA can generate an interrupt or invoke another IDMA according to link settings. Intelligent DMA transfer IDMA DMA address bus BBCU Address bus Data bus DMA control information data bus Load/store DMA control information transfer request signal Load/store DMA control information transfer acknowledge signal (3) DMA data transfer request signal Memory, I/O (2) Memory, I/O (1) A3RAM or external RAM Destination Source Control information III Control information transfer Data transfer DMA data transfer acknowledge signal (Software trigger) (4) IDMA Hardware trigger ITC IDMA Ch. number #DMAREQx DMA request (1) The control information stored in the memory is loaded into the IDMA temporary register. (2) Transfer data is read from the source memory or I/O device. (3) Transfer data is written to the destination memory or I/O device. (4) The updated control information in the IDMA temporary register is written back to the memory. Figure III.5.1.1 Data and Control Information Flow in Intelligent DMA Transfer The features of IDMA are outlined below. * Controller * Number of channels * Control information Equivalent to the HSDMA dual-address transfer controller 128 channels Programmable in the RAM The information table can be stored in the internal memory except A0RAM (nowait RAM built into area 0) or in the external RAM. * Source External memory and internal memory except Area 0 (including peripheral area) * Destination External memory and internal memory except Area 0 (including peripheral area) * Transfer data size 8, 16, or 32 bits * Trigger 1. Software trigger (register control) 2. Hardware trigger (external trigger input, causes of interrupts) * Transfer mode 1. Single transfer (one unit of data is transferred by one trigger) 2. Successive transfer (specified number of data are transferred by one trigger) 3. Block transfer (data block of the specified size is transferred by one trigger) * Transfer address control The source and/or destination addresses can be incremented or decremented in units of the transfer data size upon completion of transfer. In successive or block transfers, the address can be reset to the initial value upon completion of transfer. * Programmable link function Any channel can be linked with another to perform data transfer by multiple channels sequentially. S1C33401 TECHNICAL MANUAL EPSON III-5-1 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) C33 ADV extended functions In the C33 ADV DMA controller, some IDMA functions have been extended from those of the C33 STD. Table III.5.1.1 shows differences between C33 STD IDMA and C33 ADV IDMA. Table III.5.1.1 Differences between C33 STD IDMA and C33 ADV IDMA C33 STD IDMA C33 ADV IDMA 28 bits 24 bits 16 bits 8 bits 16 bits, 8 bits Unavailable 3 words (96 bits) 28 bits (word alignment) 32 bits 32 bits 20 bits 12 bits 32 bits, 16 bits, 8 bits Available 4 words (128 bits) 32 bits (4-word alignment) Function Source/destination address bit width Transfer counter (for single/successive transfer) Transfer counter (for block transfer) Block size setup bit width Transfer data size Address decrement function with initialization Control information size per channel Control information base address Note that the item layout in the control information has been changed along with this functional extension. Furthermore, the control information is no longer placed in the area 0 built-in RAM (A0RAM). III-5-2 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.2 Programming Control Information The intelligent DMA operates according to the control information prepared in RAM. Note that the control information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0) cannot be used to store control information. The control information is 4 words (16 bytes) per channel in size, and must be located at continuous addresses beginning with the base address that is set in the software application as the starting address of channel 0. Consequently, an area of 512 words (2,048 bytes) in RAM is required in order for all of 128 channels to be used. The following explains how to set the base address and the contents of control information. Before using IDMA, make each the settings described below. III.5.2.1 Setting the Base Address Set the starting address of control information (starting address of channel 0) to DBASEL[15:0] (D[15:0]/0x48200) for 16 low-order bits and DBASEH[15:0] (D[15:0]/0x48202) for 16 high-order address bits. DBASEL[15:0]: IDMA Low-order Base Address Bits in the IDMA Base Address Register 0 (D[15:0]/0x48200) DBASEH[15:0]: IDMA High-order Base Address Bits in the IDMA Base Address Register 1 (D[15:0]/0x48202) When initially reset, the base address is set to 0x200003A0. Notes: * The control information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0) cannot be used to store control information. * The address you set in the IDMA base address register must always be 4-word units boundary address. * Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base address. Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN (D0/0x48205) = 1). When the register is read, the read data is indeterminate. IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205) III.5.2.2 Control Information Write the control information for the IDMA channels used to RAM. The addresses at which the control information of each channel is placed are determined by the base address and a channel number. Starting address of channel = base address + (channel number x 16 [bytes]) Note: The control information must be written only when the channel to be set does not start a DMA transfer. If a DMA transfer starts when the control information is being written to the RAM, proper transfer cannot be performed. Reading the control information can always be done. S1C33401 TECHNICAL MANUAL EPSON III-5-3 III IDMA III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) The contents of control information (4 words) in each channel are shown in the table below. Table III.5.2.2.1 IDMA Control Information Word Bit Name 1st D31 D30-24 D23-18 D17-16 LNKEN LNKCHN[6:0] reserved DATSIZ[1:0] D15 reserved D14-12 SRINC[2:0] Function IDMA link enable 1 = Enabled, 0 = Disabled IDMA link field - Data size control (Do not set to 11.) DATSIZ1 DATSIZ0 Setting contents 1 0 Word (32 bits) Half-word (16 bits) 0 1 Byte (8 bits) 0 0 - Source address control (Do not set to others.) SRINC2 SRINC1 SRINC0 Setting contents Address decrement with initialization 1 0 0 (address is reset in successive or block transfer mode) 0 1 1 Address increment without initialization 0 1 0 Address increment with initialization 0 0 1 Address decrement without initialization 0 0 0 Address fixed (address is not reset) (address is reset in successive or block transfer mode) (address is not reset) D11 D10-8 reserved DSINC[2:0] - Destination address control (Do not set to others.) DSINC2 DSINC1 DSINC0 Setting contents Address decrement with initialization 1 0 0 (address is reset in successive or block transfer mode) 0 1 1 Address increment without initialization 0 1 0 Address increment with initialization 0 0 1 Address decrement without initialization 0 0 0 Address fixed (address is not reset) (address is reset in successive or block transfer mode) (address is not reset) D7-6 D5-4 - Transfer mode (Do not set to 11.) DMOD1 DMOD0 Setting contents Block transfer mode 1 0 Successive transfer mode 0 1 Single transfer mode 0 0 D3-1 - reserved D0 End-of-transfer interrupt enable 1 = Enabled, 0 = Disabled DINTEN 2nd D31-12 TC[19:0] Transfer counter (block transfer mode) Transfer counter - 20 high-order bits (single or successive transfer mode) D11-0 BLKLEN[11:0] Block size (block transfer mode) Transfer counter - 12 low-order bits (single or successive transfer mode) 3rd D31-0 SRADR[31:0] Source address 4th D31-0 DSADR[31:0] Destination address reserved DMOD[1:0] LNKEN: IDMA link enable (D31/1st word) If this bit remains set (= 1), the IDMA channel that is set in the IDMA link field is invoked after the completion of a DMA transfer in this channel. DMA transfers in multiple channels can be performed successively by merely triggering the first channel to be executed. There is no limit to the number of channels linked. Set this link in order of the IDMA channels you want to be executed. If this bit is 0, IDMA is completed by merely executing a DMA transfer in this channel. LNKCHN[6:0]: IDMA link field (D[30:24]/1st word) If you want IDMA to be linked, set the channel numbers (0 to 127) to be executed next. The data in this field is valid only when LNKEN = 1. III-5-4 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) DATSIZ[1:0]: Data size control (D[17:16]/1st word) Set the unit size of data to be transferred. Table III.5.2.2.2 Transfer Data Size DATSIZ1 DATSIZ0 Transfer data size 1 1 0 0 1 0 1 0 Invalid Word (32 bits) Half-word (16 bits) Byte (8 bits) SRINC[2:0]: Source address control (D[14:12]/1st word) Set the source address control condition. * SRINC[2:0] = 000: Address fixed The source address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always read from the same address. * SRINC[2:0] = 011: Address increment without initialization (address is not reset) The source address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. * SRINC[2:0] = 001: Address decrement without initialization (address is not reset) The source address is decremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. The address that has been decremented during transfer does not return to the initial value. * SRINC[2:0] = 010: Address increment with initialization (address is reset in successive or block transfer mode) The source address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. In single transfer mode, the address that has been incremented during transfer does not return to the initial value. In successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the incremented address returns to the initial value when the block transfer is completed. * SRINC[2:0] = 100: Address decrement with initialization (address is reset in successive or block transfer mode) The source address is decremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. In single transfer mode, the address that has been decremented during transfer does not return to the initial value. In successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the decremented address returns to the initial value when the block transfer is completed. * SRINC[2:0] = Other than above: settings are prohibited Note: In single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. DSINC[2:0]: Destination address control (D[10:8]/1st word) Set the destination address control condition. * DSINC[2:0] = 000: Address fixed The destination address is not changed by a data transfer performed. Even when transferring multiple data, the transfer data is always written to the same address. * DSINC[2:0] = 011: Address increment without initialization (address is not reset) The destination address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. The address that has been incremented during transfer does not return to the initial value. S1C33401 TECHNICAL MANUAL EPSON III-5-5 III IDMA III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) * DSINC[2:0] = 001: Address decrement without initialization (address is not reset) The destination address is decremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. The address that has been decremented during transfer does not return to the initial value. * DSINC[2:0] = 010: Address increment with initialization (address is reset in successive or block transfer mode) The destination address is incremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. In single transfer mode, the address that has been incremented during transfer does not return to the initial value. In successive transfer modes, the incremented address returns to the initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the incremented address returns to the initial value when the block transfer is completed. * DSINC[2:0] = 100: Address decrement with initialization (address is reset in successive or block transfer mode) The destination address is decremented by an amount equal to the data size set by DATSIZ when one data transfer is completed. In single transfer mode, the address that has been decremented during transfer does not return to the initial value. In successive transfer modes, the decremented address returns to the initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the decremented address returns to the initial value when the block transfer is completed. * DSINC[2:0] = Other than above: settings are prohibited Note: In single transfer mode, the address does not return to the initial value even if a condition with address initialization is specified. DMOD[1:0]: Transfer mode (D[5:4]/1st word) Use these bits to set the desired transfer mode. The transfer modes are outlined below (to be detailed later): * DMOD[1:0] = 00: Single transfer mode In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. * DMOD[1:0] = 01: Successive transfer mode In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 each time data is transferred. * DMOD[1:0] = 10: Block transfer mode In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the transfer counter, an equal number of triggers are required. * DMOD[1:0] = 11: Settings are prohibited DINTEN: End-of-transfer interrupt enable (D0/1st word) If this bit is left set (= 1), when the transfer counter reaches 0, an interrupt request to the CPU is generated based on the cause-of-interrupt flag by which IDMA has been invoked. If this bit is 0, no interrupt request to the CPU is generated even when the transfer counter has reached 0. TC[19:0]: Transfer counter (D[31:12]/2nd word) In block transfer mode, a transfer count can be specified using up to 20 bits. Set this value here. In single transfer and successive transfer modes, a transfer count can be specified using up to 32 bits. Set a 20-bit high-order value here. III-5-6 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) BLKLEN[11:0]: Block size/transfer counter (D[11:0]/2nd word) In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In single transfer and successive transfer modes, set an 12-bit low-order value for the transfer count here. Note: The transfer count and block size thus set is decremented according to the transfers performed. If the transfer count is set to 0, it is decremented to all Fs by the first transfer performed. This means that you have set the maximum value that is determined by the number of bits available. SRADR[31:0]: Source address (D[31:0]/3rd word) Use these bits to set the starting address at the source of transfer. The content set here is updated according to the setting of SRINC. DSADR[31:0]: Destination address (D[31:0]/4th word) Use these bits to set the starting address at the destination of transfer. The content set here is updated according to the setting of DSINC. Notes: * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in the area for which the MMU is enabled to use. * Area 0 (A0RAM) and Area 2 cannot be used for IDMA transfer and storing control information. * Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this information, make sure that no DMA transfer is generated in the channel whose information you are going to rewrite. III IDMA S1C33401 TECHNICAL MANUAL EPSON III-5-7 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.3 IDMA Invocation The triggers by which IDMA is invoked have the following three causes: 1. Cause of interrupt in internal peripheral circuits (hardware trigger) 2. Trigger in the software application 3. Link setting Enabling/disabling DMA transfer The IDMA controller is enabled by writing 1 to the IDMA enable bit IDMAEN (D0/0x48205), and is ready to accept the triggers described above. However, before enabling a DMA transfer, be sure to set the base address and the control information for the channel to be invoked correctly. If IDMAEN (D0/0x48205) is set to 0, no IDMA invocation request is accepted. IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205) IDMA invocation by a cause of interrupt in internal peripheral circuits Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by a cause of interrupt in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are predetermined. The relationship between the causes of interrupt that have this function and the IDMA channels is shown in Table III.5.3.1. Table III.5.3.1 Interrupt Causes Used to Invoke IDMA Peripheral circuit I/O Ports High-speed DMA 16-bit timers 0-5 8-bit timers 0-3 Serial interface Ch.0-Ch.1 A/D converter I/O Ports 8-bit timers 4-5 Serial interface Ch.2-Ch.3 III-5-8 Cause of interrupt Port input 0 Port input 1 Port input 2 Port input 3 Ch.0, end of transfer Ch.1, end of transfer Timer 0 comparison B Timer 0 comparison A Timer 1 comparison B Timer 1 comparison A Timer 2 comparison B Timer 2 comparison A Timer 3 comparison B Timer 3 comparison A Timer 4 comparison B Timer 4 comparison A Timer 5 comparison B Timer 5 comparison A Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Ch.0 receive buffer full Ch.0 transmit buffer empty Ch.1 receive buffer full Ch.1 transmit buffer empty End of A/D conversion Port input 4 Port input 5 Port input 6 Port input 7 Timer 4 underflow Timer 5 underflow Ch.2 receive buffer full Ch.2 transmit buffer empty Ch.3 receive buffer full Ch.3 transmit buffer empty IDMA Ch. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 EPSON IDMA request bit IDMA enable bit RP0 (D0/0x40290) RP1 (D1/0x40290) RP2 (D2/0x40290) RP3 (D3/0x40290) RHDM0 (D4/0x40290) RHDM1 (D5/0x40290) R16TU0 (D6/0x40290) R16TC0 (D7/0x40290) R16TU1 (D0/0x40291) R16TC1 (D1/0x40291) R16TU2 (D2/0x40291) R16TC2 (D3/0x40291) R16TU3 (D4/0x40291) R16TC3 (D5/0x40291) R16TU4 (D6/0x40291) R16TC4 (D7/0x40291) R16TU5 (D0/0x40292) R16TC5 (D1/0x40292) R8TU0 (D2/0x40292) R8TU1 (D3/0x40292) R8TU2 (D4/0x40292) R8TU3 (D5/0x40292) RSRX0 (D6/0x40292) RSTX0 (D7/0x40292) RSRX1 (D0/0x40293) RSTX1 (D1/0x40293) RADE (D2/0x40293) RP4 (D4/0x40293) RP5 (D5/0x40293) RP6 (D6/0x40293) RP7 (D7/0x40293) R8TU4 (D0/0x4029B) R8TU5 (D1/0x4029B) RSRX2 (D2/0x4029B) RSTX2 (D3/0x4029B) RSRX3 (D4/0x4029B) RSTX3 (D5/0x4029B) DEP0 (D0/0x40294) DEP1 (D1/0x40294) DEP2 (D2/0x40294) DEP3 (D3/0x40294) DEHDM0 (D4/0x40294) DEHDM1 (D5/0x40294) DE16TU0 (D6/0x40294) DE16TC0 (D7/0x40294) DE16TU1 (D0/0x40295) DE16TC1 (D1/0x40295) DE16TU2 (D2/0x40295) DE16TC2 (D3/0x40295) DE16TU3 (D4/0x40295) DE16TC3 (D5/0x40295) DE16TU4 (D6/0x40295) DE16TC4 (D7/0x40295) DE16TU5 (D0/0x40296) DE16TC5 (D1/0x40296) DE8TU0 (D2/0x40296) DE8TU1 (D3/0x40296) DE8TU2 (D4/0x40296) DE8TU3 (D5/0x40296) DESRX0 (D6/0x40296) DESTX0 (D7/0x40296) DESRX1 (D0/0x40297) DESTX1 (D1/0x40297) DEADE (D2/0x40297) DEP4 (D4/0x40297) DEP5 (D5/0x40297) DEP6 (D6/0x40297) DEP7 (D7/0x40297) DE8TU4 (D0/0x4029C) DE8TU5 (D1/0x4029C) DESRX2 (D2/0x4029C) DESTX2 (D3/0x4029C) DESRX3 (D4/0x4029C) DESTX3 (D5/0x4029C) S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) Cause of interrupt Peripheral circuit I/O Ports 16-bit timers 6-9 Port input 8 Port input 9 Port input 10 Port input 11 Port input 12 Port input 13 Port input 14 Port input 15 Timer 6 comparison B Timer 6 comparison A Timer 7 comparison B Timer 7 comparison A Timer 8 comparison B Timer 8 comparison A Timer 9 comparison B Timer 9 comparison A IDMA Ch. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 IDMA request bit RP8 (D0/0x402AC) RP9 (D1/0x402AC) RP10 (D2/0x402AC) RP11 (D3/0x402AC) RP12 (D4/0x402AC) RP13 (D5/0x402AC) RP14 (D6/0x402AC) RP15 (D7/0x402AC) R16TU6 (D0/0x402AD) R16TC6 (D1/0x402AD) R16TU7 (D2/0x402AD) R16TC7 (D3/0x402AD) R16TU8 (D4/0x402AD) R16TC8 (D5/0x402AD) R16TU9 (D6/0x402AD) R16TC9 (D7/0x402AD) IDMA enable bit DEP8 (D0/0x402AE) DEP9 (D1/0x402AE) DEP10 (D2/0x402AE) DEP11 (D3/0x402AE) DEP12 (D4/0x402AE) DEP13 (D5/0x402AE) DEP14 (D6/0x402AE) DEP15 (D7/0x402AE) DE16TU6 (D0/0x402AF) DE16TC6 (D1/0x402AF) DE16TU7 (D2/0x402AF) DE16TC7 (D3/0x402AF) DE16TU8 (D4/0x402AF) DE16TC8 (D5/0x402AF) DE16TU9 (D6/0x402AF) DE16TC9 (D7/0x402AF) These causes of interrupt are used in common for interrupt requests and IDMA invocation requests. To invoke IDMA upon the occurrence of a cause of interrupt, set the corresponding bits of the IDMA request and IDMA enable registers shown in the table by writing 1. Then when a cause of interrupt occurs, an interrupt request to the CPU is kept pending and the corresponding IDMA channel is invoked. The cause-of-interrupt flag that has been set to 1 remains set until the DMA transfer invoked by it is completed. If the following two conditions are met when one DMA transfer is completed, an interrupt request is generated without resetting the cause-of-interrupt flag. * The transfer counter has reached 0. * DINTEN in control information is set to 1 (interrupt enabled). In this case, the IDMA request register is cleared to 0. Therefore, if IDMA needs to be invoked when a cause of interrupt occurs next time, this register must be set up again. To prevent unwanted IDMA requests from being generated, this setting must be performed before enabling interrupts and after resetting the cause-of-interrupt flag. The IDMA enable bit is not cleared and remains set to 1. If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to 1. When DINTEN in control information has been set to 0, the cause-of-interrupt flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. If the IDMA request register bit is left reset to 0, the relevant cause of interrupt generates an interrupt request and not an IDMA request. The control registers (interrupt enable register and interrupt priority register) corresponding to the cause of interrupt do not affect IDMA invocation. IDMA can be invoked even if the interrupt enable bit in ITC is set to 0 (interrupt disabled). However, these register must be set to enable the interrupt when generating the interrupt after completing the DMA transfer. S1C33401 TECHNICAL MANUAL EPSON III-5-9 III IDMA III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) IDMA invocation by a trigger in the software application All IDMA channels for which control information is set, including those corresponding to causes of interrupt described above, can be invoked by a trigger in the software application. When the IDMA channel number to be invoked (0 to 127) is written to DCHN[6:0] (D[6:0]/0x48204) and DSTART (D7/0x48204) is set to 1 after setting IDMAEN (D0/0x48205) to 1, the specified IDMA channel starts a DMA transfer. DCHN[6:0]: IDMA Channel Number Set-up Bits in the IDMA Start Register (D[6:0]/0x48204) DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204) DSTART remains set (= 1) during a DMA transfer and is reset to 0 in hardware when one DMA transfer operation is completed. Do not modify these bits during a DMA transfer. If DINTEN is set to 1 (interrupt enabled), an interrupt factor for the completion of IDMA transfer is generated when one DMA transfer is completed. IDMA invocation by link setting If LNKEN in the control information is set to 1 (link enabled), the IDMA channel that is set in the IDMA link field "LNKCHN" is invoked successively after a DMA transfer in the link-enabled channel is completed. The interrupt request by the first channel is generated after transfers in all linked channels are completed if the interrupt conditions are met. To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to 1. IDMA invocation request during a DMA transfer An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared, new requests will be accepted when the DMA transfer under execution is completed. An IDMA invocation request to the same channel cannot be accepted while the channel is executing a DMA transfer because the same cause of interrupt is used. Therefore, an interval longer than the DMA transfer period is required when invoking the same channel. IDMA invocation request when DMA transfer is disabled An IDMA invocation request generated when IDMAEN (D0/0x48205) is 0 (DMA transfer disabled) is kept pending until IDMAEN (D0/0x48205) is set to 1. Since an invocation request is not cleared, it is accepted when DMA transfer is enabled. Simultaneous generation of a software trigger and a hardware trigger When a software trigger and the hardware trigger for the same channel are generated simultaneously, the software trigger starts IDMA transfer. The IDMA transfer by the hardware trigger is executed after the DMA transfer by the software trigger is completed. III-5-10 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.4 Operation of IDMA IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, a cause of interrupt is processed differently depending on the type of trigger. IDMA supports only dual-address transfers. It does not support single-address transfers. The following describes the operation of IDMA in each transfer mode and how an interrupt factor is processed for each type of trigger. III.5.4.1 Single Transfer Mode The channels for which DMOD in control information is set to 00 operate in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZ. If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in single transfer mode is shown by the flow chart in Figure III.5.4.1.1. START Calculates address of control information Loads channel control information Transfers one unit of data A Base address + (Channel number x 16) Bn (4 words) :n = 1-4 C (Data read from source of transfer) D (Data write to destination of transfer) III Transfer counter - 1 E Saves channel control information Fn (4 words) Transfer counter = 0 :n = 1-4 IDMA N Y IDMA interrupt processing (if interrupt is enabled) END Trigger A B1 B2 B3 B4 C D E F1 F2 F3 F4 Figure III.5.4.1.1 Operation Flow in Single Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and the transfer counter is decremented. (6) The modified control information is written to RAM. (7) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit ________________________________________________________________________________________ Transfer counter 0: Reset (0) Not changed (1) Not changed (1) Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1) Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0) S1C33401 TECHNICAL MANUAL EPSON III-5-11 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.4.2 Successive Transfer Mode The channels for which DMOD in control information is set to 01 operate in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer counter is decremented to 0 by one transfer executed. The operation of IDMA in successive transfer mode is shown by the flow chart in Figure III.5.4.2.1. START Calculates address of control information Loads channel control information Transfers one unit of data Transfer counter - 1 A Base address + (Channel number x 16) Bn (4 words) :n = 1-4 C (Data read from source of transfer) D (Data write to destination of transfer) E Transfer counter = 0 N Y Restores initial values to address Saves channel control information F : according to SRINC/DSINC settings Gn (4 words) :n = 1-4 IDMA interrupt processing (if interrupt is enabled) END Trigger A B1 B2 B3 B4 C1 D1 E1 Cn Dn En F G1 G2 G3 G4 Figure III.5.4.2.1 Operation Flow in Successive Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and the transfer counter is decremented. (6) Steps (3) to (5) are repeated until the transfer counter reaches 0. (7) If SRINC and/or DSINC are 010 or 100, the address is recycled to the initial value. (8) The modified control information is written to RAM. (9) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit ________________________________________________________________________________________ Transfer counter 0: Reset (0) Not changed (1) Not changed (1) Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1) Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0) III-5-12 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.4.3 Block Transfer Mode The channels for which DMOD in control information is set to 10 operate in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers are required. The operation of IDMA in block transfer mode is shown by the flow chart in Figure III.5.4.3.1. START Calculates address of control information Loads channel control information Transfers one unit of data Block size - 1 A Base address + (Channel number x 16) Bn (4 words) :n = 1-4 C (Data read from source of transfer) D (Data write to destination of transfer) E Block size = 0 N 1-block transfer Y F Transfer counter - 1 G Saves channel control information Hn (4 words) Transfer counter = 0 III : according to SRINC/DSINC settings Restores initial values to block size and address IDMA :n = 1-4 N Y IDMA interrupt processing (if interrupt is enabled) END F Trigger A B1 B2 B3 B4 C1 D1 E1 G Cn Dn En H1 H2 H3 H4 Figure III.5.4.3.1 Operation Flow in Block Transfer Mode (1) When a trigger is accepted, the address for control information is calculated from the base address and channel number. (2) Control information is read from the calculated address into the internal temporary register. (3) Data of the size set in the control information is read from the source address. (4) The read data is written to the destination address. (5) The address is incremented or decremented and BLKLEN is decremented. (6) Steps (3) to (5) are repeated until BLKLEN reaches 0. (7) If SRINC and/or DSINC are 010 or 100, the address is recycled to the initial value. (8) The transfer counter is decremented. (9) The modified control information is written to RAM. (10) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA. Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit ________________________________________________________________________________________ Transfer counter 0: Reset (0) Not changed (1) Not changed (1) Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1) Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0) S1C33401 TECHNICAL MANUAL EPSON III-5-13 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.4.4 Cause-of-Interrupt Processing by Trigger Type When invoked by a cause of interrupt The cause-of-interrupt flag by which IDMA has been invoked remains set even during a DMA transfer. If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is completed, the cause of interrupt that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to 0. The IDMA enable bit is not cleared and remains set to 1. If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to 1. When DINTEN has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. Trigger by cause of interrupt Data transfer Transfer counter 0 1 0 1 2 DINTEN IDMA request bit IDMA enable bit Cause-of-interrupt flag Interrupt request Figure III.5.4.4.1 Operation when Invoked by Cause of Interrupt When IDMA is invoked by a cause of interrupt, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) will not be set. FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281) When invoked by a software trigger If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is completed, FIDMA (D4/0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = 0 (interrupt disabled), FIDMA (D4/0x40281) is not set. If the cause-of-interrupt flag for the same channel is set during a software-triggered transfer, the IDMA invocation request by that cause-of-interrupt flag is kept pending. However, the cause-of-interrupt flag will be reset when the current execution is completed, so there will be no DMA transfer by the cause-of-interrupt flag. Software trigger Data transfer Transfer counter 2 1 0 1 0 DINTEN FIDMA (D4/0x40281) Interrupt request Figure III.5.4.4.2 Operation when Invoked by Software Trigger III-5-14 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.5 Linking If the IDMA channel number to be executed next is set in the IDMA link field LNKCHN of control information and LNKEN is set to 1 (link enabled), DMA successive transfer in that IDMA channel can be performed. An example of link setting is shown in Figure III.5.5.1. Trigger After transfer Ch.3 Ch.5 Ch.7 LNKEN = 1 LNKCHN = 5 DMOD = 01 DINTEN = 1 TC = 1024 LNKEN = 1 LNKCHN = 7 DMOD = 00 DINTEN = 1 TC = 8 LNKEN = 0 LNKCHN = 9 DMOD = 10 DINTEN = 1 TC = 1 TC = 0 TC = 7 TC = 0 Figure III.5.5.1 Example of Link Setting For the above example, IDMA operates as described below. For trigger in hardware (1) The IDMA channel 3 is invoked by a cause of interrupt and the DMA transfer that is set is performed. Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and DINTEN is set to 1, the cause-of-interrupt flag by which the channel 3 has been invoked remains set. (2) Next, a DMA transfer is performed via the linked IDMA channel 5. Channel 5 is set for single transfer mode and the transfer counter in this transfer is decremented by 1. III (3) Finally, a DMA transfer in IDMA channel 7 is performed. Although the channel 7 is set for block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. (4) Since the cause-of-interrupt flag that has invoked IDMA channel 3 in (1) remains set, an interrupt is generated when the IDMA transfer (channel 7) in (3) is completed. The transfer result does not affect the cause-ofinterrupt flag of channel 3. To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must be set to 1. For trigger in the software application (1) The IDMA channel 3 is invoked by a software trigger DSTART (D7/0x48204) and the DMA transfer that is set is performed. Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and DINTEN is set to 1, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) is set when the transfer is completed. DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204) FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281) (2) Next, a DMA transfer is performed in the linked IDMA channel 5. The channel 5 is set for the single transfer mode and the transfer counter in this transfer is decremented by 1. (3) Finally, a DMA transfer in IDMA channel 7 is performed. Although channel 7 is set for the block transfer mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers to be performed is 1. The completion of this transfer also causes FIDMA (D4/0x40281) to be set to 1. However, FIDMA (D4/0x40281) has already been set when the transfer is completed in (1) above. (4) Since FIDMA (D4/0x40281) is set, an interrupt request is generated here. In cases when IDMA has been invoked by a trigger in the software application, if the transfer counter in any one of the linked channels is decremented to 0 and DINTEN for that channel is set to 1, an interrupt request for the completion of IDMA transfer is generated when a transfer operation in each of the linked channels is completed. The channel in which an interrupt request has been generated can be verified by reading out the transfer counter. Transfer operations in each channel are performed as described earlier. S1C33401 TECHNICAL MANUAL EPSON III-5-15 IDMA III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.6 Interrupt Function of Intelligent DMA IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA transfer itself. Interrupt when invoked by a cause of interrupt If the corresponding bits of the IDMA request and interrupt enable registers are left set (= 1), assertion of an interrupt request is kept pending even when the enabled cause of interrupt has occurred and the IDMA channel assigned to that cause of interrupt is invoked. If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is completed, the cause of interrupt that has invoked IDMA is not reset and an interrupt request is generated. At the same time, the IDMA request register is cleared to 0. The IDMA enable bit is not cleared and remains set to 1. If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain set to 1. When DINTEN has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the IDMA enable bit is cleared. When IDMA is invoked by a cause of interrupt, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) will not be set. For details about the causes of interrupt that can be used to invoke IDMA and the interrupt control registers, refer to the descriptions of the peripheral circuits in this manual. Note that the priority levels of causes of interrupt are set by the interrupt priority register. Refer to Section IV.2, "Interrupt Controller (ITC)." However, when compared between IDMA and interrupt requests, IDMA is given higher priority over the other. Consequently, even when a cause of interrupt occurring during an IDMA transfer has higher priority than the cause of interrupt that invoked the IDMA transfer, an interrupt request for it or a new IDMA invocation request is not accepted until after the current IDMA transfer is completed. Software-triggered interrupts If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer operation is completed, FIDMA (D4/0x40281) is set, thereby generating an interrupt request. If the transfer counter is not 0 or DINTEN = 0 (interrupt disabled), FIDMA (D4/0x40281) is not set. IDMA interrupt control register in the interrupt controller The following control bits are used to control an interrupt for the completion of IDMA transfer: FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281) EIDMA: IDMA Interrupt Enable Bit in the DMA Interrupt Enable Register (D4/0x40271) PDM[2:0]: IDMA Interrupt Level Bits in the IDMA Interrupt Priority Register (D[2:0]/0x40265) When a DMA transfer in the IDMA channel invoked by a trigger in the software application or subsequent link is completed and the transfer counter is decremented to 0, the cause-of-interrupt flag for the completion of IDMA transfer is set to 1. However, this requires as a precondition that interrupt be enabled (DINTEN = 1) in the control information for that channel. If the interrupt enable register bit remains set (= 1) when the flag is set, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit cleared (= 0). Use the interrupt priority register to set interrupt priority levels (0 to 7). An interrupt request to the CPU is accepted on condition that no other interrupt request of higher priority is generated. Furthermore, it is only when the PSR's IE bit = 1 (interrupt enabled) and the set value of IL is smaller than the IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA interrupt request. For details about these interrupt control registers, and for information on device operation when an interrupt occurs, refer to Section IV.2, "Interrupt Controller (ITC)." Trap vector The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x20000068. The trap table base address can be changed using the TTBR registers. III-5-16 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.7 Details of Control Registers Table III.5.7.1 List of IDMA Registers Address 0x00048200 0x00048202 0x00048204 0x00048205 Register name IDMA Base Address Register 0 (pIDMABASE) IDMA Base Address Register 1 IDMA Start Register (pIDMA_START) IDMA Enable Register (pIDMA_EN) Size 16 16 8 8 Function Sets 16 low-order bits of IDMA base address. Sets 16 high-order bits of IDMA base address. Invokes an IDMA channel. Enables IDMA. The following describes each IDMA control register. The IDMA control registers are mapped in the 16-bit device area from 0x48200 to 0x48205, and can be accessed in units of half-words or bytes. Note: When setting the IDMA control registers, be sure to write a 0, and not a 1, for all "reserved bits." III IDMA S1C33401 TECHNICAL MANUAL EPSON III-5-17 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) 0x48200: IDMA Base Address Register 0 (pIDMABASE) 0x48202: IDMA Base Address Register 1 Register name Address Bit Name 0048200 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 DBASEH15 DBASEH14 DBASEH13 DBASEH12 DBASEH11 DBASEH10 DBASEH9 DBASEH8 DBASEH7 DBASEH6 DBASEH5 DBASEH4 DBASEH3 DBASEH2 DBASEH1 DBASEH0 IDMA base address register 0 (pIDMABASE) IDMA base address register 1 0048202 (HW) Function Setting IDMA base address low-order 16 bits (Initial value: 0x200003A0) IDMA base address high-order 16 bits (Initial value: 0x200003A0) Init. R/W 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W Fix at 0. R/W Specify the starting address of the control information to be placed in RAM. At initial reset, the base address is set to 0x200003A0. D[15:0]/0x48200 DBASEL[15:0]: IDMA Low-order Base Address Bits Use DBASEL to set the 16 low-order bits of the base address. D[15:0]/0x48202 DBASEH[15:0]: IDMA High-order Base Address Bits Use DBASEH to set the 16 high-order bits of the base address. In the C33 ADV IDMA, the DBASEH[15:12] bits have been added to extend the base address into 32 bits. Notes: * The control information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0) cannot be used to store control information. * The address you set in the IDMA base address registers must always be 4-word units boundary address. * These registers cannot be read or written in bytes. The registers must be accessed in words for read/write operations to address 0x48200, or in half-words for read/write operations to addresses 0x48200 and 0x48202. Write operations in half-words must be performed in order of 0x48200 and 0x48202. Read operations in half-words may be performed in any order. * Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base address. Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN (D0/0x48205) = 1). When the register is read, the read data is indeterminate. III-5-18 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) 0x48204: IDMA Start Register (pIDMA_START) Register name Address Bit Name 0048204 (B) D7 D6 D5 D4 D3 D2 D1 D0 DSTART DCHN6 DCHN5 DCHN4 DCHN3 DCHN2 DCHN1 DCHN0 IDMA start register (pIDMA_START) D7 Function IDMA start IDMA channel number Setting 1 IDMA start 0 Stop 0 to 127 Init. R/W 0 0 Remarks R/W R/W DSTART: IDMA Start Control Bit Use this bit for software trigger and for monitoring the operation of IDMA. 1 (W): Start IDMA 0 (W): Has no effect 1 (R): Operating (only when invoked by software trigger) 0 (R): Idle (default) When DSTART is set to 1, it functions as a software trigger, invoking the IDMA channel that is set in the DCHN register. D[6:0] DCHN[6:0]: IDMA Channel Number Setting Bits Set the channel numbers (0 to 127) to be invoked by software trigger. (Default: 0) Note: Do not start an IDMA transfer and change the IDMA channel number simultaneously. When setting DCHN[6:0], write 0 to DSTART. III IDMA S1C33401 TECHNICAL MANUAL EPSON III-5-19 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) 0x48205: IDMA Enable Register (pIDMA_EN) Register name Address IDMA enable register (pIDMA_EN) 0048205 (B) Name Bit D7-1 - D0 IDMAEN Function IDMA enable (for software trigger) 1 Enabled D[7:1] Reserved D0 IDMAEN: IDMA Enable Bit Enable a IDMA transfer. 1 (R/W): Enable 0 (R/W): Disable (default) Setting Init. R/W - reserved 0 Disabled - - 0 R/W Remarks 0 when being read. IDMA transfer is enabled by writing 1 to this bit and is disabled by writing 0. III-5-20 EPSON S1C33401 TECHNICAL MANUAL III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) III.5.8 Precautions * The control information must be placed in A3RAM (area 3) or an external RAM. Area 0 (A0RAM) and Area 2 cannot be used for IDMA transfer and storing control information. * The address you set in the IDMA base address registers must always be 4-word units boundary address. * Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base address. Writing to the IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN (D0/0x48205) = 1). When the register is read, the read data is indeterminate. IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205) * Do not start an IDMA transfer and change the IDMA channel number simultaneously. When setting DCHN[6:0] (D[6:0]/0x48204), write 0 to DSTART (D7/0x48204). DCHN[6:0]: IDMA Channel Number Set-up Bits in the IDMA Start Register (D[6:0]/0x48204) DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204) * The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in the area for which the MMU is enabled to use. * Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this information, make sure that no DMA transfer is generated in the channel whose information you are going to rewrite. * Since the C33 ADV core performs look-ahead operations, do not specify another channel immediately after a software trigger has invoked a channel. III * Be sure to disable the IDMA before setting the chip in SLEEP mode (executing the slp instruction). HALT and HALT2 mode can be set even if the IDMA is enabled. IDMA S1C33401 TECHNICAL MANUAL EPSON III-5-21 III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA) THIS PAGE IS BLANK. III-5-22 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 Technical Manual IV C33 ADV BASIC PERIPHERAL BLOCK IV IV C33 ADV BASIC PERIPHERAL BLOCK: PREFACE IV.1 Preface I The S1C33 microcomputers using the C33 ADV Core Macro incorporate a basic peripheral circuit block in which the basic peripheral circuits are integrated. Chapter IV describes each peripheral circuit included in this basic peripheral circuit block. Since the descriptions that follow are for standard specifications common to S1C33 microcomputers, some functions may not be available or additional functions may be included, depending on the specific C33 model used. For details, see Section I.8, "Changes from Core/Basic Peripheral Functions." C33 ADV CPU HBCU High-speed bus CMU Bridge Standard Peripheral Block OSC3 oscillator, PLL, SSCG Prescaler (PSC) Interrupt controller (ITC) A/D converter (ADC) 16-bit timers (T16) Watchdog timer (WDT) Serial interface (SIO) IV 8-bit timers (T8) Card interface (CARD) Preface I/O ports (PORT) Figure IV.1.1 Configuration of the C33 ADV Basic Peripheral Circuit Block S1C33401 TECHNICAL MANUAL EPSON IV-1-1 IV C33 ADV BASIC PERIPHERAL BLOCK: PREFACE The following circuit modules are built into the basic peripheral circuit block: Interrupt controller (ITC) Controls all interrupts except NMI. OSC3 oscillator circuit, PLL and SSCG These circuits generate the system source clock. Prescaler (PSC) This programmable frequency divider generates operating clocks for the 8-bit and 16-bit timers, and A/D converter. 8-bit timer (T8) Standard specifications incorporate six-channel, 8-bit timers that can be used to generate clocks for internal/ external devices or periodic interrupts at designated intervals. 16-bit timer (T16) Standard specifications incorporate 10-channel, 16-bit timers that can be used as event counters or to generate clocks for external output, periodic interrupts at designated intervals, or PWM waveforms compliant with DA16 mode. Watchdog timer (WDT) This 30-bit watchdog timer generates nonmaskable interrupts (NMI) when not reset for a set period or more. Serial interface with FIFO (SIO) This serial interface with FIFO enables the selection of asynchronous or clock-synchronized communication mode, as well as an IrDA interface. Card interface (CARD) Generates control signals for NAND flash (SmartMedia), CompactFlash, and PC Card interfaces. Input/output ports (PORT) Standard specifications support 63 input/output ports. When not being used for the input/output of other peripheral circuits, these port pins can be used as general-purpose input/output ports. A/D converter (ADC) This 10-bit A/D converter can accommodate eight analog inputs. IV-1-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2 Interrupt Controller (ITC) I The C33 ADV macro contains an interrupt controller, making it possible to control all interrupts generated by the internal peripheral circuits. This section explains the functions of this interrupt controller centering around the method for controlling maskable interrupts. For details about the various causes and conditions under which interrupts are generated, refer to the description of each peripheral circuit in this manual. IV.2.1 Outline of Interrupt Functions IV.2.1.1 Maskable Interrupts The ITC can handle 64 kinds of maskable interrupts. Table IV.2.1.1.1 shows the trap table in the C33 ADV macro. Table IV.2.1.1.1 Trap Table Vector number (Hex address) Exception/interrupt name (peripheral circuit) 0(Base) 1-3 4(Base+10) 5 6(Base+18) 0x0 or 0x60000 7(Base+1C) 8-11 12(Base+30) 13(Base+34) 14(Base+38) 15(Base+3C) 16(Base+40) 17(Base+44) 18(Base+48) 19(Base+4C) 20(Base+50) 21(Base+54) 22(Base+58) 23(Base+5C) 24(Base+60) 25(Base+64) 26(Base+68) 27-29 30(Base+78) 31(Base+7C) 32-33 34(Base+88) 35(Base+8C) 36-37 38(Base+98) 39(Base+9C) 40-41 42(Base+A8) 43(Base+AC) 44-45 46(Base+B8) 47(Base+BC) 48-49 50(Base+C8) 51(Base+CC) 52(Base+D0) 53(Base+D4) 54(Base+D8) 55(Base+DC) Reset reserved Division by zero reserved Address misaligned exception Debugging exception NMI reserved Software exception 0 Software exception 1 Software exception 2 Software exception 3 Port input interrupt 0 Port input interrupt 1 Port input interrupt 2 Port input interrupt 3 Key input interrupt 0 Key input interrupt 1 High-speed DMA Ch.0 High-speed DMA Ch.1 High-speed DMA Ch.2 High-speed DMA Ch.3 Intelligent DMA reserved 16-bit timer 0 reserved 16-bit timer 1 reserved 16-bit timer 2 reserved 16-bit timer 3 reserved 16-bit timer 4 reserved 16-bit timer 5 8-bit timers 0-3 S1C33401 TECHNICAL MANUAL Cause of exception/interrupt Low input to the reset pin - Division instruction - Memory access instruction brk instruction, etc. Low input to the #NMI pin - int instruction int instruction int instruction int instruction Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Rising or falling edge Rising or falling edge High-speed DMA Ch.0, end of transfer High-speed DMA Ch.1, end of transfer High-speed DMA Ch.2, end of transfer High-speed DMA Ch.3, end of transfer Intelligent DMA, end of transfer - Timer 0 compare-match B Timer 0 compare-match A - Timer 1 compare-match B Timer 1 compare-match A - Timer 2 compare-match B Timer 2 compare-match A - Timer 3 compare-match B Timer 3 compare-match A - Timer 4 compare-match B Timer 4 compare-match A - Timer 5 compare-match B Timer 5 compare-match A Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow EPSON IDMA Priority Ch. - - - - - - - - - - - - 1 2 3 4 - - 5 6 - - - - 7 8 - 9 10 - 11 12 - 13 14 - 15 16 - 17 18 19 20 21 22 High IV ITC Low IV-2-1 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Vector number (Hex address) 56(Base+E0) 57(Base+E4) 58(Base+E8) 59 60(Base+F0) 61(Base+F4) 62(Base+F8) 63(Base+FC) 64(Base+100) 65(Base+104) Exception/interrupt name (peripheral circuit) Serial interface Ch.0 reserved Serial interface Ch.1 A/D converter RTC 66-67 reserved 68(Base+110) Port input interrupt 4 69(Base+114) Port input interrupt 5 70(Base+118) Port input interrupt 6 71(Base+11C) Port input interrupt 7 72(Base+120) 8-bit timers 4-5 73(Base+124) 74-75 reserved 76(Base+130) Serial interface Ch.2 77(Base+134) 78(Base+138) 79 reserved 80(Base+140) Serial interface Ch.3 81(Base+144) 82(Base+148) 83 reserved 84(Base+150) Port input interrupt 8 85(Base+154) Port input interrupt 9 86(Base+158) Port input interrupt 10 87(Base+15C) Port input interrupt 11 88(Base+160) Port input interrupt 12 89(Base+164) Port input interrupt 13 90(Base+168) Port input interrupt 14 91(Base+16C) Port input interrupt 15 92-93 reserved 94(Base+178) 16-bit timer 6 95(Base+17C) 96-97 reserved 98(Base+188) 16-bit timer 7 99(Base+18C) 100-101 reserved 102(Base+198) 16-bit timer 8 103(Base+19C) 104-105 reserved 106(Base+1A8) 16-bit timer 9 107(Base+1AC) Cause of exception/interrupt Receive error Receive buffer full Transmit buffer empty - Receive error Receive buffer full Transmit buffer empty Result out of range (upper-limit and lower-limit) End of conversion 1/64 second, 1 second, 1 minuet, or 1 hour count up - Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Timer 4 underflow Timer 5 underflow - Receive error Receive buffer full Transmit buffer empty - Receive error Receive buffer full Transmit buffer empty - Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) Edge (rising or falling) or level (High or Low) - Timer 6 compare-match B Timer 6 compare-match A - Timer 7 compare-match B Timer 7 compare-match A - Timer 8 compare-match B Timer 8 compare-match A - Timer 9 compare-match B Timer 9 compare-match A IDMA Priority Ch. - 23 24 - - 25 26 - 27 - - 28 29 30 31 32 33 - - 34 35 - - 36 37 - 38 39 40 41 42 43 44 45 - 46 47 - 48 49 - 50 51 - 52 53 High Low Contents of table "Vector number (Address)" indicates the trap table's vector number. The numerals in parentheses show an offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table by default is the boot address, 0x20000000 set at an initial reset. This address can be changed using the TTBR register. "Exception/interrupt name (peripheral circuit)" indicates that interrupt levels can be programmed for each peripheral circuit written. "Cause of exception/interrupt" indicates the cause of the interrupt occurring in each interrupt system. "IDMA Ch." indicates that a cause of interrupt which has a numeric value in this column can start up the intelligent DMA (IDMA) to transfer data when a cause of interrupt occurs. The numeric value indicates the IDMA's channel number. Causes of interrupt that do not have a numeric value here cannot start up the IDMA. IV-2-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) "Priority" indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt level. If two or more causes of interrupt occur simultaneously, interrupt requests are accepted in order of highest priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the priorities of causes of interrupt in the same interrupt system are fixed in the order that they are written here. I Maskable interrupt generating conditions A maskable interrupt to the CPU occurs when all of the conditions described below are met. * The interrupt enable register for the cause of interrupt that has occurred is set to 1. * The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to 1. * The cause of interrupt that has occurred has a higher priority level than the value that is set in the PSR's Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt system.) * No other cause of trap having higher priority, such as NMI, has occurred. * The cause of interrupt does not invoke IDMA (the IDMA request bit is set to 0). When a cause of interrupt occurs, the corresponding cause-of-interrupt flag is set to 1 and the flag remains set until it is reset in the software program. Therefore, in no cases can the generated cause of interrupt be inadvertently cleared even if the above conditions are not met when the cause of interrupt has occurred. The interrupt will occur when the above conditions are met. However, when the cause of interrupt invokes IDMA, the cause of interrupt is reset if the following condition is met. * The IDMA transfer counter is not 0. * Interrupts are disabled in the IDMA control information even if the transfer counter is 0. If two or more maskable causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept pending until the above conditions are met. The PSR and interrupt control register will be detailed later. For details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in this manual. IV.2.1.2 Causes of Interrupt and Intelligent DMA Several causes of interrupt can be set so that they can invoke IDMA startup. When one of these causes of interrupt occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated after IDMA is completed. (The interrupt request can be disabled by a program.) IDMA is always started up regardless of how the PSR is set. For details, refer to Section IV.2.5, "IDMA Invocation." IV.2.1.3 Nonmaskable Interrupt (NMI) The nonmaskable interrupt (NMI) can be generated by controlling the #NMI pin or using the internal watchdog timer. The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes. This interrupt is prioritized over other interrupts and is unconditionally accepted by the CPU. However, since this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked in hardware until a write to the SP is completed after an initial reset. For controlling the #NMI input, refer to Section II.3.3, "NMI Input." S1C33401 TECHNICAL MANUAL EPSON IV-2-3 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.1.4 Interrupt Processing by the CPU The CPU keeps sampling interrupt requests every cycle. When the CPU accepts an interrupt request, it enters trap processing after completing execution of the instruction that was being executed. The following lists the contents executed in trap processing. (1) The PSR and the current program counter (PC) value are saved to the stack. (2) The IE bit of the PSR is reset to 0 (following maskable interrupts are disabled). (3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level changed). (4) The vector of the generated cause of interrupt is loaded into the PC, thus executing the interrupt processing routine. Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts can also be handled by setting the IE bit to 1 in the interrupt processing routine. In this case, since the IL has been changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is accepted. When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one that was being executed when the interrupt occurred. IV.2.1.5 Clearing Standby Mode by Interrupts The standby modes (HALT, HALT2, and SLEEP) are cleared by an NMI or a maskable interrupt. All maskable interrupts can be used to clear HALT/HALT2 mode. However, DMA interrupt cannot be used in HALT2 mode. In SLEEP mode, since the clock supply to the peripheral circuit is disabled, interrupts from the peripheral circuits except RTC and I/O ports cannot be used. Interrupts that can be used to clear basic HALT mode: NMI and all maskable interrupts Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts) Interrupts that can be used to clear SLEEP mode: NMI, I/O port interrupts, and RTC interrupt When the CPU is released from HALT/HALT2 mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the address for the instruction next to halt is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches to the instruction next to halt. The CPU is released from HALT/HALT2 mode when the ITC asserts the interrupt signal to be sent to the CPU. In other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the interrupt enable bits in the ITC is set to 1, the CPU can be released from HALT/HALT2 mode even if the PSR is set to disable interrupts. However, in this case the CPU does not execute the interrupt handling routine. The #NMI signal releases the CPU from HALT/HALT2 mode when it goes low level even if the NMI detection mode has been set to edge detection mode (refer to Section II.3, "Clock Management Unit (CMU)"). When the CPU is reawaken from SLEEP mode by an interrupt, it enters a program executable state by trap processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so that the reti instruction in the interrupt handling routine branches to the instruction next to slp. Cause-of-interrupt flags in the interrupt controller (ITC) cannot be set in SLEEP mode as the clock is not supplied to the ITC in SLEEP mode. Therefore, when the clock is not supplied to the ITC, the interrupt signals from the interrupt sources that have been enabled to generate an interrupt are input to the CMU through the ITC and used to wake up the CPU from a standby mode. In this case, the cause-of-interrupt flag is set after the clock has started supplying to the ITC. The CPU can wake up from SLEEP mode by a cause of interrupt as described above even if the PSR is set to disable interrupts, note however, that the CPU does not execute the interrupt handling routine. The #NMI signal releases the CPU from SLEEP mode when it goes low level even if the NMI detection mode has been set to edge detection mode. IV-2-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Notes: * In SLEEP mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the ITC, so a delay will occur until the interrupt controller (ITC) sets the cause-of-interrupt flag. Therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the ITC, as the cause-of-interrupt flag in the ITC is not set. Furthermore, additional time is needed for the CPU to accept the interrupt request from the ITC, the CPU may execute a few instructions that follow the slp instruction before it starts the interrupt processing. The same problem may occur when the CPU wakes up from SLEEP mode by NMI. No interrupt will occur if the #NMI signal is deasserted before the clock is supplied, as the NMI flag is not set. I * If the cause of interrupt used to restart from the standby mode has been set to invoke the IDMA, the IDMA is started up by that interrupt. If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-5 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.2 Trap Table The C33 ADV CPU allows the base (starting) address of the trap table to be set by the TTBR register. After an initial reset, the TTBR register is set to 0x20000000. Therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the above address. Bits 9 to 0 in the TTBR register are fixed at 0. Therefore, the trap table starting address always begins with a 1KB boundary address. The TTBR register can be written only in supervisor mode to prevent them from being inadvertently rewritten. IV-2-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.3 ITC Operating Clock I The ITC is clocked by the peripheral circuit clock (PCLK) generated by the CMU. For details on how to set PCLK and control the clock, see Section II.3, "Clock Management Unit (CMU)." Controlling supply of the ITC operating clock PCLK is supplied to the ITC with default settings. There are two ways of supplying PCLK to the ITC by the CMU as detailed below. Use the respective control bits to turn off any unnecessary clock supplies to reduce the amount of power consumed on the chip. 1. ITC clock When this clock supply is turned off, the ITC registers except the interrupt cause flag registers and IDMA related registers (interrupt priority registers, interrupt enable registers, and DMA trigger setup registers) are disabled for writing. However, the cause-of-interrupt flags can be set by the corresponding interrupt request signals from the peripheral circuit, thus interrupt requests to the CPU can also be generated if the interrupt has been enabled. The cause-of-interrupt flag can be cleared by software. Moreover, HSDMA can be invoked normally. IDMA cannot be invoked. However, an interrupt sets the IDMA request bit when the IDMA enable bit has been set to 1 (IDMA request enabled). (The IDMA does not activate even if the IDMA request bit is set.) The clock supply can be controlled by ITCCLK (D0/0x40180). ITCCLK: ITC Clock Control Bit in the Peripheral Clock Control Register 1 (D0/0x40180) 2. Interrupt generation clock This clock is used to generate interrupt requests to the CPU. When this clock supply is turned off, the function to generate interrupt requests to the CPU stops and writing to the interrupt cause flag registers (to clear the flag) is disabled. The clock supply can be controlled by INTCLK (D4/0x40181). INTCLK: Interrupt Generation Clock Control Bit in the Peripheral Clock Control Register 2 (D4/0x40181) Setting any of the above clock control bits (initially 1) to 0 turns off the corresponding clock supply to the ITC. Clock state in standby mode ITC The supply of PCLK stops depending on the type of standby mode. HALT mode: PCLK is supplied the same way as in normal mode. HALT2 mode: PCLK is supplied the same way as in normal mode. SLEEP mode: The supply of PCLK stops. Therefore, the ITC also stops operating when in SLEEP mode. S1C33401 TECHNICAL MANUAL IV EPSON IV-2-7 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.4 Control of Maskable Interrupts IV.2.4.1 Structure of the Interrupt Controller The interrupt controller is configured as shown in Figure IV.2.4.1.1. ITC Key input x HSDMA x Cause-of-interrupt flag CPU interrupt priority judgment (with interrupt level) Interrupt enable IDMA request Interrupt vector generator IDMA enable Interrupt request Interrupt level CPU Interrupt vector Causes of interrupt 16-bit timer x 8-bit timer x Serial I/F x A/D Port input x RTC IDMA Cause-of-interrupt flag Interrupt enable IDMA request IDMA enable IDMA request priority judgment (without interrupt level) IDMA request IDMA channel number generator IDMA completion * * * IDMA channel number IDMA Reset A Reset B Reset C HSDMA trigger selection circuit Ch.x HSDMA request HSDMA Ch.x #DMAREQx input Software trigger Figure IV.2.4.1.1 Configuration of Interrupt Controller The following sections explain the functions of the registers used to control interrupts. IV.2.4.2 Processor Status Register (PSR) The PSR is a special register incorporated in the core CPU and contains control bits to enable or disable an interrupt request to the CPU. Interrupt Enable (IE) bit: PSR[4] This bit is used to enable or disable an interrupt request to the CPU. When this bit is set to 1, the CPU is enabled to accept a maskable interrupt request. When this bit is reset to 0, no maskable interrupt request is accepted by the CPU. When the CPU accepts an interrupt request (or some other trap occurs), it saves the PSR to the stack and resets the IE bit to 0. Consequently, no maskable interrupt request occurring thereafter will be accepted unless the IE bit is set to 1 in software program or the interrupt (trap) processing routine is terminated by the reti instruction. The IE bit is initialized to 0 (interrupts disabled) by an initial reset. Interrupt Level (IL): PSR[11:8] The IL bits disable the interrupts whose priorities are below the set interrupt level. For example, if the interrupt level set in the IL is 3, the interrupts whose priorities are set below 3 in the interrupt priority register (described later) are not accepted by the CPU even if the IE bit is set to 1. The IL and the interrupt priority register together allow you to control the interrupt priorities in each interrupt system. For details about the interrupt levels, refer to Section IV.2.4.4, "Interrupt Priority Register and Interrupt Levels." When the CPU accepts a maskable interrupt request, it saves the PSR to the stack and sets the IL to the accepted interrupt's priority level. Therefore, even when the IE bit is set to 1 in the interrupt processing routine, no interrupts whose priority levels are equal or below that of the interrupt currently being processed are accepted unless the IL is rewritten. The IL is restored to its previous status when the interrupt processing routine is terminated by the reti instruction. The IL is rewritten for only maskable interrupts and not for any other traps (except a reset). The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset. IV-2-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Note: As the C33 ADV Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. I IV.2.4.3 Cause-of-Interrupt Flag and Interrupt Enable Register A cause-of-interrupt flag and an interrupt enable register are provided for each cause of maskable interrupt. Cause-of-interrupt flag The cause-of-interrupt flag is set to 1 when the corresponding cause of interrupt occurs. Reading the flag enables you to determine what caused an interrupt, making it unnecessary to resort to the CPU's trap processing. The cause-of-interrupt flag is reset by writing data in software. Note that the method by which this flag is reset can be selected from the software application using either of the two methods described below. This selection is accomplished using RSTONLY (D0/0x4029F). RSTONLY: Cause-of-Interrupt Flag Reset Method Select Bit in the Flag Set/Reset Method Select Register (D0/0x4029F) * Reset-only method (default) This method is selected (RSTONLY (D0/0x4029F) = 1) when initially reset. With this method, the cause-of-interrupt flag is reset by writing 1. Although multiple cause-of-interrupt flags are located at the same address of the interrupt control register, the cause-of-interrupt flags for which 0 has been written can be neither set nor reset. Therefore, this method ensures that only a specific cause-of-interrupt flag is reset. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that a cause-of-interrupt flag that has been set to 1 is reset by writing. In this method, no cause-of-interrupt flag can be set in the software application. * Read/write method This method is selected by writing 0 to RSTONLY (D0/0x4029F). When this method is used, cause-of-interrupt flags can be read and written as for other registers. Therefore, the flag is reset by writing 0 and set by writing 1. In this case, all cause-of-interrupt flags for which 0 has been written are reset. Even in a read-modify-write operation, a cause of interrupt can occur between the read and the write, so be careful when using this method. Since cause-of-interrupt flags are not initialized by an initial reset, be sure to reset them before enabling interrupts. Notes: * Even when a maskable interrupt request is accepted by the CPU and control branches off to the interrupt processing routine, the cause-of-interrupt flag is not reset. Consequently, if control is returned from the interrupt processing routine by the reti instruction without resetting the cause-of-interrupt flag in a program, the same cause of interrupt occurs again. * When the reti instruction is executed immediately after a cause-of-interrupt flag is reset, the CPU may execute an interrupt processing again even if no interrupt to be processed next is occurred. This problem is caused by a time lag from execution of an instruction (ld, etc.) for resetting the cause-of-interrupt flag until the interrupt request signal to the CPU is negated, which is occurred due to the pipeline processing in the ITC to generate interrupt requests to the CPU using PCLK and the bus-processing pipeline. Care should be taken especially when PCLK is slower than CCLK. To avoid this problem, after the cause-of-interrupt flag is reset (by writing with the ld or other instruction), read the interrupt cause flag register before executing the reti instruction. This makes it possible to return from the interrupt handler routine after the interrupt request to the CPU is negated. For details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in this manual. S1C33401 TECHNICAL MANUAL EPSON IV-2-9 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Interrupt enable register This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this register is set to 1 can an interrupt request to the CPU be enabled by an occurrence of the corresponding cause of interrupt. If the bit is set to 0, no interrupt request is made to the CPU even when the corresponding cause of interrupt occurs. Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset by writing 0 and set by writing 1. By reading this register, its setup status can be checked at any time. Settings of the interrupt enable register do not affect the operation of cause-of-interrupt flags, so when a cause of interrupt occurs the cause-of-interrupt flag is set to 1 even if the corresponding interrupt enable bit is set to 0. When initially reset, the interrupt enable register is set to 0 (interrupts are disabled). In cases when IDMA is started up by occurrence of a cause of interrupt or when clearing standby mode (HALT or SLEEP mode) too, the corresponding interrupt enable bit must be set to 1. The interrupt controller outputs an interrupt request to the CPU when the following conditions are met: * A cause of interrupt has occurred and the cause-of-interrupt flag is set to 1. * The bit of the interrupt enable register for the cause of interrupt that has occurred is set to 1 (interrupt enable). * The bit of the IDMA request register for the cause of interrupt that has occurred is set to 0 (interrupt request). If two or more causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is allowed to signal an interrupt request to the CPU. (See the following section.) When these conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector number. These signals remain asserted until the cause-of-interrupt flag is reset to 0 or the corresponding bit of the interrupt enable register is set to 0 (interrupts are disabled) or until some other cause of interrupt of higher priority occurs. They are not cleared if the CPU simply accepts the interrupt request. IV-2-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.4.4 Interrupt Priority Register and Interrupt Levels I The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table IV.2.1.1.1 can be modified according to system requirements by this setting. The value set in this register is used by the interrupt controller and the CPU as described below. Roles of the interrupt priority register in the interrupt controller If two or more causes of interrupt that have been enabled by the interrupt enable register occur simultaneously, the cause of interrupt in the interrupt system whose interrupt priority register contains the greatest value is allowed by the interrupt controller to signal an interrupt request to the CPU. If a cause of interrupt occurs in two or more interrupt systems having the same value, the interrupt priority is resolved according to the default priorities in Table IV.2.1.1.1. Causes of interrupt in the same interrupt system also have their priorities resolved according to the order in Table IV.2.1.1.1. Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the CPU. When outputting an interrupt request signal to the CPU, the interrupt controller outputs the content of the interrupt priority register to the CPU along with it. If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the interrupt controller changes the vector number and interrupt level to those of the new cause of interrupt before they are output to the CPU. The first interrupt request is left pending. Roles of the interrupt priority register in CPU processing The CPU compares the content of the interrupt priority register received from the interrupt controller with the interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request. IE bit = 1 & IL < interrupt priority register: the interrupt request is accepted IE bit = 1 & IL interrupt priority register: the interrupt request is rejected Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL. For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the interrupt priority register are 4 or more will be accepted. When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL. As a result, the interrupt requests below that interrupt level can no longer be accepted. If the interrupt priority register for an interrupt is set to 0, the interrupt is disabled. However, invoking IDMA by means of a cause of interrupt works fine. Notes: * As the C33 ADV Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. * Multiple interrupts can also be handled by rewriting the interrupt level to the IL in the interrupt processing routine. However, if the interrupt level of the IL is set below the current level and the IE is set to enable interrupts before resetting the cause-of-interrupt flag after an interrupt has occurred, the same interrupt may occur again. S1C33401 TECHNICAL MANUAL EPSON IV-2-11 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.5 IDMA Invocation The causes of interrupt for which IDMA channel numbers are written in Table IV.2.1.1.1 have the function to invoke the intelligent DMA (IDMA). IDMA request register The IDMA request register is used to specify the cause of interrupt that invoke an IDMA transfer. If an IDMA request bit is set to 1, the IDMA request will be generated when the corresponding cause of interrupt occurs. When the IDMA request bit is set to 0, the corresponding cause of interrupt does not invoke IDMA and a normal interrupt processing will be performed. The IDMA request register is set to 0 by an initial reset. The method by which this register is set can be selected from the software application using either of the two methods described below. This selection is accomplished using IDMAONLY (D1/0x4029F). IDMAONLY: IDMA Request Register Set Method Select Bit in the Flag Set/Reset Method Select Register (D1/0x4029F) * Set-only method (default) This method is selected (IDMAONLY (D1/0x4029F) = 1) when initially reset. With this method, an IDMA request bit is set by writing 1. Although multiple IDMA request bits are located in the IDMA request register, the IDMA request bits for which 0 has been written can be neither set nor reset. Therefore, this method ensures that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit that has been set to 1 is not reset by writing. * Read/write method This method is selected by writing 0 to IDMAONLY (D1/0x4029F). When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing 0 and set by writing 1. In this case, all IDMA request bits for which 0 has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. IDMA enable register To perform IDMA transfer using a cause of interrupt, the corresponding bit of the IDMA enable register must be set to 1. If this bit is set to 0, the cause of interrupt cannot invoke the IDMA channel. The IDMA enable register is set to 0 by an initial reset. The IDMA enable register allows selection of a set method (set-only method or read/write method) similar to the IDMA request register. This selection is accomplished using DENONLY (D2/0x4029F). See the above explanation for the set method. DENONLY: IDMA Enable Register Set Method Select Bit in the Flag Set/Reset Method Select Register (D2/0x4029F) Invoking IDMA Before IDMA can be invoked by the occurrence of a cause of interrupt, the corresponding bits of the IDMA request and IDMA enable registers must be set to 1. Then when a cause of interrupt occurs, the interrupt request to the CPU is made pending and the corresponding IDMA channel is invoked. The DMA transfer is performed according to the control information of that IDMA channel. The interrupt level set by the interrupt priority register of the ITC does not affect the IDMA invocation. The IDMA request can be accepted even if the interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled using the interrupt level set by the interrupt priority register. An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to disable interrupts. It is also necessary that the control information for the IDMA channel has been set. IV-2-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Interrupt after IDMA transfer I To generate an interrupt after completion of IDMA transfer: The interrupt request that has been kept pending can be generated after completion of the DMA transfer. In this case, the interrupt must be enabled by the IDMA control information (DINTEN = 1) in addition to the interrupt controller and the PSR register settings. However, if the transfer counter set for the selected IDMA channel does not reach the terminal count of 0 after the number of transfers set have been performed, the cause-of-interrupt flag is reset and no interrupt request is generated. The transfer counter is decremented by 1 for each transfer performed. If the transfer counter is decremented to 0 when DINTEN is set to 1, the cause-of-interrupt flag is not reset and the IDMA request bit is cleared to 0. An interrupt request is generated if other interrupt conditions are met. The IDMA request bit must be set up again in order for IDMA to be invoked when a cause of interrupt occurs next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after resetting the cause-of-interrupt flag. Figure IV.2.5.1 shows the hardware sequence when DINTEN is set to 1. IDMA trigger (cause-of-interrupt flag) Transfer counter 2 3 1 0 Data transfer Reset A signal (reset cause-of-interrupt flag) Reset B signal (reset IDMA request bit) IDMA request bit Interrupt request Figure IV.2.5.1 Sequence when DINTEN = 1 IV To disable an interrupt after completion of IDMA transfer: If an interrupt has been disabled in the IDMA control information (DINTEN = 0), the interrupt is not generated since the cause-of-interrupt flag is reset when the transfer counter becomes 0. In this case, the IDMA request bit remains set to 1 without being cleared. However, the IDMA enable bit is cleared, so the following IDMA request by the same cause of interrupt will be disabled. Figure IV.2.5.2 shows the hardware sequence when DINTEN is set to 0. IDMA trigger (cause-of-interrupt flag) 3 Transfer counter 2 1 0 Data transfer Reset A signal (reset cause-of-interrupt flag) Reset B signal (reset IDMA request bit) Reset C signal (reset IDMA enable bit) IDMA request bit L "1" IDMA enable bit Figure IV.2.5.2 Sequence when DINTEN = 0 For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." S1C33401 TECHNICAL MANUAL EPSON IV-2-13 ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.6 HSDMA Invocation Some causes of interrupt can invoke high-speed DMAs (HSDMA). HSDMA trigger set-up register The DMA block contains four channel of HSDMA circuit. Each channel allows selection of a cause of interrupt as the trigger. HSDxS[3:0] (0x40298-0x40299) is used for this selection. HSD0S[3:0]: Ch.0 Trigger Set-up Bits in the HSDMA Ch.0-1 Trigger Set-up Register (D[3:0]/0x40298) HSD1S[3:0]: Ch.1 Trigger Set-up Bits in the HSDMA Ch.0-1 Trigger Set-up Register (D[7:4]/0x40298) HSD2S[3:0]: Ch.2 Trigger Set-up Bits in the HSDMA Ch.2-3 Trigger Set-up Register (D[3:0]/0x40299) HSD3S[3:0]: Ch.3 Trigger Set-up Bits in the HSDMA Ch.2-3 Trigger Set-up Register (D[7:4]/0x40299) Table IV.2.6.1 shows the setting value and the corresponding trigger source. Table IV.2.6.1 HSDMA Trigger Source Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Ch.0 trigger source Software trigger #DMAREQ0 input (falling edge) #DMAREQ0 input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Port 8 input Port 12 input Ch.1 trigger source Software trigger #DMAREQ1 input (falling edge) #DMAREQ1 input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Port 9 input Port 13 input Ch.2 trigger source Software trigger #DMAREQ2 input (falling edge) #DMAREQ2 input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 6 compare B 16-bit timer 6 compare A Serial I/F Ch.2 Rx buffer full Serial I/F Ch.2 Tx buffer empty A/D conversion completion Port 10 input Port 14 input Ch.3 trigger source Software trigger #DMAREQ3 input (falling edge) #DMAREQ3 input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 7 compare B 16-bit timer 7 compare A Serial I/F Ch.3 Rx buffer full Serial I/F Ch.3 Tx buffer empty A/D conversion completion Port 11 input Port 15 input Invoking HSDMA By selecting a cause of interrupt with the HSDMA trigger set-up register, the HSDMA channel is invoked when the selected cause of interrupt occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable register, IDMA request register, interrupt priority register) do not affect this invocation. The interrupt request to the CPU by the cause of interrupt that invokes HSDMA is output two clocks (PCLK) after the HSDMA request, so the DMA transfer and interrupt handling are performed concurrently when the CPU runs with the instructions in the cache. However, when the interrupt handler contains an instruction that accesses a peripheral circuit, the execution of the instruction is pending until the DMA transfer is completed since the bus is used by the HSDMA. Before HSDMA can be invoked by the occurrence of a cause of interrupt, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to Section III.4, "High-Speed DMA (HSDMA)." IV-2-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.7 Details of Control Registers I Table IV.2.7.1 List of ITC Registers Address 0x00040260 0x00040261 0x00040262 0x00040263 0x00040264 0x00040265 0x00040266 0x00040267 0x00040268 0x00040269 0x0004026A 0x0004026B 0x0004026C 0x0004026D 0x0004026E 0x00040270 0x00040271 0x00040272 0x00040273 0x00040274 0x00040275 0x00040276 0x00040277 0x00040278 0x00040279 0x00040280 0x00040281 0x00040282 0x00040283 0x00040284 0x00040285 0x00040286 0x00040287 0x00040288 0x00040289 0x00040290 0x00040291 0x00040292 Size Register name Function 8 Sets interrupt level for port input 0-1 interrupts. Port Input 0-1 Interrupt Priority Register (pINT_PR01L) 8 Sets interrupt level for port input 2-3 interrupts. Port Input 2-3 Interrupt Priority Register (pINT_PR23L) 8 Sets interrupt level for key input interrupts. Key Input Interrupt Priority Register (pINT_PK01L) 8 Sets interrupt level for HSDMA Ch.0-1 interrupts. HSDMA Ch.0-1 Interrupt Priority Register (pINT_PHSD01L) 8 Sets interrupt level for HSDMA Ch.2-3 interrupts. HSDMA Ch.2-3 Interrupt Priority Register (pINT_PHSD23L) 8 Sets interrupt level for IDMA interrupts. IDMA Interrupt Priority Register (pINT_PDM) 16-bit Timer 0-1 Interrupt Priority Register (pINT_P16T01) 8 Sets interrupt level for 16-bit timer 0-1 interrupts. 16-bit Timer 2-3 Interrupt Priority Register (pINT_P16T23) 8 Sets interrupt level for 16-bit timer 2-3 interrupts. 16-bit Timer 4-5 Interrupt Priority Register (pINT_P16T45) 8 Sets interrupt level for 16-bit timer 4-5 interrupts. 8 Sets interrupt level for 8-bit timer and serial I/F Ch.0 8-bit Timer, Serial I/F Ch.0 Interrupt Priority Register (pINT_P8T_PSI00) interrupts. 8 Sets interrupt level for serial I/F Ch.1 and A/D Serial I/F Ch.1, A/D Interrupt Priority Register (pINT_PSI01_PAD) converter interrupts. 8 Sets interrupt level for RTC interrupts. RTC Interrupt Priority Register (pINT_PCTM) 8 Sets interrupt level for port input 4-5 interrupts. Port Input 4-5 Interrupt Priority Register (pINT_PR45L) 8 Sets interrupt level for port input 6-7 interrupts. Port Input 6-7 Interrupt Priority Register (pINT_PR67L) 8 Sets interrupt level for serial I/F Ch.2-3 interrupts. Serial I/F Ch.2-3 Interrupt Priority Register (pINT_PSI0203) 8 Enables key input and port input 0-3 interrupts. Key Input, Port Input 0-3 Interrupt Enable Register (pINT_EK01_EP03) 8 Enables DMA interrupts. DMA Interrupt Enable Register (pINT_EDMA) 16-bit Timer 0-1 Interrupt Enable Register (pINT_E16T01) 8 Enables 16-bit timer 0-1 interrupts. 16-bit Timer 2-3 Interrupt Enable Register (pINT_E16T23) 8 Enables 16-bit timer 2-3 interrupts. 16-bit Timer 4-5 Interrupt Enable Register (pINT_E16T45) 8 Enables 16-bit timer 4-5 interrupts. 8 Enables 8-bit timer 0-3 interrupts. 8-bit Timer 0-3 Interrupt Enable Register (pINT_E8T03) Serial I/F Ch.0-1 Interrupt Enable Register (pINT_ESIF01) 8 Enables serial I/F Ch.0-1 interrupts. 8 Enables port input 4-7, RTC and A/D interrupts. Port Input 4-7, RTC, A/D Interrupt Enable Register (pINT_EP47_ECT_EAD) 8 Enables 8-bit timer 4-5 interrupts. 8-bit Timer 4-5 Interrupt Enable Register (pINT_E8T45) Serial I/F Ch.2-3 Interrupt Enable Register (pINT_ESIF23) 8 Enables serial I/F Ch.2-3 interrupts. 8 Indicates/resets key input and port input 0-3 interrupt Key Input, Port Input 0-3 Interrupt Cause Flag Register (pINT_FK01_FP03) status. 8 Indicates/resets DMA interrupt status. DMA Interrupt Cause Flag Register (pINT_FDMA) 8 Indicates/resets 16-bit timer 0-1 interrupt status. 16-bit Timer 0-1 Interrupt Cause Flag Register (pINT_F16T01) 8 Indicates/resets 16-bit timer 2-3 interrupt status. 16-bit Timer 2-3 Interrupt Cause Flag Register (pINT_F16T23) 8 Indicates/resets 16-bit timer 4-5 interrupt status. 16-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F16T45) 8 Indicates/resets 8-bit timer 0-3 interrupt status. 8-bit Timer 0-3 Interrupt Cause Flag Register (pINT_F8T03) 8 Indicates/resets serial I/F Ch.0-1 interrupt status. Serial I/F Ch.0-1 Interrupt Cause Flag Register (pINT_FSIF01) 8 Indicates/resets port input 4-7, RTC and A/D Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (pINT_FP47_FCT_FAD) converter interrupt status. 8 Indicates/resets 8-bit timer 4-5 interrupt status. 8-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F8T45) 8 Indicates/resets serial I/F Ch.2-3 interrupt status. Serial I/F Ch.2-3 Interrupt Cause Flag Register (pINT_FSIF23) 8 Sets IDMA invocation by port input 0-3, HSDMA Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Request Register (pIDMAREQ_RP03_RHS_R16T0) Ch.0-1 and 16-bit timer 0. 8 Sets IDMA invocation by 16-bit timer 1-4. 16-bit Timer 1-4 IDMA Request Register (pIDMAREQ_R16T14) 8 Sets IDMA invocation by 16-bit timer 5, 8-bit timer 0-3 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Request Register (pIDMAREQ_R16T5_R8T_RSIF0) and serial I/F Ch.0. S1C33401 TECHNICAL MANUAL EPSON IV-2-15 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Address 0x00040293 0x00040294 0x00040295 0x00040296 0x00040297 0x00040298 0x00040299 0x0004029A 0x0004029B 0x0004029C 0x0004029F 0x000402A0 0x000402A1 0x000402A2 0x000402A3 0x000402A4 0x000402A5 0x000402A6 0x000402A7 0x000402A8 0x000402A9 0x000402AA 0x000402AB 0x000402AC 0x000402AD 0x000402AE 0x000402AF Size Register name Function 8 Sets IDMA invocation by serial I/F Ch.1, A/D Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Request Register (pIDMAREQ_RSIF1_RAD_RP47) converter, and port input 4-7. 8 Enables IDMA requests by port input 0-3, HSDMA Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Enable Register (pIDMAEN_DEP03_DEHS_DE16T0) Ch.0-1, and 16-bit timer 0. 8 Enables IDMA requests by 16-bit timer 1-4. 16-bit Timer 1-4 IDMA Enable Register (pIDMAEN_DE16T14) 8 Enables IDMA requests by 16-bit timer 5, 8-bit timer 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Enable Register (pIDMAEN_DE16T5_DE8T_DESIF0) 0-3, and Serial I/F Ch.0. 8 Enables IDMA requests by serial I/F Ch.1, A/D Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Enable Register (pIDMAEN_DESIF1_DEAD_DEP47) converter, and port input 4-7. 8 Selects HSDMA Ch.0-1 trigger sources. HSDMA Ch.0-1 Trigger Set-up Register (pHSDMA_HTGR1) 8 Selects HSDMA Ch.2-3 trigger sources. HSDMA DMA Ch.2-3 Trigger Set-up Register (pHSDMA_HTGR2) 8 Invokes HSDMA. HSDMA Software Trigger Register (pHSDMA_HSOFTTGR) 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Request Register 8 Sets IDMA invocation by 8-bit timer 4-5 and serial I/F (pIDMAREQ_R8T45_RSIF23) Ch.2-3. 8 Enables IDMA requests by 8-bit timer 4-5 and serial 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Enable Register (pIDMAEN_DE8T45_DESIF23) I/F Ch.2-3. 8 Selects flag set/reset method. Flag Set/Reset Method Select Register (pRST_RESET) 8 Sets interrupt level for port input 8-9 interrupts. Port Input 8-9 Interrupt Priority Register (pINT_PR89L) 8 Sets interrupt level for port input 10-11 interrupts. Port Input 10-11 Interrupt Priority Register (pINT_PR1011L) 8 Sets interrupt level for port input 12-13 interrupts. Port Input 12-13 Interrupt Priority Register (pINT_PR1213L) 8 Sets interrupt level for port input 14-15 interrupts. Port Input 14-15 Interrupt Priority Register (pINT_PR1415L) 8 Sets interrupt level for 16-bit timer 6-7 interrupts. 16-bit Timer 6-7 Interrupt Priority Register (pINT_P16T67) 8 Sets interrupt level for 16-bit timer 8-9 interrupts. 16-bit Timer 8-9 Interrupt Priority Register (pINT_P16T89) 8 Enables port input 8-15 interrupts. Port Input 8-15 Interrupt Enable Register (pINT_EP815) 16-bit Timer 6-7 Interrupt Enable Register (pINT_E16T67) 8 Enables 16-bit timer 6-7 interrupts. 16-bit Timer 8-9 Interrupt Enable Register (pINT_E16T89) 8 Enables 16-bit timer 8-9 interrupts. 8 Indicates/resets port input 8-15 interrupt status. Port Input 8-15 Interrupt Cause Flag Register (pINT_FP815) 8 Indicates/resets 16-bit timer 6-7 interrupt status. 16-bit Timer 6-7 Interrupt Cause Flag Register (pINT_F16T67) 8 Indicates/resets 16-bit timer 8-9 interrupt status. 16-bit Timer 8-9 Interrupt Cause Flag Register (pINT_F16T89) 8 Sets IDMA invocation by port input 8-15. Port Input 8-15 IDMA Request Register (pIDMAREQ_RP815) 8 Sets IDMA invocation by 16-bit timer 6-9. 16-bit Timer 6-9 IDMA Request Register (pIDMAREQ_R16T69) 8 Enables IDMA requests by port input 8-15. Port Input 8-15 IDMA Enable Register (pIDMAEN_DEP815) 8 Enables IDMA requests by 16-bit timer 6-9. 16-bit Timer 6-9 IDMA Enable Register (pIDMAEN_DE16T69) The following describes each ITC control register. The ITC control registers are mapped in the 8-bit device area from 0x40260 to 0x402AF, and can be accessed in units of bytes. Note: When setting the ITC control registers, be sure to write a 0, and not a 1, for all "reserved bits." IV-2-16 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40260: Port Input 0-1 Interrupt Priority Register (pINT_PR01L) Register name Address Bit Port input 0-1 0040260 (B) interrupt priority register (pINT_PR01L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 Function Setting reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP1L[2:0]: Port Input 1 Interrupt Level Bits Sets the priority level of the port input 1 interrupt. D3 Reserved D[2:0] PP0L[2:0]: Port Input 0 Interrupt Level Bits Sets the priority level of the port input 0 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-17 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40261: Port Input 2-3 Interrupt Priority Register (pINT_PR23L) Register name Address Bit Port input 2-3 0040261 (B) interrupt priority register (pINT_PR23L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 Function Setting reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP3L[2:0]: Port Input 3 Interrupt Level Bits Sets the priority level of the port input 3 interrupt. D3 Reserved D[2:0] PP2L[2:0]: Port Input 2 Interrupt Level Bits Sets the priority level of the port input 2 interrupt. IV-2-18 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40262: Key Input Interrupt Priority Register (pINT_PK01L) Register name Address Bit 0040262 Key input (B) interrupt priority register (pINT_PK01L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 Function Setting reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 I Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PK1L[2:0]: Key Input 1 Interrupt Level Bits Sets the priority level of the key input 1 interrupt. D3 Reserved D[2:0] PK0L[2:0]: Key Input 0 Interrupt Level Bits Sets the priority level of the key input 0 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-19 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40263: HSDMA Ch.0-1 Interrupt Priority Register (pINT_PHSD01L) Register name Address Bit HSDMA Ch.0-1 0040263 (B) interrupt priority register (pINT_PHSD01L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 Function Setting reserved HSDMA Ch.1 interrupt level - 0 to 7 reserved HSDMA Ch.0 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PHSD1L[2:0]: HSDMA Ch.1 Interrupt Level Bits Sets the priority level of the HSDMA Ch.1 interrupt. D3 Reserved D[2:0] PHSD0L[2:0]: HSDMA Ch.0 Interrupt Level Bits Sets the priority level of the HSDMA Ch.0 interrupt. IV-2-20 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40264: HSDMA Ch.2-3 Interrupt Priority Register (pINT_PHSD23L) Register name Address Bit HSDMA Ch.2-3 0040264 (B) interrupt priority register (pINT_PHSD23L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 Function Setting reserved HSDMA Ch.3 interrupt level - 0 to 7 reserved HSDMA Ch.2 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PHSD3L[2:0]: HSDMA Ch.3 Interrupt Level Bits Sets the priority level of the HSDMA Ch.3 interrupt. D3 Reserved D[2:0] PHSD2L[2:0]: HSDMA Ch.2 Interrupt Level Bits Sets the priority level of the HSDMA Ch.2 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-21 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40265: IDMA Interrupt Priority Register (pINT_PDM) Register name Address Bit IDMA interrupt 0040265 (B) priority register (pINT_PDM) D7-3 D2 D1 D0 Name - PDM2 PDM1 PDM0 Function Setting - 0 to 7 reserved IDMA interrupt level Init. R/W - X X X Remarks - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D[7:3] Reserved D[2:0] PDM[2:0]: IDMA Interrupt Level Bits Sets the priority level of the IDMA interrupt. IV-2-22 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40266: 16-bit Timer 0-1 Interrupt Priority Register (pINT_P16T01) Register name Address Bit 16-bit timer 0-1 0040266 (B) interrupt priority register (pINT_P16T01) D7 D6 D5 D4 D3 D2 D1 D0 Name - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 Function Setting reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] P16T1[2:0]: 16-bit Timer 1 Interrupt Level Bits Sets the priority levels of the 16-bit timer 1 interrupt. D3 Reserved D[2:0] P16T0[2:0]: 16-bit Timer 0 Interrupt Level Bits Sets the priority levels of the 16-bit timer 0 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-23 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40267: 16-bit Timer 2-3 Interrupt Priority Register (pINT_P16T23) Register name Address Bit 16-bit timer 2-3 0040267 (B) interrupt priority register (pINT_P16T23) D7 D6 D5 D4 D3 D2 D1 D0 Name - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 Function Setting reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] P16T3[2:0]: 16-bit Timer 3 Interrupt Level Bits Sets the priority levels of the 16-bit timer 3 interrupt. D3 Reserved D[2:0] P16T2[2:0]: 16-bit Timer 2 Interrupt Level Bits Sets the priority levels of the 16-bit timer 2 interrupt. IV-2-24 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40268: 16-bit Timer 4-5 Interrupt Priority Register (pINT_P16T45) Register name Address Bit 16-bit timer 4-5 0040268 (B) interrupt priority register (pINT_P16T45) D7 D6 D5 D4 D3 D2 D1 D0 Name - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 Function Setting reserved 16-bit timer 5 interrupt level - 0 to 7 reserved 16-bit timer 4 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] P16T5[2:0]: 16-bit Timer 5 Interrupt Level Bits Sets the priority levels of the 16-bit timer 5 interrupt. D3 Reserved D[2:0] P16T4[2:0]: 16-bit Timer 4 Interrupt Level Bits Sets the priority levels of the 16-bit timer 4 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-25 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40269: 8-bit Timer, Serial I/F Ch.0 Interrupt Priority Register (pINT_P8T_PSI00) Register name Address Bit 0040269 8-bit timer, (B) serial I/F Ch.0 interrupt priority register (pINT_P8T_PSI00) D7 D6 D5 D4 D3 D2 D1 D0 Name - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 Function Setting reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-5 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PSIO0[2:0]: Serial Interface Ch.0 Interrupt Level Bits Sets the priority levels of the serial interface Ch.0 interrupt. D3 Reserved D[2:0] P8TM[2:0]: 8-bit Timer 0-5 Interrupt Level Bits Sets the priority levels of the 8-bit timer 0-5 interrupt. IV-2-26 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4026A: Serial I/F Ch.1, A/D Interrupt Priority Register (pINT_PSI01_PAD) Register name Address Bit Serial I/F Ch.1, 004026A (B) A/D interrupt priority register (pINT_PSI01_PAD) D7 D6 D5 D4 D3 D2 D1 D0 Name - PAD2 PAD1 PAD0 - PSIO12 PSIO11 PSIO10 Function Setting reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PAD[2:0]: A/D Converter Interrupt Level Bits Sets the priority levels of the A/D converter interrupt. D3 Reserved D[2:0] PSIO1[2:0]: Serial Interface Ch.1 Interrupt Level Bits Sets the priority levels of the serial interface Ch.1 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-27 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4026B: RTC Interrupt Priority Register (pINT_PCTM) Register name Address Bit Name RTC interrupt 004026B D7-3 - D2 PCTM2 (B) priority register D1 PCTM1 (pINT_PCTM) D0 PCTM0 Function Setting - 0 to 7 reserved RTC interrupt level Init. R/W - X X X Remarks - Writing 1 not allowed. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D[7:3] Reserved D[2:0] PCTM[2:0]: RTC Interrupt Level Bits Sets the priority level of the RTC interrupt. IV-2-28 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4026C: Port Input 4-5 Interrupt Priority Register (pINT_PR45L) Register name Address Bit Port input 4-5 004026C (B) interrupt priority register (pINT_PR45L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 Function Setting reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP5L[2:0]: Port Input 5 Interrupt Level Bits Sets the priority level of the port input 5 interrupt. D3 Reserved D[2:0] PP4L[2:0]: Port Input 4 Interrupt Level Bits Sets the priority level of the port input 4 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-29 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4026D: Port Input 6-7 Interrupt Priority Register (pINT_PR67L) Register name Address Bit Port input 6-7 004026D (B) interrupt priority register (pINT_PR67L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 Function Setting reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP7L[2:0]: Port Input 7 Interrupt Level Bits Sets the priority level of the port input 7 interrupt. D3 Reserved D[2:0] PP6L[2:0]: Port Input 6 Interrupt Level Bits Sets the priority level of the port input 6 interrupt. IV-2-30 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4026E: Serial I/F Ch.2-3 Interrupt Priority Register (pINT_PSI0203) Register name Address Bit 004026E Serial I/F (B) Ch.2-3 interrupt priority register (pINT_PSI0203) D7 D6 D5 D4 D3 D2 D1 D0 Name - PSIO32 PSIO31 PSIO30 - PSIO22 PSIO21 PSIO20 Function Setting reserved Serial interface Ch.3 interrupt level - 0 to 7 reserved Serial interface Ch.2 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PSIO3[2:0]: Serial Interface Ch.3 Interrupt Level Bits Sets the priority levels of the serial interface Ch.3 interrupt. D3 Reserved D[2:0] PSIO2[2:0]: Serial Interface Ch.2 Interrupt Level Bits Sets the priority levels of the serial interface Ch.2 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-31 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40270: Key Input, Port Input 0-3 Interrupt Enable Register (pINT_EK01_EP03) Register name Address Bit 0040270 Key input, (B) port input 0-3 interrupt enable register (pINT_EK01_EP03) D7-6 D5 D4 D3 D2 D1 D0 Name - EK1 EK0 EP3 EP2 EP1 EP0 Function reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Setting - 1 Enabled 0 Disabled Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:6] Reserved D5 EK1: Key Input 1 Interrupt Enable Bit Enables or disables the key input 1 interrupt. D4 EK0: Key Input 0 Interrupt Enable Bit Enables or disables the key input 0 interrupt. D3 EP3: Port Input 3 Interrupt Enable Bit Enables or disables the port input 3 interrupt. D2 EP2: Port Input 2 Interrupt Enable Bit Enables or disables the port input 2 interrupt. D1 EP1: Port Input 1 Interrupt Enable Bit Enables or disables the port input 1 interrupt. D0 EP0: Port Input 0 Interrupt Enable Bit Enables or disables the port input 0 interrupt. IV-2-32 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40271: DMA Interrupt Enable Register (pINT_EDMA) Register name Address Bit DMA interrupt 0040271 (B) enable register (pINT_EDMA) D7-5 D4 D3 D2 D1 D0 Name - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 Function reserved IDMA HSDMA Ch.3 HSDMA Ch.2 HSDMA Ch.1 HSDMA Ch.0 Setting - 1 Enabled 0 Disabled I Init. R/W - 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:5] Reserved D4 EIDMA: IDMA Enable Interrupt Bit Enables or disables the IDMA interrupt. D3 EHDMA3: HSDMA Ch.3 Interrupt Enable Bit Enables or disables the HSDMA Ch.3 interrupt. D2 EHDMA2: HSDMA Ch.2 Interrupt Enable Bit Enables or disables the HSDMA Ch.2 interrupt. D1 EHDMA1: HSDMA Ch.1 Interrupt Enable Bit Enables or disables the HSDMA Ch.1 interrupt. D0 EHDMA0: HSDMA Ch.0 Interrupt Enable Bit Enables or disables the HSDMA Ch.0 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-33 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40272: 16-bit Timer 0-1 Interrupt Enable Register (pINT_E16T01) Register name Address Bit 16-bit timer 0-1 0040272 (B) interrupt enable register (pINT_E16T01) D7 D6 D5-4 D3 D2 D1-0 Name E16TC1 E16TU1 - E16TC0 E16TU0 - Function 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - Init. R/W 0 0 - 0 0 - Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 E16TC1: 16-bit Timer 1 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 1 comparison A interrupt. D6 E16TU1: 16-bit Timer 1 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 1 comparison B interrupt. D[5:4] Reserved D3 E16TC0: 16-bit Timer 0 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 0 comparison A interrupt. D2 E16TU0: 16-bit Timer 0 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 0 comparison B interrupt. D[1:0] Reserved IV-2-34 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40273: 16-bit Timer 2-3 Interrupt Enable Register (pINT_E16T23) Register name Address Bit 16-bit timer 2-3 0040273 (B) interrupt enable register (pINT_E16T23) D7 D6 D5-4 D3 D2 D1-0 Name E16TC3 E16TU3 - E16TC2 E16TU2 - Function 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - Init. R/W 0 0 - 0 0 - I Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 E16TC3: 16-bit Timer 3 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 3 comparison A interrupt. D6 E16TU3: 16-bit Timer 3 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 3 comparison B interrupt. D[5:4] Reserved D3 E16TC2: 16-bit Timer 2 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 2 comparison A interrupt. D2 E16TU2: 16-bit Timer 2 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 2 comparison B interrupt. D[1:0] Reserved IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-35 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40274: 16-bit Timer 4-5 Interrupt Enable Register (pINT_E16T45) Register name Address Bit 16-bit timer 4-5 0040274 (B) interrupt enable register (pINT_E16T45) D7 D6 D5-4 D3 D2 D1-0 Name E16TC5 E16TU5 - E16TC4 E16TU4 - Function 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - Init. R/W 0 0 - 0 0 - Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 E16TC5: 16-bit Timer 5 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 5 comparison A interrupt. D6 E16TU5: 16-bit Timer 5 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 5 comparison B interrupt. D[5:4] Reserved D3 E16TC4: 16-bit Timer 4 Comparison A Interrupt Enable Bit Enables or disables the 16-bit timer 4 comparison A interrupt. D2 E16TU4: 16-bit Timer 4 Comparison B Interrupt Enable Bit Enables or disables the 16-bit timer 4 comparison B interrupt. D[1:0] Reserved IV-2-36 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40275: 8-bit Timer 0-3 Interrupt Enable Register (pINT_E8T03) Register name Address Bit 8-bit timer 0-3 0040275 (B) interrupt enable register (pINT_E8T03) D7-4 D3 D2 D1 D0 Name - E8TU3 E8TU2 E8TU1 E8TU0 Function reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Setting - 1 Enabled 0 Disabled Init. R/W - 0 0 0 0 I Remarks - 0 when being read. R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:4] Reserved D3 E8TU3: 8-bit Timer 3 Underflow Interrupt Enable Bit Enables or disables the 8-bit timer 3 underflow interrupt. D2 E8TU2: 8-bit Timer 2 Underflow Interrupt Enable Bit Enables or disables the 8-bit timer 2 underflow interrupt. D1 E8TU1: 8-bit Timer 1 Underflow Interrupt Enable Bit Enables or disables the 8-bit timer 1 underflow interrupt. D0 E8TU0: 8-bit Timer 0 Underflow Interrupt Enable Bit Enables or disables the 8-bit timer 0 underflow interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-37 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40276: Serial I/F Ch.0-1 Interrupt Enable Register (pINT_ESIF01) Register name Address Bit 0040276 Serial I/F (B) Ch.0-1 interrupt enable register (pINT_ESIF01) D7-6 D5 D4 D3 D2 D1 D0 Name - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 Function reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Setting - 1 Enabled 0 Disabled Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:6] Reserved D5 ESTX1: SIF Ch.1 Transmit Buffer Empty Interrupt Enable Bit Enables or disables the SIF Ch.1 transmit buffer empty interrupt. D4 ESRX1: SIF Ch.1 Receive Buffer Full Interrupt Enable Bit Enables or disables the SIF Ch.1 receive buffer full interrupt. D3 ESERR1: SIF Ch.1 Receive Error Interrupt Enable Bit Enables or disables the SIF Ch.1 receive error interrupt. D2 ESTX0: SIF Ch.0 Transmit Buffer Empty Interrupt Enable Bit Enables or disables the SIF Ch.0 transmit buffer empty interrupt. D1 ESRX0: SIF Ch.0 Receive Buffer Full Interrupt Enable Bit Enables or disables the SIF Ch.0 receive buffer full interrupt. D0 ESERR0: SIF Ch.0 Receive Error Interrupt Enable Bit Enables or disables the SIF Ch.0 receive error interrupt. IV-2-38 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40277: Port Input 4-7, RTC, A/D Interrupt Enable Register (pINT_EP47_ECT_EAD) Register name Address Bit Port input 4-7, 0040277 (B) RTC, A/D interrupt enable register (pINT_EP47_ECT _EAD) D7 D6 D5 D4 D3 D2 D1 D0 Name - EP7 EP6 EP5 EP4 ECTM EADE EADC Function reserved Port input 7 Port input 6 Port input 5 Port input 4 RTC A/D conversion completion A/D upper/lower limit Setting - 1 Enabled 0 Disabled I Init. R/W - 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 Reserved D6 EP7: Port Input 7 Interrupt Enable Bit Enables or disables the port input 7 interrupt. D5 EP6: Port Input 6 Interrupt Enable Bit Enables or disables the port input 6 interrupt. D4 EP5: Port Input 5 Interrupt Enable Bit Enables or disables the port input 5 interrupt. D3 EP4: Port Input 4 Interrupt Enable Bit Enables or disables the port input 4 interrupt. IV D2 ECTM: RTC Interrupt Enable Bit Enables or disables the RTC interrupt. ITC D1 EADE: A/D Conversion Completion Interrupt Enable Bit Enables or disables the A/D conversion completion interrupt. D0 EADC: A/D Upper/Lower Limit Interrupt Enable Bit Enables or disables the A/D upper/lower limit interrupt. S1C33401 TECHNICAL MANUAL EPSON IV-2-39 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40278: 8-bit Timer 4-5 Interrupt Enable Register (pINT_E8T45) Register name Address 8-bit timer 4-5 0040278 (B) interrupt enable register (pINT_E8T45) Name Bit D7-2 - D1 D0 E8TU5 E8TU4 Function Setting reserved Init. R/W - 8-bit timer 5 underflow 8-bit timer 4 underflow 1 Enabled 0 Disabled - - 0 0 R/W R/W Remarks 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:2] Reserved D1 E8TU5: 8-bit Timer 5 Underflow Interrupt Enable Bit Enables or disables interrupt generation of the 8-bit timer 5 underflow interrupt. D0 E8TU4: 8-bit Timer 4 Underflow Interrupt Enable Bit Enables or disables interrupt generation of the 8-bit timer 4 underflow interrupt. IV-2-40 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40279: Serial I/F Ch.2-3 Interrupt Enable Register (pINT_ESIF23) Register name Address Bit 0040279 Serial I/F (B) Ch.2-3 interrupt enable register (pINT_ESIF23) D7-6 D5 D4 D3 D2 D1 D0 Name - ESTX3 ESRX3 ESERR3 ESTX2 ESRX2 ESERR2 Function reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.3 receive error SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full SIF Ch.2 receive error Setting - 1 Enabled 0 Disabled Init. R/W - 0 0 0 0 0 0 I Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D[7:6] Reserved D5 ESTX3: SIF Ch.3 Transmit Buffer Empty Interrupt Enable Bit Enables or disables the SIF Ch.3 transmit buffer empty interrupt. D4 ESRX3: SIF Ch.3 Receive Buffer Full Interrupt Enable Bit Enables or disables the SIF Ch.3 receive buffer full interrupt. D3 ESERR3: SIF Ch.3 Receive Error Interrupt Enable Bit Enables or disables the SIF Ch.3 receive error interrupt. D2 ESTX2: SIF Ch.2 Transmit Buffer Empty Interrupt Enable Bit Enables or disables the SIF Ch.2 transmit buffer empty interrupt. D1 ESRX2: SIF Ch.2 Receive Buffer Full Interrupt Enable Bit Enables or disables the SIF Ch.2 receive buffer full interrupt. D0 ESERR2: SIF Ch.2 Receive Error Interrupt Enable Bit Enables or disables the SIF Ch.2 receive error interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-41 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40280: Key Input, Port Input 0-3 Interrupt Cause Flag Register (pINT_FK01_FP03) Register name Address Bit 0040280 Key input, (B) port input 0-3 interrupt cause flag register (pINT_FK01_FP03) D7-6 D5 D4 D3 D2 D1 D0 Name - FK1 FK0 FP3 FP2 FP1 FP0 Function reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 Setting Init. R/W - 1 Occurred 0 Not occurred - X X X X X X Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset The cause-of-interrupt flag is set to 1 when a cause of interrupt occurs in each peripheral circuit. If the following conditions are met at this time, an interrupt is generated to the CPU: 1. The corresponding bit of the interrupt enable register is set to 1. 2. No other interrupt request of higher priority has occurred. 3. The IE bit of the PSR is set to 1 (interrupt enabled). 4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL). When using a cause of interrupt to request IDMA, note that even when the above conditions are met, no interrupt request to the CPU is generated for the cause of interrupt that has occurred. If interrupts are enabled at the setting of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed. The cause-of-interrupt flag is always set to 1 when a cause of interrupt occurs no matter how the interrupt enable and interrupt priority registers are set. In order for the next interrupt to be accepted after interrupt generation, the cause-of-interrupt flag must be reset and the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and setting the IE bit to 1 or executing the reti instruction). The cause-of-interrupt flag can only be reset by a write instruction in the software application. If the PSR is again set up to accept interrupts (or the reti instruction is executed) without resetting the cause-of-interrupt flag, the same interrupt may occur again. Note also that the value to be written to reset the flag is 1 when using the reset-only method (RSTONLY (D0/0x4029F) = 1) and 0 when using the read/write method (RSTONLY (D0/0x4029F) = 0). Be careful not to confuse these two conditions. The cause-of-interrupt flag becomes indeterminate when initially reset, so be sure to reset the flag in the software application. IV-2-42 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) Notes: * Even when a maskable interrupt request is accepted by the CPU and control branches off to the interrupt processing routine, the cause-of-interrupt flag is not reset. Consequently, if control is returned from the interrupt processing routine by the reti instruction without resetting the cause-of-interrupt flag in a program, the same cause of interrupt occurs again. I * When the reti instruction is executed immediately after a cause-of-interrupt flag is reset, the CPU may execute an interrupt processing again even if no interrupt to be processed next is occurred. This problem is caused by a time lag from execution of an instruction (ld, etc.) for resetting the cause-of-interrupt flag until the interrupt request signal to the CPU is negated, which is occurred due to the pipeline processing in the ITC to generate interrupt requests to the CPU using PCLK and the bus-processing pipeline. Care should be taken especially when PCLK is slower than CCLK. To avoid this problem, after the cause-of-interrupt flag is reset (by writing with the ld or other instruction), read the interrupt cause flag register before executing the reti instruction. This makes it possible to return from the interrupt handler routine after the interrupt request to the CPU is negated. D[7:6] Reserved D5 FK1: Key Input 1 Cause-of-Interrupt Flag Indicates the key input 1 interrupt cause status. D4 FK0: Key Input 0 Cause-of-Interrupt Flag Indicates the key input 0 interrupt cause status. D3 FP3: Port Input 3 Cause-of-Interrupt Flag Indicates the port input 3 interrupt cause status. D2 FP2: Port Input 2 Cause-of-Interrupt Flag Indicates the port input 2 interrupt cause status. D1 FP1: Port Input 1 Cause-of-Interrupt Flag Indicates the port input 1 interrupt cause status. D0 IV ITC FP0: Port Input 0 Cause-of-Interrupt Flag Indicates the port input 0 interrupt cause status. S1C33401 TECHNICAL MANUAL EPSON IV-2-43 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40281: DMA Interrupt Cause Flag Register (pINT_FDMA) Register name Address DMA interrupt cause flag register (pINT_FDMA) 0040281 (B) Bit D7-5 D4 D3 D2 D1 D0 Name - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 Function reserved IDMA HSDMA Ch.3 HSDMA Ch.2 HSDMA Ch.1 HSDMA Ch.0 Setting Init. R/W - 1 Occurred 0 Not occurred - X X X X X Remarks - 0 when being read. R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D[7:5] Reserved D4 FIDMA: IDMA Cause-of-Interrupt Flag Indicates the IDMA interrupt cause status. D3 FHDM3: HSDMA Ch.3 Cause-of-Interrupt Flag Indicates the HSDMA Ch.3 interrupt cause status. D2 EHDM2: HSDMA Ch.2 Cause-of-Interrupt Flag Indicates the HSDMA Ch.2 interrupt cause status. D1 FHDM1: HSDMA Ch.1 Cause-of-Interrupt Flag Indicates the HSDMA Ch.1 interrupt cause status. D0 FHDM0: HSDMA Ch.0 Cause-of-Interrupt Flag Indicates the HSDMA Ch.0 interrupt cause status. IV-2-44 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40282: 16-bit Timer 0-1 Interrupt Cause Flag Register (pINT_F16T01) Register name Address Bit 16-bit timer 0-1 0040282 (B) interrupt cause flag register (pINT_F16T01) D7 D6 D5-4 D3 D2 D1-0 Name F16TC1 F16TU1 - F16TC0 F16TU0 - Function 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved Setting 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - Init. R/W X X - X X - I Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 F16TC1: 16-bit Timer 1 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 1 comparison A interrupt cause status. D6 F16TU1: 16-bit Timer 1 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 1 comparison B interrupt cause status. D[5:4] Reserved D3 F16TC0: 16-bit Timer 0 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 0 comparison A interrupt cause status. IV D2 F16TU0: 16-bit Timer 0 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 0 comparison B interrupt cause status. ITC D[1:0] Reserved S1C33401 TECHNICAL MANUAL EPSON IV-2-45 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40283: 16-bit Timer 2-3 Interrupt Cause Flag Register (pINT_F16T23) Register name Address Bit 16-bit timer 2-3 0040283 (B) interrupt cause flag register (pINT_F16T23) D7 D6 D5-4 D3 D2 D1-0 Name F16TC3 F16TU3 - F16TC2 F16TU2 - Function 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved Setting 1 Occurred Init. R/W 0 Not occurred - 1 Occurred 0 Not occurred - X X - X X - Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 F16TC3: 16-bit Timer 3 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 3 comparison A interrupt cause status. D6 F16TU3: 16-bit Timer 3 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 3 comparison B interrupt cause status. D[5:4] Reserved D3 F16TC2: 16-bit Timer 2 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 2 comparison A interrupt cause status. D2 F16TU2: 16-bit Timer 2 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 2 comparison B interrupt cause status. D[1:0] Reserved IV-2-46 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40284: 16-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F16T45) Register name Address Bit 16-bit timer 4-5 0040284 (B) interrupt cause flag register (pINT_F16T45) D7 D6 D5-4 D3 D2 D1-0 Name F16TC5 F16TU5 - F16TC4 F16TU4 - Function 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved Setting 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - Init. R/W X X - X X - I Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 F16TC5: 16-bit Timer 5 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 5 comparison A interrupt cause status. D6 F16TU5: 16-bit Timer 5 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 5 comparison B interrupt cause status. D[5:4] Reserved D3 F16TC4: 16-bit Timer 4 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 4 comparison A interrupt cause status. IV D2 F16TU4: 16-bit Timer 4 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 4 comparison B interrupt cause status. ITC D[1:0] Reserved S1C33401 TECHNICAL MANUAL EPSON IV-2-47 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40285: 8-bit Timer 0-3 Interrupt Cause Flag Register (pINT_F8T03) Register name Address Bit 8-bit timer 0-3 0040285 (B) interrupt cause flag register (pINT_F8T03) D7-4 D3 D2 D1 D0 Name - F8TU3 F8TU2 F8TU1 F8TU0 Function reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow Setting Init. R/W - 1 Occurred 0 Not occurred - X X X X Remarks - 0 when being read. R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D[7:4] Reserved D3 F8TU3: 8-bit Timer 3 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 3 underflow interrupt cause status. D2 F8TU2: 8-bit Timer 2 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 2 underflow interrupt cause status. D1 F8TU1: 8-bit Timer 1 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 1 underflow interrupt cause status. D0 F8TU0: 8-bit Timer 0 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 0 underflow interrupt cause status. IV-2-48 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40286: Serial I/F Ch.0-1 Interrupt Cause Flag Register (pINT_FSIF01) Register name Address Bit 0040286 Serial I/F (B) Ch.0-1 interrupt cause flag register (pINT_FSIF01) D7-6 D5 D4 D3 D2 D1 D0 Name - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 Function reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error Setting - 1 Occurred 0 Not occurred Init. R/W - X X X X X X I Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D[7:6] Reserved D5 FSTX1: SIF Ch.1 Transmit Buffer Empty Cause-of-Interrupt Flag Indicates the SIF Ch.1 transmit buffer empty interrupt cause status. D4 FSRX1: SIF Ch.1 Receive Buffer Full Cause-of-Interrupt Flag Indicates the SIF Ch.1 receive buffer full interrupt cause status. D3 FSERR1: SIF Ch.1 Receive Error Cause-of-Interrupt Flag Indicates the SIF Ch.1 receive error interrupt cause status. IV D2 FSTX0: SIF Ch.0 Transmit Buffer Empty Cause-of-Interrupt Flag Indicates the SIF Ch.0 transmit buffer empty interrupt cause status. ITC D1 FSRX0: SIF Ch.0 Receive Buffer Full Cause-of-Interrupt Flag Indicates the SIF Ch.0 receive buffer full interrupt cause status. D0 FSERR0: SIF Ch.0 Receive Error Cause-of-Interrupt Flag Indicates the SIF Ch.0 receive error interrupt cause status. S1C33401 TECHNICAL MANUAL EPSON IV-2-49 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40287: Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (pINT_FP47_FCT_FAD) Register name Address Bit Port input 4-7, 0040287 (B) RTC, A/D interrupt cause flag register (pINT_FP47_FCT _FAD) D7 D6 D5 D4 D3 D2 D1 D0 Name - FP7 FP6 FP5 FP4 FCTM FADE FADC Function reserved Port input 7 Port input 6 Port input 5 Port input 4 RTC A/D conversion completion A/D upper/lower limit Setting Init. R/W - 1 Occurred 0 Not occurred - X X X X X X X Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 Reserved D6 FP7: Port Input 7 Cause-of-Interrupt Flag Indicates the port input 7 interrupt cause status. D5 FP6: Port Input 6 Cause-of-Interrupt Flag Indicates the port input 6 interrupt cause status. D4 FP5: Port Input 5 Cause-of-Interrupt Flag Indicates the port input 5 interrupt cause status. D3 FP4: Port Input 4 Cause-of-Interrupt Flag Indicates the port input 4 interrupt cause status. D2 FCTM: RTC Cause-of-Interrupt Flag Indicates the RTC interrupt cause status. D1 FADE: A/D Conversion Completion Cause-of-Interrupt Flag Indicates the A/D conversion completion interrupt cause status. D0 FADC: A/D Upper/Lower Limit Cause-of-Interrupt Flag Indicates the A/D upper/lower limit interrupt cause status. IV-2-50 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40288: 8-bit Timer 4-5 Interrupt Cause Flag Register (pINT_F8T45) Register name Address 8-bit timer 4-5 0040288 (B) interrupt cause flag register (pINT_F8T45) Name Bit D7-2 - D1 D0 F8TU5 F8TU4 Function Setting reserved - 8-bit timer 5 underflow 8-bit timer 4 underflow 1 Occurred 0 Not occurred Init. R/W - - X X R/W R/W I Remarks 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D[7:2] Reserved D1 F8TU5: 8-bit Timer 5 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 5 underflow interrupt cause status. D0 F8TU4: 8-bit Timer 4 Underflow Cause-of-Interrupt Flag Indicates the 8-bit timer 4 underflow interrupt cause status. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-51 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40289: Serial I/F Ch.2-3 Interrupt Cause Flag Register (pINT_FSIF23) Register name Address Bit 0040289 Serial I/F (B) Ch.2-3 interrupt cause flag register (pINT_FSIF23) D7-6 D5 D4 D3 D2 D1 D0 Name - FSTX3 FSRX3 FSERR3 FSTX2 FSRX2 FSERR2 Function reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.3 receive error SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full SIF Ch.2 receive error Setting Init. R/W - 1 Occurred 0 Not occurred - X X X X X X Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D[7:6] Reserved D5 FSTX3: SIF Ch.3 Transmit Buffer Empty Cause-of-Interrupt Flag Indicates the SIF Ch.3 transmit buffer empty interrupt cause status. D4 FSRX3: SIF Ch.3 Receive Buffer Full Cause-of-Interrupt Flag Indicates the SIF Ch.3 receive buffer full interrupt cause status. D3 FSERR3: SIF Ch.3 Receive Error Cause-of-Interrupt Flag Indicates the SIF Ch.3 receive error interrupt cause status. D2 FSTX2: SIF Ch.2 Transmit Buffer Empty Cause-of-Interrupt Flag Indicates the SIF Ch.2 transmit buffer empty interrupt cause status. D1 FSRX2: SIF Ch.2 Receive Buffer Full Cause-of-Interrupt Flag Indicates the SIF Ch.2 receive buffer full interrupt cause status. D0 FSERR2: SIF Ch.2 Receive Error Cause-of-Interrupt Flag Indicates the SIF Ch.2 receive error interrupt cause status. IV-2-52 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40290: Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Request Register (pIDMAREQ_RP03_RHS_R16T0) Register name Address Bit Name Port input 0-3, 0040290 (B) HSDMA Ch.0-1, 16-bit timer 0 IDMA request register (pIDMAREQ_RP03 _RHS_R16T0) D7 D6 D5 D4 D3 D2 D1 D0 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 Function 16-bit timer 0 comparison A 16-bit timer 0 comparison B HSDMA Ch.1 HSDMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 Setting 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 R16TC0: 16-bit Timer 0 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 0 comparison A interrupt occurs or not. D6 R16TU0: 16-bit Timer 0 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 0 comparison B interrupt occurs or not. D5 RHDM1: HSDMA Ch.1 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the HSDMA Ch.1 interrupt occurs or not. D4 RHDM0: HSDMA Ch.0 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the HSDMA Ch.0 interrupt occurs or not. D3 RP3: Port Input 3 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 3 interrupt occurs or not. D2 RP2: Port Input 2 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 2 interrupt occurs or not. D1 RP1: Port Input 1 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 1 interrupt occurs or not. D0 RP0: Port Input 0 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 0 interrupt occurs or not. S1C33401 TECHNICAL MANUAL EPSON IV-2-53 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40291: 16-bit Timer 1-4 IDMA Request Register (pIDMAREQ_R16T14) Register name Address Bit Name 16-bit timer 1-4 0040291 (B) IDMA request register (pIDMAREQ _R16T14) D7 D6 D5 D4 D3 D2 D1 D0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 Function 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B Setting 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 R16TC4: 16-bit Timer 4 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 4 comparison A interrupt occurs or not. D6 R16TU4: 16-bit Timer 4 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 4 comparison B interrupt occurs or not. D5 R16TC3: 16-bit Timer 3 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 3 comparison A interrupt occurs or not. D4 R16TU3: 16-bit Timer 3 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 3 comparison B interrupt occurs or not. D3 R16TC2: 16-bit Timer 2 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 2 comparison A interrupt occurs or not. D2 R16TU2: 16-bit Timer 2 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 2 comparison B interrupt occurs or not. D1 R16TC1: 16-bit Timer 1 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 1 comparison A interrupt occurs or not. D0 R16TU1: 16-bit Timer 1 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 1 comparison B interrupt occurs or not. IV-2-54 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40292: 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Request Register (pIDMAREQ_R16T5_R8T_RSIF0) Register name Address Bit Name 0040292 16-bit timer 5, (B) 8-bit timer 0-3, serial I/F Ch.0 IDMA request register (pIDMAREQ_R16T5 _R8T_RSIF0) D7 D6 D5 D4 D3 D2 D1 D0 RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 Function SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B Setting 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 RSTX0: SIF Ch.0 Transmit Buffer Empty IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.0 transmit buffer empty interrupt occurs or not. D6 RSRX0: SIF Ch.0 Receive Buffer Full IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.0 receive buffer full interrupt occurs or not. D5 R8TU3: 8-bit Timer 3 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 3 underflow interrupt occurs or not. D4 R8TU2: 8-bit Timer 2 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 2 underflow interrupt occurs or not. D3 R8TU1: 8-bit Timer 1 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 1 underflow interrupt occurs or not. D2 R8TU0: 8-bit Timer 0 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 0 underflow interrupt occurs or not. D1 R16TC5: 16-bit Timer 5 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 5 comparison A interrupt occurs or not. D0 R16TU5: 16-bit Timer 5 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 5 comparison B interrupt occurs or not. S1C33401 TECHNICAL MANUAL EPSON IV-2-55 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40293: Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Request Register (pIDMAREQ_RSIF1_RAD_RP47) Register name Address Bit Serial I/F Ch.1, 0040293 (B) A/D, port input 4-7 IDMA request register (pIDMAREQ_RSIF1 _RAD_RP47) D7 D6 D5 D4 D3 D2 D1 D0 Name RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 Function Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D conversion completion SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full Setting 1 IDMA request 0 Interrupt request - 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 - 0 0 0 Remarks R/W R/W R/W R/W - 0 when being read. R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 RP7: Port Input 7 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 7 interrupt occurs or not. D6 RP6: Port Input 6 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 6 interrupt occurs or not. D5 RP5: Port Input 5 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 5 interrupt occurs or not. D4 RP4: Port Input 4 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 4 interrupt occurs or not. D3 Reserved D2 RADE: A/D Conversion Completion IDMA Request Bit Specifies whether to invoke IDMA when a cause of the A/D conversion completion interrupt occurs or not. D1 RSTX1: SIF Ch.1 Transmit Buffer Empty IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.1 transmit buffer empty interrupt occurs or not. D0 RSRX1: SIF Ch.1 Receive Buffer Full IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.1 receive buffer full interrupt occurs or not. IV-2-56 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40294: Port Input 0-3, HSDMA Ch.0-1, 16-bit Timer 0 IDMA Enable Register (pIDMAEN_DEP03_DEHS_DE16T0) Register name Address Bit Port input 0-3, 0040294 (B) HSDMA Ch.0-1, 16-bit timer 0 IDMA enable register (pIDMAEN_DEP03 _DEHS_DE16T0) D7 D6 D5 D4 D3 D2 D1 D0 Name DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 Function 16-bit timer 0 comparison A 16-bit timer 0 comparison B HSDMA Ch.1 HSDMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 Setting 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DE16TC0: 16-bit Timer 0 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 0 comparison A interrupt. D6 DE16TU0: 16-bit Timer 0 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 0 comparison B interrupt. D5 DEHDM1: HSDMA Ch.1 IDMA Enable Bit Enables or disables the IDMA request by a cause of the HSDMA Ch.1 interrupt. IV D4 DEHDM0: HSDMA Ch.0 IDMA Enable Bit Enables or disables the IDMA request by a cause of the HSDMA Ch.0 interrupt. ITC D3 DEP3: Port Input 3 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 3 interrupt. D2 DEP2: Port Input 2 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 2 interrupt. D1 DEP1: Port Input 1 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 1 interrupt. D0 DEP0: Port Input 0 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 0 interrupt. S1C33401 TECHNICAL MANUAL EPSON IV-2-57 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40295: 16-bit Timer 1-4 IDMA Enable Register (pIDMAEN_DE16T14) Register name Address Bit 16-bit timer 1-4 0040295 (B) IDMA enable register (pIDMAEN _DE16T14) D7 D6 D5 D4 D3 D2 D1 D0 Name DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 Function 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B Setting 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DE16TC4: 16-bit Timer 4 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 4 comparison A interrupt. D6 DE16TU4: 16-bit Timer 4 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 4 comparison B interrupt. D5 DE16TC3: 16-bit Timer 3 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 3 comparison A interrupt. D4 DE16TU3: 16-bit Timer 3 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 3 comparison B interrupt. D3 DE16TC2: 16-bit Timer 2 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 2 comparison A interrupt. D2 DE16TU2: 16-bit Timer 2 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 2 comparison B interrupt. D1 DE16TC1: 16-bit Timer 1 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 1 comparison A interrupt. D0 DE16TU1: 16-bit Timer 1 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 1 comparison B interrupt. IV-2-58 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40296: 16-bit Timer 5, 8-bit Timer 0-3, Serial I/F Ch.0 IDMA Enable Register (pIDMAEN_DE16T5_DE8T_DESIF0) Register name Address Bit 0040296 16-bit timer 5, (B) 8-bit timer 0-3, serial I/F Ch.0 IDMA enable register (pIDMAEN_DE16T5 _DE8T_DESIF0) D7 D6 D5 D4 D3 D2 D1 D0 Name DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 Function SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B Setting 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DESTX0: SIF Ch.0 Transmit Buffer Empty IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.0 transmit buffer empty interrupt. D6 DESRX0: SIF Ch.0 Receive Buffer Full IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.0 receive buffer full interrupt. D5 DE8TU3: 8-bit Timer 3 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 3 underflow interrupt. IV D4 DE8TU2: 8-bit Timer 2 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 2 underflow interrupt. ITC D3 DE8TU1: 8-bit Timer 1 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 1 underflow interrupt. D2 DE8TU0: 8-bit Timer 0 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 0 underflow interrupt. D1 DE16TC5: 16-bit Timer 5 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 5 comparison A interrupt. D0 DE16TU5: 16-bit Timer 5 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 5 comparison B interrupt. S1C33401 TECHNICAL MANUAL EPSON IV-2-59 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40297: Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Enable Register (pIDMAEN_DESIF1_DEAD_DEP47) Register name Address Bit Name Serial I/F Ch.1, 0040297 (B) A/D, port input 4-7 IDMA enable register (pIDMAEN_DESIF1 _DEAD_DEP47) D7 D6 D5 D4 D3 D2 D1 D0 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Function Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D conversion completion SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full Setting 1 IDMA enabled Init. R/W 0 0 0 0 - 0 0 0 0 IDMA disabled - 1 IDMA enabled 0 IDMA disabled Remarks R/W R/W R/W R/W - 0 when being read. R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DEP7: Port Input 7 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 7 interrupt. D6 DEP6: Port Input 6 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 6 interrupt. D5 DEP5: Port Input 5 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 5 interrupt. D4 DEP4: Port Input 4 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 4 interrupt. D3 Reserved D2 DEADE: A/D Conversion Completion IDMA Enable Bit Enables or disables the IDMA request by a cause of the A/D conversion completion interrupt. D1 DESTX1: SIF Ch.1 Transmit Buffer Empty IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.1 transmit buffer empty interrupt. D0 DESRX1: SIF Ch.1 Receive Buffer Full IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.1 receive buffer full interrupt. IV-2-60 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x40298: HSDMA Ch.0-1 Trigger Set-up Register (pHSDMA_HTGR1) 0x40299: HSDMA Ch.2-3 Trigger Set-up Register (pHSDMA_HTGR2) Register name Address Bit Name HSDMA Ch.0-1 0040298 (B) trigger set-up register (pHSDMA_HTGR1) D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSDMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 HSDMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 HSDMA Ch.3 trigger set-up HSDMA Ch.2-3 0040299 (B) trigger set-up register (pHSDMA_HTGR2) D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 S1C33401 TECHNICAL MANUAL Function HSDMA Ch.2 trigger set-up EPSON Setting 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E Software trigger #DMAREQ1 input (falling edge) #DMAREQ1 input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Port 9 input Port 13 input Software trigger #DMAREQ0 input (falling edge) #DMAREQ0 input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion Port 8 input Port 12 input Software trigger #DMAREQ3 input (falling edge) #DMAREQ3 input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 7 compare B 16-bit timer 7 compare A SI/F Ch.3 Rx buffer full SI/F Ch.3 Tx buffer empty A/D conversion completion Port 11 input Port 15 input Software trigger #DMAREQ2 input (falling edge) #DMAREQ2 input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 6 compare B 16-bit timer 6 compare A SI/F Ch.2 Rx buffer full SI/F Ch.2 Tx buffer empty A/D conversion completion Port 10 input Port 14 input Init. R/W 0 0 0 0 R/W 0 0 0 0 R/W 0 0 0 0 R/W I Remarks IV ITC 0 0 0 0 R/W IV-2-61 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) These registers are used to select a trigger source for invoking each HSDMA channel. Table IV.2.7.2 HSDMA Trigger Source Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Ch.0 trigger source Software trigger #DMAREQ0 input (falling edge) #DMAREQ0 input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A Serial I/F Ch.0 Rx buffer full Serial I/F Ch.0 Tx buffer empty A/D conversion completion Port 8 input Port 12 input Ch.1 trigger source Software trigger #DMAREQ1 input (falling edge) #DMAREQ1 input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A Serial I/F Ch.1 Rx buffer full Serial I/F Ch.1 Tx buffer empty A/D conversion completion Port 9 input Port 13 input Ch.2 trigger source Software trigger #DMAREQ2 input (falling edge) #DMAREQ2 input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 6 compare B 16-bit timer 6 compare A Serial I/F Ch.2 Rx buffer full Serial I/F Ch.2 Tx buffer empty A/D conversion completion Port 10 input Port 14 input Ch.3 trigger source Software trigger #DMAREQ3 input (falling edge) #DMAREQ3 input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 7 compare B 16-bit timer 7 compare A Serial I/F Ch.3 Rx buffer full Serial I/F Ch.3 Tx buffer empty A/D conversion completion Port 11 input Port 15 input (Default: 0000) By selecting a cause of interrupt with the HSDMA trigger set-up bit, the HSDMA channel is invoked when the selected cause of interrupt occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable register, IDMA request register, interrupt priority register) do not affect this invocation. The interrupt request to the CPU by the cause of interrupt that invokes HSDMA is output two clocks (PCLK) after the HSDMA request, so the DMA transfer and interrupt handling are performed concurrently when the CPU runs with the instructions in the cache. However, when the interrupt handler contains an instruction that accesses a peripheral circuit, the execution of the instruction is pending until the DMA transfer is completed since the bus is used by the HSDMA. Before HSDMA can be invoked by the occurrence of a cause of interrupt, it is necessary that DMA be enabled on the HSDMA side by setting the control register for HSDMA transfer. For details about HSDMA, refer to Section III.4, "High-Speed DMA (HSDMA)." IV-2-62 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4029A: HSDMA Software Trigger Register (pHSDMA_HSOFTTGR) Register name Address Bit Name 004029A D7-4 - HSDMA D3 HST3 (B) software D2 HST2 trigger register D1 HST1 (pHSDMA D0 HST0 _HSOFTTGR) Function reserved HSDMA Ch.3 software trigger HSDMA Ch.2 software trigger HSDMA Ch.1 software trigger HSDMA Ch.0 software trigger Setting - 1 Trigger 0 Invalid Init. R/W - 0 0 0 0 - W W W W I Remarks 0 when being read. Each control bit in this register is used to start a HSDMA transfer. 1 (W): Trigger 0 (W): Has no effect 0 (R): Always 0 when read (default) Writing 1 to HSTx generates a trigger pulse that starts a DMA transfer. HSTx is effective only when software trigger is selected as the trigger source of the HSDMA channel using a HSDMA trigger set-up register (0x40298 or 0x40299). D[7:4] Reserved D3 HST3: HSDMA Ch.3 Software Trigger Starts a DMA transfer using the HSDMA Ch.3. D2 HST2: HSDMA Ch.2 Software Trigger Starts a DMA transfer using the HSDMA Ch.2. D1 HST1: HSDMA Ch.1 Software Trigger Starts a DMA transfer using the HSDMA Ch.1. D0 HST0: HSDMA Ch.0 Software Trigger Starts a DMA transfer using the HSDMA Ch.0. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-63 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4029B: 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Request Register (pIDMAREQ_R8T45_RSIF23) Register name Address Bit Name 8-bit timer 4-5 004029B D7-6 - D5 RSTX3 (B) serial I/F Ch.2-3 D4 RSRX3 IDMA request D3 RSTX2 register D2 RSRX2 (pIDMAREQ_R8T45 D1 R8TU5 _RSIF23) D0 R8TU4 Function reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full 8-bit timer 5 underflow 8-bit timer 4 underflow Setting - 1 IDMA request 0 Interrupt request Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D[7:6] Reserved D5 RSTX3: SIF Ch.3 Transmit Buffer Empty IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.3 transmit buffer empty interrupt occurs or not. D4 RSRX3: SIF Ch.3 Receive Buffer Full IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.3 receive buffer full interrupt occurs or not. D3 RSTX2: SIF Ch.2 Transmit Buffer Empty IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.2 transmit buffer empty interrupt occurs or not. D2 RSRX2: SIF Ch.2 Receive Buffer Full IDMA Request Bit Specifies whether to invoke IDMA when a cause of the SIF Ch.2 receive buffer full interrupt occurs or not. D1 R8TU5: 8-bit Timer 5 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 5 underflow interrupt occurs or not. D0 R8TU4: 8-bit Timer 4 Underflow IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 8-bit timer 4 underflow interrupt occurs or not. IV-2-64 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4029C: 8-bit Timer 4-5, Serial I/F Ch.2-3 IDMA Enable Register (pIDMAEN_DE8T45_DESIF23) Register name Address Bit Name 8-bit timer 4-5 004029C D7-6 - D5 DESTX3 (B) serial I/F Ch.2-3 D4 DESRX3 IDMA enable D3 DESTX2 register D2 DESRX2 (pIDMAEN_DE8T45 D1 DE8TU5 _DESIF23) D0 DE8TU4 Function reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full 8-bit timer 5 underflow 8-bit timer 4 underflow Setting - 1 IDMA enabled 0 IDMA disabled Init. R/W - 0 0 0 0 0 0 I Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D[7:6] Reserved D5 DESTX3: SIF Ch.3 Transmit Buffer Empty IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.3 transmit buffer empty interrupt. D4 DESRX3: SIF Ch.3 Receive Buffer Full IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.3 receive buffer full interrupt. D3 DESTX2: SIF Ch.2 Transmit Buffer Empty IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.2 transmit buffer empty interrupt. D2 DESRX2: SIF Ch.2 Receive Buffer Full IDMA Enable Bit Enables or disables the IDMA request by a cause of the SIF Ch.2 receive buffer full interrupt. D1 DE8TU5: 8-bit Timer 5 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 5 underflow interrupt. D0 DE8TU4: 8-bit Timer 4 Underflow IDMA Enable Bit Enables or disables the IDMA request by a cause of the 8-bit timer 4 underflow interrupt. S1C33401 TECHNICAL MANUAL EPSON IV ITC IV-2-65 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x4029F: Flag Set/Reset Method Select Register (pRST_RESET) Register name Address Flag set/reset method select register (pRST_RESET) 004029F (B) Bit Name Function Setting D7-3 - reserved - D2 DENONLY IDMA enable register set method 1 Set only 0 RD/WR selection D1 IDMAONLY IDMA request register set method 1 Set only 0 RD/WR selection D0 RSTONLY Cause-of-interrupt flag reset 1 Reset only 0 RD/WR method selection D[7:3] Reserved D2 DENONLY: IDMA Enable Register Set Method Select Bit Selects the method for setting the IDMA enable registers. 1 (R/W): Set-only method (default) 0 (R/W): Read/write method Init. R/W - 1 - R/W 1 R/W 1 R/W Remarks With the set-only method, IDMA enable bits are set by writing 1. The IDMA enable bits for which 0 has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA enable bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA enable bit that has been set to 1 is not reset by writing. The read/write method is selected by writing 0 to this bit. When this method is selected, IDMA enable bits can be read and written as for other registers. Therefore, the IDMA enable bit is reset by writing 0 and set by writing 1. In this case all IDMA enable bits for which 0 has been written are reset. Even in a read-modify-write operation, an IDMA enable bit can be reset by the hardware between the read and the write, so be careful when using this method. D1 IDMAONLY: IDMA Request Register Set Method Select Bit Selects the method for setting the IDMA request registers. 1 (R/W): Set-only method (default) 0 (R/W): Read/write method With the set-only method, IDMA request bits are set by writing 1. The IDMA request bits for which 0 has been written can neither be set nor reset. Therefore, this method ensures that only a specific IDMA request bit is set. However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit that has been set to 1 is not reset by writing. The read/write method is selected by writing 0 to this bit. When this method is selected, IDMA request bits can be read and written as for other registers. Therefore, the IDMA request bit is reset by writing 0 and set by writing 1. In this case all IDMA request bits for which 0 has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by the hardware between the read and the write, so be careful when using this method. D0 RSTONLY: Cause-of-Interrupt Flag Reset Method Select Bit Selects the method for resetting the cause-of-interrupt flags. 1 (R/W): Reset-only method (default) 0 (R/W): Read/write method With the reset-only method, the cause-of-interrupt flag is reset by writing 1. The cause-of-interrupt flags for which 0 has been written can neither be set nor reset. Therefore, this method ensures that only a specific cause-of-interrupt flag is reset. However, when using readmodify-write instructions (e.g., bset, bclr, or bnot), note that a cause-of-interrupt flag that has been set to 1 is reset by writing. This method cannot be used to set any cause-of-interrupt flag in the software application. The read/write method is selected by writing 0 to this bit. When this method is selected, cause-ofinterrupt flags can be read and written as for other registers. Therefore, the flag is reset by writing 0 and set by writing 1. In this case all cause-of-interrupt flags for which 0 has been written are reset. Even in a read-modify-write operation, a cause of interrupt can occur between read and write instructions, so be careful when using this method. IV-2-66 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A0: Port Input 8-9 Interrupt Priority Register (pINT_PR89L) Register name Address Bit Port input 8-9 00402A0 (B) interrupt priority register (pINT_PR89L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP9L2 PP9L1 PP9L0 - PP8L2 PP8L1 PP8L0 Function Setting reserved Port input 9 interrupt level - 0 to 7 reserved Port input 8 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP9L[2:0]: Port Input 9 Interrupt Level Bits Sets the priority level of the port input 9 interrupt. D3 Reserved D[2:0] PP8L[2:0]: Port Input 8 Interrupt Level Bits Sets the priority level of the port input 8 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-67 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A1: Port Input 10-11 Interrupt Priority Register (pINT_PR1011L) Register name Address Bit 00402A1 Port input (B) 10-11 interrupt priority register (pINT_PR1011L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP11L2 PP11L1 PP11L0 - PP10L2 PP10L1 PP10L0 Function Setting reserved Port input 11 interrupt level - 0 to 7 reserved Port input 10 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP11L[2:0]: Port Input 11 Interrupt Level Bits Sets the priority level of the port input 11 interrupt. D3 Reserved D[2:0] PP10L[2:0]: Port Input 10 Interrupt Level Bits Sets the priority level of the port input 10 interrupt. IV-2-68 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A2: Port Input 12-13 Interrupt Priority Register (pINT_PR1213L) Register name Address Bit 00402A2 Port input (B) 12-13 interrupt priority register (pINT_PR1213L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP13L2 PP13L1 PP13L0 - PP12L2 PP12L1 PP12L0 Function Setting reserved Port input 13 interrupt level - 0 to 7 reserved Port input 12 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP13L[2:0]: Port Input 13 Interrupt Level Bits Sets the priority level of the port input 13 interrupt. D3 Reserved D[2:0] PP12L[2:0]: Port Input 12 Interrupt Level Bits Sets the priority level of the port input 12 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-69 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A3: Port Input 14-15 Interrupt Priority Register (pINT_PR1415L) Register name Address Bit 00402A3 Port input (B) 14-15 interrupt priority register (pINT_PR1415L) D7 D6 D5 D4 D3 D2 D1 D0 Name - PP15L2 PP15L1 PP15L0 - PP14L2 PP14L1 PP14L0 Function Setting reserved Port input 15 interrupt level - 0 to 7 reserved Port input 14 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] PP15L[2:0]: Port Input 15 Interrupt Level Bits Sets the priority level of the port input 15 interrupt. D3 Reserved D[2:0] PP14L[2:0]: Port Input 14 Interrupt Level Bits Sets the priority level of the port input 14 interrupt. IV-2-70 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A4: 16-bit Timer 6-7 Interrupt Priority Register (pINT_P16T67) Register name Address Bit 16-bit timer 6-7 00402A4 (B) interrupt priority register (pINT_P16T67) D7 D6 D5 D4 D3 D2 D1 D0 Name - P16T72 P16T71 P16T70 - P16T62 P16T61 P16T60 Function Setting reserved 16-bit timer 7 interrupt level - 0 to 7 reserved 16-bit timer 6 interrupt level - 0 to 7 Init. R/W - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] P16T7[2:0]: 16-bit Timer 7 Interrupt Level Bits Sets the priority levels of the 16-bit timer 7 interrupt. D3 Reserved D[2:0] P16T6[2:0]: 16-bit Timer 6 Interrupt Level Bits Sets the priority levels of the 16-bit timer 6 interrupt. IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-71 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A5: 16-bit Timer 8-9 Interrupt Priority Register (pINT_P16T89) Register name Address Bit 16-bit timer 8-9 00402A5 (B) interrupt priority register (pINT_P16T89) D7 D6 D5 D4 D3 D2 D1 D0 Name - P16T92 P16T91 P16T90 - P16T82 P16T81 P16T80 Function Setting reserved 16-bit timer 9 interrupt level - 0 to 7 reserved 16-bit timer 8 interrupt level - 0 to 7 Init. R/W - X X X - X X X Remarks - 0 when being read. R/W - 0 when being read. R/W This register is used to set an interrupt priority level. (Default: indeterminate) The priority level can be set in the range of 0 to 7. If the level is set below the IL value of the PSR, no interrupt is generated. D7 Reserved D[6:4] P16T9[2:0]: 16-bit Timer 9 Interrupt Level Bits Sets the priority levels of the 16-bit timer 9 interrupt. D3 Reserved D[2:0] P16T8[2:0]: 16-bit Timer 8 Interrupt Level Bits Sets the priority levels of the 16-bit timer 8 interrupt. IV-2-72 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A6: Port Input 8-15 Interrupt Enable Register (pINT_EP815) Register name Address Bit Port input 8-15 00402A6 (B) interrupt enable register (pINT_EP815) D7 D6 D5 D4 D3 D2 D1 D0 Name EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 Function Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 Setting 1 Enabled 0 Disabled Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 EP15: Port Input 15 Enable Bit Enables or disables the port input 15 interrupt. D6 EP14: Port Input 14 Enable Bit Enables or disables the port input 14 interrupt. D5 EP13: Port Input 13 Enable Bit Enables or disables the port input 13 interrupt. D4 EP12: Port Input 12 Enable Bit Enables or disables the port input 12 interrupt. D3 EP11: Port Input 11 Enable Bit Enables or disables the port input 11 interrupt. D2 EP10: Port Input 10 Enable Bit Enables or disables the port input 10 interrupt. D1 EP9: Port Input 9 Enable Bit Enables or disables the port input 9 interrupt. D0 EP8: Port Input 8 Enable Bit Enables or disables the port input 8 interrupt. S1C33401 TECHNICAL MANUAL EPSON IV ITC IV-2-73 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A7: 16-bit Timer 6-7 Interrupt Enable Register (pINT_E16T67) Register name Address Bit Name D7 E16TC7 16-bit timer 6-7 00402A7 D6 E16TU7 (B) interrupt D5-4 - enable register D3 E16TC6 (pINT_E16T67) D2 E16TU6 D1-0 - Function 16-bit timer 7 comparison A 16-bit timer 7 comparison B reserved 16-bit timer 6 comparison A 16-bit timer 6 comparison B reserved Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - Init. R/W 0 0 - 0 0 - Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 E16TC7: 16-bit Timer 7 Comparison A Enable Bit Enables or disables the 16-bit timer 7 comparison A interrupt. D6 E16TU7: 16-bit Timer 7 Comparison B Enable Bit Enables or disables the 16-bit timer 7 comparison B interrupt. D[5:4] Reserved D3 E16TC6: 16-bit Timer 6 Comparison A Enable Bit Enables or disables the 16-bit timer 6 comparison A interrupt. D2 E16TU6: 16-bit Timer 6 Comparison B Enable Bit Enables or disables the 16-bit timer 6 comparison B interrupt. D[1:0] Reserved IV-2-74 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A8: 16-bit Timer 8-9 Interrupt Enable Register (pINT_E16T89) Register name Address Bit Name D7 E16TC9 16-bit timer 8-9 00402A8 D6 E16TU9 (B) interrupt D5-4 - enable register D3 E16TC8 (pINT_E16T89) D2 E16TU8 D1-0 - Function 16-bit timer 9 comparison A 16-bit timer 9 comparison B reserved 16-bit timer 8 comparison A 16-bit timer 8 comparison B reserved Setting 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - Init. R/W 0 0 - 0 0 - I Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register enables or disables an interrupt to the CPU. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set to 0. For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt enable register bit must be set for interrupt enable. D7 E16TC9: 16-bit Timer 9 Comparison A Enable Bit Enables or disables the 16-bit timer 9 comparison A interrupt. D6 E16TU9: 16-bit Timer 9 Comparison B Enable Bit Enables or disables the 16-bit timer 9 comparison B interrupt. D[5:4] Reserved D3 E16TC8: 16-bit Timer 8 Comparison A Enable Bit Enables or disables the 16-bit timer 8 comparison A interrupt. D2 E16TU8: 16-bit Timer 8 Comparison B Enable Bit Enables or disables the 16-bit timer 8 comparison B interrupt. D[1:0] Reserved IV ITC S1C33401 TECHNICAL MANUAL EPSON IV-2-75 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402A9: Port Input 8-15 Interrupt Cause Flag Register (pINT_FP815) Register name Address Bit Port input 8-15 00402A9 (B) interrupt cause flag register (pINT_FP815) D7 D6 D5 D4 D3 D2 D1 D0 Name FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 Function Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 Setting 1 Occurred Init. R/W 0 Not occurred X X X X X X X X Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 FP15: Port Input 15 Cause-of-Interrupt Flag Indicates the port input 15 interrupt cause status. D6 FP14: Port Input 14 Cause-of-Interrupt Flag Indicates the port input 14 interrupt cause status. D5 FP13: Port Input 13 Cause-of-Interrupt Flag Indicates the port input 13 interrupt cause status. D4 FP12: Port Input 12 Cause-of-Interrupt Flag Indicates the port input 12 interrupt cause status. D3 FP11: Port Input 11 Cause-of-Interrupt Flag Indicates the port input 11 interrupt cause status. D2 FP10: Port Input 10 Cause-of-Interrupt Flag Indicates the port input 10 interrupt cause status. D1 FP9: Port Input 9 Cause-of-Interrupt Flag Indicates the port input 9 interrupt cause status. D0 FP8: Port Input 8 Cause-of-Interrupt Flag Indicates the port input 8 interrupt cause status. IV-2-76 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AA: 16-bit Timer 6-7 Interrupt Cause Flag Register (pINT_F16T67) Register name Address Bit Name 16-bit timer 6-7 00402AA D7 F16TC7 D6 F16TU7 (B) interrupt cause D5-4 - flag register D3 F16TC6 (pINT_F16T67) D2 F16TU6 D1-0 - Function 16-bit timer 7 comparison A 16-bit timer 7 comparison B reserved 16-bit timer 6 comparison A 16-bit timer 6 comparison B reserved Setting 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - Init. R/W X X - X X - I Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 F16TC7: 16-bit Timer 7 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 7 comparison A interrupt cause status. D6 F16TU7: 16-bit Timer 7 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 7 comparison B interrupt cause status. D[5:4] Reserved D3 F16TC6: 16-bit Timer 6 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 6 comparison A interrupt cause status. IV D2 F16TU6: 16-bit Timer 6 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 6 comparison B interrupt cause status. ITC D[1:0] Reserved S1C33401 TECHNICAL MANUAL EPSON IV-2-77 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AB: 16-bit Timer 8-9 Interrupt Cause Flag Register (pINT_F16T89) Register name Address Bit Name 16-bit timer 8-9 00402AB D7 F16TC9 D6 F16TU9 (B) interrupt cause D5-4 - flag register D3 F16TC8 (pINT_F16T89) D2 F16TU8 D1-0 - Function 16-bit timer 9 comparison A 16-bit timer 9 comparison B reserved 16-bit timer 8 comparison A 16-bit timer 8 comparison B reserved Setting 1 Occurred Init. R/W 0 Not occurred - 1 Occurred 0 Not occurred - X X - X X - Remarks R/W R/W - 0 when being read. R/W R/W - 0 when being read. Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that has been set can be reset by writing. (Default: indeterminate) 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred When written using the reset-only method (default) 1 (W): Flag is reset 0 (W): Has no effect When written using the read/write method 1 (W): Flag is set 0 (W): Flag is reset See "Key Input, Port Input 0-3 Interrupt Cause Flag Register (0x40280)" for more information. D7 F16TC9: 16-bit Timer 9 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 9 comparison A interrupt cause status. D6 F16TU9: 16-bit Timer 9 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 9 comparison B interrupt cause status. D[5:4] Reserved D3 F16TC8: 16-bit Timer 8 Comparison A Cause-of-Interrupt Flag Indicates the 16-bit timer 8 comparison A interrupt cause status. D2 F16TU8: 16-bit Timer 8 Comparison B Cause-of-Interrupt Flag Indicates the 16-bit timer 8 comparison B interrupt cause status. D[1:0] Reserved IV-2-78 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AC: Port Input 8-15 IDMA Request Register (pIDMAREQ_RP815) Register name Address Bit Port input 8-15 00402AC (B) IDMA request register (pIDMAREQ _RP815) D7 D6 D5 D4 D3 D2 D1 D0 Name RP15 RP14 RP13 RP12 RP11 RP10 RP9 RP8 Function Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 Setting 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 RP15: Port Input 15 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 15 interrupt occurs or not. D6 RP14: Port Input 14 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 14 interrupt occurs or not. D5 RP13: Port Input 13 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 13 interrupt occurs or not. D4 RP12: Port Input 12 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 12 interrupt occurs or not. D3 RP11: Port Input 11 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 11 interrupt occurs or not. D2 RP10: Port Input 10 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 10 interrupt occurs or not. D1 RP9: Port Input 9 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 9 interrupt occurs or not. D0 RP8: Port Input 8 IDMA Request Bit Specifies whether to invoke IDMA when a cause of the port input 8 interrupt occurs or not. S1C33401 TECHNICAL MANUAL EPSON IV ITC IV-2-79 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AD: 16-bit Timer 6-9 IDMA Request Register (pIDMAREQ_R16T69) Register name Address Bit Name 16-bit timer 6-9 00402AD (B) IDMA request register (pIDMAREQ _R16T69) D7 D6 D5 D4 D3 D2 D1 D0 R16TC9 R16TU9 R16TC8 R16TU8 R16TC7 R16TU7 R16TC6 R16TU6 Function 16-bit timer 9 comparison A 16-bit timer 9 comparison B 16-bit timer 8 comparison A 16-bit timer 8 comparison B 16-bit timer 7 comparison A 16-bit timer 7 comparison B 16-bit timer 6 comparison A 16-bit timer 6 comparison B Setting 1 IDMA request 0 Interrupt request Init. R/W 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register specifies whether to invoke IDMA when a cause of interrupt occurs. When using the set-only method (default) 1 (R/W): IDMA request 0 (R/W): IDMA not invoked (default) When using the read/write method 1 (R/W): IDMA request 0 (R/W): Interrupt request If the bit is set to 1, IDMA is invoked when a cause of interrupt occurs, thereby performing a programmed data transfer. If the bit is set to 0, normal interrupt processing is performed, without invoking IDMA. For details on IDMA, refer to Section III.5, "Intelligent DMA (IDMA)." If interrupts are enabled on the IDMA side and the transfer counter reaches the terminal count of 0 after completion of DMA transfer, the IDMA request bit is reset to 0 and an interrupt request for the cause of interrupt that enabled IDMA invoking is generated. D7 R16TC9: 16-bit Timer 9 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 9 comparison A interrupt occurs or not. D6 R16TU9: 16-bit Timer 9 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 9 comparison B interrupt occurs or not. D5 R16TC8: 16-bit Timer 8 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 8 comparison A interrupt occurs or not. D4 R16TU8: 16-bit Timer 8 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 8 comparison B interrupt occurs or not. D3 R16TC7: 16-bit Timer 7 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 7 comparison A interrupt occurs or not. D2 R16TU7: 16-bit Timer 7 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 7 comparison B interrupt occurs or not. D1 R16TC6: 16-bit Timer 6 Comparison A IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 6 comparison A interrupt occurs or not. D0 R16TU6: 16-bit Timer 6 Comparison B IDMA Request Bit Specifies whether to invoke IDMA when a cause of the 16-bit timer 6 comparison B interrupt occurs or not. IV-2-80 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AE: Port Input 8-15 IDMA Enable Register (pIDMAEN_DEP815) Register name Address Bit Port input 8-15 00402AE (B) IDMA enable register (pIDMAEN_DEP815) D7 D6 D5 D4 D3 D2 D1 D0 Name DEP15 DEP14 DEP13 DEP12 DEP11 DEP10 DEP9 DEP8 Function Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 Setting 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DEP15: Port Input 15 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 15 interrupt. D6 DEP14: Port Input 14 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 14 interrupt. D5 DEP13: Port Input 13 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 13 interrupt. D4 DEP12: Port Input 12 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 12 interrupt. D3 DEP11: Port Input 11 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 11 interrupt. D2 DEP10: Port Input 10 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 10 interrupt. D1 DEP9: Port Input 9 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 9 interrupt. D0 DEP8: Port Input 8 IDMA Enable Bit Enables or disables the IDMA request by a cause of the port input 8 interrupt. S1C33401 TECHNICAL MANUAL EPSON IV ITC IV-2-81 IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) 0x402AF: 16-bit Timer 6-9 IDMA Enable Register (pIDMAEN_DE16T69) Register name Address Bit 16-bit timer 6-9 00402AF (B) IDMA enable register (pIDMAEN _DE16T69) D7 D6 D5 D4 D3 D2 D1 D0 Name DE16TC9 DE16TU9 DE16TC8 DE16TU8 DE16TC7 DE16TU7 DE16TC6 DE16TU6 Function 16-bit timer 9 comparison A 16-bit timer 9 comparison B 16-bit timer 8 comparison A 16-bit timer 8 comparison B 16-bit timer 7 comparison A 16-bit timer 7 comparison B 16-bit timer 6 comparison A 16-bit timer 6 comparison B Setting 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W R/W R/W Each bit in this register enables or disables the IDMA request by a cause of interrupt. When using the set-only method (default) 1 (R/W): IDMA-request enabled 0 (R): IDMA-request disabled (default) 0 (W): Has no effect When using the read/write method 1 (R/W): IDMA-request enabled 0 (R/W): IDMA-request disabled If a bit of this register is set to 1, the IDMA request by the cause of interrupt is enabled. If the register bit is set to 0, the IDMA request is disabled. D7 DE16TC9: 16-bit Timer 9 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 9 comparison A interrupt. D6 DE16TU9: 16-bit Timer 9 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 9 comparison B interrupt. D5 DE16TC8: 16-bit Timer 8 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 8 comparison A interrupt. D4 DE16TU8: 16-bit Timer 8 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 8 comparison B interrupt. D3 DE16TC7: 16-bit Timer 7 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 7 comparison A interrupt. D2 DE16TU7: 16-bit Timer 7 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 7 comparison B interrupt. D1 DE16TC6: 16-bit Timer 6 Comparison A IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 6 comparison A interrupt. D0 DE16TU6: 16-bit Timer 6 Comparison B IDMA Enable Bit Enables or disables the IDMA request by a cause of the 16-bit timer 6 comparison B interrupt. IV-2-82 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) IV.2.8 Precautions I * In SLEEP mode, there is a time lag between input of an interrupt signal for wakeup and the start of the clock supply to the ITC, so a delay will occur until the ITC sets the cause-of-interrupt flag. Therefore, no interrupt will occur if the interrupt signal is deasserted before the clock is supplied to the ITC, as the cause-of-interrupt flag in the ITC is not set. Furthermore, additional time is needed for the CPU to accept the interrupt request from the ITC, the CPU may execute a few instructions that follow the slp instruction before it starts the interrupt processing. The same problem may occur when the CPU wakes up from SLEEP mode by NMI. No interrupt will occur if the #NMI signal is deasserted before the clock is supplied, as the NMI flag is not set. * If the cause of interrupt used to restart from the standby mode has been set to invoke the IDMA, the IDMA is started up by that interrupt. If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the next interrupt request is generated. * As the C33 ADV Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However, since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each interrupt system can only be set for up to 8. * When the reset-only method is used to reset the cause-of-interrupt flag (by writing 1), if a read-modify-write instruction (e.g., bset, bclr, or bnot) is executed, the other cause-of-interrupt flags at the same address that have been set to 1 are reset by a write. This requires caution. In cases when the read/write method is used to reset the cause-of-interrupt flag (by writing 0), all cause-of-interrupt flags for which 0 has been written are reset. When a read-modify-write operation is performed, a cause of interrupt may occur between reads and writes, so be careful when using this method. The same applies to the set-only method and read/write method for the IDMA request and IDMA enable registers. * After an initial reset, the cause-of-interrupt flags and interrupt priority registers all become indeterminate. To prevent unwanted interrupts or IDMA requests from being generated inadvertently, be sure to reset these flags and registers in the software application. * To prevent another interrupt from being generated for the same cause again after generation of an interrupt, be sure to reset the cause-of-interrupt flag before enabling interrupts and setting the PSR again or executing the reti instruction. * When the reti instruction is executed immediately after a cause-of-interrupt flag is reset, the CPU may execute an interrupt processing again even if no interrupt to be processed next is occurred. This problem is caused by a time lag from execution of an instruction (ld, etc.) for resetting the cause-of-interrupt flag until the interrupt request signal to the CPU is negated, which is occurred due to the pipeline processing in the ITC to generate interrupt requests to the CPU using PCLK and the bus-processing pipeline. Care should be taken especially when PCLK is slower than CCLK. To avoid this problem, after the cause-of-interrupt flag is reset (by writing with the ld or other instruction), read the interrupt cause flag register before executing the reti instruction. This makes it possible to return from the interrupt handler routine after the interrupt request to the CPU is negated. S1C33401 TECHNICAL MANUAL EPSON IV-2-83 IV ITC IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC) THIS PAGE IS BLANK. IV-2-84 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG IV.3 OSC3 Oscillator Circuit, PLL, and SSCG I IV.3.1 Overview of the System Clock Generator Unit The system clock generator unit consists of an OSC3 oscillator circuit, PLL, and SSCG, and is positioned outside the core block. The OSC3 oscillator circuit generates the main clock for the C33 ADV chip. PLL generates the system source clock from the OSC3 clock by multiplying it by 1 to 16. Note that PLL is bypassed when the OSC3 clock is used directly as the system source clock, thus reducing current consumed on the chip. The Spread Spectrum Clock Generator (SSCG) is a circuit used to reduce Electromagnetic Interference (EMI) noise by spreading spectrum (or performing SS modulation) for the PLL output clock. OSC3 OSC3 oscillator Divider (1/1, 1/2, 1/4, 1/8 OSC4 PLL OSC1 OSC2 SSCG System clock source selector RTC (OSC1 oscillator) CCLK PCLK CMU Figure IV.3.1.1 Configuration of the System Clock Generator Unit The Clock Management Unit (CMU) of the C33 ADV Core Block controls the OSC3 oscillator circuit, PLL, and SSCG. This section mainly describes the circuit configuration of the OSC3 oscillator circuit. For details of clock control and the control registers, see Section II.3, "Clock Management Unit (CMU)." S1C33401 TECHNICAL MANUAL EPSON IV-3-1 IV OSC3 IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG IV.3.2 OSC3 Oscillator Circuit The OSC3 oscillator circuit generates the main clock with which to operate the CPU and internal peripheral circuits. IV.3.2.1 Input/Output Pins of the OSC3 Oscillator Circuit Table IV.3.2.1.1 lists the input/output pins of the OSC3 oscillator circuit. Table IV.3.2.1.1 Input/Output Pins of the OSC3 Oscillator Circuit Pin name I/O OSC3 OSC4 I O Function OSC3 oscillator input pin: Crystal/ceramic oscillator or external clock input OSC3 oscillator output pin: Crystal/ceramic oscillator (left open when using external clock input) IV.3.2.2 Structure of the Oscillator Circuit The OSC3 oscillator circuit accommodates a crystal/ceramic oscillator and external clock input. The core voltage VDD supplies power for this circuit. Figure IV.3.2.2.1 shows the structure of the OSC3 oscillator circuit. CG3 OSC3 X'tal3 or Ceramic CD3 VSS Rd VDD VSS fOSC3 Rf Oscillation circuit control signal SLEEP control OSC4 OSC3 fOSC3 External clock Oscillation circuit control signal SLEEP control N.C. OSC4 (1) Crystal/ceramic oscillation circuit (2) External clock input Figure IV.3.2.2.1 OSC3 Oscillator Circuit For use as a crystal or ceramic oscillator circuit, connect a crystal (X'tal3) or ceramic resonator and a feedback resistor (Rf), two capacitors (CG3, CD3) and, if necessary, a drain resistor (Rd) to the OSC3 and OSC4 pins and VSS. To use an external clock, leave the OSC4 pin open and input a VDD-level clock (with a 50% duty cycle) to the OSC3 pin. The range of oscillation frequencies is 5 to 33 MHz when using the internal oscillator circuit, and 2 to 33 MHz when using external clock input. For details of oscillation characteristics and external clock input characteristics, see "Electrical Characteristics." IV.3.2.3 Oscillation Control CMU register control bit SOSC3 (D1/0x48360) is used to control OSC3 oscillation. SOSC3: High-speed Oscillation (OSC3) On/Off Control Bit in the Core System Clock Control Register (D1/0x48360) Setting this control bit to 0 causes the OSC3 oscillator circuit to stop; setting it to 1 causes the OSC3 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. When initially reset, this bit is set to 1 for enabling OSC3 oscillation. For the OSC3 oscillation control procedure and other details of clock control, see Section II.3, "Clock Management Unit (CMU)." Notes: * The Core System Clock Control Register (0x48360) is write-protected. Write protection for this register and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure that the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. * When the oscillator is made to start oscillating by setting SOSC3 (D1/0x48360) from 0 to 1, a finite time is required until oscillation stabilizes (see "Electrical Characteristics"). To prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses. IV-3-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG IV.3.3 PLL I PLL generates the system source clock from the OSC3 clock input by multiplying it. PLL input clock frequency: 5 to 150 MHz PLL output clock frequency: 20 to 200 MHz Multiplying factor: 1 to 16 To reduce the current consumed on the chip, PLL may be turned off to use the OSC3 clock directly as the system source clock. IV.3.3.1 Control of PLL PLL can be controlled as described below by using the CMU registers. For details of PLL control, see Section II.3, "Clock Management Unit (CMU)." 1. PLL On/Off PLL is turned on by setting PLLPOWR (D0/0x40184) to 1, and turned off by setting this bit to 0. PLLPOWR: PLL On/Off Control Bit in the PLL Control Register 1 (D0/0x40184) 2. Multiplying factor The PLL multiplying factor can be set to x1 to x16 by using PLLN[3:0] (D[7:4]/0x40184). PLLN[3:0]: PLL Multiplication Rate Setup Bits in the PLL Control Register 1 (D[7:4]/0x40184) PLL output clock frequency = PLL input clock frequency (OSC3) x multiplying factor 3. Other PLL settings Moreover, the PLL circuit constants described below must be set depending on the output clock frequency. V-Divider To ensure that the frequency obtained by <output clock frequency x W>, fVCO, falls within 100 to 400 MHz, use PLLV[1:0] (D[3:2]/0x40184) to set the value of W. IV PLLV[1:0]: PLL V-Divider Setup Bits in the PLL Control Register 1 (D[3:2]/0x40184) VCO Kv constant (VC value) According to the fVCO range obtained by <output clock frequency x W>, use PLLVC[3:0] (D[7:4]/0x40185) to set the VCO Kv circuit constant (VC value). PLLVC[3:0]: PLL VCO Kv Setup Bits in the PLL Control Register 2 (D[7:4]/0x40185) LPF resistance value (RS value) According to the input clock (OSC3) frequency, use PLLRS[3:0] (D[3:0]/0x40185) to set the LPF resistance value (RS value) of PLL. PLLRS[3:0]: PLL LPF Resistance Setup Bits in the PLL Control Register 2 (D[3:0]/0x40185) Table IV.3.3.1.1 Example PLL Settings PLL input clock (OSC3) PLL output clock PLLN[3:0] PLLV[1:0] PLLVC[3:0] PLLRS[3:0] 5 MHz 65 MHz 60 MHz 40 MHz 60 MHz 40 MHz 60 MHz 40 MHz 66 MHz x13, 0b1100 x12, 0b1011 x8, 0b0111 x6, 0b0101 x4, 0b0011 x3, 0b0010 x2, 0b0001 x2, 0b0001 0b01 0b01 0b10 0b01 0b10 0b01 0b10 0b01 0b0010 0b0001 0b0010 0b0001 0b0010 0b0001 0b0010 0b0010 0b1010 0b1010 0b1010 0b1010 0b1010 0b1000 0b1000 0b1000 10 MHz 20 MHz 33 MHz S1C33401 TECHNICAL MANUAL EPSON IV-3-3 OSC3 IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG Notes: * Immediately after PLL is made to start by setting PLLPOWR (D0/0x40184) to 1, a finite wait time is required for the output clock to stabilize (e.g., 200 s, typ.). (For details, see "Electrical Characteristics.") When switching the system clock source to PLL, consider this wait time after turning PLL on. * The multiplying factor that can be set varies with the upper-limit operating frequency and OSC3 oscillation frequency of the specific C33 ADV model used. Make sure that the upperlimit operating frequency is not exceeded. * Before setting up PLL, always make sure that PLL is turned off (PLLPOWR (D0/0x40184) = 0), and that the system clock source is other than PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0- 2). Altering PLL settings while the system is being clocked by PLL may cause the system to operate erratically. * PLL control registers are write-protected. Write protection for these registers and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure that the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. IV.3.3.2 Power Supply for PLL The power for PLL is supplied from the PLLVDD and PLLVSS pins (separately from the core power supply) to prevent the effects of noise. Make sure that the following voltages are supplied to the respective pins. PLLVDD pin: Supply VDD level voltage. PLLVSS pin: Connect to VSS level. For pin assignments, see Section I.3, "Pin Description." IV-3-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG IV.3.4 SSCG I The Spread Spectrum Clock Generator (SSCG) is a circuit used to reduce Electromagnetic Interference (EMI) noise by spreading the spectrum (or performing SS modulation) for the PLL output clock signal. The SS modulation is effective for all operating clocks for the core and peripheral circuits (except the RTC that uses the OSC1 clock) when the PLL output clock has been selected as the system clock source and only this case has the effect of reducing noise. Note: When the OSC3 or OSC1 clock is selected as the system clock source, SS modulation is not performed for the operating clock (system clock). About spectrum spread (SS modulation) The SSCG performs SS modulation by adjusting the width of the high section of the input clock. This adjustment is made by increasing or reducing the set value of the internal delay adjust circuit of the SSCG. The maximum width within which the set value is changed constitutes the maximum frequency change width. The relevant control register is used to set the upper-limit value of this width. In the SSCG, an interval timer adjusts the interval at which the set value changes. The relevant control register is also used to set this interval (frequency change cycle). + Input clock cycle Maximum frequency change width 0 - Frequency change cycle IV Figure IV.3.4.1 SS Modulation The SSCG can be controlled as described below by using the CMU registers. For details of SSCG control, see Section II.3, "Clock Management Unit (CMU)." 1. SSCG On/Off The SSCG is turned on by setting SSMCON (D0/0x40187) to 1, and turned off (bypassed) by setting this bit to 0. SSMCON: SS Macro On/Off Control Bit in the SS Macro Control Register 1 (D0/0x40187) 2. SS modulation parameter settings The upper-limit value of the maximum frequency change width and interval at which the frequency changes or frequency change cycle described in "About spectrum spread (SS modulation)" above are set by using SSMCIDT[3:0] (D[3:0]/0x40188) and SSMCITM[3:0] (D[7:4]/0x40188), respectively. SSMCIDT[3:0]: SS Macro Maximum Frequency Change Width Setting Bits in the SS Macro Control Register 2 (D[3:0]/0x40188) SSMCITM[3:0]: SS Macro Interval Timer Setting Bits in the SS Macro Control Register 2 (D[7:4]/0x40188) Notes: * The SS macro control registers are write-protected. Write protection for these registers and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure that the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. * The SSCG is effective only when the PLL is selected as the system clock source. Furthermore, the SSCG control registers cannot be set when the PLL is inactive. S1C33401 TECHNICAL MANUAL EPSON IV-3-5 OSC3 IV C33 ADV BASIC PERIPHERAL BLOCK: OSC3 OSCILLATOR CIRCUIT, PLL, AND SSCG IV.3.5 Precautions When the OSC3 oscillator circuit and PLL are turned on, a finite time is required for oscillation and the output clock to stabilize (see "Electrical Characteristics"). To prevent erratic system operation, do not use the generated clock until this oscillation/output clock stabilization time elapses. IV-3-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4 Prescaler (PSC) I IV.4.1 Configuration of Prescaler The prescaler divides the PCLK clock (generated by the CMU from the OSC3 clock, PLL output clock or OSC1 clock) to generate the clocks for the internal peripheral circuits. The prescaler division ratio can be selected for each peripheral circuit in a program. A clock control circuit to control the clock supply to each peripheral circuit is also included. The following are the peripheral circuits that use the output clock: * 16-bit timers 9 to 0 The prescaler clock is used as the count clock. * 8-bit timers 5 to 0 (and serial interface) The prescaler clock is used as the count clock. * A/D converter The prescaler clock is used as the A/D conversion clock. Figure IV.4.1.1 shows the configuration of the prescaler. For details on control of each peripheral circuit, refer to each corresponding section in this manual. PSCCLK PCLKSEL[1:0] OSCSEL[1:0] OSC3 clock PLL output clock OSC1 clock Selector PCLK Divider 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 CMU Division ratio select register Prescaler output control Selector 16-bit timers 9-0 8-bit timers 5-0 A/D converter Control register 1/2 IV PSC_CLK (port output) PPOTS[4:0] Figure IV.4.1.1 Configuration of Prescaler and Clock Control Circuit S1C33401 TECHNICAL MANUAL EPSON PSC IV-4-1 IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.2 Source Clock The prescaler uses the peripheral circuit clock (PCLK) generated by the CMU as the source clock. For details on how to set and control PCLK, see Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the source clock PCLK is supplied to the prescaler with default settings. It can be turned off using PSCCLK (D7/0x40180) to reduce the amount of power consumed on the chip if all the 16-bit timers, 8-bit timers, serial interface and A/D converter are not used. PSCCLK: Prescaler Clock Control Bit in the Peripheral Clock Control Register 1 (D7/0x40180) Setting PSCCLK (D7/0x40180) to 0 (1 by default) turns off the PCLK clock supply to the prescaler. Clock state in standby mode The supply of PCLK stops depending on type of standby mode. HALT mode: PCLK is supplied the same way as in normal mode. HALT2 mode: PCLK is supplied the same way as in normal mode. SLEEP mode: The supply of PCLK stops. Therefore, the prescaler also stops operating when in SLEEP modes. IV-4-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.3 Selecting Division Ratio and Output Control for Prescaler I The prescaler has registers for selecting the division ratio and clock output control separately for each peripheral circuit described above, allowing each peripheral circuit to be controlled. The prescaler's division ratio can be selected from among eight ratios set for each peripheral circuit through the use of the division ratio selection bits. The divided clock is output to the corresponding peripheral circuit by writing 1 to the clock control bit. Table IV.4.3.1 Control Bits of the Clock Control Registers Peripheral circuit Division ratio selection bit 16-bit timer 0 16-bit timer 1 16-bit timer 2 16-bit timer 3 16-bit timer 4 16-bit timer 5 16-bit timer 6 16-bit timer 7 16-bit timer 8 16-bit timer 9 8-bit timer 0 8-bit timer 1 8-bit timer 2 8-bit timer 3 8-bit timer 4 8-bit timer 5 A/D converter P16TS0[2:0] P16TS1[2:0] P16TS2[2:0] P16TS3[2:0] P16TS4[2:0] P16TS5[2:0] P16TS6[2:0] P16TS7[2:0] P16TS8[2:0] P16TS9[2:0] P8TS0[2:0] P8TS1[2:0] P8TS2[2:0] P8TS3[2:0] P8TS4[2:0] P8TS5[2:0] PSAD[2:0] Clock control bit (D[2:0]/0x40147) 1 (D[2:0]/0x40148) 1 (D[2:0]/0x40149) 1 (D[2:0]/0x4014A) 1 (D[2:0]/0x4014B) 1 (D[2:0]/0x4014C) 1 (D[2:0]/0x40141) 1 (D[2:0]/0x40142) 1 (D[2:0]/0x40143) 1 (D[2:0]/0x40144) 1 (D[2:0]/0x4014D) 2 (D[6:4]/0x4014D) 3 (D[2:0]/0x4014E) 4 (D[6:4]/0x4014E) 2 (D[2:0]/0x40145) 5 (D[6:4]/0x40145) 2 (D[2:0]/0x4014F) 2 P16TON0 (D3/0x40147) P16TON1 (D3/0x40148) P16TON2 (D3/0x40149) P16TON3 (D3/0x4014A) P16TON4 (D3/0x4014B) P16TON5 (D3/0x4014C) P16TON6 (D3/0x40141) P16TON7 (D3/0x40142) P16TON8 (D3/0x40143) P16TON9 (D3/0x40144) P8TON0 (D3/0x4014D) P8TON1 (D7/0x4014D) P8TON2 (D3/0x4014E) P8TON3 (D7/0x4014E) P8TON4 (D3/0x40145) P8TON5 (D7/0x40145) PSONAD (D3/0x4014F) 1 to 5: See Table IV.4.3.2. Table IV.4.3.2 Division Ratio Bit setting 7 1 2 3 4 5 PCLK/4096 PCLK/256 PCLK/4096 PCLK/4096 PCLK/4096 6 5 PCLK/1024 PCLK/256 PCLK/64 PCLK/128 PCLK/2048 PCLK/1024 PCLK/2048 PCLK/256 PCLK/2048 PCLK/64 4 3 2 1 0 PCLK/64 PCLK/32 PCLK/512 PCLK/64 PCLK/32 PCLK/16 PCLK/16 PCLK/256 PCLK/16 PCLK/16 PCLK/4 PCLK/8 PCLK/128 PCLK/8 PCLK/8 PCLK/2 PCLK/4 PCLK/64 PCLK/4 PCLK/4 PCLK/1 PCLK/2 PCLK/32 PCLK/2 PCLK/2 Current consumption can be reduced by turning off the clock output to the peripheral circuits that are unused among those listed above. Note: In the following cases, the prescaler output clock may contain a hazard: * If, when a clock is output, its division ratio is changed * When the clock output is switched between on and off * When the PCLK clock is switched over Before performing these operations, make sure the 16-bit and 8-bit timers and the A/D converter are turned off. S1C33401 TECHNICAL MANUAL EPSON IV-4-3 IV PSC IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.4 Source Clock Output to 8-Bit Timer In addition to the divided clock, the prescaler can output the source clock directly to the 8-bit timer. This function can be selected for each 8-bit timer using P8TPCKx. P8TPCK0: 8-bit Timer 0 Clock Select Bit in the 8-bit Timer 0-3 Clock Select Register (D0/0x40146) P8TPCK1: 8-bit Timer 1 Clock Select Bit in the 8-bit Timer 0-3 Clock Select Register (D1/0x40146) P8TPCK2: 8-bit Timer 2 Clock Select Bit in the 8-bit Timer 0-3 Clock Select Register (D2/0x40146) P8TPCK3: 8-bit Timer 3 Clock Select Bit in the 8-bit Timer 0-3 Clock Select Register (D3/0x40146) P8TPCK4: 8-bit Timer 4 Clock Select Bit in the 8-bit Timer 4-5 Clock and Port Output Clock Select Register (D0/0x40140) P8TPCK5: 8-bit Timer 5 Clock Select Bit in the 8-bit Timer 4-5 Clock and Port Output Clock Select Register (D1/0x40140) When P8TPCKx is set to 1, the prescaler input clock (PCLK/1) is selected for the 8-bit timer x count clock. The clock output is controlled by P8TONx even if P8TPCKx is set to 1. P8TON0: 8-bit Timer 0 Clock Control Bit in the 8-bit Timer 0-1 Clock Control Register (D3/0x4014D) P8TON1: 8-bit Timer 1 Clock Control Bit in the 8-bit Timer 0-1 Clock Control Register (D7/0x4014D) P8TON2: 8-bit Timer 2 Clock Control Bit in the 8-bit Timer 2-3 Clock Control Register (D3/0x4014E) P8TON3: 8-bit Timer 3 Clock Control Bit in the 8-bit Timer 2-3 Clock Control Register (D7/0x4014E) P8TON4: 8-bit Timer 4 Clock Control Bit in the 8-bit Timer 4-5 Clock Control Register (D3/0x40145) P8TON5: 8-bit Timer 5 Clock Control Bit in the 8-bit Timer 4-5 Clock Control Register (D7/0x40145) When P8TPCKx is 0, the divided clock that is selected by P8TSx[2:0] will be output to the 8-bit timer x. At initial reset, P8TPCKx is set to 0 and P8TSx[2:0] becomes effective. P8TS0[2:0]: 8-bit Timer 0 Clock Division Ratio Select Bits in the 8-bit Timer 0-1 Clock Control Register (D[2:0]/0x4014D) P8TS1[2:0]: 8-bit Timer 1 Clock Division Ratio Select Bits in the 8-bit Timer 0-1 Clock Control Register (D[6:4]/0x4014D) P8TS2[2:0]: 8-bit Timer 2 Clock Division Ratio Select Bits in the 8-bit Timer 2-3 Clock Control Register (D[2:0]/0x4014E) P8TS3[2:0]: 8-bit Timer 3 Clock Division Ratio Select Bits in the 8-bit Timer 2-3 Clock Control Register (D[6:4]/0x4014E) P8TS4[2:0]: 8-bit Timer 4 Clock Division Ratio Select Bits in the 8-bit Timer 4-5 Clock Control Register (D[2:0]/0x40145) P8TS5[2:0]: 8-bit Timer 5 Clock Division Ratio Select Bits in the 8-bit Timer 4-5 Clock Control Register (D[6:4]/0x40145) IV-4-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.5 PSC_CLK External Output I The prescaler can output the PSC_CLK clock, which is the divided-by-2 clock of a prescaler clock selected in software, from an I/O port pin (depending on the S1C33 model). The PSC_CLK output pin is shared with a general-purpose I/O port or other peripheral circuit inputs/outputs, so that functionality in the initial state may be set to other than the PSC_CLK output. Before the PSC_CLK output signal assigned to this pin can be used, the function of this pin must be switched for the PSC_CLK output by setting the corresponding Port Function Select Register. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." The prescaler clock to be output should be selected using PPOTS[4:0] (D[6:2]/0x40140). PPOTS[4:0]: Port Output Clock Select Bits in the 8-bit Timer 4-5 Clock and Port Output Clock Select Register (D[6:2]/0x40140) Table IV.4.5.1 Selecting PSC_CLK PPOTS4 PPOTS3 PPOTS2 PPOTS1 PPOTS0 Output clock 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A/D converter clock 8-bit timer 5 clock 8-bit timer 4 clock 8-bit timer 3 clock 8-bit timer 2 clock 8-bit timer 1 clock 8-bit timer 0 clock 16-bit timer 9 clock 16-bit timer 8 clock 16-bit timer 7 clock 16-bit timer 6 clock 16-bit timer 5 clock 16-bit timer 4 clock 16-bit timer 3 clock 16-bit timer 2 clock 16-bit timer 1 clock 16-bit timer 0 clock IV At initial reset, the 16-bit timer 0 clock is selected. Notes: * The selected prescaler clock is divided by 2 before it is output from the port. For example, when a PCLK/64 of prescaler clock is selected, the PSC_CLK clock is output as PCLK/128. * To output PSC_CLK from the port, the output control bit for the selected prescaler clock must be set to 1. When the output control bit is set to 0, the PSC_CLK pin is fixed at a Low level. S1C33401 TECHNICAL MANUAL EPSON IV-4-5 PSC IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.6 Details of Control Registers Table IV.4.6.1 List of Prescaler Registers Address 0x00040140 0x00040141 0x00040142 0x00040143 0x00040144 0x00040145 0x00040146 0x00040147 0x00040148 0x00040149 0x0004014A 0x0004014B 0x0004014C 0x0004014D 0x0004014E 0x0004014F Function Register name Size 8-bit Timer 4-5 Clock and Port Output Clock Select 8 Selects 8-bit timer 4-5 count clock and port output clock. Register (pCLKSEL_T8_45) 16-bit Timer 6 Clock Control Register (pCLKCTL_T16_6) 8 Controls 16-bit timer 6 clock and selects division ratio. 16-bit Timer 7 Clock Control Register (pCLKCTL_T16_7) 8 Controls 16-bit timer 7 clock and selects division ratio. 16-bit Timer 8 Clock Control Register (pCLKCTL_T16_8) 8 Controls 16-bit timer 8 clock and selects division ratio. 16-bit Timer 9 Clock Control Register (pCLKCTL_T16_9) 8 Controls 16-bit timer 9 clock and selects division ratio. 8-bit Timer 4-5 Clock Control Register (pCLKCTL_T8_45) 8 Controls 8-bit timer 4-5 clock and selects division ratio. 8-bit Timer 0-3 Clock Select Register (pCLKSEL_T8) 8 Selects 8-bit timer 0-3 count clock. 16-bit Timer 0 Clock Control Register (pCLKCTL_T16_0) 8 Controls 16-bit timer 0 clock and selects division ratio. 16-bit Timer 1 Clock Control Register (pCLKCTL_T16_1) 8 Controls 16-bit timer 1 clock and selects division ratio. 16-bit Timer 2 Clock Control Register (pCLKCTL_T16_2) 8 Controls 16-bit timer 2 clock and selects division ratio. 16-bit Timer 3 Clock Control Register (pCLKCTL_T16_3) 8 Controls 16-bit timer 3 clock and selects division ratio. 16-bit Timer 4 Clock Control Register (pCLKCTL_T16_4) 8 Controls 16-bit timer 4 clock and selects division ratio. 16-bit Timer 5 Clock Control Register (pCLKCTL_T16_5) 8 Controls 16-bit timer 5 clock and selects division ratio. 8-bit Timer 0-1 Clock Control Register (pCLKCTL_T8_01) 8 Controls 8-bit timer 0-1 clock and selects division ratio. 8-bit Timer 2-3 Clock Control Register (pCLKCTL_T8_23) 8 Controls 8-bit timer 2-3 clock and selects division ratio. A/D Clock Control Register (pCLKCTL_AD) 8 Controls A/D converter clock and selects division ratio. The following describes each prescaler control register. The prescaler control registers are mapped in the 8-bit device area from 0x40140 to 0x4014F, and can be accessed in units of bytes. Note: When setting the prescaler control registers, be sure to write a 0, and not a 1, for all "reserved bits." IV-4-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x40140: 8-bit Timer 4-5 Clock and Port Output Clock Select Register (pCLKSEL_T8_45) Register name Address Bit Name 8-bit timer 4-5 0040140 (B) clock and port output clock select register (pCLKSEL_T8_45) D7 D6 D5 D4 D3 D2 - PPOTS4 PPOTS3 PPOTS2 PPOTS1 PPOTS0 reserved Port output clock select D1 D0 P8TPCK5 P8TPCK4 8-bit timer 5 clock select 8-bit timer 4 clock select Function Setting D7 Reserved D[6:2] PPOTS[4:0]: Port Output Clock Select Bits Selects a prescaler clock to be output as PSC_CLK. Init. R/W - PPOTS[4:0] 1xxxx 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 1 PCLK/1 1 PCLK/1 Output clock ADC T8-5 T8-4 T8-3 T8-2 T8-1 T8-0 T16-9 T16-8 T16-7 T16-6 T16-5 T16-4 T16-3 T16-2 T16-1 T16-0 0 Divided clk. 0 Divided clk. I Remarks - 0 0 0 0 0 - 0 when being read. R/W 0 0 R/W PCLK: see 0x48366 R/W Table IV.4.6.2 Setting PPOTS PPOTS4 PPOTS3 PPOTS2 PPOTS1 PPOTS0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D1 P8TPCK5: 8-bit Timer 5 Clock Select Bit Selects the 8-bit timer 5 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) D0 P8TPCK4: 8-bit Timer 4 Clock Select Bit Selects the 8-bit timer 4 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) S1C33401 TECHNICAL MANUAL EPSON Output clock A/D converter clock 8-bit timer 5 clock 8-bit timer 4 clock 8-bit timer 3 clock 8-bit timer 2 clock 8-bit timer 1 clock 8-bit timer 0 clock 16-bit timer 9 clock 16-bit timer 8 clock 16-bit timer 7 clock 16-bit timer 6 clock 16-bit timer 5 clock 16-bit timer 4 clock 16-bit timer 3 clock 16-bit timer 2 clock 16-bit timer 1 clock 16-bit timer 0 clock (Default: 0b00000) IV PSC IV-4-7 IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x40141-0x4014C: 16-bit Timer x Clock Control Registers (pCLKCTL_T16_x) Register name Address Bit Name 0040141 D7-4 - 16-bit timer x D3 P16TONx | clock control D2 P16TSx2 004014C register D1 P16TSx1 (B) (pCLKCTL_T16_x) D0 P16TSx0 Function Setting reserved 16-bit timer x clock control 16-bit timer x clock division ratio select Init. R/W - 1 On P16TSx[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 0 0 0 0 Remarks - 0 when being read. R/W R/W PCLK: see 0x48366 Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 9. 0x40141 0x40142 0x40143 0x40144 0x40147 0x40148 0x40149 0x4014A 0x4014B 0x4014C 16-bit Timer 6 Clock Control Register (pCLKCTL_T16_6) 16-bit Timer 7 Clock Control Register (pCLKCTL_T16_7) 16-bit Timer 8 Clock Control Register (pCLKCTL_T16_8) 16-bit Timer 9 Clock Control Register (pCLKCTL_T16_9) 16-bit Timer 0 Clock Control Register (pCLKCTL_T16_0) 16-bit Timer 1 Clock Control Register (pCLKCTL_T16_1) 16-bit Timer 2 Clock Control Register (pCLKCTL_T16_2) 16-bit Timer 3 Clock Control Register (pCLKCTL_T16_3) 16-bit Timer 4 Clock Control Register (pCLKCTL_T16_4) 16-bit Timer 5 Clock Control Register (pCLKCTL_T16_5) D[7:4] Reserved D3 P16TONx: 16-bit Timer x Clock Control Bit Controls the clock supply to 16-bit timer x. 1 (R/W): On 0 (R/W): Off (default) D[2:0] P16TSx[2:0]: 16-bit Timer x Clock Division Ratio Setup Bits Selects a division ratio to generate the 16-bit timer x clock. Table IV.4.6.3 Selecting Division Ratio IV-4-8 P16TSx2 P16TSx1 P16TSx0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 EPSON Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 (Default: 0b000) S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x40145: 8-bit Timer 4-5 Clock Control Register (pCLKCTL_T8_45) Register name Address Bit Name 8-bit timer 4-5 0040145 (B) clock control register (pCLKCTL_T8_45) D7 D6 D5 D4 P8TON5 P8TS52 P8TS51 P8TS50 8-bit timer 5 clock control 8-bit timer 5 clock division ratio select D3 D2 D1 D0 P8TON4 P8TS42 P8TS41 P8TS40 8-bit timer 4 clock control 8-bit timer 4 clock division ratio select Function Setting 1 On P8TS5[2:0] 111 110 101 100 011 010 001 000 1 On P8TS4[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 D7 P8TON5: 8-bit Timer 5 Clock Control Bit Controls the clock supply to 8-bit timer 5. 1 (R/W): On 0 (R/W): Off (default) D[6:4] P8TS5[2:0]: 8-bit Timer 5 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 5 clock. Init. R/W I Remarks 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 Table IV.4.6.4 Selecting Division Ratio P8TS52 P8TS51 P8TS50 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) D3 P8TON4: 8-bit Timer 4 Clock Control Bit Controls the clock supply to 8-bit timer 4. 1 (R/W): On 0 (R/W): Off (default) D[2:0] P8TS4[2:0]: 8-bit Timer 4 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 4 clock. IV PSC Table IV.4.6.5 Selecting Division Ratio S1C33401 TECHNICAL MANUAL P8TS42 P8TS41 P8TS40 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 EPSON Division ratio PCLK/4096 PCLK/2048 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) IV-4-9 IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x40146: 8-bit Timer 0-3 Clock Select Register (pCLKSEL_T8) Register name Address 8-bit timer 0-3 clock select register (pCLKSEL_T8) 0040146 (B) Bit D7-4 D3 D2 D1 D0 Name - P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0 Function reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection D[7:4] Reserved D3 P8TPCK3: 8-bit Timer 3 Clock Select Bit Selects the 8-bit timer 3 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) D2 P8TPCK2: 8-bit Timer 2 Clock Select Bit Selects the 8-bit timer 2 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) D1 P8TPCK1: 8-bit Timer 1 Clock Select Bit Selects the 8-bit timer 1 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) D0 P8TPCK0: 8-bit Timer 0 Clock Select Bit Selects the 8-bit timer 0 count clock. 1 (R/W): Prescaler input clock (PCLK/1) 0 (R/W): Divided clock (default) IV-4-10 EPSON Setting Init. R/W - 1 1 1 1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 0 0 0 0 Divided clk. Divided clk. Divided clk. Divided clk. - 0 0 0 0 Remarks - 0 when being read. R/W PCLK: see 0x48366 R/W R/W R/W S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x4014D: 8-bit Timer 0-1 Clock Control Register (pCLKCTL_T8_01) Register name Address Bit Name 8-bit timer 0-1 004014D (B) clock control register (pCLKCTL_T8_01) D7 D6 D5 D4 P8TON1 P8TS12 P8TS11 P8TS10 8-bit timer 1 clock control 8-bit timer 1 clock division ratio select D3 D2 D1 D0 P8TON0 P8TS02 P8TS01 P8TS00 8-bit timer 0 clock control 8-bit timer 0 clock division ratio select Function Setting 1 On P8TS1[2:0] 111 110 101 100 011 010 001 000 1 On P8TS0[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/1024 PCLK/512 PCLK/256 PCLK/128 PCLK/64 PCLK/32 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 D7 P8TON1: 8-bit Timer 1 Clock Control Bit Controls the clock supply to 8-bit timer 1. 1 (R/W): On 0 (R/W): Off (default) D[6:4] P8TS1[2:0]: 8-bit Timer 1 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 1 clock. Init. R/W I Remarks 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 Table IV.4.6.6 Selecting Division Ratio P8TS12 P8TS11 P8TS10 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Division ratio PCLK/4096 PCLK/2048 PCLK/1024 PCLK/512 PCLK/256 PCLK/128 PCLK/64 PCLK/32 (Default: 0b000) D3 P8TON0: 8-bit Timer 0 Clock Control Bit Controls the clock supply to 8-bit timer 0. 1 (R/W): On 0 (R/W): Off (default) D[2:0] P8TS0[2:0]: 8-bit Timer 0 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 0 clock. IV PSC Table IV.4.6.7 Selecting Division Ratio S1C33401 TECHNICAL MANUAL P8TS02 P8TS01 P8TS00 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 EPSON Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) IV-4-11 IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x4014E: 8-bit Timer 2-3 Clock Control Register (pCLKCTL_T8_23) Register name Address Bit Name 8-bit timer 2-3 004014E (B) clock control register (pCLKCTL_T8_23) D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 8-bit timer 3 clock control 8-bit timer 3 clock division ratio select D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 8-bit timer 2 clock control 8-bit timer 2 clock division ratio select Function Setting 1 On P8TS3[2:0] 111 110 101 100 011 010 001 000 1 On P8TS2[2:0] 111 110 101 100 011 010 001 000 Init. R/W 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/256 PCLK/64 PCLK/16 PCLK/8 PCLK/4 PCLK/2 D7 P8TON3: 8-bit Timer 3 Clock Control Bit Controls the clock supply to 8-bit timer 3. 1 (R/W): On 0 (R/W): Off (default) D[6:4] P8TS3[2:0]: 8-bit Timer 3 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 3 clock. Remarks 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 Table IV.4.6.8 Selecting Division Ratio P8TS32 P8TS31 P8TS30 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) D3 P8TON2: 8-bit Timer 2 Clock Control Bit Controls the clock supply to 8-bit timer 2. 1 (R/W): On 0 (R/W): Off (default) D[2:0] P8TS2[2:0]: 8-bit Timer 2 Clock Division Ratio Setup Bits Selects a division ratio to generate the 8-bit timer 2 clock. Table IV.4.6.9 Selecting Division Ratio IV-4-12 P8TS22 P8TS21 P8TS20 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 EPSON Division ratio PCLK/4096 PCLK/2048 PCLK/256 PCLK/64 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) 0x4014F: A/D Clock Control Register (pCLKCTL_AD) Register name Address Bit 004014F A/D clock (B) control register (pCLKCTL_AD) D7-4 D3 D2 D1 D0 Name - PSONAD PSAD2 PSAD1 PSAD0 Function Setting reserved A/D converter clock control A/D converter clock division ratio select - 1 On PSAD[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 D[7:4] Reserved D3 PSONAD: A/D Converter Clock Control Bit Controls the clock supply to the A/D converter. 1 (R/W): On 0 (R/W): Off (default) D[2:0] PSAD[2:0]: A/D Converter Clock Division Ratio Setup Bits Selects a division ratio to generate the A/D converter clock. I Init. R/W - 0 0 0 0 Remarks - 0 when being read. R/W R/W PCLK: see 0x48366 Table IV.4.6.10 Selecting Division Ratio PSAD2 PSAD1 PSAD0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 (Default: 0b000) IV PSC S1C33401 TECHNICAL MANUAL EPSON IV-4-13 IV C33 ADV BASIC PERIPHERAL BLOCK: PRESCALER (PSC) IV.4.7 Precautions * In the following cases, the prescaler output clock may contain a hazard: - If, during outputting of a clock, its division ratio is changed - When the clock output is switched between on and off - When the PCLK clock is switched over Before performing these operations, make sure the 16-bit and 8-bit timers and the A/D converter are turned off. * When the 16-bit and 8-bit timers and the A/D converter do not need to be operated, turn off the clock supply to those peripheral circuits. This helps to reduce current consumption. * Be aware that the serial interface stops operating when the prescaler is turned off (PSCCLK (D7/0x40180) = 0) as well as the peripheral circuits that use the prescaler output clock. PSCCLK: Prescaler Clock Control Bit in the Peripheral Clock Control Register 1 (D7/0x40180) IV-4-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5 8-Bit Timers (T8) I IV.5.1 Configuration of 8-bit Timer The Basic Peripheral Block contains six channels of 8-bit programmable timers (timers 0 to 5). Figure IV.5.1.1 shows the structure of the 8-bit timer. Prescaler 8-bit reload data register (RLDx) Reload Clock output Underflow signal output Underflow interrupt 8-bit down counter Underflow Data buffer (PTDx) Control circuit Data bus CMU Control registers Interrupt controller Figure IV.5.1.1 Structure of 8-bit Timer Each timer consists of an 8-bit presentable counter and can output a clock generated by the counter's underflow signal to the internal peripheral circuits or external devices. The output clock cycle can be selected from a wide range of cycles by setting the preset data that can be set in the software and the input clock in the prescaler. IV T8 S1C33401 TECHNICAL MANUAL EPSON IV-5-1 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.2 Output Pins of 8-bit Timers The underflow signals of 8-bit timers 0 to 5 can be output to external devices. Table IV.5.2.1 shows the pins that are used to output the underflow signals of the 8-bit timers to external devices. Table IV.5.2.1 Output Pins of 8-bit Timers Pin name T8UF0 T8UF1 T8UF2 T8UF3 T8UF4 T8UF5 I/O I/O I/O I/O I/O I/O I/O Function 8-bit timer 0 output 8-bit timer 1 output 8-bit timer 2 output 8-bit timer 3 output 8-bit timer 4 output 8-bit timer 5 output The T8UFx pin outputs the underflow signal generated by each 8-bit timer. The pulse width is equal to that of input clock of the 8-bit timer (prescaler output). Therefore, the pulse width varies according to the prescaler setting. Notes: * The list above indicates the output pins that the 8-bit timer can accommodate. Depending on the C33 ADV model used, all output pins may not be available. * The 8-bit timer output pins are shared with general-purpose I/O ports or other peripheral circuit inputs/outputs, so that functionality in the initial state may be set to other than the 8-bit timer output. Before the 8-bit timer output signals assigned to these pins can be used, the function of these pins must be switched for the 8-bit timer output by setting the corresponding Port Function Select Registers. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." IV-5-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.3 Uses of 8-bit Timers I The down-counter of the 8-bit timer cyclically outputs an underflow signal according to the preset data that is set in the software. This underflow signal is used to generate an interrupt request to the CPU or to control the internal peripheral circuits. In addition, this signal can be output to external devices. Furthermore, each 8-bit timer generates a clock from the underflow signal by dividing it by 2, and the resulting clock is output to a specific internal peripheral circuit. CPU interrupt request/IDMA invocation request (8-bit timers 0-5) Each timer's underflow condition can be used as a cause of interrupt to output an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set in the software. This cause of interrupt also can be used to invoke IDMA or HSDMA. Underflow signal output to external devices (8-bit timers 0-5) Each timer can output its underflow signal from the chip to the outside. This output can be used to control external devices. The output pin of each timer is described in the preceding section. Control of and clock supply to internal peripheral circuits The following describes the functions controlled by the underflow signal from the 8-bit timer and the internal peripheral circuits that use the timer's output clock. 8-bit timer 0 * A/D conversion start trigger The A/D converter enables a trigger for starting the A/D conversion to be selected from among four available types. One of these is the underflow signal of the 8-bit timer 0. This makes it possible to perform the A/D conversion at programmable intervals. To use this function, write 0b10 to the A/D converter control bit TS[1:0] (D[4:3]/0x48142) to select the 8-bit timer 0 as the trigger. TS[1:0]: A/D Conversion Trigger Select Bits in the A/D Trigger/Channel Select Register (D[4:3]/0x48142) IV 8-bit timer 1 The internal basic peripheral circuits do not use the 8-bit timer 1 underflow signal. 8-bit timer 2 * Clock supply to the Ch.0 serial interface When using the Ch.0 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit timer 2 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write 0 to the serial interface control bit SSCK0 (D2/0x401E3) to select the internal clock. SSCK0: Ch.0 Input Clock Select Bit in the Serial I/F Ch.0 Control Register (D2/0x401E3) 8-bit timer 3 * Clock supply to the Ch.1 serial interface When using the Ch.1 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit timer 3 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write 0 to the serial interface control bit SSCK1 (D2/0x401E8) to select the internal clock. SSCK1: Ch.1 Input Clock Select Bit in the Serial I/F Ch.1 Control Register (D2/0x401E8) S1C33401 TECHNICAL MANUAL EPSON IV-5-3 T8 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) 8-bit timer 4 * Clock supply to the Ch.2 serial interface When using the Ch.2 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit timer 4 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write 0 to the serial interface control bit SSCK2 (D2/0x401F3) to select the internal clock. SSCK2: Ch.2 Input Clock Select Bit in the Serial I/F Ch.2 Control Register (D2/0x401F3) 8-bit timer 5 * Clock supply to the Ch.3 serial interface When using the Ch.3 serial interface in the clock-synchronized master mode or the internal clock-based asynchronous mode, the output clock derived from the underflow signal of the 8-bit timer 5 by dividing it by 2 is supplied to the serial interface as its operating clock. This enables the transfer rate of the serial interface to be programmed. To use this function, write 0 to the serial interface control bit SSCK3 (D2/0x401F8) to select the internal clock. SSCK3: Ch.3 Input Clock Select Bit in the Serial I/F Ch.3 Control Register (D2/0x401F8) IV-5-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.4 8-bit Timer Operating Clock and Count Clock I The 8-bit timers use the peripheral circuit clock (PCLK) generated by the CMU as the operating clock. Furthermore, each timer uses the count clock supplied from the prescaler. Controlling the supply of the operating clock PCLK is supplied to the 8-bit timers with default settings. It can be turned off using T8CLK (D2/0x40180) to reduce the amount of power consumed on the chip if all the 8-bit timers are not used. T8CLK: 8-bit Timer Clock Control Bit in the Peripheral Clock Control Register 1 (D2/0x40180) Setting T8CLK (D2/0x40180) to 0 (1 by default) turns off the PCLK clock supply to the 8-bit timers. When the clock supply is turned off, the 8-bit timer control registers cannot be accessed. For details on how to set and control PCLK, refer to Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the count clock The count clock is supplied from the prescaler separately with the operating clock described above. Set the count clock for each 8-bit timer in the prescaler. For details on how to set and control the count clock, refer to Section IV.4, "Prescaler (PSC)." Clock state in standby mode The clock supply to the 8-bit timer stops depending on type of standby mode. HALT mode: The operating and count clocks are supplied the same way as in normal mode. HALT2 mode: The operating and count clocks are supplied the same way as in normal mode. SLEEP mode: The operating and count clock supply stops. Therefore, the 8-bit timer also stops operating when in SLEEP modes. IV T8 S1C33401 TECHNICAL MANUAL EPSON IV-5-5 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.5 Control and Operation of 8-bit Timer With the 8-bit timer, the following settings must first be made before it starts counting: 1. Setting the output pin (only when necessary) ... See Section IV.5.2. 2. Setting the count clock 3. Setting the preset data (initial counter value) 4. Setting the interrupt/IDMA/HSDMA ... See Section IV.5.7. Note: The 8-bit timers 0 through 5 all operate in the same way during counting, and the structure of their control registers is also the same. The control bit names are assigned the numerals 0 through 5 to denote the timer numbers. Since all these timers have common functions, timer numbers here are represented it is by `x' unless necessary to specify a timer number. Setting the count clock The 8-bit timer counter operates with the prescaler's output clock. The prescaler provides the clock select and output control registers for each 8-bit timer. Use these registers to set up the clock and to turn the clock supply on. For details on how to set and control the count clock, refer to Section IV.4, "Prescaler (PSC)." Notes: * The 8-bit timer operates only when the prescaler is operating. * Do not use a clock that is faster than the CPU operating clock as the 8-bit timer. * When setting a count clock, make sure the 8-bit timer is turned off. Setting preset data (initial counter value) Each timer has an 8-bit down-counter and a reload data register. The reload data register RLDx[7:0] (D[7:0]/ 0x40161 + 4*x) is used to set the initial value of the down-counter of each timer. RLDx[7:0]: 8-bit Timer x Reload Data Bits in the 8-bit Timer x Reload Data Register (D[7:0]/0x40161 + 4*x) The reload data registers can be read and written. At initial reset, the reload data registers are not initialized. The data written to this register is preset in the down-counter, and the counter starts counting down from the preset value. Data is thus preset in the down-counter in the following two cases: 1. When it is preset in the software Presetting in the software is performed using the preset control bit PSETx (D1/0x40160 + 4*x). When this bit is set to 1, the content of the reload data register is loaded into the down-counter at that point. PSETx: 8-bit Timer x Preset Bit in the 8-bit Timer x Control Register (D1/0x40160 + 4*x) 2. When the down-counter underflown during counting Since the reload data is preset in the down-counter upon underflow, its underflow cycle is determined by the value that is set in the reload data register. This underflow signal controls each function described in Section IV.5.3. Before starting the 8-bit timer, set the initial value in the reload data register and use PSETx (D1/0x40160 + 4*x) to preset the data in the down-counter. The underflow cycle is determined by the prescaler setting and the reload data. The relationship between these two parameters is expressed by the following equation: RLDx + 1 Under flow cycle = ------------ [sec.] fPSCIN x pdr fPSCIN: Prescaler input clock frequency [Hz] pdr: Prescaler division ratio set by P8TSx (see Section IV.4, "Prescaler (PSC).") RLDx: Set value of the RLDx register (0 to 255) IV-5-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) Timer RUN/STOP control I Each timer has PTRUNx (D0/0x40160 + 4*x) to control RUN/STOP. PTRUNx: 8-bit Timer x RUN/STOP Control Bit in the 8-bit Timer x Control Register (D0/0x40160 + 4*x) The timer is initiated to start counting down by writing 1 to PTRUNx (D0/0x40160 + 4*x). Writing 0 to PTRUNx (D0/0x40160 + 4*x) disables the count clock input and causes the timer to stop counting. This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the counter retains its count so that it can start counting again from that point. When the terminal count is reached and the counter underflows, the initial value is reloaded from the reload data register into the counter. When both the timer RUN/STOP control bit (PTRUNx (D0/0x40160 + 4*x)) and the timer preset bit (PSETx (D1/0x40160 + 4*x)) are set to 1 at the same time, the timer starts counting after presetting the reload register value into the counter. PTRUNx PSETx RLDx 0x10 0xA6 0xF3 Input clock PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 IV PTDx0 Timer initial setup Preset Reload and interrupt Figure IV.5.5.1 Basic Operation Timing of Counter Reading out counter data T8 The counter data is read out via PTDx[7:0] (D[7:0]/0x40162 + 4*x) data buffer. The counter data can be read out at any time. PTDx[7:0]: 8-bit Timer x Counter Data Bits in the 8-bit Timer x Counter Data Register (D[7:0]/0x40162 + 4*x) S1C33401 TECHNICAL MANUAL EPSON IV-5-7 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.6 Control of Underflow Signal and Clock Outputs Underflow signal output Each 8-bit timer can output its underflow signal to inside and outside the IC. Each timer provides PTUFOx (D3/0x40160 + 4*x) for controlling the underflow signal output. PTUFOx: 8-bit Timer x Underflow Signal Output Control Bit in the 8-bit Timer x Control Register (D3/0x40160 + 4*x) The underflow signal is output from 8-bit timer x when PTUFOx (D3/0x40160 + 4*x) is set to 0 (default). When 1 is written to PTUFOx (D3/0x40160 + 4*x), 8-bit timer x stops outputting the underflow signal (the signal is fixed at low level). The underflow signal can be output to external devices after the output pin (T8UFx) is set up. At cold reset, the output pins are set for general-purpose I/O or other functions. Before the underflow signal can be used, the function of these pins must be switched for the 8-bit timer output by setting the corresponding Port Function Select Registers. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." The output pin goes low when it is set for underflow signal output and outputs a high-level pulse every time an underflow occurs in the 8-bit timer after it starts counting. The underflow signal's pulse width (duration of the high period) is equal to that of the timer's input clock (prescaler's output). Count clock (from prescaler) Underflow signal PTUFOx External output (T8UFx pin) Figure IV.5.6.1 8-bit Timer Underflow Signal Output Waveform Note: To output the underflow signal of 8-bit timer 0 as the A/D conversion trigger signal, it is not necessary to control PTUFOx (D3/0x40160 + 4*x). Clock output Each 8-bit timer can output a clock generated from the underflow signal by dividing it by 2 to internal devices (serial interface). Each timer provides PTOUTx (D2/0x40160 + 4*x) for controlling the clock output. PTOUTx: 8-bit Timer x Clock Output Control Bit in the 8-bit Timer x Control Register (D2/0x40160 + 4*x) To output the clock, write 1 to PTOUTx (D2/0x40160 + 4*x). The clock output is turned off by writing 0 to PTOUTx (D2/0x40160 + 4*x), and the clock output signal is fixed at high. In the C33 ADV basic peripheral circuit, Ch.0 to Ch.3 of the serial interface use the output clocks of 8-bit timers 2 to 5 for generating the transfer clock, respectively. Control the timer output according to the serial interface to be used. The output clocks of 8-bit timers 0 and 1 are not used by the basic peripheral circuit. However, the control bits are provided so that user circuits or extended peripheral circuits can use the clocks. Underflow signal Underflow signal/2 PTOUTx Clock output (to serial interface) Figure IV.5.6.2 8-bit Timer Clock Output Waveform IV-5-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.7 8-bit Timer Interrupts and DMA I The 8-bit timer has a function to generate an interrupt based on the underflow state of the timer 0 to 5. The timing at which an interrupt is generated is shown in Figure IV.5.5.1. Control registers of the interrupt controller Table IV.5.7.1 shows the interrupt controller's control register provided for each timer. Table IV.5.7.1 Control Registers of Interrupt Controller Timer Cause-of-interrupt flag Interrupt enable register Interrupt priority register Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 F8TU0(D0/0x40285) F8TU1(D1/0x40285) F8TU2(D2/0x40285) F8TU3(D3/0x40285) F8TU4(D0/0x40288) F8TU5(D1/0x40288) E8TU0(D0/0x40275) E8TU1(D1/0x40275) E8TU2(D2/0x40275) E8TU3(D3/0x40275) E8TU4(D0/0x40278) E8TU5(D1/0x40278) P8TM[2:0](D[2:0]/0x40269) When the timer underflows, the corresponding cause-of-interrupt flag is set to 1. If the interrupt enable register bit corresponding to that cause-of-interrupt flag has been set to 1, an interrupt request is generated. An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to 0. The cause-of-interrupt flag is set to 1 whenever the timer underflows, regardless of how the interrupt enable register is set (even when it is set to 0). The interrupt priority register sets an interrupt priority level (0 to 7) for the six timers as one interrupt source. Within 8-bit timers, timer 0 has the highest priority and timer 5 the lowest. An interrupt request to the CPU is accepted on the condition that no other interrupt request of a higher priority has been generated. It is only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the timer interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the CPU. For details on these interrupt control registers and device operation when an interrupt has occurred, refer to Section IV.2, "Interrupt Controller (ITC)." Intelligent DMA The underflow interrupt cause of the timer 0 to 5 can invoke intelligent DMA (IDMA). This enables memoryto-memory DMA transfers to be performed cyclically. The following shows the IDMA channel numbers set to each timer: IDMA channel Timer 0: 0x13 Timer 1: 0x14 Timer 2: 0x15 Timer 3: 0x16 Timer 4: 0x20 Timer 5: 0x21 For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table IV.5.7.2 must be set to 1 in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table IV.5.7.2 Control Bits for IDMA Transfer Timer IDMA request bit IDMA enable bit Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 R8TU0(D2/0x40292) R8TU1(D3/0x40292) R8TU2(D4/0x40292) R8TU3(D5/0x40292) R8TU4(D0/0x4029B) R8TU5(D1/0x4029B) DE8TU0(D2/0x40296) DE8TU1(D3/0x40296) DE8TU2(D4/0x40296) DE8TU3(D5/0x40296) DE8TU4(D0/0x4029C) DE8TU5(D1/0x4029C) If the IDMA request and enable bits are set to 1, IDMA is invoked through generation of a cause of interrupt. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." S1C33401 TECHNICAL MANUAL EPSON IV-5-9 IV T8 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) High-speed DMA The underflow interrupt cause of the timer 0 to 3 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the timer 0 to 3: Table IV.5.7.3 HSDMA Trigger Set-up Bits Timer HSDMA channel Trigger set-up bits Timer 0 Timer 1 Timer 2 Timer 3 0 1 2 3 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) For HSDMA to be invoked, the trigger set-up bits should be set to 0b0101 in advance. Transfer conditions, etc. must also be set on the HSDMA side. If the 8-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the cause of interrupt. For details on HSDMA transfer, refer to Section III.4, "High-Speed DMA (HSDMA)." Trap vectors The trap vector addresses for individual underflow interrupt causes are set by default as shown below: Timer 0 underflow interrupt: 0x200000D0 Timer 1 underflow interrupt: 0x200000D4 Timer 2 underflow interrupt: 0x200000D8 Timer 3 underflow interrupt: 0x200000DC Timer 4 underflow interrupt: 0x20000120 Timer 5 underflow interrupt: 0x20000124 The base address of the trap table can be changed using the TTBR register. IV-5-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.8 Details of Control Registers I Table IV.5.8.1 List of 8-bit Timer Registers Address 0x00040160 0x00040161 0x00040162 0x00040164 0x00040165 0x00040166 0x00040168 0x00040169 0x0004016A 0x0004016C 0x0004016D 0x0004016E 0x00040174 0x00040175 0x00040176 0x00040178 0x00040179 0x0004017A Register name 8-bit Timer 0 Control Register (pT8_CTL0) 8-bit Timer 0 Reload Data Register (pT8_RLD0) 8-bit Timer 0 Counter Data Register (pT8_PTD0) 8-bit Timer 1 Control Register (pT8_CTL1) 8-bit Timer 1 Reload Data Register (pT8_RLD1) 8-bit Timer 1 Counter Data Register (pT8_PTD1 8-bit Timer 2 Control Register (pT8_CTL2) 8-bit Timer 2 Reload Data Register (pT8_RLD2) 8-bit Timer 2 Counter Data Register (pT8_PTD2) 8-bit Timer 3 Control Register (pT8_CTL3) 8-bit Timer 3 Reload Data Register (pT8_RLD3) 8-bit Timer 3 Counter Data Register (pT8_PTD3) 8-bit Timer 4 Control Register (pT8_CTL4) 8-bit Timer 4 Reload Data Register (pT8_RLD4) 8-bit Timer 4 Counter Data Register (pT8_PTD4) 8-bit Timer 5 Control Register (pT8_CTL5) 8-bit Timer 5 Reload Data Register (pT8_RLD5) 8-bit Timer 5 Counter Data Register (pT8_PTD5) Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Function Controls 8-bit timer 0 operation and clock output. Specifies 8-bit timer 0 reload data. 8-bit timer 0 counter data Controls 8-bit timer 1 operation and clock output. Specifies 8-bit timer 1 reload data. 8-bit timer 1 counter data Controls 8-bit timer 2 operation and clock output. Specifies 8-bit timer 2 reload data. 8-bit timer 2 counter data Controls 8-bit timer 3 operation and clock output. Specifies 8-bit timer 3 reload data. 8-bit timer 3 counter data Controls 8-bit timer 4 operation and clock output. Specifies 8-bit timer 4 reload data. 8-bit timer 4 counter data Controls 8-bit timer 5 operation and clock output. Specifies 8-bit timer 5 reload data. 8-bit timer 5 counter data The following describes each 8-bit timer control register. The 8-bit timer control registers are mapped in the 8-bit device area from 0x40160 to 0x4017A, and can be accessed in units of bytes. Note: When setting the 8-bit timer control registers, be sure to write a 0, and not a 1, for all "reserved bits." IV T8 S1C33401 TECHNICAL MANUAL EPSON IV-5-11 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) 0x40160-0x40178: 8-bit Timer x Control Registers (pT8_CTLx) Register name Address Bit 0040160 8-bit timer x | control register 0040178 (pT8_CTLx) (B) D7-4 D3 D2 D1 D0 Name - PTUFOx PTOUTx PSETx PTRUNx Function Setting reserved 8-bit timer x UF signal output control 8-bit timer x clock output control 8-bit timer x preset 8-bit timer x Run/Stop control - 1 1 1 1 Off On Preset Run 0 0 0 0 Init. R/W On Off Invalid Stop - 0 0 - 0 Remarks - 0 when being read. R/W R/W W 0 when being read. R/W Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 5. 0x40160 0x40164 0x40168 0x4016C 0x40174 0x40178 8-bit Timer 0 Control Register (pT8_CTL0) 8-bit Timer 1 Control Register (pT8_CTL1) 8-bit Timer 2 Control Register (pT8_CTL2) 8-bit Timer 3 Control Register (pT8_CTL3) 8-bit Timer 4 Control Register (pT8_CTL4) 8-bit Timer 5 Control Register (pT8_CTL5) D[7:4] Reserved D3 PTUFOx: 8-bit Timer x Underflow Signal Output Control Bit Controls the underflow signal output of each timer. 1 (R/W): Off 0 (R/W): On (default) The underflow signal of 8-bit timer x is output from the external output pin when PTUFOx is set to 0. It is necessary to set up the output pin for the underflow signal output (T8UFx) before the signal can be output. The clock output is turned off by writing 1 to PTUFOx, and the external output is fixed at 0. D2 PTOUTx: 8-bit Timer x Clock Output Control Bit Controls the clock output of each timer. 1 (R/W): On 0 (R/W): Off (default) The clock generated from the underflow signal by dividing it by 2 is output from each timer by writing 1 to PTOUTx. The clocks generated by timers 2 to 5 are used for the transfer clocks of the serial interface Ch.0 to Ch.3, respectively. The clock output is turned off by writing 0 to PTOUTx, and the clock output is fixed at 1. D1 PSETx: 8-bit Timer x Preset Bit Preset the reload data in the counter. 1 (W): Preset 0 (W): Has no effect 0 (R): Always 0 when read The reload data of RLDx[7:0] (D[7:0]/0x40161 + 4*x) is preset in the counter of timer x by writing 1 to PSETx. If the counter is preset when in a RUN state, the counter starts counting immediately after the reload data is preset. If the counter is preset when in a STOP state, the reload data that has been preset is retained. D0 PTRUNx: 8-bit Timer x Run/Stop Control Bit Controls the counter's RUN/STOP states. 1 (R/W): Run 0 (R/W): Stop (default) The counter of each timer starts counting down when 1 written to PTRUNx, and stops counting when 0 is written. While in a STOP state, the counter retains its count until it is preset with reload data or placed in a RUN state. When the state is changed from STOP to RUN, the counter can restart counting beginning with the retained count. IV-5-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) 0x40161-0x40179: 8-bit Timer x Reload Data Registers (pT8_RLDx) Register name Address Bit 0040161 | 0040179 (B) D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer x reload data register (pT8_RLDx) Name RLDx7 RLDx6 RLDx5 RLDx4 RLDx3 RLDx2 RLDx1 RLDx0 Function 8-bit timer x reload data RLDx7 = MSB RLDx0 = LSB Setting 0 to 255 Init. R/W X X X X X X X X I Remarks R/W Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 5. 0x40161 0x40165 0x40169 0x4016D 0x40175 0x40179 D[7:0] 8-bit Timer 0 Reload Data Register (pT8_RLD0) 8-bit Timer 1 Reload Data Register (pT8_RLD1) 8-bit Timer 2 Reload Data Register (pT8_RLD2) 8-bit Timer 3 Reload Data Register (pT8_RLD3) 8-bit Timer 4 Reload Data Register (pT8_RLD4) 8-bit Timer 5 Reload Data Register (pT8_RLD5) RLDx[7:0]: 8-bit Timer x Reload Data Set the initial counter value of each timer. (Default: indeterminate) The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with this data, which is used as the initial count. There are two cases in which the reload data is loaded into the counter: when data is preset after 1 is written to PSETx (D1/0x40160 + 4*x), or when data is automatically reloaded upon counter underflow. IV T8 S1C33401 TECHNICAL MANUAL EPSON IV-5-13 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) 0x40162-0x4017A: 8-bit Timer x Counter Data Registers (pT8_PTDx) Register name Address Bit 0040162 | 004017A (B) D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer x counter data register (pT8_PTDx) Name PTDx7 PTDx6 PTDx5 PTDx4 PTDx3 PTDx2 PTDx1 PTDx0 Function 8-bit timer x counter data PTDx7 = MSB PTDx0 = LSB Setting 0 to 255 Init. R/W X X X X X X X X Remarks R Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 5. 0x40162 0x40166 0x4016A 0x4016E 0x40176 0x4017A D[7:0] IV-5-14 8-bit Timer 0 Counter Data Register (pT8_PTD0) 8-bit Timer 1 Counter Data Register (pT8_PTD1) 8-bit Timer 2 Counter Data Register (pT8_PTD2) 8-bit Timer 3 Counter Data Register (pT8_PTD3) 8-bit Timer 4 Counter Data Register (pT8_PTD4) 8-bit Timer 5 Counter Data Register (pT8_PTD5) PTDx[7:0]: 8-bit Timer x Counter Data The 8-bit timer data can be read out from these bits. (Default: indeterminate) These bits function as buffers that retain the counter data when read out, enabling the data to be read out at any time. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) IV.5.9 Precautions I * The 8-bit timer operates only when the prescaler is operating. * Do not use a clock that is faster than the CPU operating clock for the 8-bit timer. * When setting a count clock, make sure the 8-bit timer is turned off. * Since the underflow interrupt condition and the timer output status are undefined after an initial reset, the counter initial value should be set to the 8-bit timer before resetting the cause-of-interrupt flag or turning the timer output on. * After an initial reset, the cause-of-interrupt flag (F8TUx) becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag in the software. * To prevent another interrupt from being generated again by the same factor after an interrupt has occurred, be sure to reset the cause-of-interrupt flag (F8TUx) before setting the PSR again or executing the reti instruction. F8TUx: 8-bit Timer x Underflow Interrupt Cause Flag in the 8-bit Timer 0-3 (4-5) Interrupt Cause Flag Register (0x40285, 0x40288) IV T8 S1C33401 TECHNICAL MANUAL EPSON IV-5-15 IV C33 ADV BASIC PERIPHERAL BLOCK: 8-BIT TIMERS (T8) THIS PAGE IS BLANK. IV-5-16 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6 16-Bit Timers (T16) I IV.6.1 Configuration of 16-bit Timer The Peripheral Block contains 10 systems of 16-bit programmable timers (timers 0 to 9). The following lists the main functions of the 16-bit timers. * Programmable count clocks using the prescaler * Event counter function using external clocks * Interrupt generation function with programmable interrupt cycles using the compare data registers * PWM output using the compare data registers * Supports fine mode and DA16 mode suitable for high-quality audio output using PWM Note: On the following pages, each timer is identified as timer x (x = 0 to 9). The functions and control register structures of 16-bit timers 0 to 9 are the same. Control bit names are assigned numerals `0' to `9' denoting timer numbers. Since explanations are common to all timers, timer numbers are represented by `x' unless it is necessary to specify a timer number. Figure IV.6.1.1 shows the structure of one channel of the 16-bit timer. Timer x Comparison register A buffer (CRBxA) Prescaler INCLx 16-bit comparison data register A (CRxA) Clock select circuit EXCLx External clock Comparator Comparison match A 16-bit up counter (TCx) TMx Clock output Control circuit Comparison A interrupt Comparison B interrupt Interrupt controller Comparator Comparison match B Data bus CMU IV 16-bit comparison data register B (CRxB) Comparison A Comparison B Comparison register B buffer (CRBxB) T16 Timer x control register Figure IV.6.1.1 Structure of 16-bit Timer In each timer, a 16-bit up-counter (TCx[15:0] (D[15:0]/0x48184 + 8*x)), as well as two 16-bit comparison data registers (CRxA[15:0] (D[15:0]/0x48180 + 8*x), CRxB[15:0] (D[15:0]/0x48182 + 8*x)) and their buffers (CRBxA, CRBxB), are provided. TCx[15:0]: 16-bit Timer x Counter Data Bits in the 16-bit Timer x Counter Data Register (D[15:0]/0x48184 + 8*x) CRxA[15:0]: 16-bit Timer x Comparison Data A Bits in the 16-bit Timer x Comparison Data A Setup Register (D[15:0]/0x48180 + 8*x) CRxB[15:0]: 16-bit Timer x Comparison Data B Bits in the 16-bit Timer x Comparison Data B Setup Register (D[15:0]/0x48182 + 8*x) The 16-bit counter can be reset to 0 by software and counts up using the prescaler output clock or an external signal input from the I/O port. The counter value can be read by software. S1C33401 TECHNICAL MANUAL EPSON IV-6-1 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) The comparison data registers A and B are used to store the data to be compared with the content of the upcounter. This register can be directly read and written. Furthermore, comparison data can be set via the comparison register buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match B signal or software (by writing 1 to PRESETx (D1/0x48186 + 8*x)). The software can select whether comparison data is written to the comparison data register or the buffer. PRESETx: 16-bit Timer x Reset Bit in the 16-bit Timer x Control Register (D1/0x48186 + 8*x) When the counter value matches to the content of each comparison data register, the comparator outputs a signal that controls the interrupt and the output signal. Thus the registers allow interrupt generating intervals and the timer's output clock frequency and duty ratio to be programmed. IV-6-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.2 I/O Pins of 16-bit Timers I Table IV.6.2.1 shows the input/output pins used for the 16-bit timers. Table IV.6.2.1 I/O Pins of 16-bit Timer Pin name EXCL0 EXCL1 EXCL2 EXCL3 EXCL4 EXCL5 EXCL6 EXCL7 EXCL8 EXCL9 TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8 TM9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function 16-bit timer 0 event counter input 16-bit timer 1 event counter input 16-bit timer 2 event counter input 16-bit timer 3 event counter input 16-bit timer 4 event counter input 16-bit timer 5 event counter input 16-bit timer 6 event counter input 16-bit timer 7 event counter input 16-bit timer 8 event counter input 16-bit timer 9 event counter input 16-bit timer 0 output 16-bit timer 1 output 16-bit timer 2 output 16-bit timer 3 output 16-bit timer 4 output 16-bit timer 5 output 16-bit timer 6 output 16-bit timer 7 output 16-bit timer 8 output 16-bit timer 9 output TMx (output pin of the 16-bit timer) This pin outputs a clock generated by the timer x. EXCLx (event counter input pin) When using the timer x as an event counter, input count pulses from an external source to this pin. Notes: * The list above indicates the input/output pins that the 16-bit timer can accommodate. Depending on the C33 ADV model used, all output pins may not be available. * The 16-bit timer input/output pins are shared with general-purpose I/O ports or other peripheral circuit inputs/outputs, so that functionality in the initial state may be set to other than the 16-bit timer output. Before the 16-bit timer input/output signals assigned to these pins can be used, the function of these pins must be switched for the 16-bit timer input/output by setting the corresponding Port Function Select Registers. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." S1C33401 TECHNICAL MANUAL EPSON IV-6-3 IV T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.3 Uses of 16-bit Timers The up-counters of the 16-bit timer cyclically output a comparison-match signal in accordance with the comparison data that are set in the software. This signal is used to generate an interrupt request to the CPU or control the internal peripheral circuits. A clock generated from the signal can also be output to external devices. CPU interrupt request/IDMA invocation request (timers 0 to 9) Each timer's comparison match (matching of counter and comparison data) can be used as a cause of interrupt to generate an interrupt request to the CPU. Therefore, an interrupt can be generated at an interval that is set in the software. Furthermore, this cause of interrupt can also be used to invoke IDMA or HSDMA. Clock output to external devices (timers 0 to 9) A clock generated from the comparison-match signal can be output from the chip to the outside. The clock cycle is determined by comparison data B, and the duty ratio is determined by comparison data A. This output can be used to control external devices. The output pin of each timer is described in the preceding section. A/D converter start trigger (timer 0) The A/D converter allows a trigger to start the A/D conversion to be selected from among four available types. One is the comparison-match B of the 16-bit timer 0. This makes it possible to perform the A/D conversion at programmable intervals. To use this function, write 0b01 to the A/D converter control bit TS[1:0] (D[4:3]/0x48142) to select the 16-bit timer 0 as the trigger. TS[1:0]: A/D Conversion Trigger Select Bits in the A/D Trigger/Channel Select Register (D[4:3]/0x48142) IV-6-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.4 16-bit Timer Operating Clock and Count Clock I The 16-bit timers use the peripheral circuit clock (PCLK) generated by the CMU as the operating clock. Furthermore, each timer uses the count clock supplied from the prescaler. Controlling the supply of the operating clock PCLK is supplied to the 16-bit timers with default settings. It can be turned off using T16CLK (D3/0x40180) to reduce the amount of power consumed on the chip if all the 16-bit timers are not used. T16CLK: 16-bit Timer Clock Control Bit in the Peripheral Clock Control Register 1 (D3/0x40180) Setting T16CLK (D3/0x40180) to 0 (1 by default) turns off the PCLK clock supply to the 16-bit timers. When the clock supply is turned off, the 16-bit timer control registers cannot be accessed. For details on how to set and control PCLK, refer to Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the count clock The count clock is supplied from the prescaler separately with the operating clock described above. Set the count clock for each 16-bit timer in the prescaler when the internal clock is used. For details on how to set and control the count clock, refer to Section IV.4, "Prescaler (PSC)." Clock state in standby mode The clock supply to the 16-bit timer stops depending on type of standby mode. HALT mode: The operating and count clocks are supplied the same way as in normal mode. HALT2 mode: The operating and count clocks are supplied the same way as in normal mode. SLEEP mode: The operating and count clock supply stops. Therefore, the 16-bit timer also stops operating when in SLEEP modes. IV T16 S1C33401 TECHNICAL MANUAL EPSON IV-6-5 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.5 Control and Operation of 16-bit Timer The following settings must first be made before the 16-bit timer starts counting: 1. Setting pins for input/output (only when necessary) ... See Section IV.6.2. 2. Setting count clock 3. Selecting comparison data register/buffer 4. Setting clock output conditions (signal active level, initial signal level, fine mode) ... See Section IV.6.6. 5. Setting comparison data 6. Setting interrupt/DMA ... See Section IV.6.7. Standard mode and advanced mode The 16-bit timer in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV 16-bit timer has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table IV.6.5.1 shows differences between standard mode and advanced mode. Table IV.6.5.1 Differences between Standard Mode and Advanced Mode Function Writing to the count data register Setting of the initial timer output level (high or low) DA16 function (DA16 registers) Multiple timer full-sync function Standard mode Advanced mode Disabled (read only) Disabled (depending on the OUTINVx set value) Cannot be used Not supported Enabled Enabled (can be specified using INITOLx) Can be used Supported (can be controlled using PAUSEx) To configure the 16-bit timer in advanced mode, set T16ADV (D0/0x481DE) to 1. The control registers/bits for the extended functions are enabled to write after this setting. At initial reset, T16ADV (D0/0x481DE) is set to 0 and the 16-bit timer enters standard mode. T16ADV: Standard Mode/Advanced Mode Select Bit in the 16-bit Timer STD/ADV Mode Select Register (D0/0x481DE) The following descriptions unless otherwise specified are common contents for both modes. The extended functions in advanced mode are explained assuming that T16ADV (D0/0x481DE) has been set to 1. Note: Standard or advanced mode currently set is applied to all the 16-bit timers. It cannot be selected for each timer individually. Setting the count clock The count clock for each timer can be selected from between an internal clock and an external clock. Select the input clock using CKSLx (D3/0x48186 + 8*x). CKSLx: 16-bit Timer x Input Clock Select Bit in the 16-bit Timer x Control Register (D3/0x48186 + 8*x) An external clock is selected by writing 1 to CKSLx (D3/0x48186 + 8*x), and the internal clock is selected by writing 0. At initial reset, CKSLx (D3/0x48186 + 8*x) is set for the internal clock. An external clock can be used for the timer for which the pin is set for input. * Internal clock When the internal clock is selected as a timer, the timer operates with the prescaler output clock. The prescaler provides the clock select and output control registers for each timer. Use these registers to set up the clock and to turn the clock supply on. For details on how to set and control the count clock, refer to Section IV.4, "Prescaler (PSC)." Notes: * When the internal clock is used, the 16-bit timer operates only when the prescaler is operating. * When setting a count clock, make sure the 16-bit timer is turned off. * External clock When using the timer as an event counter by supplying clock pulses from an external source, make sure the event cycle is at least two CPU operating clock cycles. IV-6-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) Selecting comparison data register/buffer I The comparison data registers A and B are used to store the data to be compared with the content of the upcounter. This register can be directly read and written. Furthermore, comparison data can be set via the comparison register buffer. In this case, the set value is loaded to the comparison data register when the counter is reset by the comparison match B signal or software (by writing 1 to PRESETx (D1/0x48186 + 8*x)). Select whether comparison data is written to the comparison data register or the buffer using SELCRBx (D5/ 0x48186 + 8*x). SELCRBx: 16-bit Timer x Comparison Register Buffer Enable Bit in the 16-bit Timer x Control Register (D5/0x48186 + 8*x) When 1 is written to SELCRBx (D5/0x48186 + 8*x), the comparison register buffer is selected and when 0 is written, the comparison data register is selected. At initial reset, the comparison data register is selected. Setting comparison data The timer contains two data comparators that allows the count data to be compared with given values. CRxA[15:0] (D[15:0]/0x48180 + 8*x) and CRxB[15:0] (D[15:0]/0x48182 + 8*x) are used to set these values. CRxA[15:0]: 16-bit Timer x Comparison Data A Bits in the 16-bit Timer x Comparison Data A Setup Register (D[15:0]/0x48180 + 8*x) CRxB[15:0]: 16-bit Timer x Comparison Data B Bits in the 16-bit Timer x Comparison Data B Setup Register (D[15:0]/0x48182 + 8*x) When SELCRBx (D5/0x48186 + 8*x) is set to 0, these registers allow direct reading/writing from/to the comparison data register. When SELCRBx is set to 1, these registers are used to read/write from/to the comparison register buffer. The content of the buffer is loaded to the comparison data register when the counter is reset. At initial reset, the comparison data registers/buffers are not initialized. The timer compares the comparison data register and count data and, when the two values are equal, generates a comparison match signal. This comparison match signal controls the clock output (TMx signal) to external devices, in addition to generating an interrupt. The comparison data B is also used to reset the counter. IV DA16 function (advanced mode) Advanced mode supports the DA16 function that divides a 16-bit data into 10 high-order bits and 6 low-order bits and writes them to the comparison data A registers (or buffers) of a two timer pair simultaneously. This makes it possible to reduce software load for using two 16-bit timers as a 16-bit D/A converter. Four DA16 registers are provided for this function. The following shows the correspondence between these registers and timers: (timer A and timer B) DA16 Ch.0 Register (0x481D0): timer 1 and timer 2 DA16 Ch.1 Register (0x481D2): timer 3 and timer 4 DA16 Ch.2 Register (0x481D4): timer 5 and timer 6 DA16 Ch.3 Register (0x481D6): timer 7 and timer 8 When data is written to this register, 10 high-order bits are loaded into the Timer A Comparison Data A Setup Register (buffer) as 10 low-order compare data bits and 6 low-order bits are loaded into the Timer B Comparison Data A Setup Register (buffer) as 6 low-order compare data bits. In standard mode, data cannot be written to the DA16 registers. S1C33401 TECHNICAL MANUAL EPSON IV-6-7 T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 16-bit data write DA16 Ch.0 register Timer 1 (SELCRB1 = 1) Comparison data A register buffer or Comparison data A register (SELCRB1 = 0) DA0A[15:6] DA0A[5:0] CR1A[9:0] CR2A[5:0] Timer 2 (SELCRB2 = 1) Comparison data A register buffer or Comparison data A register (SELCRB2 = 0) (CR1A[15:10] = 0) (CR2A[15:6] = 0) Comparator Comparator Figure IV.6.5.1 DA16 Function (Ch.0) Resetting the counter Each timer includes PRESETx (D1/0x48186 + 8*x) to reset the counter. PRESETx: 16-bit Timer x Reset Bit in the 16-bit Timer x Control Register (D1/0x48186 + 8*x) Normally, reset the counter before starting count-up by writing 1 to this control bit. After the counter starts counting, it will be reset by comparison match B. Timer RUN/STOP control Each timer includes PRUNx (D0/0x48186 + 8*x) to control RUN/STOP. PRUNx: 16-bit Timer x Run/Stop Control Bit in the 16-bit Timer x Control Register (D0/0x48186 + 8*x) The timer starts counting when 1 is written to PRUNx (D0/0x48186 + 8*x). The clock input is disabled and the timer stops counting when 0 is written to PRUNx. This RUN/STOP control does not affect the counter data. Even when the timer has stopped counting, the counter retains its count so that the timer can start counting again from that point. If the count of the counter matches the set value of the comparison data register during count-up, the timer generates a comparison match interrupt. When the counter matches comparison data B, an interrupt is generated and the counter is reset. At the same time, the values set in the compare register buffer are loaded to the compare data register if SELCRBx (D5/ 0x48186 + 8*x) is set to 1. The counter continues counting up regardless of which interrupt has occurred. In the case of a comparison B interrupt, the counter starts counting beginning with 0. When both PRUNx (D0/0x48186 + 8*x) and PRESETx (D1/0x48186 + 8*x) are set to 1 at the same time, the timer starts counting after resetting the counter. PRUNx PRESETx CRxA 0x2 CRxB 0x5 Input clock TCx 0 Reset 1 2 3 Comparison A interrupt 4 5 0 1 2 3 Reset and Comparison A Comparison B interrupt interrupt 4 5 0 1 Reset and Comparison B interrupt Figure IV.6.5.2 Basic Operation Timing of Counter IV-6-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) To synchronize multiple timers (advanced mode) I Since the timer RUN/STOP control bits are located in different addresses, two or more timers cannot be started at the same time. To synchronize multiple timers, the control bits PAUSEx (Dx/0x481DC) that stop each timer are provided in an address. PAUSEx: 16-bit Timer x Count Pause Bit in the Count Pause Register (Dx/0x481DC) When PAUSEx (Dx/0x481DC) is set to 1, timer x is placed in pause state and when set to 0, timer x starts counting or continues stop state according to the set value of PRUNx (D0/0x48186 + 8*x). However, it is necessary to set the 16-bit timer in advanced mode for using PAUSEx (Dx/0x481DC). The following shows a procedure to synchronize multiple timers. 1. Set the prescaler clocks for the timers to be synchronized to the same condition. 2. Set PAUSEx (Dx/0x481DC) for the timers to 1 to place the timers in pause state. 3. Set PRUNx (D0/0x48186 + 8*x) for the timers to 1. The timers do not start counting at this time as PAUSEx (Dx/0x481DC) for the timers have been set to 1. 4. Set all the PAUSEx (Dx/0x481DC) bits for the timers to 0 at the same time. The corresponding timers start counting simultaneously. Reading counter data The counter data can be read out from TCx[15:0] (D[15:0]/0x48184 + 8*x) at any time. TCx[15:0]: 16-bit Timer x Counter Data Bits in the 16-bit Timer x Counter Data Register (D[15:0]/0x48184 + 8*x) Writing counter data (advanced mode) In advanced mode, counter data can be written to TCx[15:0] (D[15:0]/0x48184 + 8*x) at any time. This makes it possible to change the interrupt and/or clock output cycles temporarily. Standard mode does not allow writing of counter data. IV T16 S1C33401 TECHNICAL MANUAL EPSON IV-6-9 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.6 Controlling Clock Output Logic MUX INITOLx Compare A Compare B MUX The timers can generate a TMx signal using the comparison match signals from the counter. Figure IV.6.6.1 shows the 16-bit timer clock output circuit. PTMx OUTINVx D Q TMx Q Clock Figure IV.6.6.1 16-bit Timer Clock Output Circuit Setting the initial output level (advanced mode) The default output level while the clock output is turned off is 0 (low level). This level can be changed to 1 (high level) using INITOLx (D8/0x48186 + 8*x). However, this function is available only in advanced mode. INITOLx: 16-bit Timer x Initial Output Level Select Bit in the 16-bit Timer x Control Register (D8/0x48186 + 8*x) When INITOLx (D8/0x48186 + 8*x) is 0 (default), the initial output level is low. When INITOLx (D8/0x48186 + 8*x) is set to 1, the initial output level is set to high. The timer output goes to the initial output level when the timer is reset by writing 1 to PRESETx (D1/0x48186 + 8*x) as well as when the timer output is turned off. Setting the signal active level By default, an active high signal (normal low) is generated. This logic can be inverted using OUTINVx (D4/ 0x48186 + 8*x). When 1 is written to OUTINVx, the timer generates an active low (normal high) signal. OUTINVx: 16-bit Timer x Clock Output Inversion Bit in the 16-bit Timer x Control Register (D4/0x48186 + 8*x) Note that the initial output level set by INITOLx (D8/0x48186 + 8*x) is inverted when OUTINVx (D4/0x48186 + 8*x) is set to 1. See Figure IV.6.6.2 for the waveforms. Setting the output port The TMx signal generated here can be output from the clock output pins (see Table IV.6.2.1), enabling a programmable clock to be supplied to external devices. After a cold start, the output pins are set for the I/O ports and set in input mode. The pins go into highimpedance status. When the pin function is switched to the timer output, the pin outputs the level according to the set values of INITOLx (D8/0x48186 + 8*x) and OUTINVx (D4/0x48186 + 8*x). The output pin holds this level until the output level changes due to the counter value after the timer output is enabled. Table IV.6.6.1 Initial Output Level IV-6-10 INITOLx OUTINVx Initial output level 1 1 0 0 1 0 1 0 Low High High Low EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) Starting clock output I To output the TMx clock, write 1 to the clock output control bit PTMx (D2/0x48186 + 8*x). Clock output is stopped by writing 0 to PTMx and goes to the initial output level according to the set values of INITOLx (D8/ 0x48186 + 8*x) and OUTINVx (D4/0x48186 + 8*x). PTMx: 16-bit Timer x Clock Output Control Bit in the 16-bit Timer x Control Register (D2/0x48186 + 8*x) Figure IV.6.6.2 shows the waveform of the output signal. Input clock PRESETx PTMx PRUNx Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Comparison match A signal Comparison match B signal TMx output (INITOLx = 0, OUTINVx = 0) TMx output (INITOLx = 0, OUTINVx = 1) TMx output (INITOLx = 1, OUTINVx = 0) TMx output (INITOLx = 1, OUTINVx = 1) (When CRxA = 3 and CRxB = 5) Figure IV.6.6.2 Waveform of 16-bit Timer Output When OUTINVx (D4/0x48186 + 8*x) = 0 (active high): The timer outputs a low level (initial output level when output is started) until the counter becomes equal to the comparison data A set in CRxA[15:0] (D[15:0]/0x48180 + 8*x). When the counter is incremented to the next value from the comparison data A, the output pin goes high and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in CRxB[15:0] (D[15:0]/0x48182 + 8*x), the counter is reset and the output pin goes low. At the same time a comparison B interrupt occurs. IV CRxA[15:0]: 16-bit Timer x Comparison Data A Bits in the 16-bit Timer x Comparison Data A Setup Register (D[15:0]/0x48180 + 8*x) CRxB[15:0]: 16-bit Timer x Comparison Data B Bits in the 16-bit Timer x Comparison Data B Setup Register (D[15:0]/0x48182 + 8*x) When OUTINVx (D4/0x48186 + 8*x) = 1 (active low): The timer outputs a high level (inverted initial output level when output is started) until the counter becomes equal to the comparison data A set in CRxA[15:0] (D[15:0]/0x48180 + 8*x). When the counter is incremented to the next value from the comparison data A, the output pin goes low and a comparison A interrupt occurs. When the counter becomes equal to the comparison data B set in CRxB[15:0] (D[15:0]/0x48182 + 8*x), the counter is reset and the output pin goes high. At the same time a comparison B interrupt occurs. S1C33401 TECHNICAL MANUAL EPSON IV-6-11 T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) Setting clock output fine mode By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when CRxA[15:0] (D[15:0]/0x48180 + 8*x) becomes equal to TCx[15:0] (D[15:0]/0x48184 + 8*x). TCx[15:0]: 16-bit Timer x Counter Data Bits in the 16-bit Timer x Counter Data Register (D[15:0]/0x48184 + 8*x) In fine mode, the output signal changes according to CRxA0 (D0/0x48180 + 8*x) when CRxA[15:1] (D[15:1]/ 0x48180 + 8*x) becomes equal to TCx[14:0] (D[14:0]/0x48184 + 8*x). When CRxA0 is 0, the output signal changes at the rising edge of the input clock. When CRxA0 is 1, the output signal changes at the falling edge of the input clock a half cycle from the default setting. Input clock Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 CRxA 2 3 4 5 6 5 CRxB Comparison match A signal Comparison match B signal TMx output (OUTINVx = 0) TMx output (OUTINVx = 1) Figure IV.6.6.3 Clock Output in Fine Mode As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the input clock. However, when CRxA[15:0] value is 0, the timer outputs a pulse with a 1-cycle width as the input clock, the same as the default setting. In fine mode, the maximum value of CRxB[15:0] is 215 - 1 = 32,767 and the range of CRxA[15:0] that can be set is 0 to (2 x CRxB[15:0] - 1). The fine mode is set using SELFMx (D6/0x48186 + 8*x). SELFMx: 16-bit Timer x Fine Mode Select Bit in the 16-bit Timer x Control Register (D6/0x48186 + 8*x) When 1 is written to SELFMx (D6/0x48186 + 8*x), fine mode is set. At initial reset, the fine mode is disabled. Precautions (1) If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal. Therefore, do not set the comparison registers as A = B. There is no problem when the interrupt function only is used. (2) When using the output clock, set the comparison data registers as A 0 and B 1. The minimum settings are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock x 1/2. (3) When the comparison data registers are set as A > B, no comparison A signal is generated. In this case, the output signal is fixed at the off level. IV-6-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.7 16-bit Timer Interrupts and DMA I The 16-bit timer has a function for generating an interrupt using the comparison match A and B states. The timing at which an interrupt is generated is shown in Figure IV.6.5.2 in the preceding section. Control registers of the interrupt controller Table IV.6.7.1 shows the control registers of the interrupt controller provided for each timer. Table IV.6.7.1 Control Registers of Interrupt Controller Cause of interrupt Cause-of-interrupt flag Interrupt enable register Interrupt priority register Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B Timer 6 comparison A Timer 6 comparison B Timer 7 comparison A Timer 7 comparison B Timer 8 comparison A Timer 8 comparison B Timer 9 comparison A Timer 9 comparison B F16TC0 (D3/0x40282) F16TU0 (D2/0x40282) F16TC1 (D7/0x40282) F16TU1 (D6/0x40282) F16TC2 (D3/0x40283) F16TU2 (D2/0x40283) F16TC3 (D7/0x40283) F16TU3 (D6/0x40283) F16TC4 (D3/0x40284) F16TU4 (D2/0x40284) F16TC5 (D7/0x40284) F16TU5 (D6/0x40284) F16TC6 (D3/0x402AA) F16TU6 (D2/0x402AA) F16TC7 (D7/0x402AA) F16TU7 (D6/0x402AA) F16TC8 (D3/0x402AB) F16TU8 (D2/0x402AB) F16TC9 (D7/0x402AB) F16TU9 (D6/0x402AB) E16TC0 (D3/0x40272) E16TU0 (D2/0x40272) E16TC1 (D7/0x40272) E16TU1 (D6/0x40272) E16TC2 (D3/0x40273) E16TU2 (D2/0x40273) E16TC3 (D7/0x40273) E16TU3 (D6/0x40273) E16TC4 (D3/0x40274) E16TU4 (D2/0x40274) E16TC5 (D7/0x40274) E16TU5 (D6/0x40274) E16TC6 (D3/0x402A7) E16TU6 (D2/0x402A7) E16TC7 (D7/0x402A7) E16TU7 (D6/0x402A7) E16TC8 (D3/0x402A8) E16TU8 (D2/0x402A8) E16TC9 (D7/0x402A8) E16TU9 (D6/0x402A8) P16T0[2:0] (D[2:0]/0x40266) P16T1[2:0] (D[6:4]/0x40266) P16T2[2:0] (D[2:0]/0x40267) P16T3[2:0] (D[6:4]/0x40267) P16T4[2:0] (D[2:0]/0x40268) P16T5[2:0] (D[6:4]/0x40268) P16T6[2:0] (D[2:0]/0x402A4) P16T7[2:0] (D[6:4]/0x402A4) P16T8[2:0] (D[2:0]/0x402A5) P16T9[2:0] (D[6:4]/0x402A5) When a comparison match state occurs in the timer, the corresponding cause-of-interrupt flag is set to 1. If the interrupt enable register bit corresponding to that cause-of-interrupt flag has been set to 1, an interrupt request is generated. An interrupt caused by a timer can be disabled by leaving the interrupt enable register bit for that timer set to 0. The cause-of-interrupt flag is always set to 1 by the timer's comparison match state, regardless of how the interrupt enable register is set (even when set to 0). The interrupt priority register sets an interrupt priority level (0 to 7) for each timer. Priorities within a timer block are such that timers of smaller numbers have a higher priority. Priorities between interrupt types are such that the comparison B interrupt has priority over the comparison A interrupt. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. It is only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the timer interrupt level set by the interrupt priority register, that a timer interrupt request is actually accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to Section IV.2, "Interrupt Controller (ITC)." S1C33401 TECHNICAL MANUAL EPSON IV-6-13 IV T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) Intelligent DMA The cause of interrupt of each timer can also invoke intelligent DMA (IDMA). This allows memory-to-memory DMA transfers to be performed cyclically. The following shows the IDMA channel numbers set for each cause of interrupt of timer: IDMA Ch. IDMA Ch. Timer 0 comparison B: 0x07 Timer 0 comparison A: 0x08 Timer 1 comparison B: 0x09 Timer 1 comparison A: 0x0A Timer 2 comparison B: 0x0B Timer 2 comparison A: 0x0C Timer 3 comparison B: 0x0D Timer 3 comparison A: 0x0E Timer 4 comparison B: 0x0F Timer 4 comparison A: 0x10 Timer 5 comparison B: 0x11 Timer 5 comparison A: 0x12 Timer 6 comparison B: 0x2E Timer 6 comparison A: 0x2F Timer 7 comparison B: 0x30 Timer 7 comparison A: 0x31 Timer 8 comparison B: 0x32 Timer 8 comparison A: 0x33 Timer 9 comparison B: 0x34 Timer 9 comparison A: 0x35 For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table IV.6.7.2 must be set to 1 in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table IV.6.7.2 Control Bits for IDMA Transfer Cause of interrupt IDMA request bit IDMA enable bit Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B Timer 6 comparison A Timer 6 comparison B Timer 7 comparison A Timer 7 comparison B Timer 8 comparison A Timer 8 comparison B Timer 9 comparison A Timer 9 comparison B R16TC0(D7/0x40290) R16TU0(D6/0x40290) R16TC1(D1/0x40291) R16TU1(D0/0x40291) R16TC2(D3/0x40291) R16TU2(D2/0x40291) R16TC3(D5/0x40291) R16TU3(D4/0x40291) R16TC4(D7/0x40291) R16TU4(D6/0x40291) R16TC5(D1/0x40292) R16TU5(D0/0x40292) R16TC6(D1/0x402AD) R16TU6(D0/0x402AD) R16TC7(D3/0x402AD) R16TU7(D2/0x402AD) R16TC8(D5/0x402AD) R16TU8(D4/0x402AD) R16TC9(D7/0x402AD) R16TU9(D6/0x402AD) DE16TC0(D7/0x40294) DE16TU0(D6/0x40294) DE16TC1(D1/0x40295) DE16TU1(D0/0x40295) DE16TC2(D3/0x40295) DE16TU2(D2/0x40295) DE16TC3(D5/0x40295) DE16TU3(D4/0x40295) DE16TC4(D7/0x40295) DE16TU4(D6/0x40295) DE16TC5(D1/0x40296) DE16TU5(D0/0x40296) DE16TC6(D1/0x402AF) DE16TU6(D0/0x402AF) DE16TC7(D3/0x402AF) DE16TU7(D2/0x402AF) DE16TC8(D5/0x402AF) DE16TU8(D4/0x402AF) DE16TC9(D7/0x402AF) DE16TU9(D6/0x402AF) If the IDMA request and enable bits are set to 1, IDMA is invoked through generation of a cause of interrupt. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." IV-6-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) High-speed DMA I The timer 0-7 interrupt causes can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to the channel 0 to 7 timers: Table IV.6.7.3 HSDMA Trigger Set-up Bits Cause of interrupt HSDMA channel Timer 0 comparison A Timer 0 comparison B Timer 1 comparison A Timer 1 comparison B Timer 2 comparison A Timer 2 comparison B Timer 3 comparison A Timer 3 comparison B Timer 4 comparison A Timer 4 comparison B Timer 5 comparison A Timer 5 comparison B Timer 6 comparison A Timer 6 comparison B Timer 7 comparison A Timer 7 comparison B 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 0111 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 0110 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 0111 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 0110 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 0111 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 0110 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 0111 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 0110 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 1001 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 1000 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 1001 HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) = 1000 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 1001 HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 1000 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 1001 HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) = 1000 For HSDMA to be invoked, a 16-bit timer interrupt cause should be selected using the trigger set-up bits in advance. Transfer conditions, etc. must also be set on the HSDMA side. If a 16-bit timer is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the cause of interrupt. For details on HSDMA transfer, refer to Section III.4, "High-Speed DMA (HSDMA)." Trap vectors The trap vector addresses for each default cause of interrupt are set as shown below: Timer 0 comparison B: 0x20000078 Timer 0 comparison A: 0x2000007C Timer 1 comparison B: 0x20000088 Timer 1 comparison A: 0x2000008C Timer 2 comparison B: 0x20000098 Timer 2 comparison A: 0x2000009C Timer 3 comparison B: 0x200000A8 Timer 3 comparison A: 0x200000AC Timer 4 comparison B: 0x200000B8 Timer 4 comparison A: 0x200000BC Timer 5 comparison B: 0x200000C8 Timer 5 comparison A: 0x200000CC Timer 6 comparison B: 0x20000178 Timer 6 comparison A: 0x2000017C Timer 7 comparison B: 0x20000188 Timer 7 comparison A: 0x2000018C Timer 8 comparison B: 0x20000198 Timer 8 comparison A: 0x2000019C Timer 9 comparison B: 0x200001A8 Timer 9 comparison A: 0x200001AC IV T16 The base address of the trap table can be changed using the TTBR register. S1C33401 TECHNICAL MANUAL EPSON IV-6-15 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.8 Details of Control Registers Table IV.6.8.1 List of 16-bit Timer Registers Address 0x00048180 0x00048182 0x00048184 0x00048186 0x00048188 0x0004818A 0x0004818C 0x0004818E 0x00048190 0x00048192 0x00048194 0x00048196 0x00048198 0x0004819A 0x0004819C 0x0004819E 0x000481A0 0x000481A2 0x000481A4 0x000481A6 0x000481A8 0x000481AA 0x000481AC 0x000481AE 0x000481B0 0x000481B2 0x000481B4 0x000481B6 0x000481B8 0x000481BA 0x000481BC 0x000481BE 0x000481C0 0x000481C2 0x000481C4 0x000481C6 0x000481C8 0x000481CA 0x000481CC 0x000481CE IV-6-16 Register name 16-bit Timer 0 Comparison Data A Setup Register (pT16_CR0A) 16-bit Timer 0 Comparison Data B Setup Register (pT16_CR0B) 16-bit Timer 0 Counter Data Register (pT16_TC0) 16-bit Timer 0 Control Register (pT16_CTL0) 16-bit Timer 1 Comparison Data A Setup Register (pT16_CR1A) 16-bit Timer 1 Comparison Data B Setup Register (pT16_CR1B) 16-bit Timer 1 Counter Data Register (pT16_TC1) 16-bit Timer 1 Control Register (pT16_CTL1) 16-bit Timer 2 Comparison Data A Setup Register (pT16_CR2A) 16-bit Timer 2 Comparison Data B Setup Register (pT16_CR2B) 16-bit Timer 2 Counter Data Register (pT16_TC2) 16-bit Timer 2 Control Register (pT16_CTL2) 16-bit Timer 3 Comparison Data A Setup Register (pT16_CR3A) 16-bit Timer 3 Comparison Data B Setup Register (pT16_CR3B) 16-bit Timer 3 Counter Data Register (pT16_TC3) 16-bit Timer 3 Control Register (pT16_CTL3) 16-bit Timer 4 Comparison Data A Setup Register (pT16_CR4A) 16-bit Timer 4 Comparison Data B Setup Register (pT16_CR4B) 16-bit Timer 4 Counter Data Register (pT16_TC4) 16-bit Timer 4 Control Register (pT16_CTL4) 16-bit Timer 5 Comparison Data A Setup Register (pT16_CR5A) 16-bit Timer 5 Comparison Data B Setup Register (pT16_CR5B) 16-bit Timer 5 Counter Data Register (pT16_TC5) 16-bit Timer 5 Control Register (pT16_CTL5) 16-bit Timer 6 Comparison Data A Setup Register (pT16_CR6A) 16-bit Timer 6 Comparison Data B Setup Register (pT16_CR6B) 16-bit Timer 6 Counter Data Register (pT16_TC6) 16-bit Timer 6 Control Register (pT16_CTL6) 16-bit Timer 7 Comparison Data A Setup Register (pT16_CR7A) 16-bit Timer 7 Comparison Data B Setup Register (pT16_CR7B) 16-bit Timer 7 Counter Data Register (pT16_TC7) 16-bit Timer 7 Control Register (pT16_CTL7) 16-bit Timer 8 Comparison Data A Setup Register (pT16_CR8A) 16-bit Timer 8 Comparison Data B Setup Register (pT16_CR8B) 16-bit Timer 8 Counter Data Register (pT16_TC8) 16-bit Timer 8 Control Register (pT16_CTL8) 16-bit Timer 9 Comparison Data A Setup Register (pT16_CR9A) 16-bit Timer 9 Comparison Data B Setup Register (pT16_CR9B) 16-bit Timer 9 Counter Data Register (pT16_TC9) 16-bit Timer 9 Control Register (pT16_CTL9) EPSON Size Function 16 Sets 16-bit timer 0 comparison data A. 16 Sets 16-bit timer 0 comparison data B. 16 16 16 16-bit timer 0 counter data Controls 16-bit timer 0. Sets 16-bit timer 1 comparison data A. 16 Sets 16-bit timer 1 comparison data B. 16 16 16 16-bit timer 1 counter data Controls 16-bit timer 1. Sets 16-bit timer 2 comparison data A. 16 Sets 16-bit timer 2 comparison data B. 16 16 16 16-bit timer 2 counter data Controls 16-bit timer 2. Sets 16-bit timer 3 comparison data A. 16 Sets 16-bit timer 3 comparison data B. 16 16 16 16-bit timer 3 counter data Controls 16-bit timer 3. Sets 16-bit timer 4 comparison data A. 16 Sets 16-bit timer 4 comparison data B. 16 16 16 16-bit timer 4 counter data Controls 16-bit timer 4. Sets 16-bit timer 5 comparison data A. 16 Sets 16-bit timer 5 comparison data B. 16 16 16 16-bit timer 5 counter data Controls 16-bit timer 5. Sets 16-bit timer 6 comparison data A. 16 Sets 16-bit timer 6 comparison data B. 16 16 16 16-bit timer 6 counter data Controls 16-bit timer 6. Sets 16-bit timer 7 comparison data A. 16 Sets 16-bit timer 7 comparison data B. 16 16 16 16-bit timer 7 counter data Controls 16-bit timer 7. Sets 16-bit timer 8 comparison data A. 16 Sets 16-bit timer 8 comparison data B. 16 16 16 16-bit timer 8 counter data Controls 16-bit timer 8. Sets 16-bit timer 9 comparison data A. 16 Sets 16-bit timer 9 comparison data B. 16 16 16-bit timer 9 counter data Controls 16-bit timer 9. S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) Address 0x000481D0 0x000481D2 0x000481D4 0x000481D6 0x000481DC 0x000481DE Size 16 16 16 16 16 16 Register name DA16 Ch.0 Register (pDA16_CR0A) DA16 Ch.1 Register (pDA16_CR1A) DA16 Ch.2 Register (pDA16_CR2A) DA16 Ch.3 Register (pDA16_CR3A) Count Pause Register (pT16_CNT_PAUSE) 16-bit Timer STD/ADV Mode Select Register (pT16_ADVMODE) I Function Sets DA16 Ch.0 comparison data A. Sets DA16 Ch.1 comparison data A. Sets DA16 Ch.2 comparison data A. Sets DA16 Ch.3 comparison data A. Stops multiple timers simultaneously. Selects standard or advanced mode. The following describes each 16-bit timer control register. The 16-bit timer control registers are mapped in the 16-bit device area from 0x48180 to 0x481DE, and can be accessed in units of half-words or bytes. Note: When setting the 16-bit timer control registers, be sure to write a 0, and not a 1, for all "reserved bits." IV T16 S1C33401 TECHNICAL MANUAL EPSON IV-6-17 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x48180-0x481C8: 16-bit Timer x Comparison Data A Setup Registers (pT16_CRxA) Register name Address Bit Name 0048180 | 00481C8 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRxA15 CRxA14 CRxA13 CRxA12 CRxA11 CRxA10 CRxA9 CRxA8 CRxA7 CRxA6 CRxA5 CRxA4 CRxA3 CRxA2 CRxA1 CRxA0 16-bit timer x comparison data A setup register (pT16_CRxA) Function Setting 16-bit timer x comparison data A CRxA15 = MSB CRxA0 = LSB 0 to 65535 Init. R/W X X X X X X X X X X X X X X X X Remarks R/W Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 9. 0x48180 0x48188 0x48190 0x48198 0x481A0 0x481A8 0x481B0 0x481B8 0x481C0 0x481C8 D[15:0] IV-6-18 16-bit Timer 0 Comparison Data A Setup Register (pT16_CR0A) 16-bit Timer 1 Comparison Data A Setup Register (pT16_CR1A) 16-bit Timer 2 Comparison Data A Setup Register (pT16_CR2A) 16-bit Timer 3 Comparison Data A Setup Register (pT16_CR3A) 16-bit Timer 4 Comparison Data A Setup Register (pT16_CR4A) 16-bit Timer 5 Comparison Data A Setup Register (pT16_CR5A) 16-bit Timer 6 Comparison Data A Setup Register (pT16_CR6A) 16-bit Timer 7 Comparison Data A Setup Register (pT16_CR7A) 16-bit Timer 8 Comparison Data A Setup Register (pT16_CR8A) 16-bit Timer 9 Comparison Data A Setup Register (pT16_CR9A) CRxA[15:0]: 16-bit Timer x Comparison Data A Bits Sets the comparison data A for each timer. (Default: indeterminate) When SELCRBx (D5/0x48186 + 8*x) is set to 0, comparison data is directly read or writing from/to the comparison data register A. When SELCRBx is set to 1, comparison data is read or written from/to the comparison register buffer A. The content of the buffer is loaded to the comparison data register A when the counter is reset. The data set in this register is compared with each corresponding counter data. When the contents match, a comparison A interrupt is generated and the output signal rises (OUTINVx (D4/0x48186 + 8*x) = 0) or falls (OUTINVx = 1). This does not affect the counter value and count-up operation. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x48182-0x481CA: 16-bit Timer x Comparison Data B Setup Registers (pT16_CRxB) Register name Address Bit Name 0048182 | 00481CA (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CRxB15 CRxB14 CRxB13 CRxB12 CRxB11 CRxB10 CRxB9 CRxB8 CRxB7 CRxB6 CRxB5 CRxB4 CRxB3 CRxB2 CRxB1 CRxB0 16-bit timer x comparison data B setup register (pT16_CRxB) Function Setting 16-bit timer x comparison data B CRxB15 = MSB CRxB0 = LSB 0 to 65535 Init. R/W X X X X X X X X X X X X X X X X I Remarks R/W Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 9. 0x48182 0x4818A 0x48192 0x4819A 0x481A2 0x481AA 0x481B2 0x481BA 0x481C2 0x481CA D[15:0] 16-bit Timer 0 Comparison Data B Setup Register (pT16_CR0B) 16-bit Timer 1 Comparison Data B Setup Register (pT16_CR1B) 16-bit Timer 2 Comparison Data B Setup Register (pT16_CR2B) 16-bit Timer 3 Comparison Data B Setup Register (pT16_CR3B) 16-bit Timer 4 Comparison Data B Setup Register (pT16_CR4B) 16-bit Timer 5 Comparison Data B Setup Register (pT16_CR5B) 16-bit Timer 6 Comparison Data B Setup Register (pT16_CR6B) 16-bit Timer 7 Comparison Data B Setup Register (pT16_CR7B) 16-bit Timer 8 Comparison Data B Setup Register (pT16_CR8B) 16-bit Timer 9 Comparison Data B Setup Register (pT16_CR9B) CRxB[15:0]: 16-bit Timer x Comparison Data B Bits Sets the comparison data B for each timer. (Default: indeterminate) When SELCRBx (D5/0x48186 + 8*x) is set to 0, comparison data is directly read or writing from/to the comparison data register B. When SELCRBx is set to 1, comparison data is read or written from/to the comparison register buffer B. The content of the buffer is loaded to the comparison data register B when the counter is reset. The data set in this register is compared with each corresponding counter data. When the contents match, a comparison B interrupt is generated and the output signal falls (OUTINVx (D4/0x48186 + 8*x) = 0) or rises (OUTINVx = 1). Furthermore, the counter is reset to 0. S1C33401 TECHNICAL MANUAL EPSON IV-6-19 IV T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x48184-0x481CC: 16-bit Timer x Counter Data Registers (pT16_TCx) Register name Address Bit 0048184 | 00481CC (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer x counter data register (pT16_TCx) Name TCx15 TCx14 TCx13 TCx12 TCx11 TCx10 TCx9 TCx8 TCx7 TCx6 TCx5 TCx4 TCx3 TCx2 TCx1 TCx0 Function 16-bit timer x counter data TCx15 = MSB TCx0 = LSB Setting 0 to 65535 Init. R/W X X X X X X X X X X X X X X X X Remarks R/W Data can be written only in advanced mode. Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 9. 0x48184 0x4818C 0x48194 0x4819C 0x481A4 0x481AC 0x481B4 0x481BC 0x481C4 0x481CC D[15:0] IV-6-20 16-bit Timer 0 Counter Data Register (pT16_TC0) 16-bit Timer 1 Counter Data Register (pT16_TC1) 16-bit Timer 2 Counter Data Register (pT16_TC2) 16-bit Timer 3 Counter Data Register (pT16_TC3) 16-bit Timer 4 Counter Data Register (pT16_TC4) 16-bit Timer 5 Counter Data Register (pT16_TC5) 16-bit Timer 6 Counter Data Register (pT16_TC6) 16-bit Timer 7 Counter Data Register (pT16_TC7) 16-bit Timer 8 Counter Data Register (pT16_TC8) 16-bit Timer 9 Counter Data Register (pT16_TC9) TCx[15:0]: 16-bit Timer x Counter Data Bits The counter data of each timer can be read from this register. (Default: indeterminate) The data can be read out at any time. In advanced mode, counter data can be written at any time. This makes it possible to change the interrupt and/or clock output cycles temporarily. Standard mode does not allow writing of counter data. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x48186-0x481CE: 16-bit Timer x Control Registers (pT16_CTLx) Register name Address Bit Name 0048186 D15-9 - 16-bit timer x D8 INITOLx | control register 00481CE D7 (TMODEx) (pT16_CTLx) D6 SELFMx (HW) D5 SELCRBx D4 OUTINVx D3 CKSLx D2 PTMx D1 PRESETx D0 PRUNx Function reserved 16-bit timer x initial output level (reserved for 16-bit timer x test) 16-bit timer x fine mode selection 16-bit timer x comparison buffer 16-bit timer x output inversion 16-bit timer x input clock selection 16-bit timer x clock output control 16-bit timer x reset 16-bit timer x Run/Stop control Setting 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On Reset 0 Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - 0 0 0 0 0 0 0 0 0 - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. Note: The letter `x' in bit names, etc., denotes a timer number from 0 to 9. 0x48186 0x4818E 0x48196 0x4819E 0x481A6 0x481AE 0x481B6 0x481BE 0x481C6 0x481CE 16-bit Timer 0 Control Register (pT16_CTL0) 16-bit Timer 1 Control Register (pT16_CTL1) 16-bit Timer 2 Control Register (pT16_CTL2) 16-bit Timer 3 Control Register (pT16_CTL3) 16-bit Timer 4 Control Register (pT16_CTL4) 16-bit Timer 5 Control Register (pT16_CTL5) 16-bit Timer 6 Control Register (pT16_CTL6) 16-bit Timer 7 Control Register (pT16_CTL7) 16-bit Timer 8 Control Register (pT16_CTL8) 16-bit Timer 9 Control Register (pT16_CTL9) D[15:9] Reserved D8 INITOLx: 16-bit Timer x Initial Output Level Select Bit (Advanced Mode) Selects an initial output level for timer output. 1 (R/W): High 0 (R/W): Low (default) The timer output pin goes to the initial output level set using this bit when the timer output is turned off by writing 0 to PTMx (D2) or when the timer is reset by writing 1 to PRESETx (D1). However, this level is inverted if OUTINVx (D4) is set to 1. Note that writing to this bit is enabled only in advanced mode. D7 (TMODEx): Reserved Do not set this bit to 1. D6 SELFMx: 16-bit Timer x Fine Mode Select Bit Sets fine mode for clock output. 1 (R/W): Fine mode 0 (R/W): Normal output (default) IV T16 When SELFMx is set to 1, clock output is set in fine mode which allows adjustment of the output signal duty ratio in units of a half cycle for the input clock. When SELFMx is set to 0, normal clock output will be performed. D5 SELCRBx: 16-bit Timer x Comparison Buffer Enable Bit Enables or disables writing to the comparison register buffer. 1 (R/W): Enabled 0 (R/W): Disabled (default) When SELCRBx is set to 1, comparison data is read and written from/to the comparison register buffer. The content of the buffer is loaded to the comparison data register when the counter is reset by the software or the comparison B signal. When SELCRBx is set to 0, comparison data is read and written from/to the comparison data register. S1C33401 TECHNICAL MANUAL EPSON IV-6-21 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) D4 OUTINVx: 16-bit Timer x Output Inversion Bit Selects a logic of the output signal. 1 (R/W): Inverted (active low) 0 (R/W): Normal (active high) (default) By writing 1 to OUTINVx, an active-low signal (off level = high) is generated for the TMx output. When OUTINVx is set to 0, an active-high signal (off level = low) is generated. Writing 1 to this bit inverts the initial output level set using INITOLx (D8) as well. D3 CKSLx: 16-bit Timer x Input Clock Select Bit Selects the input clock for each timer. 1 (R/W): External clock 0 (R/W): Internal clock (default) The internal clock (prescaler output) is selected for the input clock of each timer by writing 0 to CKSLx. An external clock (one that is fed from the clock input pin) is selected by writing 1, and the timer functions as an event counter. In this case, the clock input pin must be set using the corresponding port function select register before an external clock is selected here. D2 PTMx: 16-bit Timer x Clock Output Control Bit Controls the output of the TMx signal (timer output clock). 1 (R/W): On 0 (R/W): Off (default) The TMx signal is output from the clock output pin by writing 1 to PTMx. Clock output is stopped by writing 0 to PTMx and goes to the off level according to the set values of OUTINVx (D4) and INITOLx (D8). In this case, the clock output pin must be set using the corresponding port function select register before outputting the TMx signal here. D1 PRESETx: 16-bit Timer x Reset Bit Preset the reload data in the counter. 1 (W): Reset 0 (W): Has no effect 0 (R): Always 0 when read (default) The counter of timer x is reset by writing 1 to PRESETx. D0 PRUNx: 16-bit Timer x Run/Stop Control Bit Controls the timer's RUN/STOP state. 1 (R/W): Run 0 (R/W): Stop (default) Each timer is made to start counting up by writing 1 to PRUNx and made to stop counting by writing 0. In the STOP state, the counter data is retained until the timer is reset or placed in a RUN state. By changing states from STOP to RUN, the timer can restart counting beginning at the retained count. IV-6-22 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x481D0-0x481D6: DA16 Ch.x Registers (pDA16_CRxA) Register name Address Bit Name 00481D0 | 00481D6 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAxA15 DAxA14 DAxA13 DAxA12 DAxA11 DAxA10 DAxA9 DAxA8 DAxA7 DAxA6 DAxA5 DAxA4 DAxA3 DAxA2 DAxA1 DAxA0 DA16 Ch.x register (pDA16_CRxA) Function DA16 Ch.x comparison data A DAxA15 = MSB DAxA0 = LSB Setting 0 to 65535 I Init. R/W X X X X X X X X X X X X X X X X Remarks R/W Advanced mode Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x481D0 0x481D2 0x481D4 0x481D6 D[15:0] DA16 Ch.0 Register (pDA16_CR0A) DA16 Ch.1 Register (pDA16_CR1A) DA16 Ch.2 Register (pDA16_CR2A) DA16 Ch.3 Register (pDA16_CR3A) DAxA[15:0]: DA16 Ch.x Comparison Data A Bits (Advanced Mode) Sets the comparison data A for each channel in DA16 mode. (Default: indeterminate) The following shows the correspondence between these registers and timers: (timer A and timer B) DA16 Ch.0 Register: timer 1 and timer 2 DA16 Ch.1 Register: timer 3 and timer 4 DA16 Ch.2 Register: timer 5 and timer 6 DA16 Ch.3 Register: timer 7 and timer 8 IV When data is written to this register, 10 high-order bits (DAxA[15:6]) are loaded into the Timer A Comparison Data A Setup Register (buffer) as 10 low-order compare data bits and 6 low-order bits (DAxA[5:0]) are loaded into the Timer B Comparison Data A Setup Register (buffer) as 6 low-order compare data bits. This makes it possible to reduce software load for using two 16-bit timers as a 16-bit D/A converter. Note that writing to this register is enabled only in advanced mode. S1C33401 TECHNICAL MANUAL EPSON IV-6-23 T16 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x481DC: Count Pause Register (pT16_CNT_PAUSE) Register name Address Bit Name 00481DC D15-10 - Count pause D9 PAUSE9 (HW) register D8 PAUSE8 (pT16_CNT_PAUSE) D7 PAUSE7 D6 PAUSE6 D5 PAUSE5 D4 PAUSE4 D3 PAUSE3 D2 PAUSE2 D1 PAUSE1 D0 PAUSE0 Function reserved 16-bit timer 9 count pause 16-bit timer 8 count pause 16-bit timer 7 count pause 16-bit timer 6 count pause 16-bit timer 5 count pause 16-bit timer 4 count pause 16-bit timer 3 count pause 16-bit timer 2 count pause 16-bit timer 1 count pause 16-bit timer 0 count pause Setting - 1 Pause 0 Count Init. R/W - 0 0 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W Advanced mode R/W R/W R/W R/W R/W R/W R/W R/W R/W Since the timer RUN/STOP control bits are located in different addresses, two or more timers cannot be started at the same time. To synchronize multiple timers, the control bits PAUSEx that stop each timer are provided in this register. 1 (R/W): Pause 0 (R/W): Count (default) When PAUSEx is set to 1, timer x is placed in pause state and when set to 0, timer x starts counting or continues stop state according to the set value of PRUNx (D0/0x48186 + 8*x). Note that writing to this bit is enabled only in advanced mode. The following shows a procedure to synchronize multiple timers. 1. Set the prescaler clocks for the timers to be synchronized to the same condition. 2. Set PAUSEx for the timers to 1 to place the timers in pause state. 3. Set PRUNx (D0/0x48186 + 8*x) for the timers to 1. 4. Set all the PAUSEx bits for the timers to 0 at the same time. D[15:10] Reserved D9 PAUSE9: 16-bit Timer 9 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 9. D8 PAUSE8: 16-bit Timer 8 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 8. D7 PAUSE7: 16-bit Timer 7 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 7. D6 PAUSE6: 16-bit Timer 6 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 6. D5 PAUSE5: 16-bit Timer 5 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 5. D4 PAUSE4: 16-bit Timer 4 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 4. D3 PAUSE3: 16-bit Timer 3 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 3. D2 PAUSE2: 16-bit Timer 2 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 2. D1 PAUSE1: 16-bit Timer 1 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 1. D0 PAUSE0: 16-bit Timer 0 Count Pause Bit (Advanced Mode) Stops the counter in 16-bit timer 0. IV-6-24 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) 0x481DE: 16-bit Timer STD/ADV Mode Select Register (pT16_ADVMODE) Register name Address Bit Name 00481DE D15-1 - 16-bit timer (HW) STD/ADV mode D0 T16ADV select register (pT16_ADVMODE) Function Setting reserved Init. R/W - Standard mode/advanced mode select 1 Advanced mode D[15:1] Reserved D0 T16ADV: Standard/Advanced Mode Select Bit Selects standard or advanced mode. 1 (R/W): Advanced mode 0 (R/W): Standard mode (default) 0 Standard mode - - 0 R/W I Remarks Writing 1 not allowed. The 16-bit timer in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV 16-bit timer has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table IV.6.8.2 shows differences between standard mode and advanced mode. Table IV.6.8.2 Differences between Standard Mode and Advanced Mode Function Writing to the count data register Setting of the initial timer output level (high or low) DA16 function (DA16 registers) Multiple timer full-sync function Standard mode Advanced mode Disabled (read only) Disabled (depending on the OUTINVx set value) Cannot be used Not supported Enabled Enabled (can be specified using INITOLx) Can be used Supported (can be controlled using PAUSEx) To configure the 16-bit timer in advanced mode, set this bit to 1. The control registers/bits for the extended functions are enabled to write after this setting. Note: Standard or advanced mode currently set is applied to all the 16-bit timers. It cannot be selected for each timer individually. IV T16 S1C33401 TECHNICAL MANUAL EPSON IV-6-25 IV C33 ADV BASIC PERIPHERAL BLOCK: 16-BIT TIMERS (T16) IV.6.9 Precautions * The 16-bit timers operate only when the prescaler is operating. * When setting the count clock or operation mode, make sure the 16-bit timer is turned off. * If a same value is set to the comparison data A and B registers, a hazard may be generated in the output signal. Therefore, do not set the comparison registers as A = B. There is no problem when the interrupt function only is used. * When using the output clock, set the comparison data registers as A 0 and B 1. The minimum settings are A = 0 and B = 1. In this case, the timer output clock cycle is the input clock x 1/2. * When the comparison data registers are set as A > B in normal mode, no comparison A interrupt is generated. In this case, the output signal is fixed at the off level. In fine mode, no comparison A interrupt is generated when the comparison data registers are set as A > 2 x B + 1. * After an initial reset, the cause-of-interrupt flag becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag and register in the software. * To prevent another interrupt from being generated by the same cause of interrupt after an interrupt has occurred, be sure to reset the cause-of-interrupt flag before setting the PSR again or executing the reti instruction. IV-6-26 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7 Watchdog Timer (WDT) I IV.7.1 Configuration of the Watchdog Timer The C33 ADV basic peripheral circuit block incorporates a watchdog timer to detect the CPU running uncontrollably. The watchdog timer consists of a 30-bit up counter and comparison data register for generating an NMI or internal reset signal at programmable cycles. By resetting the watchdog timer within such a cycle in software so as not to generate NMI or internal reset signals, it is possible to detect a program running uncontrollably that does not execute that processing routine. The peripheral circuit clock (PCLK) or external clock input for 16-bit timer 0 (EXCL0) can be selected as the count clock for the watchdog timer. Moreover, a clock can be generated synchronously with NMI/reset generation cycles (set by the comparison data register) and output from the watchdog timer to external devices. Figure IV.7.1.1 shows a block diagram of the watchdog timer. Watchdog timer reset (WDRESEN) Watchdog timer Run/Stop control (RUNSTP) EXCL0 30-bit up counter (CTRDT) PCLK CLKSEL CMU NMI NMIEN Comparator Comparison signal RESET Data bus External clock 30-bit comparison data register (CMPDT) RESEN WDT_CLK Clock output circuit IV CLKEN Watchdog timer Figure IV.7.1.1 Block Diagram of Watchdog Timer WDT S1C33401 TECHNICAL MANUAL EPSON IV-7-1 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.2 Input/Output Pins of the Watchdog Timer Table IV.7.2.1 Input/Output Pins of Watchdog Timer Pin name EXCL0 WDT_CLK I/O I O Function External clock input pin (external clock input for 16-bit timer 0) Watchdog timer clock output pin Use EXCL0 to clock the counter of the watchdog timer with an external clock; use WDT_CLK to output the clock generated in the watchdog timer to external devices. Note: These pins are shared with general-purpose input/output ports or other peripheral circuit input/ output pins, and set for other than the watchdog timer function by default. Therefore, before these pins can be used as input/output ports for the watchdog timer clock, the corresponding Port Function Select Register must be set to switch over the pin functions. For details about pin functions and how to switch over, see Section I.3.3, "Switching Over Multiplexed Pin Functions." IV-7-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.3 Operating Clock of the Watchdog Timer I The watchdog timer module is clocked by the peripheral circuit clock (PCLK) supplied from the CMU. At initial reset, this clock is selected as the operating clock for the watchdog timer. While the watchdog timer remains idle or is not being used, the clock supplied from the CMU can be turned off to reduce the amount of current consumed on the chip. Use WDTCLK (D3/0x40181) for this control. WDTCLK: Watchdog Timer Clock Control Bit in the Peripheral Clock Control Register 2 (D3/0x40181) Setting WDTCLK (D3/0x40181) to 0 turns off the clock supplied from the CMU to the watchdog timer. For details about PCLK generation and control, see Section II.3, "Clock Management Unit (CMU)." Notes: * Even when using an external clock as the count clock for the watchdog timer, PCLK is required for watchdog timer operation and access to its control register. * The Peripheral Clock Control Register 2 (0x40181) is write-protected. To rewrite this register and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372, write protection must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 may cause the system to operate erratically, make sure that data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW) unless rewriting said registers. IV WDT S1C33401 TECHNICAL MANUAL EPSON IV-7-3 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.4 Control of the Watchdog Timer IV.7.4.1 Setting Up the Watchdog Timer Selecting the count clock The internal clock (PCLK) or external clock (EXCL0) can be selected as the count clock for the 30-bit upcounter by using CLKSEL (D6/0x48162). CLKSEL: Watchdog Timer Input Clock Select Bit in Watchdog Timer Enable Register (D6/0x48162) Setting CLKSEL (D6/0x48162) to 0 (default) selects the internal clock (PCLK); setting it to 1 selects the external clock (EXCL0). Therefore, before an external clock can be used, the function of the pin set as an I/O port by default must be switched to EXCL0 (external clock input for 16-bit timer 0) by using the Port Function Select Register. For details about pin functions and how to switch over, see Section I.3.3, "Switching Over Multiplexed Pin Functions." For details about PCLK generation and control, see Section II.3, "Clock Management Unit (CMU)." Setting the NMI/reset generation cycle The watchdog timer has a 30-bit comparison data register that can be used to set a cycle in which to generate an NMI or reset signal. CMPDT[15:0]: 16 Low-order Comparison Data Bits in the Watchdog Timer Comparison Data Setup Register 0 (D[15:0]/0x48164) CMPDT[29:16]: 14 High-order Comparison Data Bits in the Watchdog Timer Comparison Data Setup Register 1 (D[13:0]/0x48166) The data set in these register bits is compared with the up-counter value. When both match, a specified NMI or reset signal is output. The up-counter is reset to 0 at this time. The NMI/reset generation cycle can be calculated from the equation below. CMPDT + 1 NMI generating cycle = -------- [sec] fWDTIN where CMPDT = value set in CMPDT[29:0] (D[13:0]/0x48166, D[15:0]/0x48164) fWDTIN = PCLK or EXCL0 input clock frequency [Hz] For example, the specifiable maximum NMI/reset generation cycle is about 21.47 seconds at 50-MHz PCLK input. Note: Do not set a value equal to or less than 0x0000001F in the comparison data register. Selecting the NMI/reset generation function To output an NMI signal when the watchdog timer is not reset within a specified cycle, set NMIEN (D1/0x48162) to 1. To output a reset signal instead, set RESEN (D0/0x48162) to 1. NMIEN: Watchdog Timer NMI Enable Bit in the Watchdog Timer Enable Register (D1/0x48162) RESEN: Watchdog Timer RESET Enable Bit in the Watchdog Timer Enable Register (D0/0x48162) Setting both bits to 0 (default) generates neither an NMI signal nor a reset signal, although the up-counter remains active and can output a clock. Setting both bits to 1 outputs both an NMI signal and a reset signal. In this case, however, reset exception handling is executed since it has priority over the NMI exception handling. The NMI and reset signals are both output as pulses of 32 PCLK clocks in width. Note: Depending on the counter and comparison register values, an NMI or reset signal may be generated after the NMI or reset function is enabled here (or even when the watchdog timer has not yet been started). Always be sure to set comparison data and reset the watchdog timer before writing 1 to NMIEN (D1/0x48162) or RESEN (D0/0x48162). IV-7-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) Write protection of watchdog timer registers I The Watchdog Timer Enable Register (0x48162) and Watchdog Timer Comparison Data Registers (0x48164, 0x48166) are write-protected to prevent NMI or reset signals from being inadvertently generated by unnecessary write operations. To rewrite these registers, write protection must be removed by writing 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160). Once the registers are rewritten, be sure to write other than 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160) to reapply write protection. IV.7.4.2 Starting/Stopping the Watchdog Timer Writing 1 to RUNSTP (D4/0x48162) starts counting by the watchdog timer; writing 0 stops the watchdog timer. RUNSTP: Watchdog Timer Run/Stop Control Bit in the Watchdog Timer Enable Register (D4/0x48162) Since RUNSTP (D4/0x48162) exists in the write-protected Watchdog Timer Enable Register (0x48162), write protection must be removed by writing 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160) before the content of RUNSTP can be altered. IV.7.4.3 Resetting the Watchdog Timer Before the NMI/reset generation function of the watchdog timer can be used, a routine to reset the watchdog timer before NMI or reset generation must be prepared in a location for periodic processing. Make sure that this routine is processed within the NMI/reset generation cycle described earlier. Writing 1 to WDRESEN (D0/0x4816C) resets the watchdog timer. The up-counter is reset to 0 at this time, then starts counting NMI/reset generation cycles all over again. WDRESEN: Watchdog Timer Reset Bit in the Watchdog Timer Control Register (D0/0x4816C) If the watchdog timer is not reset within the set cycle for some reason, the CPU is placed into trap handling by an NMI or reset signal to execute the processing routine. The reset and NMI trap vector addresses are set by default to 0x20000000 and 0x2000001C, respectively. The trap table base address can be altered by using TTBR. The count value of the up-counter can be read out from the Watchdog Timer Count Registers (0x48168, 0x4816A) at any time. IV CTRDT[15:0]: 16 Low-order Counter Data Bits in the Watchdog Timer Count Register 0 (D[15:0]/0x48168) CTRDT[29:16]: 14 High-order Counter Data Bits in the Watchdog Timer Count Register 1 (D[13:0]/0x4816A) IV.7.4.4 Operation in Standby Mode In HALT/HALT2 modes WDT In HALT and HALT2 modes, the watchdog timer remains active as it is supplied with a clock. Therefore, if HALT/HALT2 mode remains active beyond the NMI/reset generation cycle, an NMI or reset signal deactivates HALT mode. To disable the watchdog timer in HALT/HALT2 mode, set NMIEN (D1/0x48162) or RESEN (D0/0x48162) to 0. Otherwise, write 0 to RUNSTP (D4/0x48162) to stop the watchdog timer before executing the halt instruction. When NMIEN (D1/0x48162) or RESEN (D0/0x48162) disables NMI or reset generation, the watchdog timer continues counting even in HALT/HALT2 mode. To reenable NMI or reset generation after exiting HALT/ HALT2 mode, be sure to reset the watchdog timer beforehand. When HALT/HALT2 mode is entered after stopping the watchdog timer, be sure to reset the watchdog timer before restarting it. In SLEEP mode The supply of PCLK from the CMU stops in SLEEP mode. Therefore, the watchdog timer also stops operating. To prevent an unnecessary NMI or reset signal from being generated after exiting SLEEP mode, be sure to reset the watchdog timer before executing the slp instruction. Moreover, disable NMI/reset generation by setting NMIEN (D1/0x48162) or RESEN (D0/0x48162) as required. S1C33401 TECHNICAL MANUAL EPSON IV-7-5 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.4.5 Clock Output of the Watchdog Timer The watchdog timer can output an NMI/reset generation cycle-synchronous clock from the IC to external devices. For this clock output, set CLKEN (D5/0x48162) to 1 after setting up the WDT_CLK pin. CLKEN: Watchdog Timer Clock Output Control Bit in the Watchdog Timer Enable Register (D5/0x48162) Since CLKEN (D5/0x48162) also exists in the write-protected Watchdog Timer Enable Register (0x48162), write protection must be removed by writing 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160) before the content of CLKEN can be altered. If the watchdog timer is not reset in software, the level of clock output from the IC is reversed synchronously with the NMI generation cycles. (This applies when reset generation is disabled.) When the watchdog timer is reset in software, clock output from the IC goes low at that time and remains low. PCLK clock Counter data Comparison data FFFF1D FFFF1E FFFF1F FFFF20 0 1 2 FFFF1F FFFF20 0 1 2 FFFF20 Comparison match signal WDT_CLK output clock Figure IV.7.4.5.1 Clock Output of Watchdog Timer IV-7-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.5 Control Register Details I Table IV.7.5.1 List of Watchdog Timer Control Registers Address 0x00048160 0x00048162 0x00048164 0x00048166 0x00048168 0x0004816A 0x0004816C Register name Watchdog Timer Write-Protect Register (pWD_WP) Watchdog Timer Enable Register (pWD_EN) Watchdog Timer Comparison Data Setup Register 0 (pWD_COMP_LOW) Watchdog Timer Comparison Data Setup Register 1 (pWD_COMP_HIGH) Watchdog Timer Count Register 0 (pWD_CNT_LOW) Watchdog Timer Count Register 1 (pWD_CNT_HIGH) Watchdog Timer Control Register (pWD_CNTL) Function Size 16 Enables/disables WDT control registers for writing. 16 Configures and starts watchdog timer. 16 Sets comparison data (16 low-order bits). 16 Sets comparison data (14 high-order bits). 16 16 16 Watchdog timer counter data (16 low-order bits) Watchdog timer counter data (14 high-order bits) Resets watchdog timer. The following describes the watchdog timer control registers. The watchdog timer control registers are mapped to the 16-bit device area at addresses 0x48160 to 0x4816C, and can be accessed in units of half-words or bytes. IV WDT S1C33401 TECHNICAL MANUAL EPSON IV-7-7 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) 0x48160: Watchdog Timer Write-Protect Register (pWD_WP) Register name Address Bit 0048160 Watchdog (HW) timer writeprotect register (pWD_WP) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D[15:0] Name Function WDPTC15 Watchdog timer register writeWDPTC14 protect WDPTC13 WDPTC12 WDPTC11 WDPTC10 WDPTC9 WDPTC8 WDPTC7 WDPTC6 WDPTC5 WDPTC4 WDPTC3 WDPTC2 WDPTC1 WDPTC0 Setting Init. R/W Writing 0x0096 removes the write protection of the watchdog timer enable and comparison data registers (0x48162-0x48166). Writing another value set the write protection. X X X X X X X X X X X X X X X X W Remarks 0 when being read. WDPTC[15:0]: Watchdog Timer Write-Protect Bits These bits set or clear write protection at addresses 0x48162 to 0x48166. 0x0096 (W): Clears write protection Other than 0x0096 (W): Applies write protection (default, indeterminate value) 0x0000 (R): Always 0x0000 when read Before altering the Watchdog Timer Enable Register (0x48162) or Watchdog Timer Comparison Data Registers (0x48164, 0x48166), write 0x0096 to this register to remove write protection. Setting this register to other than 0x0096 will result in the contents of the registers above not being altered even when executing the write instruction without any problem. Once write protection is removed by writing 0x0096 to this register, said registers can be rewritten any number of times until this register is set to other than 0x0096. When the clock control registers have been rewritten, be sure to write other than 0x0096 to this register to prevent erroneous writing to said registers. IV-7-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) 0x48162: Watchdog Timer Enable Register (pWD_EN) Register name Address Watchdog timer enable register (pWD_EN) Bit Name 0048162 D15-7 - D6 CLKSEL (HW) D5 CLKEN D4 RUNSTP D3-2 - D1 NMIEN D0 RESEN Function reserved Watchdog timer input clock select Watchdog timer clock output control Watchdog timer Run/Stop control reserved Watchdog timer NMI enable Watchdog timer RESET enable Setting - 1 External clock 0 1 On 0 1 Run 0 - 1 Enabled 0 1 Enabled 0 I Init. R/W Internal clock Off Stop Disabled Disabled - 0 0 0 - 0 0 Remarks - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W Note: This register is write-protected to prevent NMI or reset signals from being inadvertently generated by unnecessary write operations. To rewrite this register, write protection must be removed by writing 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160). Once the register has been rewritten, be sure to write other than 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160) to reapply write protection. D[15:7] Reserved D6 CLKSEL: Watchdog Timer Input Clock Select Bit This bit selects the count clock for the watchdog timer. 1 (R/W): External clock (EXCL0) 0 (R/W): Internal clock (PCLK) (default) Setting this bit to 0 (default) selects the internal clock (PCLK); setting it to 1 selects the external clock (EXCL0). Before an external clock can be used, the function of the pin set by default as an I/O port must be switched to EXCL0 (external clock input for 16-bit timer 0) by using the Port Function Select Register. For details about pin functions and how to switch over, see Section I.3.3, "Switching Over Multiplexed Pin Functions." D5 CLKEN: Watchdog Timer Clock Output Control Bit This bit controls the clock output of the watchdog timer. 1 (R/W): On 0 (R/W): Off (default) IV Setting this bit to 1 outputs an NMI/reset generation cycle-synchronous clock from the IC. Before this clock output can be used, however, the function of the pin set by default as an I/O port must be switched to WDT_CLK (watchdog timer clock output) by using the Port Function Select Register. For details about pin functions and how to switch over, see Section I.3.3, "Switching Over Multiplexed Pin Functions." D4 RUNSTP: Watchdog Timer Run/Stop Control Bit This bit starts or stops the watchdog timer. 1 (R/W): Start 0 (R/W): Stop (default) WDT When the NMI or reset generation function is enabled, be sure to set comparison data and reset the watchdog timer before starting the watchdog timer, thus preventing the generation of unnecessary NMI or reset signals. D[3:2] Reserved S1C33401 TECHNICAL MANUAL EPSON IV-7-9 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) D1 NMIEN: Watchdog Timer NMI Enable Bit This bit enables NMI signal output by the watchdog timer. 1 (R/W): Enable 0 (R/W): Disable (default) Setting this bit to 1 outputs an NMI signal (a pulse 32 PCLK clocks in width) to the CMU when the count of the up-counter matches the value set in the comparison data register. Setting this bit to 0 outputs no NMI signals. Regardless of how this bit is set, the up-counter is reset to 0 when the up-counter and set value of the comparison data register match, then starts counting all over again. D0 RESEN: Watchdog Timer RESET Enable Bit This bit enables internal reset signal output by the watchdog timer. 1 (R/W): Enable 0 (R/W): Disable (default) Setting this bit to 1 outputs a reset signal (a pulse 32 PCLK clocks in width) to the CMU when the count of the up-counter matches the value set in the comparison data register. Setting this bit to 0 outputs no reset signals. IV-7-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) 0x48164: Watchdog Timer Comparison Data Setup Register 0 (pWD_COMP_LOW) 0x48166: Watchdog Timer Comparison Data Setup Register 1 (pWD_COMP_HIGH) Register name Address 0048164 Watchdog (HW) timer comparison data setup register 0 (pWD_COMP_LOW) Name Function Setting CMPDT15 CMPDT14 CMPDT13 CMPDT12 CMPDT11 CMPDT10 CMPDT9 CMPDT8 CMPDT7 CMPDT6 CMPDT5 CMPDT4 CMPDT3 CMPDT2 CMPDT1 CMPDT0 - CMPDT29 CMPDT28 CMPDT27 CMPDT26 CMPDT25 CMPDT24 CMPDT23 CMPDT22 CMPDT21 CMPDT20 CMPDT19 CMPDT18 CMPDT17 CMPDT16 Watchdog timer comparison data CMPDT0 = LSB 0x0 to 0x3FFFFFFF (low-order 16 bits) reserved Watchdog timer comparison data CMPDT29 = MSB - 0x0 to 0x3FFFFFFF (high-order 14 bits) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048166 D15-14 Watchdog D13 (HW) timer D12 comparison D11 data setup D10 register 1 D9 (pWD_COMP_HIGH) D8 D7 D6 D5 D4 D3 D2 D1 D0 Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W - 0 when being read. R/W Note: These registers are write-protected to prevent NMI or reset signals from being inadvertently generated by unnecessary write operations. To rewrite these registers, write protection must be removed by writing 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160). Once the registers have been rewritten, be sure to write other than 0x0096 (HW) to the Watchdog Timer Write-Protect Register (0x48160) to reapply write protection. Use these registers to set the NMI/reset generation cycle. With NMI or reset generation enabled, an NMI or reset signal is output when the up-counter matches the comparison data set in these registers. When a clock is output from the watchdog timer, these registers also set the output clock cycle. D[15:0]/0x48164 CMPDT[15:0]: Watchdog Timer Comparison Data (16 low-order bits) The 16 low-order bits of comparison data are set in these bits. (Default: 0x0000) D[13:0]/0x48166 CMPDT[29:16]: Watchdog Timer Comparison Data (14 high-order bits) The 14 high-order bits of comparison data are set in these bits. (Default: 0x0000) Note: Do not set a value equal to or less than 0x0000001F as comparison data. S1C33401 TECHNICAL MANUAL EPSON I IV-7-11 IV WDT IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) 0x48168: Watchdog Timer Count Register 0 (pWD_CNT_LOW) 0x4816A: Watchdog Timer Count Register 1 (pWD_CNT_HIGH) Register name Address 0048168 Watchdog (HW) timer count register 0 (pWD_CNT_LOW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004816A D15-14 Watchdog D13 (HW) timer count D12 register 1 D11 (pWD_CNT_HIGH) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name CTRDT15 CTRDT14 CTRDT13 CTRDT12 CTRDT11 CTRDT10 CTRDT9 CTRDT8 CTRDT7 CTRDT6 CTRDT5 CTRDT4 CTRDT3 CTRDT2 CTRDT1 CTRDT0 - CTRDT29 CTRDT28 CTRDT27 CTRDT26 CTRDT25 CTRDT24 CTRDT23 CTRDT22 CTRDT21 CTRDT20 CTRDT19 CTRDT18 CTRDT17 CTRDT16 Function Setting Watchdog timer counter data CTRDT0 = LSB 0x0 to 0x3FFFFFFF (low-order 16 bits) reserved Watchdog timer counter data CTRDT29 = MSB - 0x0 to 0x3FFFFFFF (high-order 14 bits) Init. R/W X X X X X X X X X X X X X X X X - X X X X X X X X X X X X X X Remarks R - R 0 when being read. The current count value of the up-counter can be read out from these registers. D[15:0]/0x48168 CTRDT[15:0]: Watchdog Timer Count Data (16 low-order bits) The 16 low-order bits of the 30-bit up-counter are read out from these bits. (Default: indeterminate) D[13:0]/0x4816A CTRDT[29:16]: Watchdog Timer Count Data (14 high-order bits) The 14 high-order bits of the 30-bit up-counter are read out from these bits. (Default: indeterminate) IV-7-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) 0x4816C: Watchdog Timer Control Register (pWD_CNTL) Register name Address Bit Name Function reserved Watchdog timer 004816C D15-1 - control register (HW) D0 WDRESEN Watchdog timer reset (pWD_CNTL) D[15:1] Reserved D0 WDRESEN: Watchdog Timer Reset Bit This bit resets the watchdog timer. 1 (W): Reset 0 (W): Has no effect 0 (R): Always 0 when read (default) Setting - 1 Reset 0 Invalid I Init. R/W - - 0 W Remarks 0 when being read. With NMI or reset signal output enabled, the watchdog timer must be reset by writing 1 to this bit within the set NMI/reset generation cycle. The up-counter is thereby reset to 0, then starts counting NMI/reset generation cycles all over again. IV WDT S1C33401 TECHNICAL MANUAL EPSON IV-7-13 IV C33 ADV BASIC PERIPHERAL BLOCK: WATCHDOG TIMER (WDT) IV.7.6 Precautions * When NMI or reset signal output by the watchdog timer is enabled, the watchdog timer must be reset within the set NMI/reset generation cycle. * Do not set a value equal to or less than 0x0000001F in the comparison data register. * Depending on the counter and comparison register values, an NMI or reset signal may be generated after the NMI or reset function is enabled, or immediately after the watchdog timer starts. Always be sure to set comparison data and reset the watchdog timer before writing 1 to NMIEN (D1/0x48162), RESEN (D0/0x48162), or RUNSTP (D4/0x48162). NMIEN: Watchdog Timer NMI Enable Bit in the Watchdog Timer Enable Register (D1/0x48162) RESEN: Watchdog Timer RESET Enable Bit in the Watchdog Timer Enable Register (D0/0x48162) RUNSTP: Watchdog Timer Run/Stop Control Bit in the Watchdog Timer Enable Register (D4/0x48162) IV-7-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8 Serial Interface (SIO) I IV.8.1 Configuration of Serial Interfaces IV.8.1.1 Features of Serial Interfaces The C33 ADV Basic Peripheral Block contains four channels (Ch.0, Ch.1, Ch.2 and Ch.3) of serial interfaces, the features of which are described below. The functions of these four serial interfaces are the same. * A clock-synchronized or asynchronous mode can be selected for the transfer method. Clock-synchronized mode Data length: 8 bits, fixed (No start, stop, and parity bits) Receive error: An overrun error can been detected. Asynchronous mode Data length: 7 or 8 bits, selectable Receive error: Overrun, framing, or parity errors can been detected. Start bit: 1 bit, fixed Stop bit: 1 or 2 bits, selectable Parity bit: Even, odd, or none; selectable Since the transmit and receive units are independent, full-duplex communication is possible. * Baud-rate setting: Any desired baud rate can be set by selecting the prescaler's division ratio, setting the 8-bit timer, or using external clock input (asynchronous mode only). Up to 8 Mbps transfer in clock-synchronized mode or up to 1 Mbps transfer in asynchronous mode are possible. * 4-byte receive buffer (FIFO) and 2-byte transmit buffer (FIFO) are built in, allowing for successive receive and transmit operations. * Data transfers using IDMA or HSDMA are possible. * Three types of interrupts (transmit buffer empty, receive buffer full, and receive error) can be generated. IV Figure IV.8.1.1.1 shows the configuration of the serial interface (one channel). Internal data bus Control registers Transmit unit Receive unit SOUTx Serial output control circuit 2-byte FIFO and shift register 4-byte FIFO and shift register SINx Serial input control circuit Transmit data buffer empty interrupt request Interrupt control circuit Receive error interrupt request Ready signal control circuit Start bit detection circuit Clock control circuit #SCLKx Receive data buffer full interrupt request SIO #SRDYx 8-bit timer output Figure IV.8.1.1.1 Configuration of Serial Interface Note: Ch.0 to Ch.3 have the same configuration and the same function. The signal and control bit names are suffixed by a 0, 1, 2, or 3 to indicate the channel number, enabling discrimination between channels 0 to 3. In this manual, however, channel numbers 0 to 3 are replaced with `x' unless discrimination is necessary, because explanations are common to all four channels. S1C33401 TECHNICAL MANUAL EPSON IV-8-1 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.1.2 I/O Pins of Serial Interface Table IV.8.1.2.1 lists the I/O pins used by the serial interface. Table IV.8.1.2.1 Serial-Interface Pin Configuration Pin name SIN0 SOUT0 #SCLK0 #SRDY0 SIN1 SOUT1 #SCLK1 #SRDY1 SIN2 SOUT2 #SCLK2 #SRDY2 SIN3 SOUT3 #SCLK3 #SRDY3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Serial IF Ch.0 data input Serial IF Ch.0 data output Serial IF Ch.0 clock input/output Serial IF Ch.0 ready input/output Serial IF Ch.1 data input Serial IF Ch.1 data output Serial IF Ch.1 clock input/output Serial IF Ch.1 ready input/output Serial IF Ch.2 data input Serial IF Ch.2 data output Serial IF Ch.2 clock input/output Serial IF Ch.2 ready input/output Serial IF Ch.3 data input Serial IF Ch.3 data output Serial IF Ch.3 clock input/output Serial IF Ch.3 ready input/output SINx (serial-data input pin) This pin is used to input serial data to the device, regardless of the transfer mode. SOUTx (serial-data output pin) This pin is used to output serial data from the device, regardless of the transfer mode. #SCLKx (clock input/output pin) This pin is used to input or output a clock. In the clock-synchronized slave mode, it is used as a clock input pin; in the clock-synchronized master mode, it is used as a clock output pin. In the asynchronous mode, this pin is used as clock input when an external clock is used. This pin is not used when the internal clock is used, so it can be used as an I/O port. #SRDYx (ready-signal input/output pin) This pin is used to input or output the ready signal that is used in the clock-synchronized mode. In the clock-synchronized slave mode, it is used as a ready-signal output pin; in the clock-synchronized master mode, it is used as a ready-signal input pin. This pin is not used in the asynchronous mode, so it can be used as an I/O port. Notes: * The list above indicates the input/output pins that the serial interface can accommodate. Depending on the C33 ADV model used, all output pins (all channels) may not be available. * The serial interface input/output pins are shared with general-purpose I/O ports or other peripheral circuit inputs/outputs, so that functionality in the initial state may be set to other than the serial interface input/output. Before the serial interface input/output signals assigned to these pins can be used, the function of these pins must be switched for the serial interface input/output by setting the corresponding Port Function Select Registers. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." IV-8-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.1.3 Setting Transfer Mode I The transfer mode of the serial interface can be set using SMDx[1:0] individually for each channel as shown in Table IV.8.1.3.1 below. SMD0[1:0]: Serial I/F Ch.0 Transfer Mode Select Bits in the Serial I/F Ch.0 Control Register (D[1:0]/0x401E3) SMD1[1:0]: Serial I/F Ch.1 Transfer Mode Select Bits in the Serial I/F Ch.1 Control Register (D[1:0]/0x401E8) SMD2[1:0]: Serial I/F Ch.2 Transfer Mode Select Bits in the Serial I/F Ch.2 Control Register (D[1:0]/0x401F3) SMD3[1:0]: Serial I/F Ch.3 Transfer Mode Select Bits in the Serial I/F Ch.3 Control Register (D[1:0]/0x401F8) Table IV.8.1.3.1 Transfer Mode SMDx1 SMDx0 1 1 0 0 1 0 1 0 Transfer mode 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode At initial reset, SMDx[1:0] becomes indeterminate, so be sure to initialize it in the software. When using the IrDA interface, set the transfer mode for the asynchronous 7-bit or asynchronous 8-bit mode. The input/output pins are configured differently, depending on the transfer mode. The pin configuration in each mode is shown in Table IV.8.1.3.2. Table IV.8.1.3.2 Pin Configuration by Transfer Mode Transfer mode 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode SINx SOUTx #SCLKx #SRDYx Data input Data input Data input Data input Data output Data output Data output Data output Clock input/P port Clock input/P port Clock input Clock output P port P port Ready output Ready input All four pins are used in the clock-synchronized mode. In the asynchronous mode, since #SRDYx is unused, the #SRDYx pin can be used as an I/O (P) port. In addition, when an external clock is not used, the #SCLKx pin can also be used as an I/O port. The I/O control and data registers for the I/O ports used in the serial interface can be used as general-purpose read/ write registers. IV Note: To enable the IrDA interface to be set, IRMDx[1:0] is provided. Since these bits become indeterminate at initial reset, be sure to initialize them by writing 0b00 when using as the normal interface or 0b10 when using as the IrDA interface. IRMD0[1:0]: Serial I/F Ch.0 Interface Mode Select Bits in the Serial I/F Ch.0 IrDA Register (D[1:0]/0x401E4) IRMD1[1:0]: Serial I/F Ch.1 Interface Mode Select Bits in the Serial I/F Ch.1 IrDA Register (D[1:0]/0x401E9) IRMD2[1:0]: Serial I/F Ch.2 Interface Mode Select Bits in the Serial I/F Ch.2 IrDA Register (D[1:0]/0x401F4) IRMD3[1:0]: Serial I/F Ch.3 Interface Mode Select Bits in the Serial I/F Ch.3 IrDA Register (D[1:0]/0x401F9) SIO S1C33401 TECHNICAL MANUAL EPSON IV-8-3 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.1.4 Serial Interface Operating Clock The serial interface use the peripheral circuit clock (PCLK) generated by the CMU as the operating clock. Furthermore, each channel uses the source clock supplied from the 8-bit timer for data transfer. Controlling the supply of the operating clock PCLK is supplied to the serial interface with default settings. It can be turned off using SIOCLK (D4/0x40180) to reduce the amount of power consumed on the chip if all the serial interface functions are not used. SIOCLK: Serial Interface Clock Control Bit in the Peripheral Clock Control Register 1 (D4/0x40180) Setting SIOCLK (D4/0x40180) to 0 (1 by default) turns off the PCLK clock supply to the serial interface. When the clock supply is turned off, the serial interface control registers cannot be accessed. For details on how to set and control PCLK, refer to Section II.3, "Clock Management Unit (CMU)." Clock for data transfer The source clock for data transfer is supplied from an 8-bit timer. Any desired clock frequency can be selected by setting the division ratio of the prescaler and the reload data of the 8-bit timer as necessary. For setting the transfer clock, refer to Sections IV.8.2.2 and IV.8.3.2. Clock state in standby mode The clock supply to the serial interface stops depending on type of standby mode. HALT mode: The operating and transfer clocks are supplied the same way as in normal mode. HALT2 mode: The operating and transfer clocks are supplied the same way as in normal mode. SLEEP mode: The operating and transfer clock supply stops. Therefore, the serial interface also stops operating when in SLEEP modes. IV.8.1.5 Standard Mode and Advanced Mode The serial interface in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV serial interface has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table IV.8.1.5.1 shows differences between standard mode and advanced mode. Table IV.8.1.5.1 Differences between Standard Mode and Advanced Mode Function #SRDY mask control Number of received data in the buffer to generate a receive-buffer full interrupt Standard mode Advanced mode Disabled One Enabled One to four can be specified. To configure the serial interface in advanced mode, set SIOADV (D0/0x401FF) to 1. The control bits for the extended functions are enabled to write after this setting. At initial reset, SIOADV (D0/0x401FF) is set to 0 and the serial interface enters standard mode. SIOADV: Standard Mode/Advanced Mode Select Bit in the Serial Interface STD/ADV Mode Select Register (D0/0x401FF) The following descriptions unless otherwise specified are common contents for both modes. The extended functions in advanced mode are explained assuming that SIOADV (D0/0x401FF) has been set to 1. Note: Standard or advanced mode currently set is applied to all the serial interface channels. It cannot be selected for each channel individually. IV-8-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.2 Clock-Synchronized Interface I IV.8.2.1 Outline of Clock-Synchronized Interface In the clock-synchronized transfer mode, 8 bits of data are synchronized to the common clock on both the transmit and receive sides when the data is transferred. Since the transmit unit has 2-byte buffer and the receive unit has 4-byte buffer (FIFO), successive transmit and receive operations are possible. Since the clock line is shared between the transmit and receive units, the communication mode is half-duplex. Master and slave modes Either the clock-synchronized master mode or the clock-synchronized slave mode can be selected using SMDx[1:0]. SMD0[1:0]: Serial I/F Ch.0 Transfer Mode Select Bits in the Serial I/F Ch.0 Control Register (D[1:0]/0x401E3) SMD1[1:0]: Serial I/F Ch.1 Transfer Mode Select Bits in the Serial I/F Ch.1 Control Register (D[1:0]/0x401E8) SMD2[1:0]: Serial I/F Ch.2 Transfer Mode Select Bits in the Serial I/F Ch.2 Control Register (D[1:0]/0x401F3) SMD3[1:0]: Serial I/F Ch.3 Transfer Mode Select Bits in the Serial I/F Ch.3 Control Register (D[1:0]/0x401F8) Clock-synchronized master mode (SMDx[1:0] = 00) In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as the master, can be performed using the internal clock to synchronize the operation of the internal shift registers. The synchronizing clock is output from the #SCLKx pin, enabling an external (slave side) serial input/output device to be controlled. The #SRDYx pin is also used to input a signal that indicates whether the external serial input/output device is ready to transmit or receive (when ready in a low level). Clock-synchronized slave mode (SMDx[1:0] = 01) In this mode, clock-synchronized 8-bit serial transfers, in which the serial interface functions as a slave, can be performed using the synchronizing clock that is supplied by an external (master side) serial input/output device. The synchronizing clock is input from the #SCLKx pin for use as the synchronizing clock of the serial interface. In addition, a #SRDYx signal indicating whether the serial interface is ready to transmit or receive (when ready in a low level) is output from the #SRDYx pin. IV Figure IV.8.2.1.1 shows an example of how the input/output pins are connected in the clock-synchronized mode. S1C33 S1C33 External serial device Data input SINx External serial device SINx Data input SOUTx Data output SOUTx Data output #SCLKx Clock input #SCLKx Clock output #SRDYx Ready output #SRDYx Ready input (1) Master mode SIO (2) Slave mode Figure IV.8.2.1.1 Example of Connection in Clock-Synchronized Mode Clock-synchronized transfer data format In clock-synchronized transfers, the data format is fixed as shown below. Data length: 8 bits Start bit: None Stop bit: None Parity bit: None #SCLKx Data LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 Figure IV.8.2.1.2 Clock-Synchronized Transfer Data Format Serial data is transmitted and received starting with the LSB. S1C33401 TECHNICAL MANUAL EPSON IV-8-5 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.2.2 Setting Clock-Synchronized Interface When performing clock-synchronized transfers via the serial interface, the following settings must be made before data transfer is actually begun: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting the receive FIFO level 6. Setting interrupts and IDMA/HSDMA The following explains the content of each setting. For details on interrupt/DMA settings, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Note: Always make sure the serial interface is inactive (TXENx and RXENx = 0) before these settings are made. A change of settings during operation may cause a malfunction. TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) Setting input/output pins All four pins--SINx, SOUTx, #SCLKx, and #SRDYx--are used in the clock-synchronized mode. Configure the Port Function Select Registers to enable these pin functions according to the channel to be used (two or more channel can be used simultaneously). For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." Setting the interface mode IRMDx[1:0] is used to set the interface mode (normal or IrDA interface). Write 0b00 to IRMDx[1:0] to choose the ordinary interface. Since IRMDx[1:0] becomes indeterminate at initial reset, it must be initialized. IRMD0[1:0]: Serial I/F Ch.0 Interface Mode Select Bits in the Serial I/F Ch.0 IrDA Register (D[1:0]/0x401E4) IRMD1[1:0]: Serial I/F Ch.1 Interface Mode Select Bits in the Serial I/F Ch.1 IrDA Register (D[1:0]/0x401E9) IRMD2[1:0]: Serial I/F Ch.2 Interface Mode Select Bits in the Serial I/F Ch.2 IrDA Register (D[1:0]/0x401F4) IRMD3[1:0]: Serial I/F Ch.3 Interface Mode Select Bits in the Serial I/F Ch.3 IrDA Register (D[1:0]/0x401F9) Setting the transfer mode Use SMDx[1:0] to set the transfer mode of the serial interface as described earlier. When using the serial interface as the master for clock-synchronized transfer, set SMDx[1:0] to 0b00; when using the serial interface as a slave, set SMDx[1:0] to 0b01. Setting the input clock * Clock-synchronized master mode This mode operates using an internally derived clock. The clock source for each channel is as follows: Ch.0: A clock output by 8-bit timer 2 Ch.1: A clock output by 8-bit timer 3 Ch.2: A clock output by 8-bit timer 4 Ch.3: A clock output by 8-bit timer 5 Therefore, in order for the serial interface to be used in the clock-synchronized master mode, the following conditions must be met: 1. The prescaler is feeding a clock to the 8-bit timer corresponding to the serial interface channel to be used. 2. The 8-bit timer is generating a clock. IV-8-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Any desired clock frequency can be selected by setting the division ratio of the prescaler and the reload data of the 8-bit timer as necessary. The relationship between the contents of these settings and the transfer rate is expressed by Eq. 1 below. To ensure that the duty ratio of the clock to be fed to the serial interface is 50%, the 8-bit timer further divides the underflow signal frequency by 2 internally. This 1/2 frequency division is factored into Eq. 1. fPCLK x pdr RLD = -------- - 1 2 x bps RLD: fPCLK: bps: pdr: I (Eq. 1) Reload data register setup value of the 8-bit timer Peripheral clock frequency (Hz) Transfer rate (bits/second) Division ratio of the prescaler For details on how to control the prescaler and 8-bit timers, refer to Section IV.4, "Prescaler (PSC)" and Section IV.5, "8-Bit Timers (T8)." The serial-interface control register contains SSCKx to select the clock source used for the asynchronous mode. Although this bit does not affect the clock in the clock-synchronized mode, its content becomes indeterminate at initial reset. Therefore, be sure to initialize this bit by writing 0 (Internal clock), even when using the serial interface in the clock-synchronized master mode. SSCK0: Serial I/F Ch.0 Input Clock Select Bit in the Serial I/F Ch.0 Control Register (D2/0x401E3) SSCK1: Serial I/F Ch.1 Input Clock Select Bit in the Serial I/F Ch.1 Control Register (D2/0x401E8) SSCK2: Serial I/F Ch.2 Input Clock Select Bit in the Serial I/F Ch.2 Control Register (D2/0x401F3) SSCK3: Serial I/F Ch.3 Input Clock Select Bit in the Serial I/F Ch.3 Control Register (D2/0x401F8) * Clock-synchronized slave mode This mode operates using the clock that is output by the external master. This clock is input from the #SCLKx pin. Therefore, there is no need to control the prescaler or 8-bit timer. Initialize SSCKx by writing 1 (#SCLKx). IV Setting the receive FIFO level (advanced mode) This serial interface incorporates a 4-byte receive FIFO allowing up to 4 bytes of data that can be received without an error even when the receive data register is not read. This serial interface can generate a receivebuffer full interrupt when the specified number of data are received in the receive FIFO. Use FIFOINTx[1:0] to set this number of data. Writing 0-3 to FIFOINTx[1:0] sets the number of data to 1-4. The default setting at initial reset is 0 so that a receive-buffer full interrupt will generate when one data is received. FIFOINT0[1:0]: Serial I/F Ch.0 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.0 IrDA Register (D[6:5]/0x401E4) FIFOINT1[1:0]: Serial I/F Ch.1 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.1 IrDA Register (D[6:5]/0x401E9) FIFOINT2[1:0]: Serial I/F Ch.2 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.2 IrDA Register (D[6:5]/0x401F4) FIFOINT3[1:0]: Serial I/F Ch.3 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.3 IrDA Register (D[6:5]/0x401F9) S1C33401 TECHNICAL MANUAL EPSON IV-8-7 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.2.3 Control and Operation of Clock-Synchronized Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. When transmit is enabled by writing 1 to this bit, the clock input to the shift register is enabled (ready for input), thus allowing for data to be transmitted. The synchronizing clock input/output of the #SCLKx pin is also enabled (ready for input/output). Transmit is disabled and the transmit data buffer (FIFO) is cleared by writing 0 to TXENx. TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) After the port function select register is set for the serial input/output, the I/O direction of the #SRDYx and #SCLKx pins are changed at follows: #SRDYx: When slave mode is set, a switch is made to output mode. Otherwise, input mode is maintained. #SCLKx: When master mode is set, a switch is made to output mode. Otherwise, input mode is maintained. Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. Therefore, TXENx and receive-enable bit RXENx cannot be enabled simultaneously. When transmitting data, fix RXENx at 0 and do not change it during a transmit operation. In addition, make sure TXENx is not set to 0 during a transmit operation. (2) Transmit procedure The serial interface contains a transmit shift register and a transmit data register, which are provided independently of those used for a receive operation. Transmit data is written to TXDx[7:0]. The data written to TXDx[7:0] enters the transmit data buffer and waits for transmission. TXD0[7:0]: Serial I/F Ch.0 Transmit Data Bits in the Serial I/F Ch.0 Transmit Data Register (D[7:0]/0x401E0) TXD1[7:0]: Serial I/F Ch.1 Transmit Data Bits in the Serial I/F Ch.1 Transmit Data Register (D[7:0]/0x401E5) TXD2[7:0]: Serial I/F Ch.2 Transmit Data Bits in the Serial I/F Ch.2 Transmit Data Register (D[7:0]/0x401F0) TXD3[7:0]: Serial I/F Ch.3 Transmit Data Bits in the Serial I/F Ch.3 Transmit Data Register (D[7:0]/0x401F5) The transmit data buffer is a 2-byte FIFO and up to two data can be written to it successively if empty. Older data will be transmitted first and cleared after transmission. The next transmit data can be written to the transmit data register, even during data transmission. The transmit data buffer status flag TDBEx is provided to check whether this buffer is full or not. This flag is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing transmit data. TDBE0: Serial I/F Ch.0 Transmit Data Buffer Empty Flag in the Serial I/F Ch.0 Status Register (D1/0x401E2) TDBE1: Serial I/F Ch.1 Transmit Data Buffer Empty Flag in the Serial I/F Ch.1 Status Register (D1/0x401E7) TDBE2: Serial I/F Ch.2 Transmit Data Buffer Empty Flag in the Serial I/F Ch.2 Status Register (D1/0x401F2) TDBE3: Serial I/F Ch.3 Transmit Data Buffer Empty Flag in the Serial I/F Ch.3 Status Register (D1/0x401F7) The serial interface starts transmitting when data is written to the transmit data register. The transfer status can be checked using the transmit-completion flag TENDx. This flag goes 1 when data is being transmitted and goes 0 when the transmission has completed. TEND0: Serial I/F Ch.0 Transmit-Completion Flag in the Serial I/F Ch.0 Status Register (D5/0x401E2) TEND1: Serial I/F Ch.1 Transmit-Completion Flag in the Serial I/F Ch.1 Status Register (D5/0x401E7) TEND2: Serial I/F Ch.2 Transmit-Completion Flag in the Serial I/F Ch.2 Status Register (D5/0x401F2) TEND3: Serial I/F Ch.3 Transmit-Completion Flag in the Serial I/F Ch.3 Status Register (D5/0x401F7) IV-8-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) When data is transmitted successively in clock-synchronized master mode, TENDx maintains 1 until all data is transmitted (Figure IV.8.2.3.1). In slave mode, TENDx goes 0 every time 1-byte data is transmitted (Figure IV.8.2.3.2). I When all the data in the transmit data buffer are transferred, a cause of the transmit-data empty interrupt occurs. Since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing routine. In addition, since this cause of interrupt can be used to invoke DMA, the data prepared in memory can be transmitted successively to the transmit-data register through DMA transfers. For details on how to control interrupts and DMA requests, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Following explains transmit operation in both the master and slave modes. * Clock-synchronized master mode The timing at which the device starts transmitting in the master mode is as follows: When #SRDYx is on a low level while the transmit-data buffer contains data written to it or when data has been written to the transmit-data buffer while #SRDYx is on a low level. Figure IV.8.2.3.1 shows a transmit timing chart in the clock-synchronized master mode. #SCLKx A #SRDYx SOUTx TDBEx B B A A B D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D1 C B D6 D7 D TENDx Transmit-buffer empty interrupt request A Slave device receives the LSB. B Slave device receives the MSB. Transmit-buffer empty interrupt request IV C First data is written. (2 bytes) D Next data is written. (2 bytes) Figure IV.8.2.3.1 Transmit Timing Chart in Clock-Synchronized Master Mode 1. If the #SRDYx signal from the slave is on a high level, the master waits until it is on a low level (ready to receive). 2. If #SRDYx is on a low level, the synchronizing clock input to the serial interface begins. The synchronizing clock is also output from the #SCLKx pin to the slave device. 3. The content of the data buffer is transferred to the shift register synchronously with the first falling edge of the clock. At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. If the transmit data buffer becomes empty at this point, a transmit-buffer empty interrupt request occurs. 4. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. The slave device takes in each bit synchronously with the rising edges of the synchronizing clock. 5. The next data transfer begins if the transmit data buffer contains other data. S1C33401 TECHNICAL MANUAL EPSON IV-8-9 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * Clock-synchronized slave mode Figure IV.8.2.3.2 shows a transmit timing chart in the clock-synchronized slave mode. #SCLKx SOUTx D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D1 D6 D7 #SRDYx TDBEx A B TENDx Transmit-buffer empty interrupt request Transmit-buffer empty interrupt request A First data is written. (2 bytes) B Next data is written. (2 bytes) Figure IV.8.2.3.2 Transmit Timing Chart in Clock-Synchronized Slave Mode 1. After setting the #SRDYx signal to a low level (ready to transmit), the slave waits for clock input from the master. 2. When the synchronizing clock is input from the #SCLKx pin, the content of the data register is transferred to the shift register synchronously with the first falling edge of the clock. At the same time, the LSB of the data transferred to the shift register is output from the SOUTx pin. The #SRDYx signal is returned to a high level at this point. 3. The data in the shift register is shifted 1 bit by the next falling edge of the clock, and the bit following the LSB is output from SOUTx. This operation is repeated until all 8 bits of data are transmitted. 4. The #SRDYx signal is set to a low level when the last bit (8th bit) is output from the SOUTx pin. The master device takes in each bit synchronously with the rising edges of the synchronizing clock. 5. The next data transfer begins if the transmit data buffer contains other data. (3) Terminating transmit operation Upon completion of data transmission, write 0 to the transmit-enable bit TXENx to disable transmit operation. This operation clears (initializes) the transmit data buffer (FIFO), therefore, make sure that the transmit data buffer does not contain any data waiting for transmission before writing 0 to TXENx. IV-8-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Receive control I (1) Enabling receive operation Use the receive-enable bit RXENx for receive control. When receive operations are enabled by writing 1 to this bit, clock input to the shift register is enabled (ready for input), thereby starting a data-receive operation. The synchronizing clock input/output on the #SCLKx pin also is enabled (ready for input/output). Receive operations are disabled and the receive data buffer (FIFO) is cleared by writing 0 to RXENx. RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) After the port function select register is set for the serial input/output, the I/O direction of the #SRDYx and #SCLKx pins are changed at follows: #SRDYx: When slave mode is set, a switch is made to output mode. Otherwise, input mode is maintained. #SCLKx: When master mode is set, a switch is made to output mode. Otherwise, input mode is maintained. Note: In clock-synchronized transfers, the clock line is shared between the transmit and receive units, so the communication mode is half-duplex. Therefore, RXENx and transmit-enable bit TXENx cannot be enabled simultaneously. When receiving data, fix TXENx at 0 and do not change it during a receive operation. In addition, make sure RXENx is not set to 0 during a receive operation. (2) Receive procedure This serial interface has a receive shift register, receive data buffer and a receive data register that are provided independently of those used for transmit operations. The received data enters the received data buffer. The receive data buffer is a 4-byte FIFO and can receive data until it becomes full unless the received data is not read out. The received data in the buffer can be read by accessing RXDx[7:0]. The older data is output first and cleared by reading. IV RXD0[7:0]: Serial I/F Ch.0 Receive Data Bits in the Serial I/F Ch.0 Receive Data Register (D[7:0]/0x401E1) RXD1[7:0]: Serial I/F Ch.1 Receive Data Bits in the Serial I/F Ch.1 Receive Data Register (D[7:0]/0x401E6) RXD2[7:0]: Serial I/F Ch.2 Receive Data Bits in the Serial I/F Ch.2 Receive Data Register (D[7:0]/0x401F1) RXD3[7:0]: Serial I/F Ch.3 Receive Data Bits in the Serial I/F Ch.3 Receive Data Register (D[7:0]/0x401F6) The number of data in the receive data buffer can be checked by reading RXDxNUM[1:0]. When RXDxNUM[1:0] is 0, the buffer contains 0 or 1 data. When RXDxNUM[1:0] is 1-3, the buffer contains 2-4 data. RXD0NUM[1:0]: Number of Ch.0 Receive Data in FIFO in the Serial I/F Ch.0 Status Register (D[7:6]/0x401E2) RXD1NUM[1:0]: Number of Ch.1 Receive Data in FIFO in the Serial I/F Ch.1 Status Register (D[7:6]/0x401E7) RXD2NUM[1:0]: Number of Ch.2 Receive Data in FIFO in the Serial I/F Ch.2 Status Register (D[7:6]/0x401F2) RXD3NUM[1:0]: Number of Ch.3 Receive Data in FIFO in the Serial I/F Ch.3 Status Register (D[7:6]/0x401F7) Furthermore, RDBFx is provided for indicating whether the received data buffer is empty or not. This flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. RDBF0: Serial I/F Ch.0 Receive Data Buffer Full Flag in the Serial I/F Ch.0 Status Register (D0/0x401E2) RDBF1: Serial I/F Ch.1 Receive Data Buffer Full Flag in the Serial I/F Ch.1 Status Register (D0/0x401E7) RDBF2: Serial I/F Ch.2 Receive Data Buffer Full Flag in the Serial I/F Ch.2 Status Register (D0/0x401F2) RDBF3: Serial I/F Ch.3 Receive Data Buffer Full Flag in the Serial I/F Ch.3 Status Register (D0/0x401F7) When the receive data buffer has received the specified number or more data (one in standard mode or one to four in advanced mode), a cause of the receive-data full interrupt occurs. Since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. In addition, since this cause of interrupt can be used to invoke DMA, the received data can be received successively in locations prepared in memory through DMA transfers. For details on how to control interrupts/DMA, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." The following describes a receive operation in the master and slave modes. S1C33401 TECHNICAL MANUAL EPSON IV-8-11 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * Clock-synchronized master mode Figure IV.8.2.3.3 shows a receive timing chart in the clock-synchronized master mode. #SCLKx data 1 SINx data 2 data 3 data 4 data 6 data 5 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 Receive data buffer data 1 1, 2 1, 2, 3 2, 3 2, 3, 4 2, 3, 4, 5 2 3 A RXDxNUM[1:0] 1 0 2 1 RDBFx #SRDYx (SRDYCTLx = 0) Receive-buffer full interrupt request (FIFOINTx[1:0] = 2) Overrun error interrupt request A First data is read. Figure IV.8.2.3.3 Receive Timing Chart in Clock-Synchronized Master Mode 1. If the #SRDYx signal from the slave is on a high level, the master waits until it turns to a low level (ready to receive). 2. If #SRDYx is on a low level, synchronizing clock input to the serial interface begins. The synchronizing clock is also output from the #SCLKx pin to the slave device. 3. The slave device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 4. This serial interface takes the SINx input into the shift register at the rising edges of the clock. The data in the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data is received. 5. When the MSB is taken in, the data in the shift register is transferred to the receive data buffer, enabling the data to be read out. * Clock-synchronized slave mode Figure IV.8.2.3.4 shows a receive timing chart in the clock-synchronized slave mode. #SCLKx data 1 SINx data 2 data 3 data 4 data 5 data 6 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 Receive data buffer data 1 1, 2 1, 2, 3 2, 3 2, 3, 4 2, 3, 4, 5 2 3 A RXDxNUM[1:0] 0 1 2 A 1 RDBFx #SRDYx (SRDYCTLx = 0) Receive-buffer full interrupt request (FIFOINTx[1:0] = 2) Overrun error interrupt request A Data (1 byte ) is read. Figure IV.8.2.3.4 Receive Timing Chart in Clock-Synchronized Slave Mode 1. After setting the #SRDYx signal to a low level (ready to receive), the slave waits for clock input from the master. 2. The master device outputs each bit of data synchronously with the falling edges of the clock. The LSB is output first. 3. This serial interface takes the SINx input into the shift register at the rising edges of the clock that is input from #SCLKx. The data in the shift register is sequentially shifted as bits are taken in. This operation is repeated until the MSB of data is received. 4. When the MSB is taken in, the data in the shift register is transferred to the receive data buffer, enabling the data to be read out. IV-8-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) (3) Overrun error Even when the receive data buffer is full (4 data have been received), the next (5th) data can be received into the shift register. If there is no space in the buffer (data has not been read) when the 5th data has been received, the 5th data in the shift register cannot be transferred to the buffer. If one more (6th) data is transferred to this serial interface, the shift register (5th data) is overwritten with the 6th data and an overrun error is generated. When an overrun error is generated, the overrun error flag OERx is set to 1. Once the overrun error flag is set to 1, it remains set until it is reset by writing 0 to it in the software. I OER0: Serial I/F Ch.0 Overrun Error Flag in the Serial I/F Ch.0 Status Register (D2/0x401E2) OER1: Serial I/F Ch.1 Overrun Error Flag in the Serial I/F Ch.1 Status Register (D2/0x401E7) OER2: Serial I/F Ch.2 Overrun Error Flag in the Serial I/F Ch.2 Status Register (D2/0x401F2) OER3: Serial I/F Ch.3 Overrun Error Flag in the Serial I/F Ch.3 Status Register (D2/0x401F7) The overrun error is one of the receive-error interrupt causes in the serial interface. An interrupt can be generated for this error by setting the interrupt controller as necessary, so that the error can be processed by an interrupt processing routine. Generation of overrun error can be disabled by controlling the #SRDYx as shown below. (4) Controlling the #SRDYx signal (advanced mode) When the slave device is in receive mode, the #SRDYx signal is output from the slave device to the master device to notify whether the slave device is ready to receive data or not. When this serial interface is in the clock-synchronized slave mode, the #SRDYx signal is turned to a low level by writing 1 to RXENx to enable receive operations, thereby indicating to the master device that the slave is ready to receive. When the LSB of data is received, #SRDYx is turned to a high level; when the MSB is received, #SRDYx is returned to a low level, in preparation for the next receive operation. If an overrun error occurs, #SRDYx is turned to a high level (unable to receive) at that point, so receive operations for the following data are suspended. In this case, #SRDYx is returned to low by reading out the receive data buffer, and if any receive data follows, the slave restarts receiving data. In the normal mode, the #SRDYx signal indicating ready to receive is output even if the receive data buffer is full. If the receive data buffer cannot be read in this case, an overrun error occurs in the next data transfer. To prevent this error, the serial interface provides #SRDYx high mask mode. In this mode, if the receive data buffer is full, the #SRDYx signal is forcibly fixed at high in order to suspend data transfer from the master device until the data in the buffer is read. To use this function, set SRDYCTLx to 1. IV SRDYCTL0: Serial I/F Ch.0 #SRDY Control Bit in the Serial I/F Ch.0 IrDA Register (D7/0x401E4) SRDYCTL1: Serial I/F Ch.1 #SRDY Control Bit in the Serial I/F Ch.1 IrDA Register (D7/0x401E9) SRDYCTL2: Serial I/F Ch.2 #SRDY Control Bit in the Serial I/F Ch.2 IrDA Register (D7/0x401F4) SRDYCTL3: Serial I/F Ch.3 #SRDY Control Bit in the Serial I/F Ch.3 IrDA Register (D7/0x401F9) This function is effective in the clock-synchronized master mode as well. In this case, the #SRDYx signal (low) from the slave device is ignored when the receive data buffer is full and the serial interface stops outputting the #SCLKx signal until the buffer data is read. When the receive data buffer is not full, normal receive operation is performed even if this function is enabled. S1C33401 TECHNICAL MANUAL EPSON IV-8-13 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Clock-synchronized master mode #SCLKx data 1 SINx data 2 data 3 data 4 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 Receive data buffer data 1 RXDxNUM[1:0] 0 data 5 D0 D1 *** D6 D7 1, 2 1, 2, 3 1, 2, 3, 4 2, 3, 4 1 2 3 2 A RDBFx #SRDYx (SRDYCTLx = 1) A First data is read. The clock output stops while FIFO is full. Clock-synchronized slave mode #SCLKx data 1 SINx Receive data buffer RXDxNUM[1:0] data 2 data 3 data 4 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 D7 D0 D1 *** D6 data 1 0 data 5 D7 D0 D1 *** D6 1, 2 1, 2, 3 1, 2, 3, 4 2, 3, 4 1 2 3 2 A RDBFx #SRDYx (SRDYCTLx = 1) A First data is read. #SRDYx is fixed at high while FIFO is full. Figure IV.8.2.3.5 #SRDYx High Mask Mode (5) Terminating receive operation Upon completion of a data receive operation, write 0 to the receive-enable bit RXENx to disable receive operations. This operation clears (initializes) the receive data buffer (FIFO), therefore, make sure that there is no data that has not been read in the receive data buffer before setting RXENx to 0. IV-8-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.3 Asynchronous Interface I IV.8.3.1 Outline of Asynchronous Interface Asynchronous transfers are performed by adding a start bit and a stop bit to the start and end points of each serialconverted data. With this method, there is no need to use a clock that is fully synchronized on the transmit and receive sides; instead, transfer operations are timed by the start and stop bits added to the start and end points of each data. In the 8-bit asynchronous mode (SMDx[1:0] = 0b11), 8 bits of data can be transferred; in the 7-bit asynchronous mode (SMDx[1:0] = 0b10), 7 bits of data can be transferred. SMD0[1:0]: Serial I/F Ch.0 Transfer Mode Select Bits in the Serial I/F Ch.0 Control Register (D[1:0]/0x401E3) SMD1[1:0]: Serial I/F Ch.1 Transfer Mode Select Bits in the Serial I/F Ch.1 Control Register (D[1:0]/0x401E8) SMD2[1:0]: Serial I/F Ch.2 Transfer Mode Select Bits in the Serial I/F Ch.2 Control Register (D[1:0]/0x401F3) SMD3[1:0]: Serial I/F Ch.3 Transfer Mode Select Bits in the Serial I/F Ch.3 Control Register (D[1:0]/0x401F8) In either mode, it is possible to select the stop-bit length, add a parity bit, and choose between even and odd parity. The start bit is fixed at 1. The operating clock can be selected between an internal clock generated by an 8-bit timer or an external clock that is input from the #SCLKx pin. Since the transmit unit has 2-byte buffer and the receive unit has 4-byte buffer (FIFO), successive transmit and receive operations are possible. Furthermore, since the transmit and receive units are independent, full-duplex communication in which transmit and receive operations are performed simultaneously is also possible. Figure IV.8.3.1.1 shows an example of how input/output pins are connected for transfers in the asynchronous mode. S1C33 S1C33 External serial device SINx Data output SOUTx Data output #SCLKx Data input SINx Data input SOUTx External serial device External clock (1) When external clock is used (2) When internal clock is used IV Figure IV.8.3.1.1 Example of Connection in Asynchronous Mode When the asynchronous mode is selected, it is possible to use the IrDA interface function. Asynchronous-transfer data format The data format for asynchronous transfer is shown below. Data length: 7 or 8 bits (determined by the selected transfer mode) Start bit: 1 bit, fixed Stop bit: 1 or 2 bits Parity bit: Even or odd parity, or none SIO Sampling clock (for transmitting) 7-bit asynchronous mode (Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2 (Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 2 bits, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 s2 s3 (Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 p s2 (Stop bit: 1 bit, parity: none) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 (Stop bit: 1 bit, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 (Stop bit: 2 bits, parity: non) s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 (Stop bit: 2 bits, parity: used) s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 8-bit asynchronous mode s3 s3 s1: start bit, s2 & s3: stop bit, p: parity bit Figure IV.8.3.1.2 Data Format for Asynchronous Transfer Serial data is transmitted and received, starting with the LSB. S1C33401 TECHNICAL MANUAL EPSON IV-8-15 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.3.2 Setting Asynchronous Interface When performing asynchronous transfer via the serial interface, the following must be done before data transfer can be started: 1. Setting input/output pins 2. Setting the interface mode 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting the receive FIFO level 7. Setting interrupt/IDMA/HSDMA The following describes how to set each of the above. For details on interrupt/DMA settings, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Note: Always make sure the serial interface is inactive (TXENx and RXENx = 0) before making these settings. A change in settings during operation may result in a malfunction. TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) Setting input/output pins In the asynchronous mode, two pins--SINx and SOUTx--are used. When external clock input is used, one more pin, #SCLKx, is also used. Configure the Port Function Select Registers to enable these pin functions according to the channel to be used (two or more channel can be used simultaneously). For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." Setting the interface mode IRMDx[1:0] is used to set the IrDA interface. Since IRMDx[1:0] becomes indeterminate at initial reset, initialize it by writing 0b00 when using the serial interface as a normal interface, or 0b10 when using the serial interface as an IrDA interface. This setting must be made before a transfer mode is set. IRMD0[1:0]: Serial I/F Ch.0 Interface Mode Select Bits in the Serial I/F Ch.0 IrDA Register (D[1:0]/0x401E4) IRMD1[1:0]: Serial I/F Ch.1 Interface Mode Select Bits in the Serial I/F Ch.1 IrDA Register (D[1:0]/0x401E9) IRMD2[1:0]: Serial I/F Ch.2 Interface Mode Select Bits in the Serial I/F Ch.2 IrDA Register (D[1:0]/0x401F4) IRMD3[1:0]: Serial I/F Ch.3 Interface Mode Select Bits in the Serial I/F Ch.3 IrDA Register (D[1:0]/0x401F9) Setting the transfer mode Use SMDx[1:0] to set the transfer mode of the serial interface as described earlier. When using the serial interface in the 8-bit asynchronous mode, set SMDx[1:0] to 0b11, when using the serial interface in the 7-bit asynchronous mode, set SMDx[1:0] to 0b10. Setting the input clock In the asynchronous mode, the operating clock can be selected between the internal clock and an external clock using SSCKx. SSCK0: Serial I/F Ch.0 Input Clock Select Bit in the Serial I/F Ch.0 Control Register (D2/0x401E3) SSCK1: Serial I/F Ch.1 Input Clock Select Bit in the Serial I/F Ch.1 Control Register (D2/0x401E8) SSCK2: Serial I/F Ch.2 Input Clock Select Bit in the Serial I/F Ch.2 Control Register (D2/0x401F3) SSCK3: Serial I/F Ch.3 Input Clock Select Bit in the Serial I/F Ch.3 Control Register (D2/0x401F8) The external clock is selected (input from the #SCLKx pin) by writing 1 to SSCKx, and an internal clock is selected by writing 0. Note: SSCKx becomes indeterminate at initial reset, so be sure to reset it in the software. IV-8-16 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * Internal clock When the internal clock is selected, the serial interface is clocked by a clock generated using an 8-bit timer. The clock source for each channel is as follows: Ch.0: Clock output by 8-bit timer 2 Ch.1: Clock output by 8-bit timer 3 Ch.2: Clock output by 8-bit timer 4 Ch.3: Clock output by 8-bit timer 5 I Therefore, before the internal clock can be used, the following conditions must be met: 1. The prescaler is outputting a clock to the 8-bit timer corresponding to the serial interface channel to be used. 2. The 8-bit timer is outputting a clock. Any desired clock frequency can be obtained by setting the prescaler division ratio and the reload data of the 8-bit timer as necessary. The relationship between the contents of these setting and the transfer rate is expressed by Eq. 2. The 8-bit timer has its underflow signal further divided by 2 internally, in order to ensure that the duty ratio of the clock supplied to the serial interface is 50%. Furthermore, the clock output by the 8-bit timer is divided by 16 or 8 internally in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. These division ratios are taken into account in Eq. 2. fPCLK x pdr x sdr RLD = ------------ - 1 2 x bps RLD: fPCLK: bps: pdr: sdr: (Eq. 2) Set value of the 8-bit timer's reload data register Peripheral clock frequency (Hz) Transfer rate (bits/second) Division ratio of the prescaler Internal division ratio of the serial interface (1/16 or 1/8) Table IV.8.3.2.1 shows examples of prescaler division ratios and the reload data settings of the 8-bit timer, in cases in which the internal division ratio of the serial interface is set to 1/16. IV Table IV.8.3.2.1 Example of Transfer Rate Settings Transfer rate (bps) RLD 300 1200 2400 4800 9600 14400 28800 129 129 129 64 32 21 10 fPCLK = 20 MHz pdr Error (%) 1/16 1/4 1/2 1/2 1/2 1/2 1/2 RLD 0.16025 0.16025 0.16025 0.16025 -1.35732 -1.35732 -1.35732 fPCLK = 25 MHz pdr Error (%) 162 162 162 80 40 13 13 1/16 1/4 1/2 1/2 1/2 1/4 1/2 RLD -0.14698 -0.14698 -0.14698 -0.46939 -0.75584 -3.11880 -3.11880 216 216 216 108 53 35 17 fPCLK = 33 MHz pdr Error (%) 1/16 1/4 1/2 1/2 1/2 1/2 1/2 0.00640 0.00640 0.00640 -0.45234 0.46939 0.46939 0.46939 Make sure the error is within 1%. Calculate the error using the following equation: fPCLK x pdr Error = {-------------- - 1} x 100 [%] (RLD + 1) x 32 x bps For details on how to control the prescaler and 8-bit timers, refer to Section IV.4, "Prescaler (PSC)" and Section IV.5, "8-Bit Timers (T8)." S1C33401 TECHNICAL MANUAL EPSON IV-8-17 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * External clock When an external clock is selected, the serial interface is clocked by a clock input from the #SCLKx pin. Therefore, there is no need to control the prescaler and 8-bit timers. Any desired clock frequency can be set. The clock input from the #SCLKx pin is internally divided by 16 or 8 in the serial interface, in order to create a sampling clock (refer to "Sampling clock"). This division ratio must also be considered when setting the transfer rate. * Sampling clock In the asynchronous mode, TCLK (the clock output by the 8-bit timer or input from the #SCLKx pin) is internally divided in the serial interface, in order to create a sampling clock. A 1/16 division ratio is selected by writing 0 to DIVMDx , and a 1/8 ratio is selected by writing 1. DIVMD0: Serial I/F Ch.0 Clock Division Ratio Select Bit in the Serial I/F Ch.0 IrDA Register (D4/0x401E4) DIVMD1: Serial I/F Ch.1 Clock Division Ratio Select Bit in the Serial I/F Ch.1 IrDA Register (D4/0x401E9) DIVMD2: Serial I/F Ch.2 Clock Division Ratio Select Bit in the Serial I/F Ch.2 IrDA Register (D4/0x401F4) DIVMD3: Serial I/F Ch.3 Clock Division Ratio Select Bit in the Serial I/F Ch.3 IrDA Register (D4/0x401F9) Note: DIVMDx becomes indeterminate at initial reset, so be sure to reset it in the software. Settings of this bit are valid only in the asynchronous mode (and when using the IrDA interface). For receiving Start bit SINx 1 D0 8 1 8 TCLK Sampling clock 8xTCLK 16xTCLK Sampling of start bit Sampling of D0 bit Figure IV.8.3.2.1 Sampling Clock for Asynchronous Receive Operation (when 1/16 division is selected) Each bit data is sampled in the timing shown in Figure IV.8.3.2.1. When the SINx input signal is detected as a low level at the rising edge of TCLK, sampling for the start bit is performed 8xTCLK (4xTCLK when 1/8 division is selected) after that point. If a low level is not detected in the sampling for the start bit, the interface aborts the subsequent samplings and returns to the start bit detection phase (in this case no error occurs). When the SINx input signal is low at the start bit sampling, subsequent bit data is sampled in 16xTCLK cycles (8x TCLK cycles when 1/8 division is selected). For transmitting 1 8 16 TCLK Sampling clock SOUTx 16xTCLK Start bit D0 Figure IV.8.3.2.2 Sampling Clock for Asynchronous Transmit Operation (when 1/16 division is selected) During transmission, each bit data is output from the SOUTx pin in 16xTCLK cycles (8xTCLK cycles when 1/8 division is selected). IV-8-18 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Setting the data format I In the asynchronous mode, the data length is 7 or 8 bits as determined by the transfer mode set. The start bit is fixed at 1. The stop and parity bits can be set as shown in the Table IV.8.3.2.2 using STPBx, EPRx and PMDx. Table IV.8.3.2.2 Serial I/F Control Bits Item Stop-bit select Parity enable Parity-mode select Ch.0 (Serial I/F Ch.0 control register) Ch.1 (Serial I/F Ch.1 control register) Ch.2 (Serial I/F Ch.2 control register) Ch.3 (Serial I/F Ch.3 control register) STPB0(D3/0x401E3) EPR0(D5/0x401E3) PMD0(D4/0x401E3) STPB1(D3/0x401E8) EPR1(D5/0x401E8) PMD1(D4/0x401E8) STPB2(D3/0x401F3) EPR2(D5/0x401F3) PMD2(D4/0x401F3) STPB3(D3/0x401F8) EPR3(D5/0x401F8) PMD3(D4/0x401F8) STPB0: Serial I/F Ch.0 Stop-Bit Length Select Bit in the Serial I/F Ch.0 Control Register (D3/0x401E3) STPB1: Serial I/F Ch.1 Stop-Bit Length Select Bit in the Serial I/F Ch.1 Control Register (D3/0x401E8) STPB2: Serial I/F Ch.2 Stop-Bit Length Select Bit in the Serial I/F Ch.2 Control Register (D3/0x401F3) STPB3: Serial I/F Ch.3 Stop-Bit Length Select Bit in the Serial I/F Ch.3 Control Register (D3/0x401F8) EPR0: Serial I/F Ch.0 Parity Enable Bit in the Serial I/F Ch.0 Control Register (D5/0x401E3) EPR1: Serial I/F Ch.1 Parity Enable Bit in the Serial I/F Ch.1 Control Register (D5/0x401E8) EPR2: Serial I/F Ch.2 Parity Enable Bit in the Serial I/F Ch.2 Control Register (D5/0x401F3) EPR3: Serial I/F Ch.3 Parity Enable Bit in the Serial I/F Ch.3 Control Register (D5/0x401F8) PMD0: Serial I/F Ch.0 Parity Mode Select Bit in the Serial I/F Ch.0 Control Register (D4/0x401E3) PMD1: Serial I/F Ch.1 Parity Mode Select Bit in the Serial I/F Ch.1 Control Register (D4/0x401E8) PMD2: Serial I/F Ch.2 Parity Mode Select Bit in the Serial I/F Ch.2 Control Register (D4/0x401F3) PMD3: Serial I/F Ch.3 Parity Mode Select Bit in the Serial I/F Ch.3 Control Register (D4/0x401F8) Table IV.8.3.2.3 Stop Bit and Parity Bit Settings STPBx EPRx 1 1 0 0 1 0 PMDx Stop bit Parity bit 1 2 bits Odd 0 2 bits Even 2 bits None 1 1 bit Odd 0 1 bit Even 1 bit Non Setting PMDx is invalid when EPRx = 0. IV Note: These bits become indeterminate at initial reset, so be sure to initialize them in the software. Setting the receive FIFO level (advanced mode) This serial interface incorporates a 4-byte receive FIFO allowing up to 4 bytes of data that can be received without an error even when the receive data register is not read. This serial interface can generate a receivebuffer full interrupt when the specified number of data are received in the receive FIFO. Use FIFOINTx[1:0] to set this number of data. Writing 0-3 to FIFOINTx[1:0] sets the number of data to 1-4. The default setting at initial reset is 0 so that a receive-buffer full interrupt will generate when one data is received. FIFOINT0[1:0]: Serial I/F Ch.0 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.0 IrDA Register (D[6:5]/0x401E4) FIFOINT1[1:0]: Serial I/F Ch.1 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.1 IrDA Register (D[6:5]/0x401E9) FIFOINT2[1:0]: Serial I/F Ch.2 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.2 IrDA Register (D[6:5]/0x401F4) FIFOINT3[1:0]: Serial I/F Ch.3 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.3 IrDA Register (D[6:5]/0x401F9) S1C33401 TECHNICAL MANUAL EPSON IV-8-19 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.3.3 Control and Operation of Asynchronous Transfer Transmit control (1) Enabling transmit operation Use the transmit-enable bit TXENx for transmit control. When transmit is enabled by writing 1 to this bit, the clock input to the shift register is enabled (ready for input), thus allowing data to be transmitted. Transmit is disabled and the transmit data buffer (FIFO) is cleared by writing 0 to TXENx. TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) Note: Do not set TXENx to 0 during a transmit operation. (2) Transmit procedure The serial interface contains a transmit shift register and a transmit data register, which are provided independently of those used for a receive operation. Transmit data is written to TXDx[7:0]. TXD0[7:0]: Serial I/F Ch.0 Transmit Data Bits in the Serial I/F Ch.0 Transmit Data Register (D[7:0]/0x401E0) TXD1[7:0]: Serial I/F Ch.1 Transmit Data Bits in the Serial I/F Ch.1 Transmit Data Register (D[7:0]/0x401E5) TXD2[7:0]: Serial I/F Ch.2 Transmit Data Bits in the Serial I/F Ch.2 Transmit Data Register (D[7:0]/0x401F0) TXD3[7:0]: Serial I/F Ch.3 Transmit Data Bits in the Serial I/F Ch.3 Transmit Data Register (D[7:0]/0x401F5) In the 7-bit asynchronous mode, bit 7 (MSB) in each register is ignored. The data written to TXDx[7:0] enters the transmit data buffer and waits for transmission. The transmit data buffer is a 2-byte FIFO and up to two data can be written to it successively if empty. Older data will be transmitted first and cleared after transmission. The next transmit data can be written to the transmit data register, even during data transmission. The transmit data buffer status flag TDBEx is provided to check whether this buffer is full or not. This flag is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing transmit data. TDBE0: Serial I/F Ch.0 Transmit Data Buffer Empty Flag in the Serial I/F Ch.0 Status Register (D1/0x401E2) TDBE1: Serial I/F Ch.1 Transmit Data Buffer Empty Flag in the Serial I/F Ch.1 Status Register (D1/0x401E7) TDBE2: Serial I/F Ch.2 Transmit Data Buffer Empty Flag in the Serial I/F Ch.2 Status Register (D1/0x401F2) TDBE3: Serial I/F Ch.3 Transmit Data Buffer Empty Flag in the Serial I/F Ch.3 Status Register (D1/0x401F7) The serial interface starts transmitting when data is written to the transmit data register. The transfer status can be checked using the transmit-completion flag TENDx. This flag goes 1 when data is being transmitted and goes 0 when the transmission has completed. TEND0: Serial I/F Ch.0 Transmit-Completion Flag in the Serial I/F Ch.0 Status Register (D5/0x401E2) TEND1: Serial I/F Ch.1 Transmit-Completion Flag in the Serial I/F Ch.1 Status Register (D5/0x401E7) TEND2: Serial I/F Ch.2 Transmit-Completion Flag in the Serial I/F Ch.2 Status Register (D5/0x401F2) TEND3: Serial I/F Ch.3 Transmit-Completion Flag in the Serial I/F Ch.3 Status Register (D5/0x401F7) When all the data in the transmit data buffer are transferred, a cause of the transmit-data empty interrupt occurs. Since an interrupt can be generated as set by the interrupt controller, the next piece of transmit data can be written using an interrupt processing routine. In addition, since this cause of interrupt can be used to invoke DMA, the data prepared in memory can be transmitted successively to the transmit-data register through DMA transfers. For details on how to control interrupts and DMA requests, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Figure IV.8.3.3.1 shows a transmit timing chart in the asynchronous mode. IV-8-20 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Example: Data length 8 bits Stop bit 1 bit Parity bit Included I Sampling clock SOUTx TDBEx S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1 A D7 P S2 S1 D0 D1 D7 P S2 S1 D0 D1 D7 P S2 B TENDx Transmit-buffer empty interrupt request S1 Start bit S2 Stop bit P Parity bit Transmit-buffer empty interrupt request A First data is written. (2 bytes) B Next data is written. (2 bytes) Figure IV.8.3.3.1 Transmit Timing Chart in Asynchronous Mode 1. The contents of the data register are transferred to the shift register synchronously with the first falling edge of the sampling clock. At the same time, the SOUTx pin is setting to a low level to send the start bit. 2. Each bit of data in the shift register is transmitted beginning with the LSB at each falling edge of the subsequent sampling clock. This operation is repeated until all 8 (or 7) bits of data are transmitted. 3. After sending the MSB, the parity bit (if EPRx = 1) and the stop bit are transmitted in succession. EPR0: Serial I/F Ch.0 Parity Enable Bit in the Serial I/F Ch.0 Control Register (D5/0x401E3) EPR1: Serial I/F Ch.1 Parity Enable Bit in the Serial I/F Ch.1 Control Register (D5/0x401E8) EPR2: Serial I/F Ch.2 Parity Enable Bit in the Serial I/F Ch.2 Control Register (D5/0x401F3) EPR3: Serial I/F Ch.3 Parity Enable Bit in the Serial I/F Ch.3 Control Register (D5/0x401F8) 4. The next data transfer begins if the transmit data buffer contains other data. (3) Terminating transmit operations When data transmission is completed, write 0 to the transmit-enable bit TXENx to disable transmit operations. This operation clears (initializes) the transmit data buffer (FIFO), therefore, make sure that the transmit data buffer does not contain any data waiting for transmission before writing 0 to TXENx. IV SIO S1C33401 TECHNICAL MANUAL EPSON IV-8-21 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Receive control (1) Enabling receive operations Use the receive-enable bit RXENx for receive control. When receiving enabled by writing 1 to this bit, clock input to the shift register is enabled (ready for input), meaning that it is ready to receive data. Receive operations are disabled and the receive data buffer (FIFO) is cleared by writing 0 to RXENx. RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) Note: Do not set RXENx to 0 during a receive operation. (2) Receive procedure This serial interface has a receive shift register, receive data buffer and a receive data register that are provided independently of those used for transmit operations. The received data enters the received data buffer. The receive data buffer is a 4-byte FIFO and can receive data until it becomes full unless the received data is not read out. The received data in the buffer can be read by accessing RXDx[7:0]. The older data is output first and cleared by reading. RXD0[7:0]: Serial I/F Ch.0 Receive Data Bits in the Serial I/F Ch.0 Receive Data Register (D[7:0]/0x401E1) RXD1[7:0]: Serial I/F Ch.1 Receive Data Bits in the Serial I/F Ch.1 Receive Data Register (D[7:0]/0x401E6) RXD2[7:0]: Serial I/F Ch.2 Receive Data Bits in the Serial I/F Ch.2 Receive Data Register (D[7:0]/0x401F1) RXD3[7:0]: Serial I/F Ch.3 Receive Data Bits in the Serial I/F Ch.3 Receive Data Register (D[7:0]/0x401F6) The number of data in the receive data buffer can be checked by reading RXDxNUM[1:0]. When RXDxNUM[1:0] is 0, the buffer contains 0 or 1 data. When RXDxNUM[1:0] is 1-3, the buffer contains 2-4 data. RXD0NUM[1:0]: Number of Ch.0 Receive Data in FIFO in the Serial I/F Ch.0 Status Register (D[7:6]/0x401E2) RXD1NUM[1:0]: Number of Ch.1 Receive Data in FIFO in the Serial I/F Ch.1 Status Register (D[7:6]/0x401E7) RXD2NUM[1:0]: Number of Ch.2 Receive Data in FIFO in the Serial I/F Ch.2 Status Register (D[7:6]/0x401F2) RXD3NUM[1:0]: Number of Ch.3 Receive Data in FIFO in the Serial I/F Ch.3 Status Register (D[7:6]/0x401F7) Furthermore, RDBFx is provided for indicating whether the received data buffer is empty or not. This flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. RDBF0: Serial I/F Ch.0 Receive Data Buffer Full Flag in the Serial I/F Ch.0 Status Register (D0/0x401E2) RDBF1: Serial I/F Ch.1 Receive Data Buffer Full Flag in the Serial I/F Ch.1 Status Register (D0/0x401E7) RDBF2: Serial I/F Ch.2 Receive Data Buffer Full Flag in the Serial I/F Ch.2 Status Register (D0/0x401F2) RDBF3: Serial I/F Ch.3 Receive Data Buffer Full Flag in the Serial I/F Ch.3 Status Register (D0/0x401F7) When the receive data buffer has received the specified number or more data (one in standard mode or one to four in advanced mode), a cause of the receive-data full interrupt occurs. Since an interrupt can be generated as set by the interrupt controller, the received data can be read by an interrupt processing routine. In addition, since this cause of interrupt can be used to invoke DMA, the received data can be received successively in locations prepared in memory through DMA transfers. For details on how to control interrupts/DMA, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Figure IV.8.3.3.2 shows a receive timing chart in the asynchronous mode. IV-8-22 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Example: Data length 8 bits Stop bit 1 bit Parity bit Included I Sampling clock data 1 SINx data 2 data 3 Receive data buffer data 1 RXDxNUM[1:0] data 5 data 6 0 1, 2 1, 2, 3 2, 3 2, 3, 4 2, 3, 4, 5 1 2 1 2 3 A RDBFx S1 Start bit S2 Stop bit data 4 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 P Parity bit A First data is read. Receive-buffer full interrupt request (FIFOINTx[1:0] = 2) Overrun error interrupt request Figure IV.8.3.3.2 Receive Timing Chart in Asynchronous Mode 1. The serial interface starts sampling when the start bit is input (SINx = low). 2. When the start bit is sampled at the first rising edge of the sampling clock, each bit of receive data is taken into the shift register, beginning with the LSB at each rising edge of the subsequent clock. This operation is repeated until the MSB of data is received. 3. When the MSB is taken in, the parity bit that follows is also taken in (if EPRx = 1). 4. When the stop bit is sampled, the data in the shift register is transferred to the receive data register, enabling the data to be read out. The parity is checked when data is transferred to the receive data register (if EPRx = 1). Note: The receive operation is terminated when the first stop bit is sampled even if the stop bit is configured with two bits. (3) Receive errors Three types of receive errors can be detected when receiving data in the asynchronous mode. Since an interrupt can be generated by setting the interrupt controller, the error can be processed using an interrupt processing routine. For details on receive error interrupts, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." IV * Parity error If EPRx is set to 1 (parity added), the parity is checked when data is received. This parity check is performed when the data received in the shift register is transferred to the receive data register in order to check conformity with PMDx settings (odd or even parity). PMD0: Serial I/F Ch.0 Parity Mode Select Bit in the Serial I/F Ch.0 Control Register (D4/0x401E3) PMD1: Serial I/F Ch.1 Parity Mode Select Bit in the Serial I/F Ch.1 Control Register (D4/0x401E8) PMD2: Serial I/F Ch.2 Parity Mode Select Bit in the Serial I/F Ch.2 Control Register (D4/0x401F3) PMD3: Serial I/F Ch.3 Parity Mode Select Bit in the Serial I/F Ch.3 Control Register (D4/0x401F8) SIO If any nonconformity is found in this check, a parity error is assumed and the parity error flag PERx is set to 1. PER0: Serial I/F Ch.0 Parity Error Flag in the Serial I/F Ch.0 Status Register (D3/0x401E2) PER1: Serial I/F Ch.1 Parity Error Flag in the Serial I/F Ch.1 Status Register (D3/0x401E7) PER2: Serial I/F Ch.2 Parity Error Flag in the Serial I/F Ch.2 Status Register (D3/0x401F2) PER3: Serial I/F Ch.3 Parity Error Flag in the Serial I/F Ch.3 Status Register (D3/0x401F7) Even when this error occurs, the received data in error is transferred to the receive data buffer and the receive operation is continued. However, the content of the received data for which a parity error is flagged cannot be guaranteed. PERx is reset to 0 by writing 0. S1C33401 TECHNICAL MANUAL EPSON IV-8-23 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * Framing error If data with a stop bit = 0 is received, the serial interface assumes that the data is out of synchronization and generates a framing error. If two stop bits are used, only the first stop bit is checked. When this error occurs, the framing-error flag FERx is set to 1. FER0: Serial I/F Ch.0 Framing Error Flag in the Serial I/F Ch.0 Status Register (D4/0x401E2) FER1: Serial I/F Ch.1 Framing Error Flag in the Serial I/F Ch.1 Status Register (D4/0x401E7) FER2: Serial I/F Ch.2 Framing Error Flag in the Serial I/F Ch.2 Status Register (D4/0x401F2) FER3: Serial I/F Ch.3 Framing Error Flag in the Serial I/F Ch.3 Status Register (D4/0x401F7) Even when this error occurs, the received data in error is transferred to the receive data register and the receive operation is continued. However, the content of the received data for which a framing error is flagged cannot be guaranteed, even if no framing error is found in the following data received. The FERx flag is reset to 0 by writing 0. * Overrun error Even when the receive data buffer is full (4 data have been received), the next (5th) data can be received into the shift register. If there is no space in the buffer (data has not been read) when the 5th data has been received, the 5th data in the shift register cannot be transferred to the buffer. If one more (6th) data is transferred to this serial interface, the shift register (5th data) is overwritten with the 6th data and an overrun error is generated. When an overrun error is generated, the overrun error flag OERx is set to 1. OER0: Serial I/F Ch.0 Overrun Error Flag in the Serial I/F Ch.0 Status Register (D2/0x401E2) OER1: Serial I/F Ch.1 Overrun Error Flag in the Serial I/F Ch.1 Status Register (D2/0x401E7) OER2: Serial I/F Ch.2 Overrun Error Flag in the Serial I/F Ch.2 Status Register (D2/0x401F2) OER3: Serial I/F Ch.3 Overrun Error Flag in the Serial I/F Ch.3 Status Register (D2/0x401F7) Even when this error occurs, the receive operation is continued. OERx is reset to 0 by writing 0. (4) Terminating receive operation When a data receive operation is completed, write 0 to the receive-enable bit RXENx to disable receive operations. This operation clears (initializes) the receive data buffer (FIFO), therefore, make sure that there is no data that has not been read in the receive data buffer before setting RXENx to 0. IV-8-24 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.4 IrDA Interface I IV.8.4.1 Outline of IrDA Interface Each channel of the serial interface contains a RZI modulator circuit, allowing an infrared-ray communication circuit to be configured based on IrDA 1.0 simply by adding a simple external circuit. Infrared communication module S1C33 RZI Modulator LED A SOUTx LED TXD VP1N LED C Serial I/F RZI Modulator Photodiode SINx RXD CX1 VDD Vcc CX2 VSS VP1N GND (Example: HP HSDL-1000) Figure IV.8.4.1.1 Configuration Example of IrDA Interface This IrDA interface function can be used only when the selected transfer mode is an asynchronous mode. Since the contents of the asynchronous mode are applied directly for the serial-interface functions other than the IrDA interface unit, refer to Section IV.8.3, "Asynchronous Interface," for details on how to set and control the data formats and data transfers. IV IV.8.4.2 Setting IrDA Interface When performing infrared-ray communication, the following settings must be made before communication can be started: 1. Setting input/output pins 2. Selecting the interface mode (IrDA interface function) 3. Setting the transfer mode 4. Setting the input clock 5. Setting the data format 6. Setting the receive FIFO level 7. Setting the interrupt/IDMA/HSDMA 8. Setting the input/output logic The contents for items 1 through 6 have been explained in connection with the asynchronous interface. For details, refer to Section IV.8.3, "Asynchronous Interface." For details on item 7, refer to Section IV.8.5, "Serial Interface Interrupts and DMA." Note: Before making these settings, always make sure the serial interface is inactive (TXENx and RXENx are both set to 0), as a change in settings during operation could cause a malfunction. In addition, be sure to set the transfer mode in (3) and the following items before selecting the IrDA interface function in (2). TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) S1C33401 TECHNICAL MANUAL EPSON IV-8-25 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Selecting the IrDA interface function To use the IrDA interface function, select it using IRMDx[1:0] and then set the 8-bit (or 7-bit) asynchronous mode as the transfer mode. Table IV.8.4.2.1 Setting of IrDA Interface IRMDx1 IRMDx0 1 1 0 0 1 0 1 0 Interface mode Do not set. (reserved) IrDA 1.0 interface Do not set. (reserved) Normal interface IRMD0[1:0]: Serial I/F Ch.0 Interface Mode Select Bits in the Serial I/F Ch.0 IrDA Register (D[1:0]/0x401E4) IRMD1[1:0]: Serial I/F Ch.1 Interface Mode Select Bits in the Serial I/F Ch.1 IrDA Register (D[1:0]/0x401E9) IRMD2[1:0]: Serial I/F Ch.2 Interface Mode Select Bits in the Serial I/F Ch.2 IrDA Register (D[1:0]/0x401F4) IRMD3[1:0]: Serial I/F Ch.3 Interface Mode Select Bits in the Serial I/F Ch.3 IrDA Register (D[1:0]/0x401F9) Note: IRMDx[1:0] becomes indeterminate when initially reset, so be sure to initialize it in the software. Setting the input/output logic When using the IrDA interface, the logic of the input/output signals of the RZI modulator circuit can be changed in accordance with the infrared-ray communication module or the circuit connected externally to the chip. The logic of the internal serial interface is "active-low." If the input/output signals are active-high, the logic of these signals must be inverted before they can be used. The input SINx and output SOUTx logic can be set individually through the use of IRRLx and IRTLx, respectively. Table IV.8.4.2.2 IrDA Input/Output Logic Inversion Bits Item IrDA input logic inversion IrDA output logic inversion Ch.0 (Serial I/F Ch.0 control register) Ch.1 (Serial I/F Ch.1 control register) Ch.2 (Serial I/F Ch.2 control register) Ch.3 (Serial I/F Ch.3 control register) IRRL0(D2/0x401E4) IRRL1(D2/0x401E9) IRRL2(D2/0x401F4) IRRL3(D2/0x401F9) IRTL0(D3/0x401E4) IRTL1(D3/0x401E9) IRTL2(D3/0x401F4) IRTL3(D3/0x401F9) IRRL0: Serial I/F Ch.0 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.0 IrDA Register (D2/0x401E4) IRRL1: Serial I/F Ch.1 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.1 IrDA Register (D2/0x401E9) IRRL2: Serial I/F Ch.2 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.2 IrDA Register (D2/0x401F4) IRRL3: Serial I/F Ch.3 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.3 IrDA Register (D2/0x401F9) IRTL0: Serial I/F Ch.0 IrDA I/F Output Logic Inversion Bit in the Serial I/F Ch.0 IrDA Register (D3/0x401E4) IRTL1: Serial I/F Ch.1 IrDA I/F Output Logic Inversion Bit in the Serial I/F Ch.1 IrDA Register (D3/0x401E9) IRTL2: Serial I/F Ch.2 IrDA I/F Output Logic Inversion Bit in the Serial I/F Ch.2 IrDA Register (D3/0x401F4) IRTL3: Serial I/F Ch.3 IrDA I/F Output Logic Inversion Bit in the Serial I/F Ch.3 IrDA Register (D3/0x401F9) The logic of the input/output signal is inverted by writing 1 to each corresponding bit. Logic is not inverted if the bit is set to 0. When transmitting (1) IRTLx = 0 RZI modulator input (I/F output) RZI modulator output (SOUTx) (2) IRTLx = 1 RZI modulator input (I/F output) RZI modulator output (SOUTx) When receiving (1) IRRLx = 0 RZI modulator input (SINx) RZI modulator output (I/F input) (2) IRRLx = 1 RZI modulator input (SINx) RZI modulator output (I/F input) Figure IV.8.4.2.1 IRRLx and IRTLx Settings Note: IRRLx and IRTLx become indeterminate at initial reset, so be sure to initialize them in the software. IV-8-26 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.4.3 Control and Operation of IrDA Interface I The transmit/receive procedures have been explained in the section on the asynchronous interface, so refer to Section IV.8.3.3, "Control and Operation of Asynchronous Transfer." The following describes the data modulation and demodulation performed using the RZI modulator circuit: When transmitting During data transmission, the pulse width of the serial interface output signal is set to 3/16 before the signal is output from the SOUTx pin. TCLK 1 2 3 8 9 10 11 16 RZI modulator input (I/F output) 16xTCLK RZI modulator output (SOUTx) 3xTCLK Figure IV.8.4.3.1 Data Modulation by RZI Circuit When receiving During data reception, the pulse width of the input signal from SINx is set to 16/3 before the signal is transferred to the serial interface. TCLK 1 2 3 4 16 RZI modulator input (SINx) 3xTCLK RZI modulator output (I/F input) IV 16xTCLK Figure IV.8.4.3.2 Demodulation by RZI Circuit Notes: * When using the IrDA interface, set the internal division ratio of the serial interface 1/16 (DIVMDx = 1), rather than 1/8 (DIVMDx = 0). DIVMD0: Serial I/F Ch.0 Clock Division Ratio Select Bit in the Serial I/F Ch.0 IrDA Register (D4/0x401E4) DIVMD1: Serial I/F Ch.1 Clock Division Ratio Select Bit in the Serial I/F Ch.1 IrDA Register (D4/0x401E9) DIVMD2: Serial I/F Ch.2 Clock Division Ratio Select Bit in the Serial I/F Ch.2 IrDA Register (D4/0x401F4) DIVMD3: Serial I/F Ch.3 Clock Division Ratio Select Bit in the Serial I/F Ch.3 IrDA Register (D4/0x401F9) * Although Figure IV.8.4.3.2 shows the input signal as a low pulse of a 3xTCLK width, the RZI circuit recognizes low pulses by means of the signal edge (rising edge when IRRLx = 0; falling edge when IRRLx = 1). Note that noise may cause a malfunction. S1C33401 TECHNICAL MANUAL EPSON IV-8-27 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.5 Serial Interface Interrupts and DMA The serial interface can generate the following three types of interrupts in each channel: * Transmit-buffer empty interrupt * Receive-buffer full interrupt * Receive-error interrupt Transmit-buffer empty interrupt This cause of interrupt occurs when the transmit data set in the transmit data register is transferred to the shift register, in which case the cause-of-interrupt flag FSTXx is set to 1. At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Occurrence of this cause of interrupt indicates that the next transmit data can be written to the transmit data register. This cause of interrupt can also be used to invoke IDMA, enabling transmit data to be written to the register by means of a DMA transfer. Receive-buffer full interrupt This cause of interrupt occurs when the number of data specified with FIFOINTx[1:0] (one data in standard mode) has been received in the receive data buffer, in which case the cause-of-interrupt flag FSRXx is set to 1. At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Occurrence of this cause of interrupt indicates that the received data can be read out. This cause of interrupt can also be used to invoke IDMA, enabling the received data to be written into specified memory locations by means of a DMA transfer. FIFOINT0[1:0]: Serial I/F Ch.0 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.0 IrDA Register (D[6:5]/0x401E4) FIFOINT1[1:0]: Serial I/F Ch.1 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.1 IrDA Register (D[6:5]/0x401E9) FIFOINT2[1:0]: Serial I/F Ch.2 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.2 IrDA Register (D[6:5]/0x401F4) FIFOINT3[1:0]: Serial I/F Ch.3 Receive Buffer Full Interrupt Timing Select Bits in the Serial I/F Ch.3 IrDA Register (D[6:5]/0x401F9) Receive-error interrupt This cause of interrupt occurs when a parity, framing, or overrun error is detected during data reception, in which case the cause-of-interrupt flag FSERRx is set to 1. At this time, if the interrupt conditions set using the interrupt control register are met, an interrupt to the CPU is generated. Since all three types of errors generate the same cause of interrupt, check the error flags PERx (parity error), OERx (overrun error), and FERx (framing error) to identify the type of error that has occurred. In the clocksynchronized mode, parity and framing errors do not occur. PER0: Serial I/F Ch.0 Parity Error Flag in the Serial I/F Ch.0 Status Register (D3/0x401E2) PER1: Serial I/F Ch.1 Parity Error Flag in the Serial I/F Ch.1 Status Register (D3/0x401E7) PER2: Serial I/F Ch.2 Parity Error Flag in the Serial I/F Ch.2 Status Register (D3/0x401F2) PER3: Serial I/F Ch.3 Parity Error Flag in the Serial I/F Ch.3 Status Register (D3/0x401F7) OER0: Serial I/F Ch.0 Overrun Error Flag in the Serial I/F Ch.0 Status Register (D2/0x401E2) OER1: Serial I/F Ch.1 Overrun Error Flag in the Serial I/F Ch.1 Status Register (D2/0x401E7) OER2: Serial I/F Ch.2 Overrun Error Flag in the Serial I/F Ch.2 Status Register (D2/0x401F2) OER3: Serial I/F Ch.3 Overrun Error Flag in the Serial I/F Ch.3 Status Register (D2/0x401F7) FER0: Serial I/F Ch.0 Framing Error Flag in the Serial I/F Ch.0 Status Register (D4/0x401E2) FER1: Serial I/F Ch.1 Framing Error Flag in the Serial I/F Ch.1 Status Register (D4/0x401E7) FER2: Serial I/F Ch.2 Framing Error Flag in the Serial I/F Ch.2 Status Register (D4/0x401F2) FER3: Serial I/F Ch.3 Framing Error Flag in the Serial I/F Ch.3 Status Register (D4/0x401F7) Note: If a receive error (parity or framing error) occurs, the receive-error interrupt and receive-buffer full interrupt causes occur simultaneously. However, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. It is therefore necessary for the receive-buffer full interrupt cause flag be cleared through the use of the receiveerror interrupt processing routine. IV-8-28 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) Control registers of the interrupt controller I Table IV.8.5.1 shows the interrupt controller's control registers provided for each interrupt source (channel). Table IV.8.5.1 Control Register of Interrupt Controller Channel Ch.0 Ch.1 Ch.2 Ch.3 Cause of interrupt Receive-error Receive-buffer full Transmit-buffer empty Receive-error interrupt Receive-buffer full Transmit-buffer empty Receive-error Receive-buffer full Transmit-buffer empty Receive-error Receive-buffer full Transmit-buffer empty Cause-of-interrupt flag Interrupt enable register Interrupt priority register FSERR0(D0/0x40286) FSRX0(D1/0x40286) FSTX0(D2/0x40286) FSERR1(D3/0x40286) FSRX1(D4/0x40286) FSTX1(D5/0x40286) FSERR2(D0/0x40289) FSRX2(D1/0x40289) FSTX2(D2/0x40289) FSERR3(D3/0x40289) FSRX3(D4/0x40289) FSTX3(D5/0x40289) ESERR0(D0/0x40276) ESRX0(D1/0x40276) ESTX0(D2/0x40276) ESERR1(D3/0x40276) ESRX1(D4/0x40276) ESTX1(D5/0x40276) ESERR2(D0/0x40279) ESRX2(D1/0x40279) ESTX2(D2/0x40279) ESERR3(D3/0x40279) ESRX3(D4/0x40279) ESTX3(D5/0x40279) PSIO0[2:0](D[6:4]/0x40269) PSIO1[2:0](D[2:0]/0x4026A) PSIO2[2:0](D[2:0]/0x4026E) PSIO3[2:0](D[6:4]/0x4026E) When a cause of interrupt described above occurs, the corresponding cause-of-interrupt flag is set to 1. If the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0. The cause-of-interrupt flag is set to 1 whenever interrupt conditions are met, regardless of the setting of the interrupt enable register (even if it is set to 0). The interrupt priority register sets the interrupt priority level of each interrupt source in a range between 0 and 7. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. In addition, only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the input interrupt level set by the interrupt priority register, will the input interrupt request actually be accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to Section IV.2, "Interrupt Controller (ITC)." Intelligent DMA IV The receive-buffer full interrupt and transmit-buffer empty interrupt causes can be used to invoke intelligent DMA (IDMA). This enables successive transmit/receive operations between memory and the transmit/receivebuffer to be performed by means of a DAM transfer. The following shows the IDMA channel numbers set for each cause of interrupt: IDMA Ch. Ch.0 receive-buffer full interrupt: 0x17 Ch.0 transmit-buffer empty interrupt: 0x18 Ch.1 receive-buffer full interrupt: 0x19 Ch.1 transmit-buffer empty interrupt: 0x1A Ch.2 receive-buffer full interrupt: 0x22 Ch.2 transmit-buffer empty interrupt: 0x23 Ch.3 receive-buffer full interrupt: 0x24 Ch.3 transmit-buffer empty interrupt: 0x25 The IDMA request and enable bits shown in Table IV.8.5.2 must be set to 1 for IDMA to be invoked. Transfer conditions, etc. on the IDMA side must also be set in advance. Table IV.8.5.2 Control Bits for IDMA Transfer Channel Ch.0 Ch.1 Ch.2 Ch.3 Cause of interrupt Receive-buffer full Transmit-buffer empty Receive-buffer full Transmit-buffer empty Receive-buffer full Transmit-buffer empty Receive-buffer full Transmit-buffer empty S1C33401 TECHNICAL MANUAL IDMA request bit IDMA enable bit RSRX0(D6/0x40292) RSTX0(D7/0x40292) RSRX1(D0/0x40293) RSTX1(D1/0x40293) RSRX2(D2/0x4029B) RSTX2(D3/0x4029B) RSRX3(D4/0x4029B) RSTX3(D5/0x4029B) DESRX0(D6/0x40296) DESTX0(D7/0x40296) DESRX1(D0/0x40297) DESTX1(D1/0x40297) DESRX2(D2/0x4029C) DESTX2(D3/0x4029C) DESRX3(D4/0x4029C) DESTX3(D5/0x4029C) EPSON IV-8-29 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) If an cause of interrupt occurs when the IDMA request and enable bits are set to 1, IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. The bits can also be set so as not to generate an interrupt, with only a DAM transfer performed. For details on DMA transfer and how to control interrupts upon completion of DMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." High-speed DMA The receive-buffer full interrupt and transmit-buffer empty interrupt causes for Ch.0 and Ch.1 can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit corresponding to each channel: Table IV.8.5.3 HSDMA Trigger Set-up Bits HSDMA SIF channel channel 0 1 2 3 0 1 2 3 Trigger set-up bits HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) For HSDMA to be invoked by a cause of receive-buffer full interrupt, the trigger set-up bits should be set to "1010." For HSDMA to be invoked by a cause of transmit-buffer empty interrupt, the trigger set-up bits should be set to "1011." Transfer conditions, etc. must also be set on the HSDMA side. The HSDMA channel is invoked through generation of the cause of interrupt. For details on HSDMA transfer, refer to Section III.4, "High-Speed DMA (HSDMA)." Trap vectors The trap-vector address of each default cause of interrupt is set as follows: Ch.0 receive-error interrupt: 0x200000E0 Ch.0 receive-buffer full interrupt: 0x200000E4 Ch.0 transmit-buffer empty interrupt: 0x200000E8 Ch.1 receive-error interrupt: 0x200000F0 Ch.1 receive-buffer full interrupt: 0x200000F4 Ch.1 transmit-buffer empty interrupt: 0x200000F8 Ch.2 receive-error interrupt: 0x20000130 Ch.2 receive-buffer full interrupt: 0x20000134 Ch.2 transmit-buffer empty interrupt: 0x20000138 Ch.3 receive-error interrupt: 0x20000140 Ch.3 receive-buffer full interrupt: 0x20000144 Ch.3 transmit-buffer empty interrupt: 0x20000148 The base address of the trap table can be changed using the TTBR register. IV-8-30 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.6 Details of Control Registers I Table IV.8.6.1 List of Serial Interface Registers Address 0x000401E0 0x000401E1 0x000401E2 0x000401E3 0x000401E4 0x000401E5 0x000401E6 0x000401E7 0x000401E8 0x000401E9 0x000401F0 0x000401F1 0x000401F2 0x000401F3 0x000401F4 0x000401F5 0x000401F6 0x000401F7 0x000401F8 0x000401F9 0x000401FF Register name Serial I/F Ch.0 Transmit Data Register (pFSIF0_TXD) Serial I/F Ch.0 Receive Data Register (pFSIF0_RXD) Serial I/F Ch.0 Status Register (pFSIF0_STATUS) Serial I/F Ch.0 Control Register (pFSIF0_CTL) Serial I/F Ch.0 IrDA Register (pFSIF0_IRDA) Serial I/F Ch.1 Transmit Data Register (pFSIF1_TXD) Serial I/F Ch.1 Receive Data Register (pFSIF1_RXD) Serial I/F Ch.1 Status Register (pFSIF1_STATUS) Serial I/F Ch.1 Control Register (pFSIF1_CTL) Serial I/F Ch.1 IrDA Register (pFSIF1_IRDA) Serial I/F Ch.2 Transmit Data Register (pFSIF2_TXD) Serial I/F Ch.2 Receive Data Register (pFSIF2_RXD) Serial I/F Ch.2 Status Register (pFSIF2_STATUS) Serial I/F Ch.2 Control Register (pFSIF2_CTL) Serial I/F Ch.2 IrDA Register (pFSIF2_IRDA) Serial I/F Ch.3 Transmit Data Register (pFSIF3_TXD) Serial I/F Ch.3 Receive Data Register (pFSIF3_RXD) Serial I/F Ch.3 Status Register (pFSIF3_STATUS) Serial I/F Ch.3 Control Register (pFSIF3_CTL) Serial I/F Ch.3 IrDA Register (pFSIF3_IRDA) Serial I/F STD/ADV Mode Select Register (pFSIF_ADV) Size 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Function Ch.0 transmit data Ch.0 receive data Ch.0 transfer/error status Sets Ch.0 transfer mode and controls transfer. Sets Ch.0 asynchronous/IrDA mode. Ch.1 transmit data Ch.1 receive data Ch.1 transfer/error status Sets Ch.1 transfer mode and controls transfer. Sets Ch.1 asynchronous/IrDA mode. Ch.2 transmit data Ch.2 receive data Ch.2 transfer/error status Sets Ch.2 transfer mode and controls transfer. Sets Ch.2 asynchronous/IrDA mode. Ch.3 transmit data Ch.3 receive data Ch.3 transfer/error status Sets Ch.3 transfer mode and controls transfer. Sets Ch.3 asynchronous/IrDA mode. Selects standard or advanced mode. The following describes each serial interface control register. The serial interface control registers are mapped in the 8-bit device area from 0x401E0 to 0x401FF, and can be accessed in units of bytes. Note: When setting the serial interface control registers, be sure to write a 0, and not a 1, for all "reserved bits." IV SIO S1C33401 TECHNICAL MANUAL EPSON IV-8-31 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401E0-0x401F5: Serial I/F Ch.x Transmit Data Registers (pFSIFx_TXD) Register name Address Bit 00401E0 | 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.x transmit data register (pFSIFx_TXD) Name TXDx7 TXDx6 TXDx5 TXDx4 TXDx3 TXDx2 TXDx1 TXDx0 Function Serial I/F Ch.x transmit data TXDx7(x6) = MSB TXDx0 = LSB Setting 0x0 to 0xFF(0x7F) Init. R/W X X X X X X X X Remarks R/W 7-bit asynchronous mode does not use TXDx7. Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x401E0 0x401E5 0x401F0 0x401F5 D[7:0] IV-8-32 Serial I/F Ch.0 Transmit Data Register (pFSIF0_TXD) Serial I/F Ch.1 Transmit Data Register (pFSIF1_TXD) Serial I/F Ch.2 Transmit Data Register (pFSIF2_TXD) Serial I/F Ch.3 Transmit Data Register (pFSIF3_TXD) TXDx[7:0]: Serial I/F Ch.x Transmit Data Bits Sets transmit data. (Default: indeterminate) When data is written to this register (transmit data buffer) after 1 is written to TXENx, a transmit operation is begun. The data written to TXDx[7:0] enters the transmit data buffer and waits for transmission. The transmit data buffer is a 2-byte FIFO and up to two data can be written to it successively if empty. Older data will be transmitted first and cleared after transmission. When all the data in the transmit data buffer are transferred, a cause of transmit-data empty interrupt occurs. In the 7-bit asynchronous mode, TXDx7 (MSB) is ignored. The serial-converted data is output from the SOUTx pin beginning with the LSB, in which the bits set to 1 are output as high-level signals and those set to 0 output as low-level signals. This register can be read as well as written. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401E1-0x401F6: Serial I/F Ch.x Receive Data Registers (pFSIFx_RXD) Register name Address Bit 00401E1 | 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.x receive data register (pFSIFx_RXD) Name RXDx7 RXDx6 RXDx5 RXDx4 RXDx3 RXDx2 RXDx1 RXDx0 Function Serial I/F Ch.x receive data RXDx7(x6) = MSB RXDx0 = LSB Setting 0x0 to 0xFF(0x7F) Init. R/W X X X X X X X X R I Remarks 7-bit asynchronous mode does not use RXDx7 (fixed at 0). Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x401E1 0x401E6 0x401F1 0x401F6 D[7:0] Serial I/F Ch.0 Receive Data Register (pFSIF0_RXD) Serial I/F Ch.1 Receive Data Register (pFSIF1_RXD) Serial I/F Ch.2 Receive Data Register (pFSIF2_RXD) Serial I/F Ch.3 Receive Data Register (pFSIF3_RXD) RXDx[7:0]: Serial I/F Ch.x Receive Data Bits The data in the receive data buffer can be read from this register beginning with the oldest data first. The received data enters the receive data buffer. The receive data buffer is a 4-byte FIFO and can receive data until it becomes full unless received data is not read out. When the buffer is full and also the shift register contains received data, an overrun error will occur if the received data is not read until the next data receiving begins. The receive buffer status flag RDBFx is provided to indicate that it is necessary to read the receive data buffer. This flag is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. When the receive data buffer has received the number of data specified with FIFOINTx[1:0] (one data in standard mode), a cause of receive buffer full interrupt occurs. In the 7-bit asynchronous mode, 0 is stored in RXDx7. The serial data input from the SINx pin is converted into parallel data beginning with the LSB, with the high-level signals changed to 1s and the low-level signals changed to 0s. The resulting data is stored in this buffer. This register is a read-only register, so no data can be written to it. (Default: indeterminate) IV SIO S1C33401 TECHNICAL MANUAL EPSON IV-8-33 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401E2-0x401F7: Serial I/F Ch.x Status Registers (pFSIFx_STATUS) Name Register name Address Bit Serial I/F Ch.x 00401E2 | status register (pFSIFx_STATUS) 00401F7 (B) D7 D6 RXDxNUM1 Number of Ch.x receive data RXDxNUM0 in FIFO D5 D4 D3 D2 D1 D0 TENDx FERx PERx OERx TDBEx RDBFx Function Ch.x transmit-completion flag Ch.x framing error flag Ch.x parity error flag Ch.x overrun error flag Ch.x transmit data buffer empty Ch.x receive data buffer full Setting Init. R/W RXDxNUM[1:0] Number of data 1 1 4 1 0 3 0 1 2 0 0 1 or 0 1 Transmitting 0 End 1 Error 0 Normal 0 Normal 1 Error 1 Error 0 Normal 1 Empty 0 Not empty 1 Full 0 Not full 0 0 0 0 0 0 1 0 Remarks R R R/W Reset by writing 0. R/W R/W R R Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x401E2 0x401E7 0x401F2 0x401F7 D[7:6] Serial I/F Ch.0 Status Register (pFSIF0_STATUS) Serial I/F Ch.1 Status Register (pFSIF1_STATUS) Serial I/F Ch.2 Status Register (pFSIF2_STATUS) Serial I/F Ch.3 Status Register (pFSIF3_STATUS) RXDxNUM[1:0]: Number of Ch.x Receive Data in FIFO Indicates the number of data in the receive data buffer (FIFO) that have not been read. Table IV.8.6.2 Number of Receive Data RXDxNUM1 RXDxNUM0 1 1 0 0 1 0 1 0 Number of data 4 3 2 1 or 0 (Default: 0b00) When RXDxNUM[1:0] is 0, it indicates that the receive data buffer contains 0 or 1 received data. When RXDxNUM[1:0] is 1 to 3, it indicates that the receive data buffer contains 2 to 4 received data. D5 TENDx: Serial I/F Ch.x Transmit-Completion Flag Indicates the transmission status. 1 (R): During transmitting 0 (R): End of transmission (default) TENDx goes 1 when data is being transmitted and goes 0 when the transmission has completed. When data is transmitted successively in clock-synchronized master mode or asynchronous mode, TENDx maintains 1 until all data is transmitted (see Figure IV.8.2.3.1 and Figure IV.8.3.3.1). In clocksynchronized slave mode, TENDx goes 0 every time 1-byte data is transmitted (see Figure IV.8.2.3.2). D4 FERx: Serial I/F Ch.x Framing Error Flag Indicates whether a framing error occurred. 1 (R): An error occurred 0 (R): No error occurred (default ) 1 (W): Has no effect 0 (W): Reset to 0 FERx is an error flag indicating whether a framing error occurred. When an error has occurred, it is set to 1. A framing error occurs when data with a stop bit = 0 is received in the asynchronous mode. FERx is reset by writing 0 or when RXENx and TXENx both are set to 0. IV-8-34 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) D3 PERx: Serial I/F Ch.x Parity Error Flag Indicates whether a parity error occurred. 1 (R): An error occurred 0 (R): No error occurred (default) 1 (W): Has no effect 0 (W): Reset to 0 I PERx is an error flag indicating whether a parity error occurred. When an error has occurred, it is set to 1. Parity checks are valid only in the asynchronous mode with EPRx set to 1 (parity added). This check is performed when the received data is transferred from the shift register to the receive data buffer. PERx is reset by writing 0 or when RXENx and TXENx both are set to 0. D2 OERx: Serial I/F Ch.x Overrun Error Flag Indicates whether an overrun error occurred. 1 (R): An error occurred 0 (R): No error occurred (default) 1 (W): Has no effect 0 (W): Reset to 0 OERx is an error flag indicating whether an overrun error occurred. When an error has occurred, it is set to 1. An overrun error will occur if a new data is transferred to this serial interface when the receive data buffer is full and also the shift register contains received data. When this error occurs, the shift register is overwritten with the new received data and the receive data in the buffer is maintained as is. OERx is reset by writing 0 or when RXENx and TXENx both are set to 0. D1 TDBEx: Serial I/F Ch.x Transmit Data Buffer Empty Flag Indicates the status of the transmit data buffer. 1 (R): Not full (default) 0 (R): Buffer full TDBEx is set to 1 when the transmit data buffer has a free space for transmit data to be written and reset to 0 when the transmit data buffer becomes full by writing transmit data. Up to two transmit data can be written to the transmit data buffer. D0 IV RDBFx: Serial I/F Ch.x Receive Data Buffer Full Flag Indicates the status of the receive data buffer. 1 (R): Not empty 0 (R): Buffer empty (default) RDBFx is set to 1 when the receive data buffer contains one or more received data, and is reset to 0 when the receive data buffer becomes empty by reading all the received data. S1C33401 TECHNICAL MANUAL EPSON IV-8-35 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401E3-0x401F8: Serial I/F Ch.x Control Registers (pFSIFx_CTL) Register name Address Bit Serial I/F Ch.x 00401E3 | control register 00401F8 (pFSIFx_CTL) (B) D7 D6 D5 D4 D3 D2 D1 D0 Name TXENx RXENx EPRx PMDx STPBx SSCKx SMDx1 SMDx0 Function Ch.x transmit enable Ch.x receive enable Ch.x parity enable Ch.x parity mode select Ch.x stop bit select Ch.x input clock select Ch.x transfer mode select Setting Init. R/W 1 Enabled 0 Disabled 0 Disabled 1 Enabled 1 With parity 0 No parity 1 Odd 0 Even 1 2 bits 0 1 bit 1 #SCLKx 0 Internal clock SMDx[1:0] Transfer mode 11 8-bit asynchronous 10 7-bit asynchronous 01 Clock sync. Slave 00 Clock sync. Master 0 0 X X X X X X Remarks R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x401E3 0x401E8 0x401F3 0x401F8 D7 Serial I/F Ch.0 Control Register (pFSIF0_CTL) Serial I/F Ch.1 Control Register (pFSIF1_CTL) Serial I/F Ch.2 Control Register (pFSIF2_CTL) Serial I/F Ch.3 Control Register (pFSIF3_CTL) TXENx: Serial I/F Ch.x Transmit Enable Bit Enables each channel for transmit operations. 1 (R/W): Transmit enabled 0 (R/W): Transmit disabled (default) When TXENx for a channel is set to 1, the channel is enabled for transmit operations. When TXENx is set to 0, the channel is disabled for transmit operations. Always make sure TXENx = 0 before setting the transfer mode and other conditions. Writing 0 to TXENx clears the transmit data buffer (FIFO) as well as disabling transmit operations. D6 RXENx: Serial I/F Ch.x Receive Enable Bit Enables each channel for receive operations. 1 (R/W): Receive enabled 0 (R/W): Receive disabled (default) When RXENx for a channel is set to 1, the channel is enabled for receive operations. When RXENx is set to 0, the channel is disabled for receive operations. Always make sure RXENx = 0 before setting the transfer mode and other conditions. Writing 0 to RXENx clears the receive data buffer (FIFO) as well as disabling receive operations. D5 EPRx: Serial I/F Ch.x Parity Enable Bit Selects a parity function. (Default: indeterminate) 1 (R/W): Parity added 0 (R/W): No parity added EPRx is used to select whether receive data is to be checked for parity, and whether a parity bit is to be added to transmit data. When EPRx is set to 1, the receive data is checked for parity. A parity bit is automatically added to the transmit data. When EPRx is set to 0, parity is not checked and no parity bit is added. The parity function is only valid in the asynchronous mode. Settings of EPRx have no effect in the clock-synchronized mode. IV-8-36 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) D4 PMDx: Serial I/F Ch.x Parity Mode Select Bit Selects an odd or even parity. (Default: indeterminate) 1 (R/W): Odd parity 0 (R/W): Even parity I Odd parity is selected by writing 1 to PMDx, and even parity is selected by writing 0. Parity check and the addition of a parity bit are only effective in asynchronous transfers in which EPRx is set to 1. If EPRx = 0, settings of PMDx do not have any effect. D3 STPBx: Serial I/F Ch.x Stop-Bit Length Select Bit Selects a stop-bit length during the performance of an asynchronous transfer. (Default: indeterminate) 1 (R/W): 2 bits 0 (R/W): 1 bit STPBx is only valid in an asynchronous transfer. Two stop bits are selected by writing 1 to STPBx, and one stop bit is selected by writing 0. The start bit is fixed at 1 bit. Settings of STPBx are ignored during the performance of a clock-synchronized transfer. D2 SSCKx: Serial I/F Ch.x Input Clock Select Bit Selects the clock source for an asynchronous transfer. (Default: indeterminate) 1 (R/W): #SCLKx (external clock) 0 (R/W): Internal clock During operation in the asynchronous mode, this bit is used to select the clock source between an internal clock (output by an 8-bit timer) and an external clock (input from the #SCLKx pin). An external clock is selected by writing 1 to this bit, and an internal clock is selected by writing 0. D[1:0] SMDx[1:0]: Serial I/F Ch.x Transfer Mode Select Bits Sets the transfer mode of the serial interface as shown in Table IV.8.6.3 below. Table IV.8.6.3 Setting of Transfer Mode SMDx1 SMDx0 Transfer mode 1 1 0 0 1 0 1 0 8-bit asynchronous mode 7-bit asynchronous mode Clock-synchronized slave mode Clock-synchronized master mode (Default: indeterminate) IV SMDx[1:0] can be read as well as written. When using the IrDA interface, always be sure to set an asynchronous mode for the transfer mode. SIO S1C33401 TECHNICAL MANUAL EPSON IV-8-37 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401E4-0x401F9: Serial I/F Ch.x IrDA Registers (pFSIFx_IRDA) Name Register name Address Bit 00401E4 | 00401F9 (B) D7 D6 D5 SRDYCTLx Ch.x #SRDY control FIFOINTx1 Ch.x receive buffer full interrupt FIFOINTx0 timing D4 D3 D2 D1 D0 DIVMDx IRTLx IRRLx IRMDx1 IRMDx0 Serial I/F Ch.x IrDA register (pFSIFx_IRDA) Function Setting 1 High mask FIFOINTx[1:0] 11 10 01 00 Ch.x async. clock division ratio 1 1/8 Ch.x IrDA I/F output logic inversion 1 Inverted Ch.x IrDA I/F input logic inversion 1 Inverted Ch.x interface mode select IRMDx[1:0] 11 10 01 00 Init. R/W 0 Normal Receive level 4 3 2 1 0 1/16 0 Direct 0 Direct I/F mode reserved IrDA 1.0 reserved General I/F Remarks 0 0 0 R/W Writing is disabled R/W when SIOADV (D0/0x401FF) = "0". X X X X X R/W R/W Valid only in R/W asynchronous mode. R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 3. 0x401E4 0x401E9 0x401F4 0x401F9 D7 Serial I/F Ch.0 IrDA Register (pFSIF0_IRDA) Serial I/F Ch.1 IrDA Register (pFSIF1_IRDA) Serial I/F Ch.2 IrDA Register (pFSIF2_IRDA) Serial I/F Ch.3 IrDA Register (pFSIF3_IRDA) SRDYCTLx: Serial I/F Ch.x #SRDY Control Bit Selects a control method for the #SRDYx signal. 1 (R/W): High mask mode 0 (R/W): Normal output (default) When SRDYCTLx is set to 0, the #SRDYx signal is controlled normally and indicates ready to receive even if the receive data buffer is full. When SRDYCTLx is set to 1, high-mask mode is selected. The following shows the #SRDYx controls in the clock-synchronized slave mode and master mode: Clock-synchronizes slave mode When the receive data buffer is full, the #SRDYx signal is forcibly fixed at high in order to suspend data transfer from the master device until the data in the buffer is read. Clock-synchronized master mode When the receive data buffer is full, the #SRDYx signal (low) from the slave device is ignored and the serial interface stops outputting the #SCLKx signal until the buffer data is read. The high mask mode can avoid overrun errors. When the receive data buffer is not full, normal receive operations are performed even if this function is enabled. In the asynchronous mode, this bit is ignored as it does not use the #SRDYx signal. Note: This bit can be rewritten only when SIOADV (D0/0x401FF) is set to 1 (advanced mode). D[6:5] FIFOINTx[1:0]: Serial I/F Ch.x Receive Buffer Full Interrupt Timing Select Bits Sets the number of data in the receive data buffer to generate a receive-buffer full interrupt. Table IV.8.6.4 Number of Receive Data Buffer FIFOINTx1 FIFOINTx0 1 1 0 0 1 0 1 0 Receive level 4 3 2 1 (Default: 0b00) Writing 0-3 to FIFOINTx[1:0] sets the number of data to 1-4. When the number of data in the receive data buffer reaches the number specified here, the receivebuffer full interrupt cause flag FSRXx are set to 1. Note: These bits can be rewritten only when SIOADV (D0/0x401FF) is set to 1 (advanced mode). IV-8-38 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) D4 DIVMDx: Serial I/F Ch.x Clock Division Ratio Select Bit Selects the division ratio of the sampling clock. (Default: indeterminate) 1 (R/W): 1/8 0 (R/W): 1/16 I Select the division ratio necessary to generate the sampling clock for asynchronous transfers. When DIVMDx is set to 1, the sampling clock is generated from the input clock of the serial interface (output by an 8-bit timer or input from #SCLKx) by dividing it by 8. When DIVMDx is set to 0, the input clock is divided by 16. D3 IRTLx: Serial I/F Ch.x IrDA I/F Output Logic Inversion Bit Inverts the logic of the IrDA output signal. (Default: indeterminate) 1 (R/W): Inverted 0 (R/W): Not inverted When using the IrDA interface, set the logic of the SOUTx output signal to suit the infrared-ray communication circuit that is connected external to the chip. If IRTLx is set to 1, a high pulse is output when the output data = 0 (held low-level when the output data = 1). If IRTLx is set to 0, a low pulse is output when the output data = 0 (held high-level when the output data = 1). D2 IRRLx: Serial I/F Ch.x IrDA I/F Input Logic Inversion Bit Inverts the logic of the IrDA input signal. (Default: indeterminate) 1 (R/W): Inverted 0 (R/W): Not inverted When using the IrDA interface, set the logic of the signal that is input from an external infrared-ray communication circuit to the chip to suit the serial interface. If IRRLx is set to 1, a high pulse is input as a logic 0. If IRRLx is set to 0, a low pulse is input as a logic 0. D[1:0] IRMDx[1:0]: Serial I/F Ch.x Interface Mode Select Bits Selects the IrDA interface function. IV Table IV.8.6.5 IrDA Interface Setting IRMDx1 IRMDx0 Interface mode 1 1 0 0 1 0 1 0 Do not set. (reserved) IrDA 1.0 interface Do not set. (reserved) Normal interface (Default: indeterminate) When using the IrDA interface function, write 0b10 to IRMDx[1:0] while setting to an asynchronous mode for the transfer mode. If the IrDA interface function is not to be used, write 0b00 to IRMDx[1:0]. Note: This selection must always be performed before the transfer mode and other conditions are set. S1C33401 TECHNICAL MANUAL EPSON IV-8-39 SIO IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) 0x401FF: Serial I/F STD/ADV Mode Select Register (pFSIF_ADV) Register name Address Bit Name 00401FF D7-1 - Serial I/F (B) STD/ADV mode D0 SIOADV select register (pFSIF_ADV) Function Setting reserved Init. R/W - Standard mode/advanced mode select 1 Advanced mode D[7:1] Reserved D0 SIOADV: Standard/Advanced Mode Select Bit Selects standard or advanced mode. 1 (R/W): Advanced mode 0 (R/W): Standard mode (default) 0 Standard mode - - 0 R/W Remarks Writing 1 not allowed. The serial interface in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV serial interface has two operating modes, standard (STD) mode of which functions are compatible with the existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table IV.8.6.6 shows differences between standard mode and advanced mode. Table IV.8.6.6 Differences between Standard Mode and Advanced Mode Function #SRDY mask control Number of received data in the buffer to generate a receive-buffer full interrupt Standard mode Advanced mode Disabled One Enabled One to four can be specified. To configure the serial interface in advanced mode, set SIOADV to 1. The control bits (SRDYCTLx and FIFOINTx[1:0]) for the extended functions are enabled to write after this setting. Note: Standard or advanced mode currently set is applied to all the serial interface channels. It cannot be selected for each channel individually. IV-8-40 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) IV.8.7 Precautions I * Before setting various serial-interface parameters, make sure the transmit and receive operations are disabled (TXENx = RXENx = 0). TXEN0: Serial I/F Ch.0 Transmit Enable Bit in the Serial I/F Ch.0 Control Register (D7/0x401E3) TXEN1: Serial I/F Ch.1 Transmit Enable Bit in the Serial I/F Ch.1 Control Register (D7/0x401E8) TXEN2: Serial I/F Ch.2 Transmit Enable Bit in the Serial I/F Ch.2 Control Register (D7/0x401F3) TXEN3: Serial I/F Ch.3 Transmit Enable Bit in the Serial I/F Ch.3 Control Register (D7/0x401F8) RXEN0: Serial I/F Ch.0 Receive Enable Bit in the Serial I/F Ch.0 Control Register (D6/0x401E3) RXEN1: Serial I/F Ch.1 Receive Enable Bit in the Serial I/F Ch.1 Control Register (D6/0x401E8) RXEN2: Serial I/F Ch.2 Receive Enable Bit in the Serial I/F Ch.2 Control Register (D6/0x401F3) RXEN3: Serial I/F Ch.3 Receive Enable Bit in the Serial I/F Ch.3 Control Register (D6/0x401F8) * When the serial interface is transmitting or receiving data, do not set TXENx or RXENx to 0, and do not execute the slp instruction. * In clock-synchronized transfers, the mode of communication is half-duplex, in which the clock line is shared between the transmit and receive units. Therefore, RXENx and TXENx cannot be enabled simultaneously. * After an initial reset, the cause-of-interrupt flags become indeterminate. To prevent generation of an unwanted interrupt or IDMA request, reset these flags in the program. * If a receive error occurs, the receive-error interrupt and receive-buffer full interrupt causes occur simultaneously. However, since the receive-error interrupt has priority over the receive-buffer full interrupt, the receive-error interrupt is processed first. Therefore, it is necessary to reset the receive-buffer full interrupt cause flag through the use of the receive-error interrupt processing routine. * To prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt, always be sure to reset the cause-of-interrupt flag before setting the PSR again or executing the reti instruction. * Follow the procedure described below to initialize the serial interface. Set IRMDx[1:0] 00(normal I/F) or 10(IrDA I/F) Set SMDx[1:0] Transfer mode setting Other settings Data format and clock selection Internal division ratio, IrDA I/O logic and other settings Enable transmitting/receiving IV Enable transmitting, receiving or both Figure IV.8.7.1 Serial Interface Initialize Procedure SIO * When transmitting data in the clock-synchronized master mode, transmit data is written to the transmit data register after the initial setting is performed following the flow above. However, the clock generated by the 8-bit timer must be supplied to the serial interface (at least one underflow has had to have occurred in the 8-bit timer) before this writing. Otherwise, 0xFF will be transmitted prior to the written data. * The maximum transfer rate of the serial interface is limited to 8 Mbps in clock-synchronized mode or 1 Mbps in asynchronous mode. Do not set a transfer rate (baud rate) that exceeds the limit. * If the receive circuit is stopped during reception, set both transmission and reception to the disabled status. * When performing data transfer in the clock-synchronized mode, the division ratio of the prescaler and the reload data for the 8-bit timer should be set so that the baud-rate is 1/4 of the system clock frequency or lower. * The serial interface operates only when the prescaler is operating. S1C33401 TECHNICAL MANUAL EPSON IV-8-41 IV C33 ADV BASIC PERIPHERAL BLOCK: SERIAL INTERFACE (SIO) * When the transmit-enable bit TXENx is set to 0 to disable transmit operations, the transmit data buffer (FIFO) is cleared (initialized). Similarly, when the receive-enable bit RXENx is set to 0 to disable receive operations, the receive data buffer (FIFO) is cleared (initialized). Therefore, make sure that the buffer does not contain any data waiting for transmission or reading before writing 0 to these bits. * During IrDA receive operations, the RZI circuit recognizes low pulses by means of the signal edge (rising edge when IRRLx = 0; falling edge when IRRLx = 1). Note that noise may cause a malfunction. IRRL0: Serial I/F Ch.0 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.0 IrDA Register (D2/0x401E4) IRRL1: Serial I/F Ch.1 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.1 IrDA Register (D2/0x401E9) IRRL2: Serial I/F Ch.2 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.2 IrDA Register (D2/0x401F4) IRRL3: Serial I/F Ch.3 IrDA I/F Input Logic Inversion Bit in the Serial I/F Ch.3 IrDA Register (D2/0x401F9) IV-8-42 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9 Card Interface (CARD) I IV.9.1 Overview of the Card Interface The Card Interface (CARD) generates control signals for the card interfaces listed below. * #SMRD and #SMWR signals for SmartMedia (NAND flash) * #CFCE1 and #CFCE2 signals for CompactFlash * #IORD, #IOWR, #OE and #WE signals for PC Card Each device may be located in any of the CE4, CE7, CE9, or CE11 areas. The data and address signals of each device can be connected directly to the external bus of the BBCU. Use general-purpose input/output ports to control the signals specific to each card. The PC card interface can accommodate up to two channels by locating each channel in different areas. IV CARD S1C33401 TECHNICAL MANUAL EPSON IV-9-1 IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.2 Card Interface Pins The Card Interface has six ports (CARD0 to CARD5) to output each interface signal listed above. Note, however, that these pins are shared with general-purpose I/O ports or other peripheral circuit input/output pins. In the initial state, these pins are set for functions other than the card interface. Before the pins can be used as CARD0 to CARD5 ports, the pin functions must be switched over by setting the corresponding Port Function Select Register. For details on how to switch over the pin functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." Selecting the card interface pin functions The CARD0 to CARD5 ports each are assigned two card interface signals, either of which can be selected for output from the respective ports. Table IV.9.2.1 lists the signals assigned to each port. Table IV.9.2.1 Relationship between Ports and Card Interface Signals Pin name Function 0 (default) Function 1 Function select bit CARD0 CARD1 CARD2 CARD3 CARD4 CARD5 #SMRD #SMWR #IORD #IOWR #OE #WE #CFCE1 #CFCE2 #SMRD #SMWR #CFCE1 #CFCE2 CARDIO0 (D0/0x40302) CARDIO1 (D1/0x40302) CARDIO2 (D2/0x40302) CARDIO3 (D3/0x40302) CARDIO4 (D4/0x40302) CARDIO5 (D5/0x40302) CARDIOx: CARDx Port Function Select Bit in the Card I/F Output Port Configuration Register (Dx/0x40302) CARDIOx (Dx/0x40302) is initially set to 0, with function 0 selected. To use function 1, set CARDIOx (Dx/ 0x40302) to 1. IV-9-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.3 Card Area I IV.9.3.1 Selecting the Area The following CE areas can be used as memory areas for cards. CE4 area: Area 4 (0x100000 to 0x1FFFFF, 1MB) or Area 14 (0x3000000 to 0x3FFFFFF, 16MB) CE7 area: Area 7 (0x400000 to 0x5FFFFF, 2MB) or Area 19 (0x10000000 to 0x1FFFFFFF, 256MB) CE9 area: Area 9 (0x800000 to 0xBFFFFF, 4MB) or Area 22 (0x80000000 to 0xFFFFFFFF, 2GB) CE11 area: Area 11 (0x1000000 to 0x17FFFFF, 8MB) or Area 12 (0x1800000 to 0x1FFFFFF, 8MB) One of the four areas above can be selected for each card interface. The following describes the control bits used to select any area and the bit settings. SmartMedia (NAND flash) CARDSMT[1:0]: SmartMedia Area Configuration Bits in the Card I/F Area Configuration Register (D[1:0]/0x40300) CompactFlash CARDCF[1:0]: CF Area Configuration Bits in the Card I/F Area Configuration Register (D[3:2]/0x40300) PC Card 1 CARDPC1[1:0]: PC Card 1 Area Configuration Bits in the Card I/F Area Configuration Register (D[5:4]/0x40300) PC Card 2 CARDPC2[1:0]: PC Card 2 Area Configuration Bits in the Card I/F Area Configuration Register (D[7:6]/0x40300) Table IV.9.3.1.1 Area Selection Area Control bit settings CE11 (area 11, 12) CE9 (area 9, 22) CE7 (area 7, 19) CE4 (area 4, 14) (Default: 0b00 = CE4) 11 10 01 00 IV IV.9.3.2 Setting Area Access Conditions Depending on the core system clock (CCLK) frequency, access timing conditions must be set for the area assigned to a card. Use the BBCU registers to set these conditions as suitable for the A.C. characteristics of the connected card. For details of access timing conditions and the BBCU registers, see Section III.2, "Basic Bus Control Unit (BBCU)." CARD S1C33401 TECHNICAL MANUAL EPSON IV-9-3 IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.4 Card Interface Control Signals This section describes the logic used to generate each card interface signal, and shows an example of connecting a card. IV.9.4.1 SmartMedia Interface Figure IV.9.4.1.1 shows the logic used to generate SmartMedia interface signals. Figure IV.9.4.1.2 shows an example of connecting the S1C33 and a SmartMedia (NAND flash) card. #RD #SMRD Specified #CEx #SMWR #WRLL Figure IV.9.4.1.1 SmartMedia Interface Signal Generation Circuit SmartMedia card (NAND flash) S1C33 D[15:0] or D[7:0] I/O[15:0] (16-bit flash) or I/O[7:0] (8-bit flash) #CEx #SMRD #SMWR #CE #RE #WE CLE ALE RY/#BY #WP (Software control) P Figure IV.9.4.1.2 Example of Connecting a SmartMedia Card For SmartMedia and CompactFlash, the C33 ADV has a middleware available for use in developing S1C33 Family applications. For details of the system and applications that can be implemented, refer to the manual included with the middleware. IV-9-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.4.2 CompactFlash Interface I Figure IV.9.4.2.1 shows the logic used to generate CompactFlash interface signals. Figure IV.9.4.2.2 shows an example of connecting the S1C33 and a CompactFlash card. A4 #CE1 Specified #CEx #CE2 Figure IV.9.4.2.1 CompactFlash Interface Signal Generation Circuit CompactFlash card S1C33 #CE1 #CE2 A[3:1] D[15:0] #RD #WRL #WAIT /CE1 /CE2 A[2:0] D[15:0] /IORD /IOWR IORDY INTRQ /CD1 /CD2 (Software control) P Figure IV.9.4.2.2 Example of Connecting a CompactFlash Card For SmartMedia and CompactFlash, the C33 ADV has a middleware available for use in developing S1C33 Family applications. For details of the system and applications that can be implemented, refer to the manual included with the middleware. IV IV.9.4.3 PC Card Interface Figure IV.9.4.3.1 shows the logic used to generate PC Card interface signals. Figure IV.9.4.3.2 shows an example of connecting the S1C33 and a PC Card. #RD #IORD Specified #CEx CARD #WR #IOWR A19 #OE #WE Figure IV.9.4.3.1 PC Card Interface Signal Generation Circuit S1C33401 TECHNICAL MANUAL EPSON IV-9-5 IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) Example connection 1 Area used: Device size: Attribute memory space: I/O space: Area 7 8 bits (only accessible in units of bytes) 0x480000 to 0x4FFFFF, 512KB (common memory not used) 0x400000 to 0x47FFFF, 512KB PC card S1C33 VSS VDD #CEx A[20:0] D[15:0] #OE #WE #IORD #IOWR #WAIT (Software control) P REG# CE2# CE1# A[20:0] D[15:0] OE# WE# IORD# IOWR# WAIT# IREQ# Example connection 2 Area used: Device size: Attribute memory space: I/O space: Area 7 16 bits (only accessible in units of half-words) 0x480000 to 0x4FFFFF, 512KB (common memory not used) 0x400000 to 0x47FFFF, 512KB PC card S1C33 (Software control) P #CEx #CEx A[20:0] D[15:0] #OE #WE #IORD #IOWR #WAIT (Software control) P REG# CE2# CE1# A[20:0] D[15:0] OE# WE# IORD# IOWR# WAIT# IREQ# Since this example connection only supports access in units of half-words, PC cards with only 16-bit registers can be used. PC cards with 8-bit registers cannot be used. Figure IV.9.4.3.2 Example of Connecting a PC Card Precautions on using the PC Card interface * This interface supports 16-bit PC cards, such as ATA (CF), LAN (Ethernet, wireless), and modem that are connected as an I/O card. SRAM cards, etc. are not supported. * Live or hot-line card insertion and removal are not supported. Power must be turned off before inserting or removing a card. Automatic recognition of cards is also not supported. * DMA, ZV, and CardBus are also not supported. * To accommodate differences in power supply voltage between the PC card (5 V or 3.3 V) and S1C33 chip, use a buffer IC (e.g., S1C37120). IV-9-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.5 Card Interface Operating Clock I The card interface module is clocked by the peripheral circuit clock (PCLK) supplied by the CMU. When initially reset, this clock is selected for supply to the card interface. However, when the card interface is idle or not in use, clock supply from the CMU may be turned off to reduce current consumed on the chip. Use CARDCLK (D2/ 0x40181) of the CMU for this control. CARDCLK: CARD I/F Clock Control Bit in the Peripheral Clock Control Register 2 (D2/0x40181) Setting CARDCLK (D2/0x40181) to 0 stops clock supply from the CMU to the card interface. For details of the generation and control of PCLK, see Section II.3, "Clock Management Unit (CMU)." Note: The Peripheral Clock Control Register 2 (0x40181) is write-protected. Write protection of this and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. IV CARD S1C33401 TECHNICAL MANUAL EPSON IV-9-7 IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.6 Details of Control Registers Table IV.9.6.1 Card Interface Control Register List Address 0x00040300 0x00040302 Register name Card I/F Area Configuration Register (pCARDSETUP) Card I/F Output Port Configuration Register (pCARDFUNCSEL05) Size 8 Allocates card space. 8 Function Selects the function of signal output ports for card control. The following describes each card interface control register. The card interface control registers are mapped to the 8-bit device area at addresses 0x40300 to 0x40302, and can be accessed in units of bytes. 0x40300: Card I/F Area Configuration Register (pCARDSETUP) Register name Address Bit Name Card I/F area configuration register (pCARDSETUP) D7 D6 D5 D4 D3 D2 D1 D0 CARDPC21 CARDPC20 CARDPC11 CARDPC10 CARDCF1 CARDCF0 CARDSMT1 CARDSMT0 0040300 (B) Function PC card 2 area configuration PC card 1 area configuration CF area configuration SmartMedia area configuration Init. R/W Setting bit[1:0] CE area 11 10 01 00 CE11 (Area 11, 12) CE9 (Area 9, 22) CE7 (Area 7, 19) CE4 (Area 4, 14) 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W This register sets the area in which to allocate each card space. Table IV.9.6.2 lists the settings of each card interface control bit used to select this area. Table IV.9.6.2 Area Selection Area Control bit settings CE11 (area 11, 12) CE9 (area 9, 22) CE7 (area 7, 19) CE4 (area 4, 14) (Default: 0b00 = CE4) 11 10 01 00 D[7:6] CARDPC2[1:0]: PC Card 2 Area Configuration Bits These bits select the area used for PC Card 2. D[5:4] CARDPC1[1:0]: PC Card 1 Area Configuration Bits These bits select the area used for PC Card 1. D[3:2] CARDCF[1:0]: CF Area Configuration Bits These bits select the area used for the CompactFlash card. D[1:0] CARDSMT[1:0]: SmartMedia Area Configuration Bits These bits select the area used for the SmartMedia (NAND flash) card. IV-9-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) 0x40302: Card I/F Output Port Configuration Register (pCARDFUNCSEL05) Register name Address Bit 0040302 Card I/F (B) output port configuration register (pCARDFUNCSEL05) D7-6 D5 D4 D3 D2 D1 D0 Name - CARDIO5 CARDIO4 CARDIO3 CARDIO2 CARDIO1 CARDIO0 Function reserved CARD5 port function select CARD4 port function select CARD3 port function select CARD2 port function select CARD1 port function select CARD0 port function select Setting Init. R/W - 1 1 1 1 1 1 #CFCE2 #CFCE1 #SMWR #SMRD #CFCE2 #CFCE1 0 0 0 0 0 0 #WE #OE #IOWR #IORD #SMWR #SMRD - 0 0 0 0 0 0 I Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W Table IV.9.6.3 Relationship between Ports and Card Interface Signals Pin name Function 0 (default) Function 1 CARD0 CARD1 CARD2 CARD3 CARD4 CARD5 #SMRD #SMWR #IORD #IOWR #OE #WE #CFCE1 #CFCE2 #SMRD #SMWR #CFCE1 #CFCE2 D[7:6] Reserved D5 CARDIO5: CARD5 Port Function Select Bit This bit selects the signal to output from the CARD5 pin. 1 (R/W): #CFCE2 0 (R/W): #WE (default) D4 CARDIO4: CARD4 Port Function Select Bit This bit selects the signal to output from the CARD4 pin. 1 (R/W): #CFCE1 0 (R/W): #OE (default) D3 CARDIO3: CARD3 Port Function Select Bit This bit selects the signal to output from the CARD3 pin. 1 (R/W): #SMWR 0 (R/W): #IOWR (default) D2 CARDIO2: CARD2 Port Function Select Bit This bit selects the signal to output from the CARD2 pin. 1 (R/W): #SMRD 0 (R/W): #IORD (default) D1 CARDIO1: CARD1 Port Function Select Bit This bit selects the signal to output from the CARD1 pin. 1 (R/W): #CFCE2 0 (R/W): #SMWR (default) D0 IV CARD CARDIO0: CARD0 Port Function Select Bit This bit selects the signal to output from the CARD0 pin. 1 (R/W): #CFCE1 0 (R/W): #SMRD (default) S1C33401 TECHNICAL MANUAL EPSON IV-9-9 IV C33 ADV BASIC PERIPHERAL BLOCK: CARD INTERFACE (CARD) IV.9.7 Precautions The PC Card interface (CARD) is subject to the following limitations: - The interface supports 16-bit PC cards, such as ATA (CF), LAN (Ethernet, wireless), or modem connected as an I/O card. SRAM cards, etc. are not supported. - Live or hot-line card insertion and removal are not supported. Power must be turned off before inserting or removing a card. The automatic recognition of cards is also not supported. - DMA, ZV, and CardBus are also not supported. - To accommodate differences in power supply voltage between the PC card (5 V or 3.3 V) and S1C33 chip, use a buffer IC (e.g., S1C37120). IV-9-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10 General-Purpose I/O Ports (PORT) I IV.10.1 Structure of I/O Port The C33 ADV Basic Peripheral Block contains I/O ports (Pxx) that can be directed for input or output through the use of a program. Although each pin is used for input/output from/to the internal peripheral circuits, some pins can be used as general-purpose input/output ports unless they are used for the peripheral circuits. Figure IV.10.1.1 shows the structure of a typical I/O port. Internal data bus I/O control register Peripheral circuit I/O control VDDE I/O control signal 1 Function select register Pxx Data register Peripheral circuit output VSS Peripheral circuit input 1 A pull-up resistor is provided depending on model. Figure IV.10.1.1 Structure of I/O Port Notes: * C33 ADV Basic Peripheral Block contains 71 I/O port cells (P0[7:0], P1[7:0], P2[7:0], P3[3:0], P4[7:0], P5[6:0], P6[7:0], P7[3:0], P8[7:0], and P9[7:0]). However, some ports cannot be used due to the limitation of the number of pins available depending on the C33 ADV model. Refer to Section I.3, "Pin Description," for the I/O port pin configuration. IV * Depending on the model, a pull-up resistor may be provided for each pin and it can be enabled/disabled by software control. Refer to Section V.4, "Pin Control Registers," for how to control the pull-up resistor. IV.10.2 Selecting the I/O Pin Functions The I/O ports concurrently serve as the input/output pins for peripheral circuits or bus signals. Whether they are used as I/O ports or for peripheral circuits/bus signals can be selected bit-for-bit using the port function select registers. All pins not used for peripheral circuits/bus signals can be used as general-purpose I/O ports. Each I/O port pin (Pxx) is initialized for a default function at cold reset. For the pin that has two or more functions assigned, the port extended function select bits (CFPxx[1:0]) provided for each I/O port pin can be used to select the desired function. The selected pin function does not initialized by a hot reset. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." The subsequent sections explain the port functions assuming that the pin has been set as a general-purpose I/O port. Note: To use the P65, P66, and P67 pins that are configured as the debug interface pins by default for general-purpose inputs/outputs, clear DPCTOE (D0/0x402EC) to 0. DPCTOE: PC Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D0/0x402EC) Note, however, that the PC trace function of the debugger cannot be used when DPCTOE (D0/ 0x402EC) is set to 0. S1C33401 TECHNICAL MANUAL EPSON IV-10-1 PORT IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.3 I/O Control Register and I/O Modes The I/O ports are directed for input or output modes by writing data to IOCx corresponding to each port bit. IOC0[7:0]: P07-P00 I/O Control Bits in the P0 I/O Control Register (D[7:0]/0x40341) IOC1[7:0]: P17-P10 I/O Control Bits in the P1 I/O Control Register (D[7:0]/0x40343) IOC2[7:0]: P27-P20 I/O Control Bits in the P2 I/O Control Register (D[7:0]/0x40345) IOC3[3:0]: P33-P30 I/O Control Bits in the P3 I/O Control Register (D[3:0]/0x40347) IOC4[7:0]: P47-P40 I/O Control Bits in the P4 I/O Control Register (D[7:0]/0x40349) IOC5[6:0]: P56-P50 I/O Control Bits in the P5 I/O Control Register (D[6:0]/0x4034B) IOC6[7:0]: P67-P60 I/O Control Bits in the P6 I/O Control Register (D[7:0]/0x4034D) IOC8[7:0]: P87-P80 I/O Control Bits in the P8 I/O Control Register (D[7:0]/0x40351) IOC9[7:0]: P97-P90 I/O Control Bits in the P9 I/O Control Register (D[7:0]/0x40353) To set an I/O port for input, write 0 to the I/O control bit. I/O ports set for input mode are placed in the highimpedance state, and thus function as input ports. In the input mode, the state of the input pin is read directly, so the data is 1 when the pin state is high (VDD level) or 0 when the pin state is low (VSS level). Even in the input mode, data can be written to the data register without affecting the pin state. To set an I/O port for output, write 1 to the I/O control bit. I/O port set for output function as output ports. When the port output data is 1, the port outputs a high level (VDD level); when the data is 0, the port outputs a low level (VSS level). At cold start, the I/O control register is set to 0 (input mode). At hot start, the pins retain their state from prior to the reset. Note: The P7x port has no I/O control register, as it is input only port. IV-10-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.4 Input Interrupt I The I/O ports support 16 system of port input interrupts and two systems of key input interrupts. IV.10.4.1 Port Input Interrupt The port input interrupt circuit has 16 interrupt systems (FPT15-FPT0) and a port can be selected for generating each cause of interrupt. The interrupt condition can also be selected from between input signal edge and input signal level. Figure IV.10.4.1.1 shows the configuration of the port input interrupt circuit. P43 P53 P67 P97 Interrupt signal generation Input port selection SPTF Input polarity selection SPPTF Internal data bus Address Edge/level selection SEPTF Address FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 Interrupt request FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 IV Figure IV.10.4.1.1 Configuration of Port Input Interrupt Circuit S1C33401 TECHNICAL MANUAL EPSON PORT IV-10-3 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) Selecting input pins The causes of interrupt allow selection of an input pin from the four predefined pins independently. Table IV.10.4.1.1 shows the control bits and the selectable pins for each cause of interrupt. Table IV.10.4.1.1 Selecting Pins for Port Input Interrupts Cause of interrupt FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 Control bit 11 SPTF[1:0] (D[7:6])/Port input interrupt select register 4 (0x40385) SPTE[1:0] (D[5:4])/Port input interrupt select register 4 (0x40385) SPTD[1:0] (D[3:2])/Port input interrupt select register 4 (0x40385) SPTC[1:0] (D[1:0])/Port input interrupt select register 4 (0x40385) SPTB[1:0] (D[7:6])/Port input interrupt select register 3 (0x40384) SPTA[1:0] (D[5:4])/Port input interrupt select register 3 (0x40384) SPT9[1:0] (D[3:2])/Port input interrupt select register 3 (0x40384) SPT8[1:0] (D[1:0])/Port input interrupt select register 3 (0x40384) SPT7[1:0] (D[7:6])/Port input interrupt select register 2 (0x40381) SPT6[1:0] (D[5:4])/Port input interrupt select register 2 (0x40381) SPT5[1:0] (D[3:2])/Port input interrupt select register 2 (0x40381) SPT4[1:0] (D[1:0])/Port input interrupt select register 2 (0x40381) SPT3[1:0] (D[7:6])/Port input interrupt select register 1 (0x40380) SPT2[1:0] (D[5:4])/Port input interrupt select register 1 (0x40380) SPT1[1:0] (D[3:2])/Port input interrupt select register 1 (0x40380) SPT0[1:0] (D[1:0])/Port input interrupt select register 1 (0x40380) P97 P96 P95 P94 P93 P92 P91 P90 P63 P62 P61 P60 P33 P32 P31 P30 SPT settings 10 01 P67 P66 P65 P64 P87 P86 P85 P84 P17 P16 P15 P14 P13 P12 P11 P10 P53 P52 P51 P50 P83 P82 P81 P80 P27 P26 P25 P24 P23 P22 P21 P20 00 P43 P42 P41 P40 P73 P72 P71 P70 P07 P06 P05 P04 P03 P02 P01 P00 Conditions for port input-interrupt generation Each port input interrupt can be generated by the edge or level of the input signal. SEPTx (Dx/0x40383, Dx 8/0x40387) is used for this selection. When SEPTx is set to 1, the FPTx interrupt will be generated at the signal edge. When SEPTx is set to 0, the FPTx interrupt will be generated by the input signal level. SEPT[7:0]: FPTx Edge/Level Select Bits in the Port Input Interrupt Edge/Level Select Register 1 (Dx/0x40383) SEPT[F:8]: FPTx Edge/Level Select Bits in the Port Input Interrupt Edge/Level Select Register 2 (Dx - 8/0x40387) Furthermore, the signal polarity can be selected using SPPTx (Dx/0x40382, Dx - 8/0x40386). SPPT[7:0]: FPTx Input Polarity Select Bits in the Port Input Interrupt Polarity Select Register 1 (Dx/0x40382) SPPT[F:8]: FPTx Input Polarity Select Bits in the Port Input Interrupt Polarity Select Register 2 (Dx - 8/0x40386) With these registers, the port input interrupt condition is decided as shown in Table IV.10.4.1.2. Table IV.10.4.1.2 Port Input Interrupt Condition SEPTx SPPTx FPTx interrupt condition 1 1 0 0 1 0 1 0 Rising edge Falling edge High level Low level When the input signal goes to the selected status, the cause-of-interrupt flag FPx is set to 1 and, if other interrupt conditions set by the interrupt controller are met, an interrupt is generated. IV-10-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.4.2 Key Input Interrupt I The key input interrupt circuit has two interrupt systems (FPK1 and FPK0) and a port group can be selected for generating each cause of interrupt. The interrupt condition can also be set by software. Figure IV.10.4.2.1 shows the configuration of the port input interrupt circuit. FPK0 system P00 P10 P20 P40 P60 P50 P80 P90 Interrupt signal generation FPK0 Interrupt request Input port selection SPPK0 Input comparison register SCPK0 Address Input mask register SMPK0 Internal data bus Address P00, P10, P20, P40, P60, P50, P80, P90 P01, P11, P21, P41, P61, P51, P81, P91 P02, P12, P22, P42, P62, P52, P82, P92 P03, P13, P23, P43, P63, P53, P83, P93 P04, P14, P24, P44, P64, P54, P84, P94 IV FPK1 system P04 P14 P24 P30 P64 P70 P84 P94 Interrupt signal generation FPK1 Interrupt request Input port selection SPPK1 PORT Input comparison register SCPK1 Address Input mask register SMPK1 Address P04, P14, P24, P30, P64, P70, P84, P94 P05, P15, P25, P31, P65, P71, P85, P95 P06, P16, P26, P32, P66, P72, P86, P96 P07, P17, P27, P33, P67, P73, P87, P97 Figure IV.10.4.2.1 Configuration of Key Input Interrupt Circuit S1C33401 TECHNICAL MANUAL EPSON IV-10-5 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) Selecting input pins For the FPK1 interrupt system, a four-bit input pin group can be selected from the eight predefined groups. For the FPK0 system, a five-bit input pin group can be selected. Table IV.10.4.2.1 shows the control bits and the selectable groups for each cause of interrupt. Table IV.10.4.2.1 Selecting Pins for Key Input Interrupts Cause of interrupt FPK1 FPK0 Control bit 111 110 101 SPPK settings 011 100 010 001 000 SPPK1[2:0] (D[6:4]) Key input interrupt select P9[7:4] P8[7:4] P7[3:0] P6[7:4] P3[3:0] P2[7:4] P1[7:4] P0[7:4] SPPK0[2:0] (D[2:0]) register (0x40390) P9[4:0] P8[4:0] P5[4:0] P6[4:0] P4[4:0] P2[4:0] P1[4:0] P0[4:0] Conditions for key input-interrupt generation The key input interrupt circuit has the input mask bits SMPK0[4:0] (D[4:0]/0x40394) for FPK0 and SMPK1[3:0] (D[3:0]/0x40395) for FPK1, and the input comparison bits SCPK0[4:0] (D[4:0]/0x40392) for FPK0 and SCPK1[3:0] (D[3:0]/0x40393) for FPK1 to set input-interrupt conditions. SMPK0[4:0]: FPK0 Input Mask Bits in the Key Input Interrupt (FPK0) Input Mask Register (D[4:0]/0x40394) SMPK1[3:0]: FPK1 Input Mask Bits in the Key Input Interrupt (FPK1) Input Mask Register (D[3:0]/0x40395) SCPK0[4:0]: FPK0 Input Comparison Bits in the Key Input Interrupt (FPK0) Input Comparison Register (D[4:0]/0x40392) SCPK1[3:0]: FPK1 Input Comparison Bits in the Key Input Interrupt (FPK1) Input Comparison Register (D[3:0]/0x40393) The input mask bit (SMPK) is used to mask the input pin that is not used for an interrupt. This bit masks each input pin, whereas the interrupt enable bit of the interrupt controller masks the cause of interrupt for each interrupt group. The input comparison bit (SCPK) is used to select whether an interrupt for each input port is to be generated at the rising or falling edge of the input. A change in state occurs so that the input pin enabled for interrupt by the interrupt mask bit (SMPK) and the content of the input comparison bit (SCPK) become unmatched after being matched, the cause-of-interrupt flag (FK) is set to 1 and, if other interrupt conditions are met, an interrupt is generated. Figure IV.10.4.2.2 shows cases in which a FPK0 interrupt is generated. Here, it is assumed that the P0[4:0] pins are selected for the input-pin group and the control register of the interrupt controller is set so as to enable generation of a FPK0 interrupt. Input mask register SMPK0 SMPK04 SMPK03 SMPK02 SMPK01 SMPK00 1 1 1 1 0 Input comparison register SCPK0 SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 1 1 0 1 0 With the settings shown above, FPK0 interrupt is generated under the condition shown below. Input port P0 (1) P04 P03 1 P02 0 P01 P00 1 0 P04 1 P03 P02 P01 P00 1 0 1 1 P04 P03 P00 0 P02 0 P01 1 1 0 P04 P03 P02 P01 P00 1 0 1 1 0 1 (2) (3) (4) (Initial value) Interrupt generation Because interrupt has been disabled for P00, an interrupt will be generated when non-conformity occurs between the contents of the four bits P01-P04 and the four input comparison bits SCPK0[4:1]. Figure IV.10.4.2.2 FPK0 Interrupt Generation Example (when P0[4:0] is selected by SPPK0[2:0]) IV-10-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) Since P00 is masked from interrupt by SMPK00 (D0/0x40394), no interrupt occurs at that point (2) above. Next, because P03 becomes 0 at (3), an interrupt is generated due to the lack of a match between the data of the input pin P0[4:1] that is enabled for interrupt and that of the input comparison register SCPK0[4:1] (D[4:1]/ 0x40392). Since only a change in states in which the input data and the content of SCPKx (D[4:0]/0x40392, D[3:0]/ 0x40393) become unmatched after being matched constitutes an interrupt generation condition as described above, no interrupt is generated when a change in states from one unmatched state to another, as in (4), occurs. Consequently, if another interrupt is to be generated again following the occurrence of an interrupt, the state of the input pin must be temporarily restored to the same content as that of SCPKx, or SCPKx must be set again. Note that the input pins masked from interrupt by SMPKx (D[4:0]/0x40394, D[3:0]/0x40395) do not affect interrupt generation conditions. I An interrupt is generated for FPK1 in the same way as described above. IV.10.4.3 Control Registers of the Interrupt Controller Table IV.10.4.3.1 shows the control registers of the interrupt controller that are provided for each input-interrupt system. Table IV.10.4.3.1 Control Registers of Interrupt Controller System Cause-of-interrupt flag Interrupt enable register Interrupt priority register FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 FPK1 FPK0 FP15(D7/0x402A9) FP14(D6/0x402A9) FP13(D5/0x402A9) FP12(D4/0x402A9) FP11(D3/0x402A9) FP10(D2/0x402A9) FP9(D1/0x402A9) FP8(D0/0x402A9) FP7(D6/0x40287) FP6(D5/0x40287) FP5(D4/0x40287) FP4(D3/0x40287) FP3(D3/0x40280) FP2(D2/0x40280) FP1(D1/0x40280) FP0(D0/0x40280) FK1(D5/0x40280) FK0(D4/0x40280) EP15(D7/0x402A6) EP14(D6/0x402A6) EP13(D5/0x402A6) EP12(D4/0x402A6) EP11(D3/0x402A6) EP10(D2/0x402A6) EP9(D1/0x402A6) EP8(D0/0x402A6) EP7(D6/0x40277) EP6(D5/0x40277) EP5(D4/0x40277) EP4(D3/0x40277) EP3(D3/0x40270) EP2(D2/0x40270) EP1(D1/0x40270) EP0(D0/0x40270) EK1(D5/0x40270) EK0(D4/0x40270) PP15L[2:0](D[6:4]/0x402A3) PP14L[2:0](D[2:0]/0x402A3) PP13L[2:0](D[6:4]/0x402A2) PP12L[2:0](D[2:0]/0x402A2) PP11L[2:0](D[6:4]/0x402A1) PP10L[2:0](D[2:0]/0x402A1) PP9L[2:0](D[6:4]/0x402A0) PP8L[2:0](D[2:0]/0x402A0) PP7L[2:0](D[6:4]/0x4026D) PP6L[2:0](D[2:0]/0x4026D) PP5L[2:0](D[6:4]/0x4026C) PP4L[2:0](D[2:0]/0x4026C) PP3L[2:0](D[6:4]/0x40261) PP2L[2:0](D[2:0]/0x40261) PP1L[2:0](D[6:4]/0x40260) PP0L[2:0](D[2:0]/0x40260) PK1L[2:0](D[6:4]/0x40262) PK0L[2:0](D[2:0]/0x40262) IV When the interrupt generation condition described above is met, the corresponding cause-of-interrupt flag is set to 1. If the interrupt enable register bit for that cause of interrupt has been set to 1, an interrupt request is generated. Interrupts due to a cause of interrupt can be disabled by leaving the interrupt enable register bit for that cause of interrupt set to 0. The cause-of-interrupt flag is set to 1 whenever interrupt generation conditions are met, regardless of the setting of the interrupt enable register. The interrupt priority register sets the interrupt priority level (0 to 7) for each interrupt system. An interrupt request to the CPU is accepted only when no other interrupt request of a higher priority has been generated. In addition, only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the input interrupt level set using the interrupt priority register will the input interrupt request actually be accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to Section IV.2, "Interrupt Controller (ITC)." S1C33401 TECHNICAL MANUAL EPSON IV-10-7 PORT IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) Intelligent DMA The port input interrupt system can invoke an intelligent DMA (IDMA) through the use of its cause of interrupt. This enables the port inputs to be used as a trigger to perform DMA transfer. The following shows the IDMA channel numbers assigned to each cause of interrupt: IDMA Ch. IDMA Ch. FPT0 input interrupt: 1 FPT8 input interrupt: 38 FPT1 input interrupt: 2 FPT9 input interrupt: 39 FPT2 input interrupt: 3 FPT10 input interrupt: 40 FPT3 input interrupt: 4 FPT11 input interrupt: 41 FPT4 input interrupt: 28 FPT12 input interrupt: 42 FPT5 input interrupt: 29 FPT13 input interrupt: 43 FPT6 input interrupt: 30 FPT14 input interrupt: 44 FPT7 input interrupt: 31 FPT15 input interrupt: 45 For IDMA to be invoked, the IDMA request and IDMA enable bits shown in Table IV.10.4.3.2 must be set to 1 in advance. Transfer conditions, etc. must also be set on the IDMA side in advance. Table IV.10.4.3.2 Control Bits for IDMA Transfer System IDMA request bit IDMA enable bit FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 RP15(D7/0x402AC) RP14(D6/0x402AC) RP13(D5/0x402AC) RP12(D4/0x402AC) RP11(D3/0x402AC) RP10(D2/0x402AC) RP9(D1/0x402AC) RP8(D0/0x402AC) RP7(D7/0x40293) RP6(D6/0x40293) RP5(D5/0x40293) RP4(D4/0x40293) RP3(D3/0x40290) RP2(D2/0x40290) RP1(D1/0x40290) RP0(D0/0x40290) DEP15(D7/0x402AE) DEP14(D6/0x402AE) DEP13(D5/0x402AE) DEP12(D4/0x402AE) DEP11(D3/0x402AE) DEP10(D2/0x402AE) DEP9(D1/0x402AE) DEP8(D0/0x402AE) DEP7(D7/0x40297) DEP6(D6/0x40297) DEP5(D5/0x40297) DEP4(D4/0x40297) DEP3(D3/0x40294) DEP2(D2/0x40294) DEP1(D1/0x40294) DEP0(D0/0x40294) If the IDMA request and enable bits are set to 1, IDMA is invoked through generation of a cause of interrupt. No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is completed. The registers can also be set so as not to generate an interrupt, with only DMA transfers performed. For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." Trap vectors The trap-vector address of each input default cause of interrupt is set as follows: FPT0 input interrupt: 0x20000040 FPT7 input interrupt: 0x2000011C FPT1 input interrupt: 0x20000044 FPT8 input interrupt: 0x20000150 FPT2 input interrupt: 0x20000048 FPT9 input interrupt: 0x20000154 FPT3 input interrupt: 0x2000004C FPT10 input interrupt: 0x20000158 FPK0 input interrupt: 0x20000050 FPT11 input interrupt: 0x2000015C FPK1 input interrupt: 0x20000054 FPT12 input interrupt: 0x20000160 FPT4 input interrupt: 0x20000110 FPT13 input interrupt: 0x20000164 FPT5 input interrupt: 0x20000114 FPT14 input interrupt: 0x20000168 FPT6 input interrupt: 0x20000118 FPT15 input interrupt: 0x2000016C The base address of the trap table can be changed using the TTBR register. IV-10-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.5 I/O Port Operating Clock I The I/O port module is clocked by the peripheral circuit clock (PCLK) supplied by the CMU. When initially reset, this clock is selected for supply to the I/O port. However, when all the I/O ports are idle or not in use, clock supply from the CMU may be turned off to reduce current consumed on the chip. Use POT1CLK (D0/0x40181) of the CMU for this control. POT1CLK: Port Clock Control Bit in the Peripheral Clock Control Register 2 (D0/0x40181) Setting POT1CLK (D0/0x40181) to 0 stops clock supply from the CMU to the I/O port. When the CMU stop supplying the PCLK clock to the I/O port, all the I/O port registers are disabled for writing. However, the I/O port can generate the port input and key input interrupts and the cause-of-interrupt flags can also be reset in software. Furthermore, input pin levels can be read correctly. For details of the generation and control of PCLK, see Section II.3, "Clock Management Unit (CMU)." Note: The Peripheral Clock Control Register 2 (0x40181) is write-protected. Write protection of this and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said registers. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-9 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.6 Details of Control Registers Table IV.10.6.1 List of I/O Port Registers Address 0x00040340 0x00040341 0x00040342 0x00040343 0x00040344 0x00040345 0x00040346 0x00040347 0x00040348 0x00040349 0x0004034A 0x0004034B 0x0004034C 0x0004034D 0x0004034E 0x00040350 0x00040351 0x00040352 0x00040353 0x00040360 0x00040361 0x00040362 0x00040363 0x00040364 0x00040365 0x00040366 0x00040368 0x00040369 0x0004036A 0x0004036B 0x0004036C 0x0004036D 0x0004036E 0x00040370 0x00040371 0x00040372 0x00040373 0x00040380 0x00040381 0x00040382 0x00040383 0x00040384 0x00040385 0x00040386 0x00040387 0x00040390 0x00040392 0x00040393 0x00040394 0x00040395 Size Register name Function 8 P0 Port Data Register (pP0_P0D) P0 port data read/write register 8 P0 I/O Control Register (pP0_IOC0) Controls P0 port input/output direction. 8 P1 Port Data Register (pP1_P1D) P1 port data read/write register 8 P1 I/O Control Register (pP1_IOC1) Controls P1 port input/output direction. 8 P2 Port Data Register (pP2_P2D) P2 port data read/write register 8 P2 I/O Control Register (pP2_IOC2) Controls P2 port input/output direction. 8 P3 Port Data Register (pP3_P3D) P3 port data read/write register 8 P3 I/O Control Register (pP3_IOC3) Controls P3 port input/output direction. 8 P4 Port Data Register (pP4_P4D) P4 port data read/write register 8 P4 I/O Control Register (pP4_IOC4) Controls P4 port input/output direction. 8 P5 Port Data Register (pP5_P5D) P5 port data read/write register 8 P5 I/O Control Register (pP5_IOC5) Controls P5 port input/output direction. 8 P6 Port Data Register (pP6_P6D) P6 port data read/write register 8 P6 I/O Control Register (pP6_IOC6) Controls P6 port input/output direction. 8 P7 Port Data Register (pP7_P7D) P7 port data read/write register 8 P8 Port Data Register (pP8_P8D) P8 port data read/write register 8 P8 I/O Control Register (pP8_IOC8) Controls P8 port input/output direction. 8 P9 Port Data Register (pP9_P9D) P9 port data read/write register 8 P9 I/O Control Register (pP9_IOC9) Controls P9 port input/output direction. 8 P00-P03 Port Function Select Register (pP0_03_CFP) Sets P00-P03 port pin function. 8 P04-P07 Port Function Select Register (pP0_47_CFP) Sets P04-P07 port pin function. 8 P10-P13 Port Function Select Register (pP1_03_CFP) Sets P10-P13 port pin function. 8 P14-P17 Port Function Select Register (pP1_47_CFP) Sets P14-P17 port pin function. 8 P20-P23 Port Function Select Register (pP2_03_CFP) Sets P20-P23 port pin function. 8 P24-P27 Port Function Select Register (pP2_47_CFP) Sets P24-P27 port pin function. 8 P30-P33 Port Function Select Register (pP3_03_CFP) Sets P30-P33 port pin function. 8 P40-P43 Port Function Select Register (pP4_03_CFP) Sets P40-P43 port pin function. 8 P44-P47 Port Function Select Register (pP4_47_CFP) Sets P44-P47 port pin function. 8 P50-P53 Port Function Select Register (pP5_03_CFP) Sets P50-P53 port pin function. 8 P54-P56 Port Function Select Register (pP5_46_CFP) Sets P54-P56 port pin function. 8 P60-P63 Port Function Select Register (pP6_03_CFP) Sets P60-P63 port pin function. 8 P64-P67 Port Function Select Register (pP6_47_CFP) Sets P64-P67 port pin function. 8 P70-P73 Port Function Select Register (pP7_03_CFP) Sets P70-P73 port pin function. 8 P80-P83 Port Function Select Register (pP8_03_CFP) Sets P80-P83 port pin function. 8 P84-P87 Port Function Select Register (pP8_47_CFP) Sets P84-P87 port pin function. 8 P90-P93 Port Function Select Register (pP9_03_CFP) Sets P90-P93 port pin function. 8 P94-P97 Port Function Select Register (pP9_47_CFP) Sets P94-P97 port pin function. 8 Port Input Interrupt Select Register 1 Selects ports used for FPT0-FPT3 port input (pPINTSEL_SPT03) interrupts. 8 Port Input Interrupt Select Register 2 Selects ports used for FPT4-FPT7 port input (pPINTSEL_SPT47) interrupts. 8 Port Input Interrupt Polarity Select Register 1 Selects signal polarity to generate FPT0-FPT7 port (pPINTPOL_SPP07) input interrupts. 8 Port Input Interrupt Edge/Level Select Register 1 Selects FPT0-FPT7 port interrupt trigger condition. (pPINTEL_SEPT07) 8 Port Input Interrupt Select Register 3 Selects ports used for FPT8-FPT11 port input (pPINTSEL_SPT811) interrupts. 8 Port Input Interrupt Select Register 4 Selects ports used for FPT12-FPT15 port input (pPINTSEL_SPT1215) interrupts. 8 Port Input Interrupt Polarity Select Register 2 Selects signal polarity to generate FPT8-FPT15 port (pPINTPOL_SPP815) input interrupts. Port Input Interrupt Edge/Level Select Register 2 8 Selects FPT8-FPT15 port interrupt trigger condition. (pPINTEL_SEPT815) Key Input Interrupt Select Register (pKINTSEL_SPPK01) 8 Selects ports used for key input interrupts. Key Input Interrupt (FPK0) Input Comparison Register 8 Sets FPK0 interrupt trigger edge condition. (pKINTCOMP_SCPK0) Key Input Interrupt (FPK1) Input Comparison Register 8 Sets FPK1 interrupt trigger edge condition. (pKINTCOMP_SCPK1) Key Input Interrupt (FPK0) Input Mask Register 8 Enables/disables ports for generating FPK0 (pKINTCOMP_SMPK0) interrupts. Key Input Interrupt (FPK1) Input Mask Register 8 Enables/disables ports for generating FPK1 (pKINTCOMP_SMPK1) interrupts. The following describes each I/O port control register. The I/O port control registers are mapped in the 8-bit device area from 0x40340 to 0x40395, and can be accessed in units of bytes. IV-10-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40340-0x40352: Px Port Data Registers (pPx_PxD) Register name Address Bit 0040340 | 0040352 (B) D7 D6 D5 D4 D3 D2 D1 D0 Px port data register (pPx_PxD) Name Px7D Px6D Px5D Px4D Px3D Px2D Px1D Px0D Function Px7 I/O port data Px6 I/O port data Px5 I/O port data Px4 I/O port data Px3 I/O port data Px2 I/O port data Px1 I/O port data Px0 I/O port data Setting 1 High 0 Low I Init. R/W Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. Remarks R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W Note: The letter `x' in bit names, etc., denotes a port number from 0 to 6 and 8, 9. 0x40340 0x40342 0x40344 0x40346 0x40348 0x4034A 0x4034C 0x40350 0x40352 P0 Port Data Register (pP0_P0D) P1 Port Data Register (pP1_P1D) P2 Port Data Register (pP2_P2D) P3 Port Data Register (pP3_P3D) P4 Port Data Register (pP4_P4D) P5 Port Data Register (pP5_P5D) P6 Port Data Register (pP6_P6D) P8 Port Data Register (pP8_P8D) P9 Port Data Register (pP9_P9D) These registers are used to read data from I/O-port pins or to set output data. (Default: external pin status) 1 (R/W): High level 0 (R/W): Low level When an I/O port is set for output, the data written to the register is directly output to the I/O port pin. If the data written to the port is 1, the port pin is set high (VDD or VDDE level); if the data is 0, the port pin is set low (VSS level). Even in input mode, data can be written to the port data register. When the register is read, the voltage level on the port pin is read out regardless of whether an I/O port is set for input or output mode. If the pin voltage is high (VDD or VDDE level), 1 is read out as input data; if the pin voltage is low (VSS level), 0 is read out as input data. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-11 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x4034E: P7 Port Data Register (pP7_P7D) Register name Address P7 port data register (pP7_P7D) Bit Name 004034E D7-4 - D3 P73D (B) D2 P72D D1 P71D D0 P70D Function reserved P73 input port data P72 input port data P71 input port data P70 input port data Setting - 1 High 0 Low Init. R/W - Ext. Ext. Ext. Ext. - R R R R Remarks 0 when being read. Ext.: The initial value depends on the external pin status. This register is used to read data from P7 I/O-port pins. (Default: external pin status) 1 (R): High level 0 (R): Low level The voltage level on the port pin is read out. If the pin voltage is high (AVDD and VDDE level), 1 is read out as input data; if the pin voltage is low (VSS level), 0 is read out as input data. Note: The P7 port has no output function, therefore this register is a read only register. IV-10-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40341-0x40353: Px I/O Control Registers (pPx_IOCx) Register name Address Bit 0040341 | 0040353 (B) D7 D6 D5 D4 D3 D2 D1 D0 Px I/O control register (pPx_IOCx) Name IOCx7 IOCx6 IOCx5 IOCx4 IOCx3 IOCx2 IOCx1 IOCx0 Function Px7 I/O control Px6 I/O control Px5 I/O control Px4 I/O control Px3 I/O control Px2 I/O control Px1 I/O control Px0 I/O control Setting 1 Output I Init. R/W 0 Input 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W R/W R/W R/W R/W Note: The letter `x' in bit names, etc., denotes a port number from 0 to 6 and 8, 9. 0x40341 0x40343 0x40345 0x40347 0x40349 0x4034B 0x4034D 0x40351 0x40353 P0 I/O Control Register (pP0_IOC0) P1 I/O Control Register (pP1_IOC1) P2 I/O Control Register (pP2_IOC2) P3 I/O Control Register (pP3_IOC3) P4 I/O Control Register (pP4_IOC4) P5 I/O Control Register (pP5_IOC5) P6 I/O Control Register (pP6_IOC6) P8 I/O Control Register (pP8_IOC8) P9 I/O Control Register (pP9_IOC9) Directs an I/O port for input or output and indicates the I/O control signal value of the port. 1 (R/W): Output mode 0 (R/W): Input mode (default) Each I/O control register bit corresponds to each I/O port. When IOCx is set to 1, the corresponding I/O port is directed for output; if it is set to 0, the I/O port is directed for input. When the pin is used for a peripheral function, the input/output direction depends on the peripheral function. When the register is read, the I/O control signal value for the port pin is read out. When I/O port function is selected using the port function select register, the value written to the IOC register is read out as is. When peripheral function is selected, the read value depends on the peripheral circuit status and may not indicate the value written to IOCx. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-13 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40360-0x40373: Pxx Port Function Select Registers (pPx_xx_CFP) Register name Address Bit Name 0040360 | 0040373 (B) D7 D6 CFPx31 CFPx30 or CFPx71 CFPx70 CFPx21 CFPx20 or CFPx61 CFPx60 CFPx11 CFPx10 or CFPx51 CFPx50 CFPx01 CFPx00 or CFPx41 CFPx40 Px0-Px3 port function select register (pPx_03_CFP) or Px4-Px7 port function select register (pPx_47_CFP) D5 D4 D3 D2 D1 D0 Function Px3/Px7 port extended function Px2/Px6 port extended function Px1/Px5 port extended function Px0/Px4 port extended function Setting CFPx3/7[1:0] 11 10 01 00 CFPx2/6[1:0] 11 10 01 00 CFPx1/5[1:0] 11 10 01 00 CFPx0/4[1:0] 11 10 01 00 Init. R/W Function Pin function 3 Pin function 2 Pin function 1 Pin function 0 Function Pin function 3 Pin function 2 Pin function 1 Pin function 0 Function Pin function 3 Pin function 2 Pin function 1 Pin function 0 Function Pin function 3 Pin function 2 Pin function 1 Pin function 0 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks Note: The letter `x' in bit names, etc., denotes a port number from 0 to 9. 0x40360 0x40361 0x40362 0x40363 0x40364 0x40365 0x40366 0x40368 0x40369 0x4036A 0x4036B 0x4036C 0x4036D 0x4036E 0x40370 0x40371 0x40372 0x40373 P00-P03 Port Function Select Register (pP0_03_CFP) P04-P07 Port Function Select Register (pP0_47_CFP) P10-P13 Port Function Select Register (pP1_03_CFP) P14-P17 Port Function Select Register (pP1_47_CFP) P20-P23 Port Function Select Register (pP2_03_CFP) P24-P27 Port Function Select Register (pP2_47_CFP) P30-P33 Port Function Select Register (pP3_03_CFP) P40-P43 Port Function Select Register (pP4_03_CFP) P44-P47 Port Function Select Register (pP4_47_CFP) P50-P53 Port Function Select Register (pP5_03_CFP) P54-P56 Port Function Select Register (pP5_46_CFP) P60-P63 Port Function Select Register (pP6_03_CFP) P64-P67 Port Function Select Register (pP6_47_CFP) P70-P73 Port Function Select Register (pP7_03_CFP) P80-P83 Port Function Select Register (pP8_03_CFP) P84-P87 Port Function Select Register (pP8_47_CFP) P90-P93 Port Function Select Register (pP9_03_CFP) P97-P97 Port Function Select Register (pP9_47_CFP) These bits select the function of each I/O port pin. (Default: 0b00 = Pin function 0) The I/O ports concurrently serve as the input/output pins for peripheral circuits or bus signals. Whether they are used as I/O ports or for peripheral circuits/bus signals can be selected bit-for-bit using these registers. All pins not used for peripheral circuits/bus signals can be used as general-purpose I/O ports. For details of pin functions, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." IV-10-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40380: Port Input Interrupt Select Register 1 (pPINTSEL_SPT03) 0x40381: Port Input Interrupt Select Register 2 (pPINTSEL_SPT47) 0x40384: Port Input Interrupt Select Register 3 (pPINTSEL_SPT811) 0x40385: Port Input Interrupt Select Register 4 (pPINTSEL_SPT1215) Name Register name Address Bit 0040380 Port input (B) interrupt select register 1 (pPINTSEL _SPT03) D7 D6 SPT31 SPT30 D5 D4 SPT21 SPT20 D3 D2 SPT11 SPT10 D1 D0 SPT01 SPT00 D7 D6 SPT71 SPT70 D5 D4 SPT61 SPT60 D3 D2 SPT51 SPT50 D1 D0 SPT41 SPT40 D7 D6 SPTB1 SPTB0 D5 D4 SPTA1 SPTA0 D3 D2 SPT91 SPT90 D1 D0 SPT81 SPT80 0040381 Port input (B) interrupt select register 2 (pPINTSEL _SPT47) Port input 0040384 interrupt select (B) register 3 (pPINTSEL _SPT811) S1C33401 TECHNICAL MANUAL Function FPT3 interrupt input port selection SPT3[1:0] 11 10 01 00 FPT2 interrupt input port selection SPT2[1:0] 11 10 01 00 FPT1 interrupt input port selection SPT1[1:0] 11 10 01 00 FPT0 interrupt input port selection SPT0[1:0] 11 10 01 00 FPT7 interrupt input port selection SPT7[1:0] 11 10 01 00 FPT6 interrupt input port selection SPT6[1:0] 11 10 01 00 FPT5 interrupt input port selection SPT5[1:0] 11 10 01 00 FPT4 interrupt input port selection SPT4[1:0] 11 10 01 00 FPT11 interrupt input port selection SPTB[1:0] 11 10 01 00 FPT10 interrupt input port selection SPTA[1:0] 11 10 01 00 FPT9 interrupt input port selection SPT9[1:0] 11 10 01 00 FPT8 interrupt input port selection SPT8[1:0] 11 10 01 00 EPSON Setting Init. R/W Port P33 P13 P23 P03 Port P32 P12 P22 P02 Port P31 P11 P21 P01 Port P30 P10 P20 P00 Port P63 P17 P27 P07 Port P62 P16 P26 P06 Port P61 P15 P25 P05 Port P60 P14 P24 P04 Port P93 P87 P83 P73 Port P92 P86 P82 P72 Port P91 P85 P81 P71 Port P90 P84 P80 P70 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W I Remarks IV PORT IV-10-15 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) Name Register name Address Bit 0040385 Port input (B) interrupt select register 4 (pPINTSEL _SPT1215) D7 D6 SPTF1 SPTF0 D5 D4 SPTE1 SPTE0 D3 D2 SPTD1 SPTD0 D1 D0 SPTC1 SPTC0 Function Setting FPT15 interrupt input port selection SPTF[1:0] 11 10 01 00 FPT14 interrupt input port selection SPTE[1:0] 11 10 01 00 FPT13 interrupt input port selection SPTD[1:0] 11 10 01 00 FPT12 interrupt input port selection SPTC[1:0] 11 10 01 00 Init. R/W Port P97 P67 P53 P43 Port P96 P66 P52 P42 Port P95 P65 P51 P41 Port P94 P64 P50 P40 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks SPTx[1:0]: FPTx Interrupt Input Port Select Bits Selects an input pin used to generate the FPTx port input interrupt. Table IV.10.6.2 Selecting Pins for Port Input Interrupts IV-10-16 Interrupt system 11 FPT15 FPT14 FPT13 FPT12 FPT11 FPT10 FPT9 FPT8 FPT7 FPT6 FPT5 FPT4 FPT3 FPT2 FPT1 FPT0 P97 P96 P95 P94 P93 P92 P91 P90 P63 P62 P61 P60 P33 P32 P31 P30 SPT settings 10 01 P67 P66 P65 P64 P87 P86 P85 P84 P17 P16 P15 P14 P13 P12 P11 P10 EPSON 00 P53 P43 P52 P42 P51 P41 P50 P40 P83 P73 P82 P72 P81 P71 P80 P70 P27 P07 P26 P06 P25 P05 P24 P04 P23 P03 P22 P02 P21 P01 P20 P00 (Default: 0b00) S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40382: Port Input Interrupt Polarity Select Register 1 (pPINTPOL_SPP07) 0x40386: Port Input Interrupt Polarity Select Register 2 (pPINTPOL_SPP815) Name Register name Address Bit Port input interrupt polarity select register 1 (pPINTPOL _SPP07) 0040382 (B) D7 D6 D5 D4 D3 D2 D1 D0 SPPT7 SPPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 FPT7 input polarity selection FPT6 input polarity selection FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 High level 0 Low level or or Falling edge Rising edge 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Port input interrupt polarity select register 2 (pPINTPOL _SPP815) 0040386 (B) D7 D6 D5 D4 D3 D2 D1 D0 SPPTF SPPTE SPPTD SPPTC SPPTB SPPTA SPPT9 SPPT8 FPT15 input polarity selection FPT14 input polarity selection FPT13 input polarity selection FPT12 input polarity selection FPT11 input polarity selection FPT10 input polarity selection FPT9 input polarity selection FPT8 input polarity selection 1 High level 0 Low level or or Falling edge Rising edge 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Function Setting Init. R/W I Remarks These registers are used to select the input signal polarity for generating port input interrupts. 1 (R/W): High level or Rising edge (default) 0 (R/W): Low level or Falling edge SPPTx is the input polarity select bit corresponding to the FPTx interrupt. When SPPTx is set to 1, the FPTx interrupt will be generated by a high level input or at the rising edge. When SPPTx is set to 0, the interrupt will be generated by a low level input or at the falling edge. An edge or a level interrupt is selected by SEPTx (0x40383, 0x40387). D[7:0]/0x40382 SPPT[7:0]: FPT[7:0] Interrupt Polarity Select Bits Selects input signal polarity to generate an FPT[7:0] interrupt. D[7:0]/0x40386 SPPT[F:8]: FPT[15:8] Interrupt Polarity Select Bits Selects input signal polarity to generate an FPT[15:8] interrupt. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-17 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40383: Port Input Interrupt Edge/Level Select Register 1 (pPINTEL_SEPT07) 0x40387: Port Input Interrupt Edge/Level Select Register 2 (pPINTEL_SEPT815) Name Register name Address Bit 0040383 Port input (B) interrupt edge/level select register 1 (pPINTEL _SEPT07) D7 D6 D5 D4 D3 D2 D1 D0 SEPT7 SEPT6 SEPT5 SEPT4 SEPT3 SEPT2 SEPT1 SEPT0 FPT7 edge/level selection FPT6 edge/level selection FPT5 edge/level selection FPT4 edge/level selection FPT3 edge/level selection FPT2 edge/level selection FPT1 edge/level selection FPT0 edge/level selection 1 Edge 0 Level 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0040387 Port input (B) interrupt edge/level select register 2 (pPINTEL _SEPT815) D7 D6 D5 D4 D3 D2 D1 D0 SEPTF SEPTE SEPTD SEPTC SEPTB SEPTA SEPT9 SEPT8 FPT15 edge/level selection FPT14 edge/level selection FPT13 edge/level selection FPT12 edge/level selection FPT11 edge/level selection FPT10 edge/level selection FPT9 edge/level selection FPT8 edge/level selection 1 Edge 0 Level 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Function Setting Init. R/W Remarks These registers are used to select an edge trigger or a level sense condition for generating port input interrupts. 1 (R/W): Edge (default) 0 (R/W): Level SEPTx is the edge/level select bit corresponding to the FPTx interrupt. When SEPTx is set to 1, the FPTx interrupt will be generated at the signal edge. Either falling edge or rising edge can be selected by SPPTx (0x40382, 0x40386). When SEPTx is set to 0, the interrupt will be generated by the level (high or low) specified with SPPTx. D[7:0]/0x40383 SEPT[7:0]: FPT[7:0] Edge/Level Select Bits Selects an edge trigger or a level sense for the FPT[7:0] interrupt. D[7:0]/0x40387 SEPT[F:8]: FPT[15:8] Edge/Level Select Bits Selects an edge trigger or a level sense for the FPT[15:8] interrupt. IV-10-18 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40390: Key Input Interrupt Select Register (pKINTSEL_SPPK01) Register name Address Bit Name 0040390 Key input (B) interrupt select register (pKINTSEL _SPPK01) D7 D6 D5 D4 - SPPK12 SPPK11 SPPK10 D3 D2 D1 D0 - SPPK02 SPPK01 SPPK00 Function Setting reserved FPK1 interrupt input port selection SPPK1[2:0] 111 110 101 100 011 010 001 000 reserved FPK0 interrupt input port selection SPPK0[2:0] 111 110 101 100 011 010 001 000 Init. R/W - Port P9[7:4] P8[7:4] P7[3:0] P6[7:4] P3[3:0] P2[7:4] P1[7:4] P0[7:4] - Port P9[4:0] P8[4:0] P5[4:0] P6[4:0] P4[4:0] P2[4:0] P1[4:0] P0[4:0] I Remarks - 0 0 0 - 0 when being read. R/W - 0 0 0 - 0 when being read. R/W This register is used to select an input-pin group for generating key interrupts. Table IV.10.6.3 Selecting Pins for Key Input Interrupts Interrupt system FPK1 FPK0 111 110 101 SPPK settings 011 100 010 001 000 P9[7:4] P8[7:4] P7[3:0] P6[7:4] P3[3:0] P2[7:4] P1[7:4] P0[7:4] P9[4:0] P8[4:0] P5[4:0] P6[4:0] P4[4:0] P2[4:0] P1[4:0] P0[4:0] (Default: 0b000) D7 Reserved D[6:4] SPPK1[2:0]: FPK1 Interrupt Input Port Select Bits Selects an input-pin group for the FPK1 interrupt. D3 Reserved D[2:0] SPPK0[2:0]: FPK0 Interrupt Input Port Select Bits Selects an input-pin group for the FPK0 interrupt. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-19 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40392: Key Input Interrupt (FPK0) Input Comparison Register (pKINTCOMP_SCPK0) 0x40393: Key Input Interrupt (FPK1) Input Comparison Register (pKINTCOMP_SCPK1) Register name Address Key input interrupt (FPK0) input comparison register (pKINTCOMP _SCPK0) 0040392 (B) Key input interrupt (FPK1) input comparison register (pKINTCOMP _SCPK1) 0040393 (B) Name Bit D7-5 - Function Setting reserved - D4 D3 D2 D1 D0 D7-4 SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 - FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison reserved 1 High D3 D2 D1 D0 SCPK13 SCPK12 SCPK11 SCPK10 FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 input comparison 1 High 0 Low - 0 Low Init. R/W - - 0 0 0 0 0 R/W R/W R/W R/W R/W - - 0 0 0 0 R/W R/W R/W R/W Remarks 0 when being read. 0 when being read. D[4:0]/0x40392 SCPK0[4:0]: FPK0[4:0] Input Comparison Bits Sets the conditions for generating FPK0 key-input interrupts (timing of interrupt generation). 1 (R/W): Falling edge 0 (R/W): Rising edge (default) SCPK0[4:0] is compared with the input state of five bits of the FPK0 input ports, and when a change in states from a matched to an unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by SMPK0[4:0] (D[4:0]/0x40394)). D[3:0]/0x40393 SCPK1[3:0]: FPK1[3:0] Input Comparison Bits Sets the conditions for generating FPK1 key-input interrupts (timing of interrupt generation). 1 (R/W): Falling edge 0 (R/W): Rising edge (default) SCPK1[3:0] is compared with the input state of four bits of the FPK1 input ports, and when a change in states from a matched to an unmatched state occurs in either, an interrupt is generated (except for the inputs disabled from interrupt by SMPK1[3:0] (D[3:0]/0x40395)). IV-10-20 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) 0x40394: Key Input Interrupt (FPK0) Input Mask Register (pKINTCOMP_SMPK0) 0x40395: Key Input Interrupt (FPK1) Input Mask Register (pKINTCOMP_SMPK1) Register name Address Key input interrupt (FPK0) input mask register (pKINTCOMP _SMPK0) 0040394 (B) Key input interrupt (FPK1) input mask register (pKINTCOMP _SMPK1) 0040395 (B) Name Bit Function D7-5 D4 D3 D2 D1 D0 D7-4 - SMPK04 SMPK03 SMPK02 SMPK01 SMPK00 - reserved FPK04 input mask FPK03 input mask FPK02 input mask FPK01 input mask FPK00 input mask reserved D3 D2 D1 D0 SMPK13 SMPK12 SMPK11 SMPK10 FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask Setting - 1 Interrupt enabled 0 Interrupt disabled - 1 Interrupt enabled 0 Interrupt disabled I Init. R/W Remarks - 0 0 0 0 0 - - 0 when being read. R/W R/W R/W R/W R/W 0 0 0 0 R/W R/W R/W R/W - 0 when being read. D[4:0]/0x40394 SMPK0[4:0]: FPK0[4:0] Input Mask Bits Sets conditions for generating FPK0 key-input interrupts (interrupt enabled/disabled). 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) SMPK0x is an input mask bit for each FPK0 key-input interrupt port. Interrupts for bits set to 1 are enabled, and interrupts for bits set to 0 are disabled. A change in the state of an input pin that is disabled from interrupt does not affect interrupt generation. D[3:0]/0x40395 SMPK1[3:0]: FPK1[3:0] Input Mask Bits Sets conditions for generating FPK1 key-input interrupts (interrupt enabled/disabled). 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) SMPK1x is an input mask bit for each FPK1 key-input interrupt port. Interrupts for bits set to 1 are enabled, and interrupts for bits set to 0 are disabled. A change in the state of an input pin that is disabled from interrupt does not affect interrupt generation. IV PORT S1C33401 TECHNICAL MANUAL EPSON IV-10-21 IV C33 ADV BASIC PERIPHERAL BLOCK: GENERAL-PURPOSE I/O PORTS (PORT) IV.10.7 Precautions * After an initial reset, the cause-of-interrupt flags become indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset the flags in a program. * To prevent regeneration of interrupts due to the same cause of interrupt following the occurrence of an interrupt, always be sure to reset the cause-of-interrupt flag before resetting the PSR or executing the reti instruction. * When using an port input interrupt as the trigger to restart from the HALT2 or SLEEP mode, an interrupt will occur due to the input signal level even if edge interrupt is specified as an interrupt condition. The signal level to restart the CPU is as follows according to the signal edge selected: If a rising-edge interrupt is set, the CPU restarts when the input signal goes to a high level. If a falling-edge interrupt is set, the CPU restarts when the input signal goes to a low level. When a falling edge interrupt is selected to restart after the slp instruction is executed, the operation is as follows. If the interrupt port is already at a low level when the slp instruction is executed, the CPU enters SLEEP mode instantaneously and restarts immediately afterward. If the interrupt port is at a high level when the slp instruction is executed, the SLEEP mode continues until the port goes low. Therefore, design the system assuming that the CPU can restart normally due to the signal level at the interrupt port, not an edge interrupt, when restarting the CPU from HALT2 or SLEEP mode using a port input interrupt. * To use the P65, P66, and P67 pins that are configured as the debug interface pins by default for general-purpose inputs/outputs, clear DPCTOE (D0/0x402EC) to 0. DPCTOE: PC Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D0/0x402EC) Note, however, that the PC trace function of the debugger cannot be used when DPCTOE (D0/0x402EC) is set to 0. * Even if the port input interrupt condition is set to falling edge, the input pulse width must be longer than 1 cycle of the peripheral circuit operating clock (PCLK) to be certain an interrupt will be generated. IV-10-22 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11 A/D Converter (ADC) I IV.11.1 Features and Structure of A/D Converter The C33 ADV Basic Peripheral Block contains an A/D converter with the following features: * Conversion method: Successive comparison * Resolution: 10 bits * Input channels: Maximum of 8 * A/D converter input clock: Maximum of 2 MHz, minimum of 16 kHz * Conversion time: Minimum of 10 s (when a 2-MHz input clock is selected) Maximum of 1250 s (when a 16-kHz input clock is selected) * Conversion range: Between VSS and AVDD * Two conversion modes can be selected: Normal mode: Conversion is completed in one operation. Continuous mode: Conversion is continuous and terminated through software control. Continuous conversion of multiple channels can be performed in each mode. * Four types of A/D-conversion start triggers can be selected: Triggered by the external pin (#ADTRG) Triggered by the compare match B of the 16-bit timer 0 Triggered by the underflow of the 8-bit timer 0 Triggered by the software * A/D conversion results can be read out from the 10-bit data register or the conversion result buffer* for each channel. * An interrupt is generated upon completion of A/D conversion or when the conversion result is out of the specified range (upper and lower-limit values can be specified)*. These functions can be used in the advanced mode. The A/D converter of the C33 ADV has two operating modes, standard mode of which functions are compatible with the C33 STD analog block for the existing models and an advanced mode allowing use of the extended functions. IV Figure IV.11.1.1 shows the structure of the A/D converter. Control registers AVDD AIN3 AIN4 AIN5 Data register Analog input decoder Analog block Successive approximation block Ch0-Ch7 conversion result buffers Control circuit AIN6 AIN7 Comparator (See Note below.) Out of range #ADTRG 8-bit timer 0 16-bit timer 0 Conversion completed Upper-limit/ lower-limit value registers Internal data bus AIN0 AIN1 AIN2 ADC V Interrupt control circuit A/D converter input clock CMU Prescaler Interrupt request Can be used in advanced mode Figure IV.11.1.1 Structure of A/D Converter Note: The A/D converter supports a maximum of eight input channels (AIN0-AIN7). Note, however, that the number of analog input channels available depends on the C33 ADV model to be used. S1C33401 TECHNICAL MANUAL EPSON IV-11-1 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.2 I/O Pins of A/D Converter Table IV.11.2.1 shows the pins used by the A/D converter. Table IV.11.2.1 I/O Pins of A/D Converter Pin name #ADTRG AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AVDD I/O I I I I I I I I I - Function A/D trigger A/D converter input 0 A/D converter input 1 A/D converter input 2 A/D converter input 3 A/D converter input 4 A/D converter input 5 A/D converter input 6 A/D converter input 7 Analog power supply voltage (+) AVDD (analog power-supply pin) AVDD is the power-supply pin for the analog circuit. Note: When the A/D converter is set to enabled state, a current flows between AVDD and VSS, and power is consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it must be set to the disabled state (default 0 setting of ADE (D2/0x48144)). ADE: A/D Enable Bit in the A/D Control/Status Register (D2/0x48144) AIN[7:0] (analog-signal input pins) The analog input pins AIN7 (Ch.7) through AIN0 (Ch.0) are shared with I/O ports. Therefore, when these pins are used for analog input, they must be set for use with the A/D converter in the software. This setting can be made individually for each pin. At cold start, all these pins are set for I/O ports. The analog input voltage AVIN can be input in the range of VSS AVIN AVDD. #ADTRG (external-trigger input pin) This pin is used to input a trigger signal to start A/D conversion from an external source. Since this pin is shared with I/O port, it must be set for use with the A/D converter in the software before an external trigger can be applied to the pin. At cold start, this pin is set for I/O port. Notes: * The list above indicates the input pins that the A/D converter can accommodate. Depending on the C33 ADV model used, all input pins (all channels) may not be available. * The A/D input pins are shared with general-purpose I/O ports or other peripheral circuit inputs/ outputs, so that functionality in the initial state may be set to other than the A/D input. Before the A/D converter can be used, the function of these pins must be switched for the analog input by setting the corresponding Port Function Select Registers. For details of pin functions and how to switch over, see Section I.3.3, "Switching Over the Multiplexed Pin Functions." IV-11-2 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.3 A/D Converter Operating Clock and Conversion Clock I The A/D converter use the peripheral circuit clock (PCLK) generated by the CMU as the operating clock. Furthermore, it uses the conversion clock supplied from the prescaler. Controlling the supply of the operating clock PCLK is supplied to the A/D converter with default settings. It can be turned off using ADCCLK (D6/0x40180) to reduce the amount of power consumed on the chip if the A/D converter is not used. ADCCLK: A/D Converter Clock Control Bit in the Peripheral Clock Control Register 1 (D6/0x40180) Setting ADCCLK (D6/0x40180) to 0 (1 by default) turns off the PCLK clock supply to the A/D converter. When the clock supply is turned off, the A/D converter control registers cannot be accessed. For details on how to set and control PCLK, refer to Section II.3, "Clock Management Unit (CMU)." Controlling the supply of the conversion clock The conversion clock is supplied from the prescaler separately with the operating clock described above. Set the conversion clock for the A/D converter in the prescaler. For details on how to set and control the conversion clock, refer to Section IV.4, "Prescaler (PSC)." Clock state in standby mode The clock supply to the A/D converter stops depending on type of standby mode. HALT mode: The operating and conversion clocks are supplied the same way as in normal mode. HALT2 mode: The operating and conversion clocks are supplied the same way as in normal mode. SLEEP mode: The operating and conversion clock supply stops. Therefore, the A/D converter also stops operating when in SLEEP modes. IV ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-3 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.4 Setting A/D Converter When the A/D converter is used, the following settings must be made before an A/D conversion can be performed: 1. Setting analog input pins ... See Section IV.11.2. 2. Setting the operating mode (standard mode/advanced mode) 3. Setting the input clock 4. Selecting the analog-conversion start and end channels 5. Setting the A/D conversion mode 6. Selecting a trigger 7. Setting the sampling time 8. Setting the upper-limit and lower-limit values (advanced mode) 9. Setting the interrupt mode (advanced mode) 10. Setting interrupt/IDMA/HSDMA ... See Section IV.11.6. Note: Before making these settings, make sure the A/D converter is disabled (ADE (D2/0x48144) = 0). Changing the settings while the A/D converter is enabled could cause a malfunction. ADE: A/D Enable Bit in the A/D Control/Status Register (D2/0x48144) Setting the operating mode (standard mode / advanced mode) The A/D converter of the C33 ADV has two operating modes, standard mode of which functions are compatible with the C33 STD analog block for the existing models and an advanced mode allowing use of the extended functions. Table IV.11.4.1 shows differences between the standard mode and the advanced mode. Table IV.11.4.1 Differences Between Standard Mode and Advanced Mode Function Standard mode Advanced mode The conversion results are read from the A/D conversion result register common to all channels. When converting for multiple channels, the A/D conversion result register must be read before conversion for the next channel has completed. The conversion results can be read from the conversion result buffer provided for each channel. Thus the conversion result for the current channel will not be lost even when the conversion for the next channel is completed during a multiple channel conversion. Different flags are provided for each Conversion-complete flag, One bit is assigned for the flag and is commonly used in all channels. channel. overwrite error flag Not supported. An upper-limit value and a lower-limit value Comparison with can be set and conversion results of the upper/lower-limit values specified channel can be checked whether they are within the specified range or not. Conversion-complete interrupt only can be Conversion-complete interrupts and out-ofInterrupts generated. range interrupts can be generated. The interrupts cannot be masked in channel Conversion complete interrupts for the units. specified channels can be masked. Reading conversion results To configure the A/D converter in the advanced mode, set ADCADV (D8/0x4815E) to 1. The control bits for the extended functions can be accessed after this setting. At initial reset, ADCADV is set to 0 and the A/D converter enters the standard mode. ADCADV: Standard/Advanced Mode Select Bit in the A/D Converter Mode Select/Internal Status Register (D8/0x4815E) The following descriptions unless otherwise specified are common contents for both modes. The extended functions in the advanced mode are explained assuming that ADCADV (D8/0x4815E) has been set to 1. IV-11-4 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) Setting the input clock I As explained in Section IV.4, "Prescaler (PSC)," the A/D conversion clock can be selected from among the eight types shown in Table IV.11.4.2 below. Use PSAD[2:0] (D[2:0]/0x4014F) for this selection. PSAD[2:0]: A/D Converter Clock Division Ratio Setup Bits in the A/D Clock Control Register (D[2:0]/0x4014F) Table IV.11.4.2 Input Clock Selection PSAD2 1 1 1 1 0 0 0 0 PSAD1 PSAD0 Division ratio 1 1 fPCLK/256 1 0 fPCLK/128 0 1 fPCLK/64 0 0 fPCLK/32 1 1 fPCLK/16 1 0 fPCLK/8 0 1 fPCLK/4 0 0 fPCLK/2 fPCLK: Peripheral circuit clock (PCLK) frequency The selected clock is output from the prescaler to the A/D converter by writing 1 to PSONAD (D3/0x4014F). PSONAD: A/D Converter Clock Control Bit in the A/D Clock Control Register (D3/0x4014F) Notes: * The A/D converter operates only when the prescaler is operating. * The recommended input clock frequency is a maximum of 2 MHz and a minimum of 16 kHz. * Do not start an A/D conversion when the clock output from the prescaler to the A/D converter is turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway. This could cause the A/D converter to operate erratically. Selecting analog-conversion start and end channels Select the channel in which the A/D conversion is to be performed from among the pins (channels) that have been set for analog input. To enable A/D conversions in multiple channels to be performed successively through one convert operation, specify the conversion start and conversion end channels using CS[2:0] (D[10:8]/0x48142) and CE[2:0] (D[13:11]/0x48142) respectively. IV CS[2:0]: A/D Converter Start Channel Setup Bits in the A/D Trigger/Channel Select Register (D[10:8]/0x48142) CE[2:0]: A/D Converter End Channel Setup Bits in the A/D Trigger/Channel Select Register (D[13:11]/0x48142) Table IV.11.4.3 Relationship between CS/CE and Input Channel CS2/CE2 CS1/CE1 CS0/CE0 Channel selected 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 ADC Example: Operation of one A/D conversion CS[2:0] = 0, CE[2:0] = 0: Converted only in AIN0 CS[2:0] = 0, CE[2:0] = 3: Converted in the following order: AIN0AIN1AIN2AIN3 CS[2:0] = 5, CE[2:0] = 1: Converted in the following order: AIN5AIN6AIN7AIN0AIN1 V Note: Only conversion-channel input pins that have been set for use with the A/D converter can be set using CS[2:0] (D[10:8]/0x48142) and CE[2:0] (D[13:11]/0x48142). S1C33401 TECHNICAL MANUAL EPSON IV-11-5 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) Setting the A/D conversion mode The A/D converter can operate in one of the following two modes. This operation mode is selected using MS (D5/0x48142). MS: A/D Conversion Mode Select Bit in the A/D Trigger/Channel Select Register (D5/0x48142) 1. Normal mode (MS = 0) All inputs in the range of channels set using CS[2:0] (D[10:8]/0x48142) and CE[2:0] (D[13:11]/0x48142) are A/D converted once and then stopped. 2. Continuous mode (MS = 1) A/D conversions in the range of channels set using CS[2:0] and CE[2:0] are executed successively until stopped by the software. At initial reset, the normal mode is selected. Selecting a trigger Use TS[1:0] (D[4:3]/0x48142) to select a trigger to start A/D conversion from among the four types shown in Table IV.11.4.4. TS[1:0]: A/D Conversion Trigger Select Bits in the A/D Trigger/Channel Select Register (D[4:3]/0x48142) Table IV.11.4.4 Trigger Selection TS1 TS0 1 1 0 0 1 0 1 0 Trigger External trigger (#ADTRG) 8-bit timer 0 16-bit timer 0 Software 1. External trigger The signal input to the #ADTRG pin is used as a trigger. When this trigger is used, the #ADTRG pin must be set in advance using the port function select register. A/D conversion is started when a low level of the #ADTRG signal is detected. 2. 8-bit or 16-bit timer The underflow signal of 8-bit timer 0 or the comparison match B signal of the 16-bit timer 0 is used as a trigger. Since the cycle can be programmed using each timer, this trigger is effective when cyclic A/D conversions are required. For details on how to set a timer, refer to the explanation of each timer in this manual. 3. Software trigger Writing 1 to ADST (D1/0x48144) in the software serves as a trigger to start A/D conversion. ADST: A/D Conversion Control/Status Bit in the A/D Control/Status Register (D1/0x48144) Setting the sampling time The A/D converter contains ST[1:0] (D[9:8]/0x48144) that allows the analog-signal input sampling time to be set in four steps (3, 5, 7, or 9 times the conversion clock period). However, this register should be used as set by default (ST[1:0] = 11; x9 clock periods). ST[1:0]: Input Signal Sampling Time Setup Bits in the A/D Control/Status Register (D[9:8]/0x48144) IV-11-6 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) Setting the upper-limit and lower-limit values (advanced mode) I The advanced mode allows a range check of the conversion results by setting the upper-limit and lower-limit values. Setup the A/D converter according to the procedure shown below to use this function. 1. Selecting the channel Select the channel to compare the A/D conversion results and the upper-limit and lower-limit value using ADCMP[2:0] (D[14:12]/0x48144). ADCMP[2:0]: A/D Upper/Lower-limit Comparison Channel Select Bits in the A/D Control/Status Register (D[14:12]/0x48144) Table IV.11.4.5 Selecting the Channel for Checking Conversion Results ADCMP2 ADCMP1 ADCMP0 Channel selected 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 2. Setting upper-limit and lower-limit values Set the upper-limit value to ADUPR[9:0] (D[9:0]/0x48158) and the lower-limit value to ADLWR[9:0] (D[9:0]/0x4815A). ADUPR[9:0]: A/D Upper Limit Value Setup Bits in the A/D Upper Limit Value Register (D[9:0]/0x48158) ADLWR[9:0]: A/D Lower Limit Value Setup Bits in the A/D Lower Limit Value Register (D[9:0]/0x4815A) When the conversion result exceeds the upper-limit value set or is lower than the lower-limit value, it is determined as out of range. If the conversion result is the same value as the upper-limit or lower-limit value, it is determined as within the range. 3. Enabling comparison with the upper-limit and lower-limit values Set ADCMPE (D15/0x48144) to 1 to enable the range check function. IV ADCMPE: A/D Upper/Lower-limit Comparison Enable Bit in the A/D Control/Status Register (D15/0x48144) Setting the interrupt mode (advanced mode) The interrupt functions are extended in the advanced mode, so the following configuration is necessary. 1. Enabling/disabling the conversion-complete interrupt The conversion-complete interrupt can be enabled/disabled using CNVINTEN (D4/0x48144). Set CNVINTEN to 1 when using the conversion-complete interrupt, or to 0 when it is not used. At initial reset, CNVINTEN is set to 1, so the conversion-complete interrupt function is enabled. CNVINTEN: A/D Conversion-Complete Interrupt Enable Bit in the A/D Control/Status Register (D4/0x48144) 2. Enabling/disabling the out-of-range interrupt The out-of-range interrupt can be enabled/disabled using CMPINTEN (D5/0x48144). Set CMPINTEN to 1 when using the out-of range interrupt, or to 0 when it is not used. At initial reset, CMPINTEN is set to 0, so the out-of-range interrupt function is disabled. CMPINTEN: A/D Out-of-Range Interrupt Enable Bit in the A/D Control/Status Register (D5/0x48144) 3. Setting the interrupt signal mode The A/D converter uses one signal line for interrupt requests to the interrupt controller (ITC). In the initial setting, only the conversion-complete interrupt signal is output to the ITC. When using the out-of-range interrupt, the out-of-range interrupt signal is ORed with the above signal to send to the ITC. This signal mode can be selected by setting INTMODE (D6/0x48144) to 1. INTMODE: Interrupt Signal Mode Select Bit in the A/D Control/Status Register (D6/0x48144) S1C33401 TECHNICAL MANUAL EPSON IV-11-7 ADC V IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 4. Masking conversion-complete interrupt for the specified channels The A/D conversion-complete interrupt mask register is used to mask the conversion-complete interrupts of the specified channels. When INTMASKx (Dx/0x4815C) for channel `x' in the register is set to 0, channel `x' does not generate conversion-complete interrupts. For instance, by masking the conversion-complete interrupt of the channel used for range checking, it is possible to generate out-of range interrupts only. INTMASKx: Ch.x Conversion-Complete Interrupt Mask Bit in the A/D Conversion Complete Interrupt Mask Register (Dx/0x4815C) At initial reset, INTMASKx are all set to 1 to enable conversion-complete interrupts. IV-11-8 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.5 Control and Operation of A/D Conversion I Figure IV.11.5.1 shows the operation of the A/D converter. ADE Trigger ADST A/D operation (When AIN0 to AIN2 are converted) Sampling Conversion Sampling Conversion Sampling Conversion AIN0 AIN0 AIN1 AIN1 AIN2 AIN2 AIN0 converted data ADD AIN1 converted data AIN2 converted data ADD is overwritten ADF Conversion-result (ADD) read OWE AIN0 converted data AD0BUF* ADF0* OWE0* AIN1 converted data AD1BUF* ADF1* OWE1* AIN2 converted data AD2BUF* ADF2* OWE2* Interrupt request IV (1) Normal mode ADE Trigger ADST A/D operation ADD (When AIN0 to AIN1 are converted) Reset in software Sampling Conversion Sampling Conversion Sampling Conversion AIN0-1 AIN0-1 AIN1-1 AIN1-1 AIN0-2 AIN0-2 Sampling Conversion AIN1-2 invalid AIN0-1 converted data AIN1-1 converted data AIN0-2 converted data ADF Conversion-result (ADD) read OWE AD0BUF* AIN0-1 converted data AIN0-2 converted data AD0BUF is overwritten ADF0* OWE0* AIN1-1 converted data AD1BUF* ADF1* OWE1* Interrupt request (2) Continuous mode S1C33401 TECHNICAL MANUAL Extended functions that can be used when ADCADV = 1 Figure IV.11.5.1 Operation of A/D Converter IV-11-9 EPSON ADC V IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) Starting up the A/D converter circuit After the settings specified in the preceding section have been made, write 1 to ADE (D2/0x48144) to enable the A/D converter. The A/D converter is thereby readied to accept a trigger to start A/D conversion. To set the A/D converter again, or if it is not be used, set ADE to 0. ADE: A/D Enable Bit in the A/D Control/Status Register (D2/0x48144) Starting A/D conversion When a trigger is input while ADE (D2/0x48144) = 1, A/D conversion is started. If a software trigger has been selected, A/D conversion is started by writing 1 to ADST (D1/0x48144). ADST: A/D Conversion Control/Status Bit in the A/D Control/Status Register (D1/0x48144) Only the trigger selected using TS[1:0] (D[4:3]/0x48142) are valid; no other trigger is accepted. TS[1:0]: A/D Conversion Trigger Select Bits in the A/D Trigger/Channel Select Register (D[4:3]/0x48142) When a trigger is input, the A/D converter samples and A/D-converts the analog input signal, beginning with the conversion start channel selected by CS[2:0] (D[10:8]/0x48142). CS[2:0]: A/D Converter Start Channel Setup Bits in the A/D Trigger/Channel Select Register (D[10:8]/0x48142) ADST (D1/0x48144) used for the software trigger is set to 1 during A/D conversion, even when it is started by some other trigger, so it can be used as an A/D-conversion status bit. The channel in which conversion is underway can be identified by reading CH[2:0] (D[2:0]/0x48142). CH[2:0]: A/D Conversion Channel Status Bits in the A/D Trigger/Channel Select Register (D[2:0]/0x48142) Reading out A/D conversion results * Standard mode Upon completion of the A/D conversion in the start channel, the A/D converter stores the conversion result, in 10-bit data registers ADD[9:0] (D[9:0]/0x48140), and sets the conversion-complete flag ADF (D3/0x48144) and cause-of-interrupt flag FADE (D1/0x40287). If multiple channels are specified using CS[2:0] (D[10:8]/ 0x48142) and CE[2:0] (D[13:11]/0x48142), A/D conversions in the subsequent channels are performed in succession. ADD[9:0]: A/D Converted Data Bits in the A/D Conversion Result Register (D[9:0]/0x48140) ADF: A/D Conversion Completion Flag in the A/D Control/Status Register (D3/0x48144) FADE: A/D Conversion Completion Interrupt Cause Flag in the Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (D1/0x40287) CE[2:0]: A/D Converter End Channel Setup Bits in the A/D Trigger/Channel Select Register (D[13:11]/0x48142) The results of A/D conversion are stored in ADD[9:0] (D[9:0]/0x48140) each time conversion in one channel is completed. Since an interrupt can be generated simultaneously, this interrupt is normally used to read out the converted data. In addition, be sure to reset the cause-of-interrupt flag (by writing 0) to prepare the A/D converter for the next operation. Since the cause of interrupt of the A/D converter can also be used to invoke DMA, the conversion results can automatically be transferred to a specified memory location. If multiple A/D conversion channels are specified, the conversion results in one channel must be read out prior to completion of conversion in the next channel. If the A/D conversion currently under way is completed before the previous conversion results are read out, ADD[9:0] is overwritten with the new conversion results. If ADD[9:0] is updated when the conversion-complete flag ADF (D3/0x48144) = 1 (before the converted data is read out), the overwrite-error flag OWE (D0/0x48144) is set to 1. The conversion-complete flag ADF is reset to 0 when the converted data is read out. If ADD[9:0] is updated when ADF = 0, OWE remains at 0, indicating that the operation has been completed normally. When reading out data, also read OWE to make sure the data is valid. Once OWE is set, it remains set until it is reset to 0 in the software. Note also that if OWE is set, ADF also is set. In this case, read out the converted data and reset ADF. OWE: Overwrite Error Flag in the A/D Control/Status Register (D0/0x48144) IV-11-10 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) * Advanced mode Upon completion of the A/D conversion in the start channel (Ch.x), the A/D converter stores the conversion result to the 10-bit Ch.x conversion result buffer ADxBUF[9:0] (D[9:0]/0x48148 + 2*x) and sets the Ch.x conversion-complete flag ADFx (Dx/0x48146) and the cause-of-interrupt flag FADE (D1/0x40287). If multiple channels are specified using CS[2:0] (D[10:8]/0x48142) and CE[2:0] (D[13:11]/0x48142), A/D conversions in the subsequent channels are performed in succession. I ADxBUF[9:0]: A/D Ch.x Converted Data Bits in the A/D Ch.x Conversion Result Buffer Register (D[9:0]/ 0x48148 + 2*x) ADFx: A/D Ch.x Conversion-Complete Flag in the A/D Channel Status Flag Register (Dx/0x48146) The results of A/D conversion are stored in the A/D conversion result buffer for each channel each time conversion in one channel is completed. Since an interrupt can be generated simultaneously, this interrupt is normally used to read out the converted data. In addition, be sure to reset the cause-of-interrupt flag (by writing 0) to prepare the A/D converter for the next operation. Since the cause of interrupt of the A/D converter can also be used to invoke DMA, the conversion results can automatically be transferred to a specified memory location. In the advanced mode, each channel has a conversion result buffer, so it is not necessary to read the conversion results prior to completion of conversion in the next channel. However, if the next A/D conversion in the same channel is completed before the previous conversion results are read out, the conversion result buffer is overwritten with the new conversion results. If ADxBUF[9:0] (D[9:0]/0x48148 + 2*x) is updated when the conversion-complete flag ADFx = 1 (before the converted data is read out), the overwrite-error flag OWEx (Dx + 8/0x48146) is set to 1. ADFx (Dx/0x48146) is reset to 0 when the converted data is read out. If ADxBUF[9:0] is updated when ADFx = 0, OWEx remains at 0, indicating that the operation has been completed normally. When reading out data, also read OWEx to make sure the data is valid. Once OWEx is set, it remains set until it is reset to 0 by writing 0 in the software. Note also that if OWEx is set, ADFx is also set. In this case, read out the converted data and reset ADFx. OWEx: A/D Ch.x Overwrite Error Flag in the A/D Channel Status Flag Register (Dx + 8/0x48146) ADD[9:0] (D[9:0]/0x48140), ADF (D3/0x48144) and OWE (D0/0x48144) used in the standard mode are also effective in the advanced mode as well. The functions and actions of the register/bits are the same as those of the standard mode. OWE is set during conversion in multiple-channels, but it is not necessary to reset it. IV Range check (comparison with upper-limit/lower-limit values in advanced mode) When the range check function is enabled (ADCMPE (D15/0x48144) = 1) and an A/D conversion in the channel specified using ADCMP[2:0] (D[14:12]/0x48144) has completed, the conversion results are compared with the contents of ADUPR[9:0] (D[9:0]/0x48158) and ADLWR[9:0] (D[9:0]/0x4815A). ADCMPE: A/D Upper/Lower-limit Comparison Enable Bit in the A/D Control/Status Register (D15/0x48144) ADCMP[2:0]: A/D Upper/Lower-limit Comparison Channel Select Bits in the A/D Control/Status Register (D[14:12]/0x48144) ADUPR[9:0]: A/D Upper Limit Value Setup Bits in the A/D Upper Limit Value Register (D[9:0]/0x48158) ADLWR[9:0]: A/D Lower Limit Value Setup Bits in the A/D Lower Limit Value Register (D[9:0]/0x4815A) If the conversion results exceed the upper-limit value, the upper-limit comparison status bit ADUPRST (D11/ 0x48144) is set to 1. If the results are less than the lower-limit value, the lower-limit comparison status bit ADLWRST (D10/0x48144) is set to 1. When the out-of range interrupt is enabled, an interrupt occurs if one of the status bits has been set. This interrupt request sets the same cause-of-interrupt flag FADE (D1/0x40287) as the conversion-complete interrupt to 1. Therefore, the above status bits must be read out to check whether the out-of-range interrupt is generated or not if the conversion-complete interrupt is also enabled. ADUPRST: A/D Upper-limit Comparison Status Bit in the A/D Control/Status Register (D11/0x48144) ADLWRST: A/D Lower-limit Comparison Status Bit in the A/D Control/Status Register (D10/0x48144) When the conversion results are the same as the upper-limit or lower-limit values, it is assumed within the range and an interrupt is not generated. S1C33401 TECHNICAL MANUAL EPSON IV-11-11 ADC V IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) Terminating A/D conversion * For normal mode (MS = 1) In the normal mode, A/D conversion is performed successively from the conversion start channel specified using CS[2:0] (D[10:8]/0x48142) to the conversion end channel specified using CE[2:0] (D[13:11]/0x48142), and is completed after these conversions are executed in one operation. ADST (D1/0x48144) is reset to 0 upon completion of the conversion. MS: A/D Conversion Mode Select Bit in the A/D Trigger/Channel Select Register (D5/0x48142) * For continuous mode (MS = 0) In the continuous mode, A/D conversion from the conversion-start to the conversion-end channels is executed repeatedly, without being stopped in the hardware. To terminate conversion, therefore, ADST (D1/0x48144) must be reset to 0 in the software. However, the A/D conversion being executed will be completed normally or forcibly stopped depending on the timing of writing 0 to ADST. When the A/D conversion has completed normally, ADF (D3/0x48144) is set to 1 and the conversion results can be obtained. If it is forcibly stopped, ADF maintains its previous status, therefore, conversion results cannot be obtained. * Forced termination A/D conversion is immediately terminated by writing 0 to ADST (D1/0x48144). The results of the conversion then under-way cannot be obtained. IV-11-12 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.6 A/D Converter Interrupt and DMA I Upon completion of A/D conversion in each channel, the A/D converter generates an interrupt and invokes the IDMA if necessary. In the advanced mode, the A/D converter can generate an interrupt when the conversion results are out of the range specified with the upper-limit and lower-limit registers. Control registers of the interrupt controller The following shows the interrupt control bits available for the A/D converter: FADE: A/D Conversion Completion Interrupt Cause Flag in the Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (D1/0x40287) EADE: A/D Conversion Completion Interrupt Enable Bit in the Port Input 4-7, RTC, A/D Interrupt Enable Register (D1/0x40277) PAD[2:0]: A/D Interrupt Level Bits in the Serial I/F Ch.1, A/D Interrupt Priority Register (D[6:4]/0x4026A) The A/D converter sets the cause-of-interrupt flag to 1 when A/D conversion in one channel is completed, and the conversion results are stored in ADD[9:0] and ADxBUF[9:0] (advanced mode). ADxBUF[9:0]: A/D Ch.x Converted Data Bits in the A/D Ch.x Conversion Result Buffer Register (D[9:0]/ 0x48148 + 2*x) ADD[9:0]: A/D Converted Data Bits in the A/D Conversion Result Register (D[9:0]/0x48140) If the out-of-range interrupt is enabled in the advanced mode, the cause-of-interrupt flag is set to 1 when the conversion results in the specified channel are out of range. Both the conversion-complete and out-orange interrupts use the same cause-of-interrupt flag. At this time, if the interrupt enable register bit has been set to 1, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit set to 0. The cause-of-interrupt flag is set to 1 upon completion of A/D conversion in each channel, regardless of the setting of the interrupt enable register (even when it is set to 0). The interrupt priority register sets the priority level (0 to 7) of an interrupt. An interrupt request to the CPU is accepted no other interrupt request of a higher priority has been generated. In addition, it is only when the PSR's IE bit = 1 (interrupts enabled) and the set value of the IL is smaller than the A/ D-converter interrupt level set by the interrupt priority register, that the A/D converter's interrupt request is actually accepted by the CPU. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, refer to Section IV.2, "Interrupt Controller (ITC)." IV Intelligent DMA The A/D converter can invoke the intelligent DMA (IDMA) through the use of its cause of interrupt. This allows the conversion results to be transferred to a specified memory location with no need to execute an interrupt processing routine. The IDMA channel number assigned to the A/D converter is 0x1B. Before IDMA can be invoked, the IDMA request bit RADE (D2/0x40293) and the IDMA enable bit DEADE (D2/0x40297) must be set to 1. Transfer conditions on the IDMA side must also be set in advance. RADE: A/D Conversion Completion IDMA Request Bit in the Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Request Register (D2/0x40293) DEADE: A/D Conversion Completion IDMA Enable Bit in the Serial I/F Ch.1, A/D, Port Input 4-7 IDMA Enable Register (D2/0x40297) If a cause of interrupt occurs when the IDMA request and IDMA enable bits are set to 1, IDMA is invoked. No interrupt request is generated at that point. An interrupt request is generated upon completion of the DMA transfer. Otherwise, the bit can be set so as not to generate an interrupt, with only a DMA transfer performed. For details on DMA transfers and how to control interrupts upon completion of a DMA transfer, refer to Section III.5, "Intelligent DMA (IDMA)." S1C33401 TECHNICAL MANUAL EPSON IV-11-13 ADC V IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) High-speed DMA The cause of A/D interrupt can also invoke high-speed DMA (HSDMA). The following shows the HSDMA channel number and trigger set-up bit: Table IV.11.6.1 HSDMA Trigger Set-up Bits HSDMA channel Trigger set-up bits 0 1 2 3 HSD0S[3:0] (D[3:0]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD1S[3:0] (D[7:4]) / HSDMA Ch.0-1 trigger set-up register (0x40298) HSD2S[3:0] (D[3:0]) / HSDMA Ch.2-3 trigger set-up register (0x40299) HSD3S[3:0] (D[7:4]) / HSDMA Ch.2-3 trigger set-up register (0x40299) For HSDMA to be invoked, the trigger set-up bits should be set to 0b1100 in advance. Transfer conditions, etc. must also be set on the HSDMA side. If the A/D cause of interrupt is selected as the HSDMA trigger, the HSDMA channel is invoked through generation of the cause of interrupt. For details on HSDMA transfer, refer to Section III.4, "High-Speed DMA (HSDMA)." Trap vector The A/D converter's interrupt trap-vector default address is set to 0x20000100. The base address of the trap table can be changed using the TTBR register. IV-11-14 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.7 Details of Control Registers I Table IV.11.7.1 List of A/D Converter Registers Address 0x00048140 0x00048142 0x00048144 0x00048146 0x00048148 0x0004814A 0x0004814C 0x0004814E 0x00048150 0x00048152 0x00048154 0x00048156 0x00048158 0x0004815A 0x0004815C 0x0004815E Size Register name Function 16 A/D conversion data A/D Conversion Result Register (pAD_ADD) A/D Trigger/Channel Select Register (pAD_TRIG_CHNL) 16 Sets start/end channels and conversion mode. 16 Controls A/D converter and indicates conversion status. A/D Control/Status Register (pAD_EN_SMPL_STAT) 16 Overwrite error and conversion complete status A/D Channel Status Flag Register (pAD_END) 16 A/D Ch.0 conversion data A/D Ch.0 Conversion Result Buffer Register (pAD_CH0_BUF) 16 A/D Ch.1 conversion data A/D Ch.1 Conversion Result Buffer Register (pAD_CH1_BUF) 16 A/D Ch.2 conversion data A/D Ch.2 Conversion Result Buffer Register (pAD_CH2_BUF) 16 A/D Ch.3 conversion data A/D Ch.3 Conversion Result Buffer Register (pAD_CH3_BUF) 16 A/D Ch.4 conversion data A/D Ch.4 Conversion Result Buffer Register (pAD_CH4_BUF) 16 A/D Ch.5 conversion data A/D Ch.5 Conversion Result Buffer Register (pAD_CH5_BUF) 16 A/D Ch.6 conversion data A/D Ch.6 Conversion Result Buffer Register (pAD_CH6_BUF) 16 A/D Ch.7 conversion data A/D Ch.7 Conversion Result Buffer Register (pAD_CH7_BUF) 16 Specifies A/D conversion upper limit value. A/D Upper Limit Value Register (pAD_UPPER) 16 Specifies A/D conversion lower limit value. A/D Lower Limit Value Register (pAD_LOWER) 16 Masks A/D conversion complete interrupt. A/D Conversion Complete Interrupt Mask Register (pAD_CH07_INTMASK) 16 Selects A/D operating mode and indicates internal A/D Converter Mode Select/Internal Status Register (pAD_ADVMODE) status and internal counter value. The following describes each A/D converter control register. The A/D converter control registers are mapped in the 16-bit device area from 0x48140 to 0x4815E, and can be accessed in units of half-words and bytes. IV Note: When setting the A/D converter control registers, be sure to write a 0, and not a 1, for all "reserved bits." ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-15 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48140: A/D Conversion Result Register (pAD_ADD) Register name Address Bit Name A/D conversion 0048140 D15-10 - D9 ADD9 (HW) result register D8 ADD8 (pAD_ADD) D7 ADD7 D6 ADD6 D5 ADD5 D4 ADD4 D3 ADD3 D2 ADD2 D1 ADD1 D0 ADD0 Function reserved A/D converted data ADD9 = MSB ADD0 = LSB Setting - 0x0 to 0x3FF Init. R/W - 0 0 0 0 0 0 0 0 0 0 - R Remarks 0 when being read. D[15:10] Reserved D[9:0] IV-11-16 ADD[9:0]: A/D Converted Data Bits Stores the results of A/D conversion. (Default: 0x000) The LSB is stored in ADD0, and the MSB is stored in ADD9. This is a read-only register, so writing to this register is ignored. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48142: A/D Trigger/Channel Select Register (pAD_TRIG_CHNL) Register name Address Name Bit 0048142 D15-14 - A/D trigger/ D13 CE2 (HW) channel select D12 CE1 register D11 CE0 (pAD_TRIG_CHNL) D10 CS2 D9 CS1 D8 CS0 D7-6 - D5 MS D4 TS1 D3 TS0 D2 D1 D0 CH2 CH1 CH0 Function Setting reserved A/D converter end channel selection - 0 to 7 (depends on the model.) A/D converter start channel selection 0 to 7 (depends on the model.) reserved A/D conversion mode selection A/D conversion trigger selection A/D conversion channel status - 1 Continuous 0 Normal TS[1:0] Trigger 11 #ADTRG pin 10 8-bit timer 01 16-bit timer 00 Software 0 to 7 (depends on the model.) Init. R/W - 0 0 0 0 0 0 - 0 0 0 0 0 0 I Remarks - 0 when being read. R/W R/W - 0 when being read. R/W R/W R D[15:14] Reserved D[13:11] CE[2:0]: A/D Converter End Channel Setup Bits Sets the conversion end channel by selecting a channel number from 0 to 7. (Default: 0b000 = AIN0) Analog inputs can be A/D-converted successively from the channel set using CS[2:0] (D[10:8]) to the channel set using these bits in one operation. If only one channel is to be A/D converted, set the same channel number in both CS[2:0] and CE[2:0]. D[10:8] CS[2:0]: A/D Converter Start Channel Setup Bits Sets the conversion start channel by selecting a channel number from 0 to 7. (Default: 0b000 = AIN0) Analog inputs can be A/D-converted successively from the channel set using these bits to the channel set using CE[2:0] (D[13:11]) in one operation. If only one channel is to be A/D converted, set the same channel number in both CS[2:0] and CE[2:0]. D[7:6] Reserved D5 MS: A/D Conversion Mode Select Bit Selects an A/D conversion mode. 1 (R/W): Continuous mode 0 (R/W): Normal mode (default) IV The A/D converter is set for the continuous mode by writing 1 to MS. In this mode, A/D conversions in the range of the channels selected using CS[2:0] (D[10:8]) and CE[2:0] (D[13:11]) are executed continuously until stopped in the software. When MS = 0, the A/D converter operates in the normal mode. In this mode, A/D conversion is completed after all inputs in the range of the channels selected by CS[2:0] and CE[2:0] are converted in one operation. ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-17 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) D[4:3] TS[1:0]: A/D Conversion Trigger Select Bits Selects a trigger to start A/D conversion. Table IV.11.7.2 Trigger Selection TS1 TS0 Trigger 1 1 0 0 1 0 1 0 External trigger (#ADTRG) 8-bit timer 0 16-bit timer 0 Software (Default: 0b00 = Software trigger) When an external trigger is used, the #ADTRG pin must be set in advance using the port function select register. A/D conversion is started when a low level of the #ADTRG signal is detected. When a timer is used, since its underflow signal (8-bit timer) or comparison match B signal (16-bit timer) serves as a trigger, set the cycle and other parameters for the timer. D[2:0] IV-11-18 CH[2:0]: A/D Conversion Channel Status Bits Indicates the channel number (0 to 7) currently being A/D-converted. (Default: 0b000 = AIN0) When A/D conversion is performed in multiple channels, read this bit to identify the channel in which conversion is underway. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48144: A/D Control/Status Register (pAD_EN_SMPL_STAT) Register name Address Bit Name 0048144 (HW) D15 D14 D13 D12 D11 D10 D9 D8 ADCMPE ADCMP2 ADCMP1 ADCMP0 ADUPRST ADLWRST ST1 ST0 Upper/lower-limit comparison enable 1 Enabled 0 Disabled Upper/lower-limit comparison 0 to 7 channel selection (depends on the model.) D7 D6 D5 D4 D3 D2 D1 D0 - INTMODE CMPINTEN CNVINTEN ADF ADE ADST OWE reserved Interrupt signal mode Out-of-range int. enable Conversion-complete int. enable Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag A/D control/ status register (pAD_EN_SMPL _STAT) D15 Function Upper-limit comparison status Lower-limit comparison status Input signal sampling time setup Setting 1 Out of range 0 Within range 1 Out of range 0 Within range ST[1:0] Sampling time 11 9 clocks 10 7 clocks 01 5 clocks 00 3 clocks - 1 Complete only 0 OR 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 Completed 0 Run/Standby 0 Disabled 1 Enabled 1 Start/Run 0 Stop 1 Error 0 Normal Init. R/W I Remarks 0 0 0 0 0 0 1 1 R/W Can be used when R/W ADCADV = "1". - 0 0 1 0 0 0 0 - R/W R/W R/W R R/W R/W R/W R R R/W Use with 9 clocks. 0 when being read. Can be used when ADCADV = "1". Reset when ADD is read. Reset by writing 0. ADCMPE: A/D Upper/Lower-limit Comparison Enable Bit (for advanced mode) Enables/disables comparison between converted data and upper-/lower-limit values. 1 (R/W): Enabled 0 (R/W): Disabled (default) ADCMPE selects whether the converted data is compared with the upper-/lower-limit values after A/D conversion of the channel specified using ADCMP[2:0] (D[14:12]). Set ADCMPE to 1 when using the comparison function or set to 0 when not used. D[14:12] ADCMP[2:0]: A/D Upper/Lower-limit Comparison Channel Select Bits (for advanced mode) Set the channel number (0-7) to compare its converted data with the upper-/ lower-limit values. (Default: 0b000 = AIN0) D11 IV ADUPRST: A/D Upper-limit Comparison Status Bit (for advanced mode) Indicates the results of comparison between the A/D converted data and the upper-limit value. 1 (R): Exceeded the upper limit 0 (R): Within the range (default) When the upper-/lower-limit comparison function is enabled (ADCMPE (D15) = 1), the converted data is compared with the upper-/lower-limit values after A/D conversion of the channel specified using ADCMP[2:0] (D[14:12]) has completed. If the converted data exceeds the upper-limit value set in ADUPR[9:0] (D[9:0]/0x48158), ADUPRST is set to 1. If the converted data is equal to or less than the upper-limit value, ADUPRST is set to 0. An interrupt occurs when ADUPRST is set to 1 if the out-ofrange interrupt is enabled. D10 ADLWRST: A/D Lower-limit Comparison Status Bit (for advanced mode) Indicates the results of comparison between the A/D converted data and the lower-limit value. 1 (R): Under the lower limit 0 (R): Within the range (default) ADC V When the upper-/lower-limit comparison function is enabled (ADCMPE (D15) = 1), the converted data is compared with the upper-/lower-limit values after A/D conversion of the channel specified using ADCMP[2:0] (D[14:12]) has completed. If the converted data is less than the lower-limit value set in ADLWR[9:0] (D[9:0]/0x4815A), ADLWRST is set to 1. If the converted data is equal to or more than the lower-limit value, ADLWRST is set to 0. An interrupt occurs when ADLWRST is set to 1 if the out-of-range interrupt is enabled. S1C33401 TECHNICAL MANUAL EPSON IV-11-19 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) D[9:8] ST[1:0]: Input Signal Sampling Time Setup Bits Sets the analog input sampling time. Table IV.11.7.3 Sampling Time ST1 ST0 1 1 0 0 1 0 1 0 Sampling time 9-clock period 7-clock period 5-clock period 3-clock period (Default: 0b11 = 9-clock period) The A/D converter conversion clock is used for counting. To maintain the conversion accuracy, use ST as set by default (9-clock period). D7 Reserved D6 INTMODE: Interrupt Signal Mode Select Bit (for advanced mode) Configures the interrupt signal delivered to the ITC. 1 (R/W): Conversion-complete signal only 0 (R/W): OR between conversion-complete and out-of-range signals (default) INTMODE selects whether the interrupt signal line connected to the ITC is used to send the conversioncomplete signal only or used to send the signal of which the conversion-complete and out-of-range signal are ORed. Set INTMODE to 1 if the out-of-range interrupt is not used. When using the out-of-range interrupt, set INTMODE to 0 and CMPINTEN (D5) to 1. D5 CMPINTEN: A/D Out-of-Range Interrupt Enable Bit (for advanced mode) Enables/disables the out-of-range interrupt. 1 (R/W): Enabled 0 (R/W): Disabled (default) When CMPINTEN is set to 1, upper and lower-limit comparison results become a cause of interrupt. When it is set to 0, an out-of-range interrupt is not generated. D4 CNVINTEN: A/D Conversion-Complete Interrupt Enable Bit (for advanced mode) Enables/disables the conversion-complete interrupt. 1 (R/W): Enabled (default) 0 (R/W): Disabled When CNVINTEN is set to 1, completion of an A/D conversion becomes a cause of interrupt. When it is set to 0, a conversion-complete interrupt is not generated. D3 ADF: A/D Conversion Completion Flag Indicates that A/D conversion has been completed. 1 (R): Conversion completed 0 (R): Being converted or standing by (default) This flag is set to 1 when A/D conversion is completed, and the converted data is stored in the data register and is reset to 0 when the converted data is read out. When A/D conversion is performed in multiple channels, if the next A/D conversion is completed while ADF = 1 (before the converted data is read out), the data register is overwritten with the new conversion results, causing an overrun error to occur. Therefore, ADF must be reset by reading out the converted data before the next A/D conversion is completed. IV-11-20 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) D2 ADE: A/D Enable Bit Enables the A/D converter (readied for conversion). 1 (R/W): Enabled 0 (R/W): Disabled (default) I When ADE is set to 1, the A/D converter is enabled, meaning it is ready to start A/D conversion (i.e., ready to accept a trigger). When ADE = 0, the A/D converter is disabled, meaning it is unable to accept a trigger. Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to reset ADE to 0. This helps to prevent the A/D converter from operating erratically. D1 ADST: A/D Conversion Control/Status Bit Controls A/D conversion. 1 (R/W): Software trigger 0 (R/W): A/D conversion is stopped (default) If A/D conversion is to be started by a software trigger, set ADST to 1. If any other trigger is used, ADST is automatically set to 1 by the hardware. ADST remains set while A/D conversion is underway. In normal mode, upon completion of A/D conversion in selected channels, ADST is reset to 0 and the A/D conversion circuit is turned off. To stop A/D conversion during operation in continuous mode, reset ADST by writing 0. When ADE (D2) = 0 (A/D conversion disabled), ADST is fixed to 0, with no trigger accepted. D0 OWE: Overwrite Error Flag Indicates that the converted data has been overwritten. 1 (R): Overwritten 0 (R): Normal (default) 1 (W): Has no effect 0 (W): Flag is reset During A/D conversion in multiple channels, if the conversion results for the next channel are written to the converted-data register (overwritten) before the converted data is read out to reset the conversioncomplete flag ADF (D3) that has been set through conversion of the preceding channel, OWE is set to 1. When ADF (D3) is reset, because this means that the converted data has been read out, OWE is not set. Once OWE is set to 1, it remains set until it is reset by writing 0 in the software. IV ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-21 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48146: A/D Channel Status Flag Register (pAD_END) Register name Address Bit 0048146 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D channel status flag register (pAD_END) Name OWE7 OWE6 OWE5 OWE4 OWE3 OWE2 OWE1 OWE0 ADF7 ADF6 ADF5 ADF4 ADF3 ADF2 ADF1 ADF0 Function Ch.7 overwrite error flag Ch.6 overwrite error flag Ch.5 overwrite error flag Ch.4 overwrite error flag Ch.3 overwrite error flag Ch.2 overwrite error flag Ch.1 overwrite error flag Ch.0 overwrite error flag Ch.7 conversion-complete flag Ch.6 conversion-complete flag Ch.5 conversion-complete flag Ch.4 conversion-complete flag Ch.3 conversion-complete flag Ch.2 conversion-complete flag Ch.1 conversion-complete flag Ch.0 conversion-complete flag Setting 1 Error 1 Completed Init. R/W 0 Normal 0 Run/Standby 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Remarks Can be used when ADCADV = "1". Reset by writing 0. Can be used when ADCADV = "1". Reset when ADBUFx is read. Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 7. D[15:8] OWE[7:0]: A/D Ch.x Overwrite Error Flags (for advanced mode) These bits indicate that the conversion result buffer for each channel has been overwritten. 1 (R): Overwritten 0 (R): Normal (default) 1 (W): Has no effect 0 (W): Flag is reset During A/D conversion in continuous mode, if the new conversion results in the same channel are written to the conversion result buffer (overwritten) before the converted data is read out to reset the ADFx conversion-complete flag that has been set through the previous conversion, OWEx is set to 1. When ADFx is reset, because this means that the converted data has been read out, OWEx is not set. Once OWEx is set to 1, it remains set until it is reset by writing 0 in the software. D[7:0] ADF[7:0]: A/D Ch.x Conversion-Complete Flags (for advanced mode) These bits indicate that A/D conversion in each channel has been completed. 1 (R): Conversion completed 0 (R): Being converted or standing by (default) This flag is set to 1 when A/D conversion of the corresponding channel is completed, and the converted data is stored in the conversion result buffer and is reset to 0 when the conversion result buffer is read out. When A/D conversion is performed in continuous mode, if the next A/D conversion of the same channel is completed while ADFx = 1 (before the conversion result buffer is read out), the buffer is overwritten with the new conversion results, causing an overrun error to occur. Therefore, ADFx must be reset by reading out the converted data before the next A/D conversion is completed. IV-11-22 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48148-0x48156: A/D Ch.x Conversion Result Buffer Registers (pAD_CHx_BUF) Register name Address A/D Ch.x conversion result buffer register (pAD_CHx_BUF) Bit Name 0048148 D15-10 - D9 ADxBUF9 | D8 ADxBUF8 0048156 D7 ADxBUF7 (HW) D6 ADxBUF6 D5 ADxBUF5 D4 ADxBUF4 D3 ADxBUF3 D2 ADxBUF2 D1 ADxBUF1 D0 ADxBUF0 Function reserved A/D Ch.x converted data ADxBUF9 = MSB ADxBUF0 = LSB Setting - 0x0 to 0x3FF Init. R/W - 0 0 0 0 0 0 0 0 0 0 - R I Remarks 0 when being read. Can be used when ADCADV = "1". Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 7. 0x48148 0x4814A 0x4814C 0x4814E 0x48150 0x48152 0x48154 0x48156 A/D Ch.0 Conversion Result Buffer Register (pAD_CH0_BUF) A/D Ch.1 Conversion Result Buffer Register (pAD_CH1_BUF) A/D Ch.2 Conversion Result Buffer Register (pAD_CH2_BUF) A/D Ch.3 Conversion Result Buffer Register (pAD_CH3_BUF) A/D Ch.4 Conversion Result Buffer Register (pAD_CH4_BUF) A/D Ch.5 Conversion Result Buffer Register (pAD_CH5_BUF) A/D Ch.6 Conversion Result Buffer Register (pAD_CH6_BUF) A/D Ch.7 Conversion Result Buffer Register (pAD_CH7_BUF) D[15:10] Reserved D[9:0] ADxBUF[9:0]: A/D Ch.x Converted Data Bits (for advanced mode) The conversion results in each channel are stored. (Default: 0x000) This is a read-only register, so writing to this register is ignored. IV ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-23 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x48158: A/D Upper Limit Value Register (pAD_UPPER) Register name Address Bit Name A/D upper limit 0048158 D15-10 - D9 ADUPR9 (HW) value register D8 ADUPR8 (pAD_UPPER) D7 ADUPR7 D6 ADUPR6 D5 ADUPR5 D4 ADUPR4 D3 ADUPR3 D2 ADUPR2 D1 ADUPR1 D0 ADUPR0 Function Setting reserved A/D conversion upper limit value ADUPR9 = MSB ADUPR0 = LSB - 0x0 to 0x3FF Init. R/W - 0 0 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W Can be used when ADCADV = "1". D[15:10] Reserved D[9:0] IV-11-24 ADUPR[9:0]: A/D Upper Limit Value Setup Bits (for advanced mode) Set the upper-limit value to be compared with the A/D conversion results. (Default: 0x000) The value set in this register is used for the range check of the A/D conversion results in the channel specified with ADCMP[2:0] (D[14:12]/0x48144). If the converted data exceeds the set value, an interrupt can be generated. EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x4815A: A/D Lower Limit Value Register (pAD_LOWER) Register name Address Bit Name A/D lower limit 004815A D15-10 - D9 ADLWR9 (HW) value register D8 ADLWR8 (pAD_LOWER) D7 ADLWR7 D6 ADLWR6 D5 ADLWR5 D4 ADLWR4 D3 ADLWR3 D2 ADLWR2 D1 ADLWR1 D0 ADLWR0 Function reserved A/D conversion lower limit value ADLWR9 = MSB ADLWR0 = LSB Setting - 0x0 to 0x3FF I Init. R/W - 0 0 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W Can be used when ADCADV = "1". D[15:10] Reserved D[9:0] ADLWR[9:0]: A/D Lower Limit Value Setup Bits (for advanced mode) Set the lower-limit value to be compared with the A/D conversion results. (Default: 0x000) The value set in this register is used for the range check of the A/D conversion results in the channel specified with ADCMP[2:0] (D[14:12]/0x48144). If the converted data is less than the set value, an interrupt can be generated. IV ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-25 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x4815C: A/D Conversion Complete Interrupt Mask Register (pAD_CH07_INTMASK) Register name Address Bit Name Function reserved A/D conversion 004815C D15-8 - D7 INTMASK7 Ch.7 conversion-complete int. mask 1 Interrupt (HW) complete D6 INTMASK6 Ch.6 conversion-complete int. mask interrupt mask enabled D5 INTMASK5 Ch.5 conversion-complete int. mask register D4 INTMASK4 Ch.4 conversion-complete int. mask (pAD_CH07 D3 INTMASK3 Ch.3 conversion-complete int. mask _INTMASK) D2 INTMASK2 Ch.2 conversion-complete int. mask D1 INTMASK1 Ch.1 conversion-complete int. mask D0 INTMASK0 Ch.0 conversion-complete int. mask Setting - 0 Interrupt mask Init. R/W - 1 1 1 1 1 1 1 1 Remarks - 0 when being read. R/W Can be used when R/W ADCADV = "1". R/W R/W R/W R/W R/W R/W Note: The letter `x' in bit names, etc., denotes a channel number from 0 to 7. D[15:8] Reserved D[7:0] INTMASK[7:0]: Ch.x Conversion-Complete Interrupt Mask Bits (for advanced mode) These bits mask the A/D conversion-complete interrupt for each channel individually. 1 (R/W): Interrupt is enabled (default) 0 (R/W): Interrupt is masked When INTMASKx is set to 0, the conversion-completed interrupt request of the Ch.x is masked and the cause-of-interrupt flag FADE (D1/0x40287) will not be set to 1 even if A/D conversion is completed. When INTMASKx is 1, the A/D converter can generate an interrupt upon completion of A/D conversion in Ch.x. FADE: A/D Conversion Completion Interrupt Cause Flag in the Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (D1/0x40287) IV-11-26 EPSON S1C33401 TECHNICAL MANUAL IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) 0x4815E: A/D Converter Mode Select/Internal Status Register (pAD_ADVMODE) Register name Address Name Bit Function Setting A/D converter 004815E D15-9 - D8 ADCADV (HW) mode select/ D7-6 - internal status D5 ISTATE1 register D4 ISTATE0 (pAD_ADVMODE) D3 D2 D1 D0 reserved - Standard/advanced mode selection 1 Advanced 0 Standard reserved - Internal status Status ISTATE[1:0] Converting 11 reserved 10 Sampling 01 Idle 00 ICOUNTER3 Internal counter value 0 to 15 ICOUNTER2 ICOUNTER1 ICOUNTER0 D[15:9] Reserved D8 ADCADV: Standard/Advanced Mode Select Bit Selects the A/D converter operating mode. 1 (R/W): Advanced mode 0 (R/W): Standard mode (default) Init. R/W - 0 - 0 0 0 0 0 0 I Remarks - Do not write 1. R/W - 0 when being read. R R When ADCADV is set to 1, the A/D converter is set in the advanced mode, and the registers/bits for the extended function can be used. When ADCADV is set to 0, only the standard C33 A/D converter functions implemented in C33 STD models can be used. In this mode, the extended registers/bits for advanced mode become read only and writing operation is disabled. D[7:6] Reserved D[5:4] ISTATE[1:0]: Internal Status Bits Indicates the A/D converter internal status. IV Table IV.11.7.4 Internal Status D[3:0] ISTATE1 ISTATE0 1 1 0 0 1 0 1 0 Status Converting reserved Sampling Idle (Default: 0b00 = Idle) ICOUNTER[3:0]: Internal Counter Value Setup Bits Indicates the internal counter value. (Default: 0b0000) ADC V S1C33401 TECHNICAL MANUAL EPSON IV-11-27 IV C33 ADV BASIC PERIPHERAL BLOCK: A/D CONVERTER (ADC) IV.11.8 Precautions * Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable ADE (D2/ 0x48144). A change in settings while the A/D converter is enabled could cause it to operate erratically. ADE: A/D Enable Bit in the A/D Control/Status Register (D2/0x48144) * The A/D converter operates only when the prescaler is operating. In consideration of the conversion accuracy, we recommend that the A/D conversion clock be min. 16 kHz to max. 2 MHz. * Do not start an A/D conversion when the clock supplied from the prescaler to the A/D converter is turned off, and do not turn off the prescaler's clock output when an A/D conversion is underway, as doing so could cause the A/D converter to operate erratically. * After an initial reset, FADE (D1/0x40287) becomes indeterminate. To prevent generation of an unwanted interrupt or IDMA request, be sure to reset this flag and register in a program. FADE: A/D Conversion Completion Interrupt Cause Flag in the Port Input 4-7, RTC, A/D Interrupt Cause Flag Register (D1/0x40287) * To prevent the regeneration of interrupts due to the same cause of interrupt following the occurrence an interrupt, always be sure to reset the cause-of-interrupt flag before setting the PSR again or executing the reti instruction. * When the A/D converter is set to enabled state, a current flows between AVDD and VSS, and power is consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it must be set to the disabled state (default 0 setting of ADE (D2/0x48144)). * When the 8-bit timer 0 underflow signal or the 16-bit timer 0 compare match B signal is used as a trigger factor, the division ratio of the prescaler used by the relevant timer must not be set to PCLK/1. * When using an external trigger to start A/D conversion, the low period of the trigger signal to be applied to the #ADTRG pin must be two or more CPU operating clock cycles. Furthermore, return the #ADTRG input level to high within 20 cycles of the A/D input clock set. Otherwise, it will be detected as the trigger for the next A/D conversion. * Depending on the model, software controllable pull-up resistors may be provided for the input ports. In this case, disable the pull-up resistors of the ports used for analog inputs. * When in break mode during ICD-based debugging, the operating clock for the A/D converter is turned off due to the internal chip design. Therefore, the A/D converter stops operating and registers cannot be accessed for write (but can be accessed for read). IV-11-28 EPSON S1C33401 TECHNICAL MANUAL S1C33401 Technical Manual V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK V V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PREFACE V.1 Preface I The basic configuration of the C33 ADV Core Macro-based S1C33 microcomputers includes the core block, bus block, and basic peripheral block described in Chapters II to IV. The inherent functions and extended peripheral circuit, etc. of the S1C33401 are located in Area 6 for access via the BBCU. Modules in Area 6 are connected to 32-bit internal data buses, and can be accessed in units of words. The modules mapped to Area 6 of the S1C33401 are shown below. C33 ADV CPU HBCU High-speed bus BBCU Chip ID registers Pin control registers Macro control register Real-time clock (RTC) Area 6 Extension Peripheral Block Figure V.1.1 Configuration of S1C33401 Area 6 Chip ID register Enables the ID indicating the type of IC and C33 ADV model to be read out. Pin control register Enables control to pull the bus signal and other input/output pins high or forcibly drive both low. Macro control register Used to set up an interface between the BBCU and Area 6, and set general parameters of the Area 6 extended peripheral circuit. Real-time clock (RTC) This real-time clock includes a 32-kHz OSC1 oscillator circuit. Because the RTC is supplied with power independently of other modules, it is possible to run the RTC only, with all other functions turned off. V Preface S1C33401 TECHNICAL MANUAL EPSON V-1-1 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PREFACE THIS PAGE IS BLANK. V-1-2 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: AREA 6 SETTINGS AND MACRO CONTROL REGISTER V.2 Area 6 Settings and Macro Control Register I The Area 6 modules are accessed via the BBCU. It is necessary to set up the CE6 area by using the BBCU registers. Moreover, since control bits associated with all modules in Area 6 are provided in the macro control register, these control bits must also be set up. The following describes how to set up Area 6. V.2.1 Setting Up the CE6 Area with BBCU Registers Table V.2.1.1 lists the BBCU parameters that must be set up before modules in Area 6 can be used. Table V.2.1.1 BBCU Setup Items Setup item WAIT enable External/internal access Endian mode Interface mode Device type Device size Bus clock synchronization WR start state option (-0.5 clock) WR end state option (-0.5 clock) RD start state option (-0.5 clock) Output-disable cycle Access cycle multiplying factor Access disable cycle WR start state WR end state RD start state RD end state CE cycle Content Enable insertion of external WAIT Access internal device Little endian A0 mode BBCU device (SRAM) 32 bits Asynchronous Disable Disable Disable 0 clocks x1 0 clocks 1 clock 1 clock 1 clock 1 clock 4 clocks Control bit settings WAITEN (D0/0x48384) = 1 CE6IO (D13/0x48390) = 1 CE6BIG (D12/0x48390) = 0 (default) CE6BSL (D11/0x48390) = 0 (default) CE6EBCU (D10/0x48390) = 0 (default) CE6DVSZ[1:0] (D[9:8]/0x48390) = 11 CE6BCKSYN (D5/0x48390) = 0 CE6WSTHCK (D4/0x48390) = 0 (default) CE6WEDHCK (D3/0x48390) = 0 (default) CE6RSTHCK (D2/0x48390) = 0 (default) CE6ODISC[1:0] (D[1:0]/0x48390) = 00 CE6MLT[1:0] (D[15:14]/0x48392) = 00 CE6ADISC[1:0] (D[13:12]/0x48392) = 00 CE6WRSTAC[1:0] (D[11:10]/0x48392) = 00 CE6WRENDC[1:0] (D[9:8]/0x48392) = 01 CE6RDSTAC[1:0] (D[7:6]/0x48392) = 00 CE6RDENDC[1:0] (D[5:4]/0x48392) = 01 CE6CE[3:0] (D[3:0]/0x48392) = 0011 Before accessing the control registers mapped to Area 6, set the items listed in the table above to the specified contents. For details of BBCU control, see Section III.2, "Basic Bus Control Unit (BBCU)." V Area 6 S1C33401 TECHNICAL MANUAL EPSON V-2-1 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: AREA 6 SETTINGS AND MACRO CONTROL REGISTER V.2.2 Clock Control The modules (control registers) in Area 6 are clocked by the core system clock (CCLK) supplied from the CMU. When initially reset, CCLK supply is enabled. When not using the peripheral functions (except the RTC) in Area 6, the clock supply from the CMU can be turned off to reduce the amount of current consumed on the chip. This control is exercised using CE6CLKEN (D4) in the Macro Control Register (0x300F20). CE6CLKEN: Area 6 Peripheral Clock-Enable Bit in the Macro Control Register (D4/0x300F20) Setting CE6CLKEN (D4/0x300F20) to 0 disables clock supply from the CMU to Area 6. Although the RTC can operate as a time clock using only the OSC1 clock and output interrupt requests, the control registers of the RTC cannot be accessed from the CPU when the clock supply above is turned off. For details on how CCLK is generated and controlled, see Section II.3, "Clock Management Unit (CMU)." V-2-2 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: AREA 6 SETTINGS AND MACRO CONTROL REGISTER V.2.3 Setting Wait Cycles for Accessing the RTC I The Macro Control Register (0x300F20) contains the control bits RTCW[2:0] (D[2:0]) used to set the number of wait cycles to be inserted when accessing the RTC. RTCW[2:0]: RTC Wait Control Bits in the Macro Control Register (D[2:0]/0x300F20) Table V.2.3.1 Number of Wait Cycles during RTC Access RTCW2 RTCW1 RTCW0 Number of wait cycles (in units of CCLK clocks) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock 0 clocks The number of wait cycles to be set depends on the S1C33 model. The S1C33401 is able to operate with 0 clocks (no wait state). When initially reset, the wait cycle is set to 7 clocks. Before this wait cycle can be inserted as shown in Table V.2.1.1, #WAIT control must be enabled with the BBCU register (WAITEN (D0/0x48384) = 1). WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384) V Area 6 S1C33401 TECHNICAL MANUAL EPSON V-2-3 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: AREA 6 SETTINGS AND MACRO CONTROL REGISTER V.2.4 Control Register Details The following describes the contents of the macro control register. The macro control register is allocated to address 0x300F20 as a 32-bit device, and can be accessed in units of words, half-words, or bytes. 0x300F20: Macro Control Register (pMISC3) Register name Address Macro control register (pMISC3) Bit Name 0300F20 D31-5 - D4 CE6CLKEN (W) D3 - D2 RTCW2 D1 RTCW1 D0 RTCW0 Function Setting reserved Area 6 peripheral clock enable reserved RTC wait control Init. R/W - 1 - 1 1 1 - 1 Enabled 0 Disabled - 0 to 7 (cycles) D[31:5] Reserved D4 CE6CLKEN: Area 6 Peripheral Clock-Enable Bit This bit controls clock supply to the modules (control registers) in Area 6. 1 (R/W): Enable (default) 0 (R/W): Disable Remarks - 0 when being read. R/W - 0 when being read. R/W Before the registers mapped to Area 6 can be accessed, this bit must be set to 1, so that CCLK is supplied from the CMU to Area 6. When not using the functional modules in Area 6, set this bit to 0 to disable clock supply. This helps to reduce the amount of current consumed on the chip. Even when this bit is set to 0, the time-keeping function of the RTC continues operating normally. D3 Reserved D[2:0] RTCW[2:0]: RTC Wait Control Bits These bits set the number of wait cycles to be inserted when accessing the RTC control register. Table V.2.4.1 Number of Wait Cycles during RTC Access RTCW2 RTCW1 RTCW0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Number of wait cycles (in units of CCLK clocks) 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock 0 clocks (Default: 0b111 = 7 clocks) Before this wait cycle can be inserted, #WAIT control must be enabled with the BBCU register (WAITEN (D0/0x48384) = 1). WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384) Use the S1C33401 with these bits set to 0 (0 clocks). V-2-4 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: CHIP ID V.3 Chip ID I V.3.1 Chip ID Bits The S1C33401 has a device ID register shown below that allow the application software to identify CPU type, model, and chip version. Core ID Bits (D[7:0]/0x300000) These bits provide an 8-bit ID code that indicates the chip core type. ID 0x02 0x03 0x04 0x05 Chip Core Type C33 standard macro core (C33 STD core CPU) C33 mini-macro core C33 advanced macro core (C33 ADV core CPU) C33 PE The S1C33401 has adopted the C33 advanced macro core, so the chip core ID is 0x04. Product series ID Bits (D[15:8]/0x300000) These bits provide an 8-bit ID code that indicates the product series of the S1C33 Family. ID 0x03 0x04 0x15 Product Series S1C333xx Series S1C334xx Series S1C33Lxx Series The product series ID of the S1C33401 is 0x04. Model ID Bits (D[23:16]/0x300000) These bits provide an 8-bit ID code that indicates the model. The model ID of the S1C33401 is 0x01. Version Bits (D[31:28]/0x300000) These bits provide a 4-bit ID code that indicates the version number. 0x00 represents version 1.0. V ChipID S1C33401 TECHNICAL MANUAL EPSON V-3-1 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: CHIP ID V.3.2 Details of Control Register The device ID register is a 32-bit register mapped to Area 6 at address 0x300000, and can be accessed in units of words, half-words, or bytes. Note: To access the device ID register, the CE6 area must be set up in the BBCU. For setting details, see Section V.2, "Area 6 Settings and Macro Control Register." 0x300000: Device ID Register (pMISC0) Register name Address Device ID register (pMISC0) 0300000 (W) Bit D31 D30 D29 D28 D27-24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name VER3 VER2 VER1 VER0 - NAME7 NAME6 NAME5 NAME4 NAME3 NAME2 NAME1 NAME0 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 Function Setting Version code 0x00: version 1.0 0x00 reserved Model ID 0x01: S1C33401 - 0x01 Product series ID 0x03: S1C333xx 0x04: S1C334xx 0x15: S1C33Lxx 0x04 Chip core ID 0x02: C33 STD 0x03: C33 mini 0x04: C33 ADV 0x05: C33 PE 0x04 Init. R/W 0 0 0 0 - 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Remarks R - R 0 when being read. R R Note: These bits are read-only, so writing to them is ignored. D[31:28] VER[3:0]: Version Code These bits provide a version code. 0x00 represents version 1.0. D[27:24] Reserved D[23:16] NAME[7:0]: Model ID These bits provide a code (0x01 = S1C33401) to identify the model in the product series shown by MID[7:0]. D[15:8] MID[7:0]: Product Series ID These bits provide a code (0x04 = S1C334xx series) to identify the S1C33 Family product series. D[7:0] CID[7:0]: Chip Core ID These bits provide a code (0x04 = C33 advanced macro core) to identify the chip core type. V-3-2 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS V.4 Pin Control Registers I V.4.1 Pull-up Control The S1C33401 input/output pins have a pull-up resistor that can be connected/disconnected to/from the pin by software control, except some special pins. The pins are divided into groups and each group has a pull-up control bit to select whether the pull-up resistors of the pins that belong to the group are used or not. Table V.4.1.1 lists the correspondence between the register/control bits and pins. Table V.4.1.1 Correspondence between Pull-up Control Bits and Pins Control register Control bit Pin Bus Signal Low Drive/Pullup Control Register (0x300F00) Port Pull-up Control Register (0x300F04) PUPCE (D2) PUPAD (D1) PUPRW (D0) PUP9H (D19) PUP9L (D18) PUP8H (D17) PUP8L (D16) PUP7L (D14) PUP6H (D13) PUP6L (D12) PUP5H (D11) PUP5L (D10) PUP4H (D9) PUP4L (D8) PUP3L (D6) PUP2H (D5) PUP2L (D4) PUP1H (D3) PUP1L (D2) PUP0H (D1) PUP0L (D0) #CE10 A[17:0] #RD, #WRL, #WRH, #BSL P9[7:4] P9[3:0] P8[7:4] P8[3:0] P7[3:0] P6[7:4] P6[3:0] P5[6:4] P5[3:0] P4[7:4] P4[3:0] P3[3:0] P2[7:4] P2[3:0] P1[7:4] P1[3:0] P0[7:4] P0[3:0] At initial reset, the pull-up control bits are set to 1 and the pins are pulled up. When not using pull-up resistors, set the corresponding pull-up control bits to 0. Note: The pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the on-chip peripheral circuit or general-purpose I/O port. V.4.2 Driving Bus Signals Low The S1C33401 can drive the bus signal output pins forcibly low using a control register. This function is useful when turning off the power of the external device connected to the bus. Table V.4.2.1 lists the correspondence between the register/control bits and bus signals. Table V.4.2.1 Correspondence between Low-Drive Control Bits and Bus Signals Control register Control bit Bus signal Bus Signal Low Drive/Pullup Control Register (0x300F00) LDRVDB (D11) LDRVCE (D10) LDRVAD (D9) LDRVRW (D8) D[15:0] #CE[11:4] A[25:0] #RD, #WRL, #WRH, #BSL V When the control bit is set to 1, the corresponding bus signal goes low. When the control bit is set to 0, the signal control goes back to the BBCU/EBCU. Notes: * The low-drive control bit is disabled when the pin is used as the general-purpose I/O port (Pxx). * If the above signals are forcibly driven low when the CPU is running by the instructions fetched from an external memory, the CPU will not be able to run after that point. To drive the signals low, the CPU must be running with the program stored in the internal RAM. S1C33401 TECHNICAL MANUAL EPSON V-4-1 PinCtrl V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS V.4.3 Details of Control Registers Table V.4.3.1 List of Pin Status Control Registers Address 0x00300F00 Register name Bus Signal Low Drive/Pull-up Control Register (pMISC1) 0x00300F04 Port Pull-up Control Register (pMISC2) Size Function 32 Drives bus signal low and controls bus pull-up resistors. 32 Controls port pull-up resistors. The following describes the pin status control registers. The pin status control registers are mapped as 32-bit devices to Area 6 at addresses 0x300F00 to 0x300F04, and can be accessed in units of words, half-words, or bytes. Note: To access the pin status control registers, the CE6 area must be set up in the BBCU. For setting details, see Section V.2, "Area 6 Settings and Macro Control Register." V-4-2 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS 0x300F00: Bus Signal Low Drive/Pull-up Control Register (pMISC1) Register name Address Bit Name Bus signal low 0300F00 D31-12 - D11 LDRVDB (W) drive/pull-up D10 LDRVCE control register D9 LDRVAD (pMISC1) D8 LDRVRW D7-3 - D2 PUPCE D1 PUPAD D0 PUPRW Function Setting reserved - D15-D0 low drive 1 Low drive 0 Normal #CE11-#CE4 low drive output A25-A0 low drive #RD,#WRL,#WRH,#BSL low drive reserved #CE10 pull-up 1 Pulled up 0 No pull-up A17-A0 pull-up #RD,#WRL,#WRH,#BSL pull-up Init. R/W - 0 0 0 0 - 1 1 1 I Remarks - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W D[31:12] Reserved D11 LDRVDB: D15-D0 Low Drive Control Bit Drives the data bus signals forcibly low. 1 (R/W): Low drive 0 (R/W): Normal output (default) When LDRVDB is set to 1, the D15-D0 signals are forcibly driven low. When it is set to 0, the signals are controlled by the BBCU/EBCU normally. D10 LDRVCE: #CE11-#CE4 Low Drive Control Bit Drives the chip enable signals forcibly low. 1 (R/W): Low drive 0 (R/W): Normal output (default) When LDRVCE is set to 1, the #CE11-#CE4 signals are forcibly driven low. When it is set to 0, the signals are controlled by the BBCU/EBCU normally. D9 LDRVAD: A25-A0 Low Drive Control Bit Drives the address bus signals forcibly low. 1 (R/W): Low drive 0 (R/W): Normal output (default) When LDRVAD is set to 1, the A25-A0 signals are forcibly driven low. When it is set to 0, the signals are controlled by the BBCU/EBCU normally. D8 LDRVRW: #RD, #WRL, #WRH, #BSL Low Drive Control Bit Drives the bus control signals forcibly low. 1 (R/W): Low drive 0 (R/W): Normal output (default) When LDRVRW is set to 1, the #RD, #WRL, #WRH, and #BSL signals are forcibly driven low. When it is set to 0, the signals are controlled by the BBCU normally. D[7:3] Reserved D2 PUPCE: #CE10 Pull-up Control Bit Controls the pull-up resistor at the #CE10 pin. 1 (R/W): Pulled up (default) 0 (R/W): No pull-up V When PUPCE is set to 1, the #CE10 pin is pulled up to high. When it is set to 0, the pin is not pulled up. S1C33401 TECHNICAL MANUAL EPSON V-4-3 PinCtrl V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS D1 PUPAD: A17-A0 Pull-up Control Bit Controls the pull-up resistors at the address bus signal pins. 1 (R/W): Pulled up (default) 0 (R/W): No pull-up When PUPAD is set to 1, the A17-A0 pins are pulled up to high. When it is set to 0, the pins are not pulled up. D0 PUPRW: #RD, #WRL, #WRH, #BSL Pull-up Control Bit Controls the pull-up resistors at the bus control signal pins. 1 (R/W): Pulled up (default) 0 (R/W): No pull-up When PUPRW is set to 1, the #RD, #WRL, #WRH, and #BSL pins are pulled up to high. When it is set to 0, the pins are not pulled up. Notes: * When the pins (#CEx, A[25:18]) are used as the general-purpose I/O port (Pxx), the low-drive control is not effective. * If the bus signals are forcibly driven low when the CPU is running by the instructions fetched from an external memory, the CPU will not be able to run after that point. To drive the signals low, the CPU must be running with the program stored in the internal RAM. V-4-4 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS 0x300F04: Port Pull-up Control Register (pMISC2) Register name Address Bit Name 0300F04 D31-20 - Port pull-up D19 PUP9H (W) control register D18 PUP9L (pMISC2) D17 PUP8H D16 PUP8L D15 - D14 PUP7L D13 PUP6H D12 PUP6L D11 PUP5H D10 PUP5L D9 PUP4H D8 PUP4L D7 - D6 PUP3L D5 PUP2H D4 PUP2L D3 PUP1H D2 PUP1L D1 PUP0H D0 PUP0L Function reserved P97-P94 pull-up P93-P90 pull-up P87-P84 pull-up P83-P80 pull-up reserved P73-P70 pull-up P67-P64 pull-up P63-P60 pull-up P56-P54 pull-up P53-P50 pull-up P47-P44 pull-up P43-P40 pull-up reserved P33-P30 pull-up P27-P24 pull-up P23-P20 pull-up P17-P14 pull-up P13-P10 pull-up P07-P04 pull-up P03-P00 pull-up Setting - 1 Pulled up 0 No pull-up - 1 Pulled up 0 No pull-up - 1 Pulled up 0 No pull-up I Init. R/W - 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 Remarks - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W This register controls the pull-up resistors for the I/O port pins. 1 (R/W): Pulled up (default) 0 (R/W): No pull-up When the pull-up control bit is set to 1, the corresponding pins are pulled up to high. When it is set to 0, the pins are not pulled up. The pull-up control bit is effective in both cases when the pin is used for the external bus and when used for the onchip peripheral circuit or general-purpose I/O port. D[31:20] Reserved D19 PUP9H: P97-P94 Pull-up Control Bit Controls the pull-up resistors at the P97-P94 ports. D18 PUP9L: P93-P90 Pull-up Control Bit Controls the pull-up resistors at the P93-P90 ports. D17 PUP8H: P87-P84 Pull-up Control Bit Controls the pull-up resistors at the P87-P84 ports. D16 PUP8L: P83-P80 Pull-up Control Bit Controls the pull-up resistors at the P83-P80 ports. D15 Reserved D14 PUP7L: P73-P70 Pull-up Control Bit Controls the pull-up resistors at the P73-P70 ports. D13 PUP6H: P67-P64 Pull-up Control Bit Controls the pull-up resistors at the P67-P64 ports. D12 PUP6L: P63-P60 Pull-up Control Bit Controls the pull-up resistors at the P63-P60 ports. D11 PUP5H: P56-P54 Pull-up Control Bit Controls the pull-up resistors at the P56-P54 ports. D10 PUP5L: P53-P50 Pull-up Control Bit Controls the pull-up resistors at the P53-P50 ports. S1C33401 TECHNICAL MANUAL EPSON V PinCtrl V-4-5 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS D9 PUP4H: P47-P44 Pull-up Control Bit Controls the pull-up resistors at the P47-P44 ports. D8 PUP4L: P43-P40 Pull-up Control Bit Controls the pull-up resistors at the P43-P40 ports. D7 Reserved D6 PUP3L: P33-P30 Pull-up Control Bit Controls the pull-up resistors at the P33-P30 ports. D5 PUP2H: P27-P24 Pull-up Control Bit Controls the pull-up resistors at the P27-P24 ports. D4 PUP2L: P23-P20 Pull-up Control Bit Controls the pull-up resistors at the P23-P20 ports. D3 PUP1H: P17-P14 Pull-up Control Bit Controls the pull-up resistors at the P17-P14 ports. D2 PUP1L: P13-P10 Pull-up Control Bit Controls the pull-up resistors at the P13-P10 ports. D1 PUP0H: P07-P04 Pull-up Control Bit Controls the pull-up resistors at the P07-P04 ports. D0 PUP0L: P03-P00 Pull-up Control Bit Controls the pull-up resistors at the P03-P00 ports. V-4-6 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS V.4.4 Precautions I * The low-drive control bit is disabled when the pin is used as the general-purpose I/O port (Pxx). * If the bus signals are forcibly driven low when the CPU is running by the instructions fetched from an external memory, the CPU will not be able to run after that point. To drive the signals low, the CPU must be running with the program stored in the internal RAM. V PinCtrl S1C33401 TECHNICAL MANUAL EPSON V-4-7 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: PIN CONTROL REGISTERS THIS PAGE IS BLANK. V-4-8 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5 Real-Time Clock (RTC) I V.5.1 Overview of the RTC The IC described here incorporates a real-time clock (RTC) with a perpetual calendar, and an OSC1 oscillator circuit to generate the operating clock for the RTC. Since the RTC and OSC1 oscillator circuit operate with a power supply separate from that of the CPU and other modules, the system power supply can be turned off during RTC operation (standby mode). Moreover, the RTC can periodically generate interrupt requests to the CPU. The main features of the RTC are outlined below. * Contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the week, months, and year). * BCD data can be read from and written to both counters. * Capable of controlling the starting and stopping of time clocks. * 24-hour or 12-hour mode can be selected. * A 30-second correction function can be implemented in software. * Periodic interrupts are possible. * Interrupt period can be selected from 1/64 second, 1 second, 1 minute, or 1 hour, with selectable level/edge interrupts. * Independent power supply, so that the RTC can continue operating even when system power is turned off. (Standby mode) * A built-in OSC1 oscillator circuit (crystal oscillator or external clock input) that generates a 32.768-kHz (typ.) operating clock. Figure V.5.1.1 shows a block diagram of the RTC. CMU RTC OSC1 oscillator (32kHz) Interrupt control 1/64 second Controller Divider 1 minute 1 Hz 1-second counter 10-second counter 1 hour 1-minute counter 10-minute counter 1 second 24H/12H 1-hour counter 10-hour counter AM/PM Data bus OSC1 OSC2 Days of week counter V 1-day counter 10-day counter 1-month counter 10-month counter RTC 1-year counter 10-year counter #STBY Interrupt request to ITC (SLEEP release request to CMU) Figure V.5.1.1 RTC Block Diagram S1C33401 TECHNICAL MANUAL EPSON V-5-1 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.2 RTC Counters The RTC contains the following 13 counters, whose count values can be read out as BCD data from the respective registers. Each counter can also be set to any desired date and time by writing data to the respective register. 1-second counter This 4-bit BCD counter counts in units of seconds. It counts from 0 to 9 synchronously with a 1-second signal derived from the 32.768-kHz OSC1 clock by dividing the clock into smaller frequencies. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-second counter. The count data is read out and written using RTCSL[3:0] (D[3:0]/0x301010). RTCSL[3:0]: RTC 1-second Counter Bits in the RTC Second Register (D[3:0]/0x301010) 10-second counter This 3-bit BCD counter counts tens of seconds. It counts from 0 to 5 with 1 carried over from the 1-second counter. This counter is reset to 0 after 5 and outputs a carry over of 1 to the 1-minute counter. The count data is read out and written using RTCSH[2:0] (D[6:4]/0x301010). RTCSH[2:0]: RTC 10-second Counter Bits in the RTC Second Register (D[6:4]/0x301010) 1-minute counter This 4-bit BCD counter counts in units of minutes. It counts from 0 to 9 with 1 carried over from the 10-second counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-minute counter. The count data is read out and written using RTCMIL[3:0] (D[3:0]/0x301014). RTCMIL[3:0]: RTC 1-minute Counter Bits in the RTC Minute Register (D[3:0]/0x301014) 10-minute counter This 3-bit BCD counter counts tens of minutes. It counts from 0 to 5 with 1 carried over from the 1-minute counter. This counter is reset to 0 after 5 and outputs a carry over of 1 to the 1-hour counter. The count data is read out and written using RTCMIH[2:0] (D[6:4]/0x301014). RTCMIH[2:0]: RTC 10-minute Counter Bits in the RTC Minute Register (D[6:4]/0x301014) 1-hour counter This 4-bit BCD counter counts in units of hours. It counts from 0 to 9 with 1 carried over from the 10-minute counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-hour counter. Depending whether 12-hour or 24-hour mode is selected, the counter is reset at 12 o'clock or 24 o'clock. The count data is read out and written using RTCHL[3:0] (D[3:0]/0x301018). RTCHL[3:0]: RTC 1-hour Counter Bits in the RTC Hour Register (D[3:0]/0x301018) 10-hour counter This 2-bit BCD counter counts tens of hours. With a carry over of 1 from the 1-hour counter, this counter counts from 0 to 1 (when 12-hour mode is selected) or from 0 to 2 (when 24-hour mode is selected). The counter is reset at 12 o'clock or 24 o'clock, and outputs a carry over of 1 to the 1-day counter. The count data is read out and written using RTCHH[1:0] (D[5:4]/0x301018). RTCHH[1:0]: RTC 10-hour Counter Bits in the RTC Hour Register (D[5:4]/0x301018) When 12-hour mode is selected, RTCAP (D6/0x301018) that indicates A.M. or P.M. is enabled, with A.M. and P.M. represented by 0 and 1, respectively. For 24-hour mode, RTCAP (D6/0x301018) is fixed to 0. RTCAP: AM/PM Indicator Bit in the RTC Hour Register (D6/0x301018) V-5-2 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 1-day counter I This 4-bit BCD counter counts in units of days. It counts from 0 to 9 with 1 carried over from the hour counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-day counter. The number of days in each month and leap years are taken into account, so that the counter is reset to 1 when months change. The count data is read out and written using RTCDL[3:0] (D[3:0]/0x30101C). RTCDL[3:0]: RTC 1-day Counter Bits in the RTC Day Register (D[3:0]/0x30101C) 10-day counter This 2-bit BCD counter counts tens of days. It counts from 0 to 2 or 3 with 1 carried over from the 1-day counter. The number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1-day counter, and outputs a carry over of 1 to the 1-month counter. The count data is read out and written using RTCDH[1:0] (D[5:4]/0x30101C). RTCDH[1:0]: RTC 10-day Counter Bits in the RTC Day Register (D[5:4]/0x30101C) 1-month counter This 4-bit BCD counter counts in units of months. It counts from 0 to 9 with 1 carried over from the day counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-month counter. The counter is reset to 1 when years change. The count data is read out and written using RTCMOL[3:0] (D[3:0]/0x301020). RTCMOL[3:0]: RTC 1-month Counter Bits in the RTC Month Register (D[3:0]/0x301020) 10-month counter This counter counts in units of 10 months, and is set to 1 with 1 carried over from the 1-month counter. When years change, this counter is reset to 0 along with the 1-month counter, and outputs a carry over of 1 to the 1-year counter. The count data is read out and written using RTCMOH (D4/0x301020). RTCMOH: RTC 10-month Counter Bit in the RTC Month Register (D4/0x301020) 1-year counter This 4-bit BCD counter counts in units of years. It counts from 0 to 9 with 1 carried over from the month counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-year counter. The count data is read out and written using RTCYL[3:0] (D[3:0]/0x301024). RTCYL[3:0]: RTC 1-year Counter Bits in the RTC Year Register (D[3:0]/0x301024) 10-year counter This 4-bit BCD counter counts tens of years. It counts from 0 to 9 with 1 carried over from the 1-year counter. The count data is read out and written using RTCYH[3:0] (D[7:4]/0x301024). RTCYH[3:0]: RTC 10-year Counter Bits in the RTC Year Register (D[7:4]/0x301024) Days of week counter This is a septenary counter (that counts from 0 to 6) representing the days of the week. It counts with the same timing as the 1-day counter. The count data is read out and written using RTCWK[2:0] (D[2:0]/0x301028). RTCWK[2:0]: RTC Days of Week Counter Bits in the RTC Days of Week Register (D[2:0]/0x301028) V The correspondence between the counter values and days of the week can be set in a program as desired. Table V.5.2.1 lists the basic correspondence. Table V.5.2.1 Correspondence between Counter Values and Days of the Week RTCWK2 RTCWK1 RTCWK0 Days of the week 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 Saturday Friday Thursday Wednesday Tuesday Monday Sunday S1C33401 TECHNICAL MANUAL EPSON RTC V-5-3 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) Initial counter values When initially reset, the counter values are not initialized. After power-on, the counter values are indeterminate. Be sure to initialize the counters by following the procedure described in Section V.5.3.2, "Initial Sequence of the RTC." About detection of leap years The algorithm used in the RTC to detect leap years is for Anno Domini (A.D.) only, and can automatically identify leap years up to the year 2399. Years (0 to 99) without a remainder when divided by 4 are considered leap years. When the 1-year and 10-year counters both are 0, a common year is assumed. V-5-4 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.3 Control of the RTC I V.5.3.1 Controlling the Operating Clock The RTC is clocked by the 32.768-kHz (typ.) OSC1 clock. OSC1 oscillation can be turned on or off using SOSC1 (D0/0x48360) of the CMU. SOSC1: Low-speed Oscillation (OSC1) On/Off Control Bit in the Core System Clock Control Register (D0/0x48360) To use the RTC, SOSC1 (D0/0x48360) must be set to 1 (default) to turn the OSC1 oscillator circuit on and keep it running. Note: If the OSC1 oscillator circuit is turned on while idle, a finite time (of about 3 seconds) is required for its oscillation to stabilize. Do not let the RTC start counting until this time elapses. The OSC1 clock does not stop regardless of chip standby mode (HALT, HALT2, or SLEEP). For details of clock control, see Section II.3, "Clock Management Unit (CMU)." For the configuration of the OSC1 oscillator circuit, see Section V.5.6, "OSC1 Oscillator Circuit." V.5.3.2 Initial Sequence of the RTC Immediately after power-on, the contents of RTC registers are indeterminate. After powering on, follow the procedure below to let the RTC start ticking the time. Later sections detail the contents of each control. 1. Power-on 2. System initialization processing and waiting for OSC1 stabilization Although the OSC1 oscillator circuit starts oscillating immediately after power is switched on, a finite time of up to 3 seconds is required before the output clock stabilizes. 3. Disabling RTC interrupts To prevent the occurrence of unwanted RTC interrupts, the following register settings are required: Write 0x0 to the RTC Interrupt Mode Register (0x301004) to disable RTC interrupts. Write 0x1 to the RTC Interrupt Status Register (0x301000) to clear the RTC interrupt status. For details, see Section V.5.4, "RTC Interrupts." 4. Starting the count Write 0x2 (for 12-hour mode) or 0x12 (for 24-hour mode) to the RTC Control Register (0x301008) to start counting by the RTC. This operation initializes the contents of 12-hour/24-hour mode, etc. that affect count data when settings are changed, and is not the standard operation to start counting. For details, see Section V.5.3.3, "Selecting 12/24-hour Mode and Setting the Counters," and Section V.5.3.4, "Starting, Stopping, and Resetting Counters." 5. Confirming accessibility status of the RTC Use the RTC Access Control Register (0x30100C) to retain the counters intact and read out the busy flag to confirm that the RTC can now be accessed. For details, see Section V.5.3.5, "Counter Hold and Busy Flag." 6. Stopping and resetting the count Write 0x1 to the RTC Control Register (0x301008) to stop the count, then reset the divide-by stage of the count clock. For details, see Section V.5.3.4, "Starting, Stopping, and Resetting Counters." 7. Setting the date and time Use the respective count registers to initialize all counters to the current date and time. For details, see Section V.5.3.3, "Selecting 12/24-hour Mode and Setting the Counters." RTC 8. Restarting count Release the counters from the hold state (set in step 5) and repeat step 4 to restart counting by the RTC. For details, see Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.4, "Starting, Stopping, and Resetting Counters." S1C33401 TECHNICAL MANUAL EPSON V V-5-5 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.3.3 Selecting 12/24-hour Mode and Setting the Counters Selecting 12-hour/24-hour mode Whether to use the time clock in 12-hour or 24-hour mode can be selected using RTC24H (D4/0x301008). RTC24H = 1: 24-hour mode RTC24H = 0: 12-hour mode The count range of hour counters changes with this selection. RTC24H: 24H/12H Mode Select Bit in the RTC Control Register (D4/0x301008) Basically, this setting should be changed while the counters are idle. RTC24H (D4/0x301008) is allocated to the same address as the control bits that start the counters. Therefore, 12-hour mode or 24-hour mode can be selected at the same time the counters are started. Note: Rewriting RTC24H (D4/0x301008) may corrupt count data for the hours, days, months, years or days of the week. Therefore, once RTC24H (D4/0x301008) settings are changed, be sure to set data back in these counters again. Checking A.M./P.M. with 12-hour mode selected When 12-hour mode is selected, RTCAP (D6/0x301018) that indicates A.M. or P.M. is enabled. RTCAP = 0: A.M. RTCAP = 1: P.M. For 24-hour mode, RTCAP (D6/0x301018) is fixed to 0. RTCAP: AM/PM Indicator Bit in the RTC Hour Register (D6/0x301018) When setting the time of day, write either of the values above to this bit to specify A.M. or P.M. Setting the counters Idle counters can be accessed for read or write at any time. However, settings like those shown below should be avoided, since such settings may cause timekeeping errors. * Settings exceeding the effective range Do not set count data exceeding 60 seconds, 60 minutes, 12 or 24 hours, 31 days, 12 months, or 99 years. * Settings nonexistent in the calendar Do not set such nonexistent dates as April 31 or February 29, 2005. Even if such settings are made, the counters operate normally, so that when 1 is carried over from the hour counter to the 1-day counter, the day counter counts up to the first day of the next month. (For April 31, the day counter counts up to May 1; for February 29, 2005, the day counter counts up to March 1, 2005.) If any counter must be rewritten while operating, there is a procedure that must be followed to ensure that the counter is rewritten correctly. For details, see Section V.5.3.6, "Reading from and Writing to Counters in Operation." V.5.3.4 Starting, Stopping, and Resetting Counters Starting and stopping counters The RTC starts counting when RTCSTP (D1/0x301008) is set to 0, and stops counting when this bit is set to 1. RTCSTP: Counter Run/Stop Control Bit in the RTC Control Register (D1/0x301008) The RTC is stopped by writing 1 to RTCSTP (D1/0x301008) at the 32-kHz input clock divide-by stage of 8,192 Hz or those stages that follow. The RTC does not stop at up to the input clock divide-by-2 stage (16,384 Hz). If the RTC stops counting when 1 is carried over to the next-digit counter, the count value may be corrupted. Therefore, see the next section to ensure that 1 is not carried over when counters are made to stop. This is unnecessary, however, when the contents of all counters are newly set again. Resetting the counters RTCRST (D0/0x301008) is the bit used to reset the 32 kHz to 2 Hz counters. RTCRST: Software Reset Bit in the RTC Control Register (D0/0x301008) Setting RTCRST (D0/0x301008) to 1 resets the counters above (cleared to 0), and writing 0 to this bit negates the reset. V-5-6 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.3.5 Counter Hold and Busy Flag I If 1 is carried over when reading the counters, the correct counter value may not be read out. Moreover, if a write or stop operation is attempted, the counter value may be corrupted. Therefore, whether counters are in a carry (busy) state should be checked before reading or writing data from or to the count registers. For this purpose, control bits RTCBSY (D1/0x30100C) and RTCHLD (D0/0x30100C) are provided. RTCBSY: Counter Busy Flag in the RTC Access Control Register (D1/0x30100C) RTCHLD: Counter Hold Control Bit in the RTC Access Control Register (D0/0x30100C) RTCBSY (D1/0x30100C) is a read-only flag indicating that 1 is being carried over. RTCBSY (D1/0x30100C) is set to 1 when 1 is being carried over; otherwise, it is 0. RTCBSY (D1/0x30100C) should be confirmed as being 0 before accessing the counters to ensure that the correct value will be read or set. Note, however, that RTCBSY (D1/0x30100C) is fixed to 1 while counting is in progress. To reflect the current state in the count value, RTCHLD (D0/0x30100C) should be set to 1. RTCBSY = 0 (RTC accessible) If the value of RTCBSY (D1/0x30100C) is 0 when this bit is read out after writing 1 to RTCHLD (D0/0x30100C), it means that 1 is not being carried over. In this case, the counter hold function is actuated, with a carry over of 1 to the 1-second counter disabled in hardware. Counters that count less than seconds continue operating. Data can be read from or written to the count registers in this state. After reading or writing data, reset RTCHLD (D0/0x30100C) to 0. When 1 must be carried over while data is being read or written with counters in the hold state, 1 second is automatically added at the time, with RTCHLD (D0/0x30100C) reset to 0 to correct the count value. This correction is effective for only 1 second, and the time to carry over 1 on subsequent occasions is ignored. In this case, timekeeping data gets out of order. Therefore, be sure to reset RTCHLD (D0/0x30100C) to 0 as soon as possible after completing the necessary read or write operation. RTCBSY = 1 (RTC is busy) If the value of RTCBSY (D1/0x30100C) is 1 when this bit is read after writing 1 to RTCHLD (D0/0x30100C), it means that 1 is being carried over. The period needed for the counters to carry over 1 is 4 ms per second. In this case, reset RTCHLD (D0/0x30100C) to 0 as soon as possible and [A] recheck RTCBSY (D1/0x30100C) by following the same procedure or [B] wait 4 ms before checking RTCBSY (D1/0x30100C). If RTCBSY (D1/0x30100C) is found to be 1, be sure to immediately reset RTCHLD (D0/0x30100C) to 0. If RTCHLD (D0/0x30100C) is left at 1, the time of day may become incorrect. A B RTCHLD 1 RTCHLD 0 RTCBSY read No RTCBSY = 0? RTCHLD 1 4 ms wait RTCBSY read RTCHLD 0 RTCBSY = 0? No Yes Yes Register read/write Register read/write RTCHLD 0 RTCHLD 0 V RTC Figure V.5.3.5.1 Procedure for Checking whether the RTC is Busy There is also a method of reading out data without using RTCHLD (D0/0x30100C) and RTCBSY (D1/0x30100C). (See the next section.) S1C33401 TECHNICAL MANUAL EPSON V-5-7 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.3.6 Reading from and Writing to Counters in Operation As described in the previous section, the counters must be accessed for read/write when 1 is not being carried over. Follow the procedure shown in the flowchart in Figure V.5.3.5.1 to read from or write to the counters. The counters can be read without using RTCHLD (D0/0x30100C) and RTCBSY (D1/0x30100C), as shown in Figure V.5.3.6.1. First data read (DATA1) Second data read (DATA2) DATA1 = DATA2? No Yes Figure V.5.3.6.1 Procedure for Reading Counters not in the Hold State V.5.3.7 30-second Correction The description "30-second correction" means adding 1 to the minutes when seconds of the time clock are in the range of 30 to 59 seconds, and doing nothing when in the range of 0 to 29 seconds. This function may be used to round up seconds to minutes when resetting seconds in an application. This function can be executed by writing 1 to RTCADJ (D2/0x301008). RTCADJ: 30-second Adjustment Bit in the RTC Control Register (D2/0x301008) Writing 1 to RTCADJ (D2/0x301008) causes the RTC to operate as follows: * When the 10-second counter is 3 or more, the RTC generates a carry over of 1 to start counting by the 1-minute counter. * When the 10-second counter is 2 or less, the RTC does not generate a carry over of 1. After RTCADJ (D2/0x301008) is set to 1, it remains set for the 4-ms period required for this processing, then automatically returns to 0. Accessing the counters while RTCADJ (D2/0x301008) = 1 is prohibited. Writing 0 to RTCADJ (D2/0x301008) is also prohibited, because it would cause the RTC to operate erratically. A B RTCADJ 1 RTCADJ 1 RTCADJ read RTCADJ read RTCADJ = 0? No RTCADJ = 0? Yes Wait 4 ms or more No Yes Figure V.5.3.7.1 Procedure for Executing 30-second Correction V-5-8 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.4 RTC Interrupts I The RTC has a function to generate interrupts at given intervals. Since the RTC is active even in standby mode, interrupts may be used to turn off SLEEP mode. This section describes the internal interrupt control function of the RTC. To generate interrupts to the CPU, the ITC must also be set up. For details on how to control the ITC, see Section IV.2, "Interrupt Controller (ITC)." For details on how to turn off SLEEP mode using an interrupt, see Section II.3, "Clock Management Unit (CMU)." Setting the interrupt cycle The interrupt cycle (in which the RTC outputs interrupt requests at specific intervals) can be selected from four choices listed in Table V.5.4.1 by using RTCT[1:0] (D[3:2]/0x301004). RTCT[1:0]: RTC Interrupt Cycle Setup Bits in the RTC Interrupt Mode Register (D[3:2]/0x301004) Table V.5.4.1 Interrupt Cycle Settings RTCT1 RTCT0 Interrupt cycle 1 1 0 0 1 0 1 0 1 hour 1 minute 1 second 1/64 second RTCT[1:0] (D[3:2]/0x301004) should be set while RTC interrupts are disabled. (See the procedure for enabling and disabling interrupts described below.) Setting interrupt conditions The interrupt requests sent to the ITC can be selected as edge-triggered or level-sensed interrupts by setting a register bit. RTCIMD (D1/0x301004) is the bit provided for this purpose. RTCIMD: RTC Interrupt Mode Select Bit in the RTC Interrupt Mode Register (D1/0x301004) Setting RTCIMD (D1/0x301004) to 1 selects a level-sensed interrupt; setting it to 0 selects an edge-triggered interrupt. When an edge-triggered interrupt has been selected, the RTC outputs an interrupt pulse to the ITC using the bus clock supplied from the BBCU. If a cause of interrupt occurs when the bus clock has not been supplied such as in SLEEP mode, the RTC switches the interrupt mode to level-sensed and sets the interrupt signal to the active level from occurrence of the interrupt cause until the bus clock supply is started. Enabling and disabling interrupts The RTC interrupt requests output to the ITC are enabled by setting RTCIEN (D0/0x301004) to 1 and disabled by setting it to 0. RTCIEN: RTC Interrupt Enable Bit in the RTC Interrupt Mode Register (D0/0x301004) Interrupt status When the RTC is up and running, RTCIRQ (D0/0x301000) is set at the cyclic interrupt intervals set up by RTCT[1:0]. When RTC interrupts are enabled by RTCIEN (D0/0x301004), interrupt requests are sent to the ITC. V RTCIRQ: Interrupt Status Bit in the RTC Interrupt Status Register (D0/0x301000) Writing 1 to this status bit clears the bit. Because this bit is not cleared in hardware, be sure to clear it in software after an interrupt is generated. If this bit remains set while interrupts are re-enabled or control is returned from the interrupt handler routine by the reti instruction, the same interrupt may be generated again. RTC Precautions All RTC interrupt control bits described above are indeterminate when power is turned on. Moreover, these bits are not initialized to specific values by an initial reset. After power-on, be sure to set RTCIEN (D0/0x301004) to 0 (interrupt disabled) to prevent the occurrence of unwanted RTC interrupts. Also be sure to write 1 to RTCIRQ (D0/0x301000) to reset it. S1C33401 TECHNICAL MANUAL EPSON V-5-9 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.5 Standby Mode (#STBY pin) and Power Supply of the RTC The RTC has a power supply pin (RTCVDD) provided independently of other blocks of the system. When the RTC is supplied with continuous power from this pin, it is assured of continued timekeeping operation even when all other power supplies are turned off. (Standby mode) By setting the #STBY pin to a low level, the RTC enters standby mode. In standby mode, the RTC registers are disabled for writing and reading. Also the functions to request an interrupt to the ITC and to supply OSC1 clock to the CMU are disabled. When turning the power supply other than RTCVDD on or off, follow the procedure shown below. (1) Power off 1. Set the #STBY pin to low. 2. Turn the power supply other than RTCVDD off. (2) Power on 1. Turn the power supply other than RTCVDD on. 2. Set the #STBY pin to high. Make sure the same voltage as VDD is supplied to RTCVDD. V-5-10 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.6 OSC1 Oscillator Circuit I The IC described here contains an oscillator circuit (OSC1) used to generate a 32.768 kHz (typ.) clock as the clock source for timekeeping operation of the RTC. The OSC1 clock can also be used as a power-saving operating clock for the core system or peripheral circuits. For details, see Section II.3, "Clock Management Unit (CMU)," and Section IV.4, "Prescaler (PSC)." V.5.6.1 Input/Output Pins of the OSC1 Oscillator Circuit Table V.5.6.1.1 lists the input/output pins of the OSC1 oscillator circuit. Table V.5.6.1.1 Input/Output Pins of the Low-speed (OSC1) Oscillator Circuit Function I/O Pin name I O OSC1 OSC2 OSC1 input pin: Crystal oscillator or external clock input OSC1 output pin: Crystal oscillator output (left open when external clock is input) V.5.6.2 Structure of the OSC1 Oscillator Circuit The OSC1 oscillator circuit accommodates a crystal oscillator and external clock input. As for the RTC, RTCVDD is used to supply power to this circuit. Figure V.5.6.2.1 shows the structure of the OSC1 oscillator circuit. CG1 OSC1 VDD VSS fOSC1 X'tal1 CD1 VSS Rd Rf fOSC1 External clock N.C. Oscillation circuit control signal OSC2 OSC1 OSC2 Oscillation circuit control signal (2) External clock input (1) Crystal oscillation circuit OSC1 Low level Oscillation circuit control signal OSC2 VSS (3) When not used Figure V.5.6.2.1 OSC1 Oscillator Circuit For use as a crystal oscillator circuit, connect a crystal resonator X'tal1 (32.768 kHz, typ.), feedback resistor (Rf), two capacitors (CG1, CD1), and, if necessary, a drain resistor (Rd) to the OSC1 and OSC2 pins and VSS, as shown in Figure V.5.6.2.1 (1). To use an external clock, leave the OSC2 pin open and input an RTCVDD level clock (whose duty cycle is 50%) to the OSC1 pin. Do not input VDDE or other I/O level clocks. The oscillator frequency/input clock frequency is 32.768 kHz (typ.). Make sure the crystal resonator or external clock used in the RTC has this clock frequency. With any other clock frequencies, the RTC cannot be used for timekeeping purposes. For details of oscillation characteristics and the input characteristics of external clock, see "Electrical Characteristics." When not using the OSC1 oscillator circuit, connect the OSC1 pin to VSS and leave the OSC2 pin open. S1C33401 TECHNICAL MANUAL EPSON V-5-11 V RTC V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.6.3 Oscillation Control Internal control bit SOSC1 (D0/0x48360) of the CMU register is used to control OSC1 oscillation. SOSC1: Low-speed Oscillation (OSC1) On/Off Control Bit in the Core System Clock Control Register (D0/0x48360) Setting this control bit to 0 causes the OSC1 oscillator circuit to stop; setting it to 1 causes the OSC1 oscillator circuit to start oscillating, thereby outputting a clock signal waveform. When initially reset, this bit is set to 1, so that the OSC1 oscillator circuit continues oscillating. Notes: * The clock control register (0x48360) of the core system is write-protected. The write protection of this and other CMU control registers at addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 to be rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Since unnecessary rewrites to addresses 0x40180 to 0x40188 and 0x48360 to 0x48372 could cause the system to operate erratically, make sure the data set in the Clock Control Protect Register (0x4836E) is other than 0x0096 (HW) unless rewriting the said registers. * When the oscillator is made to start oscillating by setting SOSC1 (D0/0x48360) from 0 to 1, a finite time (of up to 3 seconds) is required until oscillation stabilizes. To prevent system malfunction, do not use the oscillator-derived clock until this oscillation stabilization time elapses. V-5-12 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.7 Details of Control Registers I Table V.5.7.1 RTC Register List Address 0x00301000 0x00301004 0x00301008 0x0030100C 0x00301010 0x00301014 0x00301018 0x0030101C 0x00301020 0x00301024 0x00301028 Register name RTC Interrupt Status Register (pRTCINTSTAT) RTC Interrupt Mode Register (pRTCINTMODE) RTC Control Register (pRTC_CNTL0) RTC Access Control Register (pRTC_CNTL1) RTC Second Register (pRTCSEC) RTC Minute Register (pRTCMIN) RTC Hour Register (pRTCHOUR) RTC Day Register (pRTCDAY) RTC Month Register (pRTCMONTH) RTC Year Register (pRTCYEAR) RTC Days of Week Register (pRTCDAYWEEK) Size 32 32 32 32 32 32 32 32 32 32 32 Function RTC interrupt status Sets RTC interrupt conditions and enables RTC interrupts. Controls RTC operation. Controls RTC busy status and counter hold. Seconds counter data Minutes counter data Hours counter data Days counter data Months counter data Years counter data Days of the week counter data Each RTC control register is described below. The RTC control registers are mapped as 32-bit devices to Area 6 at addresses 0x301000 to 0x301028, and can be accessed in units of words, half-words, or bytes. Notes: * The contents of all RTC control registers are indeterminate when power is turned on, and are not initialized to specific values by initial reset. These registers should be initialized in software. * If 1 is being carried over when the counters are accessed for read, the correct counter value may not be read out. Moreover, attempting to write to a counter or other control register may corrupt the counter value. Therefore, do not write to counters while 1 is being carried over. For the correct method of operation, see Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation." * To access the RTC control registers, the CE6 area must be set up in the BBCU. For setting details, see Section V.2, "Area 6 Settings and Macro Control Register." * For details of RTC-related registers in the CMU and ITC mentioned here, see the following sections: - Section II.3, "Clock Management Unit (CMU)" - Section IV.2, "Interrupt Controller (ITC)" V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-13 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301000: RTC Interrupt Status Register (pRTCINTSTAT) Register name Address RTC interrupt status register (pRTCINTSTAT) Bit Name 0301000 D31-1 - (W) D0 RTCIRQ Function Setting reserved Init. R/W - - Interrupt status 1 Occurred 0 Not occurred D[31:1] Reserved D0 RTCIRQ: Interrupt Status Bit This bit indicates whether a cause of RTC interrupt occurred as follows: 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Resets this bit to 0 0 (W): Has no effect X Remarks - R/W Reset by writing 1. This bit is set at cyclic interrupt intervals set up by RTCT[1:0] (D[3:2]/0x301004). When RTC interrupts have been enabled by RTCIEN (D0/0x301004) at this time, an interrupt request is sent to the ITC. This bit is always set, even when RTC interrupts are disabled. Note: Writing 1 to this status bit clears it. Because this bit is not cleared in hardware, be sure to clear it in software after an interrupt is generated. If this bit remains set while interrupts are re-enabled or control is returned from the interrupt handler routine by the reti instruction, the same interrupt may be generated again. Moreover, the value of this bit is indeterminate after power-on, and is not initialized to 0 by initial reset. To prevent the occurrence of unwanted RTC interrupts, be sure to reset this bit in software after power-on and initial reset. V-5-14 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301004: RTC Interrupt Mode Register (pRTCINTMODE) Register name Address RTC interrupt mode register (pRTCINTMODE) Name Bit 0301004 D31-4 - D3 RTCT1 (W) D2 RTCT0 D1 D0 RTCIMD RTCIEN Function reserved RTC interrupt cycle setup RTC interrupt mode select RTC interrupt enable D[31:4] Reserved D[3:2] RTCT[1:0]: RTC Interrupt Cycle Setup Bits These bits select the RTC interrupt cycle. Setting - RTCT[1:0] Cycle 11 1 hour 10 1 minute 01 1 second 00 1/64 second 1 Level sense 0 Edge trigger 1 Enabled 0 Disabled I Init. R/W - X X - R/W X X R/W R/W Remarks Table V.5.7.2 Interrupt Cycle Settings RTCT1 RTCT0 1 1 0 0 1 0 1 0 Interrupt cycle 1 hour 1 minute 1 second 1/64 second (Default: indeterminate) RTCIRQ (D0/0x301000) is set by a count-up pulse of the interrupt cycle counter selected. When RTC interrupts are enabled by RTCIEN (D0), an interrupt request is sent to the ITC. RTCT[1:0] should be set while RTC interrupts are disabled. (These bits may also be set simultaneously when RTC interrupts are enabled.) D1 RTCIMD: RTC Interrupt Mode Select Bit This bit specifies whether RTC interrupts are to be generated by an edge or level of the interrupt request signal. 1 (R/W): Level sensed 0 (R/W): Edge triggered When an edge-triggered interrupt is selected and used to turn off SLEEP mode via the CMU, note that no interrupts will be generated because the ITC is inactive. When an RTC interrupt handler routine must be executed after exiting SLEEP mode, select a level-sensed interrupt. D0 RTCIEN: RTC Interrupt-Enable Bit This bit enables or disables RTC interrupt request output to the ITC. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts To generate an RTC interrupt or use an RTC interrupt request signal to turn off SLEEP mode, set this bit to 1. When this bit is 0, no interrupts are generated even when RTCIRQ (D0/0x301000) is set and SLEEP mode cannot be turned off. Note: The value of RTCIEN is indeterminate after power-on, and not initialized to 0 by initial reset. To prevent the occurrence of unwanted RTC interrupts, be sure to clear this bit in software after power-on and initial reset. V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-15 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301008: RTC Control Register (pRTC_CNTL0) Register name Address RTC control register (pRTC_CNTL0) Bit Name 0301008 D31-5 - D4 RTC24H (W) D3 - D2 RTCADJ D1 RTCSTP D0 RTCRST Function reserved 24H/12H mode select reserved 30-second adjustment Counter run/stop control Software reset Setting Init. R/W - X - X X X - 1 24H 0 12H - 1 Adjust 1 Stop 1 Reset 0 - 0 Run 0 - D[31:5] Reserved D4 RTC24H: 24H/12H Mode Select Bit This bit selects whether to use the hour counter in 24-hour or 12-hour mode. 1 (R/W): 24-hour mode 0 (R/W): 12-hour mode Remarks - R/W - R/W R/W R/W The count range of hour counters changes with this selection. Basically, this setting should be changed while the counters are idle. Since this register is assigned a control bit (D1) to start the counters, 12-hour or 24-hour mode may be selected when starting the counters. Note: Rewriting RTC24H may corrupt the count data for hours, days, months, years, or days of the week. Therefore, after changing the RTC24H setting, be sure to set data back in these counters again. D3 Reserved D2 RTCADJ: 30-second Adjustment Bit This bit executes 30-second correction. 1 (W): Execute 30-second correction 0 (W): Has no effect 1 (R): 30-second correction being executed 0 (R): 30-second correction completed (not being executed) The description "30-second correction" means adding 1 to the minutes when seconds of the time clock are in the 30-to-59 second range, and doing nothing in the 0-to-29 second range. This function may be used to round up seconds to minutes when resetting seconds in an application. Writing 1 to this bit causes the RTC to operate as follows: * When the 10-second counter is 3 or more, the RTC generates a carry over of 1 to start counting by the 1-minute counter. * When the 10-second counter is 2 or less, the RTC does not generate a carry over of 1. After being set to 1, this bit remains set for the 4-ms period needed for the processing above, then is automatically reset to 0. Note: Accessing the counters while RTCADJ = 1 is prohibited. Writing 0 to this bit during such time is also prohibited, because it would cause the RTC to operate erratically. V-5-16 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) D1 RTCSTP: Counter Run/Stop Control Bit This bit starts or stops the counters. It also indicates counter operating status. 1 (R/W): Stops counters/Counters idle 0 (R/W): Starts counters/Counters operating I Setting this bit to 0 starts the counters; setting it to 1 stops the counters. The value read from this bit is 0 when the counters are operating, and 1 when the counters are idle. Writing 1 to this bit stops the counters at the 32-kHz input clock divide-by stage of 8,192 Hz or stages that follow. The counters do not stop at up to the input clock divide-by-2 stage (16,384 Hz). If the counters stop while 1 is being carried over, the count value may be corrupted. Therefore, see Section V.5.3.5 to ensure that 1 is not being carried over when the counters are stopped. This is unnecessary when, for example, the contents of all counters are newly set again. D0 RTCRST: Software Reset Bit This bit resets the counters currently at divide-by stages. 1 (R/W): Reset counters 0 (R/W): Negate reset Setting this bit to 1 resets the 32 kHz to 2 Hz counters (cleared to 0). Writing 0 to this bit negates the reset. V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-17 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x30100C: RTC Access Control Register (pRTC_CNTL1) Register name Address Bit Name 030100C D31-2 - RTC access D1 RTCBSY (W) control register D0 RTCHLD (pRTC_CNTL1) Function reserved Counter busy flag Counter hold control Setting Init. R/W - 1 Busy 1 Hold 0 R/W possible 0 Running D[31:2] Reserved D1 RTCBSY: Counter Busy Flag This flag indicates whether 1 is being carried over to the next-digit counter. 1 (R): Busy (while 1 is being carried over) 0 (R): Accessible for read/write 1/0 (W): Has no effect - X X Remarks - R R/W If 1 is being carried over while the counters are being read, correct counter values may not be read. Moreover, attempting a write or stop operation may corrupt the counter values. Therefore, this bit should be checked to confirm that the counters are not in a carry (busy) state before reading or writing data from or to the count registers. However, because this bit is fixed to 1 while the counters are operating, RTCHLD (D0) should be set to 1 so that the count value reflects the current state. When a value of 0 is read from this bit after writing 1 to RTCHLD (D0), it means that 1 is not now being carried over. In this case, the counter hold function is also actuated, with a carry over of 1 to the 1-second counter disabled in hardware. Counters for less than seconds continue operating. In this state, data can be read from or written to the count registers. After reading or writing data, reset RTCHLD (D0) to 0. If 1 is being carried over when data is being read from or written to counters in the hold state, 1 second is automatically added at that time, with RTCHLD (D0) reset to 0 for correcting the count value. This correction is only effective for 1 second, thus ignoring the time needed to carry over 1 on subsequent occasions. In this case, the timekeeping data gets out of order. Therefore, be sure to reset RTCHLD (D0) to 0 as soon as possible after completing the required read or write operation. When a value of 1 is read from this bit after writing 1 to RTCHLD (D0), it means that 1 is now being carried over. A period of 4 ms per second is required for a carry over of 1 to the counters. In this case, reset RTCHLD (D0) to 0 as soon as possible and check this bit again by following the same procedure, or wait 4 ms before checking this bit. If this bit is set to 1, always reset RTCHLD (D0) to 0 immediately. Leaving RTCHLD (D0) set to 1 may result in an incorrect time of day. D0 RTCHLD: Counter Hold Control Bit This bit allows the busy state of counters to be checked and the counters held intact. 1 (R/W): Checks for busy state/Holds counters 0 (R/W): Normal operation For the operation of this bit, see the description of RTCBSY (D1) above. V-5-18 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301010: RTC Second Register (pRTCSEC) Register name Address RTC second register (pRTCSEC) Bit Name 0301010 D31-7 - D6 RTCSH2 (W) D5 RTCSH1 D4 RTCSH0 D3 RTCSL3 D2 RTCSL2 D1 RTCSL1 D0 RTCSL0 Function I Setting reserved RTC 10-second counter - 0 to 5 RTC 1-second counter 0 to 9 Init. R/W - X X X X X X X Remarks - R/W R/W Note: Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") D[31:7] Reserved D[6:4] RTCSH[2:0]: RTC 10-second Counter Bits These bits comprise a 3-bit BCD counter used to count tens of seconds. The counter counts from 0 to 5 with a carry over of 1 from the 1-second counter. This counter is reset to 0 after 5 and outputs a carry over of 1 to the 1-minute counter. D[3:0] RTCSL[3:0]: RTC 1-second Counter Bits These bits comprise a 4-bit BCD counter used to count units of seconds. The counter counts from 0 to 9 synchronously with a 1-second signal derived from the 32.768-kHz OSC1 clock. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-second counter. V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-19 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301014: RTC Minute Register (pRTCMIN) Register name Address RTC minute register (pRTCMIN) Bit Name 0301014 D31-7 - D6 RTCMIH2 (W) D5 RTCMIH1 D4 RTCMIH0 D3 RTCMIL3 D2 RTCMIL2 D1 RTCMIL1 D0 RTCMIL0 Function Setting reserved RTC 10-minute counter - 0 to 5 RTC 1-minute counter 0 to 9 Init. R/W - X X X X X X X Remarks - R/W R/W Note: Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") D[31:7] Reserved D[6:4] RTCMIH[2:0]: RTC 10-minute Counter Bits These bits comprise a 3-bit BCD counter used to count tens of minutes. The counter counts from 0 to 5 with a carry over of 1 from the 1-minute counter. This counter is reset to 0 after 5 and outputs a carry over of 1 to the 1-hour counter. D[3:0] RTCMIL[3:0]: RTC 1-minute Counter Bits These bits comprise a 4-bit BCD counter used to count units of minutes. The counter counts from 0 to 9 with a carry over of 1 from the 10-second counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-minute counter. V-5-20 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301018: RTC Hour Register (pRTCHOUR) Name Function 0301018 D31-7 - D6 RTCAP (W) D5 RTCHH1 D4 RTCHH0 D3 RTCHL3 D2 RTCHL2 D1 RTCHL1 D0 RTCHL0 reserved AM/PM indicator RTC 10-hour counter Register name Address RTC hour register (pRTCHOUR) Bit RTC 1-hour counter I Setting - 1 PM 0 AM 0 to 2 or 0 to 1 0 to 9 Init. R/W - X X X X X X X Remarks - R/W R/W R/W Notes: * Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") * Rewriting RTC24H (D4/0x301008) may corrupt the count data in this register. Therefore, after changing the RTC24H (D4/0x301008) setting, be sure to set up this register again. D[31:7] Reserved D6 RTCAP: AM/PM Indicator Bit When 12-hour mode is selected, this bit indicates A.M. or P.M. 1 (R/W): P.M. 0 (R/W): A.M. This bit is only effective when RTC24H (D4/0x301008) is set to 0 (12-hour mode). When 24-hour mode is selected, this bit is fixed to 0. In this case, do not write 1 to RTCAP. Note: The RTCAP bit keeps the current set value even if RTC24H (D4/0x301008) is changed from 12-hour mode to 24-hour mode, and will be fixed at 0 after the hour counter is updated (or reset in software). D[5:4] RTCHH[1:0]: RTC 10-hour Counter Bits These bits comprise a 2-bit BCD counter used to count tens of hours. With a carry over of 1 from the 1-hour counter, the counter counts from 0 to 1 when 12-hour mode is selected, or from 0 to 2 when 24-hour mode is selected. The counter is reset at 12 0'clock or 24 0'clock, and outputs a carry over of 1 to the 1-day counter. D[3:0] RTCHL[3:0]: RTC 1-hour Counter Bits These bits comprise a 4-bit BCD counter used to count units of hours. The counter counts from 0 to 9 with a carry over of 1 from the 10-minute counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-hour counter. Depending on whether 12-hour mode or 24-hour mode is selected, the counter is reset at 12 0'clock or 24 0'clock. V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-21 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x30101C: RTC Day Register (pRTCDAY) Register name Address RTC day register (pRTCDAY) Bit Name 030101C D31-6 - D5 RTCDH1 (W) D4 RTCDH0 D3 RTCDL3 D2 RTCDL2 D1 RTCDL1 D0 RTCDL0 Function Setting reserved RTC 10-day counter - 0 to 3 RTC 1-day counter 0 to 9 Init. R/W - X X X X X X Remarks - R/W R/W Notes: * Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") * Rewriting RTC24H (D4/0x301008) may corrupt the count data in this register. Therefore, after changing the RTC24H (D4/0x301008) setting, be sure to set up this register again. D[31:6] Reserved D[5:4] RTCDH[1:0]: RTC 10-day Counter Bits These bits comprise a 2-bit BCD counter used to count tens of days. The counter counts from 0 to 2 or 3 with a carry over of 1 from the 1-day counter. The number of days in each month and leap years are taken into account, so that when months change the counter is reset to 0 along with the 1-day counter, and a carry over of 1 is output to the 1-month counter. D[3:0] RTCDL[3:0]: RTC 1-day Counter Bits These bits comprise a 4-bit BCD counter used to count units of days. The counter counts from 0 to 9 with a carry over of 1 from the hour counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-day counter. The number of days in each month and leap years are taken into account, so that the counter is reset to 1 when months change. V-5-22 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301020: RTC Month Register (pRTCMONTH) Register name Address RTC month register (pRTCMONTH) Bit Name Function reserved 0301020 D31-5 - D4 RTCMOH RTC 10-month counter (W) D3 RTCMOL3 RTC 1-month counter D2 RTCMOL2 D1 RTCMOL1 D0 RTCMOL0 I Setting - 0 or 1 0 to 9 Init. R/W - X X X X X Remarks - R/W R/W Notes: * Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") * Rewriting RTC24H (D4/0x301008) may corrupt the count data in this register. Therefore, after changing the RTC24H (D4/0x301008) setting, be sure to set up this register again. D[31:5] Reserved D4 RTCMOH: RTC 10-month Counter Bit This is a tens of months count bit. This bit is set to 1 with a carry over of 1 from the 1-month counter. When years change, this bit is reset to 0 along with the 1-month counter, and a carry over of 1 is output to the 1-year counter. D[3:0] RTCMOL[3:0]: RTC 1-month Counter Bits These bits comprise a 4-bit BCD counter used to count units of months. The counter counts from 0 to 9 with a carry over of 1 from the day counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-month counter. The counter is reset to 1 when years change. V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-23 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301024: RTC Year Register (pRTCYEAR) Name Function 0301024 D31-8 - D7 RTCYH3 (W) D6 RTCYH2 D5 RTCYH1 D4 RTCYH0 D3 RTCYL3 D2 RTCYL2 D1 RTCYL1 D0 RTCYL0 reserved RTC 10-year counter - 0 to 9 RTC 1-year counter 0 to 9 Register name Address RTC year register (pRTCYEAR) Bit Setting Init. R/W - X X X X X X X X Remarks - R/W R/W Notes: * Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") * Rewriting RTC24H (D4/0x301008) may corrupt the count data in this register. Therefore, after changing the RTC24H (D4/0x301008) setting, be sure to set up this register again. D[31:8] Reserved D[7:4] RTCYH[3:0]: RTC 10-year Counter Bits These bits comprise a 4-bit BCD counter used to count tens of years. The counter counts from 0 to 9 with a carry over of 1 from the 1-year counter. D[3:0] RTCYL[3:0]: RTC 1-year Counter Bits These bits comprise a 4-bit BCD counter used to count units of years. The counter counts from 0 to 9 with a carry over of 1 from the month counter. This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10-year counter. V-5-24 EPSON S1C33401 TECHNICAL MANUAL V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) 0x301028: RTC Days of Week Register (pRTCDAYWEEK) Register name Address Name Bit 0301028 D31-3 - RTC days of D2 RTCWK2 (W) week register D1 RTCWK1 (pRTCDAYWEEK) D0 RTCWK0 Function reserved RTC days of week counter Setting - RTCWK[2:0] 111 110 101 100 011 010 001 000 Days of week - Saturday Friday Thursday Wednesday Tuesday Monday Sunday I Init. R/W - X X X Remarks - R/W Notes: * Data should not be read from or written to the counters while 1 is being carried over. (See Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation.") * Rewriting RTC24H (D4/0x301008) may corrupt the count data in this register. Therefore, after changing the RTC24H (D4/0x301008) setting, be sure to set up this register again. D[31:3] Reserved D[2:0] RTCWK[2:0]: RTC Days of Week Counter Bits This is a septenary counter (that counts from 0 to 6) representing days of the week. This counter counts at the same timing as the 1-day counter. The correspondence between the counter values and days of the week can be set in a program as desired. Table V.5.7.3 lists the basic correspondence. Table V.5.7.3 Correspondence between Counter Values and Days of the Week RTCWK2 RTCWK1 RTCWK0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 Days of the week Saturday Friday Thursday Wednesday Tuesday Monday Sunday (Default: indeterminate) V RTC S1C33401 TECHNICAL MANUAL EPSON V-5-25 V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK: REAL-TIME CLOCK (RTC) V.5.8 Precautions * The contents of all RTC control registers are indeterminate when power is turned on and are not initialized to specific values by initial reset. Be sure to initialize these registers in software. * While 1 is being carried over to the next-digit counter, the correct counter value may not be read out. Moreover, attempting to write to the counters or other control registers may corrupt the counter value. Therefore, do not write to the counters while 1 is being carried over. For the correct method of operation, see Section V.5.3.5, "Counter Hold and Busy Flag," and Section V.5.3.6, "Reading from and Writing to Counters in Operation." * Note that rewriting RTC24H (D4/0x301008) to switch between 12-hour mode and 24-hour mode may corrupt the count data for hours, days, months, years, or days of the week. Therefore, after changing the RTC24H (D4/ 0x301008) setting, be sure to set data in these counters back again. * Avoid the settings below that may cause timekeeping errors. - Settings exceeding the effective range Do not set count data exceeding 60 seconds, 60 minutes, 12 or 24 hours, 31 days, 12 months, or 99 years. - Settings nonexistent in the calendar Do not set nonexistent dates such as April 31 or February 29, 2005. Even if such settings are made, the counters operate normally, so that when 1 is carried over from the hour counter to the 1-day counter, the day counter counts up to the first day of the next month. (For April 31, the day counter counts up to May 1; for February 29, 2005, the day counter counts up to March 1, 2005.) * The contents of all RTC interrupt control bits are indeterminate when power is turned on, and are not initialized to specific values by initial reset. After power-on, be sure to set RTCIEN (D0/0x301004) to 0 (interrupt disabled) for preventing the occurrence of unwanted RTC interrupts. Also be sure to write 1 to RTCIRQ (D0/0x301000) to reset it. * Immediately after the OSC1 oscillator circuit is activated (as at power-on), a finite time (of about 3 seconds) is required for OSC1 oscillation to stabilize. Do not let the RTC start counting until this time elapses. V-5-26 EPSON S1C33401 TECHNICAL MANUAL I S1C33401 Technical Manual Appendix APP APPENDIX I/O MAP I/O Map 0x40140-0x4014F 0x40160-0x4017A 0x40180-0x40188 0x401E0-0x401FF 0x40260-0x402AF 0x402E8-0x402EC 0x40300-0x40302 0x40340-0x40395 0x48140-0x4815E 0x48160-0x4816C 0x48180-0x481DE 0x48200-0x48205 0x48220-0x4829C 0x48300-0x48314 0x48320-0x48334 0x48340-0x48352 0x48360-0x48372 0x48380-0x483A6 0x483C0-0x483CC 0x300000-0x300F20 0x301000-0x301028 I Prescaler ......................................................................................APP-2 8-bit Timer ....................................................................................APP-6 Clock Management Unit (1) .........................................................APP-8 Serial Interface .............................................................................APP-9 Interrupt Controller .......................................................................APP-13 Debug Unit ...................................................................................APP-22 Card Interface ..............................................................................APP-23 I/O Ports .......................................................................................APP-24 A/D Converter ..............................................................................APP-35 Watchdog Timer ...........................................................................APP-38 16-bit Timer ..................................................................................APP-40 Intelligent DMA .............................................................................APP-52 High-Speed DMA .........................................................................APP-53 High-Speed Bus Control Unit .......................................................APP-66 Memory Management Unit ...........................................................APP-68 Cache Control Unit .......................................................................APP-71 Clock Management Unit (2) .........................................................APP-73 Basic Bus Control Unit .................................................................APP-75 Extended Bus Control Unit ...........................................................APP-84 Chip ID/Pin Status Control ...........................................................APP-86 Real Time Clock ...........................................................................APP-87 Note: (B), (HW), and (W) in [Address] indicate an 8-bit register, a 16-bit register, and a 32-bit register, respectively. The meaning of the symbols described in [Init.] are listed below: 0, 1: Initial values that are set at initial reset. (However, the registers for the bus and input/output ports are not initialized at hot start.) X: Not initialized at initial reset. -: Not set in the circuit. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-1 APPENDIX I/O MAP 0x40140-0x40144 Prescaler Register name Address Bit Name 8-bit timer 4-5 0040140 (B) clock and port output clock select register (pCLKSEL_T8_45) D7 D6 D5 D4 D3 D2 - PPOTS4 PPOTS3 PPOTS2 PPOTS1 PPOTS0 reserved Port output clock select D1 D0 D7-4 D3 D2 D1 D0 P8TPCK5 P8TPCK4 - P16TON6 P16TS62 P16TS61 P16TS60 8-bit timer 5 clock select 8-bit timer 4 clock select reserved 16-bit timer 6 clock control 16-bit timer 6 clock division ratio select 0040142 16-bit timer 7 (B) clock control register (pCLKCTL_T16_7) D7-4 D3 D2 D1 D0 - P16TON7 P16TS72 P16TS71 P16TS70 reserved 16-bit timer 7 clock control 16-bit timer 7 clock division ratio select 0040143 16-bit timer 8 (B) clock control register (pCLKCTL_T16_8) D7-4 D3 D2 D1 D0 - P16TON8 P16TS82 P16TS81 P16TS80 reserved 16-bit timer 8 clock control 16-bit timer 8 clock division ratio select 0040144 16-bit timer 9 (B) clock control register (pCLKCTL_T16_9) D7-4 D3 D2 D1 D0 - P16TON9 P16TS92 P16TS91 P16TS90 reserved 16-bit timer 9 clock control 16-bit timer 9 clock division ratio select 0040141 16-bit timer 6 (B) clock control register (pCLKCTL_T16_6) APP-2 Function EPSON Setting Init. R/W - PPOTS[4:0] 1xxxx 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 1 PCLK/1 1 PCLK/1 Output clock ADC T8-5 T8-4 T8-3 T8-2 T8-1 T8-0 T16-9 T16-8 T16-7 T16-6 T16-5 T16-4 T16-3 T16-2 T16-1 T16-0 0 Divided clk. 0 Divided clk. - 1 On P16TS6[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS7[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS8[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS9[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 Remarks - 0 0 0 0 0 - 0 when being read. R/W 0 0 R/W PCLK: see 0x48366 R/W - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40145-0x40149 Prescaler Register name Address Bit Name 8-bit timer 4-5 0040145 (B) clock control register (pCLKCTL_T8_45) D7 D6 D5 D4 P8TON5 P8TS52 P8TS51 P8TS50 8-bit timer 5 clock control 8-bit timer 5 clock division ratio select D3 D2 D1 D0 P8TON4 P8TS42 P8TS41 P8TS40 8-bit timer 4 clock control 8-bit timer 4 clock division ratio select Function 0040146 (B) D7-4 D3 D2 D1 D0 - P8TPCK3 P8TPCK2 P8TPCK1 P8TPCK0 reserved 8-bit timer 3 clock selection 8-bit timer 2 clock selection 8-bit timer 1 clock selection 8-bit timer 0 clock selection 0040147 16-bit timer 0 (B) clock control register (pCLKCTL_T16_0) D7-4 D3 D2 D1 D0 - P16TON0 P16TS02 P16TS01 P16TS00 reserved 16-bit timer 0 clock control 16-bit timer 0 clock division ratio select 0040148 16-bit timer 1 (B) clock control register (pCLKCTL_T16_1) D7-4 D3 D2 D1 D0 - P16TON1 P16TS12 P16TS11 P16TS10 reserved 16-bit timer 1 clock control 16-bit timer 1 clock division ratio select 0040149 16-bit timer 2 (B) clock control register (pCLKCTL_T16_2) D7-4 D3 D2 D1 D0 - P16TON2 P16TS22 P16TS21 P16TS20 reserved 16-bit timer 2 clock control 16-bit timer 2 clock division ratio select 8-bit timer 0-3 clock select register (pCLKSEL_T8) Setting 1 On P8TS5[2:0] 111 110 101 100 011 010 001 000 1 On P8TS4[2:0] 111 110 101 100 011 010 001 000 Init. R/W 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 - 1 1 1 1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 0 0 0 0 Divided clk. Divided clk. Divided clk. Divided clk. - 1 On P16TS0[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS1[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS2[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 I Remarks 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W PCLK: see 0x48366 R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-3 APPENDIX I/O MAP 0x4014A-0x4014D Register name Address Bit Prescaler Name Function 004014A D7-4 - 16-bit timer 3 D3 P16TON3 (B) clock control D2 P16TS32 register D1 P16TS31 (pCLKCTL_T16_3) D0 P16TS30 reserved 16-bit timer 3 clock control 16-bit timer 3 clock division ratio select 004014B D7-4 - 16-bit timer 4 D3 P16TON4 (B) clock control D2 P16TS42 register D1 P16TS41 (pCLKCTL_T16_4) D0 P16TS40 reserved 16-bit timer 4 clock control 16-bit timer 4 clock division ratio select 004014C D7-4 - 16-bit timer 5 D3 P16TON5 (B) clock control D2 P16TS52 register D1 P16TS51 (pCLKCTL_T16_5) D0 P16TS50 reserved 16-bit timer 5 clock control 16-bit timer 5 clock division ratio select 8-bit timer 0-1 004014D (B) clock control register (pCLKCTL_T8_01) APP-4 D7 D6 D5 D4 P8TON1 P8TS12 P8TS11 P8TS10 8-bit timer 1 clock control 8-bit timer 1 clock division ratio select D3 D2 D1 D0 P8TON0 P8TS02 P8TS01 P8TS00 8-bit timer 0 clock control 8-bit timer 0 clock division ratio select EPSON Setting Init. R/W - 1 On P16TS3[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS4[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 - 1 On P16TS5[2:0] 111 110 101 100 011 010 001 000 1 On P8TS1[2:0] 111 110 101 100 011 010 001 000 1 On P8TS0[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/4096 PCLK/1024 PCLK/256 PCLK/64 PCLK/16 PCLK/4 PCLK/2 PCLK/1 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/1024 PCLK/512 PCLK/256 PCLK/128 PCLK/64 PCLK/32 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 Remarks - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4014E-0x4014F Prescaler Register name Address Bit Name 8-bit timer 2-3 004014E (B) clock control register (pCLKCTL_T8_23) D7 D6 D5 D4 P8TON3 P8TS32 P8TS31 P8TS30 8-bit timer 3 clock control 8-bit timer 3 clock division ratio select D3 D2 D1 D0 P8TON2 P8TS22 P8TS21 P8TS20 8-bit timer 2 clock control 8-bit timer 2 clock division ratio select D7-4 D3 D2 D1 D0 - PSONAD PSAD2 PSAD1 PSAD0 reserved A/D converter clock control A/D converter clock division ratio select 004014F A/D clock (B) control register (pCLKCTL_AD) Function Setting 1 On P8TS3[2:0] 111 110 101 100 011 010 001 000 1 On P8TS2[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 0 Off Division ratio PCLK/4096 PCLK/2048 PCLK/256 PCLK/64 PCLK/16 PCLK/8 PCLK/4 PCLK/2 - 1 On PSAD[2:0] 111 110 101 100 011 010 001 000 0 Off Division ratio PCLK/256 PCLK/128 PCLK/64 PCLK/32 PCLK/16 PCLK/8 PCLK/4 PCLK/2 Init. R/W I Remarks 0 0 0 0 R/W R/W PCLK: see 0x48366 0 0 0 0 R/W R/W PCLK: see 0x48366 - 0 0 0 0 - 0 when being read. R/W R/W PCLK: see 0x48366 APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-5 APPENDIX I/O MAP 0x40160-0x4016A Register name Address Bit 0040160 8-bit timer 0 (B) control register (pT8_CTL0) D7-4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 8-bit timer 0 reload data register (pT8_RLD0) 0040161 (B) 8-bit timer 0 counter data register (pT8_PTD0) 0040162 (B) 0040164 8-bit timer 1 (B) control register (pT8_CTL1) 8-bit timer 1 reload data register (pT8_RLD1) 0040165 (B) 8-bit timer 1 counter data register (pT8_PTD1) 0040166 (B) 0040168 8-bit timer 2 (B) control register (pT8_CTL2) 8-bit timer 2 reload data register (pT8_RLD2) 0040169 (B) 8-bit timer 2 counter data register (pT8_PTD2) 004016A (B) APP-6 8-bit Timer Name Function Setting - PTUFO0 PTOUT0 PSET0 PTRUN0 reserved 8-bit timer 0 UF signal output control 8-bit timer 0 clock output control 8-bit timer 0 preset 8-bit timer 0 Run/Stop control - RLD07 RLD06 RLD05 RLD04 RLD03 RLD02 RLD01 RLD00 8-bit timer 0 reload data RLD07 = MSB RLD00 = LSB PTD07 PTD06 PTD05 PTD04 PTD03 PTD02 PTD01 PTD00 D7-4 - D3 PTUFO1 D2 PTOUT1 D1 PSET1 D0 PTRUN1 D7 RLD17 D6 RLD16 D5 RLD15 D4 RLD14 D3 RLD13 D2 RLD12 D1 RLD11 D0 RLD10 D7 PTD17 D6 PTD16 D5 PTD15 D4 PTD14 D3 PTD13 D2 PTD12 D1 PTD11 D0 PTD10 D7-4 - D3 PTUFO2 D2 PTOUT2 D1 PSET2 D0 PTRUN2 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RLD27 RLD26 RLD25 RLD24 RLD23 RLD22 RLD21 RLD20 PTD27 PTD26 PTD25 PTD24 PTD23 PTD22 PTD21 PTD20 1 1 1 1 Off On Preset Run 0 to 255 8-bit timer 0 counter data PTD07 = MSB PTD00 = LSB reserved 8-bit timer 1 UF signal output control 8-bit timer 1 clock output control 8-bit timer 1 preset 8-bit timer 1 Run/Stop control - 1 1 1 1 Off On Preset Run 8-bit timer 1 reload data RLD17 = MSB RLD10 = LSB 8-bit timer 2 reload data RLD27 = MSB RLD20 = LSB 8-bit timer 2 counter data PTD27 = MSB PTD20 = LSB EPSON 0 On 0 Off 0 Invalid 0 Stop 0 to 255 0 to 255 8-bit timer 1 counter data PTD17 = MSB PTD10 = LSB reserved 8-bit timer 2 UF signal output control 8-bit timer 2 clock output control 8-bit timer 2 preset 8-bit timer 2 Run/Stop control 0 On 0 Off 0 Invalid 0 Stop 0 to 255 - 1 1 1 1 Off On Preset Run 0 On 0 Off 0 Invalid 0 Stop 0 to 255 0 to 255 Init. R/W Remarks - 0 0 - 0 - 0 when being read. R/W R/W W 0 when being read. R/W X X X X X X X X R/W X X X X X X X X - 0 0 - 0 R - 0 when being read. R/W R/W W 0 when being read. R/W X X X X X X X X X X X X X X X X - 0 0 - 0 R/W X X X X X X X X X X X X X X X X R/W R - 0 when being read. R/W R/W W 0 when being read. R/W R S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4016C-0x4017A Register name Address 8-bit Timer Name Bit 004016C D7-4 - 8-bit timer 3 D3 PTUFO3 (B) control register D2 PTOUT3 (pT8_CTL3) D1 PSET3 D0 PTRUN3 8-bit timer 3 reload data register (pT8_RLD3) 004016D (B) 8-bit timer 3 counter data register (pT8_PTD3) 004016E (B) 0040174 8-bit timer 4 (B) control register (pT8_CTL4) 8-bit timer 4 reload data register (pT8_RLD4) 0040175 (B) 8-bit timer 4 counter data register (pT8_PTD4) 0040176 (B) 0040178 8-bit timer 5 (B) control register (pT8_CTL5) 8-bit timer 5 reload data register (pT8_RLD5) 0040179 (B) 8-bit timer 5 counter data register (pT8_PTD5) 004017A (B) D7 D6 D5 D4 D3 D2 D1 D0 RLD37 RLD36 RLD35 RLD34 RLD33 RLD32 RLD31 RLD30 PTD37 PTD36 PTD35 PTD34 PTD33 PTD32 PTD31 PTD30 D7-4 - D3 PTUFO4 D2 PTOUT4 D1 PSET4 D0 PTRUN4 D7 RLD47 D6 RLD46 D5 RLD45 D4 RLD44 D3 RLD43 D2 RLD42 D1 RLD41 D0 RLD40 D7 PTD47 D6 PTD46 D5 PTD45 D4 PTD44 D3 PTD43 D2 PTD42 D1 PTD41 D0 PTD40 D7-4 - D3 PTUFO5 D2 PTOUT5 D1 PSET5 D0 PTRUN5 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RLD57 RLD56 RLD55 RLD54 RLD53 RLD52 RLD51 RLD50 PTD57 PTD56 PTD55 PTD54 PTD53 PTD52 PTD51 PTD50 Function Setting reserved 8-bit timer 3 UF signal output control 8-bit timer 3 clock output control 8-bit timer 3 preset 8-bit timer 3 Run/Stop control - 1 1 1 1 Off On Preset Run 8-bit timer 3 reload data RLD37 = MSB RLD30 = LSB 0 to 255 8-bit timer 3 counter data PTD37 = MSB PTD30 = LSB reserved 8-bit timer 4 UF signal output control 8-bit timer 4 clock output control 8-bit timer 4 preset 8-bit timer 4 Run/Stop control - 1 1 1 1 Off On Preset Run 8-bit timer 4 reload data RLD47 = MSB RLD40 = LSB 8-bit timer 5 reload data RLD57 = MSB RLD50 = LSB 8-bit timer 5 counter data PTD57 = MSB PTD50 = LSB 0 On 0 Off 0 Invalid 0 Stop 0 to 255 0 to 255 8-bit timer 4 counter data PTD47 = MSB PTD40 = LSB reserved 8-bit timer 5 UF signal output control 8-bit timer 5 clock output control 8-bit timer 5 preset 8-bit timer 5 Run/Stop control 0 On 0 Off 0 Invalid 0 Stop 0 to 255 - 1 1 1 1 Off On Preset Run 0 On 0 Off 0 Invalid 0 Stop 0 to 255 0 to 255 Init. R/W Remarks - 0 0 - 0 - 0 when being read. R/W R/W W 0 when being read. R/W X X X X X X X X R/W X X X X X X X X - 0 0 - 0 R - 0 when being read. R/W R/W W 0 when being read. R/W X X X X X X X X R/W X X X X X X X X - 0 0 - 0 R X X X X X X X X X X X X X X X X I - 0 when being read. R/W R/W W 0 when being read. R/W R/W R APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-7 APPENDIX I/O MAP 0x40180-0x40188 Register name Address Peripheral clock control register 1 (pCMU1 _CLKCNTL_0) 0040180 (B) Protected Peripheral clock control register 2 (pCMU1 _CLKCNTL_1) Protected 0040181 (B) PLL control register 1 (pCMU1_PLL _CNTL0) 0040184 (B) Clock Management Unit Bit Name Function D7 D6 D5 D4 D3 D2 D1 D0 D7-5 D4 D3 D2 D1 D0 PSCCLK ADCCLK - SIOCLK T16CLK T8CLK - ITCCLK - INTCLK WDTCLK CARDCLK - POT1CLK Prescaler clock control A/D converter clock control reserved Serial I/F clock control 16-bit timer clock control 8-bit timer clock control reserved ITC clock control reserved Interrupt generation clock control Watchdog timer clock control Card I/F clock control reserved Port clock control D7 D6 D5 D4 PLLN3 PLLN2 PLLN1 PLLN0 PLL multiplication rate setup D3 D2 PLLV1 PLLV0 PLL V-divider setup D1 D0 D7 D6 D5 D4 - reserved PLLPOWR PLL on/off control PLLVC3 PLL VCO Kv setup PLLVC2 PLLVC1 PLLVC0 Protected PLL control register 2 (pCMU1_PLL _CNTL1) 0040185 (B) PLL control register 3 (pCMU1_PLL _CNTL2) 0040186 (B) Protected 0040187 SS macro (B) control register 1 (pCMU1_SS_CNTL0) Protected SS macro 0040188 control (B) register 2 (pCMU1_SS_CNTL1) Protected APP-8 D0 D7 D6 D5 D4 D3 D2 D1 D0 On On 1 On On On 1 On PLLRS3 PLLRS2 PLLRS1 PLLRS0 PLLCS1 PLLCS0 PLLBYP PLLCP4 PLLCP3 PLLCP2 PLLCP1 PLLCP0 - PLL LPF resistance setup SSMCON SSMCITM3 SSMCITM2 SSMCITM1 SSMCITM0 SSMCIDT3 SSMCIDT2 SSMCIDT1 SSMCIDT0 SS macro On/Off SS macro interval timer (ITM) setting PLL LPF capacitance setup PLL bypass mode setup PLL Charge Pump current setup 0 0 0 0 0 0 0 0 Init. R/W Off Off 0 Off Off Off 0 Off - 1 On 1 On 1 On 1 1 1 On PLLN[3:0] 1111 1110 : 0001 0000 PLLV[1:0] 11 10 01 00 1 On Protected D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-1 Setting 1 1 1 1 1 1 1 1 0 Off 0 Off 0 Off 0 0 0 Off Multiplication rate x16 x15 : x2 x1 W 8 4 2 Not allowed - 0 Off PLLVC[3:0] fVCO [MHz] 1000 360 < fVCO 400 0111 320 < fVCO 360 0110 280 < fVCO 320 0101 240 < fVCO 280 0100 200 < fVCO 240 0011 160 < fVCO 200 0010 120 < fVCO 160 0001 100 fVCO 120 Other Not allowed PLLRS[3:0] fREFCK [MHz] 1010 5 fREFCK < 20 1000 20 fREFCK 150 Other Not allowed Fixed at "00" (default) Fixed at "0" (default) Fixed at "10000" (default) reserved - SS macro maximum frequency change width setting EPSON 1 On 0 Off 0 to 0xF 0 to 0xF Remarks 1 1 1 1 1 1 1 1 - 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 R/W 0 1 R/W - 0 0 0 0 1 - 0 when being read. R/W R/W 1 0 0 0 0 0 0 1 0 0 0 0 - R/W 0 1 1 1 1 0 0 0 0 R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x401E0-0x401E5 Register name Address Bit Serial I/F Ch.0 transmit data register (pFSIF0_TXD) 00401E0 (B) Serial I/F Ch.0 receive data register (pFSIF0_RXD) 00401E1 (B) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.0 00401E2 (B) status register (pFSIF0_STATUS) Serial I/F Ch.0 00401E3 (B) control register (pFSIF0_CTL) Serial I/F Ch.0 IrDA register (pFSIF0_IRDA) Serial I/F Ch.1 transmit data register (pFSIF1_TXD) 00401E4 (B) 00401E5 (B) Serial Interface Name Function Setting Init. R/W TXD07 TXD06 TXD05 TXD04 TXD03 TXD02 TXD01 TXD00 Serial I/F Ch.0 transmit data TXD07(06) = MSB TXD00 = LSB 0x0 to 0xFF(0x7F) X X X X X X X X Serial I/F Ch.0 receive data RXD07(06) = MSB RXD00 = LSB 0x0 to 0xFF(0x7F) D7 D6 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 RXD0NUM1 RXD0NUM0 X X X X X X X X 0 0 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TEND0 FER0 PER0 OER0 TDBE0 RDBF0 TXEN0 RXEN0 EPR0 PMD0 STPB0 SSCK0 SMD01 SMD00 Ch.0 transmit-completion flag Ch.0 framing error flag Ch.0 parity error flag Ch.0 overrun error flag Ch.0 transmit data buffer empty Ch.0 receive data buffer full Ch.0 transmit enable Ch.0 receive enable Ch.0 parity enable Ch.0 parity mode select Ch.0 stop bit select Ch.0 input clock select Ch.0 transfer mode select D7 D6 D5 Number of Ch.0 receive data in FIFO RXD0NUM[1:0] Number of data 1 1 4 1 0 3 0 1 2 0 0 1 or 0 1 Transmitting 0 End 1 Error 0 Normal 0 Normal 1 Error 1 Error 0 Normal 1 Empty 0 Not empty 0 Not full 1 Full 1 Enabled 0 Disabled 0 Disabled 1 Enabled 1 With parity 0 No parity 1 Odd 0 Even 0 1 bit 1 2 bits 1 #SCLK0 0 Internal clock SMD0[1:0] Transfer mode 11 8-bit asynchronous 10 7-bit asynchronous 01 Clock sync. Slave 00 Clock sync. Master Remarks R/W 7-bit asynchronous mode does not use TXD07. R 7-bit asynchronous mode does not use RXD07 (fixed at 0). R 0 0 0 0 1 0 R R/W Reset by writing 0. R/W R/W R R 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W SRDYCTL0 Ch.0 #SRDY control FIFOINT01 Ch.0 receive buffer full interrupt FIFOINT00 timing 0 0 0 R/W Writing is disabled R/W when SIOADV (D0/0x401FF) = "0". D4 D3 D2 D1 D0 DIVMD0 IRTL0 IRRL0 IRMD01 IRMD00 X X X X X R/W R/W Valid only in R/W asynchronous mode. R/W D7 D6 D5 D4 D3 D2 D1 D0 TXD17 TXD16 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 X X X X X X X X R/W 7-bit asynchronous mode does not use TXD17. 1 High mask 0 Normal FIFOINT0[1:0] Receive level 11 4 10 3 01 2 00 1 Ch.0 async. clock division ratio 1 1/8 0 1/16 Ch.0 IrDA I/F output logic inversion 1 Inverted 0 Direct Ch.0 IrDA I/F input logic inversion 1 Inverted 0 Direct Ch.0 interface mode select IRMD0[1:0] I/F mode 11 reserved 10 IrDA 1.0 01 reserved 00 General I/F 0x0 to 0xFF(0x7F) Serial I/F Ch.1 transmit data TXD17(16) = MSB TXD10 = LSB I APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-9 APPENDIX I/O MAP 0x401E6-0x401F1 Serial Interface Register name Address Bit Name 00401E6 (B) D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1 receive data RXD17(16) = MSB RXD10 = LSB Serial I/F Ch.1 00401E7 (B) status register (pFSIF1_STATUS) D7 D6 RXD17 RXD16 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD1NUM1 RXD1NUM0 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TEND1 FER1 PER1 OER1 TDBE1 RDBF1 TXEN1 RXEN1 EPR1 PMD1 STPB1 SSCK1 SMD11 SMD10 Ch.1 transmit-completion flag Ch.1 framing error flag Ch.1 parity error flag Ch.1 overrun error flag Ch.1 transmit data buffer empty Ch.1 receive data buffer full Ch.1 transmit enable Ch.1 receive enable Ch.1 parity enable Ch.1 parity mode select Ch.1 stop bit select Ch.1 input clock select Ch.1 transfer mode select D7 D6 D5 Serial I/F Ch.1 receive data register (pFSIF1_RXD) Serial I/F Ch.1 00401E8 (B) control register (pFSIF1_CTL) Serial I/F Ch.1 IrDA register (pFSIF1_IRDA) 00401E9 (B) Serial I/F Ch.2 transmit data register (pFSIF2_TXD) 00401F0 (B) Serial I/F Ch.2 receive data register (pFSIF2_RXD) 00401F1 (B) APP-10 Function Number of Ch.1 receive data in FIFO Setting Init. R/W 0x0 to 0xFF(0x7F) RXD1NUM[1:0] Number of data 1 1 4 1 0 3 0 1 2 0 0 1 or 0 1 Transmitting 0 End 1 Error 0 Normal 0 Normal 1 Error 1 Error 0 Normal 1 Empty 0 Not empty 1 Full 0 Not full 1 Enabled 0 Disabled 0 Disabled 1 Enabled 1 With parity 0 No parity 1 Odd 0 Even 0 1 bit 1 2 bits 1 #SCLK1 0 Internal clock SMD1[1:0] Transfer mode 8-bit asynchronous 11 7-bit asynchronous 10 Clock sync. Slave 01 Clock sync. Master 00 X X X X X X X X 0 0 R Remarks 7-bit asynchronous mode does not use RXD17 (fixed at 0). R 0 0 0 0 1 0 R R/W Reset by writing 0. R/W R/W R R 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W SRDYCTL1 Ch.1 #SRDY control FIFOINT11 Ch.1 receive buffer full interrupt FIFOINT10 timing 0 0 0 R/W Writing is disabled R/W when SIOADV (D0/0x401FF) = "0". D4 D3 D2 D1 D0 DIVMD1 IRTL1 IRRL1 IRMD11 IRMD10 X X X X X R/W R/W Valid only in R/W asynchronous mode. R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TXD27 TXD26 TXD25 TXD24 TXD23 TXD22 TXD21 TXD20 X X X X X X X X X X X X X X X X R/W 7-bit asynchronous mode does not use TXD27. RXD27 RXD26 RXD25 RXD24 RXD23 RXD22 RXD21 RXD20 1 High mask 0 Normal FIFOINT1[1:0] Receive level 11 4 10 3 01 2 00 1 Ch.1 async. clock division ratio 0 1/16 1 1/8 Ch.1 IrDA I/F output logic inversion 1 Inverted 0 Direct Ch.1 IrDA I/F input logic inversion 1 Inverted 0 Direct Ch.1 interface mode select IRMD1[1:0] I/F mode reserved 11 IrDA 1.0 10 reserved 01 General I/F 00 0x0 to 0xFF(0x7F) Serial I/F Ch.2 transmit data TXD27(26) = MSB TXD20 = LSB Serial I/F Ch.2 receive data RXD27(26) = MSB RXD20 = LSB EPSON 0x0 to 0xFF(0x7F) R 7-bit asynchronous mode does not use RXD27 (fixed at 0). S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x401F2-0x401F7 Serial Interface Name Register name Address Bit Serial I/F Ch.2 00401F2 (B) status register (pFSIF2_STATUS) D7 D6 RXD2NUM1 Number of Ch.2 receive data RXD2NUM0 in FIFO D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TEND2 FER2 PER2 OER2 TDBE2 RDBF2 TXEN2 RXEN2 EPR2 PMD2 STPB2 SSCK2 SMD21 SMD20 D7 D6 D5 Serial I/F Ch.2 00401F3 (B) control register (pFSIF2_CTL) Serial I/F Ch.2 IrDA register (pFSIF2_IRDA) 00401F4 (B) Ch.2 transmit-completion flag Ch.2 framing error flag Ch.2 parity error flag Ch.2 overrun error flag Ch.2 transmit data buffer empty Ch.2 receive data buffer full Ch.2 transmit enable Ch.2 receive enable Ch.2 parity enable Ch.2 parity mode select Ch.2 stop bit select Ch.2 input clock select Ch.2 transfer mode select Setting RXD2NUM[1:0] Number of data 1 1 4 1 0 3 0 1 2 0 0 1 or 0 1 Transmitting 0 End 1 Error 0 Normal 0 Normal 1 Error 1 Error 0 Normal 1 Empty 0 Not empty 1 Full 0 Not full 1 Enabled 0 Disabled 0 Disabled 1 Enabled 1 With parity 0 No parity 1 Odd 0 Even 0 1 bit 1 2 bits 1 #SCLK2 0 Internal clock SMD2[1:0] Transfer mode 11 8-bit asynchronous 10 7-bit asynchronous 01 Clock sync. Slave 00 Clock sync. Master Init. R/W 0 0 Remarks R 0 0 0 0 1 0 R R/W Reset by writing 0. R/W R/W R R 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W SRDYCTL2 Ch.2 #SRDY control FIFOINT21 Ch.2 receive buffer full interrupt FIFOINT20 timing 0 0 0 R/W Writing is disabled R/W when SIOADV (D0/0x401FF) = "0". D4 D3 D2 D1 D0 DIVMD2 IRTL2 IRRL2 IRMD21 IRMD20 X X X X X R/W R/W Valid only in R/W asynchronous mode. R/W X X X X X X X X X X X X X X X X 0 0 R/W 7-bit asynchronous mode does not use TXD37. 0 0 0 0 1 0 R R/W Reset by writing 0. R/W R/W R R Serial I/F Ch.3 transmit data register (pFSIF3_TXD) 00401F5 (B) D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.3 receive data register (pFSIF3_RXD) 00401F6 (B) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 TXD37 TXD36 TXD35 TXD34 TXD33 TXD32 TXD31 TXD30 RXD37 RXD36 RXD35 RXD34 RXD33 RXD32 RXD31 RXD30 RXD3NUM1 RXD3NUM0 D5 D4 D3 D2 D1 D0 TEND3 FER3 PER3 OER3 TDBE3 RDBF3 Serial I/F Ch.3 00401F7 (B) status register (pFSIF3_STATUS) Function 1 High mask 0 Normal FIFOINT2[1:0] Receive level 11 4 10 3 01 2 00 1 Ch.2 async. clock division ratio 1 1/8 0 1/16 Ch.2 IrDA I/F output logic inversion 1 Inverted 0 Direct Ch.2 IrDA I/F input logic inversion 1 Inverted 0 Direct Ch.2 interface mode select IRMD2[1:0] I/F mode 11 reserved 10 IrDA 1.0 01 reserved 00 General I/F 0x0 to 0xFF(0x7F) Serial I/F Ch.3 transmit data TXD37(36) = MSB TXD30 = LSB Serial I/F Ch.3 receive data RXD37(36) = MSB RXD30 = LSB Number of Ch.3 receive data in FIFO Ch.3 transmit-completion flag Ch.3 framing error flag Ch.3 parity error flag Ch.3 overrun error flag Ch.3 transmit data buffer empty Ch.3 receive data buffer full 0x0 to 0xFF(0x7F) RXD3NUM[1:0] Number of data 1 1 4 1 0 3 0 1 2 0 0 1 or 0 1 Transmitting 0 End 1 Error 0 Normal 0 Normal 1 Error 1 Error 0 Normal 1 Empty 0 Not empty 0 Not full 1 Full I R 7-bit asynchronous mode does not use RXD37 (fixed at 0). R APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-11 APPENDIX I/O MAP 0x401F8-0x401FF Serial Interface Name Register name Address Bit Serial I/F Ch.3 00401F8 (B) control register (pFSIF3_CTL) D7 D6 D5 D4 D3 D2 D1 D0 TXEN3 RXEN3 EPR3 PMD3 STPB3 SSCK3 SMD31 SMD30 00401F9 (B) D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.3 IrDA register (pFSIF3_IRDA) Setting Init. R/W Remarks 0 0 X X X X X X R/W R/W R/W Valid only in R/W asynchronous mode. R/W R/W R/W SRDYCTL3 Ch.3 #SRDY control FIFOINT31 Ch.3 receive buffer full interrupt FIFOINT30 timing 0 0 0 R/W Writing is disabled R/W when SIOADV (D0/0x401FF) = "0". DIVMD3 IRTL3 IRRL3 IRMD31 IRMD30 X X X X X R/W R/W Valid only in R/W asynchronous mode. R/W 00401FF D7-1 - Serial I/F (B) STD/ADV mode D0 SIOADV select register (pFSIF_ADV) APP-12 Function Ch.3 transmit enable Ch.3 receive enable Ch.3 parity enable Ch.3 parity mode select Ch.3 stop bit select Ch.3 input clock select Ch.3 transfer mode select 1 Enabled 0 Disabled 0 Disabled 1 Enabled 1 With parity 0 No parity 1 Odd 0 Even 0 1 bit 1 2 bits 1 #SCLK3 0 Internal clock SMD3[1:0] Transfer mode 8-bit asynchronous 11 7-bit asynchronous 10 Clock sync. Slave 01 Clock sync. Master 00 1 High mask 0 Normal FIFOINT3[1:0] Receive level 11 4 10 3 01 2 00 1 Ch.3 async. clock division ratio 0 1/16 1 1/8 Ch.3 IrDA I/F output logic inversion 1 Inverted 0 Direct Ch.3 IrDA I/F input logic inversion 1 Inverted 0 Direct Ch.3 interface mode select IRMD3[1:0] I/F mode reserved 11 IrDA 1.0 10 reserved 01 General I/F 00 reserved - Standard mode/advanced mode select EPSON 1 Advanced mode 0 Standard mode - - 0 R/W Writing 1 not allowed. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40260-0x40267 Register name Address Bit Port input 0-1 0040260 (B) interrupt priority register (pINT_PR01L) D7 D6 D5 D4 D3 D2 D1 D0 Port input 2-3 0040261 (B) interrupt priority register (pINT_PR23L) 0040262 Key input (B) interrupt priority register (pINT_PK01L) HSDMA Ch.0-1 0040263 (B) interrupt priority register (pINT_PHSD01L) HSDMA Ch.2-3 0040264 (B) interrupt priority register (pINT_PHSD23L) IDMA interrupt 0040265 (B) priority register (pINT_PDM) 16-bit timer 0-1 0040266 (B) interrupt priority register (pINT_P16T01) 16-bit timer 2-3 0040267 (B) interrupt priority register (pINT_P16T23) Interrupt Controller Name Function Setting D7 D6 D5 D4 D3 D2 D1 D0 - PP1L2 PP1L1 PP1L0 - PP0L2 PP0L1 PP0L0 - PP3L2 PP3L1 PP3L0 - PP2L2 PP2L1 PP2L0 D7 D6 D5 D4 D3 D2 D1 D0 - PK1L2 PK1L1 PK1L0 - PK0L2 PK0L1 PK0L0 reserved Key input 1 interrupt level - 0 to 7 reserved Key input 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PHSD1L2 PHSD1L1 PHSD1L0 - PHSD0L2 PHSD0L1 PHSD0L0 reserved HSDMA Ch.1 interrupt level - 0 to 7 reserved HSDMA Ch.0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 D7-3 D2 D1 D0 - PHSD3L2 PHSD3L1 PHSD3L0 - PHSD2L2 PHSD2L1 PHSD2L0 - PDM2 PDM1 PDM0 reserved HSDMA Ch.3 interrupt level - 0 to 7 reserved HSDMA Ch.2 interrupt level - 0 to 7 reserved IDMA interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T12 P16T11 P16T10 - P16T02 P16T01 P16T00 reserved 16-bit timer 1 interrupt level - 0 to 7 reserved 16-bit timer 0 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T32 P16T31 P16T30 - P16T22 P16T21 P16T20 reserved 16-bit timer 3 interrupt level - 0 to 7 reserved 16-bit timer 2 interrupt level - 0 to 7 reserved Port input 1 interrupt level - 0 to 7 reserved Port input 0 interrupt level - 0 to 7 reserved Port input 3 interrupt level - 0 to 7 reserved Port input 2 interrupt level - 0 to 7 Init. R/W - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X I Remarks - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-13 APPENDIX I/O MAP 0x40268-0x40271 Register name Address Bit 16-bit timer 4-5 0040268 (B) interrupt priority register (pINT_P16T45) D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Controller Name - P16T52 P16T51 P16T50 - P16T42 P16T41 P16T40 Port input 4-5 004026C (B) interrupt priority register (pINT_PR45L) reserved 16-bit timer 4 interrupt level - 0 to 7 reserved Serial interface Ch.0 interrupt level - 0 to 7 reserved 8-bit timer 0-5 interrupt level - 0 to 7 reserved A/D converter interrupt level - 0 to 7 reserved Serial interface Ch.1 interrupt level - 0 to 7 reserved RTC interrupt level - 0 to 7 - PP5L2 PP5L1 PP5L0 - PP4L2 PP4L1 PP4L0 reserved Port input 5 interrupt level - 0 to 7 reserved Port input 4 interrupt level - 0 to 7 Port input 6-7 004026D (B) interrupt priority register (pINT_PR67L) - PP7L2 PP7L1 PP7L0 - PP6L2 PP6L1 PP6L0 - PSIO32 PSIO31 PSIO30 - PSIO22 PSIO21 PSIO20 - EK1 EK0 EP3 EP2 EP1 EP0 reserved Port input 7 interrupt level - 0 to 7 reserved Port input 6 interrupt level - 0 to 7 reserved Serial interface Ch.3 interrupt level - 0 to 7 reserved Serial interface Ch.2 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 004026E Serial I/F D6 (B) Ch.2-3 D5 interrupt D4 priority register D3 (pINT_PSI0203) D2 D1 D0 0040270 D7-6 Key input, D5 (B) port input 0-3 D4 interrupt D3 enable register D2 (pINT_EK01_EP03) D1 D0 DMA interrupt 0040271 D7-5 D4 (B) enable register D3 (pINT_EDMA) D2 D1 D0 APP-14 Setting - 0 to 7 - PSIO02 PSIO01 PSIO00 - P8TM2 P8TM1 P8TM0 D7 - Serial I/F Ch.1, 004026A D6 PAD2 (B) A/D interrupt D5 PAD1 priority register D4 PAD0 (pINT_PSI01_PAD) D3 - D2 PSIO12 D1 PSIO11 D0 PSIO10 RTC interrupt 004026B D7-3 - D2 PCTM2 (B) priority register D1 PCTM1 (pINT_PCTM) D0 PCTM0 0040269 8-bit timer, (B) serial I/F Ch.0 interrupt priority register (pINT_P8T_PSI00) Function reserved 16-bit timer 5 interrupt level - EIDMA EHDM3 EHDM2 EHDM1 EHDM0 reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 reserved IDMA HSDMA Ch.3 HSDMA Ch.2 HSDMA Ch.1 HSDMA Ch.0 - 1 Enabled 0 Disabled - 1 Enabled EPSON 0 Disabled Init. R/W - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X - 0 0 0 0 0 0 - 0 0 0 0 0 Remarks - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - Writing 1 not allowed. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40272-0x40281 Interrupt Controller Name Register name Address Bit 16-bit timer 0-1 0040272 (B) interrupt enable register (pINT_E16T01) D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7-4 D3 D2 D1 D0 E16TC1 E16TU1 - E16TC0 E16TU0 - E16TC3 E16TU3 - E16TC2 E16TU2 - E16TC5 E16TU5 - E16TC4 E16TU4 - - E8TU3 E8TU2 E8TU1 E8TU0 D7-6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-2 - ESTX1 ESRX1 ESERR1 ESTX0 ESRX0 ESERR0 - EP7 EP6 EP5 EP4 ECTM EADE EADC - 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error reserved Port input 7 Port input 6 Port input 5 Port input 4 RTC A/D conversion completion A/D upper/lower limit reserved E8TU5 E8TU4 8-bit timer 5 underflow 8-bit timer 4 underflow - ESTX3 ESRX3 ESERR3 ESTX2 ESRX2 ESERR2 - FK1 FK0 FP3 FP2 FP1 FP0 - FIDMA FHDM3 FHDM2 FHDM1 FHDM0 reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.3 receive error SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full SIF Ch.2 receive error reserved Key input 1 Key input 0 Port input 3 Port input 2 Port input 1 Port input 0 reserved IDMA HSDMA Ch.3 HSDMA Ch.2 HSDMA Ch.1 HSDMA Ch.0 16-bit timer 2-3 0040273 (B) interrupt enable register (pINT_E16T23) 16-bit timer 4-5 0040274 (B) interrupt enable register (pINT_E16T45) 8-bit timer 0-3 0040275 (B) interrupt enable register (pINT_E8T03) 0040276 Serial I/F (B) Ch.0-1 interrupt enable register (pINT_ESIF01) Port input 4-7, 0040277 (B) RTC, A/D interrupt enable register (pINT_EP47_ECT _EAD) 8-bit timer 4-5 0040278 (B) interrupt enable register (pINT_E8T45) 0040279 Serial I/F (B) Ch.2-3 interrupt enable register (pINT_ESIF23) 0040280 Key input, (B) port input 0-3 interrupt cause flag register (pINT_FK01_FP03) DMA interrupt cause flag register (pINT_FDMA) 0040281 (B) D1 D0 D7-6 D5 D4 D3 D2 D1 D0 D7-6 D5 D4 D3 D2 D1 D0 D7-5 D4 D3 D2 D1 D0 Function Setting 1 Enabled Init. R/W 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred Remarks 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - - 0 when being read. R/W R/W R/W R/W R/W R/W 0 0 R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W - X X X X X X - X X X X X I - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-15 APPENDIX I/O MAP 0x40282-0x40291 Register name Address Bit 16-bit timer 0-1 0040282 (B) interrupt cause flag register (pINT_F16T01) D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7-4 D3 D2 D1 D0 D7-6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-2 16-bit timer 2-3 0040283 (B) interrupt cause flag register (pINT_F16T23) 16-bit timer 4-5 0040284 (B) interrupt cause flag register (pINT_F16T45) 8-bit timer 0-3 0040285 (B) interrupt cause flag register (pINT_F8T03) 0040286 Serial I/F (B) Ch.0-1 interrupt cause flag register (pINT_FSIF01) Port input 4-7, 0040287 (B) RTC, A/D interrupt cause flag register (pINT_FP47_FCT _FAD) 8-bit timer 4-5 0040288 (B) interrupt cause flag register (pINT_F8T45) 0040289 Serial I/F (B) Ch.2-3 interrupt cause flag register (pINT_FSIF23) Port input 0-3, 0040290 (B) HSDMA Ch.0-1, 16-bit timer 0 IDMA request register (pIDMAREQ_RP03 _RHS_R16T0) 16-bit timer 1-4 0040291 (B) IDMA request register (pIDMAREQ _R16T14) APP-16 D1 D0 D7-6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Controller Name Function F16TC1 F16TU1 - F16TC0 F16TU0 - F16TC3 F16TU3 - F16TC2 F16TU2 - F16TC5 F16TU5 - F16TC4 F16TU4 - - F8TU3 F8TU2 F8TU1 F8TU0 - FSTX1 FSRX1 FSERR1 FSTX0 FSRX0 FSERR0 - FP7 FP6 FP5 FP4 FCTM FADE FADC - 16-bit timer 1 comparison A 16-bit timer 1 comparison B reserved 16-bit timer 0 comparison A 16-bit timer 0 comparison B reserved 16-bit timer 3 comparison A 16-bit timer 3 comparison B reserved 16-bit timer 2 comparison A 16-bit timer 2 comparison B reserved 16-bit timer 5 comparison A 16-bit timer 5 comparison B reserved 16-bit timer 4 comparison A 16-bit timer 4 comparison B reserved reserved 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow reserved SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full SIF Ch.1 receive error SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full SIF Ch.0 receive error reserved Port input 7 Port input 6 Port input 5 Port input 4 RTC A/D conversion completion A/D upper/lower limit reserved F8TU5 F8TU4 8-bit timer 5 underflow 8-bit timer 4 underflow - FSTX3 FSRX3 FSERR3 FSTX2 FSRX2 FSERR2 R16TC0 R16TU0 RHDM1 RHDM0 RP3 RP2 RP1 RP0 R16TC4 R16TU4 R16TC3 R16TU3 R16TC2 R16TU2 R16TC1 R16TU1 reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.3 receive error SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full SIF Ch.2 receive error 16-bit timer 0 comparison A 16-bit timer 0 comparison B HSDMA Ch.1 HSDMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B EPSON Setting 1 Occurred Init. R/W 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request Remarks X X - X X - X X - X X - X X - X X - R/W R/W - R/W R/W - R/W R/W - R/W R/W - R/W R/W - R/W R/W - - X X X X - 0 when being read. R/W R/W R/W R/W - X X X X X X - 0 when being read. R/W R/W R/W R/W R/W R/W - X X X X X X X - - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. X X R/W R/W - X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40292-0x40297 Register name Address Bit 0040292 16-bit timer 5, (B) 8-bit timer 0-3, serial I/F Ch.0 IDMA request register (pIDMAREQ_R16T5 _R8T_RSIF0) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial I/F Ch.1, 0040293 (B) A/D, port input 4-7 IDMA request register (pIDMAREQ_RSIF1 _RAD_RP47) Port input 0-3, 0040294 (B) HSDMA Ch.0-1, 16-bit timer 0 IDMA enable register (pIDMAEN_DEP03 _DEHS_DE16T0) 16-bit timer 1-4 0040295 (B) IDMA enable register (pIDMAEN _DE16T14) 0040296 16-bit timer 5, (B) 8-bit timer 0-3, serial I/F Ch.0 IDMA enable register (pIDMAEN_DE16T5 _DE8T_DESIF0) Serial I/F Ch.1, 0040297 (B) A/D, port input 4-7 IDMA enable register (pIDMAEN_DESIF1 _DEAD_DEP47) Interrupt Controller Name RSTX0 RSRX0 R8TU3 R8TU2 R8TU1 R8TU0 R16TC5 R16TU5 RP7 RP6 RP5 RP4 - RADE RSTX1 RSRX1 DE16TC0 DE16TU0 DEHDM1 DEHDM0 DEP3 DEP2 DEP1 DEP0 DE16TC4 DE16TU4 DE16TC3 DE16TU3 DE16TC2 DE16TU2 DE16TC1 DE16TU1 DESTX0 DESRX0 DE8TU3 DE8TU2 DE8TU1 DE8TU0 DE16TC5 DE16TU5 DEP7 DEP6 DEP5 DEP4 - DEADE DESTX1 DESRX1 Function SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D conversion completion SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full 16-bit timer 0 comparison A 16-bit timer 0 comparison B HSDMA Ch.1 HSDMA Ch.0 Port input 3 Port input 2 Port input 1 Port input 0 16-bit timer 4 comparison A 16-bit timer 4 comparison B 16-bit timer 3 comparison A 16-bit timer 3 comparison B 16-bit timer 2 comparison A 16-bit timer 2 comparison B 16-bit timer 1 comparison A 16-bit timer 1 comparison B SIF Ch.0 transmit buffer empty SIF Ch.0 receive buffer full 8-bit timer 3 underflow 8-bit timer 2 underflow 8-bit timer 1 underflow 8-bit timer 0 underflow 16-bit timer 5 comparison A 16-bit timer 5 comparison B Port input 7 Port input 6 Port input 5 Port input 4 reserved A/D conversion completion SIF Ch.1 transmit buffer empty SIF Ch.1 receive buffer full Setting 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request - 1 IDMA request 0 Interrupt request 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled - 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-17 APPENDIX I/O MAP 0x40298-0x4029A Interrupt Controller Register name Address Bit Name HSDMA Ch.0-1 0040298 (B) trigger set-up register (pHSDMA_HTGR1) D7 D6 D5 D4 HSD1S3 HSD1S2 HSD1S1 HSD1S0 HSDMA Ch.1 trigger set-up D3 D2 D1 D0 HSD0S3 HSD0S2 HSD0S1 HSD0S0 HSDMA Ch.0 trigger set-up D7 D6 D5 D4 HSD3S3 HSD3S2 HSD3S1 HSD3S0 HSDMA Ch.3 trigger set-up D3 D2 D1 D0 HSD2S3 HSD2S2 HSD2S1 HSD2S0 HSDMA Ch.2 trigger set-up HSDMA Ch.2-3 0040299 (B) trigger set-up register (pHSDMA_HTGR2) 004029A D7-4 - HSDMA D3 HST3 (B) software trigger register D2 HST2 (pHSDMA D1 HST1 _HSOFTTGR) D0 HST0 APP-18 Function reserved HSDMA Ch.3 software trigger HSDMA Ch.2 software trigger HSDMA Ch.1 software trigger HSDMA Ch.0 software trigger EPSON Setting 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E 0 1 2 3 4 5 6 7 8 9 A B C D E Init. R/W Software trigger #DMAREQ1 input (falling edge) #DMAREQ1 input (rising edge) Port 1 input Port 5 input 8-bit timer 1 underflow 16-bit timer 1 compare B 16-bit timer 1 compare A 16-bit timer 5 compare B 16-bit timer 5 compare A SI/F Ch.1 Rx buffer full SI/F Ch.1 Tx buffer empty A/D conversion completion Port 9 input Port 13 input Software trigger #DMAREQ0 input (falling edge) #DMAREQ0 input (rising edge) Port 0 input Port 4 input 8-bit timer 0 underflow 16-bit timer 0 compare B 16-bit timer 0 compare A 16-bit timer 4 compare B 16-bit timer 4 compare A SI/F Ch.0 Rx buffer full SI/F Ch.0 Tx buffer empty A/D conversion completion Port 8 input Port 12 input Software trigger #DMAREQ3 input (falling edge) #DMAREQ3 input (rising edge) Port 3 input Port 7 input 8-bit timer 3 underflow 16-bit timer 3 compare B 16-bit timer 3 compare A 16-bit timer 7 compare B 16-bit timer 7 compare A SI/F Ch.3 Rx buffer full SI/F Ch.3 Tx buffer empty A/D conversion completion Port 11 input Port 15 input Software trigger #DMAREQ2 input (falling edge) #DMAREQ2 input (rising edge) Port 2 input Port 6 input 8-bit timer 2 underflow 16-bit timer 2 compare B 16-bit timer 2 compare A 16-bit timer 6 compare B 16-bit timer 6 compare A SI/F Ch.2 Rx buffer full SI/F Ch.2 Tx buffer empty A/D conversion completion Port 10 input Port 14 input - 1 Trigger 0 Invalid 0 0 0 0 R/W 0 0 0 0 R/W 0 0 0 0 R/W 0 0 0 0 R/W - 0 0 0 0 - W W W W Remarks 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4029B-0x402A4 Register name Address Interrupt Controller Name Bit Function 8-bit timer 4-5 004029B D7-6 - D5 RSTX3 (B) serial I/F Ch.2-3 D4 RSRX3 IDMA request D3 RSTX2 register D2 RSRX2 (pIDMAREQ_R8T45 D1 R8TU5 _RSIF23) D0 R8TU4 reserved SIF Ch.3 transmit buffer empty SIF Ch.3 receive buffer full SIF Ch.2 transmit buffer empty SIF Ch.2 receive buffer full 8-bit timer 5 underflow 8-bit timer 4 underflow reserved 8-bit timer 4-5 004029C D7-6 - SIF Ch.3 transmit buffer empty D5 DESTX3 (B) serial I/F Ch.2-3 SIF Ch.3 receive buffer full D4 DESRX3 IDMA enable SIF Ch.2 transmit buffer empty D3 DESTX2 register SIF Ch.2 receive buffer full D2 DESRX2 (pIDMAEN_DE8T45 8-bit timer 5 underflow D1 DE8TU5 _DESIF23) 8-bit timer 4 underflow D0 DE8TU4 reserved Flag set/reset 004029F D7-3 - D2 DENONLY IDMA enable register set method (B) method select selection register D1 IDMAONLY IDMA request register set method (pRST_RESET) selection D0 RSTONLY Cause-of-interrupt flag reset method selection Port input 8-9 00402A0 (B) interrupt priority register (pINT_PR89L) 00402A1 Port input (B) 10-11 interrupt priority register (pINT_PR1011L) 00402A2 Port input (B) 12-13 interrupt priority register (pINT_PR1213L) 00402A3 Port input (B) 14-15 interrupt priority register (pINT_PR1415L) 16-bit timer 6-7 00402A4 (B) interrupt priority register (pINT_P16T67) Setting - 1 IDMA request 0 Interrupt request - 1 IDMA enabled 0 IDMA disabled - Init. R/W Remarks - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W 1 Set only 0 RD/WR - 1 - R/W 1 Set only 0 RD/WR 1 R/W 1 Reset only 0 RD/WR 1 R/W - X X X - X X X - 0 when being read. R/W D7 D6 D5 D4 D3 D2 D1 D0 - PP9L2 PP9L1 PP9L0 - PP8L2 PP8L1 PP8L0 reserved Port input 9 interrupt level - 0 to 7 reserved Port input 8 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP11L2 PP11L1 PP11L0 - PP10L2 PP10L1 PP10L0 reserved Port input 11 interrupt level - 0 to 7 reserved Port input 10 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP13L2 PP13L1 PP13L0 - PP12L2 PP12L1 PP12L0 reserved Port input 13 interrupt level - 0 to 7 reserved Port input 12 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - PP15L2 PP15L1 PP15L0 - PP14L2 PP14L1 PP14L0 reserved Port input 15 interrupt level - 0 to 7 reserved Port input 14 interrupt level - 0 to 7 D7 D6 D5 D4 D3 D2 D1 D0 - P16T72 P16T71 P16T70 - P16T62 P16T61 P16T60 reserved 16-bit timer 7 interrupt level - 0 to 7 reserved 16-bit timer 6 interrupt level - 0 to 7 - X X X - X X X - X X X - X X X - X X X - X X X - X X X - X X X I - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-19 APPENDIX I/O MAP 0x402A5-0x402AD Register name Address Bit 16-bit timer 8-9 00402A5 (B) interrupt priority register (pINT_P16T89) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5-4 D3 D2 D1-0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Port input 8-15 00402A6 (B) interrupt enable register (pINT_EP815) 16-bit timer 6-7 00402A7 (B) interrupt enable register (pINT_E16T67) 16-bit timer 8-9 00402A8 (B) interrupt enable register (pINT_E16T89) Port input 8-15 00402A9 (B) interrupt cause flag register (pINT_FP815) 16-bit timer 6-7 00402AA (B) interrupt cause flag register (pINT_F16T67) 16-bit timer 8-9 00402AB (B) interrupt cause flag register (pINT_F16T89) Port input 8-15 00402AC (B) IDMA request register (pIDMAREQ _RP815) 16-bit timer 6-9 00402AD (B) IDMA request register (pIDMAREQ _R16T69) APP-20 Interrupt Controller Name - P16T92 P16T91 P16T90 - P16T82 P16T81 P16T80 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 E16TC7 E16TU7 - E16TC6 E16TU6 - E16TC9 E16TU9 - E16TC8 E16TU8 - FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 F16TC7 F16TU7 - F16TC6 F16TU6 - F16TC9 F16TU9 - F16TC8 F16TU8 - RP15 RP14 RP13 RP12 RP11 RP10 RP9 RP8 R16TC9 R16TU9 R16TC8 R16TU8 R16TC7 R16TU7 R16TC6 R16TU6 Function Setting reserved 16-bit timer 9 interrupt level - 0 to 7 reserved 16-bit timer 8 interrupt level - 0 to 7 Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 16-bit timer 7 comparison A 16-bit timer 7 comparison B reserved 16-bit timer 6 comparison A 16-bit timer 6 comparison B reserved 16-bit timer 9 comparison A 16-bit timer 9 comparison B reserved 16-bit timer 8 comparison A 16-bit timer 8 comparison B reserved Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 16-bit timer 7 comparison A 16-bit timer 7 comparison B reserved 16-bit timer 6 comparison A 16-bit timer 6 comparison B reserved 16-bit timer 9 comparison A 16-bit timer 9 comparison B reserved 16-bit timer 8 comparison A 16-bit timer 8 comparison B reserved Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 16-bit timer 9 comparison A 16-bit timer 9 comparison B 16-bit timer 8 comparison A 16-bit timer 8 comparison B 16-bit timer 7 comparison A 16-bit timer 7 comparison B 16-bit timer 6 comparison A 16-bit timer 6 comparison B EPSON 1 Enabled 0 Disabled 1 Enabled 0 Disabled Init. R/W - X X X - X X X 0 0 0 0 0 0 0 0 - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled - 1 Occurred 0 Not occurred 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 Occurred 0 Not occurred - 1 IDMA request 0 Interrupt request 1 IDMA request 0 Interrupt request 0 0 - 0 0 - 0 0 - 0 0 - X X X X X X X X X X - X X - X X - X X - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W - R/W R/W - R/W R/W - 0 when being read. 0 when being read. 0 when being read. 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x402AE-0x402AF Register name Address Bit Port input 8-15 00402AE (B) IDMA enable register (pIDMAEN_DEP815) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 16-bit timer 6-9 00402AF (B) IDMA enable register (pIDMAEN _DE16T69) Interrupt Controller Name DEP15 DEP14 DEP13 DEP12 DEP11 DEP10 DEP9 DEP8 DE16TC9 DE16TU9 DE16TC8 DE16TU8 DE16TC7 DE16TU7 DE16TC6 DE16TU6 Function Port input 15 Port input 14 Port input 13 Port input 12 Port input 11 Port input 10 Port input 9 Port input 8 16-bit timer 9 comparison A 16-bit timer 9 comparison B 16-bit timer 8 comparison A 16-bit timer 8 comparison B 16-bit timer 7 comparison A 16-bit timer 7 comparison B 16-bit timer 6 comparison A 16-bit timer 6 comparison B Setting 1 IDMA enabled 0 IDMA disabled 1 IDMA enabled 0 IDMA disabled Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-21 APPENDIX I/O MAP 0x402E8-0x402EC Register name Address Debug signal output control write-protect register Debug signal output control register APP-22 00402E8 (B) Bit D7 D6 D5 D4 D3 D2 D1 D0 00402EC D7-2 D1 (B) D0 Debug Unit Name DBGOUTP7 DBGOUTP6 DBGOUTP5 DBGOUTP4 DBGOUTP3 DBGOUTP2 DBGOUTP1 DBGOUTP0 - DBTOE DPCTOE Function Debug signal output control register write-protect flag reserved Bus trace signal output enable PC trace signal output enable EPSON Setting Init. R/W Remarks Writing 01011001 (0x59) X W 0 when being read. removes the write protection of X the Debug signal output control X register (0x402EC). X Writing another value set the X write protection. X X X - - 0 when being read. - 0 R/W 1 Enabled 0 Disabled 1 R/W 1 Enabled 0 Disabled S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40300-0x40302 Card Interface Register name Address Bit Name Card I/F area configuration register (pCARDSETUP) D7 D6 D5 D4 D3 D2 D1 D0 CARDPC21 CARDPC20 CARDPC11 CARDPC10 CARDCF1 CARDCF0 CARDSMT1 CARDSMT0 PC card 2 area configuration - CARDIO5 CARDIO4 CARDIO3 CARDIO2 CARDIO1 CARDIO0 reserved CARD5 port function select CARD4 port function select CARD3 port function select CARD2 port function select CARD1 port function select CARD0 port function select 0040300 (B) 0040302 Card I/F (B) output port configuration register (pCARDFUNCSEL05) D7-6 D5 D4 D3 D2 D1 D0 Function Setting Init. R/W bit[1:0] CE area 11 10 01 00 CE11 (Area 11, 12) CE9 (Area 9, 22) CE7 (Area 7, 19) CE4 (Area 4, 14) PC card 1 area configuration CF area configuration SmartMedia area configuration - 1 1 1 1 1 1 #CFCE2 #CFCE1 #SMWR #SMRD #CFCE2 #CFCE1 0 0 0 0 0 0 #WE #OE #IOWR #IORD #SMWR #SMRD I Remarks 0 0 0 0 0 0 0 0 R/W - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-23 APPENDIX I/O MAP 0x40340-0x40348 Register name Address P0 port data register (pP0_P0D) 0040340 (B) P0 I/O control register (pP0_IOC0) 0040341 (B) P1 port data register (pP1_P1D) 0040342 (B) P1 I/O control register (pP1_IOC1) 0040343 (B) P2 port data register (pP2_P2D) 0040344 (B) P2 I/O control register (pP2_IOC2) 0040345 (B) P3 port data register (pP3_P3D) 0040346 (B) P3 I/O control register (pP3_IOC3) 0040347 (B) P4 port data register (pP4_P4D) 0040348 (B) APP-24 Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-4 D3 D2 D1 D0 D7-4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 I/O Ports Name P07D P06D P05D P04D P03D P02D P01D P00D IOC07 IOC06 IOC05 IOC04 IOC03 IOC02 IOC01 IOC00 P17D P16D P15D P14D P13D P12D P11D P10D IOC17 IOC16 IOC15 IOC14 IOC13 IOC12 IOC11 IOC10 P27D P26D P25D P24D P23D P22D P21D P20D IOC27 IOC26 IOC25 IOC24 IOC23 IOC22 IOC21 IOC20 - P33D P32D P31D P30D - IOC33 IOC32 IOC31 IOC30 P47D P46D P45D P44D P43D P42D P41D P40D Function P07 I/O port data P06 I/O port data P05 I/O port data P04 I/O port data P03 I/O port data P02 I/O port data P01 I/O port data P00 I/O port data P07 I/O control P06 I/O control P05 I/O control P04 I/O control P03 I/O control P02 I/O control P01 I/O control P00 I/O control P17 I/O port data P16 I/O port data P15 I/O port data P14 I/O port data P13 I/O port data P12 I/O port data P11 I/O port data P10 I/O port data P17 I/O control P16 I/O control P15 I/O control P14 I/O control P13 I/O control P12 I/O control P11 I/O control P10 I/O control P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P21 I/O port data P20 I/O port data P27 I/O control P26 I/O control P25 I/O control P24 I/O control P23 I/O control P22 I/O control P21 I/O control P20 I/O control reserved P33 I/O port data P32 I/O port data P31 I/O port data P30 I/O port data reserved P33 I/O control P32 I/O control P31 I/O control P30 I/O control P47 I/O port data P46 I/O port data P45 I/O port data P44 I/O port data P43 I/O port data P42 I/O port data P41 I/O port data P40 I/O port data Setting Remarks 0 Low Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W 1 Output 0 Input R/W R/W R/W R/W R/W R/W R/W R/W 1 High 0 Low 1 Output 0 Input 1 High 0 Low 0 0 0 0 0 0 0 0 Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. 0 0 0 0 0 0 0 0 Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. 1 Output 0 Input - 1 High 0 Low - EPSON Init. R/W 1 High 1 Output 0 Input 1 High 0 Low 0 0 0 0 0 0 0 0 - Ext. Ext. Ext. Ext. - 0 0 0 0 Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W - R/W R/W R/W R/W 0 when being read. Ext.: The initial value depends on the external pin status. 0 when being read. R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40349-0x40351 Register name Address P4 I/O control register (pP4_IOC4) 0040349 (B) P5 port data register (pP5_P5D) 004034A (B) P5 I/O control register (pP5_IOC5) 004034B (B) P6 port data register (pP6_P6D) 004034C (B) P6 I/O control register (pP6_IOC6) 004034D (B) P7 port data register (pP7_P7D) 004034E (B) P8 port data register (pP8_P8D) 0040350 (B) P8 I/O control register (pP8_IOC8) 0040351 (B) I/O Ports Name Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 IOC47 IOC46 IOC45 IOC44 IOC43 IOC42 IOC41 IOC40 - P56D P55D P54D P53D P52D P51D P50D - IOC56 IOC55 IOC54 IOC53 IOC52 IOC51 IOC50 P67D P66D P65D P64D P63D P62D P61D P60D IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 - P73D P72D P71D P70D P87D P86D P85D P84D P83D P82D P81D P80D IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80 Function P47 I/O control P46 I/O control P45 I/O control P44 I/O control P43 I/O control P42 I/O control P41 I/O control P40 I/O control reserved P56 I/O port data P55 I/O port data P54 I/O port data P53 I/O port data P52 I/O port data P51 I/O port data P50 I/O port data reserved P56 I/O control P55 I/O control P54 I/O control P53 I/O control P52 I/O control P51 I/O control P50 I/O control P67 I/O port data P66 I/O port data P65 I/O port data P64 I/O port data P63 I/O port data P62 I/O port data P61 I/O port data P60 I/O port data P67 I/O control P66 I/O control P65 I/O control P64 I/O control P63 I/O control P62 I/O control P61 I/O control P60 I/O control reserved P73 input port data P72 input port data P71 input port data P70 input port data P87 I/O port data P86 I/O port data P85 I/O port data P84 I/O port data P83 I/O port data P82 I/O port data P81 I/O port data P80 I/O port data P87 I/O control P86 I/O control P85 I/O control P84 I/O control P83 I/O control P82 I/O control P81 I/O control P80 I/O control Setting 1 Output 0 Input - 1 High 0 Low - 1 Output 0 Input 1 High 0 Low 1 Output 0 Input - 1 High 0 Low 1 High 0 Low 1 Output 0 Input Init. R/W 0 0 0 0 0 0 0 0 - Ext. Ext. Ext. Ext. Ext. Ext. Ext. - 0 0 0 0 0 0 0 Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. 0 0 0 0 0 0 0 0 - Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. 0 0 0 0 0 0 0 0 I Remarks R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W 0 when being read. Ext.: The initial value depends on the external pin status. 0 when being read. R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R R R R 0 when being read. Ext.: The initial value depends on the external pin status. R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-25 APPENDIX I/O MAP 0x40352-0x40362 I/O Ports Name Register name Address Bit P9 port data register (pP9_P9D) 0040352 (B) P9 I/O control register (pP9_IOC9) 0040353 (B) P00-P03 port function select register (pP0_03_CFP) 0040360 (B) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90 CFP031 CFP030 D5 D4 CFP021 CFP020 P02 port extended function D3 D2 CFP011 CFP010 P01 port extended function D1 D0 CFP001 CFP000 P00 port extended function D7 D6 CFP071 CFP070 P07 port extended function D5 D4 CFP061 CFP060 P06 port extended function D3 D2 CFP051 CFP050 P05 port extended function D1 D0 CFP041 CFP040 P04 port extended function D7 D6 CFP131 CFP130 P13 port extended function D5 D4 CFP121 CFP120 P12 port extended function D3 D2 CFP111 CFP110 P11 port extended function D1 D0 CFP101 CFP100 P10 port extended function P04-P07 port function select register (pP0_47_CFP) P10-P13 port function select register (pP1_03_CFP) APP-26 0040361 (B) 0040362 (B) P97D P96D P95D P94D P93D P92D P91D P90D Function P97 I/O port data P96 I/O port data P95 I/O port data P94 I/O port data P93 I/O port data P92 I/O port data P91 I/O port data P90 I/O port data P97 I/O control P96 I/O control P95 I/O control P94 I/O control P93 I/O control P92 I/O control P91 I/O control P90 I/O control P03 port extended function EPSON Setting Init. R/W 1 High 0 Low Ext. Ext. Ext. Ext. Ext. Ext. Ext. Ext. 1 Output 0 Input 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W CFP03[1:0] 1 01 00 CFP02[1:0] 1 01 00 CFP01[1:0] 1 01 00 CFP00[1:0] 1 01 00 CFP07[1:0] 1 01 00 CFP06[1:0] 1 01 00 CFP05[1:0] 1 01 00 CFP04[1:0] 1 01 00 CFP13[1:0] 1 01 00 CFP12[1:0] 1 01 00 CFP11[1:0] 1 01 00 CFP10[1:0] 1 01 00 Function reserved #SRDY0 P03 Function reserved #SCLK0 P02 Function reserved SOUT0 P01 Function reserved SIN0 P00 Function reserved #SRDY1 P07 Function reserved #SCLK1 P06 Function reserved SOUT1 P05 Function reserved SIN1 P04 Function reserved TM3 P13 Function reserved TM2 P12 Function reserved TM1 P11 Function reserved TM0 P10 Remarks R/W Ext.: The initial value R/W depends on the R/W external pin status. R/W R/W R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40363-0x40365 I/O Ports Register name Address Bit Name 0040363 (B) D7 D6 CFP171 CFP170 P17 port extended function D5 D4 CFP161 CFP160 P16 port extended function D3 D2 CFP151 CFP150 P15 port extended function D1 D0 CFP141 CFP140 P14 port extended function D7 D6 CFP231 CFP230 P23 port extended function D5 D4 CFP221 CFP220 P22 port extended function D3 D2 CFP211 CFP210 P21 port extended function D1 D0 CFP201 CFP200 P20 port extended function D7 D6 CFP271 CFP270 P27 port extended function D5 D4 CFP261 CFP260 P26 port extended function D3 D2 CFP251 CFP250 P25 port extended function D1 D0 CFP241 CFP240 P24 port extended function P14-P17 port function select register (pP1_47_CFP) P20-P23 port function select register (pP2_03_CFP) P24-P27 port function select register (pP2_47_CFP) 0040364 (B) 0040365 (B) Function Setting CFP17[1:0] 11 10 01 00 CFP16[1:0] 11 10 01 00 CFP15[1:0] 11 10 01 00 CFP14[1:0] 11 10 01 00 CFP23[1:0] 11 10 01 00 CFP22[1:0] 11 10 01 00 CFP21[1:0] 11 10 01 00 CFP20[1:0] 11 10 01 00 CFP27[1:0] 11 10 01 00 CFP26[1:0] 11 10 01 00 CFP25[1:0] 11 10 01 00 CFP24[1:0] 11 10 01 00 Function reserved #DMAACK1 TM7 P17 Function reserved #DMAACK0 TM6 P16 Function reserved #DMAEND1 TM5 P15 Function reserved #DMAEND0 TM4 P14 Function reserved #SRDY2 #SDRAS P23 Function reserved #SCLK2 #SDCS P22 Function reserved SOUT2 SDCLK P21 Function reserved SIN2 SDCKE P20 Function reserved #SRDY3 DQMH P27 Function reserved #SCLK3 DQML P26 Function reserved SOUT3 #SDWE P25 Function reserved SIN3 #SDCAS P24 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W I Remarks APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-27 APPENDIX I/O MAP 0x40366-0x40369 I/O Ports Register name Address Bit Name 0040366 (B) D7 D6 CFP331 CFP330 P33 port extended function D5 D4 CFP321 CFP320 P32 port extended function D3 D2 CFP311 CFP310 P31 port extended function D1 D0 CFP301 CFP300 P30 port extended function D7 D6 CFP431 CFP430 P43 port extended function D5 D4 CFP421 CFP420 P42 port extended function D3 D2 CFP411 CFP410 P41 port extended function D1 D0 CFP401 CFP400 P40 port extended function D7 D6 CFP471 CFP470 P47 port extended function D5 D4 CFP461 CFP460 P46 port extended function D3 D2 CFP451 CFP450 P45 port extended function D1 D0 CFP441 CFP440 P44 port extended function P30-P33 port function select register (pP3_03_CFP) P40-P43 port function select register (pP4_03_CFP) P44-P47 port function select register (pP4_47_CFP) APP-28 0040368 (B) 0040369 (B) Function EPSON Setting CFP33[1:0] 11 10 01 00 CFP32[1:0] 11 10 01 00 CFP31[1:0] 11 10 01 00 CFP30[1:0] 11 10 01 00 CFP43[1:0] 1 01 00 CFP42[1:0] 1 01 00 CFP41[1:0] 1 01 00 CFP40[1:0] 1 01 00 CFP47[1:0] 1 01 00 CFP46[1:0] 1 01 00 CFP45[1:0] 1 01 00 CFP44[1:0] 1 01 00 Init. R/W Function WDT_CLK CARD3 #DMAREQ3 P33 Function EXCL2 CARD2 #DMAREQ2 P32 Function EXCL1 T8UF1 #DMAREQ1 P31 Function EXCL0 T8UF0 #DMAREQ0 P30 Function reserved P43 A22 Function reserved P42 A23 Function reserved P41 A24 Function reserved P40 A25 Function reserved P47 A18 Function reserved P46 A19 Function reserved P45 A20 Function reserved P44 A21 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4036A-0x4036D I/O Ports Register name Address Bit Name 004036A (B) D7 D6 CFP531 CFP530 P53 port extended function D5 D4 CFP521 CFP520 P52 port extended function D3 D2 CFP511 CFP510 P51 port extended function D1 D0 CFP501 CFP500 P50 port extended function 004036B D7-6 - D5 CFP561 (B) D4 CFP560 reserved P56 port extended function D3 D2 CFP551 CFP550 P55 port extended function D1 D0 CFP541 CFP540 P54 port extended function D7 D6 CFP631 CFP630 P63 port extended function D5 D4 CFP621 CFP620 P62 port extended function D3 D2 CFP611 CFP610 P61 port extended function D1 D0 CFP601 CFP600 P60 port extended function 004036D D7-2 - D1 CFP641 (B) D0 CFP640 reserved P64 port extended function P50-P53 port function select register (pP5_03_CFP) P54-P56 port function select register (pP5_46_CFP) P60-P63 port function select register (pP6_03_CFP) P64-P67 port function select register (pP6_47_CFP) 004036C (B) Function Setting CFP53[1:0] 11 10 01 00 CFP52[1:0] 1 01 00 CFP51[1:0] 1 01 00 CFP50[1:0] 11 10 01 00 Function reserved CARD1 P53 #CE7 Function reserved P52 #CE6 Function reserved P51 #CE5 Function reserved CARD0 P50 #CE4 - CFP56[1:0] 1 01 00 CFP55[1:0] 1 01 00 CFP54[1:0] 1 01 00 CFP63[1:0] 11 10 01 00 CFP62[1:0] 11 10 01 00 CFP61[1:0] 11 10 01 00 CFP60[1:0] 11 10 01 00 Function reserved P56 #CE11 Function reserved P55 #CE9 Function reserved P54 #CE8 Function T8UF5 BCLK P63 CMU_CLK Function #ADTRG T8UF2 #BUSGET P62 Function reserved CARD5 #BUSACK P61 Function reserved CARD4 #BUSREQ P60 - CFP64[1:0] 1 01 00 Function reserved #WAIT P64 Init. R/W I Remarks 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W - 0 0 - 0 when being read. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W - 0 0 - 0 when being read. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-29 APPENDIX I/O MAP 0x4036E-0x40371 I/O Ports Register name Address Bit Name 004036E (B) D7 D6 CFP731 CFP730 P73 port extended function D5 D4 CFP721 CFP720 P72 port extended function D3 D2 CFP711 CFP710 P71 port extended function D1 D0 CFP701 CFP700 P70 port extended function D7 D6 CFP831 CFP830 P83 port extended function D5 D4 CFP821 CFP820 P82 port extended function D3 D2 CFP811 CFP810 P81 port extended function D1 D0 CFP801 CFP800 P80 port extended function D7 D6 CFP871 CFP870 P87 port extended function D5 D4 CFP861 CFP860 P86 port extended function D3 D2 CFP851 CFP850 P85 port extended function D1 D0 CFP841 CFP840 P84 port extended function P70-P73 port function select register (pP7_03_CFP) P80-P83 port function select register (pP8_03_CFP) P84-P87 port function select register (pP8_47_CFP) APP-30 0040370 (B) 0040371 (B) Function EPSON Setting CFP73[1:0] 1 01 00 CFP72[1:0] 1 01 00 CFP71[1:0] 1 01 00 CFP70[1:0] 1 01 00 CFP83[1:0] 11 10 01 00 CFP82[1:0] 11 10 01 00 CFP81[1:0] 11 10 01 00 CFP80[1:0] 11 10 01 00 CFP87[1:0] 11 10 01 00 CFP86[1:0] 11 10 01 00 CFP85[1:0] 11 10 01 00 CFP84[1:0] 11 10 01 00 Init. R/W Function reserved AIN3 P73 Function reserved AIN2 P72 Function reserved AIN1 P71 Function reserved AIN0 P70 Function reserved EXCL6 #DMAEND3 P83 Function reserved EXCL5 #DMAEND2 P82 Function EXCL4 T8UF4 #DMAACK3 P81 Function EXCL3 T8UF3 #DMAACK2 P80 Function reserved CARD1 TM9 P87 Function reserved CARD0 TM8 P86 Function reserved CARD3 CMU_CLK P85 Function reserved CARD2 PSC_CLK P84 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40372-0x40380 I/O Ports Register name Address Bit Name 0040372 (B) D7 D6 CFP931 CFP930 P93 port extended function D5 D4 CFP921 CFP920 P92 port extended function D3 D2 CFP911 CFP910 P91 port extended function D1 D0 CFP901 CFP900 P90 port extended function D7 D6 CFP971 CFP970 P97 port extended function D5 D4 CFP961 CFP960 P96 port extended function D3 D2 CFP951 CFP950 P95 port extended function D1 D0 CFP941 CFP940 P94 port extended function D7 D6 SPT31 SPT30 FPT3 interrupt input port selection D5 D4 SPT21 SPT20 FPT2 interrupt input port selection D3 D2 SPT11 SPT10 FPT1 interrupt input port selection D1 D0 SPT01 SPT00 FPT0 interrupt input port selection P90-P93 port function select register (pP9_03_CFP) P94-P97 port function select register (pP9_47_CFP) 0040373 (B) Port input 0040380 interrupt select (B) register 1 (pPINTSEL _SPT03) Function Setting CFP93[1:0] 11 10 01 00 CFP92[1:0] 11 10 01 00 CFP91[1:0] 11 10 01 00 CFP90[1:0] 11 10 01 00 CFP97[1:0] 11 10 01 00 CFP96[1:0] 11 10 01 00 CFP95[1:0] 11 10 01 00 CFP94[1:0] 11 10 01 00 SPT3[1:0] 11 10 01 00 SPT2[1:0] 11 10 01 00 SPT1[1:0] 11 10 01 00 SPT0[1:0] 11 10 01 00 Function reserved R/W #SRDY2 P93 Function reserved EXCL9 #SCLK2 P92 Function reserved EXCL8 SOUT2 P91 Function reserved EXCL7 SIN2 P90 Function reserved CARD5 #SRDY3 P97 Function reserved CARD4 #SCLK3 P96 Function reserved ASTB SOUT3 P95 Function reserved ACST SIN3 P94 Port P33 P13 P23 P03 Port P32 P12 P22 P02 Port P31 P11 P21 P01 Port P30 P10 P20 P00 Init. R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W I Remarks APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-31 APPENDIX I/O MAP 0x40381-0x40384 I/O Ports Name Register name Address Bit 0040381 Port input (B) interrupt select register 2 (pPINTSEL _SPT47) D7 D6 SPT71 SPT70 D5 D4 SPT61 SPT60 D3 D2 SPT51 SPT50 D1 D0 SPT41 SPT40 0040382 (B) D7 D6 D5 D4 D3 D2 D1 D0 0040383 Port input (B) interrupt edge/level select register 1 (pPINTEL _SEPT07) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 SPPT7 SPPT6 SPPT5 SPPT4 SPPT3 SPPT2 SPPT1 SPPT0 SEPT7 SEPT6 SEPT5 SEPT4 SEPT3 SEPT2 SEPT1 SEPT0 SPTB1 SPTB0 D5 D4 SPTA1 SPTA0 D3 D2 SPT91 SPT90 D1 D0 SPT81 SPT80 Port input interrupt polarity select register 1 (pPINTPOL _SPP07) Port input 0040384 interrupt select (B) register 3 (pPINTSEL _SPT811) APP-32 Function FPT7 interrupt input port selection Setting Init. R/W SPT7[1:0] Port P63 11 P17 10 P27 01 P07 00 FPT6 interrupt input port selection SPT6[1:0] Port P62 11 P16 10 P26 01 P06 00 FPT5 interrupt input port selection SPT5[1:0] Port 11 P61 10 P15 01 P25 00 P05 FPT4 interrupt input port selection SPT4[1:0] Port 11 P60 10 P14 01 P24 00 P04 1 High level 0 Low level FPT7 input polarity selection or or FPT6 input polarity selection Falling edge Rising edge FPT5 input polarity selection FPT4 input polarity selection FPT3 input polarity selection FPT2 input polarity selection FPT1 input polarity selection FPT0 input polarity selection 1 Edge 0 Level FPT7 edge/level selection FPT6 edge/level selection FPT5 edge/level selection FPT4 edge/level selection FPT3 edge/level selection FPT2 edge/level selection FPT1 edge/level selection FPT0 edge/level selection FPT11 interrupt input port selection SPTB[1:0] Port P93 11 P87 10 P83 01 P73 00 FPT10 interrupt input port selection SPTA[1:0] Port P92 11 P86 10 P82 01 P72 00 FPT9 interrupt input port selection SPT9[1:0] Port 11 P91 10 P85 01 P81 00 P71 FPT8 interrupt input port selection SPT8[1:0] Port 11 P90 10 P84 01 P80 00 P70 EPSON 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 R/W 0 0 R/W 0 0 R/W Remarks S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x40385-0x40392 I/O Ports Name Register name Address Bit 0040385 Port input (B) interrupt select register 4 (pPINTSEL _SPT1215) D7 D6 SPTF1 SPTF0 D5 D4 SPTE1 SPTE0 D3 D2 SPTD1 SPTD0 D1 D0 SPTC1 SPTC0 0040386 (B) D7 D6 D5 D4 D3 D2 D1 D0 0040387 Port input (B) interrupt edge/level select register 2 (pPINTEL _SEPT815) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 SPPTF SPPTE SPPTD SPPTC SPPTB SPPTA SPPT9 SPPT8 SEPTF SEPTE SEPTD SEPTC SEPTB SEPTA SEPT9 SEPT8 - SPPK12 SPPK11 SPPK10 D3 D2 D1 D0 - SPPK02 SPPK01 SPPK00 Port input interrupt polarity select register 2 (pPINTPOL _SPP815) 0040390 Key input (B) interrupt select register (pKINTSEL _SPPK01) Key input interrupt (FPK0) input comparison register (pKINTCOMP _SCPK0) 0040392 (B) D7-5 - D4 D3 D2 D1 D0 SCPK04 SCPK03 SCPK02 SCPK01 SCPK00 Function Setting FPT15 interrupt input port selection SPTF[1:0] 11 10 01 00 FPT14 interrupt input port selection SPTE[1:0] 11 10 01 00 FPT13 interrupt input port selection SPTD[1:0] 11 10 01 00 FPT12 interrupt input port selection SPTC[1:0] 11 10 01 00 1 High level 0 FPT15 input polarity selection or FPT14 input polarity selection Rising edge FPT13 input polarity selection FPT12 input polarity selection FPT11 input polarity selection FPT10 input polarity selection FPT9 input polarity selection FPT8 input polarity selection 1 Edge 0 FPT15 edge/level selection FPT14 edge/level selection FPT13 edge/level selection FPT12 edge/level selection FPT11 edge/level selection FPT10 edge/level selection FPT9 edge/level selection FPT8 edge/level selection reserved - FPK1 interrupt input port selection SPPK1[2:0] 111 110 101 100 011 010 001 000 reserved - FPK0 interrupt input port selection SPPK0[2:0] 111 110 101 100 011 010 001 000 reserved - FPK04 input comparison FPK03 input comparison FPK02 input comparison FPK01 input comparison FPK00 input comparison 1 High Init. R/W Port P97 P67 P53 P43 Port P96 P66 P52 P42 Port P95 P65 P51 P41 Port P94 P64 P50 P40 Low level or Falling edge Level Port P9[7:4] P8[7:4] P7[3:0] P6[7:4] P3[3:0] P2[7:4] P1[7:4] P0[7:4] Port P9[4:0] P8[4:0] P5[4:0] P6[4:0] P4[4:0] P2[4:0] P1[4:0] P0[4:0] 0 Low Remarks 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 - 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W - 0 0 0 - 0 when being read. R/W - - 0 0 0 0 0 R/W R/W R/W R/W R/W I 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-33 APPENDIX I/O MAP 0x40393-0x40395 Register name Address Key input interrupt (FPK1) input comparison register (pKINTCOMP _SCPK1) 0040393 (B) Key input interrupt (FPK0) input mask register (pKINTCOMP _SMPK0) 0040394 (B) Key input interrupt (FPK1) input mask register (pKINTCOMP _SMPK1) 0040395 (B) APP-34 I/O Ports Name Bit D7-4 - Function Setting reserved - D3 D2 D1 D0 D7-5 D4 D3 D2 D1 D0 D7-4 SCPK13 SCPK12 SCPK11 SCPK10 - SMPK04 SMPK03 SMPK02 SMPK01 SMPK00 - FPK13 input comparison FPK12 input comparison FPK11 input comparison FPK10 input comparison reserved FPK04 input mask FPK03 input mask FPK02 input mask FPK01 input mask FPK00 input mask reserved 1 High D3 D2 D1 D0 SMPK13 SMPK12 SMPK11 SMPK10 FPK13 input mask FPK12 input mask FPK11 input mask FPK10 input mask 1 Interrupt enabled EPSON 0 Low - 1 Interrupt enabled 0 Interrupt disabled - 0 Interrupt disabled Init. R/W - - 0 0 0 0 - 0 0 0 0 0 R/W R/W R/W R/W - - 0 0 0 0 R/W R/W R/W R/W Remarks 0 when being read. - 0 when being read. R/W R/W R/W R/W R/W 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48140-0x48146 Register name Address A/D Converter Name Bit Function A/D conversion 0048140 D15-10 - D9 ADD9 (HW) result register D8 ADD8 (pAD_ADD) D7 ADD7 D6 ADD6 D5 ADD5 D4 ADD4 D3 ADD3 D2 ADD2 D1 ADD1 D0 ADD0 reserved A/D converted data ADD9 = MSB ADD0 = LSB 0048142 D15-14 - A/D trigger/ D13 CE2 (HW) channel select D12 CE1 register D11 CE0 (pAD_TRIG_CHNL) D10 CS2 D9 CS1 D8 CS0 D7-6 - D5 MS D4 TS1 D3 TS0 A/D control/ status register (pAD_EN_SMPL _STAT) A/D channel status flag register (pAD_END) 0048144 (HW) 0048146 (HW) D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 CH2 CH1 CH0 ADCMPE ADCMP2 ADCMP1 ADCMP0 ADUPRST ADLWRST ST1 ST0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - INTMODE CMPINTEN CNVINTEN ADF ADE ADST OWE OWE7 OWE6 OWE5 OWE4 OWE3 OWE2 OWE1 OWE0 ADF7 ADF6 ADF5 ADF4 ADF3 ADF2 ADF1 ADF0 Setting Init. R/W - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 reserved A/D converter end channel selection - 0 to 7 (depends on the model.) A/D converter start channel selection 0 to 7 (depends on the model.) - 0 0 0 0 0 0 - 0 0 0 reserved A/D conversion mode selection A/D conversion trigger selection A/D conversion channel status - 1 Continuous 0 Normal TS[1:0] Trigger 11 #ADTRG pin 10 8-bit timer 01 16-bit timer 00 Software 0 to 7 (depends on the model.) Upper/lower-limit comparison enable 1 Enabled 0 Disabled Upper/lower-limit comparison 0 to 7 channel selection (depends on the model.) Upper-limit comparison status Lower-limit comparison status Input signal sampling time setup reserved Interrupt signal mode Out-of-range int. enable Conversion-complete int. enable Conversion-complete flag A/D enable A/D conversion control/status Overwrite error flag Ch.7 overwrite error flag Ch.6 overwrite error flag Ch.5 overwrite error flag Ch.4 overwrite error flag Ch.3 overwrite error flag Ch.2 overwrite error flag Ch.1 overwrite error flag Ch.0 overwrite error flag Ch.7 conversion-complete flag Ch.6 conversion-complete flag Ch.5 conversion-complete flag Ch.4 conversion-complete flag Ch.3 conversion-complete flag Ch.2 conversion-complete flag Ch.1 conversion-complete flag Ch.0 conversion-complete flag 1 Out of range 0 Within range 1 Out of range 0 Within range ST[1:0] Sampling time 11 9 clocks 10 7 clocks 01 5 clocks 00 3 clocks - 1 Complete only 0 OR 1 Enabled 0 Disabled 1 Enabled 0 Disabled 1 Completed 0 Run/Standby 1 Enabled 0 Disabled 1 Start/Run 0 Stop 1 Error 0 Normal 1 Error 0 Normal 1 Completed 0 Run/Standby 0 0 0 - R I Remarks 0 when being read. - 0 when being read. R/W R/W - 0 when being read. R/W R/W R 0 0 0 0 0 0 1 1 R/W Can be used when R/W ADCADV = "1". - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R/W Use with 9 clocks. 0 when being read. Can be used when ADCADV = "1". Reset when ADD is read. Reset by writing 0. Can be used when ADCADV = "1". Reset by writing 0. Can be used when ADCADV = "1". Reset when ADBUFx is read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-35 APPENDIX I/O MAP 0x48148-0x48152 Register name Address A/D Ch.0 conversion result buffer register (pAD_CH0_BUF) A/D Ch.1 conversion result buffer register (pAD_CH1_BUF) A/D Ch.2 conversion result buffer register (pAD_CH2_BUF) A/D Ch.3 conversion result buffer register (pAD_CH3_BUF) A/D Ch.4 conversion result buffer register (pAD_CH4_BUF) A/D Ch.5 conversion result buffer register (pAD_CH5_BUF) APP-36 Bit A/D Converter Name 0048148 D15-10 - D9 AD0BUF9 (HW) D8 AD0BUF8 D7 AD0BUF7 D6 AD0BUF6 D5 AD0BUF5 D4 AD0BUF4 D3 AD0BUF3 D2 AD0BUF2 D1 AD0BUF1 D0 AD0BUF0 004814A D15-10 - D9 AD1BUF9 (HW) D8 AD1BUF8 D7 AD1BUF7 D6 AD1BUF6 D5 AD1BUF5 D4 AD1BUF4 D3 AD1BUF3 D2 AD1BUF2 D1 AD1BUF1 D0 AD1BUF0 004814C D15-10 - D9 AD2BUF9 (HW) D8 AD2BUF8 D7 AD2BUF7 D6 AD2BUF6 D5 AD2BUF5 D4 AD2BUF4 D3 AD2BUF3 D2 AD2BUF2 D1 AD2BUF1 D0 AD2BUF0 004814E D15-10 - D9 AD3BUF9 (HW) D8 AD3BUF8 D7 AD3BUF7 D6 AD3BUF6 D5 AD3BUF5 D4 AD3BUF4 D3 AD3BUF3 D2 AD3BUF2 D1 AD3BUF1 D0 AD3BUF0 0048150 D15-10 - D9 AD4BUF9 (HW) D8 AD4BUF8 D7 AD4BUF7 D6 AD4BUF6 D5 AD4BUF5 D4 AD4BUF4 D3 AD4BUF3 D2 AD4BUF2 D1 AD4BUF1 D0 AD4BUF0 0048152 D15-10 - D9 AD5BUF9 (HW) D8 AD5BUF8 D7 AD5BUF7 D6 AD5BUF6 D5 AD5BUF5 D4 AD5BUF4 D3 AD5BUF3 D2 AD5BUF2 D1 AD5BUF1 D0 AD5BUF0 Function Setting Init. R/W Remarks reserved A/D Ch.0 converted data AD0BUF9 = MSB AD0BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.1 converted data AD1BUF9 = MSB AD1BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.2 converted data AD2BUF9 = MSB AD2BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.3 converted data AD3BUF9 = MSB AD3BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.4 converted data AD4BUF9 = MSB AD4BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.5 converted data AD5BUF9 = MSB AD5BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". EPSON S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48154-0x4815E Register name Address A/D Ch.6 conversion result buffer register (pAD_CH6_BUF) A/D Ch.7 conversion result buffer register (pAD_CH7_BUF) A/D upper limit value register (pAD_UPPER) A/D lower limit value register (pAD_LOWER) A/D conversion complete interrupt mask register (pAD_CH07 _INTMASK) Bit A/D Converter Name 0048154 D15-10 - D9 AD6BUF9 (HW) D8 AD6BUF8 D7 AD6BUF7 D6 AD6BUF6 D5 AD6BUF5 D4 AD6BUF4 D3 AD6BUF3 D2 AD6BUF2 D1 AD6BUF1 D0 AD6BUF0 0048156 D15-10 - D9 AD7BUF9 (HW) D8 AD7BUF8 D7 AD7BUF7 D6 AD7BUF6 D5 AD7BUF5 D4 AD7BUF4 D3 AD7BUF3 D2 AD7BUF2 D1 AD7BUF1 D0 AD7BUF0 0048158 D15-10 - D9 ADUPR9 (HW) D8 ADUPR8 D7 ADUPR7 D6 ADUPR6 D5 ADUPR5 D4 ADUPR4 D3 ADUPR3 D2 ADUPR2 D1 ADUPR1 D0 ADUPR0 004815A D15-10 - D9 ADLWR9 (HW) D8 ADLWR8 D7 ADLWR7 D6 ADLWR6 D5 ADLWR5 D4 ADLWR4 D3 ADLWR3 D2 ADLWR2 D1 ADLWR1 D0 ADLWR0 004815C D15-8 - D7 INTMASK7 (HW) D6 INTMASK6 D5 INTMASK5 D4 INTMASK4 D3 INTMASK3 D2 INTMASK2 D1 INTMASK1 D0 INTMASK0 Function Setting Remarks reserved A/D Ch.6 converted data AD6BUF9 = MSB AD6BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D Ch.7 converted data AD7BUF9 = MSB AD7BUF0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - R 0 when being read. Can be used when ADCADV = "1". reserved A/D conversion upper limit value ADUPR9 = MSB ADUPR0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - 0 when being read. R/W Can be used when ADCADV = "1". reserved A/D conversion lower limit value ADLWR9 = MSB ADLWR0 = LSB - 0x0 to 0x3FF - 0 0 0 0 0 0 0 0 0 0 - 1 1 1 1 1 1 1 1 - 0 - 0 0 - 0 when being read. R/W Can be used when ADCADV = "1". reserved - Ch.7 conversion-complete int. mask 1 Interrupt 0 Interrupt Ch.6 conversion-complete int. mask enabled mask Ch.5 conversion-complete int. mask Ch.4 conversion-complete int. mask Ch.3 conversion-complete int. mask Ch.2 conversion-complete int. mask Ch.1 conversion-complete int. mask Ch.0 conversion-complete int. mask reserved A/D converter 004815E D15-9 - - D8 ADCADV Standard/advanced mode selection 1 Advanced 0 Standard (HW) mode select/ reserved D7-6 - internal status - Internal status D5 ISTATE1 register Status ISTATE[1:0] D4 ISTATE0 (pAD_ADVMODE) Converting 11 reserved 10 Sampling 01 Idle 00 D3 ICOUNTER3 Internal counter value 0 to 15 D2 ICOUNTER2 D1 ICOUNTER1 D0 ICOUNTER0 S1C33401 TECHNICAL MANUAL Init. R/W EPSON 0 0 0 0 I - 0 when being read. R/W Can be used when R/W ADCADV = "1". R/W R/W R/W R/W R/W R/W - Do not write 1. R/W - 0 when being read. R R APP I/Omap APP-37 APPENDIX I/O MAP 0x48160-0x48166 Register name Address 0048160 Watchdog (HW) timer writeprotect register (pWD_WP) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048162 D15-7 Watchdog D6 (HW) timer enable D5 register D4 (pWD_EN) D3-2 D1 D0 0048164 D15 Watchdog D14 (HW) timer D13 comparison D12 data setup D11 register 0 D10 (pWD_COMP_LOW) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048166 D15-14 Watchdog D13 (HW) timer D12 comparison D11 data setup D10 register 1 D9 (pWD_COMP_HIGH) D8 D7 D6 D5 D4 D3 D2 D1 D0 APP-38 Watchdog Timer Name WDPTC15 WDPTC14 WDPTC13 WDPTC12 WDPTC11 WDPTC10 WDPTC9 WDPTC8 WDPTC7 WDPTC6 WDPTC5 WDPTC4 WDPTC3 WDPTC2 WDPTC1 WDPTC0 - CLKSEL CLKEN RUNSTP - NMIEN RESEN CMPDT15 CMPDT14 CMPDT13 CMPDT12 CMPDT11 CMPDT10 CMPDT9 CMPDT8 CMPDT7 CMPDT6 CMPDT5 CMPDT4 CMPDT3 CMPDT2 CMPDT1 CMPDT0 - CMPDT29 CMPDT28 CMPDT27 CMPDT26 CMPDT25 CMPDT24 CMPDT23 CMPDT22 CMPDT21 CMPDT20 CMPDT19 CMPDT18 CMPDT17 CMPDT16 Function Setting Init. R/W Watchdog timer register writeprotect Writing 0x0096 removes the write protection of the watchdog timer enable and comparison data registers (0x48162-0x48166). Writing another value set the write protection. X X X X X X X X X X X X X X X X reserved Watchdog timer input clock select Watchdog timer clock output control Watchdog timer Run/Stop control reserved Watchdog timer NMI enable Watchdog timer RESET enable Watchdog timer comparison data CMPDT0 = LSB - 1 External clock 0 Internal clock 1 On 0 Off 1 Run 0 Stop - 1 Enabled 0 Disabled 1 Enabled 0 Disabled 0x0 to 0x3FFFFFFF (low-order 16 bits) reserved Watchdog timer comparison data CMPDT29 = MSB - 0x0 to 0x3FFFFFFF (high-order 14 bits) - 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPSON W Remarks 0 when being read. - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48168-0x4816C Register name Address 0048168 Watchdog (HW) timer count register 0 (pWD_CNT_LOW) Watchdog Timer Name Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004816A D15-14 Watchdog D13 (HW) timer count D12 register 1 D11 (pWD_CNT_HIGH) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Watchdog timer 004816C D15-1 control register (HW) D0 (pWD_CNTL) CTRDT15 CTRDT14 CTRDT13 CTRDT12 CTRDT11 CTRDT10 CTRDT9 CTRDT8 CTRDT7 CTRDT6 CTRDT5 CTRDT4 CTRDT3 CTRDT2 CTRDT1 CTRDT0 - CTRDT29 CTRDT28 CTRDT27 CTRDT26 CTRDT25 CTRDT24 CTRDT23 CTRDT22 CTRDT21 CTRDT20 CTRDT19 CTRDT18 CTRDT17 CTRDT16 - Function Setting Watchdog timer counter data CTRDT0 = LSB 0x0 to 0x3FFFFFFF (low-order 16 bits) reserved Watchdog timer counter data CTRDT29 = MSB - 0x0 to 0x3FFFFFFF (high-order 14 bits) - reserved WDRESEN Watchdog timer reset 1 Reset 0 Invalid Init. R/W I Remarks X X X X X X X X X X X X X X X X - X X X X X X X X X X X X X X R - R 0 when being read. - - 0 when being read. 0 W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-39 APPENDIX I/O MAP 0x48180-0x48186 Register name Address 16-bit timer 0 comparison data A setup register (pT16_CR0A) 0048180 (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048182 D15 16-bit timer 0 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR0B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048184 D15 16-bit timer 0 D14 (HW) counter data D13 register D12 (pT16_TC0) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048186 D15-9 16-bit timer 0 D8 (HW) control register D7 (pT16_CTL0) D6 D5 D4 D3 D2 D1 D0 APP-40 16-bit Timer Name Function Setting CR0A15 CR0A14 CR0A13 CR0A12 CR0A11 CR0A10 CR0A9 CR0A8 CR0A7 CR0A6 CR0A5 CR0A4 CR0A3 CR0A2 CR0A1 CR0A0 CR0B15 CR0B14 CR0B13 CR0B12 CR0B11 CR0B10 CR0B9 CR0B8 CR0B7 CR0B6 CR0B5 CR0B4 CR0B3 CR0B2 CR0B1 CR0B0 TC015 TC014 TC013 TC012 TC011 TC010 TC09 TC08 TC07 TC06 TC05 TC04 TC03 TC02 TC01 TC00 - INITOL0 (TMODE0) SELFM0 SELCRB0 OUTINV0 CKSL0 PTM0 PRESET0 PRUN0 16-bit timer 0 comparison data A CR0A15 = MSB CR0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 comparison data B CR0B15 = MSB CR0B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 0 counter data TC015 = MSB TC00 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. reserved 16-bit timer 0 initial output level (reserved for 16-bit timer 0 test) 16-bit timer 0 fine mode selection 16-bit timer 0 comparison buffer 16-bit timer 0 output inversion 16-bit timer 0 input clock selection 16-bit timer 0 clock output control 16-bit timer 0 reset 16-bit timer 0 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48188-0x4818E Register name Address 16-bit timer 1 comparison data A setup register (pT16_CR1A) 0048188 (HW) 16-bit Timer Name Function Setting CR1A15 CR1A14 CR1A13 CR1A12 CR1A11 CR1A10 CR1A9 CR1A8 CR1A7 CR1A6 CR1A5 CR1A4 CR1A3 CR1A2 CR1A1 CR1A0 CR1B15 CR1B14 CR1B13 CR1B12 CR1B11 CR1B10 CR1B9 CR1B8 CR1B7 CR1B6 CR1B5 CR1B4 CR1B3 CR1B2 CR1B1 CR1B0 TC115 TC114 TC113 TC112 TC111 TC110 TC19 TC18 TC17 TC16 TC15 TC14 TC13 TC12 TC11 TC10 - INITOL1 (TMODE1) SELFM1 SELCRB1 OUTINV1 CKSL1 PTM1 PRESET1 PRUN1 16-bit timer 1 comparison data A CR1A15 = MSB CR1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 1 comparison data B CR1B15 = MSB CR1B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 1 counter data TC115 = MSB TC10 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004818A D15 16-bit timer 1 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR1B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004818C D15 16-bit timer 1 D14 (HW) counter data D13 register D12 (pT16_TC1) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004818E D15-9 16-bit timer 1 D8 (HW) control register D7 (pT16_CTL1) D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 1 initial output level (reserved for 16-bit timer 1 test) 16-bit timer 1 fine mode selection 16-bit timer 1 comparison buffer 16-bit timer 1 output inversion 16-bit timer 1 input clock selection 16-bit timer 1 clock output control 16-bit timer 1 reset 16-bit timer 1 Run/Stop control 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-41 APPENDIX I/O MAP 0x48190-0x48196 Register name Address 16-bit timer 2 comparison data A setup register (pT16_CR2A) 0048190 (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048192 D15 16-bit timer 2 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR2B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048194 D15 16-bit timer 2 D14 (HW) counter data D13 register D12 (pT16_TC2) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048196 D15-9 16-bit timer 2 D8 (HW) control register D7 (pT16_CTL2) D6 D5 D4 D3 D2 D1 D0 APP-42 16-bit Timer Name Function Setting CR2A15 CR2A14 CR2A13 CR2A12 CR2A11 CR2A10 CR2A9 CR2A8 CR2A7 CR2A6 CR2A5 CR2A4 CR2A3 CR2A2 CR2A1 CR2A0 CR2B15 CR2B14 CR2B13 CR2B12 CR2B11 CR2B10 CR2B9 CR2B8 CR2B7 CR2B6 CR2B5 CR2B4 CR2B3 CR2B2 CR2B1 CR2B0 TC215 TC214 TC213 TC212 TC211 TC210 TC29 TC28 TC27 TC26 TC25 TC24 TC23 TC22 TC21 TC20 - INITOL2 (TMODE2) SELFM2 SELCRB2 OUTINV2 CKSL2 PTM2 PRESET2 PRUN2 16-bit timer 2 comparison data A CR2A15 = MSB CR2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 comparison data B CR2B15 = MSB CR2B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 2 counter data TC215 = MSB TC20 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. reserved 16-bit timer 2 initial output level (reserved for 16-bit timer 2 test) 16-bit timer 2 fine mode selection 16-bit timer 2 comparison buffer 16-bit timer 2 output inversion 16-bit timer 2 input clock selection 16-bit timer 2 clock output control 16-bit timer 2 reset 16-bit timer 2 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48198-0x4819E Register name Address 16-bit timer 3 comparison data A setup register (pT16_CR3A) 0048198 (HW) 16-bit Timer Name Function Setting CR3A15 CR3A14 CR3A13 CR3A12 CR3A11 CR3A10 CR3A9 CR3A8 CR3A7 CR3A6 CR3A5 CR3A4 CR3A3 CR3A2 CR3A1 CR3A0 CR3B15 CR3B14 CR3B13 CR3B12 CR3B11 CR3B10 CR3B9 CR3B8 CR3B7 CR3B6 CR3B5 CR3B4 CR3B3 CR3B2 CR3B1 CR3B0 TC315 TC314 TC313 TC312 TC311 TC310 TC39 TC38 TC37 TC36 TC35 TC34 TC33 TC32 TC31 TC30 - INITOL3 (TMODE3) SELFM3 SELCRB3 OUTINV3 CKSL3 PTM3 PRESET3 PRUN3 16-bit timer 3 comparison data A CR3A15 = MSB CR3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 3 comparison data B CR3B15 = MSB CR3B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 3 counter data TC315 = MSB TC30 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004819A D15 16-bit timer 3 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR3B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004819C D15 16-bit timer 3 D14 (HW) counter data D13 register D12 (pT16_TC3) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004819E D15-9 16-bit timer 3 D8 (HW) control register D7 (pT16_CTL3) D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 3 initial output level (reserved for 16-bit timer 3 test) 16-bit timer 3 fine mode selection 16-bit timer 3 comparison buffer 16-bit timer 3 output inversion 16-bit timer 3 input clock selection 16-bit timer 3 clock output control 16-bit timer 3 reset 16-bit timer 3 Run/Stop control 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-43 APPENDIX I/O MAP 0x481A0-0x481A6 Register name Address 16-bit timer 4 comparison data A setup register (pT16_CR4A) 00481A0 (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481A2 D15 16-bit timer 4 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR4B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481A4 D15 16-bit timer 4 D14 (HW) counter data D13 register D12 (pT16_TC4) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481A6 D15-9 16-bit timer 4 D8 (HW) control register D7 (pT16_CTL4) D6 D5 D4 D3 D2 D1 D0 APP-44 16-bit Timer Name Function Setting CR4A15 CR4A14 CR4A13 CR4A12 CR4A11 CR4A10 CR4A9 CR4A8 CR4A7 CR4A6 CR4A5 CR4A4 CR4A3 CR4A2 CR4A1 CR4A0 CR4B15 CR4B14 CR4B13 CR4B12 CR4B11 CR4B10 CR4B9 CR4B8 CR4B7 CR4B6 CR4B5 CR4B4 CR4B3 CR4B2 CR4B1 CR4B0 TC415 TC414 TC413 TC412 TC411 TC410 TC49 TC48 TC47 TC46 TC45 TC44 TC43 TC42 TC41 TC40 - INITOL4 (TMODE4) SELFM4 SELCRB4 OUTINV4 CKSL4 PTM4 PRESET4 PRUN4 16-bit timer 4 comparison data A CR4A15 = MSB CR4A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 comparison data B CR4B15 = MSB CR4B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 4 counter data TC415 = MSB TC40 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. reserved 16-bit timer 4 initial output level (reserved for 16-bit timer 4 test) 16-bit timer 4 fine mode selection 16-bit timer 4 comparison buffer 16-bit timer 4 output inversion 16-bit timer 4 input clock selection 16-bit timer 4 clock output control 16-bit timer 4 reset 16-bit timer 4 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x481A8-0x481AE Register name Address 16-bit timer 5 comparison data A setup register (pT16_CR5A) 00481A8 (HW) 16-bit Timer Name Function Setting CR5A15 CR5A14 CR5A13 CR5A12 CR5A11 CR5A10 CR5A9 CR5A8 CR5A7 CR5A6 CR5A5 CR5A4 CR5A3 CR5A2 CR5A1 CR5A0 CR5B15 CR5B14 CR5B13 CR5B12 CR5B11 CR5B10 CR5B9 CR5B8 CR5B7 CR5B6 CR5B5 CR5B4 CR5B3 CR5B2 CR5B1 CR5B0 TC515 TC514 TC513 TC512 TC511 TC510 TC59 TC58 TC57 TC56 TC55 TC54 TC53 TC52 TC51 TC50 - INITOL5 (TMODE5) SELFM5 SELCRB5 OUTINV5 CKSL5 PTM5 PRESET5 PRUN5 16-bit timer 5 comparison data A CR5A15 = MSB CR5A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 5 comparison data B CR5B15 = MSB CR5B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 5 counter data TC515 = MSB TC50 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481AA D15 16-bit timer 5 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR5B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481AC D15 16-bit timer 5 D14 (HW) counter data D13 register D12 (pT16_TC5) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481AE D15-9 16-bit timer 5 D8 (HW) control register D7 (pT16_CTL5) D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 5 initial output level (reserved for 16-bit timer 5 test) 16-bit timer 5 fine mode selection 16-bit timer 5 comparison buffer 16-bit timer 5 output inversion 16-bit timer 5 input clock selection 16-bit timer 5 clock output control 16-bit timer 5 reset 16-bit timer 5 Run/Stop control 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-45 APPENDIX I/O MAP 0x481B0-0x481B6 Register name Address 16-bit timer 6 comparison data A setup register (pT16_CR6A) 00481B0 (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481B2 D15 16-bit timer 6 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR6B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481B4 D15 16-bit timer 6 D14 (HW) counter data D13 register D12 (pT16_TC6) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481B6 D15-9 16-bit timer 6 D8 (HW) control register D7 (pT16_CTL6) D6 D5 D4 D3 D2 D1 D0 APP-46 16-bit Timer Name Function Setting CR6A15 CR6A14 CR6A13 CR6A12 CR6A11 CR6A10 CR6A9 CR6A8 CR6A7 CR6A6 CR6A5 CR6A4 CR6A3 CR6A2 CR6A1 CR6A0 CR6B15 CR6B14 CR6B13 CR6B12 CR6B11 CR6B10 CR6B9 CR6B8 CR6B7 CR6B6 CR6B5 CR6B4 CR6B3 CR6B2 CR6B1 CR6B0 TC615 TC614 TC613 TC612 TC611 TC610 TC69 TC68 TC67 TC66 TC65 TC64 TC63 TC62 TC61 TC60 - INITOL6 (TMODE6) SELFM6 SELCRB6 OUTINV6 CKSL6 PTM6 PRESET6 PRUN6 16-bit timer 6 comparison data A CR6A15 = MSB CR6A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 6 comparison data B CR6B15 = MSB CR6B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 6 counter data TC615 = MSB TC60 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. reserved 16-bit timer 6 initial output level (reserved for 16-bit timer 6 test) 16-bit timer 6 fine mode selection 16-bit timer 6 comparison buffer 16-bit timer 6 output inversion 16-bit timer 6 input clock selection 16-bit timer 6 clock output control 16-bit timer 6 reset 16-bit timer 6 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x481B8-0x481BE Register name Address 16-bit timer 7 comparison data A setup register (pT16_CR7A) 00481B8 (HW) 16-bit Timer Name Function Setting CR7A15 CR7A14 CR7A13 CR7A12 CR7A11 CR7A10 CR7A9 CR7A8 CR7A7 CR7A6 CR7A5 CR7A4 CR7A3 CR7A2 CR7A1 CR7A0 CR7B15 CR7B14 CR7B13 CR7B12 CR7B11 CR7B10 CR7B9 CR7B8 CR7B7 CR7B6 CR7B5 CR7B4 CR7B3 CR7B2 CR7B1 CR7B0 TC715 TC714 TC713 TC712 TC711 TC710 TC79 TC78 TC77 TC76 TC75 TC74 TC73 TC72 TC71 TC70 - INITOL7 (TMODE7) SELFM7 SELCRB7 OUTINV7 CKSL7 PTM7 PRESET7 PRUN7 16-bit timer 7 comparison data A CR7A15 = MSB CR7A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 7 comparison data B CR7B15 = MSB CR7B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 7 counter data TC715 = MSB TC70 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481BA D15 16-bit timer 7 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR7B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481BC D15 16-bit timer 7 D14 (HW) counter data D13 register D12 (pT16_TC7) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481BE D15-9 16-bit timer 7 D8 (HW) control register D7 (pT16_CTL7) D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 7 initial output level (reserved for 16-bit timer 7 test) 16-bit timer 7 fine mode selection 16-bit timer 7 comparison buffer 16-bit timer 7 output inversion 16-bit timer 7 input clock selection 16-bit timer 7 clock output control 16-bit timer 7 reset 16-bit timer 7 Run/Stop control 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-47 APPENDIX I/O MAP 0x481C0-0x481C6 Register name Address 16-bit timer 8 comparison data A setup register (pT16_CR8A) 00481C0 (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481C2 D15 16-bit timer 8 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR8B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481C4 D15 16-bit timer 8 D14 (HW) counter data D13 register D12 (pT16_TC8) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481C6 D15-9 16-bit timer 8 D8 (HW) control register D7 (pT16_CTL8) D6 D5 D4 D3 D2 D1 D0 APP-48 16-bit Timer Name Function Setting CR8A15 CR8A14 CR8A13 CR8A12 CR8A11 CR8A10 CR8A9 CR8A8 CR8A7 CR8A6 CR8A5 CR8A4 CR8A3 CR8A2 CR8A1 CR8A0 CR8B15 CR8B14 CR8B13 CR8B12 CR8B11 CR8B10 CR8B9 CR8B8 CR8B7 CR8B6 CR8B5 CR8B4 CR8B3 CR8B2 CR8B1 CR8B0 TC815 TC814 TC813 TC812 TC811 TC810 TC89 TC88 TC87 TC86 TC85 TC84 TC83 TC82 TC81 TC80 - INITOL8 (TMODE8) SELFM8 SELCRB8 OUTINV8 CKSL8 PTM8 PRESET8 PRUN8 16-bit timer 8 comparison data A CR8A15 = MSB CR8A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 8 comparison data B CR8B15 = MSB CR8B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 8 counter data TC815 = MSB TC80 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. reserved 16-bit timer 8 initial output level (reserved for 16-bit timer 8 test) 16-bit timer 8 fine mode selection 16-bit timer 8 comparison buffer 16-bit timer 8 output inversion 16-bit timer 8 input clock selection 16-bit timer 8 clock output control 16-bit timer 8 reset 16-bit timer 8 Run/Stop control EPSON 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x481C8-0x481CE Register name Address 16-bit timer 9 comparison data A setup register (pT16_CR9A) 00481C8 (HW) 16-bit Timer Name Function Setting CR9A15 CR9A14 CR9A13 CR9A12 CR9A11 CR9A10 CR9A9 CR9A8 CR9A7 CR9A6 CR9A5 CR9A4 CR9A3 CR9A2 CR9A1 CR9A0 CR9B15 CR9B14 CR9B13 CR9B12 CR9B11 CR9B10 CR9B9 CR9B8 CR9B7 CR9B6 CR9B5 CR9B4 CR9B3 CR9B2 CR9B1 CR9B0 TC915 TC914 TC913 TC912 TC911 TC910 TC99 TC98 TC97 TC96 TC95 TC94 TC93 TC92 TC91 TC90 - INITOL9 (TMODE9) SELFM9 SELCRB9 OUTINV9 CKSL9 PTM9 PRESET9 PRUN9 16-bit timer 9 comparison data A CR9A15 = MSB CR9A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 9 comparison data B CR9B15 = MSB CR9B0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W 16-bit timer 9 counter data TC915 = MSB TC90 = LSB 0 to 65535 X X X X X X X X X X X X X X X X - 0 0 0 0 0 0 0 0 0 R/W Data can be written only in advanced mode. Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481CA D15 16-bit timer 9 D14 (HW) comparison D13 data B setup D12 register D11 (pT16_CR9B) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481CC D15 16-bit timer 9 D14 (HW) counter data D13 register D12 (pT16_TC9) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 00481CE D15-9 16-bit timer 9 D8 (HW) control register D7 (pT16_CTL9) D6 D5 D4 D3 D2 D1 D0 reserved 16-bit timer 9 initial output level (reserved for 16-bit timer 9 test) 16-bit timer 9 fine mode selection 16-bit timer 9 comparison buffer 16-bit timer 9 output inversion 16-bit timer 9 input clock selection 16-bit timer 9 clock output control 16-bit timer 9 reset 16-bit timer 9 Run/Stop control 1 1 1 1 1 1 1 1 1 - 0 High Test mode 0 Fine mode 0 Enabled 0 0 Invert External clock 0 0 On 0 Reset Run 0 Init. R/W Low Normal Normal Disabled Normal Internal clock Off Invalid Stop - R/W R R/W R/W R/W R/W R/W W R/W I Remarks 0 when being read. Advanced mode Do not write 1. 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-49 APPENDIX I/O MAP 0x481D0-0x481D6 16-bit Timer Register name Address Bit Name DA16 Ch.0 register (pDA16_CR0A) 00481D0 (HW) DA16 Ch.1 register (pDA16_CR1A) 00481D2 (HW) DA16 Ch.2 register (pDA16_CR2A) 00481D4 (HW) DA16 Ch.3 register (pDA16_CR3A) 00481D6 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DA0A15 DA0A14 DA0A13 DA0A12 DA0A11 DA0A10 DA0A9 DA0A8 DA0A7 DA0A6 DA0A5 DA0A4 DA0A3 DA0A2 DA0A1 DA0A0 DA1A15 DA1A14 DA1A13 DA1A12 DA1A11 DA1A10 DA1A9 DA1A8 DA1A7 DA1A6 DA1A5 DA1A4 DA1A3 DA1A2 DA1A1 DA1A0 DA2A15 DA2A14 DA2A13 DA2A12 DA2A11 DA2A10 DA2A9 DA2A8 DA2A7 DA2A6 DA2A5 DA2A4 DA2A3 DA2A2 DA2A1 DA2A0 DA3A15 DA3A14 DA3A13 DA3A12 DA3A11 DA3A10 DA3A9 DA3A8 DA3A7 DA3A6 DA3A5 DA3A4 DA3A3 DA3A2 DA3A1 DA3A0 APP-50 Function Setting Init. R/W Remarks DA16 Ch.0 comparison data A DA0A15 = MSB DA0A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W Advanced mode DA16 Ch.1 comparison data A DA1A15 = MSB DA1A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W Advanced mode DA16 Ch.2 comparison data A DA2A15 = MSB DA2A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W Advanced mode DA16 Ch.3 comparison data A DA3A15 = MSB DA3A0 = LSB 0 to 65535 X X X X X X X X X X X X X X X X R/W Advanced mode EPSON S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x481DC-0x481DE Register name Address Bit 16-bit Timer Name 00481DC D15-10 - Count pause D9 PAUSE9 (HW) register D8 PAUSE8 (pT16_CNT_PAUSE) D7 PAUSE7 D6 PAUSE6 D5 PAUSE5 D4 PAUSE4 D3 PAUSE3 D2 PAUSE2 D1 PAUSE1 D0 PAUSE0 00481DE D15-1 - 16-bit timer (HW) STD/ADV mode D0 T16ADV select register (pT16_ADVMODE) Function reserved 16-bit timer 9 count pause 16-bit timer 8 count pause 16-bit timer 7 count pause 16-bit timer 6 count pause 16-bit timer 5 count pause 16-bit timer 4 count pause 16-bit timer 3 count pause 16-bit timer 2 count pause 16-bit timer 1 count pause 16-bit timer 0 count pause reserved Standard mode/advanced mode select Setting - 1 Pause 0 Count - 1 Advanced mode 0 Standard mode Init. R/W Remarks - 0 0 0 0 0 0 0 0 0 0 - - 0 when being read. R/W Advanced mode R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 R/W - I Writing 1 not allowed. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-51 APPENDIX I/O MAP 0x48200-0x48205 Register name Address IDMA base address register 0 (pIDMABASE) 0048200 (HW) IDMA base address register 1 0048202 (HW) IDMA start register (pIDMA_START) 0048204 (B) IDMA enable register (pIDMA_EN) 0048205 (B) APP-52 Intelligent DMA Bit Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7-1 DBASEL15 DBASEL14 DBASEL13 DBASEL12 DBASEL11 DBASEL10 DBASEL9 DBASEL8 DBASEL7 DBASEL6 DBASEL5 DBASEL4 DBASEL3 DBASEL2 DBASEL1 DBASEL0 DBASEH15 DBASEH14 DBASEH13 DBASEH12 DBASEH11 DBASEH10 DBASEH9 DBASEH8 DBASEH7 DBASEH6 DBASEH5 DBASEH4 DBASEH3 DBASEH2 DBASEH1 DBASEH0 IDMA base address low-order 16 bits (Initial value: 0x200003A0) DSTART DCHN6 DCHN5 DCHN4 DCHN3 DCHN2 DCHN1 DCHN0 - IDMA start IDMA channel number D0 IDMAEN IDMA enable (for software trigger) 1 Enabled Function Setting IDMA base address high-order 16 bits (Initial value: 0x200003A0) 1 IDMA start 0 Stop 0 to 127 - reserved EPSON 0 Disabled Init. R/W 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 R/W R/W - - 0 R/W Remarks Fix at 0. R/W 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48220-0x48226 High-Speed DMA Register name Address Bit Name 0048220 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TC0_L7 TC0_L6 TC0_L5 TC0_L4 TC0_L3 TC0_L2 TC0_L1 TC0_L0 BLKLEN07 BLKLEN06 BLKLEN05 BLKLEN04 BLKLEN03 BLKLEN02 BLKLEN01 BLKLEN00 Ch.0 transfer counter[7:0] (block transfer mode) D15 D14 DUALM0 D0DIR Ch.0 address mode selection D) Invalid S) Ch.0 transfer direction control reserved Ch.0 transfer counter[15:8] (block transfer mode) HSDMA Ch.0 transfer counter register (pHS0_CNT) 0048222 HSDMA Ch.0 (HW) control register Note: D) Dual address mode S) Single address mode D13-8 D7 D6 D5 D4 D3 D2 D1 D0 0048224 D15 HSDMA Ch.0 D14 (HW) low-order D13 source address D12 setup register D11 (pHS0_SADR) D10 Note: D9 D) Dual address D8 mode D7 S) Single D6 address D5 mode D4 D3 D2 D1 D0 0048226 D15 HSDMA Ch.0 D14 (HW) high-order D13 source address D12 setup register Note: D) Dual address mode S) Single address mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - TC0_H7 TC0_H6 TC0_H5 TC0_H4 TC0_H3 TC0_H2 TC0_H1 TC0_H0 S0ADRL15 S0ADRL14 S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 - DATSIZE0 S0IN1 S0IN0 Function Setting Ch.0 transfer counter[15:8] (single/successive transfer mode) Ch.0 block length (block transfer mode) Ch.0 transfer counter[7:0] (single/successive transfer mode) 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.0 transfer counter[23:16] (single/successive transfer mode) D) Ch.0 source address[15:0] S) Ch.0 memory address[15:0] reserved Ch.0 transfer data size D) Ch.0 source address control S) Ch.0 memory address control S0ADRH11 D) Ch.0 source address[27:16] S0ADRH10 S) Ch.0 memory address[27:16] S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 - 1 Half word S0IN[1:0] 11 10 01 00 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W I Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 - 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 R/W - R/W - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W - 0 when being read. R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-53 APPENDIX I/O MAP 0x48228-0x48230 High-Speed DMA Name Register name Address Bit 0048228 (HW) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D0ADRL15 D) Ch.0 destination address[15:0] D0ADRL14 S) Invalid D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 D0MOD1 Ch.0 transfer mode D0MOD0 D13 D12 D0IN1 D0IN0 HSDMA Ch.0 low-order destination address setup register (pHS0_DADR) Note: D) Dual address mode S) Single address mode HSDMA Ch.0 high-order destination address setup register Note: D) Dual address mode S) Single address mode 004822A (HW) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004822C D15-1 HSDMA Ch.0 (HW) enable register D0 (pHS0_EN) HSDMA Ch.0 004822E D15-1 trigger flag (HW) D0 register (pHS0_TF) HSDMA Ch.1 0048230 D15 D14 transfer (HW) D13 counter D12 register D11 (pHS1_CNT) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 APP-54 Function D) Ch.0 destination address control S) Invalid Setting D0MOD[1:0] 11 10 01 00 D0IN[1:0] 11 10 01 00 Init. R/W Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed D0ADRH11 D) Ch.0 destination D0ADRH10 address[27:16] D0ADRH9 S) Invalid D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 - reserved HS0_EN - Ch.0 enable reserved 1 Enable HS0_TF Ch.0 trigger flag clear (writing) Ch.0 trigger flag status (reading) Ch.1 transfer counter[7:0] (block transfer mode) 1 Clear 1 Set TC1_L7 TC1_L6 TC1_L5 TC1_L4 TC1_L3 TC1_L2 TC1_L1 TC1_L0 BLKLEN17 BLKLEN16 BLKLEN15 BLKLEN14 BLKLEN13 BLKLEN12 BLKLEN11 BLKLEN10 - 0 Disable - Ch.1 transfer counter[15:8] (single/successive transfer mode) Ch.1 block length (block transfer mode) Ch.1 transfer counter[7:0] (single/successive transfer mode) EPSON 0 No operation 0 Cleared 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W - - Remarks R/W 0 R/W - - 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 when being read. 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48232-0x48238 High-Speed DMA Register name Address Bit Name 0048232 HSDMA Ch.1 (HW) control register D15 D14 DUALM1 D1DIR Note: D) Dual address mode S) Single address mode D13-8 D7 D6 D5 D4 D3 D2 D1 D0 0048234 D15 HSDMA Ch.1 D14 (HW) low-order D13 source address D12 setup register D11 (pHS1_SADR) D10 Note: D9 D) Dual address D8 mode D7 S) Single D6 address D5 mode D4 D3 D2 D1 D0 0048236 D15 HSDMA Ch.1 D14 (HW) high-order D13 source address D12 setup register Note: D) Dual address mode S) Single address mode HSDMA Ch.1 low-order destination address setup register (pHS1_DADR) Note: D) Dual address mode S) Single address mode 0048238 (HW) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - TC1_H7 TC1_H6 TC1_H5 TC1_H4 TC1_H3 TC1_H2 TC1_H1 TC1_H0 S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 - DATSIZE1 S1IN1 S1IN0 S1ADRH11 S1ADRH10 S1ADRH9 S1ADRH8 S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 Function Ch.1 address mode selection D) Invalid S) Ch.1 transfer direction control reserved Ch.1 transfer counter[15:8] (block transfer mode) Setting 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - Ch.1 transfer counter[23:16] (single/successive transfer mode) D) Ch.1 source address[15:0] S) Ch.1 memory address[15:0] reserved Ch.1 transfer data size D) Ch.1 source address control S) Ch.1 memory address control D) Ch.1 source address[27:16] S) Ch.1 memory address[27:16] D) Ch.1 destination address[15:0] S) Invalid - 1 Half word S1IN[1:0] 11 10 01 00 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W I Remarks 0 - 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 R/W - R/W - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W - 0 when being read. R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-55 APPENDIX I/O MAP 0x4823A-0x48242 High-Speed DMA Register name Address Bit Name 004823A (HW) D15 D14 D1MOD1 D1MOD0 Ch.1 transfer mode D13 D12 D1IN1 D1IN0 D) Ch.1 destination address control S) Invalid HSDMA Ch.1 high-order destination address setup register Note: D) Dual address mode S) Single address mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004823C D15-1 HSDMA Ch.1 (HW) enable register D0 (pHS1_EN) HSDMA Ch.1 004823E D15-1 trigger flag (HW) D0 register (pHS1_TF) HSDMA Ch.2 0048240 D15 D14 transfer (HW) D13 counter D12 register D11 (pHS2_CNT) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HSDMA Ch.2 0048242 D15 D14 control register (HW) Note: D) Dual address mode S) Single address mode APP-56 D13-8 D7 D6 D5 D4 D3 D2 D1 D0 Function Setting D1MOD[1:0] 11 10 01 00 D1IN[1:0] 11 10 01 00 Init. R/W Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed D1ADRH11 D) Ch.1 destination D1ADRH10 address[27:16] D1ADRH9 S) Invalid D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 - reserved HS1_EN - Ch.1 enable reserved 1 Enable HS1_TF Ch.1 trigger flag clear (writing) Ch.1 trigger flag status (reading) Ch.2 transfer counter[7:0] (block transfer mode) 1 Clear 1 Set TC2_L7 TC2_L6 TC2_L5 TC2_L4 TC2_L3 TC2_L2 TC2_L1 TC2_L0 BLKLEN27 BLKLEN26 BLKLEN25 BLKLEN24 BLKLEN23 BLKLEN22 BLKLEN21 BLKLEN20 DUALM2 D2DIR - TC2_H7 TC2_H6 TC2_H5 TC2_H4 TC2_H3 TC2_H2 TC2_H1 TC2_H0 - 0 Disable - 0 No operation 0 Cleared Ch.2 transfer counter[15:8] (single/successive transfer mode) Ch.2 block length (block transfer mode) Ch.2 transfer counter[7:0] (single/successive transfer mode) Ch.2 address mode selection D) Invalid S) Ch.2 transfer direction control reserved Ch.2 transfer counter[15:8] (block transfer mode) Ch.2 transfer counter[23:16] (single/successive transfer mode) EPSON 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - 0 0 R/W 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W - - Remarks 0 when being read. 0 R/W - - 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 - 0 - 0 0 0 0 0 0 0 0 R/W - R/W - 0 when being read. R/W 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48244-0x48248 High-Speed DMA Register name Address Bit Name 0048244 HSDMA Ch.2 (HW) low-order source address setup register (pHS2_SADR) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 - DATSIZE2 S2IN1 S2IN0 D) Ch.2 source address[15:0] S) Ch.2 memory address[15:0] D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRH11 S2ADRH10 S2ADRH9 S2ADRH8 S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 D) Ch.2 source address[27:16] S) Ch.2 memory address[27:16] Note: D) Dual address mode S) Single address mode 0048246 HSDMA Ch.2 (HW) high-order source address setup register Note: D) Dual address mode S) Single address mode HSDMA Ch.2 low-order destination address setup register (pHS2_DADR) Note: D) Dual address mode S) Single address mode 0048248 (HW) Function reserved Ch.2 transfer data size D) Ch.2 source address control S) Ch.2 memory address control D) Ch.2 destination address[15:0] S) Invalid Setting - 1 Half word S2IN[1:0] 11 10 01 00 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W I Remarks - 0 when being read. R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-57 APPENDIX I/O MAP 0x4824A-0x48252 High-Speed DMA Register name Address Bit Name 004824A (HW) D15 D14 D2MOD1 D2MOD0 Ch.2 transfer mode D13 D12 D2IN1 D2IN0 D) Ch.2 destination address control S) Invalid HSDMA Ch.2 high-order destination address setup register Note: D) Dual address mode S) Single address mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004824C D15-1 HSDMA Ch.2 (HW) enable register D0 (pHS2_EN) HSDMA Ch.2 004824E D15-1 trigger flag (HW) D0 register (pHS2_TF) HSDMA Ch.3 0048250 D15 D14 transfer (HW) D13 counter D12 register D11 (pHS3_CNT) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 HSDMA Ch.3 0048252 D15 D14 control register (HW) Note: D) Dual address mode S) Single address mode APP-58 D13-8 D7 D6 D5 D4 D3 D2 D1 D0 Function Setting D2MOD[1:0] 11 10 01 00 D2IN[1:0] 11 10 01 00 Init. R/W Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed D2ADRH11 D) Ch.2 destination D2ADRH10 address[27:16] D2ADRH9 S) Invalid D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 - reserved HS2_EN - Ch.2 enable reserved 1 Enable HS2_TF Ch.2 trigger flag clear (writing) Ch.2 trigger flag status (reading) Ch.3 transfer counter[7:0] (block transfer mode) 1 Clear 1 Set TC3_L7 TC3_L6 TC3_L5 TC3_L4 TC3_L3 TC3_L2 TC3_L1 TC3_L0 BLKLEN37 BLKLEN36 BLKLEN35 BLKLEN34 BLKLEN33 BLKLEN32 BLKLEN31 BLKLEN30 DUALM3 D3DIR - TC3_H7 TC3_H6 TC3_H5 TC3_H4 TC3_H3 TC3_H2 TC3_H1 TC3_H0 - 0 Disable - 0 No operation 0 Cleared Ch.3 transfer counter[15:8] (single/successive transfer mode) Ch.3 block length (block transfer mode) Ch.3 transfer counter[7:0] (single/successive transfer mode) Ch.3 address mode selection D) Invalid S) Ch.3 transfer direction control reserved Ch.3 transfer counter[15:8] (block transfer mode) Ch.3 transfer counter[23:16] (single/successive transfer mode) EPSON 1 Dual addr 0 Single addr - 1 Memory WR 0 Memory RD - 0 0 R/W 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W - - Remarks 0 when being read. 0 R/W - - 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 - 0 - 0 0 0 0 0 0 0 0 R/W - R/W - 0 when being read. R/W 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48254-0x48258 High-Speed DMA Register name Address Bit Name 0048254 HSDMA Ch.3 (HW) low-order source address setup register (pHS3_SADR) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 - DATSIZE3 S3IN1 S3IN0 D) Ch.3 source address[15:0] S) Ch.3 memory address[15:0] D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3ADRH11 S3ADRH10 S3ADRH9 S3ADRH8 S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 D) Ch.3 source address[27:16] S) Ch.3 memory address[27:16] Note: D) Dual address mode S) Single address mode 0048256 HSDMA Ch.3 (HW) high-order source address setup register Note: D) Dual address mode S) Single address mode HSDMA Ch.3 low-order destination address setup register (pHS3_DADR) Note: D) Dual address mode S) Single address mode 0048258 (HW) Function reserved Ch.3 transfer data size D) Ch.3 source address control S) Ch.3 memory address control D) Ch.3 destination address[15:0] S) Invalid Setting - 1 Half word S3IN[1:0] 11 10 01 00 0 Byte Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W I Remarks - 0 when being read. R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-59 APPENDIX I/O MAP 0x4825A-0x48264 High-Speed DMA Register name Address Bit Name 004825A (HW) D15 D14 D3MOD1 D3MOD0 Ch.3 transfer mode D13 D12 D3IN1 D3IN0 D) Ch.3 destination address control S) Invalid HSDMA Ch.3 high-order destination address setup register Note: D) Dual address mode S) Single address mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004825C D15-1 HSDMA Ch.3 (HW) enable register D0 (pHS3_EN) HSDMA Ch.3 004825E D15-1 trigger flag (HW) D0 register (pHS3_TF) HSDMA Ch.0 0048262 D15-6 D5 control register (HW) (pHS0_ADVMODE) D4 for ADV mode Note: D) Dual mode S) Single mode HSDMA Ch.0 0048264 low-order (HW) source address setup register (pHS0_AD_SADR) for ADV mode Note: D) Dual address mode S) Single address mode APP-60 Function Setting D3MOD[1:0] 11 10 01 00 D3IN[1:0] 11 10 01 00 D3ADRH11 D) Ch.3 destination D3ADRH10 address[27:16] D3ADRH9 S) Invalid D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 - reserved HS3_EN - Ch.3 enable reserved 1 Enable HS3_TF Ch.3 trigger flag clear (writing) Ch.3 trigger flag status (reading) 1 Clear 1 Set - 0 Disable - - D0ID 0 No operation 0 Cleared - reserved D) Ch.0 destination address control 1 Decrement 0 S) Invalid (with init.) S0ID D) Ch.0 source address control 1 Decrement 0 S) Ch.0 memory address control (with init.) D3-1 - - reserved D0 WORDSIZE0 Ch.0 transfer data size 1 Word 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Init. R/W Mode Invalid Block Successive Single Inc/dec Inc.(no init) Inc.(init) Dec.(no init) Fixed S0ADRL15 D) Ch.0 source address[15:0] S0ADRL14 S) Ch.0 memory address[15:0] S0ADRL13 S0ADRL12 S0ADRL11 S0ADRL10 S0ADRL9 S0ADRL8 S0ADRL7 S0ADRL6 S0ADRL5 S0ADRL4 S0ADRL3 S0ADRL2 S0ADRL1 S0ADRL0 EPSON D0IN[1:0] setting S0IN[1:0] setting DATSIZE0 setting 0 0 R/W 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 R/W - - Remarks 0 when being read. 0 R/W - - 0 R/W - 0 - 0 when being read. R/W 0 R/W - 0 - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 when being read. S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48266-0x48272 Register name Address 0048266 HSDMA Ch.0 (HW) high-order source address setup register for ADV mode Name Bit D15 D14 D13 D12 D11 D10 Note: D9 D) Dual address D8 mode D7 S) Single D6 address D5 mode D4 D3 D2 D1 D0 0048268 D15 HSDMA Ch.0 D14 (HW) low-order D13 destination D12 address setup D11 register D10 (pHS0_ADV_DADR) D9 for ADV mode D8 Note: D7 D) Dual address D6 mode D5 S) Single D4 address D3 mode D2 D1 D0 HSDMA Ch.0 004826A D15 D14 high-order (HW) D13 destination D12 address setup D11 register D10 for ADV mode D9 Note: D8 D) Dual address D7 mode D6 S) Single D5 address D4 mode D3 D2 D1 D0 HSDMA Ch.1 0048272 D15-6 D5 control register (HW) (pHS1_ADVMODE) D4 for ADV mode Note: D) Dual mode S) Single mode High-Speed DMA S0ADRH15 S0ADRH14 S0ADRH13 S0ADRH12 S0ADRH11 S0ADRH10 S0ADRH9 S0ADRH8 S0ADRH7 S0ADRH6 S0ADRH5 S0ADRH4 S0ADRH3 S0ADRH2 S0ADRH1 S0ADRH0 D0ADRL15 D0ADRL14 D0ADRL13 D0ADRL12 D0ADRL11 D0ADRL10 D0ADRL9 D0ADRL8 D0ADRL7 D0ADRL6 D0ADRL5 D0ADRL4 D0ADRL3 D0ADRL2 D0ADRL1 D0ADRL0 D0ADRH15 D0ADRH14 D0ADRH13 D0ADRH12 D0ADRH11 D0ADRH10 D0ADRH9 D0ADRH8 D0ADRH7 D0ADRH6 D0ADRH5 D0ADRH4 D0ADRH3 D0ADRH2 D0ADRH1 D0ADRH0 Function Setting Init. R/W D) Ch.0 source address[31:16] S) Ch.0 memory address[31:16] D) Ch.0 destination address[15:0] S) Invalid D) Ch.0 destination address[31:16] S) Invalid - D1ID - reserved D) Ch.1 destination address control 1 Decrement 0 S) Invalid (with init.) S1ID D) Ch.1 source address control 1 Decrement 0 S) Ch.1 memory address control (with init.) - D3-1 - reserved D0 WORDSIZE1 Ch.1 transfer data size 1 Word 0 D1IN[1:0] setting S1IN[1:0] setting DATSIZE1 setting I Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W - 0 - 0 when being read. R/W 0 R/W - 0 - 0 when being read. R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-61 APPENDIX I/O MAP 0x48274-0x4827A High-Speed DMA Register name Address Bit Name 0048274 HSDMA Ch.1 (HW) low-order source address setup register (pHS1_AD_SADR) for ADV mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1ADRL15 S1ADRL14 S1ADRL13 S1ADRL12 S1ADRL11 S1ADRL10 S1ADRL9 S1ADRL8 S1ADRL7 S1ADRL6 S1ADRL5 S1ADRL4 S1ADRL3 S1ADRL2 S1ADRL1 S1ADRL0 S1ADRH15 S1ADRH14 S1ADRH13 S1ADRH12 S1ADRH11 S1ADRH10 S1ADRH9 S1ADRH8 S1ADRH7 S1ADRH6 S1ADRH5 S1ADRH4 S1ADRH3 S1ADRH2 S1ADRH1 S1ADRH0 D1ADRL15 D1ADRL14 D1ADRL13 D1ADRL12 D1ADRL11 D1ADRL10 D1ADRL9 D1ADRL8 D1ADRL7 D1ADRL6 D1ADRL5 D1ADRL4 D1ADRL3 D1ADRL2 D1ADRL1 D1ADRL0 D1ADRH15 D1ADRH14 D1ADRH13 D1ADRH12 D1ADRH11 D1ADRH10 D1ADRH9 D1ADRH8 D1ADRH7 D1ADRH6 D1ADRH5 D1ADRH4 D1ADRH3 D1ADRH2 D1ADRH1 D1ADRH0 Note: D) Dual address mode S) Single address mode 0048276 HSDMA Ch.1 (HW) high-order source address setup register for ADV mode Note: D) Dual address mode S) Single address mode HSDMA Ch.1 0048278 low-order (HW) destination address setup register (pHS1_ADV_DADR) for ADV mode Note: D) Dual address mode S) Single address mode HSDMA Ch.1 high-order destination address setup register for ADV mode Note: D) Dual address mode S) Single address mode APP-62 004827A (HW) Function D) Ch.1 source address[15:0] S) Ch.1 memory address[15:0] D) Ch.1 source address[31:16] S) Ch.1 memory address[31:16] D) Ch.1 destination address[15:0] S) Invalid D) Ch.1 destination address[31:16] S) Invalid EPSON Setting Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48282-0x48288 Register name Address High-Speed DMA Name Bit Function 0048282 D15-6 - HSDMA Ch.2 D5 D2ID (HW) control register (pHS2_ADVMODE) D4 S2ID for ADV mode Note: D) Dual mode S) Single mode 0048284 HSDMA Ch.2 (HW) low-order source address setup register (pHS2_AD_SADR) for ADV mode Note: D) Dual address mode S) Single address mode 0048286 HSDMA Ch.2 (HW) high-order source address setup register for ADV mode Note: D) Dual address mode S) Single address mode 0048288 HSDMA Ch.2 (HW) low-order destination address setup register (pHS2_ADV_DADR) for ADV mode Note: D) Dual address mode S) Single address mode Setting - reserved D) Ch.2 destination address control 1 Decrement 0 S) Invalid (with init.) D) Ch.2 source address control 1 Decrement 0 S) Ch.2 memory address control (with init.) - D3-1 - reserved D0 WORDSIZE2 Ch.2 transfer data size 1 Word 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2ADRL15 S2ADRL14 S2ADRL13 S2ADRL12 S2ADRL11 S2ADRL10 S2ADRL9 S2ADRL8 S2ADRL7 S2ADRL6 S2ADRL5 S2ADRL4 S2ADRL3 S2ADRL2 S2ADRL1 S2ADRL0 S2ADRH15 S2ADRH14 S2ADRH13 S2ADRH12 S2ADRH11 S2ADRH10 S2ADRH9 S2ADRH8 S2ADRH7 S2ADRH6 S2ADRH5 S2ADRH4 S2ADRH3 S2ADRH2 S2ADRH1 S2ADRH0 D2ADRL15 D2ADRL14 D2ADRL13 D2ADRL12 D2ADRL11 D2ADRL10 D2ADRL9 D2ADRL8 D2ADRL7 D2ADRL6 D2ADRL5 D2ADRL4 D2ADRL3 D2ADRL2 D2ADRL1 D2ADRL0 D) Ch.2 source address[15:0] S) Ch.2 memory address[15:0] D) Ch.2 source address[31:16] S) Ch.2 memory address[31:16] D) Ch.2 destination address[15:0] S) Invalid Init. R/W D2IN[1:0] setting S2IN[1:0] setting DATSIZE2 setting I Remarks - 0 - 0 when being read. R/W 0 R/W - 0 - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-63 APPENDIX I/O MAP 0x4828A-0x48296 Register name Address HSDMA Ch.2 high-order destination address setup register for ADV mode Bit 004828A (HW) D15 D14 D13 D12 D11 D10 D9 Note: D8 D) Dual address D7 mode D6 S) Single D5 address D4 mode D3 D2 D1 D0 HSDMA Ch.3 0048292 D15-6 D5 control register (HW) (pHS3_ADVMODE) D4 for ADV mode Note: D) Dual mode S) Single mode HSDMA Ch.3 0048294 low-order (HW) source address setup register (pHS3_AD_SADR) for ADV mode Note: D) Dual address mode S) Single address mode HSDMA Ch.3 0048296 high-order (HW) source address setup register for ADV mode Note: D) Dual address mode S) Single address mode APP-64 High-Speed DMA Name Function Setting - D3ID - reserved D) Ch.3 destination address control 1 Decrement 0 S) Invalid (with init.) S3ID D) Ch.3 source address control 1 Decrement 0 S) Ch.3 memory address control (with init.) D3-1 - - reserved D0 WORDSIZE3 Ch.3 transfer data size 1 Word 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Init. R/W D2ADRH15 D) Ch.2 destination address[31:16] D2ADRH14 S) Invalid D2ADRH13 D2ADRH12 D2ADRH11 D2ADRH10 D2ADRH9 D2ADRH8 D2ADRH7 D2ADRH6 D2ADRH5 D2ADRH4 D2ADRH3 D2ADRH2 D2ADRH1 D2ADRH0 S3ADRL15 S3ADRL14 S3ADRL13 S3ADRL12 S3ADRL11 S3ADRL10 S3ADRL9 S3ADRL8 S3ADRL7 S3ADRL6 S3ADRL5 S3ADRL4 S3ADRL3 S3ADRL2 S3ADRL1 S3ADRL0 S3ADRH15 S3ADRH14 S3ADRH13 S3ADRH12 S3ADRH11 S3ADRH10 S3ADRH9 S3ADRH8 S3ADRH7 S3ADRH6 S3ADRH5 S3ADRH4 S3ADRH3 S3ADRH2 S3ADRH1 S3ADRH0 D) Ch.3 source address[15:0] S) Ch.3 memory address[15:0] D) Ch.3 source address[31:16] S) Ch.3 memory address[31:16] EPSON D3IN[1:0] setting S3IN[1:0] setting DATSIZE3 setting Remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W - 0 - 0 when being read. R/W 0 R/W - 0 - 0 when being read. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48298-0x4829C Register name Address 0048298 HSDMA Ch.3 (HW) low-order destination address setup register (pHS3_ADV_DADR) for ADV mode High-Speed DMA Name Function D3ADRL15 D3ADRL14 D3ADRL13 D3ADRL12 D3ADRL11 D3ADRL10 D3ADRL9 D3ADRL8 D3ADRL7 D3ADRL6 D3ADRL5 D3ADRL4 D3ADRL3 D3ADRL2 D3ADRL1 D3ADRL0 D3ADRH15 D3ADRH14 D3ADRH13 D3ADRH12 D3ADRH11 D3ADRH10 D3ADRH9 D3ADRH8 D3ADRH7 D3ADRH6 D3ADRH5 D3ADRH4 D3ADRH3 D3ADRH2 D3ADRH1 D3ADRH0 - D) Ch.3 destination address[15:0] S) Invalid Bit D15 D14 D13 D12 D11 D10 D9 D8 Note: D7 D) Dual address D6 mode D5 S) Single D4 address D3 mode D2 D1 D0 004829A D15 HSDMA Ch.3 D14 (HW) high-order D13 destination D12 address setup D11 register D10 for ADV mode D9 Note: D8 D) Dual address D7 mode D6 S) Single D5 address D4 mode D3 D2 D1 D0 004829C D15-1 HSDMA (HW) STD/ADV mode D0 select register (pHS_CNTLMODE) Setting D) Ch.3 destination address[31:16] S) Invalid reserved - HSDMAADV Standard mode/advanced mode select 1 Advanced mode 0 Standard mode Init. R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - R/W 0 R/W I Remarks R/W - 0 when being read. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-65 APPENDIX I/O MAP 0x48300-0x48310 Register name Address Bit High-Speed Bus Control Unit Name Address 0048300 D15-6 - D5 HRUWP control register (HW) D4 AEXPEN (pHBCU_ADR D3 - _CNT) D2 UMDAEN D1 UMDMEN D0 MIR Block 0 0048302 D15-6 - D5 ASIDEN0 configuration (HW) D4 MMUEN0 register D3 - (pHBCU_BLK0) D2 WRMD0 D1 DC0 D0 IC0 Block 1 0048304 D15-6 - D5 ASIDEN1 configuration (HW) D4 MMUEN1 register D3 - (pHBCU_BLK1) D2 WRMD1 D1 DC1 D0 IC1 Block 2 0048306 D15-6 - D5 ASIDEN2 configuration (HW) D4 MMUEN2 register D3 - (pHBCU_BLK2) D2 WRMD2 D1 DC2 D0 IC2 Block 3 0048308 D15-6 - D5 ASIDEN3 configuration (HW) D4 MMUEN3 register D3 - (pHBCU_BLK3) D2 WRMD3 D1 DC3 D0 IC3 Block 4 004830A D15-6 - D5 ASIDEN4 configuration (HW) D4 MMUEN4 register D3 - (pHBCU_BLK4) D2 WRMD4 D1 DC4 D0 IC4 Block 5 004830C D15-6 - D5 ASIDEN5 configuration (HW) D4 MMUEN5 register D3 - (pHBCU_BLK5) D2 WRMD5 D1 DC5 D0 IC5 Block 6 004830E D15-6 - D5 ASIDEN6 configuration (HW) D4 MMUEN6 register D3 - (pHBCU_BLK6) D2 WRMD6 D1 DC6 D0 IC6 Block 7 0048310 D15-6 - D5 ASIDEN7 configuration (HW) D4 MMUEN7 register D3 - (pHBCU_BLK7) D2 WRMD7 D1 DC7 D0 IC7 APP-66 Function Setting reserved HBCU register user write protect ASID exception enable reserved ASID forced enable (user mode) MMU forced enable (user mode) Mirroring enable reserved Block 0 ASID enable Block 0 MMU enable reserved Block 0 write-mode select Block 0 data cache enable Block 0 instruction cache enable reserved Block 1 ASID enable Block 1 MMU enable reserved Block 1 write-mode select Block 1 data cache enable Block 1 instruction cache enable reserved Block 2 ASID enable Block 2 MMU enable reserved Block 2 write-mode select Block 2 data cache enable Block 2 instruction cache enable reserved Block 3 ASID enable Block 3 MMU enable reserved Block 3 write-mode select Block 3 data cache enable Block 3 instruction cache enable reserved Block 4 ASID enable Block 4 MMU enable reserved Block 4 write-mode select Block 4 data cache enable Block 4 instruction cache enable reserved Block 5 ASID enable Block 5 MMU enable reserved Block 5 write-mode select Block 5 data cache enable Block 5 instruction cache enable reserved Block 6 ASID enable Block 6 MMU enable reserved Block 6 write-mode select Block 6 data cache enable Block 6 instruction cache enable reserved Block 7 ASID enable Block 7 MMU enable reserved Block 7 write-mode select Block 7 data cache enable Block 7 instruction cache enable - EPSON 1 Protect 1 Enabled Init. R/W 0 Write enabled 0 Disabled - 1 Enabled 1 Enabled 1 Mirrored 0 Disabled 0 Disabled 0 Not mirrored - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 1 Used 1 Used 0 Write-through 0 Not used 0 Not used Remarks - 0 0 - 0 0 0 - 0 0 - 0 0 0 - R/W R/W - R/W R/W R/W - R/W R/W - R/W R/W R/W 0 when being read. - 0 0 - 0 0 0 - 0 0 - 0 0 0 - 0 0 - 0 0 0 - 0 0 - 0 0 0 - R/W R/W - R/W R/W R/W - R/W R/W - R/W R/W R/W 0 when being read. - 0 0 - 0 0 0 - 0 0 - 0 0 0 - 0 0 - 0 0 0 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W - 0 when being read. R/W R/W R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48312-0x48314 Register name Address ASID setup register (pHBCU_ASID _SETUP) Logical ASID setup register (pHBCU_LOGIC _ASID) Bit High-Speed Bus Control Unit Name 0048312 D15-6 - D5 ASID5 (HW) D4 ASID4 D3 ASID3 D2 ASID2 D1 ASID1 D0 ASID0 0048314 D15-6 - D5 ASID_VA5 (HW) D4 ASID_VA4 D3 ASID_VA3 D2 ASID_VA2 D1 ASID_VA1 D0 ASID_VA0 Function Setting Init. R/W I Remarks reserved ASID - 0x0 to 0x3F - 0 0 0 0 0 0 - 0 when being read. R/W reserved Logical ASID (compared with VA[31:26] output from the CPU) - 0x0 to 0x3F - 0 0 0 0 0 0 - 0 when being read. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-67 APPENDIX I/O MAP 0x48320-0x48328 Register name Address MMU control register (pMMU_CNTL) MMU entry register (pMMU_ENTRY) MMU 4KB data address register (pMMU_ADR_4K) Bit Name 0048320 D15-13 - D12 MRUWP (HW) D11-9 - D8 64KMD D7-5 - D4 ASIDMIX D3-1 - D0 MEN 0048322 D15 REPWAY3 D14 REPWAY2 (HW) D13 REPWAY1 D12 REPWAY0 D11 HITWAY3 D10 HITWAY2 D9 HITWAY1 D8 HITWAY0 D7 ENT3 D6 ENT2 D5 ENT1 D4 ENT0 D3 WAY3 D2 WAY2 D1 WAY1 D0 WAY0 0048324 (HW) D15 D14 D13 D12 D11-0 MMU common 0048326 D15 D14 (HW) data address D13 register D12 (pMMU_ADR_COM) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048328 D15 MMU TAG D14 (HW) address D13 register D12 (pMMU_TAD_ADR) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 APP-68 Memory Management Unit CA15 CA14 CA13 CA12 - CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 CVA31 CVA30 CVA29 CVA28 CVA27 CVA26 CVA25 CVA24 CVA23 CVA22 CVA21 CVA20 CVA19 CVA18 CVA17 CVA16 Function reserved MMU register user write protect reserved Page size select reserved Entry number generation mode reserved MMU enable Replace Way number Hit Way number Entry number setting Way number setting Setting 1 Protect 0 Write enabled - 1 64KB 0 4KB - 1 ASID mixed 0 VA only - 1 Enabled 0 Disabled 1 Way 3 0 - 1 Way 2 0 - 1 Way 1 0 - 1 Way 0 0 - 1 Way 3 0 - 1 Way 2 0 - 1 Way 1 0 - 1 Way 0 0 - 0 to 15 1 1 1 1 Translation physical address A[15:12] (effective in 4KB/page mode) Way 3 Way 2 Way 1 Way 0 0 - 0 - 0 - 0 - 0x0 to 0xF reserved Translation physical address A[31:16] - 0x0 to 0xFFFF Comparison address A[31:16] in TAG 0x0 to 0xFFFF EPSON Init. R/W - - 0 - 0 - 0 - 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - R/W - R/W - R/W - R/W R Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. R R/W R/W R/W - 0 when being read. R/W R/W CVA[19:16] is not effective in 64KB/page mode S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4832A-0x48332 Register name Address Memory Management Unit Name Bit 004832A D15-9 - MMU page D8 ASIDUSE (HW) setting register D7 - (pMMU_PAGE D6 WP _SETUP) D5 UMP D4 ACP D3 CE D2 VLD D1 ACC D0 DTY 004832C D15-14 - TLB control D13 LRURD (HW) register D12 LRUWR (pMMU_TLB_CNTL) D11-9 - D8 FLUSH D7-6 - D5 TAGRD D4 TAGWR D3-2 - D1 DATRD D0 DATWR MMU exception 004832E D15-13 - D12 ASMIR (HW) status register D11 ASRDWR (pMMU_EXCP D10 ASSVM _STAT) D9 ASIRDA D8 ASASID D7 EXPWRP D6 EXPUMP D5 EXPACP D4 EXPASID D3 EXPMLT D2 EXPMISS D1 - D0 EXP MMU exception 0048330 D15 EA15 D14 EA14 address (HW) D13 EA13 register 1 D12 EA12 (pMMU_EXP_ADR) D11 EA11 D10 EA10 D9 EA9 D8 EA8 D7 EA7 D6 EA6 D5 EA5 D4 EA4 D3 EA3 D2 EA2 D1 EA1 D0 EA0 MMU exception 0048332 address (HW) register 2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 S1C33401 TECHNICAL MANUAL Function Setting reserved Use of ASID reserved Write protect User mode access protect Access protect Cache enable TLB entry valid bit Page access bit Dirty bit reserved LRU entry read LRU entry write reserved TLB-flush control reserved TAG entry read TAG entry write reserved DATA entry read DATA entry write reserved Mirrored access status Read/write status Supervisor/user mode status Instruction fetch/data R/W status ASID status MMU write-protect exception MMU user-mode-protect exception MMU access-protect exception ASID exception MMU multi-hit exception MMU miss exception reserved MMU exception (all causes) Exception occurred logical address (low-order 16 bits) - Exception occurred logical address (high-order 16 bits) EPSON 1 Used Init. R/W 0 Not used - 1 1 1 1 1 1 1 Protected Protected Protected Enabled Valid Accessed Written 0 0 0 0 0 0 0 Enabled Enabled Enabled Disabled Invalid Not accessed Not written - 1 Read 1 Write 0 Invalid 0 Invalid - 1 Clear V bits 0 - 1 Read 0 1 Write 0 - 1 Read 0 1 Write 0 - 1 Mirrored 0 1 Read 0 1 Supervisor 0 1 Instruction 0 0 1 Used 1 Occurred 0 0 1 Occurred 1 Occurred 0 0 1 Occurred 1 Occurred 0 1 Occurred 0 - 1 Occurred 0 Invalid Invalid Invalid Invalid Invalid Not mirrored Write User Data Not used Not occurred Not occurred Not occurred Not occurred Not occurred Not occurred Not occurred Remarks - 0 - 0 0 0 0 0 0 0 - 0 0 - 0 - 0 0 - 0 0 - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. W W - W - W W - W W - 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 when being read. R R R R R R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I R APP I/Omap APP-69 APPENDIX I/O MAP 0x48334 Memory Management Unit Register name Address MMU LRU register (pMMU_LRU) APP-70 Bit Name 0048334 D15-6 - D5 LRU5 (HW) D4 LRU4 D3 LRU3 D2 LRU2 D1 LRU1 D0 LRU0 Function reserved LRU information Setting - EPSON Init. R/W - 0 0 0 0 0 0 Remarks - 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48340-0x4834A Register name Address Cache configuration register (pCCU_SETUP) Cache way number select register (pCCU_ENTRY) Bit Cache Control Unit Name 0048340 D15-13 - D12 LKWAY (HW) D11-10 - D9 DLK D8 IRLK D7-5 - D4 WBEN D3-2 - D1 DC D0 IC 0048342 D15-2 - (HW) D1 WAY1 D0 WAY0 0048344 D15-3 - Cache entry D2 LK (HW) control register D1 VLD (pCCU_ENTRY D0 DTY _CNTL) Cache control 0048346 D15 WBSTAT D14 - (HW) register D13 LRURD (pCCU_CNTL) D12 LRUWR D11 LKSTART D10 LKFLSH D9 WB D8 CFLSH D7-6 - D5 TAGRD D4 TAGWR D3-2 - D1 DATRD D0 DATWR 0048348 D15 TA15 Cache TAG D14 TA14 (HW) address D13 TA13 register 1 D12 TA12 (pCCU_ADR) D11 TA11 D10 ENT6 D9 ENT5 D8 ENT4 D7 ENT3 D6 ENT2 D5 ENT1 D4 ENT0 D3 WO1 D2 WO0 D1-0 - Cache TAG 004834A D15 TA31 D14 TA30 address (HW) D13 TA29 register 2 D12 TA28 D11 TA27 D10 TA26 D9 TA25 D8 TA24 D7 TA23 D6 TA22 D5 TA21 D4 TA20 D3 TA19 D2 TA18 D1 TA17 D0 TA16 Function reserved Lock way select reserved Data-lock enable Instruction-lock enable reserved Write-back enable reserved Data cache enable Instruction cache enable Setting - 1 Way 1 0 Way 3 - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - 1 Write-back 0 Write through - 1 Enabled 1 Enabled 0 Disabled 0 Disabled - reserved Way number reserved Lock bit control/status Valid bit control/status Dirty bit control/status Write-back status reserved LRU entry read LRU entry write Lock-start control Lock-flush control Write-back control Cache-flush control reserved TAG entry read TAG entry write reserved DATA entry read DATA entry write Comparison address in cache TAG (5 low-order bits) Entry number (ENT[6:0] = PA[10:4]) Word offset reserved Comparison address in cache TAG (16 high-order bits) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 to 3 Way 0 to Way 3 - Locked 0 Unlocked Valid 0 Invalid 0 Unchanged Updated Underway 0 Completed - 0 Invalid Read Write 0 Invalid Lock start 0 Lock end Lock flush 0 Invalid Write back 0 Invalid Cache flush 0 Invalid - 0 Invalid Read Write 0 Invalid - Read 0 Invalid 0 Invalid Write 0 to 127 Entry 0 to Entry 127 0 to 3 W0 to W3 - Init. R/W Remarks - X - 0 0 - 0 - 0 0 - - R/W - R/W R/W - R/W - R/W R/W - 0 0 R/W - 0 0 0 - 0 when being read. R/W R/W R/W 0 - 0 0 0 0 - 0 0 - 0 0 R - 0 when being read. W W R/W W 0 when being read. W W - W W - W W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. R/W R/W - 0 when being read. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-71 APPENDIX I/O MAP 0x4834C-0x48352 Register name Address Cache data register 1 (pCCU_DATA) Cache data register 2 Interrupt lock setup register (pCCU_LOCK) Cache LRU register (pCCU_LRU) APP-72 004834C (HW) Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 004834E D15 D14 (HW) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048350 D15 D14 (HW) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0048352 D15-3 D2 (HW) D1 D0 Cache Control Unit Name CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CD31 CD30 CD29 CD28 CD27 CD26 CD25 CD24 CD23 CD22 CD21 CD20 CD19 CD18 CD17 CD16 LKIL15 LKIL14 LKIL13 LKIL12 LKIL11 LKIL10 LKIL9 LKIL8 LKIL7 LKIL6 LKIL5 LKIL4 LKIL3 LKIL2 LKIL1 LKIL0 - LRU2 LRU1 LRU0 Function Setting Init. R/W Remarks Cache data (16 low-order bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Cache data (16 high-order bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Interrupt handler lock level (compared with IL[3:0] in PSR) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W - 0 0 0 - 0 when being read. R/W reserved LRU information - EPSON S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48360-0x4836C Register name Address Core system clock control register (pCMU2_CNTL _CORE) Bit Clock Management Unit Name Function reserved 0048360 D15-11 - D10 - reserved (HW) D9 CCLKSEL1 Core clock (CCLK) selection D8 CCLKSEL0 Protected D7-4 - D3 OSCSEL1 D2 OSCSEL0 Core system clock On/Off register (pCMU2_SET) 0048362 (HW) Protected 0048364 Core system clock automatic (HW) control register (pCMU2_AUTO) Protected Peripheral and 0048366 (HW) external clock output control register (pCMU2_CNTL _PERI) Protected Clock option register (pCMU2_OPT) 0048368 (HW) Protected NMI flag register 004836A (pCMU2_NMI_FLAG) (HW) Protected 004836C NMI mode (HW) register (pCMU2_NMI_MODE) Protected reserved OSC clock selection Setting - - CCLKSEL[1:0] 11 10 01 00 CCLK OSC*1/8 OSC*1/4 OSC*1/2 OSC*1/1 - OSCSEL[1:0] Clock source 11 PLL 10 OSC3 01 OSC1 00 OSC3 D1 SOSC3 High-speed oscillation (OSC3) On/Off 1 On 0 Off D0 SOSC1 Low-speed oscillation (OSC1) On/Off 1 On 0 Off 1 On D15 DBGNCLK DBG NOSTOP clock On/Off 0 Off reserved D14-9 - - D8 DBGCLK DBG clock On/Off 1 On 0 Off reserved D7-4 - - D3 HBCUCLK HBCU clock On/Off 1 On 0 Off D2 MMUCLK MMU clock On/Off D1 CCUCLK CCU clock On/Off CPU clock On/Off D0 CPUCLK reserved D15-9 - - 1 Enabled D8 DBGAUTO DBG clock automatic control 0 Disabled reserved D7-4 - - D3 HBCUAUTO HBCU clock automatic control 1 Enabled 0 Disabled D2 MMUAUTO MMU clock automatic control D1 CCUAUTO CCU clock automatic control D0 CPUAUTO CPU clock automatic control reserved D15-11 - - D10 CMUCLK2 External clock output (CMU_CLK) CMUCLK[2:0] CMU_CLK D9 CMUCLK1 selection 111 PLL D8 CMUCLK0 110 OSC1 101 OSC3 100 CCLK(*) 011 CCLK*1/8 010 CCLK*1/4 001 CCLK*1/2 000 CCLK*1/1 reserved D7-2 - - D1 PCLKSEL1 Peripheral clock (PCLK) selection PCLKSEL[1:0] PCLK D0 PCLKSEL0 11 OSC*1/8 10 OSC*1/4 01 OSC*1/2 00 OSC*1/1 OSC oscillation stabilization-wait D15 OSCTM7 0 to 255 timer D14 OSCTM6 D13 OSCTM5 D12 OSCTM4 D11 OSCTM3 D10 OSCTM2 D9 OSCTM1 D8 OSCTM0 reserved D7-4 - - D3 OSC3OFF OSC3 disable during SLEEP 0 Run 1 Stop Wait-timer high-speed mode D2 TMHSP 1 High speed 0 Normal D1 HALTMD HALT mode selection 1 HALT2 0 HALT 1 Wait interrupt 0 No wait D0 WAKEUPWT Wakeup-wait function enable reserved D15-13 - - NMI flag D12 NMIF 1 NMI occurred 0 Not occurred reserved D11-0 - - reserved D15-9 - - NMI detection mode D8 NMIMD 1 Low level 0 Falling edge reserved D7-0 - - S1C33401 TECHNICAL MANUAL EPSON Init. R/W I Remarks - 0 0 0 - 0 when being read. - Writing 1 not allowed. R/W - 0 0 - 0 when being read. R/W 1 1 1 - 1 - 1 1 1 1 - 1 - 0 0 0 0 - 0 0 0 R/W R/W R/W - R/W - R/W R/W R/W R/W - R/W - R/W R/W R/W R/W - R/W 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. before clock tree - 0 0 - 0 when being read. R/W 0 0 0 0 0 0 0 0 - 0 0 0 0 - 0 0 R/W - 0 0 - 0 when being read. R/W - Writing 1 not allowed. - R/W R/W R/W R/W - R/W - 0 when being read. 0 when being read. Reset by writing 1. Writing 1 not allowed. APP-73 APP I/Omap APPENDIX I/O MAP 0x4836E-0x48372 Register name Address Bit Clock Management Unit Name Clock control 004836E D15-8 - D7 CLGP7 (HW) protect register D6 CLGP6 (pCMU2_PROTECT) D5 CLGP5 D4 CLGP4 D3 CLGP3 D2 CLGP2 D1 CLGP1 D0 CLGP0 CCLK system 0048370 D15-12 - D11 BBEBNCLK (HW) peripheral D10 BBHBIFCLK clock On/Off D9 BBSRAMCLK register D8 BBDBGIFCLK (pCMU2_CCLK D7-6 - _PERI) D5 EBCUHBCLK D4 EBCUSDCLK Protected D3 A3RAMCLK D2 DMACLK D1 SAPB12CCLK D0 SAPB1PCLK CCLK system 0048372 D15-11 - D10 BBHBIFAUTO (HW) peripheral D9 BBSRAMAUTO clock automatic D8 BBDBGIFAUTO control register D7-6 - (pCMU2_AUTO D5 EBCUHBAUTO _CCLK_PERI) D4 EBCUSDAUTO D3 A3RAMAUTO Protected D2 DMAAUTO D1 SAPB12CAUTO D0 SAPB1PAUTO APP-74 Function Setting Init. R/W Remarks - reserved Clock control register protect flag Writing 10010110 (0x96) removes the write protection of the clock control registers (0x40180-0x40188, 0x48360- 0x4836A, 0x48370, 0x48372). Writing another value set the write protection. - 0 0 0 0 0 0 0 0 - 0 when being read. R/W reserved BBCU, EBCU NOSTOP On/Off BBCU HB I/F clock On/Off BBCU SRAM clock On/Off BBCU DBG I/F clock On/Off reserved EBCU HB I/F clock On/Off EBCU SDRAM clock On/Off A3RAM clock On/Off DMA clock On/Off SAPB12C clock On/Off SAPB1P clock On/Off reserved BBCU HB I/F clock auto control BBCU SRAM clock auto control BBCU DBG I/F clock auto control reserved EBCU HB I/F clock auto control EBCU SDRAM clock auto control A3RAM clock auto control DMA clock auto control SAPB12C clock auto control SAPB1P clock auto control - 1 1 1 1 - 1 1 1 1 1 1 - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W - 0 0 0 - 0 0 0 0 0 0 - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W EPSON - 1 On 0 Off - 1 On 0 Off - 1 Enabled 0 Disabled - 1 Enabled 0 Disabled S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48380-0x48386 Register name Address Bit Basic Bus Control Unit Name 0048380 D15-2 - BCLK divide D1 BCLKD1 (HW) control register D0 BCLKD0 (pBBCU_BCLK _DIV) Function Setting reserved BCLK setup (CCLK division ratio) - reserved BUS control 0048384 D15-7 - D6 BROM_CE10 CE10 area burst ROM select register (HW) D5 BROM_CE8 CE8 area burst ROM select (pBBCU_BUSCTL) D4 BROM_CE5 CE5 area burst ROM select D3 - reserved D2 ASTBW ASTB pulse width D1 EBUSMST External bus master enable D0 WAITEN Wait enable reserved Common cycle 0048386 D15-4 - D3 PGRD_CYC3 Number of read cycles in page (HW) control register D2 PGRD_CYC2 mode (pBBCU_CM_CYC) D1 PGRD_CYC1 D0 PGRD_CYC0 BCLKD[1:0] 11 10 01 00 BCLK CCLK*1/8 CCLK*1/4 CCLK*1/2 CCLK*1/1 - 1 Used 1 Used 1 Used 0 Not used 0 Not used 0 Not used - 1 2 clocks 1 Enabled 1 Enabled 0 1 clock 0 Disabled 0 Disabled - PGRD_CYC[3:0] # of clocks 1111 16 x (CExMLT) : : 0000 1 x (CExMLT) Init. R/W I Remarks 0 1 1 - Writing 1 not allowed. R/W 0 0 0 0 0 0 0 0 0 1 1 1 1 - Writing 1 not allowed. R/W R/W R/W - Writing 1 not allowed. R/W R/W R/W - Writing 1 not allowed. R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-75 APPENDIX I/O MAP 0x48388-0x4838A Register name Address Bit Basic Bus Control Unit Name 0048388 D15-14 - CE4 area D13 CE4IO (HW) configuration D12 CE4BIG register D11 CE4BSL (pBBCU_CE4SET) D10 CE4EBCU D9 CE4DVSZ1 D8 CE4DVSZ0 CE4 access cycle control register (pBBCU _CE4ACCNT) APP-76 004838A (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE4BCKSYN CE4WSTHCK CE4WEDHCK CE4RSTHCK CE4ODISC1 CE4ODISC0 D15 D14 CE4MLT1 CE4MLT0 D13 D12 CE4ADISC1 CE4ADISC0 D11 D10 CE4WRSTAC1 CE4WRSTAC0 D9 D8 CE4WRENDC1 CE4WRENDC0 D7 D6 CE4RDSTAC1 CE4RDSTAC0 D5 D4 CE4RDENDC1 CE4RDENDC0 D3 D2 D1 D0 CE4CE3 CE4CE2 CE4CE1 CE4CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting Init. R/W - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE4DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 0 Disabled 1 Enabled RD start state option (-0.5 clk) 1 Enabled 0 Disabled Output disable cycle configuration CE4ODISC[1:0] # of clocks 11 3 x (CE4MLT) 10 2 x (CE4MLT) 01 1 x (CE4MLT) 00 0 clocks Access cycle multiple mode CE4MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE4ADISC[1:0] # of clocks 11 3 x (CE4MLT) 10 2 x (CE4MLT) 01 1 x (CE4MLT) 00 0 clocks Write start state setup CE4WRSTAC[1:0] # of clocks 4 x (CE4MLT) 11 3 x (CE4MLT) 10 2 x (CE4MLT) 01 1 x (CE4MLT) 00 Write end state setup CE4WRENDC[1:0] # of clocks 11 3 x (CE4MLT) 10 2 x (CE4MLT) 01 1 x (CE4MLT) 00 0 clocks Read start state setup CE4RDSTAC[1:0] # of clocks 11 4 x (CE4MLT) 10 3 x (CE4MLT) 01 2 x (CE4MLT) 00 1 x (CE4MLT) Read end state setup CE4RDENDC[1:0] # of clocks 11 3 x (CE4MLT) 10 2 x (CE4MLT) 01 1 x (CE4MLT) 00 0 clocks CE cycle setup CE4CE[3:0] # of clocks 1111 16 x (CE4MLT) : : 0000 1 x (CE4MLT) EPSON Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4838C-0x4838E Register name Address Basic Bus Control Unit Name Bit 004838C D15-14 - CE5 area D13 CE5IO (HW) configuration D12 CE5BIG register D11 CE5BSL (pBBCU_CE5SET) D10 CE5EBCU D9 CE5DVSZ1 D8 CE5DVSZ0 CE5 access cycle control register (pBBCU _CE5ACCNT) 004838E (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE5BCKSYN CE5WSTHCK CE5WEDHCK CE5RSTHCK CE5ODISC1 CE5ODISC0 D15 D14 CE5MLT1 CE5MLT0 D13 D12 CE5ADISC1 CE5ADISC0 D11 D10 CE5WRSTAC1 CE5WRSTAC0 D9 D8 CE5WRENDC1 CE5WRENDC0 D7 D6 CE5RDSTAC1 CE5RDSTAC0 D5 D4 CE5RDENDC1 CE5RDENDC0 D3 D2 D1 D0 CE5CE3 CE5CE2 CE5CE1 CE5CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE5DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE5ODISC[1:0] # of clocks 11 3 x (CE5MLT) 10 2 x (CE5MLT) 01 1 x (CE5MLT) 00 0 clocks Access cycle multiple mode CE5MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE5ADISC[1:0] # of clocks 11 3 x (CE5MLT) 10 2 x (CE5MLT) 01 1 x (CE5MLT) 00 0 clocks Write start state setup CE5WRSTAC[1:0] # of clocks 4 x (CE5MLT) 11 3 x (CE5MLT) 10 2 x (CE5MLT) 01 1 x (CE5MLT) 00 Write end state setup CE5WRENDC[1:0] # of clocks 11 3 x (CE5MLT) 10 2 x (CE5MLT) 01 1 x (CE5MLT) 00 0 clocks Read start state setup CE5RDSTAC[1:0] # of clocks 11 4 x (CE5MLT) 10 3 x (CE5MLT) 01 2 x (CE5MLT) 00 1 x (CE5MLT) Read end state setup CE5RDENDC[1:0] # of clocks 11 3 x (CE5MLT) 10 2 x (CE5MLT) 01 1 x (CE5MLT) 00 0 clocks CE cycle setup CE5CE[3:0] # of clocks 1111 16 x (CE5MLT) : : 0000 1 x (CE5MLT) Init. R/W I Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-77 APPENDIX I/O MAP 0x48390-0x48392 Register name Address Bit Basic Bus Control Unit Name 0048390 D15-14 - CE6 area D13 CE6IO (HW) configuration D12 CE6BIG register D11 CE6BSL (pBBCU_CE6SET) D10 CE6EBCU D9 CE6DVSZ1 D8 CE6DVSZ0 CE6 access cycle control register (pBBCU _CE6ACCNT) APP-78 0048392 (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE6BCKSYN CE6WSTHCK CE6WEDHCK CE6RSTHCK CE6ODISC1 CE6ODISC0 D15 D14 CE6MLT1 CE6MLT0 D13 D12 CE6ADISC1 CE6ADISC0 D11 D10 CE6WRSTAC1 CE6WRSTAC0 D9 D8 CE6WRENDC1 CE6WRENDC0 D7 D6 CE6RDSTAC1 CE6RDSTAC0 D5 D4 CE6RDENDC1 CE6RDENDC0 D3 D2 D1 D0 CE6CE3 CE6CE2 CE6CE1 CE6CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting Init. R/W - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE6DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE6ODISC[1:0] # of clocks 11 3 x (CE6MLT) 10 2 x (CE6MLT) 01 1 x (CE6MLT) 00 0 clocks Access cycle multiple mode CE6MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE6ADISC[1:0] # of clocks 11 3 x (CE6MLT) 10 2 x (CE6MLT) 01 1 x (CE6MLT) 00 0 clocks Write start state setup CE6WRSTAC[1:0] # of clocks 4 x (CE6MLT) 11 3 x (CE6MLT) 10 2 x (CE6MLT) 01 1 x (CE6MLT) 00 Write end state setup CE6WRENDC[1:0] # of clocks 11 3 x (CE6MLT) 10 2 x (CE6MLT) 01 1 x (CE6MLT) 00 0 clocks Read start state setup CE6RDSTAC[1:0] # of clocks 11 4 x (CE6MLT) 10 3 x (CE6MLT) 01 2 x (CE6MLT) 00 1 x (CE6MLT) Read end state setup CE6RDENDC[1:0] # of clocks 11 3 x (CE6MLT) 10 2 x (CE6MLT) 01 1 x (CE6MLT) 00 0 clocks CE cycle setup CE6CE[3:0] # of clocks 1111 16 x (CE6MLT) : : 0000 1 x (CE6MLT) EPSON Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x48394-0x48396 Register name Address Basic Bus Control Unit Name Bit 0048394 D15-14 - CE7 area D13 CE7IO (HW) configuration D12 CE7BIG register D11 CE7BSL (pBBCU_CE7SET) D10 CE7EBCU D9 CE7DVSZ1 D8 CE7DVSZ0 CE7 access cycle control register (pBBCU _CE7ACCNT) 0048396 (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE7BCKSYN CE7WSTHCK CE7WEDHCK CE7RSTHCK CE7ODISC1 CE7ODISC0 D15 D14 CE7MLT1 CE7MLT0 D13 D12 CE7ADISC1 CE7ADISC0 D11 D10 CE7WRSTAC1 CE7WRSTAC0 D9 D8 CE7WRENDC1 CE7WRENDC0 D7 D6 CE7RDSTAC1 CE7RDSTAC0 D5 D4 CE7RDENDC1 CE7RDENDC0 D3 D2 D1 D0 CE7CE3 CE7CE2 CE7CE1 CE7CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE7DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE7ODISC[1:0] # of clocks 11 3 x (CE7MLT) 10 2 x (CE7MLT) 01 1 x (CE7MLT) 00 0 clocks Access cycle multiple mode CE7MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE7ADISC[1:0] # of clocks 11 3 x (CE7MLT) 10 2 x (CE7MLT) 01 1 x (CE7MLT) 00 0 clocks Write start state setup CE7WRSTAC[1:0] # of clocks 4 x (CE7MLT) 11 3 x (CE7MLT) 10 2 x (CE7MLT) 01 1 x (CE7MLT) 00 Write end state setup CE7WRENDC[1:0] # of clocks 11 3 x (CE7MLT) 10 2 x (CE7MLT) 01 1 x (CE7MLT) 00 0 clocks Read start state setup CE7RDSTAC[1:0] # of clocks 11 4 x (CE7MLT) 10 3 x (CE7MLT) 01 2 x (CE7MLT) 00 1 x (CE7MLT) Read end state setup CE7RDENDC[1:0] # of clocks 11 3 x (CE7MLT) 10 2 x (CE7MLT) 01 1 x (CE7MLT) 00 0 clocks CE cycle setup CE7CE[3:0] # of clocks 1111 16 x (CE7MLT) : : 0000 1 x (CE7MLT) Init. R/W I Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-79 APPENDIX I/O MAP 0x48398-0x4839A Register name Address Bit Basic Bus Control Unit Name 0048398 D15-14 - CE8 area D13 CE8IO (HW) configuration D12 CE8BIG register D11 CE8BSL (pBBCU_CE8SET) D10 CE8EBCU D9 CE8DVSZ1 D8 CE8DVSZ0 CE8 access cycle control register (pBBCU _CE8ACCNT) APP-80 004839A (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE8BCKSYN CE8WSTHCK CE8WEDHCK CE8RSTHCK CE8ODISC1 CE8ODISC0 D15 D14 CE8MLT1 CE8MLT0 D13 D12 CE8ADISC1 CE8ADISC0 D11 D10 CE8WRSTAC1 CE8WRSTAC0 D9 D8 CE8WRENDC1 CE8WRENDC0 D7 D6 CE8RDSTAC1 CE8RDSTAC0 D5 D4 CE8RDENDC1 CE8RDENDC0 D3 D2 D1 D0 CE8CE3 CE8CE2 CE8CE1 CE8CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting Init. R/W - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE8DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE8ODISC[1:0] # of clocks 11 3 x (CE8MLT) 10 2 x (CE8MLT) 01 1 x (CE8MLT) 00 0 clocks Access cycle multiple mode CE8MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE8ADISC[1:0] # of clocks 11 3 x (CE8MLT) 10 2 x (CE8MLT) 01 1 x (CE8MLT) 00 0 clocks Write start state setup CE8WRSTAC[1:0] # of clocks 4 x (CE8MLT) 11 3 x (CE8MLT) 10 2 x (CE8MLT) 01 1 x (CE8MLT) 00 Write end state setup CE8WRENDC[1:0] # of clocks 11 3 x (CE8MLT) 10 2 x (CE8MLT) 01 1 x (CE8MLT) 00 0 clocks Read start state setup CE8RDSTAC[1:0] # of clocks 11 4 x (CE8MLT) 10 3 x (CE8MLT) 01 2 x (CE8MLT) 00 1 x (CE8MLT) Read end state setup CE8RDENDC[1:0] # of clocks 11 3 x (CE8MLT) 10 2 x (CE8MLT) 01 1 x (CE8MLT) 00 0 clocks CE cycle setup CE8CE[3:0] # of clocks 1111 16 x (CE8MLT) : : 0000 1 x (CE8MLT) EPSON Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x4839C-0x4839E Register name Address Basic Bus Control Unit Name Bit 004839C D15-14 - CE9 area D13 CE9IO (HW) configuration D12 CE9BIG register D11 CE9BSL (pBBCU_CE9SET) D10 CE9EBCU D9 CE9DVSZ1 D8 CE9DVSZ0 CE9 access cycle control register (pBBCU _CE9ACCNT) 004839E (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE9BCKSYN CE9WSTHCK CE9WEDHCK CE9RSTHCK CE9ODISC1 CE9ODISC0 D15 D14 CE9MLT1 CE9MLT0 D13 D12 CE9ADISC1 CE9ADISC0 D11 D10 CE9WRSTAC1 CE9WRSTAC0 D9 D8 CE9WRENDC1 CE9WRENDC0 D7 D6 CE9RDSTAC1 CE9RDSTAC0 D5 D4 CE9RDENDC1 CE9RDENDC0 D3 D2 D1 D0 CE9CE3 CE9CE2 CE9CE1 CE9CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE9DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE9ODISC[1:0] # of clocks 11 3 x (CE9MLT) 10 2 x (CE9MLT) 01 1 x (CE9MLT) 00 0 clocks Access cycle multiple mode CE9MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE9ADISC[1:0] # of clocks 11 3 x (CE9MLT) 10 2 x (CE9MLT) 01 1 x (CE9MLT) 00 0 clocks Write start state setup CE9WRSTAC[1:0] # of clocks 4 x (CE9MLT) 11 3 x (CE9MLT) 10 2 x (CE9MLT) 01 1 x (CE9MLT) 00 Write end state setup CE9WRENDC[1:0] # of clocks 11 3 x (CE9MLT) 10 2 x (CE9MLT) 01 1 x (CE9MLT) 00 0 clocks Read start state setup CE9RDSTAC[1:0] # of clocks 11 4 x (CE9MLT) 10 3 x (CE9MLT) 01 2 x (CE9MLT) 00 1 x (CE9MLT) Read end state setup CE9RDENDC[1:0] # of clocks 11 3 x (CE9MLT) 10 2 x (CE9MLT) 01 1 x (CE9MLT) 00 0 clocks CE cycle setup CE9CE[3:0] # of clocks 1111 16 x (CE9MLT) : : 0000 1 x (CE9MLT) Init. R/W I Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-81 APPENDIX I/O MAP 0x483A0-0x483A2 Register name Address Bit Basic Bus Control Unit Name 00483A0 D15-14 - CE10 area D13 CE10IO (HW) configuration D12 CE10BIG register D11 CE10BSL (pBBCU_CE10SET) D10 CE10EBCU D9 CE10DVSZ1 D8 CE10DVSZ0 CE10 access cycle control register (pBBCU _CE10ACCNT) APP-82 00483A2 (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE10BCKSYN CE10WSTHCK CE10WEDHCK CE10RSTHCK CE10ODISC1 CE10ODISC0 D15 D14 CE10MLT1 CE10MLT0 D13 D12 CE10ADISC1 CE10ADISC0 D11 D10 CE10WRSTAC1 CE10WRSTAC0 D9 D8 CE10WRENDC1 CE10WRENDC0 D7 D6 CE10RDSTAC1 CE10RDSTAC0 D5 D4 CE10RDENDC1 CE10RDENDC0 D3 D2 D1 D0 CE10CE3 CE10CE2 CE10CE1 CE10CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting Init. R/W - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE10DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE10ODISC[1:0] # of clocks 11 3 x (CE10MLT) 10 2 x (CE10MLT) 01 1 x (CE10MLT) 00 0 clocks Access cycle multiple mode CE10MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE10ADISC[1:0] # of clocks 11 3 x (CE10MLT) 10 2 x (CE10MLT) 01 1 x (CE10MLT) 00 0 clocks Write start state setup CE10WRSTAC[1:0] # of clocks 4 x (CE10MLT) 11 3 x (CE10MLT) 10 2 x (CE10MLT) 01 1 x (CE10MLT) 00 Write end state setup CE10WRENDC[1:0] # of clocks 11 3 x (CE10MLT) 10 2 x (CE10MLT) 01 1 x (CE10MLT) 00 0 clocks Read start state setup CE10RDSTAC[1:0] # of clocks 11 4 x (CE10MLT) 10 3 x (CE10MLT) 01 2 x (CE10MLT) 00 1 x (CE10MLT) Read end state setup CE10RDENDC[1:0] # of clocks 11 3 x (CE10MLT) 10 2 x (CE10MLT) 01 1 x (CE10MLT) 00 0 clocks CE cycle setup CE10CE[3:0] # of clocks 1111 16 x (CE10MLT) : : 0000 1 x (CE10MLT) EPSON Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x483A4-0x483A6 Register name Address Basic Bus Control Unit Name Bit 00483A4 D15-14 - CE11 area D13 CE11IO (HW) configuration D12 CE11BIG register D11 CE11BSL (pBBCU_CE11SET) D10 CE11EBCU D9 CE11DVSZ1 D8 CE11DVSZ0 CE11 access cycle control register (pBBCU _CE11ACCNT) 00483A6 (HW) D7-6 D5 D4 D3 D2 D1 D0 - CE11BCKSYN CE11WSTHCK CE11WEDHCK CE11RSTHCK CE11ODISC1 CE11ODISC0 D15 D14 CE11MLT1 CE11MLT0 D13 D12 CE11ADISC1 CE11ADISC0 D11 D10 CE11WRSTAC1 CE11WRSTAC0 D9 D8 CE11WRENDC1 CE11WRENDC0 D7 D6 CE11RDSTAC1 CE11RDSTAC0 D5 D4 CE11RDENDC1 CE11RDENDC0 D3 D2 D1 D0 CE11CE3 CE11CE2 CE11CE1 CE11CE0 Function reserved External/internal access setting Endian mode select External I/F mode select Device type select Device size select Setting - 1 Internal 0 External 1 Big endian 0 Little endian 1 BSL mode 0 A0 mode 1 EBCU device 0 BBCU device CE11DVSZ[1:0] Size 11 32 bits 10 16 bits (upper) 01 16 bits (lower) 00 8 bits reserved - Bus clock synchronization select 1 Sync. 0 Async. WR start state option (-0.5 clk) 1 Enabled 0 Disabled WR end state option (-0.5 clk) 1 Enabled 0 Disabled RD start state option (-0.5 clk) 0 Disabled 1 Enabled Output disable cycle configuration CE11ODISC[1:0] # of clocks 11 3 x (CE11MLT) 10 2 x (CE11MLT) 01 1 x (CE11MLT) 00 0 clocks Access cycle multiple mode CE11MLT[1:0] Multiple mode select 1 x4 01 x2 00 x1 Access disable state setup CE11ADISC[1:0] # of clocks 11 3 x (CE11MLT) 10 2 x (CE11MLT) 01 1 x (CE11MLT) 00 0 clocks Write start state setup CE11WRSTAC[1:0] # of clocks 4 x (CE11MLT) 11 3 x (CE11MLT) 10 2 x (CE11MLT) 01 1 x (CE11MLT) 00 Write end state setup CE11WRENDC[1:0] # of clocks 11 3 x (CE11MLT) 10 2 x (CE11MLT) 01 1 x (CE11MLT) 00 0 clocks Read start state setup CE11RDSTAC[1:0] # of clocks 11 4 x (CE11MLT) 10 3 x (CE11MLT) 01 2 x (CE11MLT) 00 1 x (CE11MLT) Read end state setup CE11RDENDC[1:0] # of clocks 11 3 x (CE11MLT) 10 2 x (CE11MLT) 01 1 x (CE11MLT) 00 0 clocks CE cycle setup CE11CE[3:0] # of clocks 1111 16 x (CE11MLT) : : 0000 1 x (CE11MLT) Init. R/W I Remarks - 0 0 0 0 0 1 - 0 when being read. R/W R/W R/W R/W R/W - 1 0 0 0 1 1 - 0 when being read. R/W R/W R/W R/W R/W 1 1 R/W 1 1 R/W 0 1 R/W 1 0 R/W 0 1 R/W 1 0 R/W 0 1 1 1 R/W APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-83 APPENDIX I/O MAP 0x483C0-0x483C6 Register name Address SDCLK divide and refresh mode register (pEBCU_DIVRF) Bit Extended Bus Control Unit Name 00483C0 D15-11 - D10 RCKS (HW) D9 RFSHMD D8 RFSH D7-5 - D4 SDCLKS D3-2 - D1 SDCLKD1 D0 SDCLKD0 00483C2 D15-8 - D7 RFCTR7 (HW) D6 RFCTR6 D5 RFCTR5 D4 RFCTR4 D3 RFCTR3 D2 RFCTR2 D1 RFCTR1 D0 RFCTR0 Refresh period 00483C4 D15-8 - D7 RFPOD7 (HW) register D6 RFPOD6 (pEBCU_RFPOD) D5 RFPOD5 D4 RFPOD4 D3 RFPOD3 D2 RFPOD2 D1 RFPOD1 D0 RFPOD0 SDRAM option 00483C6 D15 BIG D14 - (HW) register D13 DVSIZ1 (pEBCU_SDOPT) D12 DVSIZ0 Refresh counter register (pEBCU_RFTIM) reserved Refresh counter Setting Init. R/W - 1 SDCLK*1/16 0 SDCLK*1/1 1 Self-refresh 0 Auto-refresh 1 Enabled 0 Disabled - 1 Stopped 0 Output - SDCLKD[1:0] SDCLK 11 CCLK*1/8 10 CCLK*1/4 01 CCLK*1/2 00 CCLK*1/1 - 0 to 0xFF - 0 to 0xFF reserved Refresh period setup (number of cycles) Endian mode select reserved SDRAM device size select 1 Big endian 0 Little endian - DVSIZ[1:0] 11 10 01 00 RAW[1:0] 11 10 01 00 CAW[1:0] 11 10 01 00 Size 32 bits 16 bits (upper) 16 bits (lower) reserved Size 14 bits (16K) 13 bits (8K) 12 bits (4K) 11 bits (2K) Size 11 bits (2K) 10 bits (1K) 9 bits (512) 8 bits (256) D11 D10 RAW1 RAW0 Row address width D9 D8 CAW1 CAW0 Column address width - BACTMD - CMDHLD1 CMDHLD0 reserved - SDRAM bank active mode select 1 Full bank 0 No bank reserved - Command hold time setup # of clocks CMDHLD[1:0] (number of CCLK clocks) 3 clocks 11 2 clocks 10 1 clock 01 0 clocks 00 D7-5 D4 D3-2 D1 D0 APP-84 Function reserved Refresh counter clock select Refresh mode select Refresh enable reserved SDCLK output during idle reserved SDCLK setup (CCLK division ratio) EPSON Remarks - 0 0 0 - 0 - 1 1 - 0 when being read. R/W R/W R/W - 0 when being read. R/W - 0 when being read. R/W - 0 0 0 0 0 0 0 0 - 0 when being read. R/W - 0 0 0 0 0 0 0 0 0 - 0 1 - 0 when being read. R/W 0 1 R/W 0 1 R/W - 0 - 0 0 - 0 when being read. R/W - 0 when being read. R/W R/W - 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x483C8-0x483CC Register name Address Bit SDRAM access 00483C8 control register (HW) (pEBCU_SDACR) D15 D14 D13 D12 Extended Bus Control Unit Name TRFC3 TRFC2 TRFC1 TRFC0 D11-10 - D9 TRP1 D8 TRP0 Function tRFC (auto-refresh cycle time) setup (number of SDCLK clocks) reserved tRP (precharge time) setup (number of SDCLK clocks) D7-6 - D5 TWR1 D4 TWR0 reserved tWR (write-recovery time) setup (number of SDCLK clocks) D3-2 - D1 TRCD1 D0 TRCD0 reserved tRCD (RAS-CAS delay time) setup (number of SDCLK clocks) SDRAM mode 00483CA D15 INISQC (HW) D14-10 - register D9 WMODE (pEBCU_SDMOD) D8-7 - D6 CL2 D5 CL1 D4 CL0 D3 D2 D1 D0 00483CC D15-1 Self-refresh D0 control register (HW) (pEBCU_SLFEX) BT BL2 BL1 BL0 - SELF Setting TRFC[3:0] 11 1011 : 0111 : 0000 # of clocks reserved 12 clocks : 8 clocks : 1 clock - TRP[1:0] 11 10 01 00 # of clocks 4 clocks 3 clocks 2 clocks 1 clock - TWR[1:0] 11 10 01 00 # of clocks 4 clocks 3 clocks 2 clocks 1 clock reserved reserved - TRCD[1:0] # of clocks 11 4 clocks 10 3 clocks 01 2 clocks 00 1 clock 1 Init. sequence 0 MRS only - Fixed at 1 - CL[2:0] CAS latency 1 reserved 011 3 010 2 001 1 000 reserved Fixed at 0 Fixed at 000 reserved Self-refresh entry/exit control 1 Entry Initial sequence control reserved reserved reserved CAS latency - 0 Exit Init. R/W Remarks 0 1 1 1 R/W - 0 1 - 0 when being read. R/W - 0 0 - 0 when being read. R/W - 0 1 - 0 when being read. R/W 0 - - - 0 1 0 R/W - 0 when being read. R - 0 when being read. R/W - - - - - 0 I R R - 0 when being read. R/W Do not set 1 to 1 or 0 to 0. APP I/Omap S1C33401 TECHNICAL MANUAL EPSON APP-85 APPENDIX I/O MAP 0x300000-0x300F20 Register name Address Bit Chip ID/Pin Status Control Name VER3 VER2 VER1 VER0 - NAME7 NAME6 NAME5 NAME4 NAME3 NAME2 NAME1 NAME0 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 Bus signal low 0300F00 D31-12 - D11 LDRVDB (W) drive/pull-up D10 LDRVCE control register D9 LDRVAD (pMISC1) D8 LDRVRW D7-3 - D2 PUPCE D1 PUPAD D0 PUPRW 0300F04 D31-20 - Port pull-up D19 PUP9H (W) control register D18 PUP9L (pMISC2) D17 PUP8H D16 PUP8L D15 - D14 PUP7L D13 PUP6H D12 PUP6L D11 PUP5H D10 PUP5L D9 PUP4H D8 PUP4L D7 - D6 PUP3L D5 PUP2H D4 PUP2L D3 PUP1H D2 PUP1L D1 PUP0H D0 PUP0L Macro control 0300F20 D31-5 - D4 CE6CLKEN (W) register D3 - (pMISC3) D2 RTCW2 D1 RTCW1 D0 RTCW0 Device ID register (pMISC0) APP-86 0300000 (W) D31 D30 D29 D28 D27-24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Function Setting Version code 0x00: version 1.0 0x00 reserved Model ID 0x01: S1C33401 - 0x01 Product series ID 0x03: S1C333xx 0x04: S1C334xx 0x15: S1C33Lxx 0x04 Chip core ID 0x02: C33 STD 0x03: C33 mini 0x04: C33 ADV 0x05: C33 PE 0x04 reserved D15-D0 low drive #CE11-#CE4 low drive A25-A0 low drive #RD,#WRL,#WRH,#BSL low drive reserved #CE10 pull-up A17-A0 pull-up #RD,#WRL,#WRH,#BSL pull-up reserved P97-P94 pull-up P93-P90 pull-up P87-P84 pull-up P83-P80 pull-up reserved P73-P70 pull-up P67-P64 pull-up P63-P60 pull-up P56-P54 pull-up P53-P50 pull-up P47-P44 pull-up P43-P40 pull-up reserved P33-P30 pull-up P27-P24 pull-up P23-P20 pull-up P17-P14 pull-up P13-P10 pull-up P07-P04 pull-up P03-P00 pull-up reserved Area 6 peripheral clock enable reserved RTC wait control EPSON Init. R/W - 1 Low drive 0 Normal output 1 Pulled up 0 No pull-up - 1 Pulled up 0 No pull-up - 1 Pulled up 0 No pull-up - 0 No pull-up 1 Pulled up - 1 Enabled 0 Disabled - 0 to 7 (cycles) 0 0 0 0 - 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 - 0 0 0 0 - 1 1 1 - 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 - 1 1 1 Remarks R - R 0 when being read. R R - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W R/W R/W R/W R/W R/W R/W - 0 when being read. R/W - 0 when being read. R/W S1C33401 TECHNICAL MANUAL APPENDIX I/O MAP 0x301000-0x301024 Register name Address RTC interrupt status register (pRTCINTSTAT) RTC interrupt mode register (pRTCINTMODE) RTC control register (pRTC_CNTL0) 030100C RTC access (W) control register (pRTC_CNTL1) RTC second 0301010 register (W) (pRTCSEC) RTC minute register (pRTCMIN) RTC hour register (pRTCHOUR) RTC day register (pRTCDAY) 0301014 (W) 0301018 (W) 030101C (W) RTC month register (pRTCMONTH) 0301020 (W) RTC year register (pRTCYEAR) 0301024 (W) Name Bit 0301000 D31-1 (W) D0 0301004 D31-4 D3 (W) D2 0301008 (W) Real Time Clock D1 D0 D31-5 D4 D3 D2 D1 D0 D31-2 D1 D0 D31-7 D6 D5 D4 D3 D2 D1 D0 D31-7 D6 D5 D4 D3 D2 D1 D0 D31-7 D6 D5 D4 D3 D2 D1 D0 D31-6 D5 D4 D3 D2 D1 D0 D31-5 D4 D3 D2 D1 D0 D31-8 D7 D6 D5 D4 D3 D2 D1 D0 Function - reserved RTCIRQ - RTCT1 RTCT0 Interrupt status reserved RTC interrupt cycle setup RTCIMD RTCIEN RTC interrupt mode select RTC interrupt enable reserved 24H/12H mode select reserved 30-second adjustment Counter run/stop control Software reset reserved Counter busy flag Counter hold control reserved RTC 10-second counter - RTC24H - RTCADJ RTCSTP RTCRST - RTCBSY RTCHLD - RTCSH2 RTCSH1 RTCSH0 RTCSL3 RTCSL2 RTCSL1 RTCSL0 - RTCMIH2 RTCMIH1 RTCMIH0 RTCMIL3 RTCMIL2 RTCMIL1 RTCMIL0 - RTCAP RTCHH1 RTCHH0 RTCHL3 RTCHL2 RTCHL1 RTCHL0 - RTCDH1 RTCDH0 RTCDL3 RTCDL2 RTCDL1 RTCDL0 - RTCMOH RTCMOL3 RTCMOL2 RTCMOL1 RTCMOL0 - RTCYH3 RTCYH2 RTCYH1 RTCYH0 RTCYL3 RTCYL2 RTCYL1 RTCYL0 S1C33401 TECHNICAL MANUAL Setting 1 Occurred 0 Not occurred - Cycle RTCT[1:0] 11 1 hour 10 1 minute 01 1 second 00 1/64 second 1 Level sense 0 Edge trigger 1 Enabled 0 Disabled - 1 24H 0 12H - 1 Adjust 0 - 1 Stop 0 Run 1 Reset 0 - - 1 Busy 0 R/W possible 1 Hold 0 Running - 0 to 5 RTC 1-second counter 0 to 9 reserved RTC 10-minute counter - 0 to 5 RTC 1-minute counter 0 to 9 reserved AM/PM indicator RTC 10-hour counter - 1 PM 0 AM 0 to 2 or 0 to 1 RTC 1-hour counter 0 to 9 reserved RTC 10-day counter - 0 to 3 RTC 1-day counter 0 to 9 reserved RTC 10-month counter RTC 1-month counter - 0 or 1 0 to 9 reserved RTC 10-year counter - 0 to 9 RTC 1-year counter 0 to 9 EPSON Init. R/W - - I Remarks - X - X X R/W Reset by writing 1. - R/W X X - X - X X X - X X - X X X X X X X - X X X X X X X - X X X X X X X - X X X X X X R/W R/W - X X X X X - X X X X X X X X - R/W R/W - R/W - R/W R/W R/W - R R/W - R/W R/W - R/W R/W - R/W R/W R/W - R/W R/W - R/W R/W APP I/Omap APP-87 APPENDIX I/O MAP 0x301028 Register name Address Real Time Clock Bit Name 0301028 D31-3 - RTC days of D2 RTCWK2 (W) week register D1 RTCWK1 (pRTCDAYWEEK) D0 RTCWK0 APP-88 Function reserved RTC days of week counter EPSON Setting Init. R/W - RTCWK[2:0] 111 110 101 100 011 010 001 000 Days of week - Saturday Friday Thursday Wednesday Tuesday Monday Sunday - X X X Remarks - R/W S1C33401 TECHNICAL MANUAL International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: +86-10-6410-6655 Fax: +86-10-6410-7320 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-800-228-3964 Fax: +1-408-922-0238 SHANGHAI BRANCH 7F, High-Tech Bldg., 900, Yishan Road Shanghai 200233, CHINA Phone: +86-21-5423-5522 Fax: +86-21-5423-5512 - SALES OFFICES West 1960 E.Grand Avenue Flr 2 El Segundo, CA 90245, U.S.A. Phone: +1-800-249-7730 Fax: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-800-853-3588 Fax: +1-815-455-7633 Northeast 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. Phone: +1-800-922-7667 Fax: +1-781-246-5443 Southeast 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. 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IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 Fax: +81-42-587-5117 S1C33401 Technical Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epsondevice.com Document code: 410118600 Issue March, 2005 Printed in Japan L B