S1C33401F00A - Seiko Epson Corporation

Technical Manual

CMOS 32-BIT SINGLE CHIP MICROCOMPUTER

S1C33401

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission

of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not

assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or

use in any product or circuit and, further, there is no representation that this material is applicable to products requir-

ing high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by

implication or otherwise, and there is no representation or warranty that anything made in accordance with this mate-

rial will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain

technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade

Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval

from another government agency.

Devices

S1 C 33209 F 00E1

Packing specifications

00 : Besides tape & reel

0A : TCP BL 2 directions

0B : Tape & reel BACK

0C : TCP BR 2 directions

0D : TCP BT 2 directions

0E : TCP BD 2 directions

0F : Tape & reel FRONT

0G: TCP BT 4 directions

0H : TCP BD 4 directions

0J : TCP SL 2 directions

0K : TCP SR 2 directions

0L : Tape & reel LEFT

0M: TCP ST 2 directions

0N : TCP SD 2 directions

0P : TCP ST 4 directions

0Q: TCP SD 4 directions

0R : Tape & reel RIGHT

99 : Specs not fixed

Specification

Package

D: die form; F: QFP

Model number

Model name

C: microcomputer, digital products

Product classification

S1: semiconductor

Development tools

S5U1 C 33000 H2 1

Packing specifications

00: standard packing

Version

1: Version 1

Tool type

Hx : ICE

Dx : Evaluation board

Ex : ROM emulation board

Mx: Emulation memory for external ROM

Tx : A socket for mounting

Cx : Compiler package

Sx : Middleware package

Corresponding model number

33L01: for S1C33L01

Tool classification

C: microcomputer use

Product classification

S5U1: development tool for semiconductor products

Configuration of product number

Overview

Block

Power

MAP

E char

Wiring

Change

Mount

Preface

CPU

CMU

HBCU

MMU

CCU

DBG

III

Preface

BBCU

EBCU

HSDMA

IDMA

Preface

ITC

OSC3

PSC

T16

WDT

SIO

CARD

PORT

ADC

Preface

Area 6

ChipID

PinCtrl

RTC

APP

I/Omap

S1C33401 Technical Manual

I S1C33401 SPECIFICATIONS

I.1 Overview

I.2 Block Diagram

I.3 Pin Description

I.4 Power Supply

I.5 Memory Map

I.6 Electrical Characteristics

I.7 Basic External Wiring Diagram

I.8 Changes from Core/Basic Peripheral Functions

I.9 Precautions on Mounting

II C33 ADV CORE BLOCK

II.1 Preface

II.2 CPU

II.3 Clock Management Unit (CMU)

II.4 High-Speed Bus Control Unit (HBCU)

II.5 Memory Management Unit (MMU)

II.6 Cache Control Unit (CCU)

II.7 Debug Unit (DBG)

III C33 ADV BUS BLOCK

III.1 Preface

III.2 Basic Bus Control Unit (BBCU)

III.3 Extended Bus Control Unit (EBCU)

III.4 High-Speed DMA (HSDMA)

III.5 Intelligent DMA (IDMA)

IV C33 ADV BASIC PERIPHERAL BLOCK

IV.1 Preface

IV.2 Interrupt Controller (ITC)

IV.3 OSC3 Oscillator Circuit, PLL, and SSCG

IV.4 Prescaler (PSC)

IV.5 8-Bit Timers (T8)

IV.6 16-Bit Timers (T16)

IV.7 Watchdog Timer (WDT)

IV.8 Serial Interface (SIO)

IV.9 Card Interface (CARD)

IV.10 General-Purpose I/O Ports (PORT)

IV.11 A/D Converter (ADC)

V S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK

V.1 Preface

V.2 Area 6 Settings and Macro Control Register

V.3 Chip ID

V.4 Pin Control Registers

V.5 Real-Time Clock (RTC)

Appendix

I/O Map

PREFACE

S1C33401 TECHNICAL MANUAL EPSON i

Application

This manual describes the hardware functions and control registers of the S1C33401 or Seiko Epson’s RISC-type

32-bit microcomputer, and precautions to observe when designing the application system for the microcomputer.

Since this manual is written for those who design applications and circuits, knowledge of embedded-type

microcomputers and the functionality and control of general peripheral circuits is required to understand the

contents of this manual.

Organization of the Manual

I. S1C33401 Specifications

This chapter outlines the S1C33401 and describes the pin functions, electrical characteristics, and inherent

specifications of the S1C33401 that differ from standard functions of the C33 ADV core/basic peripheral

circuits. Also noise protection and other precautions to be taken when mounting the chip on the circuit board

are included.

II. C33 ADV Core Block

The C33 ADV core block is built around the CPU and incorporates various modules to control memory access

by the CPU, as listed below. This chapter describes each module. The descriptions given apply to all types of

S1C33 microcomputers using the C33 ADV macro.

• CPU

• Clock Management Unit (CMU)

• High-speed Bus Control Unit (HBCU)

• Memory Management Unit (MMU)

• Cache Control Unit (CCU)

• Debug Unit (DBG)

III. C33 ADV Bus Block

The C33 ADV bus block consists of several modules to control access to the actual internal/external devices,

as listed below. This chapter describes each module. Since the descriptions given apply to all types of S1C33

microcomputers using the C33 ADV macro, not all contents may be included in the S1C33401 due to the

limited number of pins available, etc. For details of these differences, see Section I.8, “Changes from Core/

Basic Peripheral Functions.”

• Basic Bus Control Unit (BBCU)

• Extended Bus Control Unit (EBCU)

• High-speed DMA Controller (HSDMA)

• Intelligent DMA Controller (IDMA)

IV. C33 ADV Basic Peripheral Block

The C33 ADV macro has the following built-in peripheral functions as the basic peripheral block. This chapter

describes each function. Since the descriptions given apply to all types of S1C33 microcomputers using the C33

ADV macro, not all contents may be included in the S1C33401 due to the limited number of pins available, etc.

For details of these differences, see Section I.8, “Changes from Core/Basic Peripheral Functions.”

• Interrupt Controller (ITC)

• OSC3 Oscillator Circuit, PLL, and SSCG

• Prescaler (PSC)

• 8-bit Timer (T8)

• 16-bit Timer (T16)

• Watchdog Timer (WDT)

• Serial Interface with FIFO (SIO)

• Card Interface (CARD)

• Input/Output Ports (PORT)

• A/D Converter (ADC)

PREFACE

ii EPSON S1C33401 TECHNICAL MANUAL

V. S1C33401 Area 6 Extended Peripheral Block

Area 6 of the S1C33401 incorporates the following peripheral functions that are not included in the C33 ADV

macro. This chapter describes each function.

• Chip ID Register

• Pin Control Registers

• Real Time Clock (RTC) and OSC1 Oscillator Circuit (OSC1)

Appendix

Provides a list of control registers built into the S1C33401.

Notational Conventions for Control Bits and Addresses

This manual describes some control bits as follows:

Example: 16-bit timer RUN/STOP control bits

PRUNx (D0/0x48186 + 8•x)

‘x’ in this example represents a timer number (0 to 9). Timer 0 to timer 9 have control bits for each timer that have

the same functions as other timers. This manual uses ‘x’ to describe two or more control bits (or addresses) in a

bit name (or an expression). Therefore, ‘x’ should be substituted with 0 to 9 in this example to obtain the actual bit

names and addresses.

Timer 0: PRUN0 (D0/0x48186) ∗ 0x48186 + 8 × 0 = 0x48186

Timer 1: PRUN1 (D0/0x4818E) ∗ 0x48186 + 8 × 1 = 0x4818E

Timer 2: PRUN2 (D0/0x48196)

Timer 3: PRUN3 (D0/0x4819E)

Timer 4: PRUN4 (D0/0x481A6)

Timer 5: PRUN5 (D0/0x481AE)

Timer 6: PRUN4 (D0/0x481B6)

Timer 7: PRUN7 (D0/0x481BE)

Timer 8: PRUN8 (D0/0x481C6)

Timer 9: PRUN9 (D0/0x481CE)

‘x’ is used for not only timer numbers, but also memory block numbers, A/D converter channel numbers and others.

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  iii
CONTENTS
I  S1C33401 SPECIFICATIONS
I.1  Overview .....................................................................................................................I-1-1
I.2  Block Diagram ...........................................................................................................I-2-1
I.3  Pin Description ..........................................................................................................I-3-1
I.3.1  Pin Arrangement .......................................................................................................... I-3-1
I.3.1.1  QFP Package Pin Arrangement (S1C33401F00A) ........................................ I-3-1
I.3.1.2  PFBGA Package Pin Arrangement (S1C33401B00A) ................................... I-3-2
I.3.2  Pin Functions ............................................................................................................... I-3-3
I.3.3  Switching Over the Multiplexed Pin Functions ............................................................. I-3-8
I.3.3.1  Pin Function Select Bits ................................................................................. I-3-8
I.3.3.2  List of Port Function Select Registers ........................................................... I-3-11
0x40360: P00–P03 Port Function Select Register (pP0_03_CFP) ......................................... I-3-12
0x40361: P04–P07 Port Function Select Register (pP0_47_CFP) ......................................... I-3-13
0x40362: P10–P13 Port Function Select Register (pP1_03_CFP) ......................................... I-3-14
0x40363: P14–P17 Port Function Select Register (pP1_47_CFP) ......................................... I-3-15
0x40364: P20–P23 Port Function Select Register (pP2_03_CFP) ......................................... I-3-16
0x40365: P24–P27 Port Function Select Register (pP2_47_CFP) ......................................... I-3-17
0x40366: P30–P33 Port Function Select Register (pP3_03_CFP) ......................................... I-3-18
0x40368: P40–P43 Port Function Select Register (pP4_03_CFP) ......................................... I-3-19
0x40369: P44–P47 Port Function Select Register (pP4_47_CFP) ......................................... I-3-20
0x4036A: P50–P53 Port Function Select Register (pP5_03_CFP) ......................................... I-3-21
0x4036B: P54–P56 Port Function Select Register (pP5_46_CFP) ......................................... I-3-22
0x4036C: P60–P63 Port Function Select Register (pP6_03_CFP) ......................................... I-3-23
0x4036D: P64–P67 Port Function Select Register (pP6_47_CFP) ......................................... I-3-24
0x4036E: P70–P73 Port Function Select Register (pP7_03_CFP) ......................................... I-3-25
0x40370: P80–P83 Port Function Select Register (pP8_03_CFP) ......................................... I-3-26
0x40371: P84–P87 Port Function Select Register (pP8_47_CFP) ......................................... I-3-27
0x40372: P90–P93 Port Function Select Register (pP9_03_CFP) ......................................... I-3-28
0x40373: P94–P97 Port Function Select Register (pP9_47_CFP) ......................................... I-3-29
I.3.4  Input/Output Cells and Input/Output Characteristics ................................................... I-3-30
I.3.5  Package ...................................................................................................................... I-3-33
I.3.5.1  QFP20-184pin Package ................................................................................ I-3-33
I.3.5.2  PFBGA-160pin Package ............................................................................... I-3-34
I.3.5.3  Thermal Resistance of the Package ............................................................. I-3-35
I.4  Power Supply .............................................................................................................I-4-1
I.4.1  Power Supply Pins ....................................................................................................... I-4-1
I.4.2  Operating Voltage (VDD, VSS) ........................................................................................ I-4-2
I.4.3  Power Supply for PLL (PLLVDD, PLLVSS) ...................................................................... I-4-2
I.4.4  Power Supply for I/O Interface (VDDE) .......................................................................... I-4-2
I.4.5  Power Supply for T16 PWM Output (P1x) Ports (TMVDD) ............................................ I-4-2
I.4.6  Power Supply for Analog Circuits (AVDD) ..................................................................... I-4-2
I.4.7  Power Supply for RTC (RTCVDD) ................................................................................. I-4-2
I.4.8  Precautions on Power Supply ...................................................................................... I-4-3

CONTENTS
iv  EPSON  S1C33401 TECHNICAL MANUAL
I.5  Memory Map ..............................................................................................................I-5-1
I.5.1  ROM and Boot Address ............................................................................................... I-5-2
I.5.2  Area 0 (A0RAM) ........................................................................................................... I-5-2
I.5.3  Area 1 (Internal I/O) ..................................................................................................... I-5-3
I.5.4  Area 2 (Debug Area) .................................................................................................... I-5-3
I.5.5  Area 3 (A3RAM) ........................................................................................................... I-5-3
I.5.6  Area 6 (Extended I/O) .................................................................................................. I-5-3
I.5.7  External Memory Area ................................................................................................. I-5-4
I.5.8  Limitations on Areas 0 to 6 ........................................................................................... I-5-4
I.6  Electrical Characteristics ..........................................................................................I-6-1
I.6.1  Absolute Maximum Rating ........................................................................................... I-6-1
I.6.2  Recommended Operating Conditions .......................................................................... I-6-1
I.6.3  DC Characteristics ....................................................................................................... I-6-2
I.6.4  Current Consumption ................................................................................................... I-6-3
I.6.5  A/D Converter Characteristics ...................................................................................... I-6-4
I.6.6  Oscillation Characteristics ............................................................................................ I-6-5
I.6.7  PLL Characteristics ...................................................................................................... I-6-6
I.6.8  AC Characteristics ....................................................................................................... I-6-7
I.6.8.1  Symbol Description ........................................................................................ I-6-7
I.6.8.2  AC Characteristics Measurement Condition .................................................. I-6-7
I.6.8.3  BBCU AC Characteristic Tables ..................................................................... I-6-8
I.6.8.4  BBCU AC Characteristic Timing Charts ......................................................... I-6-9
I.6.8.5  SDRAM Interface AC Characteristics ........................................................... I-6-13
I.7  Basic External Wiring Diagram ................................................................................I-7-1
I.8  Changes from Core/Basic Peripheral Functions ....................................................I-8-1
I.8.1  Limitations on the BBCU and EBCU ............................................................................ I-8-1
I.8.2  Limitations on the A/D Converter ................................................................................. I-8-2
I.9  Precautions on Mounting .........................................................................................I-9-1

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  v
II  C33 ADV CORE BLOCK
II.1  Preface ...................................................................................................................... II-1-1
II.2  CPU ........................................................................................................................... II-2-1
II.2.1  Features ......................................................................................................................II-2-1
II.2.2  Registers .....................................................................................................................II-2-3
II.2.3  Instruction Set ............................................................................................................. II-2-4
II.2.4  
Address Space and Logical to Physical Address Translation ..............................................II-2-8
II.2.4.1  Overview .......................................................................................................II-2-8
II.2.4.2  Address Processing ......................................................................................II-2-9
II.2.4.3  Block Processing .........................................................................................II-2-11
II.2.4.4  ASID Processing ..........................................................................................II-2-12
II.2.4.5  MMU Processing (Address Translation) .......................................................II-2-12
II.2.4.6  Mirror Processing .........................................................................................II-2-13
II.2.4.7  Area Processing ..........................................................................................II-2-13
II.3  Clock Management Unit (CMU) .............................................................................. II-3-1
II.3.1  Overview of the CMU ..................................................................................................II-3-1
II.3.2  Reset Input and Initial Reset .......................................................................................II-3-2
II.3.2.1  Initial Reset Pins ........................................................................................... II-3-2
II.3.2.2  Cold Reset and Hot Reset ............................................................................ II-3-2
II.3.2.3  Power-on Reset ............................................................................................ II-3-3
II.3.2.4  Boot Address ................................................................................................II-3-3
II.3.2.5  Precautions to be Taken during Initial Reset ................................................. II-3-4
II.3.3  NMI Input  ....................................................................................................................II-3-5
II.3.3.1  NMI Detection Mode ..................................................................................... II-3-5
II.3.3.2  NMI Flag .......................................................................................................II-3-5
II.3.4  Selecting the System Clock Source ............................................................................II-3-6
II.3.5  Controlling the Oscillator Circuit .................................................................................. II-3-7
II.3.6  Controlling the PLL ......................................................................................................II-3-8
II.3.6.1  On/Off Control of the PLL .............................................................................II-3-8
II.3.6.2  Setting the Frequency Multiplication Rate ....................................................II-3-8
II.3.6.3  Other PLL Settings .......................................................................................II-3-9
II.3.7  Control of the SSCG ..................................................................................................II-3-11
II.3.7.1  Turning the SSCG On/Off ............................................................................ II-3-11
II.3.7.2  Setting SS Modulation Parameters .............................................................. II-3-12
II.3.8  Setting the Core System Clock (CCLK) .....................................................................II-3-13
II.3.9  Setting the Peripheral Circuit Clock (PCLK) ...............................................................II-3-14
II.3.10  Setting the External Clock Output (CMU_CLK) .......................................................II-3-15
II.3.11  Controlling Clock Supply ..........................................................................................II-3-16
II.3.11.1  Software Control of Clock Supply ..............................................................II-3-16
II.3.11.2  Automatic Control of Clock Supply ............................................................II-3-17
II.3.12  Standby Modes ........................................................................................................ II-3-18
II.3.12.1  HALT Mode ................................................................................................ II-3-18
II.3.12.2  HALT2 Mode .............................................................................................. II-3-18
II.3.12.3  SLEEP Mode .............................................................................................II-3-18
II.3.12.4  Precautions ................................................................................................II-3-20

CONTENTS
vi  EPSON  S1C33401 TECHNICAL MANUAL
II.3.13  Clock Setup Procedure ............................................................................................ II-3-21
II.3.13.1  Changing the Clock Source from OSC3 to PLL .........................................II-3-21
II.3.13.2  Changing the Clock Source from PLL to OSC3,  
                    then Turning Off the PLL  ......................................................................II-3-22
II.3.13.3  Changing the Clock Source from OSC3 or PLL to OSC1,  
                    then Turning Off OSC3 and PLL  ..........................................................II-3-23
II.3.13.4  Changing the Clock Source from OSC1 to OSC3 .....................................II-3-24
II.3.13.5  Changing the Clock Source from OSC1 to PLL .........................................II-3-25
II.3.13.6  Turning Off OSC3 during SLEEP ...............................................................II-3-26
II.3.13.7  SLEEP Keeping Oscillation On (without Clock Change) ...........................II-3-27
II.3.13.8  HALT/HALT2 ..............................................................................................II-3-28
II.3.14  Power-Down Control ................................................................................................II-3-29
II.3.15  Details of Control Registers ..................................................................................... II-3-30
0x40180: Peripheral Clock Control Register 1 (pCMU1_CLKCNTL_0) ...................................II-3-31
0x40181: Peripheral Clock Control Register 2 (pCMU1_CLKCNTL_1) ...................................II-3-32
0x40184: PLL Control Register 1 (pCMU1_PLL_CNTL0) .......................................................II-3-33
0x40185: PLL Control Register 2 (pCMU1_PLL_CNTL1) .......................................................II-3-34
0x40186: PLL Control Register 3 (pCMU1_PLL_CNTL2) .......................................................II-3-35
0x40187: SS Macro Control Register 1 (pCMU1_SS_CNTL0) ...............................................II-3-36
0x40188: SS Macro Control Register 2 (pCMU1_SS_CNTL1) ...............................................II-3-37
0x48360: Core System Clock Control Register (pCMU2_CNTL_CORE) ................................II-3-38
0x48362: Core System Clock On/Off Register (pCMU2_SET) ................................................II-3-40
0x48364: Core System Clock Automatic Control Register (pCMU2_AUTO) ...........................II-3-41
0x48366: Peripheral and External Clock Output Control Register (pCMU2_CNTL_PERI) .....II-3-42
0x48368: Clock Option Register (pCMU2_OPT) .....................................................................II-3-43
0x4836A: NMI Flag Register (pCMU2_NMI_FLAG) ................................................................II-3-45
0x4836C: NMI Mode Register (pCMU2_NMI_MODE) ............................................................II-3-46
0x4836E: Clock Control Protect Register (pCMU2_PROTECT) ..............................................II-3-47
0x48370: CCLK System Peripheral Clock On/Off Register (pCMU2_CCLK_PERI) ................II-3-48
0x48372: CCLK System Peripheral Clock Automatic Control Register  
                    (pCMU2_AUTO_CCLK_PERI) ..........................................................................II-3-50
II.3.16  Precautions .............................................................................................................. II-3-52
II.4  High-Speed Bus Control Unit (HBCU) .........................................................................II-4-1
II.4.1  Overview of the HBCU  ...............................................................................................II-4-1
II.4.2  Outline of Address Processing .................................................................................... II-4-2
II.4.3  Managing the Address Space .....................................................................................II-4-4
II.4.3.1  Contents of Individual Block Settings ............................................................ II-4-5
II.4.3.2  Settings for the Entire Address Space ..........................................................II-4-6
II.4.4  Bus Access .................................................................................................................II-4-7
II.4.4.1  Cache Access ...............................................................................................II-4-7
II.4.4.2  External Memory Access .............................................................................. II-4-7
II.4.4.3  Area 0 Internal Memory Access ................................................................... II-4-7
II.4.5  ASID and Multiple Virtual Spaces ............................................................................... II-4-8
II.4.6  Address ASID and Mirror Processing ......................................................................... II-4-9
II.4.7  Details of Control Registers ....................................................................................... II-4-11
0x48300: Address Control Register (pHBCU_ADR_CNT) ......................................................II-4-12
0x48302–0x48310: Block x Configuration Registers (pHBCU_BLKx) .....................................II-4-13
0x48312: ASID Setup Register (pHBCU_ASID_SETUP) ........................................................II-4-15
0x48314: Logical ASID Setup Register (pHBCU_LOGIC_ASID) ............................................II-4-16
II.4.8  Precautions ................................................................................................................ II-4-17

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  vii
II.5  Memory Management Unit (MMU) .......................................................................... II-5-1
II.5.1  Overview of the MMU ..................................................................................................II-5-1
II.5.2  Logical and Physical Address Spaces ........................................................................ II-5-2
II.5.2.1  Logical Address Space ................................................................................. II-5-2
II.5.2.2  Physical Address Space ...............................................................................II-5-2
II.5.2.3  Relationship between Logical and Physical Address Spaces .......................II-5-2
II.5.3  Configuration of the MMU ........................................................................................... II-5-4
II.5.3.1  TAG Part and DATA Part ...............................................................................II-5-4
II.5.3.2  LRU ............................................................................................................... II-5-6
II.5.4  Settings and Operation of the MMU  ........................................................................... II-5-7
II.5.4.1  Enabling the MMU ........................................................................................II-5-7
II.5.4.2  Specifying a Page Size .................................................................................II-5-7
II.5.4.3  ASID Processing  ..........................................................................................II-5-7
II.5.4.4  Address Translation .......................................................................................II-5-8
II.5.5  Setting Up the TLB ..................................................................................................... II-5-11
II.5.5.1  Setting Up the TLB ....................................................................................... II-5-11
II.5.5.2  Confirming the Set Content of the TLB ........................................................II-5-12
II.5.5.3  Flushing the TLB .......................................................................................... II-5-12
II.5.6  MMU Exceptions ........................................................................................................II-5-13
II.5.6.1  Types of MMU Exceptions ...........................................................................II-5-13
II.5.6.2  MMU Exception Vector Address and Stack Area .........................................II-5-14
II.5.6.3  Processing when an MMU Exception Occurs .............................................. II-5-14
II.5.7  Details of the Control Registers ................................................................................. II-5-16
0x48320: MMU Control Register (pMMU_CNTL) ....................................................................II-5-17
0x48322: MMU Entry Register (pMMU_ENTRY) ....................................................................II-5-18
0x48324: MMU 4KB Data Address Register (pMMU_ADR_4K) .............................................II-5-19
0x48326: MMU Common Data Address Register (pMMU_ADR_COM) ..................................II-5-19
0x48328: MMU TAG Address Register (pMMU_TAD_ADR) ....................................................II-5-20
0x4832A: MMU Page Setting Register (pMMU_PAGE_SETUP) .............................................II-5-21
0x4832C: TLB Control Register (pMMU_TLB_CNTL) .............................................................II-5-23
0x4832E: MMU Exception Status Register (pMMU_EXCP_STAT) .........................................II-5-25
0x48330: MMU Exception Address Register 1 (pMMU_EXP_ADR) .......................................II-5-27
0x48332: MMU Exception Address Register 2 ........................................................................II-5-27
0x48334: MMU LRU Register (pMMU_LRU) ...........................................................................II-5-28
II.5.8  Precautions ................................................................................................................ II-5-29
II.6  Cache Control Unit (CCU) ....................................................................................... II-6-1
II.6.1  Overview of the CCU ..................................................................................................II-6-1
II.6.2  Configuration of the Cache .........................................................................................II-6-2
II.6.2.1  TAG Part and DATA Part ...............................................................................II-6-2
II.6.2.2  LRU Part .......................................................................................................II-6-2
II.6.3  Settings and Operation of the Cache ..........................................................................II-6-3
II.6.3.1  Enabling the Cache ....................................................................................... II-6-3
II.6.3.2  Address Comparison and Cache Hit/Miss .................................................... II-6-3
II.6.3.3  Read Operation ............................................................................................II-6-5
II.6.3.4  Write Operation ............................................................................................. II-6-5
II.6.3.5  Flush ............................................................................................................. II-6-6
II.6.3.6  Setting Up the Cache ....................................................................................II-6-7
II.6.3.7  Write-back in Software .................................................................................. II-6-8
II.6.4  Lock Function .............................................................................................................. II-6-9
II.6.5  Lock for Interrupt Processing ..................................................................................... II-6-10
II.6.6  Consistency of the Cache Data .................................................................................. II-6-11

CONTENTS
viii  EPSON  S1C33401 TECHNICAL MANUAL
II.6.7  Details of Control Registers ....................................................................................... II-6-12
0x48340: Cache Configuration Register (pCCU_SETUP) .......................................................II-6-13
0x48342: Cache Way Number Select Register (pCCU_ENTRY) ............................................II-6-14
0x48344: Cache Entry Control Register (pCCU_ENTRY_CNTL) ...........................................II-6-15
0x48346: Cache Control Register (pCCU_CNTL) ...................................................................II-6-16
0x48348: Cache TAG Address Register 1 (pCCU_ADR) ........................................................II-6-19
0x4834A: Cache TAG Address Register 2 ...............................................................................II-6-20
0x4834C: Cache Data Register 1 (pCCU_DATA) ....................................................................II-6-21
0x4834E: Cache Data Register 2 ............................................................................................II-6-21
0x48350: Interrupt Lock Setup Register (pCCU_LOCK) .........................................................II-6-22
0x48352: Cache LRU Register (pCCU_LRU) ..........................................................................II-6-23
II.6.8  Precautions ................................................................................................................ II-6-24
II.7  Debug Unit (DBG) .................................................................................................... II-7-1
II.7.1  Overview of the DBG ..................................................................................................II-7-1
II.7.2  Input/Output Pins of the DBG ...................................................................................... II-7-1
II.7.3  Overview of Functions ................................................................................................. II-7-2
II.7.4  Details of Control Registers ........................................................................................ II-7-3
0x402E8: Debug Signal Output Control Write-Protect Register ...............................................II-7-4
0x402EC: Debug Signal Output Control Register .....................................................................II-7-5
II.7.5  Precautions ................................................................................................................. II-7-6

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  ix
III  C33 ADV BUS BLOCK
III.1  Preface .....................................................................................................................III-1-1
III.2  Basic Bus Control Unit (BBCU) .............................................................................III-2-1
III.2.1  Overview of the BBCU .............................................................................................. III-2-1
III.2.2  BBCU Pins ................................................................................................................ III-2-2
III.2.3  General Memory Map ............................................................................................... III-2-3
III.2.4  Internal RAM Area (Areas 0 and 3) ........................................................................... III-2-4
III.2.5  Internal I/O and Debug Areas (Areas 1 and 2) .......................................................... III-2-5
III.2.5.1  Internal I/O Area (Area 1) ........................................................................... III-2-5
III.2.5.2  Debug Area (Area 2) ................................................................................... III-2-5
III.2.6  External Memory Area (Areas 4 to 22) ..................................................................... III-2-6
III.2.6.1  External Memory Area and Chip Enable .................................................... III-2-6
III.2.6.2  Area 20 and Boot Mode .............................................................................. III-2-6
III.2.6.3  Extended I/O Area ...................................................................................... III-2-6
III.2.6.4  Summary of Programmable External Memory Access Conditions ............. III-2-7
III.2.6.5  Common Condition Settings ....................................................................... III-2-9
III.2.6.6  Per-Area Condition Settings ...................................................................... III-2-10
III.2.7  Connection of External Devices and Bus Operation ................................................ III-2-18
III.2.7.1  Connecting External Devices  .................................................................... III-2-18
III.2.7.2  Data Configuration in Memory ................................................................... III-2-19
III.2.7.3  External Bus Operation .............................................................................. III-2-19
III.2.8  BBCU Operating Clock and Bus Clock .................................................................... III-2-22
III.2.8.1  Operating Clock of the BBCU .................................................................... III-2-22
III.2.8.2  Generation of the Bus Clock ...................................................................... III-2-23
III.2.8.3  External Output of the Bus Clock ............................................................... III-2-23
III.2.9  Bus Access Timing Chart ......................................................................................... III-2-24
III.2.9.1  SRAM Read/Write Timing (with no External WAIT) ................................... III-2-24
III.2.9.2  SRAM Read/Write Timing (with External WAIT) ........................................ III-2-31
III.2.9.3  Burst ROM Page Read Timing ................................................................... III-2-33
III.2.9.4  BCLK Synchronous/Asynchronous Memory Access Timing ..................... III-2-36
III.2.9.5  SRAM Access when Device Size < Data Size ........................................... III-2-37
III.2.10  External Bus Requests and Release of Bus Control .............................................. III-2-38
III.2.11  Control Register Details ......................................................................................... III-2-39
0x48380: BCLK Divide Control Register (pBBCU_BCLK_DIV) .............................................. III-2-40
0x48384: Bus Control Register (pBBCU_BUSCTL) ............................................................... III-2-41
0x48386: Common Cycle Control Register (pBBCU_CM_CYC) ............................................ III-2-42
0x48388–0x483A4: CEx Area Configuration Registers (pBBCU_CExSET) ........................... III-2-43
0x4838A–0x483A6: CEx Access Cycle Control Registers (pBBCU_CExACCNT) ................. III-2-46
III.2.12  Precautions ............................................................................................................ III-2-50
III.3  Extended Bus Control Unit (EBCU) ......................................................................III-3-1
III.3.1  Overview of the EBCU .............................................................................................. III-3-1
III.3.2  EBCU Pins ................................................................................................................ III-3-2
III.3.3  Configuration of SDRAM ........................................................................................... III-3-3
III.3.3.1  SDRAM Area .............................................................................................. III-3-3
III.3.3.2  Setting SDRAM Size and Address .............................................................. III-3-3
III.3.3.3  Configuration of SDRAM Chips .................................................................. III-3-6
III.3.3.4  Example Connection of SDRAMs ............................................................... III-3-6
III.3.3.5  Bus Operations of SDRAM ......................................................................... III-3-8

CONTENTS
x  EPSON  S1C33401 TECHNICAL MANUAL
III.3.4  EBCU Operating Clock and SDRAM Clock ............................................................... III-3-9
III.3.4.1  Operating Clock of the EBCU  .................................................................... III-3-9
III.3.4.2  Generation of SDRAM Clock ..................................................................... III-3-10
III.3.5  Setting SDRAM Access Conditions ......................................................................... III-3-11
III.3.6  Control and Operation of SDRAM Interface ............................................................. III-3-16
III.3.6.1  Initializing SDRAM ..................................................................................... III-3-16
III.3.6.2  Read/Write Operations .............................................................................. III-3-18
III.3.6.3  SDRAM Refresh ........................................................................................ III-3-35
III.3.6.4  SDRAM Refresh Request when External Bus is Released ....................... III-3-38
III.3.7  SDRAM Commands ................................................................................................. III-3-39
III.3.8  Control Register Details ........................................................................................... III-3-40
0x483C0: SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF) ............................... III-3-41
0x483C2: Refresh Counter Register (pEBCU_RFTIM) .......................................................... III-3-42
0x483C4: Refresh Period Register (pEBCU_RFPOD) ........................................................... III-3-43
0x483C6: SDRAM Option Register (pEBCU_SDOPT) .......................................................... III-3-44
0x483C8: SDRAM Access Control Register (pEBCU_SDACR) ............................................. III-3-46
0x483CA: SDRAM Mode Register (pEBCU_SDMOD) ........................................................... III-3-48
0x483CC: Self-refresh Control Register (pEBCU_SLFEX) .................................................... III-3-49
III.3.9  Precautions .............................................................................................................. III-3-50
III.4  High-Speed DMA (HSDMA) ....................................................................................III-4-1
III.4.1  Functional Outline of HSDMA ................................................................................... III-4-1
III.4.2  I/O Pins of HSDMA ................................................................................................... III-4-5
III.4.3  Programming Control Information ............................................................................. III-4-6
III.4.3.1  Standard Mode and Advanced Mode ......................................................... III-4-6
III.4.3.2  Setting the Registers in Dual-Address Mode .............................................. III-4-6
III.4.3.3  Setting the Registers in Single-Address Mode ........................................... III-4-9
III.4.4  Enabling/Disabling DMA Transfer ............................................................................. III-4-12
III.4.5  Trigger Source .......................................................................................................... III-4-13
III.4.6  Operation of HSDMA ............................................................................................... III-4-14
III.4.6.1  Operation in Dual-Address Mode .............................................................. III-4-14
III.4.6.2  Operation in Single-Address Mode ............................................................ III-4-18
III.4.7  Interrupt Function of HSDMA ................................................................................... III-4-22
III.4.8  HSDMA Operating Clock .......................................................................................... III-4-23
III.4.9  Details of Control Registers ..................................................................................... III-4-24
0x48220–0x48250: HSDMA Ch.x Transfer Counter Registers (pHSx_CNT) ......................... III-4-26
0x48222–0x48252: HSDMA Ch.x Control Registers .............................................................. III-4-27
0x48224–0x48254: HSDMA Ch.x Low-Order Source Address Setup Registers  
                              (pHSx_SADR) ....................................................................................... III-4-28
0x48226–0x48256: HSDMA Ch.x High-Order Source Address Setup Registers ................... III-4-29
0x48228–0x48258: HSDMA Ch.x Low-Order Destination Address Setup Registers  
                              (pHSx_DADR) ...................................................................................... III-4-31
0x4822A–0x4825A: HSDMA Ch.x High-Order Destination Address Setup Registers ........... III-4-32
0x4822C–0x4825C: HSDMA Ch.x Enable Registers (pHSx_EN) .......................................... III-4-34
0x4822E–0x4825E: HSDMA Ch.x Trigger Flag Registers (pHSx_TF) ................................... III-4-35
0x48262–0x48292: HSDMA Ch.x Control Registers (pHSx_ADVMODE) for ADV mode ....... III-4-36
0x48264–0x48296: HSDMA Ch.x Source Address Setup Registers  
                              (pHSx_AD_SADR) for ADV mode ........................................................ III-4-38
0x48268–0x4829A: HSDMA Ch.x Destination Address Setup Registers  
                              (pHSx_ADV_DADR) for ADV mode ...................................................... III-4-40
0x4829C: HSDMA STD/ADV Mode Select Register (pHS_CNTLMODE) .............................. III-4-42
III.4.10  Precautions ............................................................................................................ III-4-43

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  xi
III.5  Intelligent DMA (IDMA) ...........................................................................................III-5-1
III.5.1  Functional Outline of IDMA ....................................................................................... III-5-1
III.5.2  Programming Control Information ............................................................................. III-5-3
III.5.2.1  Setting the Base Address ........................................................................... III-5-3
III.5.2.2  Control Information ..................................................................................... III-5-3
III.5.3  IDMA Invocation ........................................................................................................ III-5-8
III.5.4  Operation of IDMA ................................................................................................... III-5-11
III.5.4.1  Single Transfer Mode ................................................................................. III-5-11
III.5.4.2  Successive Transfer Mode ......................................................................... III-5-12
III.5.4.3  Block Transfer Mode .................................................................................. III-5-13
III.5.5  Linking ...................................................................................................................... III-5-15
III.5.6  Interrupt Function of Intelligent DMA ........................................................................ III-5-16
III.5.7  Details of Control Registers ..................................................................................... III-5-17
0x48200: IDMA Base Address Register 0 (pIDMABASE) ...................................................... III-5-18
0x48202: IDMA Base Address Register 1 .............................................................................. III-5-18
0x48204: IDMA Start Register (pIDMA_START) .................................................................... III-5-19
0x48205: IDMA Enable Register (pIDMA_EN) ....................................................................... III-5-20
III.5.8  Precautions .............................................................................................................. III-5-21

CONTENTS
xii  EPSON  S1C33401 TECHNICAL MANUAL
IV  C33 ADV BASIC PERIPHERAL BLOCK
IV.1  Preface .................................................................................................................... IV-1-1
IV.2  Interrupt Controller (ITC) ...................................................................................... IV-2-1
IV.2.1  Outline of Interrupt Functions .................................................................................... IV-2-1
IV.2.1.1  Maskable Interrupts .................................................................................... IV-2-1
IV.2.1.2  Causes of Interrupt and Intelligent DMA ..................................................... IV-2-3
IV.2.1.3  Nonmaskable Interrupt (NMI) ...................................................................... IV-2-3
IV.2.1.4  Interrupt Processing by the CPU ................................................................ IV-2-4
IV.2.1.5  Clearing Standby Mode by Interrupts ......................................................... IV-2-4
IV.2.2  Trap Table .................................................................................................................. IV-2-6
IV.2.3  ITC Operating Clock .................................................................................................. IV-2-7
IV.2.4  Control of Maskable Interrupts .................................................................................. IV-2-8
IV.2.4.1  Structure of the Interrupt Controller ............................................................ IV-2-8
IV.2.4.2  Processor Status Register (PSR) ............................................................... IV-2-8
IV.2.4.3  Cause-of-Interrupt Flag and Interrupt Enable Register ............................... IV-2-9
IV.2.4.4  Interrupt Priority Register and Interrupt Levels .......................................... IV-2-11
IV.2.5  IDMA Invocation ....................................................................................................... IV-2-12
IV.2.6  HSDMA Invocation ................................................................................................... IV-2-14
IV.2.7  Details of Control Registers ..................................................................................... IV-2-15
0x40260: Port Input 0–1 Interrupt Priority Register (pINT_PR01L) ........................................ IV-2-17
0x40261: Port Input 2–3 Interrupt Priority Register (pINT_PR23L) ........................................ IV-2-18
0x40262: Key Input Interrupt Priority Register (pINT_PK01L) ................................................ IV-2-19
0x40263: HSDMA Ch.0–1 Interrupt Priority Register (pINT_PHSD01L) ................................ IV-2-20
0x40264: HSDMA Ch.2–3 Interrupt Priority Register (pINT_PHSD23L) ................................ IV-2-21
0x40265: IDMA Interrupt Priority Register (pINT_PDM) ......................................................... IV-2-22
0x40266: 16-bit Timer 0–1 Interrupt Priority Register (pINT_P16T01) ................................... IV-2-23
0x40267: 16-bit Timer 2–3 Interrupt Priority Register (pINT_P16T23) ................................... IV-2-24
0x40268: 16-bit Timer 4–5 Interrupt Priority Register (pINT_P16T45) ................................... IV-2-25
0x40269: 8-bit Timer, Serial I/F Ch.0 Interrupt Priority Register (pINT_P8T_PSI00) ............. IV-2-26
0x4026A: Serial I/F Ch.1, A/D Interrupt Priority Register (pINT_PSI01_PAD) ....................... IV-2-27
0x4026B: RTC Interrupt Priority Register (pINT_PCTM) ........................................................ IV-2-28
0x4026C: Port Input 4–5 Interrupt Priority Register (pINT_PR45L) ....................................... IV-2-29
0x4026D: Port Input 6–7 Interrupt Priority Register (pINT_PR67L) ....................................... IV-2-30
0x4026E: Serial I/F Ch.2–3 Interrupt Priority Register (pINT_PSI0203) ................................ IV-2-31
0x40270: Key Input, Port Input 0–3 Interrupt Enable Register (pINT_EK01_EP03) ............... IV-2-32
0x40271: DMA Interrupt Enable Register (pINT_EDMA) ....................................................... IV-2-33
0x40272: 16-bit Timer 0–1 Interrupt Enable Register (pINT_E16T01) ................................... IV-2-34
0x40273: 16-bit Timer 2–3 Interrupt Enable Register (pINT_E16T23) ................................... IV-2-35
0x40274: 16-bit Timer 4–5 Interrupt Enable Register (pINT_E16T45) ................................... IV-2-36
0x40275: 8-bit Timer 0–3 Interrupt Enable Register (pINT_E8T03) ....................................... IV-2-37
0x40276: Serial I/F Ch.0–1 Interrupt Enable Register (pINT_ESIF01) ................................... IV-2-38
0x40277: Port Input 4–7, RTC, A/D Interrupt Enable Register (pINT_EP47_ECT_EAD) ....... IV-2-39
0x40278: 8-bit Timer 4–5 Interrupt Enable Register (pINT_E8T45) ....................................... IV-2-40
0x40279: Serial I/F Ch.2–3 Interrupt Enable Register (pINT_ESIF23) ................................... IV-2-41
0x40280: Key Input, Port Input 0–3 Interrupt Cause Flag Register (pINT_FK01_FP03) ........ IV-2-42
0x40281: DMA Interrupt Cause Flag Register (pINT_FDMA) ................................................ IV-2-44
0x40282: 16-bit Timer 0–1 Interrupt Cause Flag Register (pINT_F16T01) ............................ IV-2-45
0x40283: 16-bit Timer 2–3 Interrupt Cause Flag Register (pINT_F16T23) ............................ IV-2-46
0x40284: 16-bit Timer 4–5 Interrupt Cause Flag Register (pINT_F16T45) ............................ IV-2-47
0x40285: 8-bit Timer 0–3 Interrupt Cause Flag Register (pINT_F8T03) ................................ IV-2-48
0x40286: Serial I/F Ch.0–1 Interrupt Cause Flag Register (pINT_FSIF01) ............................ IV-2-49
0x40287: Port Input 4–7, RTC, A/D Interrupt Cause Flag Register (pINT_FP47_FCT_FAD) ... IV-2-50
0x40288: 8-bit Timer 4–5 Interrupt Cause Flag Register (pINT_F8T45) ................................ IV-2-51
0x40289: Serial I/F Ch.2–3 Interrupt Cause Flag Register (pINT_FSIF23) ............................ IV-2-52

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  xiii
0x40290: Port Input 0–3, HSDMA Ch.0–1, 16-bit Timer 0 IDMA Request Register  
                    (pIDMAREQ_RP03_RHS_R16T0) .................................................................. IV-2-53
0x40291: 16-bit Timer 1–4 IDMA Request Register (pIDMAREQ_R16T14) .......................... IV-2-54
0x40292: 16-bit Timer 5, 8-bit Timer 0–3, Serial I/F Ch.0 IDMA Request Register  
                    (pIDMAREQ_R16T5_R8T_RSIF0) .................................................................. IV-2-55
0x40293: Serial I/F Ch.1, A/D, Port Input 4–7 IDMA Request Register  
                    (pIDMAREQ_RSIF1_RAD_RP47) ................................................................... IV-2-56
0x40294: Port Input 0–3, HSDMA Ch.0–1, 16-bit Timer 0 IDMA Enable Register  
                    (pIDMAEN_DEP03_DEHS_DE16T0) .............................................................. IV-2-57
0x40295: 16-bit Timer 1–4 IDMA Enable Register (pIDMAEN_DE16T14) ............................. IV-2-58
0x40296: 16-bit Timer 5, 8-bit Timer 0–3, Serial I/F Ch.0 IDMA Enable Register  
                    (pIDMAEN_DE16T5_DE8T_DESIF0) .............................................................. IV-2-59
0x40297: Serial I/F Ch.1, A/D, Port Input 4–7 IDMA Enable Register  
                    (pIDMAEN_DESIF1_DEAD_DEP47) ............................................................... IV-2-60
0x40298: HSDMA Ch.0–1 Trigger Set-up Register (pHSDMA_HTGR1) ................................ IV-2-61
0x40299: HSDMA Ch.2–3 Trigger Set-up Register (pHSDMA_HTGR2) ................................ IV-2-61
0x4029A: HSDMA Software Trigger Register (pHSDMA_HSOFTTGR) ................................. IV-2-63
0x4029B: 8-bit Timer 4–5, Serial I/F Ch.2–3 IDMA Request Register  
                    (pIDMAREQ_R8T45_RSIF23) ......................................................................... IV-2-64
0x4029C: 8-bit Timer 4–5, Serial I/F Ch.2–3 IDMA Enable Register  
                    (pIDMAEN_DE8T45_DESIF23) ....................................................................... IV-2-65
0x4029F: Flag Set/Reset Method Select Register (pRST_RESET) ....................................... IV-2-66
0x402A0: Port Input 8–9 Interrupt Priority Register (pINT_PR89L) ........................................ IV-2-67
0x402A1: Port Input 10–11 Interrupt Priority Register (pINT_PR1011L) ................................ IV-2-68
0x402A2: Port Input 12–13 Interrupt Priority Register (pINT_PR1213L) ................................ IV-2-69
0x402A3: Port Input 14–15 Interrupt Priority Register (pINT_PR1415L) ................................ IV-2-70
0x402A4: 16-bit Timer 6–7 Interrupt Priority Register (pINT_P16T67) ................................... IV-2-71
0x402A5: 16-bit Timer 8–9 Interrupt Priority Register (pINT_P16T89) ................................... IV-2-72
0x402A6: Port Input 8–15 Interrupt Enable Register (pINT_EP815) ...................................... IV-2-73
0x402A7: 16-bit Timer 6–7 Interrupt Enable Register (pINT_E16T67) ................................... IV-2-74
0x402A8: 16-bit Timer 8–9 Interrupt Enable Register (pINT_E16T89) ................................... IV-2-75
0x402A9: Port Input 8–15 Interrupt Cause Flag Register (pINT_FP815) ............................... IV-2-76
0x402AA: 16-bit Timer 6–7 Interrupt Cause Flag Register (pINT_F16T67) ........................... IV-2-77
0x402AB: 16-bit Timer 8–9 Interrupt Cause Flag Register (pINT_F16T89) ........................... IV-2-78
0x402AC: Port Input 8–15 IDMA Request Register (pIDMAREQ_RP815) ............................ IV-2-79
0x402AD: 16-bit Timer 6–9 IDMA Request Register (pIDMAREQ_R16T69) ......................... IV-2-80
0x402AE: Port Input 8–15 IDMA Enable Register (pIDMAEN_DEP815) ............................... IV-2-81
0x402AF: 16-bit Timer 6–9 IDMA Enable Register (pIDMAEN_DE16T69) ............................ IV-2-82
IV.2.8  Precautions .............................................................................................................. IV-2-83
IV.3  OSC3 Oscillator Circuit, PLL, and SSCG ............................................................. IV-3-1
IV.3.1  Overview of the System Clock Generator Unit .......................................................... IV-3-1
IV.3.2  OSC3 Oscillator Circuit ............................................................................................. IV-3-2
IV.3.2.1  Input/Output Pins of the OSC3 Oscillator Circuit ........................................ IV-3-2
IV.3.2.2  Structure of the Oscillator Circuit ................................................................ IV-3-2
IV.3.2.3  Oscillation Control  ...................................................................................... IV-3-2
IV.3.3  PLL ............................................................................................................................ IV-3-3
IV.3.3.1  Control of PLL ............................................................................................. IV-3-3
IV.3.3.2  Power Supply for PLL ................................................................................. IV-3-4
IV.3.4  SSCG ........................................................................................................................ IV-3-5
IV.3.5  Precautions ............................................................................................................... IV-3-6
IV.4  Prescaler (PSC) ...................................................................................................... IV-4-1
IV.4.1  Configuration of Prescaler ......................................................................................... IV-4-1
IV.4.2  Source Clock ............................................................................................................. IV-4-2
IV.4.3  Selecting Division Ratio and Output Control for Prescaler ............................................ IV-4-3

CONTENTS
xiv  EPSON  S1C33401 TECHNICAL MANUAL
IV.4.4  Source Clock Output to 8-Bit Timer ........................................................................... IV-4-4
IV.4.5  PSC_CLK External Output ........................................................................................ IV-4-5
IV.4.6  Details of Control Registers ...................................................................................... IV-4-6
0x40140: 8-bit Timer 4–5 Clock and Port Output Clock Select Register (pCLKSEL_T8_45) .. IV-4-7
0x40141–0x4014C: 16-bit Timer x Clock Control Registers (pCLKCTL_T16_x) ..................... IV-4-8
0x40145: 8-bit Timer 4–5 Clock Control Register (pCLKCTL_T8_45) ..................................... IV-4-9
0x40146: 8-bit Timer 0–3 Clock Select Register (pCLKSEL_T8) ........................................... IV-4-10
0x4014D: 8-bit Timer 0–1 Clock Control Register (pCLKCTL_T8_01) ................................... IV-4-11
0x4014E: 8-bit Timer 2–3 Clock Control Register (pCLKCTL_T8_23) ................................... IV-4-12
0x4014F: A/D Clock Control Register (pCLKCTL_AD) ........................................................... IV-4-13
IV.4.7  Precautions .............................................................................................................. IV-4-14
IV.5  8-Bit Timers (T8) ..................................................................................................... IV-5-1
IV.5.1  Configuration of 8-bit Timer ....................................................................................... IV-5-1
IV.5.2  Output Pins of 8-bit Timers ........................................................................................ IV-5-2
IV.5.3  Uses of 8-bit Timers .................................................................................................. IV-5-3
IV.5.4  8-bit Timer Operating Clock and Count Clock ........................................................... IV-5-5
IV.5.5  Control and Operation of 8-bit Timer ......................................................................... IV-5-6
IV.5.6  Control of Underflow Signal and Clock Outputs ........................................................ IV-5-8
IV.5.7  8-bit Timer Interrupts and DMA ................................................................................. IV-5-9
IV.5.8  Details of Control Registers ..................................................................................... IV-5-11
0x40160–0x40178: 8-bit Timer x Control Registers (pT8_CTLx) ........................................... IV-5-12
0x40161–0x40179: 8-bit Timer x Reload Data Registers (pT8_RLDx) .................................. IV-5-13
0x40162–0x4017A: 8-bit Timer x Counter Data Registers (pT8_PTDx) ................................. IV-5-14
IV.5.9  Precautions .............................................................................................................. IV-5-15
IV.6  16-Bit Timers (T16) ................................................................................................. IV-6-1
IV.6.1  Configuration of 16-bit Timer ..................................................................................... IV-6-1
IV.6.2  I/O Pins of 16-bit Timers ............................................................................................ IV-6-3
IV.6.3  Uses of 16-bit Timers ................................................................................................ IV-6-4
IV.6.4  16-bit Timer Operating Clock and Count Clock ......................................................... IV-6-5
IV.6.5  Control and Operation of 16-bit Timer ....................................................................... IV-6-6
IV.6.6  Controlling Clock Output .......................................................................................... IV-6-10
IV.6.7  16-bit Timer Interrupts and DMA .............................................................................. IV-6-13
IV.6.8  Details of Control Registers ..................................................................................... IV-6-16
0x48180–0x481C8: 16-bit Timer x Comparison Data A Setup Registers (pT16_CRxA) ........ IV-6-18
0x48182–0x481CA: 16-bit Timer x Comparison Data B Setup Registers (pT16_CRxB) ....... IV-6-19
0x48184–0x481CC: 16-bit Timer x Counter Data Registers (pT16_TCx) .............................. IV-6-20
0x48186–0x481CE: 16-bit Timer x Control Registers (pT16_CTLx) ...................................... IV-6-21
0x481D0–0x481D6: DA16 Ch.x Registers (pDA16_CRxA) .................................................... IV-6-23
0x481DC: Count Pause Register (pT16_CNT_PAUSE) ......................................................... IV-6-24
0x481DE: 16-bit Timer STD/ADV Mode Select Register (pT16_ADVMODE) ......................... IV-6-25
IV.6.9  Precautions .............................................................................................................. IV-6-26
IV.7  Watchdog Timer (WDT) .......................................................................................... IV-7-1
IV.7.1  Configuration of the Watchdog Timer  ....................................................................... IV-7-1
IV.7.2  Input/Output Pins of the Watchdog Timer  ................................................................. IV-7-2
IV.7.3  Operating Clock of the Watchdog Timer  ................................................................... IV-7-3
IV.7.4  Control of the Watchdog Timer .................................................................................. IV-7-4
IV.7.4.1  Setting Up the Watchdog Timer .................................................................. IV-7-4
IV.7.4.2  Starting/Stopping the Watchdog Timer  ...................................................... IV-7-5
IV.7.4.3  Resetting the Watchdog Timer  ................................................................... IV-7-5
IV.7.4.4  Operation in Standby Mode ........................................................................ IV-7-5
IV.7.4.5  Clock Output of the Watchdog Timer  ......................................................... IV-7-6

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  xv
IV.7.5  Control Register Details  ........................................................................................... IV-7-7
0x48160: Watchdog Timer Write-Protect Register (pWD_WP) ............................................... IV-7-8
0x48162: Watchdog Timer Enable Register (pWD_EN) .......................................................... IV-7-9
0x48164: Watchdog Timer Comparison Data Setup Register 0 (pWD_COMP_LOW) ........... IV-7-11
0x48166: Watchdog Timer Comparison Data Setup Register 1 (pWD_COMP_HIGH) .......... IV-7-11
0x48168: Watchdog Timer Count Register 0 (pWD_CNT_LOW) ........................................... IV-7-12
0x4816A: Watchdog Timer Count Register 1 (pWD_CNT_HIGH) .......................................... IV-7-12
0x4816C: Watchdog Timer Control Register (pWD_CNTL) .................................................... IV-7-13
IV.7.6  Precautions .............................................................................................................. IV-7-14
IV.8  Serial Interface (SIO) ............................................................................................. IV-8-1
IV.8.1  Configuration of Serial Interfaces .............................................................................. IV-8-1
IV.8.1.1  Features of Serial Interfaces ....................................................................... IV-8-1
IV.8.1.2  I/O Pins of Serial Interface .......................................................................... IV-8-2
IV.8.1.3  Setting Transfer Mode ................................................................................. IV-8-3
IV.8.1.4  Serial Interface Operating Clock ................................................................. IV-8-4
IV.8.1.5  Standard Mode and Advanced Mode ......................................................... IV-8-4
IV.8.2  Clock-Synchronized Interface ................................................................................... IV-8-5
IV.8.2.1  Outline of Clock-Synchronized Interface ..................................................... IV-8-5
IV.8.2.2  Setting Clock-Synchronized Interface ......................................................... IV-8-6
IV.8.2.3  Control and Operation of Clock-Synchronized Transfer .............................. IV-8-8
IV.8.3  Asynchronous Interface ............................................................................................ IV-8-15
IV.8.3.1  Outline of Asynchronous Interface ............................................................. IV-8-15
IV.8.3.2  Setting Asynchronous Interface ................................................................. IV-8-16
IV.8.3.3  Control and Operation of Asynchronous Transfer ...................................... IV-8-20
IV.8.4  IrDA Interface ........................................................................................................... IV-8-25
IV.8.4.1  Outline of IrDA Interface ............................................................................. IV-8-25
IV.8.4.2  Setting IrDA Interface ................................................................................. IV-8-25
IV.8.4.3  Control and Operation of IrDA Interface ..................................................... IV-8-27
IV.8.5  Serial Interface Interrupts and DMA ......................................................................... IV-8-28
IV.8.6  Details of Control Registers ..................................................................................... IV-8-31
0x401E0–0x401F5: Serial I/F Ch.x Transmit Data Registers (pFSIFx_TXD) ......................... IV-8-32
0x401E1–0x401F6: Serial I/F Ch.x Receive Data Registers (pFSIFx_RXD) ......................... IV-8-33
0x401E2–0x401F7: Serial I/F Ch.x Status Registers (pFSIFx_STATUS) ............................... IV-8-34
0x401E3–0x401F8: Serial I/F Ch.x Control Registers (pFSIFx_CTL) .................................... IV-8-36
0x401E4–0x401F9: Serial I/F Ch.x IrDA Registers (pFSIFx_IRDA) ....................................... IV-8-38
0x401FF: Serial I/F STD/ADV Mode Select Register (pFSIF_ADV) ....................................... IV-8-40
IV.8.7  Precautions .............................................................................................................. IV-8-41
IV.9  Card Interface (CARD) ........................................................................................... IV-9-1
IV.9.1  Overview of the Card Interface .................................................................................. IV-9-1
IV.9.2  Card Interface Pins .................................................................................................... IV-9-2
IV.9.3  Card Area .................................................................................................................. IV-9-3
IV.9.3.1  Selecting the Area ...................................................................................... IV-9-3
IV.9.3.2  Setting Area Access Conditions .................................................................. IV-9-3
IV.9.4  Card Interface Control Signals .................................................................................. IV-9-4
IV.9.4.1  SmartMedia Interface ................................................................................. IV-9-4
IV.9.4.2  CompactFlash Interface .............................................................................. IV-9-5
IV.9.4.3  PC Card Interface ....................................................................................... IV-9-5
IV.9.5  Card Interface Operating Clock ................................................................................. IV-9-7
IV.9.6  Details of Control Registers ...................................................................................... IV-9-8
0x40300: Card I/F Area Configuration Register (pCARDSETUP) ........................................... IV-9-8
0x40302: Card I/F Output Port Configuration Register (pCARDFUNCSEL05) ....................... IV-9-9
IV.9.7  Precautions .............................................................................................................. IV-9-10

CONTENTS
xvi  EPSON  S1C33401 TECHNICAL MANUAL
IV.10  General-Purpose I/O Ports (PORT) ................................................................... IV-10-1
IV.10.1  Structure of I/O Port ............................................................................................... IV-10-1
IV.10.2  Selecting the I/O Pin Functions .............................................................................. IV-10-1
IV.10.3  I/O Control Register and I/O Modes ....................................................................... IV-10-2
IV.10.4  Input Interrupt ......................................................................................................... IV-10-3
IV.10.4.1  Port Input Interrupt ................................................................................... IV-10-3
IV.10.4.2  Key Input Interrupt ................................................................................... IV-10-5
IV.10.4.3  Control Registers of the Interrupt Controller ............................................ IV-10-7
IV.10.5  I/O Port Operating Clock ........................................................................................ IV-10-9
IV.10.6  Details of Control Registers .................................................................................. IV-10-10
0x40340–0x40352: Px Port Data Registers (pPx_PxD) ........................................................ IV-10-11
0x4034E: P7 Port Data Register (pP7_P7D) ......................................................................... IV-10-12
0x40341–0x40353: Px I/O Control Registers (pPx_IOCx) .................................................... IV-10-13
0x40360–0x40373: Pxx Port Function Select Registers (pPx_xx_CFP) ............................... IV-10-14
0x40380: Port Input Interrupt Select Register 1 (pPINTSEL_SPT03) ................................... IV-10-15
0x40381: Port Input Interrupt Select Register 2 (pPINTSEL_SPT47) ................................... IV-10-15
0x40384: Port Input Interrupt Select Register 3 (pPINTSEL_SPT811) ................................. IV-10-15
0x40385: Port Input Interrupt Select Register 4 (pPINTSEL_SPT1215) ............................... IV-10-15
0x40382: Port Input Interrupt Polarity Select Register 1 (pPINTPOL_SPP07) ...................... IV-10-17
0x40386: Port Input Interrupt Polarity Select Register 2 (pPINTPOL_SPP815) .................... IV-10-17
0x40383: Port Input Interrupt Edge/Level Select Register 1 (pPINTEL_SEPT07) ................ IV-10-18
0x40387: Port Input Interrupt Edge/Level Select Register 2 (pPINTEL_SEPT815) .............. IV-10-18
0x40390: Key Input Interrupt Select Register (pKINTSEL_SPPK01) .................................... IV-10-19
0x40392: Key Input Interrupt (FPK0) Input Comparison Register (pKINTCOMP_SCPK0) ... IV-10-20
0x40393: Key Input Interrupt (FPK1) Input Comparison Register (pKINTCOMP_SCPK1) ... IV-10-20
0x40394: Key Input Interrupt (FPK0) Input Mask Register (pKINTCOMP_SMPK0) ............. IV-10-21
0x40395: Key Input Interrupt (FPK1) Input Mask Register (pKINTCOMP_SMPK1) ............. IV-10-21
IV.10.7  Precautions ........................................................................................................... IV-10-22
IV.11  A/D Converter (ADC) .......................................................................................... IV-11-1
IV.11.1  Features and Structure of A/D Converter ............................................................... IV-11-1
IV.11.2  I/O Pins of A/D Converter ....................................................................................... IV-11-2
IV.11.3  A/D Converter Operating Clock and Conversion Clock .......................................... IV-11-3
IV.11.4  Setting A/D Converter ............................................................................................ IV-11-4
IV.11.5  Control and Operation of A/D Conversion .............................................................. IV-11-9
IV.11.6  A/D Converter Interrupt and DMA ......................................................................... IV-11-13
IV.11.7  Details of Control Registers .................................................................................. IV-11-15
0x48140: A/D Conversion Result Register (pAD_ADD) ........................................................ IV-11-16
0x48142: A/D Trigger/Channel Select Register (pAD_TRIG_CHNL) .................................... IV-11-17
0x48144: A/D Control/Status Register (pAD_EN_SMPL_STAT) ........................................... IV-11-19
0x48146: A/D Channel Status Flag Register (pAD_END) ..................................................... IV-11-22
0x48148–0x48156: A/D Ch.x Conversion Result Buffer Registers (pAD_CHx_BUF) ........... IV-11-23
0x48158: A/D Upper Limit Value Register (pAD_UPPER) ..................................................... IV-11-24
0x4815A: A/D Lower Limit Value Register (pAD_LOWER) .................................................... IV-11-25
0x4815C: A/D Conversion Complete Interrupt Mask Register (pAD_CH07_INTMASK) ....... IV-11-26
0x4815E: A/D Converter Mode Select/Internal Status Register (pAD_ADVMODE) .............. IV-11-27
IV.11.8  Precautions ........................................................................................................... IV-11-28

CONTENTS
S1C33401 TECHNICAL MANUAL  EPSON  xvii
V  S1C33401 AREA 6 EXTENDED PERIPHERAL BLOCK
V.1  Preface ...................................................................................................................... V-1-1
V.2  Area 6 Settings and Macro Control Register ........................................................ V-2-1
V.2.1  Setting Up the CE6 Area with BBCU Registers ..........................................................V-2-1
V.2.2  Clock Control ...............................................................................................................V-2-2
V.2.3  Setting Wait Cycles for Accessing the RTC .................................................................V-2-3
V.2.4  Control Register Details ..............................................................................................V-2-4
0x300F20: Macro Control Register (pMISC3) ..........................................................................V-2-4
V.3  Chip ID ...................................................................................................................... V-3-1
V.3.1  Chip ID Bits .................................................................................................................V-3-1
V.3.2  Details of Control Register ..........................................................................................V-3-2
0x300000: Device ID Register (pMISC0) ..................................................................................V-3-2
V.4  Pin Control Registers ..............................................................................................V-4-1
V.4.1  Pull-up Control ............................................................................................................V-4-1
V.4.2  Driving Bus Signals Low .............................................................................................V-4-1
V.4.3  Details of Control Registers ........................................................................................V-4-2
0x300F00: Bus Signal Low Drive/Pull-up Control Register (pMISC1) ......................................V-4-3
0x300F04: Port Pull-up Control Register (pMISC2) ..................................................................V-4-5
V.4.4  Precautions .................................................................................................................V-4-7
V.5  Real-Time Clock (RTC) ............................................................................................V-5-1
V.5.1  Overview of the RTC ...................................................................................................V-5-1
V.5.2  RTC Counters .............................................................................................................V-5-2
V.5.3  Control of the RTC ......................................................................................................V-5-5
V.5.3.1  Controlling the Operating Clock ....................................................................V-5-5
V.5.3.2  Initial Sequence of the RTC ..........................................................................V-5-5
V.5.3.3  Selecting 12/24-hour Mode and Setting the Counters ..................................V-5-6
V.5.3.4  Starting, Stopping, and Resetting Counters .................................................V-5-6
V.5.3.5  Counter Hold and Busy Flag .........................................................................V-5-7
V.5.3.6  Reading from and Writing to Counters in Operation .....................................V-5-8
V.5.3.7  30-second Correction ....................................................................................V-5-8
V.5.4  RTC Interrupts .............................................................................................................V-5-9
V.5.5  Standby Mode (#STBY pin) and Power Supply of the RTC .......................................V-5-10
V.5.6  OSC1 Oscillator Circuit ..............................................................................................V-5-11
V.5.6.1  Input/Output Pins of the OSC1 Oscillator Circuit ......................................... V-5-11
V.5.6.2  Structure of the OSC1 Oscillator Circuit ......................................................V-5-11
V.5.6.3  Oscillation Control  .......................................................................................V-5-12
V.5.7  Details of Control Registers .......................................................................................V-5-13
0x301000: RTC Interrupt Status Register (pRTCINTSTAT) .....................................................V-5-14
0x301004: RTC Interrupt Mode Register (pRTCINTMODE) ...................................................V-5-15
0x301008: RTC Control Register (pRTC_CNTL0) ..................................................................V-5-16
0x30100C: RTC Access Control Register (pRTC_CNTL1) .....................................................V-5-18
0x301010: RTC Second Register (pRTCSEC) ........................................................................V-5-19
0x301014: RTC Minute Register (pRTCMIN) ..........................................................................V-5-20
0x301018: RTC Hour Register (pRTCHOUR) .........................................................................V-5-21
0x30101C: RTC Day Register (pRTCDAY) ..............................................................................V-5-22
0x301020: RTC Month Register (pRTCMONTH) ....................................................................V-5-23
0x301024: RTC Year Register (pRTCYEAR) ...........................................................................V-5-24
0x301028: RTC Days of Week Register (pRTCDAYWEEK) ....................................................V-5-25
V.5.8  Precautions ................................................................................................................V-5-26

CONTENTS
xviii  EPSON  S1C33401 TECHNICAL MANUAL
APPENDIX
I/O Map ............................................................................................................................APP-1
0x40140–0x4014F  Prescaler ...........................................................................APP-2
0x40160–0x4017A 8-bit Timer .........................................................................APP-6
0x40180–0x40188  Clock Management Unit (1) ..............................................APP-8
0x401E0–0x401FF  Serial Interface ..................................................................APP-9
0x40260–0x402AF  Interrupt Controller ...........................................................APP-13
0x402E8–0x402EC  Debug Unit .......................................................................APP-22
0x40300–0x40302  Card Interface ...................................................................APP-23
0x40340–0x40395  I/O Ports ...........................................................................APP-24
0x48140–0x4815E  A/D Converter ..................................................................APP-35
0x48160–0x4816C  Watchdog Timer ...............................................................APP-38
0x48180–0x481DE 16-bit Timer ......................................................................APP-40
0x48200–0x48205 Intelligent DMA ................................................................. APP-52
0x48220–0x4829C  High-Speed DMA .............................................................APP-53
0x48300–0x48314  High-Speed Bus Control Unit ...........................................APP-66
0x48320–0x48334  Memory Management Unit ............................................... APP-68
0x48340–0x48352  Cache Control Unit ........................................................... APP-71
0x48360–0x48372  Clock Management Unit (2) .............................................APP-73
0x48380–0x483A6  Basic Bus Control Unit .....................................................APP-75
0x483C0–0x483CC  Extended Bus Control Unit ...............................................APP-84
0x300000–0x300F20  Chip ID/Pin Status Control ...............................................APP-86
0x301000–0x301028  Real Time Clock ............................................................... APP-87

S1C33401 Technical Manual

I S1C33401 SPECIFICATIONS

I S1C33401 SPECIFICATIONS: OVERVIEW

S1C33401 TECHNICAL MANUAL EPSON I-1-1

Overview

I.1 Overview

The S1C33401 is a 32-bit RISC-type microcomputer originally developed for embedded applications by Seiko

Epson.

The S1C33401 is built around the C33 ADV core block that includes the CPU, MMU, cache, and modules that

allow various external memory and I/O devices to be connected directly, and incorporates a bus block that includes

the DMA controller and other control units. In addition to these primary units, the S1C33401 incorporates a basic

peripheral circuit block that includes an interrupt controller, timers, serial interfaces, card interfaces, input/output

ports, and A/D converter, and an extended peripheral circuit block that includes a chip ID register, RTC, and other

components.

The S1C33401 is manufactured by a 0.18 µm fine-pattern CMOS process, backed by sophisticated clock control

functions, and can operate at higher speed with less power than ever before. In addition to its use as an embedded-

type processor in various portable systems, the S1C33401 features a built-in C33 ADV CPU to provide enhanced

functionality for multimedia support while retaining upward compatibility with the conventional C33 STD CPU,

making it an ideal solution to the requirements of mobile multimedia applications.

Table I.1.1 Product Line

Model

S1C33401F00A∗∗∗

S1C33401B00A∗∗∗

Package

QFP20-184pin

PFBGA-160pin

The main functions and features of the S1C33401 are outlined below.

Core

CPU

• Original Seiko Epson 32-bit RISC-type CPU – C33 ADV

• Internal 32-bit data processing

• 4GB address space

• Powerful instruction set

- Code length: 16 bits per instruction

- Number of instructions: 164

- Main instructions executable in 1 cycle (including immediate-extended instructions, each consisting of two

to three instructions)

- 15.15 ns per instruction (when operating at 66 MHz, max.)

• Multimedia support functions

- Built-in 32-bit × 16-bit multiplier

- 16 × 16, 32 × 16 and 32 × 32-bit multiplication

- 16 × 16, 32 × 16 and 32 × 32-bit multiply-accumulate operations

- Repeated execution by loop and repeat instructions

- Rounding to minimum/maximum values by saturation instruction

- ALU instruction execution with post-shift

High-speed Bus Control Unit (HBCU)

• Controls memory access by the CPU by dividing 4GB logical space into eight 512MB blocks.

• Manages MMU, CCU, and ASID processing in each block.

• Capable of multiplexing logical space using ASID and mirroring physical space.

• Can simultaneously process A0RAM data read/write operations and instruction fetching from cache.

I S1C33401 SPECIFICATIONS: OVERVIEW

I-1-2 EPSON S1C33401 TECHNICAL MANUAL

Memory Management Unit (MMU)

• Converts logical space into physical space in page units (4KB or 64KB per page).

• Supports 16 entries per way for a total of 64 entries, due to 4-way set associative method.

• Can protect memory for each page.

• Allows optional selection of using cache for each page.

• Supports five causes of MMU exception.

Cache Control Unit (CCU)

• Physical address-based instruction/data coexisting type of cache

• Contains 8KB cache.

• Supports 128 entries per way for a total of 512 lines, due to 4-way set associative method (4 words per line).

• Allows selection of write-through or write-back mode for writing to cache.

• Can lock a specified way and interrupt handler routine.

• Forwarding function to allow immediate instruction/data transfer even during refill.

Clock Management Unit (CMU)

• Controls reset and NMI input.

• System clock control

- Selects clock source, turns clock on/off, and divides operating clock.

- Controls clock according to standby mode (SLEEP, HALT, or HALT2).

• Controls clock supply for each module (manual/auto).

Debug Unit (DBG)

• Supports on-chip trace/break and other debugging functions at the chip level.

• Provides an advanced debugging environment in conjunction with the ICD (in-circuit debugger) and

debugger.

Internal Memory

High-speed RAM incorporated in Area 0 (A0RAM)

• 32KB

• High-speed access with zero wait state

RAM incorporated in Area 3 (A3RAM)

• 1KB

• Access with one wait state

• Also usable as IDMA control information table

Bus Control Units and DMA Controller

Basic Bus Control Unit (BBCU)

• Controls external address space by dividing it into 19 areas (Areas 4 to 22).

• Allows selection of external/internal access, endian mode, interface mode, device type, device size, and

number of access cycles for each area.

• Outputs 8 chip-enable signals (#CE4–#CE11) corresponding to each external area.

• Supports two interface modes: A0 and BSL (with BSL mode for external memory only).

• Allows direct connection of SRAM, ROM, burst ROM, or flash memory to external bus.

• Allows insertion of wait state from external #WAIT pin (for SRAM type only).

• Arbitrates bus contention with external bus masters.

Extended Bus Control Unit (EBCU)

• Allows direct connection of SDRAM (in one of Areas 4 to 22 selected).

• Data bus width: 16 bits

• Bank address: Up to four banks accommodated.

• Burst length: Fixed to 1 (with burst read/write executed by issuing successive commands).

• CAS latency: 1, 2, or 3

• Write mode: Single write

I S1C33401 SPECIFICATIONS: OVERVIEW

S1C33401 TECHNICAL MANUAL EPSON I-1-3

Overview

• Supports self-refresh and auto-refresh.

• Programmable refresh cycle

• Allows selection of bank active mode (with or without auto-precharge).

High-speed DMA Controller (HSDMA)

• Up to four channels

• Capable of high-speed DMA transfer because of no need to read/write transfer conditions, etc. from/to

memory.

• Supports dual-address and single-address transfers.

• Activated by DMA request input, interrupt cause, or software trigger.

• Can generate interrupt upon completion of transfer.

Intelligent DMA Controller (IDMA)

• Up to 128 channels

• Supports dual-address transfers.

• Programmable DMA transfer control information in RAM (except A0RAM)

• Activated by a specific interrupt cause or software trigger.

• Can be linked from one IDMA channel to another.

• Can generate an interrupt upon completion of transfer.

Internal Peripheral Circuits

OSC3 Oscillator Circuit

• Generates the main system clock.

• Crystal/ceramic oscillator: 5 MHz (min.) to 33 MHz (max.)

• External clock input: 2 MHz (min.) to 33 MHz (max.)

PLL

• Allows selection of whether to use x1 to x16 OSC3 oscillation frequency.

• PLL input frequency: 5 MHz (min.) to 33 MHz (max.)

• PLL output frequency: 20 MHz (min.) to 66 MHz (max.)

SSCG (Spread Spectrum Clock Generator)

• SS-modulation circuit for system source clock (OSC3, PLL, or OSC1) to reduce Electromagnetic

Interference (EMI) noise

Interrupt Controller (ITC)

• Branches to interrupt handling routine via interrupt vector table.

• Can activate intelligent DMA.

• Handles 9 exceptions:

- Reset exception (1)

- Divide by zero exception (1)

- Address misaligned exception (1)

- NMI (1)

- Software exceptions (4)

- MMU exception (1)

• Handles 64 maskable interrupts:

- Port/key input interrupts (18)

- DMA controller interrupts (5)

- 16-bit timer interrupts (20)

- 8-bit timer interrupts (6)

- Serial interface interrupts (12)

- A/D converter interrupts (2)

- RTC interrupt (1)

I S1C33401 SPECIFICATIONS: OVERVIEW

I-1-4 EPSON S1C33401 TECHNICAL MANUAL

Prescaler (PSC)

• Programmable 8-bit and 16-bit timers, and A/D converter clock settings

8-bit Timer (T8)

• 6-channel, 8-bit programmable timers

• Can generate an interrupt upon underflow.

• Can output the clock generated by underflow to external devices.

• Generates serial interface clock as programmed.

• Can output a trigger to A/D converter at specified intervals.

16-bit Timer (T16)

• 10-channel, 16-bit programmable timers

• Can be used as PWM timer.

• Supports DA16 mode.

• Can generate two interrupts per channel upon underflow or when matching compared value.

• Can output clock generated by underflow or when matching compared value to external devices.

Watchdog Timer (WDT)

• 30-bit watchdog timer capable of generating NMI

• Programmable setting of NMI generation cycle

Serial Interface (SIO)

• 4 channels

• Contains 4-byte receive data buffer (FIFO) and 2-byte transmit data buffer (FIFO) for each channel.

• Supports full-duplex communication.

• Selectable between 8-bit clock-synchronous and 8-bit or 7-bit asynchronous modes.

• Supports IrDA 1.0 interface.

• Can generate transmit buffer empty, receive buffer full, and receive error interrupts.

Card Interface (CARD)

• Supports SmartMedia card (NAND flash).

• Supports CompactFlash card.

• Supports PC card (2 channels).

I/O Ports (PORT)

• Up to 71 ports

• Can be used as general-purpose I/O pins when not used for peripheral functions.

• Programmable port input and key input interrupts

A/D Converter (ADC)

• 4-channel, 10-bit A/D converters

• Can generate an interrupt upon completion of conversion.

• Can generate an interrupt when converted value is outside specified upper and lower limits.

RTC

• Contains BCD time (second, minute, and hour) counters and calendar (day, days of the week, month, and

year) counters.

• Allows selection between 24-hour and 12-hour modes.

• Equipped with function for 30-second correction in software.

• Can periodically generate interrupts (at intervals of 1/64 or 1 second, 1 minute, or 1 hour).

• Powered independently of other modules, and can operate even when system power is turned off.

• Contains an OSC1 oscillator circuit to generate 32.768 kHz (typ.) clock.

I S1C33401 SPECIFICATIONS: OVERVIEW

S1C33401 TECHNICAL MANUAL EPSON I-1-5

Overview

Operating Conditions and Current Consumption

Power Supply Voltage

• Core power supply voltages (VDD, PLLVDD, RTCVDD): 1.65 V to 1.95 V (1.8 V ± 0.15 V)

• I/O power supply voltages (VDDE, TMVDD, AVDD): 2.70 V to 3.60 V (3.0/3.3 V ± 0.3 V)

Input Voltage

• High-level input voltage: 2.20 V (min.) to VDDE (max.)

• Low-level input voltage: VSS (min.) to 0.80 V (max.)

Operating Clock Frequency

• CPU: 66 MHz (max.)

• Bus (BBCU, EBCU): 66 MHz (max.)

Operating Temperature

-40°C to 85°C

Power Consumption

• In SLEEP mode: 25 µW (typ.)

• In HALT mode: 36 mW (typ., 66 MHz)

• During operation: 65 mW (typ., 66 MHz, cache off)

Form of Shipment

• PFBGA 160-pin plastic package (10 mm × 10 mm × 1.2 mm, 0.65 mm pitch)

• QFP20 184-pin plastic package (20 mm × 20 mm × 1.7 mm, 0.40 mm pitch)

I S1C33401 SPECIFICATIONS: OVERVIEW

I-1-6 EPSON S1C33401 TECHNICAL MANUAL

THIS PAGE IS BLANK.

I S1C33401 SPECIFICATIONS: BLOCK DIAGRAM

S1C33401 TECHNICAL MANUAL EPSON I-2-1

Block

I.2 Block Diagram

C33 ADV CPU

HBCU

OSC3/PLL

Interrupt controller

(ITC)

CCU

MMU

CMU

DBG

EBCU

(SDRAM Controller)

DMA

A3RAM

(Area 3 RAM)

BBCU

(SRAM Controller)

Bridge

A0RAM

(Area 0 No-Wait RAM)

Prescaler

(PSC)

8-bit Timer

(T8)

16-bit Timer/PWM

(T16)

Watchdog Timer

(WDT)

Serial Interface

(SIO)

Card Interface

(CARD)

I/O Ports

(PORT)

A/D Converter

(ADC)

Real Time Clock

(RTC)

Chip ID, Pin control

and Misc. registers

C33 ADV Core Block

S1C33401

Bus Control BlockStandard Peripheral Block

High-speed bus

Extended Peripheral Block

(Area 6)

(Area 1)

Figure I.2.1 S1C33401 Block Diagram

I S1C33401 SPECIFICATIONS: BLOCK DIAGRAM

I-2-2 EPSON S1C33401 TECHNICAL MANUAL

THIS PAGE IS BLANK.

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-1

I.3 Pin Description

I.3.1 Pin Arrangement

The S1C33401 comes in a QFP20-184pin or PFBGA-160pin plastic package.

I.3.1.1 QFP Package Pin Arrangement (S1C33401F00A)

#CE11(P56)

#CE9(P55)

#CE10

P27(DQMH/#SRDY3)

P26(DQML/#SCLK3)

P21(SDCLK/SOUT2)

P25(#SDWE/SOUT3)

DDE

P24(#SDCAS/SIN3)

P23(#SDRAS/#SRDY2)

P22(#SDCS/#SCLK2)

P20(SDCKE/SIN2)

D15

D14

D13

DDE

N.C.

D12

D11

N.C.

D10

DDE

#BSL

#WRH

#WRL

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

P95(SOUT3/ASTB/DTD5)

P96(#SCLK3/CARD4/DTD6)

P97(#SRDY3/CARD5/DTD7)

DDE

P82(#DMAEND2/EXCL5/DBT)

P83(#DMAEND3/EXCL6/DTS0)

P84(PSC_CLK/CARD2/DTS1)

P85(CMU_CLK/CARD3/DTS2)

P86(TM8/CARD0/DTS3)

P87(TM9/CARD1/DTS4)

P80(#DMAACK2/T8UF3/EXCL3)

P81(#DMAACK3/T8UF4/EXCL4)

DDE

N.C.

P30(#DMAREQ0/T8UF0/EXCL0)

P31(#DMAREQ1/T8UF1/EXCL1)

P32(#DMAREQ2/CARD2/EXCL2)

P33(#DMAREQ3/CARD3/WDT_CLK)

P60(#BUSREQ/CARD4)

P61(#BUSACK/CARD5)

N.C.

P62(#BUSGET/T8UF2/#ADTRG)

CMU_CLK(P63/BCLK/T8UF5)

DDE

#CE4(P50/CARD0)

#CE5(P51)

#CE6(P52)

#CE7(P53/CARD1)

#CE8(P54)

P64(#WAIT)

TMV

P10(TM0)

P11(TM1)

P12(TM2)

P13(TM3)

P14(TM4/#DMAEND0)

P15(TM5/#DMAEND1)

P16(TM6/#DMAACK0)

P17(TM7/#DMAACK1)

RTCV

#STBY

OSC1

OSC2

PLLV

VCP

PLLV

BURNIN

SCANEN

OSC3

OSC4

TST0

TST1

DDE

#RESET

#NMI

P00(SIN0)

P01(SOUT0)

P02(#SCLK0)

N.C.

P03(#SRDY0)

P04(SIN1)

N.C.

P05(SOUT1)

P06(#SCLK1)

P07(#SRDY1)

DSIO

DST0(P65)

DST1(P66)

DST2

DPCO(P67)

DCLK

DDE

N.C.

P90(SIN2/EXCL7/DTD0)

P91(SOUT2/EXCL8/DTD1)

P92(#SCLK2/EXCL9/DTD2)

P93(#SRDY2/R

W/DTD3)

P94(SIN3/ACST/DTD4)

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

#RD

DDE

A10

N.C.

DDE

N.C.

A11

N.C.

A12

A13

A14

A15

A16

A17

A18(P47)

DDE

A19(P46)

A20(P45)

A21(P44)

A22(P43)

A23(P42)

A24(P41)

A25(P40)

P73(AIN3)

P72(AIN2)

P71(AIN1)

P70(AIN0)

Figure I.3.1.1.1 Pin Arrangement (QFP20-184pin)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-2 EPSON S1C33401 TECHNICAL MANUAL

I.3.1.2 PFBGA Package Pin Arrangement (S1C33401B00A)

Top View Bottom View

A1 Corner

Index

A B C D E F G H J K L M N P P N M L K J H G F E D C B A

N.C.

P95

SOUT3

ASTB

DTD5

P97

#SRDY3

CARD5

DTD7

P84

PSC_CLK

CARD2

DTS1

P86

TM8

CARD0

DTS3

P81

#DMAACK3

T8UF4

EXCL4

P32

#DMAREQ2

CARD2

EXCL2

CMU_CLK

P63

BCLK

T8UF5

#CE6

P52

P64

#WAIT

P14

TM4

#DMAEND0

P11

TM1

P70

AIN0

N.C.

P92

#SCLK2

EXCL9

DTD2

P93

#SRDY2

R/W

DTD3

P96

#SCLK3

CARD4

DTD6

P83

#DMAEND3

EXCL6

DTS0

P30

#DMAREQ0

T8UF0

EXCL0

P61

#BUSACK

CARD5

P62

#BUSGET

T8UF2

#ADTRG

#CE5

P51

P12

TM2

P16

TM6

#DMAACK0

P71

AIN1

P72

AIN2

P90

SIN2

EXCL7

DTD0

P91

SOUT2

EXCL8

DTD1

P82

#DMAEND2

EXCL5

DBT

P85

CMU_CLK

CARD3

DTS2

P87

TM9

CARD1

DTS4

P31

#DMAREQ1

T8UF1

EXCL1

P60

#BUSREQ

CARD4

#CE7

P53

CARD1

P13

TM3

P17

TM7

#DMAACK1

P73

AIN3

DCLK

P67

DPCO

P94

SIN3

ACST

DTD4

P80

#DMAACK2

T8UF3

EXCL3

P33

#DMAREQ3

CARD3

WDT_CLK

#CE4

P50

CARD0

#CE8

P54

P10

TM0

P15

TM5

#DMAEND1

A25

P40

A24

P41

P66

DST1

P65

DST0

DSIO

DST2

VDD

TMV

A23

P42

A22

P43

A20

P45

P06

#SCLK1

P05

SOUT1

P07

#SRDY1

A21

P44

A19

P46

A18

P47

P03

#SRDY0

VDD

P04

SIN1

P02

#SCLK0

A16

A14

A17

A15

P00

SIN0

#NMI

P01

SOUT0

#RESET

A11

A13

A12

OSC4

TST1

TST0

A10

OSC3

SCANEN

BURNIN

#CE11

P56

VDD RTCV

PLLVDD

VCP

#CE9

P55

VDD

P22

#SDCS

#SCLK2

#WRL

OSC2

P26

DQML

#SCLK3

P25

#SDWE

SOUT3

P23

#SDRAS

#SRDY2

D13

D11

VDD

#WRH

OSC1

#STBY

#CE10

PLLVSS

P24

#SDCAS

SIN3

D15

D14

D12

D10

#BSL

N.C.

P27

DQMH

#SRDY3

P21

SDCLK

SOUT2

VDDE

AVDD

VDDE

P20

SDCKE

SIN2

VDD

#RD

N.C.

2345678

Top View

9 10 11 12 13 14

VSS

Figure I.3.1.2.1 Pin Arrangement (PFBGA-160pin)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-3

I.3.2 Pin Functions

Tables I.3.2.1 to I.3.2.5 list the function of each pin on the S1C33401.

Table I.3.2.1 Power Supply Pin List

Function

Power supply (+) for the internal logic circuits (1.65 V to 1.95 V)

Power supply (–); GND

Power supply (+) for the PLL (PLLVDD = VDD)

Power supply (–) for the PLL (PLLVSS = VSS)

Power supply (+) for the RTC (RTCVDD = VDD)

Power supply (+) for the I/O block (2.7 V to 3.6 V)

Power supply (+) for PWM timer outputs (P1x port) (TMVDD = VDDE)

Power supply (+) for the analog system and AIN0–AIN3 (AVDD = VDDE)

QFP

9,25,40,57,71,82,101,

117,130,146,160,173

12,23,35,52,63,73,84,91,98,

105,113,123,132,138,151,

165,175,184

143

145

139

4,15,29,61,75,87,97,107,

119,128,154,177

Pin No.

Pin name

VDD

VSS

PLLVDD

PLLVSS

RTCVDD

VDDE

TMVDD

AVDD

PFBGA

B7,B11,E4,F11,G14,

L5,L12

A11,B14,C3,D6,D13,E2,

H14,K3,K11,L8,M10,N13

C12

D11

B12

D4,D9,E14,H4,H11,M6,N11

Table I.3.2.2 External Bus Pin List

I/O

Pull-up

∗2

∗1

Function

Data bus (D15–D0)

Bus strobe (low byte) signal in BSL mode

Read signal

Write (low byte) signal in A0 mode or write signal in BSL mode

Write (high byte) signal in A0 mode or Bus strobe (high byte) signal in BSL mode

Address bus (A17–A0)

A18: Address bus (A18) (default)

P47: General-purpose I/O port

A19: Address bus (A19) (default)

P46: General-purpose I/O port

A20: Address bus (A20) (default)

P45: General-purpose I/O port

A21: Address bus (A21) (default)

P44: General-purpose I/O port

A22: Address bus (A22) (default)

P43: General-purpose I/O port

A23: Address bus (A23) (default)

P42: General-purpose I/O port

A24: Address bus (A24) (default)

P41: General-purpose I/O port

A25: Address bus (A25) (default)

P40: General-purpose I/O port

#CE11: Chip enable signal for areas 11 and 12 (default)

P56: General-purpose I/O port

Chip enable signal for areas 10, 13 and 20

#CE9: Chip enable signal for areas 9 and 22 (default)

P55: General-purpose I/O port

#CE8: Chip enable signal for areas 8 and 21 (default)

P54: General-purpose I/O port

QFP

122–120,

115,114,

111–108,

106,

104–102,

100,99,

64–69,

72,

77–81,

83,85,

86,

88–90

137

135

136

Pin No.

Pin name

D[15:0]

#BSL

#RD

#WRL

#WRH

A[17:0]

A18

P47

A19

P46

A20

P45

A21

P44

A22

P43

A23

P42

A24

P41

A25

P40

#CE11

P56

#CE10

#CE9

P55

#CE8

P54

PFBGA

F13,G13,

G12,H13,

H12,J13,

J11,J12,

J14,K13,

K14,K12,

L11,L13,

L14,M14

M13

N14

M11

M12

N7,L7,

P7,M7,

N8,P8,

M8,P9,

M9,N9,

P10,L9,

N10,L10,

P11,P12,

N12,P13

D10

C13

E11

Module

BBCU

EBCU

BBCU

EBCU

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

BBCU

PORT

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-4 EPSON S1C33401 TECHNICAL MANUAL

I/O

Pull-up

∗1

Function

#CE7: Chip enable signal for areas 7 and 19 (default)

P53: General-purpose I/O port

CARD1:Card I/F signal 1 output (#SMWR or #CFCE2)

#CE6: Chip enable signal for areas 6, 17 and 18 (default)

P52: General-purpose I/O port

#CE5: Chip enable signal for areas 5, 15 and 16 (default)

P51: General-purpose I/O port

#CE4: Chip enable signal for areas 4 and 14 (default)

P50: General-purpose I/O port

CARD0:Card I/F signal 0 output (#SMRD or #CFCE1)

QFP

Pin No.

Pin name

#CE7

P53

CARD1

#CE6

P52

#CE5

P51

#CE4

P50

CARD0

PFBGA

Module

BBCU

PORT

CARD

BBCU

PORT

BBCU

PORT

BBCU

PORT

CARD

Table I.3.2.3 Input/Output Port and Peripheral Circuit Pin List

I/O

Pull-up

∗1

Function

P00: General-purpose I/O port (default)

SIN0: Serial I/F Ch.0 data input

P01: General-purpose I/O port (default)

SOUT0: Serial I/F Ch.0 data output

P02: General-purpose I/O port (default)

#SCLK0: Serial I/F Ch.0 clock input/output

P03: General-purpose I/O port (default)

#SRDY0: Serial I/F Ch.0 ready signal input/output

P04: General-purpose I/O port (default)

SIN1: Serial I/F Ch.1 data input

P05: General-purpose I/O port (default)

SOUT1: Serial I/F Ch.1 data output

P06: General-purpose I/O port (default)

#SCLK1: Serial I/F Ch.1 clock input/output

P07: General-purpose I/O port (default)

#SRDY1: Serial I/F Ch.1 ready signal input/output

P10: General-purpose I/O port (default)

TM0: 16-bit timer 0 output

P11: General-purpose I/O port (default)

TM1: 16-bit timer 1 output

P12: General-purpose I/O port (default)

TM2: 16-bit timer 2 output

P13: General-purpose I/O port (default)

TM3: 16-bit timer 3 output

P14: General-purpose I/O port (default)

TM4: 16-bit timer 4 output

#DMAEND0: HSDMA Ch.0 end-of-transfer signal output

P15: General-purpose I/O port (default)

TM5: 16-bit timer 5 output

#DMAEND1: HSDMA Ch.1 end-of-transfer signal output

P16: General-purpose I/O port (default)

TM6: 16-bit timer 6 output

#DMAACK0: HSDMA Ch.0 acknowledge signal output

P17: General-purpose I/O port (default)

TM7: 16-bit timer 7 output

#DMAACK1: HSDMA Ch.1 acknowledge signal output

P20: General-purpose I/O port (default)

SDCKE: SDRAM clock enable signal output

SIN2: Serial I/F Ch.2 data input

P21: General-purpose I/O port (default)

SDCLK: SDRAM clock output

SOUT2: Serial I/F Ch.2 data output

P22: General-purpose I/O port (default)

#SDCS: SDRAM chip enable signal output

#SCLK2: Serial I/F Ch.2 clock input/output

P23: General-purpose I/O port (default)

#SDRAS: SDRAM row address strobe signal output

#SRDY2: Serial I/F Ch.2 ready signal input/output

P24: General-purpose I/O port (default)

#SDCAS: SDRAM column address strobe signal output

SIN3: Serial I/F Ch.3 data input

QFP

157

158

159

162

163

166

167

168

124

131

125

126

127

Pin No.

Pin name

P00

SIN0

P01

SOUT0

P02

#SCLK0

P03

#SRDY0

P04

SIN1

P05

SOUT1

P06

#SCLK1

P07

#SRDY1

P10

TM0

P11

TM1

P12

TM2

P13

TM3

P14

TM4

#DMAEND0

P15

TM5

#DMAEND1

P16

TM6

#DMAACK0

P17

TM7

#DMAACK1

P20

SDCKE

SIN2

P21

SDCLK

SOUT2

P22

#SDCS

#SCLK2

P23

#SDRAS

#SRDY2

P24

#SDCAS

SIN3

PFBGA

F14

D14

G11

F12

E13

Module

PORT

SIO

PORT

SIO

PORT

SIO

PORT

SIO

PORT

SIO

PORT

SIO

PORT

SIO

PORT

SIO

PORT

T16

PORT

T16

PORT

T16

PORT

T16

PORT

T16

HSDMA

PORT

T16

HSDMA

PORT

T16

HSDMA

PORT

T16

HSDMA

PORT

EBCU

SIO

PORT

EBCU

SIO

PORT

EBCU

SIO

PORT

EBCU

SIO

PORT

EBCU

SIO

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-5

I/O

Pull-up

∗1

Function

P25: General-purpose I/O port (default)

#SDWE: SDRAM write signal output

SOUT3: Serial I/F Ch.3 data output

P26: General-purpose I/O port (default)

DQML: SDRAM data (low byte) input/output mask signal output

#SCLK3: Serial I/F Ch.3 clock input/output

P27: General-purpose I/O port (default)

DQMH: SDRAM data (high byte) input/output mask signal output

#SRDY3: Serial I/F Ch.3 ready signal input/output

P30: General-purpose I/O port (default)

#DMAREQ0:HSDMA Ch.0 request input

T8UF0: 8-bit timer 0 output

EXCL0: 16-bit timer 0 event counter input

P31: General-purpose I/O port (default)

#DMAREQ1:HSDMA Ch.1 request input

T8UF1: 8-bit timer 1 output

EXCL1: 16-bit timer 1 event counter input

P32: General-purpose I/O port (default)

#DMAREQ2:HSDMA Ch.2 request input

CARD2: Card I/F signal 2 output (#IORD or #SMRD)

EXCL2: 16-bit timer 2 event counter input

P33: General-purpose I/O port (default)

#DMAREQ3:HSDMA Ch.3 request input

CARD3: Card I/F signal 3 output (#IOWR or #SMWR)

WDT_CLK: Watchdog timer output

P60: General-purpose I/O port (default)

#BUSREQ: Bus release request input

CARD4: Card I/F signal 4 output (#OE or #CFCE1)

P61: General-purpose I/O port (default)

#BUSACK: Bus acknowledge output

CARD5: Card I/F signal 5 output (#WE or #CFCE2)

P62: General-purpose I/O port (default)

#BUSGET: Bus status monitor signal output

T8UF2: 8-bit timer 2 output

#ADTRG: A/D converter trigger input

P64: General-purpose I/O port (default)

#WAIT: Wait cycle request input

P70: General-purpose I/O port (default)

AIN0: A/D converter Ch.0 input

P71: General-purpose I/O port (default)

AIN1: A/D converter Ch.1 input

P72: General-purpose I/O port (default)

AIN2: A/D converter Ch.2 input

P73: General-purpose I/O port (default)

AIN3: A/D converter Ch.3 input

P80: General-purpose I/O port (default)

#DMAACK2: HSDMA Ch.2 acknowledge signal output

T8UF3: 8-bit timer 3 output

EXCL3: 16-bit timer 3 event counter input

P81: General-purpose I/O port (default)

#DMAACK3: HSDMA Ch.3 acknowledge signal output

T8UF4: 8-bit timer 4 output

EXCL4: 16-bit timer 4 event counter input

P82: General-purpose I/O port (default)

#DMAEND2: HSDMA Ch.2 end-of-transfer signal output

EXCL5: 16-bit timer 5 event counter input

DBT: DBT signal output for debugging

P83: General-purpose I/O port (default)

#DMAEND3: HSDMA Ch.3 end-of-transfer signal output

EXCL6: 16-bit timer 6 event counter input

DTS0: DTS0 signal output for debugging

P84: General-purpose I/O port (default)

PSC_CLK: Prescaler clock output

CARD2: Card I/F signal 2 output (#IORD or #SMRD)

DTS1: DTS1 signal output for debugging

QFP

129

133

134

Pin No.

Pin name

P25

#SDWE

SOUT3

P26

DQML

#SCLK3

P27

DQMH

#SRDY3

P30

#DMAREQ0

T8UF0

EXCL0

P31

#DMAREQ1

T8UF1

EXCL1

P32

#DMAREQ2

CARD2

EXCL2

P33

#DMAREQ3

CARD3

WDT_CLK

P60

#BUSREQ

CARD4

P61

#BUSACK

CARD5

P62

#BUSGET

T8UF2

#ADTRG

P64

#WAIT

P70

AIN0

P71

AIN1

P72

AIN2

P73

AIN3

P80

#DMAACK2

T8UF3

EXCL3

P81

#DMAACK3

T8UF4

EXCL4

P82

#DMAEND2

EXCL5

DBT

P83

#DMAEND3

EXCL6

DTS0

P84

PSC_CLK

CARD2

DTS1

PFBGA

E12

D12

C14

Module

PORT

EBCU

SIO

PORT

EBCU

SIO

PORT

EBCU

SIO

PORT

HSDMA

T16

PORT

HSDMA

T16

PORT

HSDMA

CARD

T16

PORT

HSDMA

CARD

WDT

PORT

BBCU

CARD

PORT

BBCU

CARD

PORT

BBCU

ADC

PORT

BBCU

PORT

ADC

PORT

ADC

PORT

ADC

PORT

ADC

PORT

HSDMA

T16

PORT

HSDMA

T16

PORT

HSDMA

T16

DBG

PORT

HSDMA

T16

DBG

PORT

PSC

CARD

DBG

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-6 EPSON S1C33401 TECHNICAL MANUAL

I/O

Pull-up

∗1

Function

P85: General-purpose I/O port (default)

CMU_CLK: CMU external clock output

CARD3: Card I/F signal 3 output (#IOWR or #SMWR)

DTS2: DTS2 signal output for debugging

P86: General-purpose I/O port (default)

TM8: 16-bit timer 8 output

CARD0: Card I/F signal 0 output (#SMRD or #CFCE1)

DTS3: DTS3 signal output for debugging

P87: General-purpose I/O port (default)

TM9: 16-bit timer 9 output

CARD1: Card I/F signal 1 output (#SMWR or #CFCE2)

DTS4: DTS4 signal output for debugging

P90: General-purpose I/O port (default)

SIN2: Serial I/F Ch.2 data input

EXCL7: 16-bit timer 7 event counter input

DTD0: DTD0 signal output for debugging

P91: General-purpose I/O port (default)

SOUT2: Serial I/F Ch.2 data output

EXCL8: 16-bit timer 8 event counter input

DTD1: DTD1 signal output for debugging

P92: General-purpose I/O port (default)

#SCLK2: Serial I/F Ch.2 clock input/output

EXCL9: 16-bit timer 9 event counter input

DTD2: DTD2 signal output for debugging

P93: General-purpose I/O port (default)

#SRDY2: Serial I/F Ch.2 ready signal input/output

R/W: Read/Write status output

DTD3: DTD3 signal output for debugging

P94: General-purpose I/O port (default)

SIN3: Serial I/F Ch.3 data input

ACST: Bus access status output

DTD4: DTD4 signal output for debugging

P95: General-purpose I/O port (default)

SOUT3: Serial I/F Ch.3 data output

ASTB: Address strobe output

DTD5: DTD5 signal output for debugging

P96: General-purpose I/O port (default)

#SCLK3: Serial I/F Ch.3 clock input/output

CARD4: Card I/F signal 4 output (#OE or #CFCE1)

DTD6: DTD6 signal output for debugging

P97: General-purpose I/O port (default)

#SRDY3: Serial I/F Ch.3 ready signal input/output

CARD5: Card I/F signal 5 output (#WE or #CFCE2)

DTD7: DTD7 signal output for debugging

QFP

179

180

181

182

183

Pin No.

Pin name

P85

CMU_CLK

CARD3

DTS2

P86

TM8

CARD0

DTS3

P87

TM9

CARD1

DTS4

P90

SIN2

EXCL7

DTD0

P91

SOUT2

EXCL8

DTD1

P92

#SCLK2

EXCL9

DTD2

P93

#SRDY2

R/W

DTD3

P94

SIN3

ACST

DTD4

P95

SOUT3

ASTB

DTD5

P96

#SCLK3

CARD4

DTD6

P97

#SRDY3

CARD5

DTD7

PFBGA

Module

PORT

CMU

CARD

DBG

PORT

T16

CARD

DBG

PORT

T16

CARD

DBG

PORT

SIO

T16

DBG

PORT

SIO

T16

DBG

PORT

SIO

T16

DBG

PORT

SIO

BBCU

DBG

PORT

SIO

BBCU

DBG

PORT

SIO

BBCU

DBG

PORT

SIO

CARD

DBG

PORT

SIO

CARD

DBG

Table I.3.2.4 Debug Pin List

I/O

O (H)

O (L)

I/O

(H)

I/O

(H)

I/O

(H)

Pull-up

–

∗1

Function

Serial input/output for debugging

DCLK signal output for debugging

DST2 signal output for debugging

DST0: DST0 signal output for debugging (default)

P65: General-purpose I/O port

DST1: DST1 signal output for debugging (default)

P66: General-purpose I/O port

DPCO: DPCO signal output for debugging (default)

P67: General-purpose I/O port

QFP

169

176

172

170

171

174

Pin No.

Pin name

DSIO

DCLK

DST2

DST0

P65

DST1

P66

DPCO

P67

PFBGA

Module

DBG

PORT

DBG

PORT

DBG

PORT

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-7

Table I.3.2.5 Other Pin List

I/O

Pull-

up/down

–

∗1

Pull-up

Pull-down

–

Pull-down

–

Function

Low speed (OSC1) oscillator input

(32 kHz crystal or external clock input with VDD level)

Low speed (OSC1) oscillator output

High speed (OSC3) oscillator input

(crystal/ceramic or external clock input with VDD level)

High speed (OSC3) oscillator output

PLL analog monitor (used for current monitor)

CMU_CLK: CMU external clock output (default)

P63: General-purpose I/O port

BCLK: Bus clock output

T8UF5: 8-bit timer 5 output

Initial reset input pin

NMI request input pin

Test input pin 0 (Connect to VSS during normal operation)

Test input pin 1 (Connect to VSS during normal operation)

Wafer level burn-in test enable input

Scan test enable input

Standby input for disabling C33 operation (except RTC)

QFP

141

142

149

150

144

155

156

152

153

147

148

140

Pin No.

Pin name

OSC1

OSC2

OSC3

OSC4

VCP

CMU_CLK

P63

BCLK

T8UF5

#RESET

#NMI

TST0

TST1

BURNIN

SCANEN

#STBY

PFBGA

A13

A12

A10

C11

C10

B10

B13

Module

OSC

CMU

PORT

BBCU

CMU

–

RTC

∗1: These pins can have pull-ups enabled or disabled by setting the pin control registers. (Pull-ups are enabled by

default.)

∗2: These pins come with a bus hold latch.

Notes: • The # prefixed to pin names indicates that input/output signals of the pin are active low.

• The pin names and I/O printed in boldface denote the default pin (signal) name and default

input/output direction.

• (H) and (L) for I/O indicate the default output level. This is only indicated for signals whose

level is fixed high or low when the chip is initially reset.

• The input level must be VDD only for the OSC1 and OSC3 pins. Input levels for other pins

should be VDDE (AVDD, TMVDD) level.

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-8 EPSON S1C33401 TECHNICAL MANUAL

I.3.3 Switching Over the Multiplexed Pin Functions

I.3.3.1 Pin Function Select Bits

Each pin is assigned one to four functions, as listed in Table I.3.3.1.1.

When the chip is powered on or cold-reset, each pin defaults to function 0. If any pin must be used for other than

this default function, select the desired function by writing data to the corresponding pin function select bits.

The pin function selected is not altered by a hot reset.

Table I.3.3.1.1 List of Pin Function Select Bits

function 0

OSC1

OSC2

OSC3

OSC4

VCP

#RESET

#NMI

DSIO

DCLK

DST2

D10

D11

D12

D13

D14

D15

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

function 1

P47

P46

P45

P44

P43

P42

P41

P40

function 2

function 3

Debug

function

Function select bit

CFP47[1:0] (D[7:6]/0x40369)

CFP46[1:0] (D[5:4]/0x40369)

CFP45[1:0] (D[3:2]/0x40369)

CFP44[1:0] (D[1:0]/0x40369)

CFP43[1:0] (D[7:6]/0x40368)

CFP42[1:0] (D[5:4]/0x40368)

CFP41[1:0] (D[3:2]/0x40368)

CFP40[1:0] (D[1:0]/0x40368)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-9

function 0

#RD

#WRL

#WRH

#BSL

#CE10

#CE4

#CE5

#CE6

#CE7

#CE8

#CE9

#CE11

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P60

P61

P62

CMU_CLK

P64

P65

P66

P67

P70

P71

P72

P73

P80

P81

P82

P83

P84

P85

P86

P87

P90

P91

function 1

P50

P51

P52

P53

P54

P55

P56

SIN0

SOUT0

#SCLK0

#SRDY0

SIN1

SOUT1

#SCLK1

#SRDY1

TM0

TM1

TM2

TM3

TM4

TM5

TM6

TM7

SDCKE

SDCLK

#SDCS

#SDRAS

#SDCAS

#SDWE

DQML

DQMH

#DMAREQ0

#DMAREQ1

#DMAREQ2

#DMAREQ3

#BUSREQ

#BUSACK

#BUSGET

P63

#WAIT

AIN0

AIN1

AIN2

AIN3

#DMAACK2

#DMAACK3

#DMAEND2

#DMAEND3

PSC_CLK

CMU_CLK

TM8

TM9

SIN2

SOUT2

function 2

CARD0

CARD1

#DMAEND0

#DMAEND1

#DMAACK0

#DMAACK1

SIN2

SOUT2

#SCLK2

#SRDY2

SIN3

SOUT3

#SCLK3

#SRDY3

T8UF0

T8UF1

CARD2

CARD3

CARD4

CARD5

T8UF2

BCLK

T8UF3

T8UF4

EXCL5

EXCL6

CARD2

CARD3

CARD0

CARD1

EXCL7

EXCL8

function 3

EXCL0

EXCL1

EXCL2

WDT_CLK

#ADTRG

T8UF5

EXCL3

EXCL4

Debug

function

DST0

DST1

DPCO

DBT

DTS0

DTS1

DTS2

DTS3

DTS4

DTD0

DTD1

Function select bit

CFP50[1:0] (D[1:0]/0x4036A)

CFP51[1:0] (D[3:2]/0x4036A)

CFP52[1:0] (D[5:4]/0x4036A)

CFP53[1:0] (D[7:6]/0x4036A)

CFP54[1:0] (D[1:0]/0x4036B)

CFP55[1:0] (D[3:2]/0x4036B)

CFP56[1:0] (D[5:4]/0x4036B)

CFP00[1:0] (D[1:0]/0x40360)

CFP01[1:0] (D[3:2]/0x40360)

CFP02[1:0] (D[5:4]/0x40360)

CFP03[1:0] (D[7:6]/0x40360)

CFP04[1:0] (D[1:0]/0x40361)

CFP05[1:0] (D[3:2]/0x40361)

CFP06[1:0] (D[5:4]/0x40361)

CFP07[1:0] (D[7:6]/0x40361)

CFP10[1:0] (D[1:0]/0x40362)

CFP11[1:0] (D[3:2]/0x40362)

CFP12[1:0] (D[5:4]/0x40362)

CFP13[1:0] (D[7:6]/0x40362)

CFP14[1:0] (D[1:0]/0x40363)

CFP15[1:0] (D[3:2]/0x40363)

CFP16[1:0] (D[5:4]/0x40363)

CFP17[1:0] (D[7:6]/0x40363)

CFP20[1:0] (D[1:0]/0x40364)

CFP21[1:0] (D[3:2]/0x40364)

CFP22[1:0] (D[5:4]/0x40364)

CFP23[1:0] (D[7:6]/0x40364)

CFP24[1:0] (D[1:0]/0x40365)

CFP25[1:0] (D[3:2]/0x40365)

CFP26[1:0] (D[5:4]/0x40365)

CFP27[1:0] (D[7:6]/0x40365)

CFP30[1:0] (D[1:0]/0x40366)

CFP31[1:0] (D[3:2]/0x40366)

CFP32[1:0] (D[5:4]/0x40366)

CFP33[1:0] (D[7:6]/0x40366)

CFP60[1:0] (D[1:0]/0x4036C)

CFP61[1:0] (D[3:2]/0x4036C)

CFP62[1:0] (D[5:4]/0x4036C)

CFP63[1:0] (D[7:6]/0x4036C)

CFP64[1:0] (D[1:0]/0x4036D)

CFP70[1:0] (D[1:0]/0x4036E)

CFP71[1:0] (D[3:2]/0x4036E)

CFP72[1:0] (D[5:4]/0x4036E)

CFP73[1:0] (D[7:6]/0x4036E)

CFP80[1:0] (D[1:0]/0x40370)

CFP81[1:0] (D[3:2]/0x40370)

CFP82[1:0] (D[5:4]/0x40370)

CFP83[1:0] (D[7:6]/0x40370)

CFP84[1:0] (D[1:0]/0x40371)

CFP85[1:0] (D[3:2]/0x40371)

CFP86[1:0] (D[5:4]/0x40371)

CFP87[1:0] (D[7:6]/0x40371)

CFP90[1:0] (D[1:0]/0x40372)

CFP91[1:0] (D[3:2]/0x40372)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-10 EPSON S1C33401 TECHNICAL MANUAL

function 0

P92

P93

P94

P95

P96

P97

TST0

TST1

BURNIN

SCANEN

#STBY

function 1

#SCLK2

#SRDY2

SIN3

SOUT3

#SCLK3

#SRDY3

function 2

EXCL9

R/W

ACST

ASTB

CARD4

CARD5

function 3

Debug

function

DTD2

DTD3

DTD4

DTD5

DTD6

DTD7

Function select bit

CFP92[1:0] (D[5:4]/0x40372)

CFP93[1:0] (D[7:6]/0x40372)

CFP94[1:0] (D[1:0]/0x40373)

CFP95[1:0] (D[3:2]/0x40373)

CFP96[1:0] (D[5:4]/0x40373)

CFP97[1:0] (D[7:6]/0x40373)

• The set values 0 to 3 of the pin function select bits correspond to functions 0 to 3, respectively.

• Pins P65 to P67 operate as debugging pins when the debug function of PC trace is enabled (Enabled by default).

Similarly, pins P82 to P97 operate as debugging pins when the debug function of bus trace is enabled (Disabled

by default). The functions of these pins are switched to debugging use, regardless of how the function select bits

are set. Therefore, while the PC trace function is being used during debugging, the other functions of respective

pins cannot be used.

The debug function (PC trace, bus trace) can be enabled/disabled using a register in the debug unit.

When using the P65 to P67 pins as general-purpose I/O ports, set DPCTOE (D0/0x402EC) to 0 (PC trace output

disabled). (It is set at 1 by default)

When using the P82 to P97 pins as general-purpose I/O ports or peripheral I/O ports, keep DBTOE (D1/0x402EC)

as 0 (bus trace output disabled, default setting).

It is necessary to remove write protection of these control bits by writing 0x59 to DBGOUTP[7:0] (D[7:0]/

0x402E8) before the bit can be altered. After the bit is altered, write a value other than 0x59 to DBGOUTP[7:0]

(D[7:0]/0x402E8) to protect address 0x402EC against unnecessary writings.

∗ DPCTOE: PC Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D0/0x402EC)

∗ DBTOE: Bus Trace Signal Output Enable Bit in the Debug Signal Output Control Register (D1/0x402EC)

∗ DBGOUTP[7:0]: Debug Signal Output Control Register Write-Protect flag Bits in the Debug Signal Output

Control Write-Protect Register (D[7:0]/0x402E8)

• CARD0 to CARD5 are the output pins for card interfaces. The functions of respective pins can be selected

according to the card interface used, as listed in Table I.3.3.1.2. Use the Card I/F Output Port Configuration

Section IV.9, “Card Interface (CARD).”

Table I.3.3.1.2 Relationship between Ports and Card Interface Signals

Pin name

CARD0

CARD1

CARD2

CARD3

CARD4

CARD5

Function 0 (default)

#SMRD

#SMWR

#IORD

#IOWR

#OE

#WE

Function select bit

CARDIO0 (D0/0x40302)

CARDIO1 (D1/0x40302)

CARDIO2 (D2/0x40302)

CARDIO3 (D3/0x40302)

CARDIO4 (D4/0x40302)

CARDIO5 (D5/0x40302)

Function 1

#CFCE1

#CFCE2

#SMRD

#SMWR

#CFCE1

#CFCE2

#SMRD, #SMWR: Output pins for SmartMedia (NAND flash)

#CFCE1, #CFCE2: Output pins for CompactFlash

#IORD, #IOWR, #OE, #WE: Output pins for PC Card

∗ CARDIOx: CARDx Port Function Select Bit in the Card I/F Output Port Configuration Register (Dx/0x40302)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-11

I.3.3.2 List of Port Function Select Registers

Table I.3.3.2.1 List of Port Function Select Registers

Address

0x00040360

0x00040361

0x00040362

0x00040363

0x00040364

0x00040365

0x00040366

0x00040368

0x00040369

0x0004036A

0x0004036B

0x0004036C

0x0004036D

0x0004036E

0x00040370

0x00040371

0x00040372

0x00040373

Function

Selects P00–P03 port pin functions.

Selects P04–P07 port pin functions.

Selects P10–P13 port pin functions.

Selects P14–P17 port pin functions.

Selects P20–P23 port pin functions.

Selects P24–P27 port pin functions.

Selects P30–P33 port pin functions.

Selects P40–P43 port pin functions.

Selects P44–P47 port pin functions.

Selects P50–P53 port pin functions.

Selects P54–P56 port pin functions.

Selects P60–P63 port pin functions.

Selects P64–P67 port pin functions.

Selects P70–P73 port pin functions.

Selects P80–P83 port pin functions.

Selects P84–P87 port pin functions.

Selects P90–P93 port pin functions.

Selects P94–P97 port pin functions.

P00–P03 Port Function Select Register (pP0_03_CFP)

P04–P07 Port Function Select Register (pP0_47_CFP)

P10–P13 Port Function Select Register (pP1_03_CFP)

P14–P17 Port Function Select Register (pP1_47_CFP)

P20–P23 Port Function Select Register (pP2_03_CFP)

P24–P27 Port Function Select Register (pP2_47_CFP)

P30–P33 Port Function Select Register (pP3_03_CFP)

P40–P43 Port Function Select Register (pP4_03_CFP)

P44–P47 Port Function Select Register (pP4_47_CFP)

P50–P53 Port Function Select Register (pP5_03_CFP)

P54–P56 Port Function Select Register (pP5_46_CFP)

P60–P63 Port Function Select Register (pP6_03_CFP)

P64–P67 Port Function Select Register (pP6_47_CFP)

P70–P73 Port Function Select Register (pP7_03_CFP)

P80–P83 Port Function Select Register (pP8_03_CFP)

P84–P87 Port Function Select Register (pP8_47_CFP)

P90–P93 Port Function Select Register (pP9_03_CFP)

P94–P97 Port Function Select Register (pP9_47_CFP)

Size

The following describes each port function select register.

The port function select registers are mapped to the 8-bit device area at addresses 0x40360 to 0x40373, and can be

accessed in units of bytes.

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-12 EPSON S1C33401 TECHNICAL MANUAL

0x40360: P00–P03 Port Function Select Register (pP0_03_CFP)

Name

Address

CFP031

CFP030

CFP021

CFP020

CFP011

CFP010

CFP001

CFP000

P03 port extended function

P02 port extended function

P01 port extended function

P00 port extended function

R/W

0040360

(B)

P00–P03

port function

select register

(pP0_03_CFP)

CFP03[1:0] Function

reserved

#SRDY0

P03

CFP02[1:0] Function

reserved

#SCLK0

P02

CFP01[1:0] Function

reserved

SOUT0

P01

1∗

CFP00[1:0] Function

reserved

SIN0

P00

This register selects the functions of ports P00 to P03.

D[7:6] CFP03[1:0]: P03 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): #SRDY0

00 (R/W): P03 (default)

D[5:4] CFP02[1:0]: P02 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): #SCLK0

00 (R/W): P02 (default)

D[3:2] CFP01[1:0]: P01 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): SOUT0

00 (R/W): P01 (default)

D[1:0] CFP00[1:0]: P00 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): SIN0

00 (R/W): P00 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-13

0x40361: P04–P07 Port Function Select Register (pP0_47_CFP)

Name

Address

CFP071

CFP070

CFP061

CFP060

CFP051

CFP050

CFP041

CFP040

P07 port extended function

P06 port extended function

P05 port extended function

P04 port extended function

R/W

0040361

(B)

P04–P07

port function

select register

(pP0_47_CFP)

CFP07[1:0] Function

reserved

#SRDY1

P07

CFP06[1:0] Function

reserved

#SCLK1

P06

CFP05[1:0] Function

reserved

SOUT1

P05

1∗

CFP04[1:0] Function

reserved

SIN1

P04

This register selects the functions of ports P04 to P07.

D[7:6] CFP07[1:0]: P07 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): #SRDY1

00 (R/W): P07 (default)

D[5:4] CFP06[1:0]: P06 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): #SCLK1

00 (R/W): P06 (default)

D[3:2] CFP05[1:0]: P05 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): SOUT1

00 (R/W): P05 (default)

D[1:0] CFP04[1:0]: P04 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): SIN1

00 (R/W): P04 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-14 EPSON S1C33401 TECHNICAL MANUAL

0x40362: P10–P13 Port Function Select Register (pP1_03_CFP)

Name

Address

CFP131

CFP130

CFP121

CFP120

CFP111

CFP110

CFP101

CFP100

P13 port extended function

P12 port extended function

P11 port extended function

P10 port extended function

R/W

0040362

(B)

P10–P13

port function

select register

(pP1_03_CFP)

CFP13[1:0] Function

reserved

TM3

P13

CFP12[1:0] Function

reserved

TM2

P12

CFP11[1:0] Function

reserved

TM1

P11

1∗

CFP10[1:0] Function

reserved

TM0

P10

This register selects the functions of ports P10 to P13.

D[7:6] CFP13[1:0]: P13 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): TM3

00 (R/W): P13 (default)

D[5:4] CFP12[1:0]: P12 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): TM2

00 (R/W): P12 (default)

D[3:2] CFP11[1:0]: P11 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): TM1

00 (R/W): P11 (default)

D[1:0] CFP10[1:0]: P10 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): TM0

00 (R/W): P10 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-15

0x40363: P14–P17 Port Function Select Register (pP1_47_CFP)

Name

Address

CFP171

CFP170

CFP161

CFP160

CFP151

CFP150

CFP141

CFP140

P17 port extended function

P16 port extended function

P15 port extended function

P14 port extended function

R/W

0040363

(B)

P14–P17

port function

select register

(pP1_47_CFP)

CFP17[1:0] Function

reserved

#DMAACK1

TM7

P17

CFP16[1:0] Function

reserved

#DMAACK0

TM6

P16

CFP15[1:0] Function

reserved

#DMAEND1

TM5

P15

CFP14[1:0] Function

reserved

#DMAEND0

TM4

P14

This register selects the functions of ports P14 to P17.

D[7:6] CFP17[1:0]: P17 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #DMAACK1

01 (R/W): TM7

00 (R/W): P17 (default)

D[5:4] CFP16[1:0]: P16 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #DMAACK0

01 (R/W): TM6

00 (R/W): P16 (default)

D[3:2] CFP15[1:0]: P15 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #DMAEND1

01 (R/W): TM5

00 (R/W): P15 (default)

D[1:0] CFP14[1:0]: P14 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #DMAEND0

01 (R/W): TM4

00 (R/W): P14 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-16 EPSON S1C33401 TECHNICAL MANUAL

0x40364: P20–P23 Port Function Select Register (pP2_03_CFP)

Name

Address

CFP231

CFP230

CFP221

CFP220

CFP211

CFP210

CFP201

CFP200

P23 port extended function

P22 port extended function

P21 port extended function

P20 port extended function

R/W

0040364

(B)

P20–P23

port function

select register

(pP2_03_CFP)

CFP23[1:0] Function

reserved

#SRDY2

#SDRAS

P23

CFP22[1:0] Function

reserved

#SCLK2

#SDCS

P22

CFP21[1:0] Function

reserved

SOUT2

SDCLK

P21

CFP20[1:0] Function

reserved

SIN2

SDCKE

P20

This register selects the functions of ports P20 to P23.

D[7:6] CFP23[1:0]: P23 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #SRDY2

01 (R/W): #SDRAS

00 (R/W): P23 (default)

D[5:4] CFP22[1:0]: P22 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #SCLK2

01 (R/W): #SDCS

00 (R/W): P22 (default)

D[3:2] CFP21[1:0]: P21 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): SOUT2

01 (R/W): SDCLK

00 (R/W): P21 (default)

D[1:0] CFP20[1:0]: P20 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): SIN2

01 (R/W): SDCKE

00 (R/W): P20 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-17

0x40365: P24–P27 Port Function Select Register (pP2_47_CFP)

Name

Address

CFP271

CFP270

CFP261

CFP260

CFP251

CFP250

CFP241

CFP240

P27 port extended function

P26 port extended function

P25 port extended function

P24 port extended function

R/W

0040365

(B)

P24–P27

port function

select register

(pP2_47_CFP)

CFP27[1:0] Function

reserved

#SRDY3

DQMH

P27

CFP26[1:0] Function

reserved

#SCLK3

DQML

P26

CFP25[1:0] Function

reserved

SOUT3

#SDWE

P25

CFP24[1:0] Function

reserved

SIN3

#SDCAS

P24

This register selects the functions of ports P24 to P27.

D[7:6] CFP27[1:0]: P27 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #SRDY3

01 (R/W): DQMH

00 (R/W): P27 (default)

D[5:4] CFP26[1:0]: P26 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): #SCLK3

01 (R/W): DQML

00 (R/W): P26 (default)

D[3:2] CFP25[1:0]: P25 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): SOUT3

01 (R/W): #SDWE

00 (R/W): P25 (default)

D[1:0] CFP24[1:0]: P24 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): SIN3

01 (R/W): #SDCAS

00 (R/W): P24 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-18 EPSON S1C33401 TECHNICAL MANUAL

0x40366: P30–P33 Port Function Select Register (pP3_03_CFP)

Name

Address

CFP331

CFP330

CFP321

CFP320

CFP311

CFP310

CFP301

CFP300

P33 port extended function

P32 port extended function

P31 port extended function

P30 port extended function

R/W

0040366

(B)

P30–P33

port function

select register

(pP3_03_CFP)

CFP33[1:0] Function

WDT_CLK

CARD3

#DMAREQ3

P33

CFP32[1:0] Function

EXCL2

CARD2

#DMAREQ2

P32

CFP31[1:0] Function

EXCL1

T8UF1

#DMAREQ1

P31

CFP30[1:0] Function

EXCL0

T8UF0

#DMAREQ0

P30

This register selects the functions of ports P30 to P33.

D[7:6] CFP33[1:0]: P33 Port Extended Function Select Bits

11 (R/W): WDT_CLK

10 (R/W): CARD3

01 (R/W): #DMAREQ3

00 (R/W): P33 (default)

D[5:4] CFP32[1:0]: P32 Port Extended Function Select Bits

11 (R/W): EXCL2

10 (R/W): CARD2

01 (R/W): #DMAREQ2

00 (R/W): P32 (default)

D[3:2] CFP31[1:0]: P31 Port Extended Function Select Bits

11 (R/W): EXCL1

10 (R/W): T8UF1

01 (R/W): #DMAREQ1

00 (R/W): P31 (default)

D[1:0] CFP30[1:0]: P30 Port Extended Function Select Bits

11 (R/W): EXCL0

10 (R/W): T8UF0

01 (R/W): #DMAREQ0

00 (R/W): P30 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-19

0x40368: P40–P43 Port Function Select Register (pP4_03_CFP)

Name

Address

CFP431

CFP430

CFP421

CFP420

CFP411

CFP410

CFP401

CFP400

P43 port extended function

P42 port extended function

P41 port extended function

P40 port extended function

R/W

0040368

(B)

P40–P43

port function

select register

(pP4_03_CFP)

CFP43[1:0] Function

reserved

P43

A22

CFP42[1:0] Function

reserved

P42

A23

CFP41[1:0] Function

reserved

P41

A24

1∗

CFP40[1:0] Function

reserved

P40

A25

This register selects the functions of ports P40 to P43.

D[7:6] CFP43[1:0]: P43 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P43

00 (R/W): A22 (default)

D[5:4] CFP42[1:0]: P42 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P42

00 (R/W): A23 (default)

D[3:2] CFP41[1:0]: P41 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P41

00 (R/W): A24 (default)

D[1:0] CFP40[1:0]: P40 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P40

00 (R/W): A25 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-20 EPSON S1C33401 TECHNICAL MANUAL

0x40369: P44–P47 Port Function Select Register (pP4_47_CFP)

Name

Address

CFP471

CFP470

CFP461

CFP460

CFP451

CFP450

CFP441

CFP440

P47 port extended function

P46 port extended function

P45 port extended function

P44 port extended function

R/W

0040369

(B)

P44–P47

port function

select register

(pP4_47_CFP)

CFP47[1:0] Function

reserved

P47

A18

CFP46[1:0] Function

reserved

P46

A19

CFP45[1:0] Function

reserved

P45

A20

1∗

CFP44[1:0] Function

reserved

P44

A21

This register selects the functions of ports P44 to P47.

D[7:6] CFP47[1:0]: P47 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P47

00 (R/W): A18 (default)

D[5:4] CFP46[1:0]: P46 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P46

00 (R/W): A19 (default)

D[3:2] CFP45[1:0]: P45 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P45

00 (R/W): A20 (default)

D[1:0] CFP44[1:0]: P44 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P44

00 (R/W): A21 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-21

0x4036A: P50–P53 Port Function Select Register (pP5_03_CFP)

Name

Address

CFP531

CFP530

CFP521

CFP520

CFP511

CFP510

CFP501

CFP500

P53 port extended function

P52 port extended function

P51 port extended function

P50 port extended function

R/W

004036A

(B)

P50–P53

port function

select register

(pP5_03_CFP)

CFP53[1:0] Function

reserved

CARD1

P53

#CE7

CFP52[1:0] Function

reserved

P52

#CE6

CFP51[1:0] Function

reserved

P51

#CE5

1∗

CFP50[1:0] Function

reserved

CARD0

P50

#CE4

This register selects the functions of ports P50 to P53.

D[7:6] CFP53[1:0]: P53 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD1

01 (R/W): P53

00 (R/W): #CE7 (default)

D[5:4] CFP52[1:0]: P52 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P52

00 (R/W): #CE6 (default)

D[3:2] CFP51[1:0]: P51 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P51

00 (R/W): #CE5 (default)

D[1:0] CFP50[1:0]: P50 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD0

01 (R/W): P50

00 (R/W): #CE4 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-22 EPSON S1C33401 TECHNICAL MANUAL

0x4036B: P54–P56 Port Function Select Register (pP5_46_CFP)

Name

Address

–

CFP561

CFP560

CFP551

CFP550

CFP541

CFP540

D7–6

reserved

P56 port extended function

P55 port extended function

P54 port extended function

–

R/W

0 when being read.

004036B

(B)

P54–P56

port function

select register

(pP5_46_CFP)

CFP56[1:0] Function

reserved

P56

#CE11

CFP55[1:0] Function

reserved

P55

#CE9

1∗

CFP54[1:0] Function

reserved

P54

#CE8

–

This register selects the functions of ports P54 to P56.

D[7:6] Reserved

D[5:4] CFP56[1:0]: P56 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P56

00 (R/W): #CE11 (default)

D[3:2] CFP55[1:0]: P55 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P55

00 (R/W): #CE9 (default)

D[1:0] CFP54[1:0]: P54 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): P54

00 (R/W): #CE8 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-23

0x4036C: P60–P63 Port Function Select Register (pP6_03_CFP)

Name

Address

CFP631

CFP630

CFP621

CFP620

CFP611

CFP610

CFP601

CFP600

P63 port extended function

P62 port extended function

P61 port extended function

P60 port extended function

R/W

004036C

(B)

P60–P63

port function

select register

(pP6_03_CFP)

CFP63[1:0] Function

T8UF5

BCLK

P63

CMU_CLK

CFP62[1:0] Function

#ADTRG

T8UF2

#BUSGET

P62

CFP61[1:0] Function

reserved

CARD5

#BUSACK

P61

CFP60[1:0] Function

reserved

CARD4

#BUSREQ

P60

This register selects the functions of ports P60 to P63.

D[7:6] CFP63[1:0]: P63 Port Extended Function Select Bits

11 (R/W): T8UF5

10 (R/W): BCLK

01 (R/W): P63

00 (R/W): CMU_CLK (default)

D[5:4] CFP62[1:0]: P62 Port Extended Function Select Bits

11 (R/W): #ADTRG

10 (R/W): T8UF2

01 (R/W): #BUSGET

00 (R/W): P62 (default)

D[3:2] CFP61[1:0]: P61 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD5

01 (R/W): #BUSACK

00 (R/W): P61 (default)

D[1:0] CFP60[1:0]: P60 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD4

01 (R/W): #BUSREQ

00 (R/W): P60 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-24 EPSON S1C33401 TECHNICAL MANUAL

0x4036D: P64–P67 Port Function Select Register (pP6_47_CFP)

Name

Address

–

CFP641

CFP640

D7–2

reserved

P64 port extended function

–

R/W

0 when being read.

004036D

(B)

P64–P67

port function

select register

(pP6_47_CFP)

CFP64[1:0] Function

reserved

#WAIT

P64

1∗

–

This register selects the function of port P64.

D[7:2] Reserved

D[1:0] CFP64[1:0]: P64 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): #WAIT

00 (R/W): P64 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-25

0x4036E: P70–P73 Port Function Select Register (pP7_03_CFP)

Name

Address

CFP731

CFP730

CFP721

CFP720

CFP711

CFP710

CFP701

CFP700

P73 port extended function

P72 port extended function

P71 port extended function

P70 port extended function

R/W

004036E

(B)

P70–P73

port function

select register

(pP7_03_CFP)

CFP73[1:0] Function

reserved

AIN3

P73

CFP72[1:0] Function

reserved

AIN2

P72

CFP71[1:0] Function

reserved

AIN1

P71

1∗

CFP70[1:0] Function

reserved

AIN0

P70

This register selects the functions of ports P70 to P73.

D[7:6] CFP73[1:0]: P73 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): AIN3

00 (R/W): P73 (default)

D[5:4] CFP72[1:0]: P72 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): AIN2

00 (R/W): P72 (default)

D[3:2] CFP71[1:0]: P71 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): AIN1

00 (R/W): P71 (default)

D[1:0] CFP70[1:0]: P70 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): Reserved

01 (R/W): AIN0

00 (R/W): P70 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-26 EPSON S1C33401 TECHNICAL MANUAL

0x40370: P80–P83 Port Function Select Register (pP8_03_CFP)

Name

Address

CFP831

CFP830

CFP821

CFP820

CFP811

CFP810

CFP801

CFP800

P83 port extended function

P82 port extended function

P81 port extended function

P80 port extended function

R/W

0040370

(B)

P80–P83

port function

select register

(pP8_03_CFP)

CFP83[1:0] Function

reserved

EXCL6

#DMAEND3

P83

CFP82[1:0] Function

reserved

EXCL5

#DMAEND2

P82

CFP81[1:0] Function

EXCL4

T8UF4

#DMAACK3

P81

CFP80[1:0] Function

EXCL3

T8UF3

#DMAACK2

P80

This register selects the functions of ports P80 to P83.

D[7:6] CFP83[1:0]: P83 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): EXCL6

01 (R/W): #DMAEND3

00 (R/W): P83 (default)

D[5:4] CFP82[1:0]: P82 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): EXCL5

01 (R/W): #DMAEND2

00 (R/W): P82 (default)

D[3:2] CFP81[1:0]: P81 Port Extended Function Select Bits

11 (R/W): EXCL4

10 (R/W): T8UF4

01 (R/W): #DMAACK3

00 (R/W): P81 (default)

D[1:0] CFP80[1:0]: P80 Port Extended Function Select Bits

11 (R/W): EXCL3

10 (R/W): T8UF3

01 (R/W): #DMAACK2

00 (R/W): P80 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-27

0x40371: P84–P87 Port Function Select Register (pP8_47_CFP)

Name

Address

CFP871

CFP870

CFP861

CFP860

CFP851

CFP850

CFP841

CFP840

P87 port extended function

P86 port extended function

P85 port extended function

P84 port extended function

R/W

0040371

(B)

P84–P87

port function

select register

(pP8_47_CFP)

CFP87[1:0] Function

reserved

CARD1

TM9

P87

CFP86[1:0] Function

reserved

CARD0

TM8

P86

CFP85[1:0] Function

reserved

CARD3

CMU_CLK

P85

CFP84[1:0] Function

reserved

CARD2

PSC_CLK

P84

This register selects the functions of ports P84 to P87.

D[7:6] CFP87[1:0]: P87 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD1

01 (R/W): TM9

00 (R/W): P87 (default)

D[5:4] CFP86[1:0]: P86 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD0

01 (R/W): TM8

00 (R/W): P86 (default)

D[3:2] CFP85[1:0]: P85 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD3

01 (R/W): CMU_CLK

00 (R/W): P85 (default)

D[1:0] CFP84[1:0]: P84 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD2

01 (R/W): PSC_CLK

00 (R/W): P84 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-28 EPSON S1C33401 TECHNICAL MANUAL

0x40372: P90–P93 Port Function Select Register (pP9_03_CFP)

Name

Address

CFP931

CFP930

CFP921

CFP920

CFP911

CFP910

CFP901

CFP900

P93 port extended function

P92 port extended function

P91 port extended function

P90 port extended function

R/W

0040372

(B)

P90–P93

port function

select register

(pP9_03_CFP)

CFP93[1:0] Function

reserved

R/W

#SRDY2

P93

CFP92[1:0] Function

reserved

EXCL9

#SCLK2

P92

CFP91[1:0] Function

reserved

EXCL8

SOUT2

P91

CFP90[1:0] Function

reserved

EXCL7

SIN2

P90

This register selects the functions of ports P90 to P93.

D[7:6] CFP93[1:0]: P93 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): R/W

01 (R/W): #SRDY2

00 (R/W): P93 (default)

D[5:4] CFP92[1:0]: P92 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): EXCL9

01 (R/W): #SCLK2

00 (R/W): P92 (default)

D[3:2] CFP91[1:0]: P91 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): EXCL8

01 (R/W): SOUT2

00 (R/W): P91 (default)

D[1:0] CFP90[1:0]: P90 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): EXCL7

01 (R/W): SIN2

00 (R/W): P90 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-29

0x40373: P94–P97 Port Function Select Register (pP9_47_CFP)

Name

Address

CFP971

CFP970

CFP961

CFP960

CFP951

CFP950

CFP941

CFP940

P97 port extended function

P96 port extended function

P95 port extended function

P94 port extended function

R/W

0040373

(B)

P94–P97

port function

select register

(pP9_47_CFP)

CFP97[1:0] Function

reserved

CARD5

#SRDY3

P97

CFP96[1:0] Function

reserved

CARD4

#SCLK3

P96

CFP95[1:0] Function

reserved

ASTB

SOUT3

P95

CFP94[1:0] Function

reserved

ACST

SIN3

P94

This register selects the functions of ports P94 to P97.

D[7:6] CFP97[1:0]: P97 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD5

01 (R/W): #SRDY3

00 (R/W): P97 (default)

D[5:4] CFP96[1:0]: P96 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): CARD4

01 (R/W): #SCLK3

00 (R/W): P96 (default)

D[3:2] CFP95[1:0]: P95 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): ASTB

01 (R/W): SOUT3

00 (R/W): P95 (default)

D[1:0] CFP94[1:0]: P94 Port Extended Function Select Bits

11 (R/W): Reserved

10 (R/W): ACST

01 (R/W): SIN3

00 (R/W): P94 (default)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-30 EPSON S1C33401 TECHNICAL MANUAL

I.3.4 Input/Output Cells and Input/Output Characteristics

Table I.3.4.1 Pin Characteristics

I/O cell name

LLINY

LLOTY

LLINY

LLOTY

HIBHP1TY

HBBH2BP1TY

HOB2BTY

HBBT2BHTY

HBBH2BP2TY

HBBH1BP2TY

Input level

transparent

–

transparent

–

Schmitt

–

LVTTL

Schmitt

IOH/IOL

–

4 mA

2 mA

Pull-up/down

–

50 kΩ up

–

Bus-hold latch

100 kΩ up

I/O

Power

source

RTCVDD

VDD

PLLVDD

VDDE

Remarks

note 5

note 2

note 6

note 1

Signal name

OSC1

OSC2

OSC3

OSC4

VCP

#RESET

#NMI

DSIO

DCLK

DST2

D10

D11

D12

D13

D14

D15

A10

A11

A12

A13

A14

A15

A16

A17

A18 (P47)

A19 (P46)

A20 (P45)

A21 (P44)

A22 (P43)

A23 (P42)

A24 (P41)

A25 (P40)

#RD

#WRL

#WRH

#BSL

#CE10

#CE4 (P50/CARD0)

#CE5 (P51)

#CE6 (P52)

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-31

I/O cell name

HBBH1BP2TY

HBBH2AP2TY

HBBH1BP2TY

HBBH2BP2TY

HIBASP2TY

HBBH1BP2TY

HBBH2BP2TY

LITST1Y

HIBHD1TY

HIBHY

HIBHD1TY

LIBHY

Input level

Schmitt

LVCMOS

Schmitt

LVCMOS

Schmitt

LVCMOS

IOH/IOL

2 mA

4 mA

2 mA

4 mA

–

2 mA

4 mA

–

Pull-up/down

100 kΩ up

60 kΩ down

50 kΩ down

–

50 kΩ down

–

I/O

Power

source

VDDE

TMVDD

VDDE

AVDD

VDDE

Remarks

note 1

note 1, 4

note 1

note 1, 3

note 1

Signal name

#CE7 (P53/CARD1)

#CE8 (P54)

#CE9 (P55)

#CE11 (P56)

P00 (SIN0)

P01 (SOUT0)

P02 (#SCLK0)

P03 (#SRDY0)

P04 (SIN1)

P05 (SOUT1)

P06 (#SCLK1)

P07 (#SRDY1)

P10 (TM0)

P11 (TM1)

P12 (TM2)

P13 (TM3)

P14 (TM4/#DMAEND0)

P15 (TM5/#DMAEND1)

P16 (TM6/#DMAACK0)

P17 (TM7/#DMAACK1)

P20 (SDCKE/SIN2)

P21 (SDCLK/SOUT2)

P22 (#SDCS/#SCLK2)

P23 (#SDRAS/#SRDY2)

P24 (#SDCAS/SIN3)

P25 (#SDWE/SOUT3)

P26 (DQML/#SCLK3)

P27 (DQMH/#SRDY3)

P30 (#DMAREQ0/T8UF0/EXCL0)

P31 (#DMAREQ1/T8UF1/EXCL1)

P32 (#DMAREQ2/CARD2/EXCL2)

P33 (#DMAREQ3/CARD3/WDT_CLK)

P60 (#BUSREQ/CARD4)

P61 (#BUSACK/CARD5)

P62 (#BUSGET/T8UF2/#ADTRG)

CMU_CLK (P63/BCLK/T8UF5)

P64 (#WAIT)

DST0 (P65)

DST1 (P66)

DPCO (P67)

P70 (AIN0)

P71 (AIN1)

P72 (AIN2)

P73 (AIN3)

P80 (#DMAACK2/T8UF3/EXCL3)

P81 (#DMAACK3/T8UF4/EXCL4)

P82 (#DMAEND2/EXCL5/DBT)

P83 (#DMAEND3/EXCL6/DTS0)

P84 (PSC_CLK/CARD2/DTS1)

P85 (CMU_CLK/CARD3/DTS2)

P86 (TM8/CARD0/DTS3)

P87 (TM9/CARD1/DTS4)

P90 (SIN2/EXCL7/DTD0)

P91 (SOUT2/EXCL8/DTD1)

P92 (#SCLK2/EXCL9/DTD2)

P93 (#SRDY2/R/W/DTD3)

P94 (SIN3/ACST/DTD4)

P95 (SOUT3/ASTB/DTD5)

P96 (#SCLK3/CARD4/DTD6)

P97 (#SRDY3/CARD5/DTD7)

TST0

TST1

BURNIN

SCANEN

#STBY

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-32 EPSON S1C33401 TECHNICAL MANUAL

Notes: 1 Pull-ups can be enabled or disabled by setting the pin control registers. (Pull-ups are enabled

by default.)

2 This pin must be used in input voltage range 0 V ≤ VIN ≤ VDD.

3 This pin must be used in input voltage range 0 V ≤ VIN ≤ AVDD.

4 This pin must be used in input voltage range 0 V ≤ VIN ≤ TMVDD.

5 This pin must be used in input voltage range 0 V ≤ VIN ≤ RTCVDD.

6 This pin must be used in input voltage range 0 V ≤ VIN ≤ PLLVDD.

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-33

I.3.5 Package

I.3.5.1 QFP20-184pin Package

93138

INDEX

461

184

139

1.4±0.1

0.1

1.7

max

20±0.1

22±0.4

20±0.1

22±0.4

0.160.4 +0.05

–0.03

0.5±0.2

0°

10°

0.125+0.05

–0.025

Figure I.3.5.1.1 QFP20-184pin Package Dimensions

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

I-3-34 EPSON S1C33401 TECHNICAL MANUAL

I.3.5.2 PFBGA-160pin Package

Top View

Bottom View

A1 Corner

Index

φφ

b×M

Symbol

Min

9.8

0.17

0.27

Dimension in Millimeters

Nom

10.0

0.22

0.65

0.32

0.325

0.775

Max

10.2

1.20

0.27

0.37

0.08

0.10

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Figure I.3.5.2.1 PFBGA-160pin Package Dimensions

I S1C33401 SPECIFICATIONS: PIN DESCRIPTION

S1C33401 TECHNICAL MANUAL EPSON I-3-35

I.3.5.3 Thermal Resistance of the Package

The chip temperature of LSI devices tends to increase with the power consumed on the chip. The chip temperature

when encapsulated in a package is calculated from its ambient temperature (Ta), the thermal resistance of the

package (θ), and power dissipation (PD).

Chip temperature (Tj) = Ta + (PD × θ) [°C]

When used under normal operating conditions, make sure that the chip temperature (Tj) is 100°C or less.

Thermal resistance of the QFP20-184pin package

1. When mounted on a board (windless condition)

Thermal resistance (θj-a) = 33.3°C/W

This value indicates the thermal resistance of the package when measured under a windless condition, with

the sample mounted on a measurement board (size: 114 × 76 × 1.6 mm thick, FR4/4 layered board).

2. When suspended alone (windless condition)

Thermal resistance = 90–100°C/W

This value indicates the thermal resistance of the package when measured under a windless condition, with

the sample suspended alone.

Thermal resistance of the PFBGA-160pin package

1. When mounted on a board (windless condition)

Thermal resistance (θj-a) = 30°C/W

This value indicates the thermal resistance of the package when measured under a windless condition, with

the sample mounted on a measurement board (size: 114.5 × 101.5 × 1.6 mm thick, FR4/4 layered board).

2. When suspended alone (windless condition)

Thermal resistance = 165°C/W

This value indicates the thermal resistance of the package when measured under a windless condition, with

the sample suspended alone.

Note: The thermal resistance of the package varies significantly depending on how it is mounted on the

board and whether forcibly air-cooled.

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THIS PAGE IS BLANK.

I S1C33401 SPECIFICATIONS: POWER SUPPLY

S1C33401 TECHNICAL MANUAL EPSON I-4-1

Power

I.4 Power Supply

This section explains the operating voltage of the S1C33401.

I.4.1 Power Supply Pins

The S1C33401 has the power supply pins shown in Table I.4.1.1.

Table I.4.1.1 Power Supply Pins

Function

Power supply (+) for the internal logic circuits (1.65 V to 1.95 V)

Power supply (–); GND

Power supply (+) for the PLL (PLLVDD = VDD)

Power supply (–) for the PLL (PLLVSS = VSS)

Power supply (+) for the RTC (RTCVDD = VDD)

Power supply (+) for the I/O block (2.7 V to 3.6 V)

Power supply (+) for PWM timer outputs (P1x port) (TMVDD = VDDE)

Power supply (+) for the analog system and AIN0–AIN3 (AVDD = VDDE)

QFP

9,25,40,57,71,82,101,

117,130,146,160,173

12,23,35,52,63,73,84,91,98,

105,113,123,132,138,151,

165,175,184

143

145

139

4,15,29,61,75,87,97,107,

119,128,154,177

Pin No.

Pin name

VDD

VSS

PLLVDD

PLLVSS

RTCVDD

VDDE

TMVDD

AVDD

PFBGA

B7,B11,E4,F11,G14,

L5,L12

A11,B14,C3,D6,D13,E2,

H14,K3,K11,L8,M10,N13

C12

D11

B12

D4,D9,E14,H4,H11,M6,N11

I/O

interface circuit

CPU core

Internal logic

circuits

VDD

1.65 to 1.95 V

GND

PLLVDD

1.65 to 1.95 V

VDDE

2.70 to 3.60 V

PLLVSS

GND

OSC3

oscillator

PLL

OSC1

oscillator RTC

I/O

interface circuit (P1x)

TMVDD

2.70 to 3.60 V

Analog circuits

(A/D converter)

AVDD

2.70 to 3.60 V

RTCVDD

1.65 to 1.95 V

Figure I.4.1.1 Power Supply System

I S1C33401 SPECIFICATIONS: POWER SUPPLY

I-4-2 EPSON S1C33401 TECHNICAL MANUAL

I.4.2 Operating Voltage (VDD, VSS)

The core CPU and internal logic circuits operate with a voltage supplied between the VDD and VSS pins. The

following operating voltage can be used:

VDD = 1.65 V to 1.95 V (1.8 V ± 0.15 V, VSS = GND)

Note: The S1C33401 QFP package has 12 VDD pins and 18 VSS pins; the PFBGA package has 7 VDD pins

and 12 VSS pins. Be sure to supply the operating voltage to all the pins. Do not open any of them.

I.4.3 Power Supply for PLL (PLLVDD, PLLVSS)

The PLL power supply pins (PLLVDD, PLLVSS) are provided separately from the VDD and VSS pins in order that the

digital circuits do not affect the PLL circuit. Supply the same voltage level as the VDD to the PLLVDD pin.

PLLVDD = VDD, PLLVSS = VSS

Noise on the PLL power lines decrease the PLL output precision, so use a stabilized power supply and make the

board pattern with consideration given to that.

I.4.4 Power Supply for I/O Interface (VDDE)

The VDDE voltage is used for interfacing with external I/O signals. For the output interface of the S1C33401, the

VDDE voltage is used as high level and the VSS voltage as low level. The VSS pin is used for the ground common

with VDD. The following voltage is enabled for VDDE:

VDDE = 2.70 V to 3.60 V (3.0/3.3 V ± 0.3 V, VSS = GND)

Notes: • The S1C33401 QFP package has 12 VDDE pins; the PFBGA package has 7 VDDE pins. Be sure

to supply the operating voltage to all the pins. Do not open any of them.

• When an external clock is input to the OSC3 pin, the clock signal level must be VDD.

I.4.5 Power Supply for T16 PWM Output (P1x) Ports (TMVDD)

The P1x port power supply pin (TMVDD) is provided separately from the VDDE pins. Supplying the AVDD voltage,

which is isolated from the power supply for other I/O signals, to the TMVDD pin as well as the AVDD pin allows

noise reduction in the audio signals output from 16-bit timers (PWM).

Supply the same voltage level as the VDDE to the TMVDD pin.

TMVDD = VDDE (VSS = GND)

I.4.6 Power Supply for Analog Circuits (AVDD)

The analog power supply pin (AVDD) is provided separately from the VDD and VDDE pins in order that the digital

circuits do not affect the analog circuit (A/D converter). The AVDD pin is used to supply an analog power voltage

and the VSS pin is used as the analog ground.

The following voltage is enabled for AVDD:

AVDD = 2.70 V to 3.60 V (3.0/3.3 V ± 0.3 V, VSS = GND)

Note: Be sure to supply VDDE to the AVDD pin when the analog circuit is not used.

Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make

the board pattern with consideration given to that.

I.4.7 Power Supply for RTC (RTCVDD)

The RTC has a power supply pin (RTCVDD) provided independently of other blocks of the system. When the RTC

is supplied with continuous power from this pin, it is assured of continued timekeeping operation even when all

other power supplies are turned off. Supply the same voltage level as the VDD to the RTCVDD pin.

RTCVDD = VDD (VSS = GND)

I S1C33401 SPECIFICATIONS: POWER SUPPLY

S1C33401 TECHNICAL MANUAL EPSON I-4-3

Power

I.4.8 Precautions on Power Supply

Power-on sequence

In order to operate the device normally, supply power in accordance with the following timing.

VDDE, TMVDD, AVDD

VDD, PLLVDD

OSC3

PLL

#RESET

min.

VDD

STA3

PLL

RST

Figure I.4.8.1 Power-On Sequence

(1) tVDD: Elapsed time until the power supply stabilizes after power-on

Supply power in the following sequence (or simultaneously).

Power-on: VDD and PLLVDD (Internal) → VDDE, TMVDD and AVDD (I/O) → Apply the input signal

(2) tSTA3: Time at which OSC3 oscillation starts

(3) tPLL: Time at which PLL locks up

(4) tRST: Minimum reset pulse width

Time at which the clock supplied to the C33 ADV core CPU stabilizes plus at least six clocks; Keep

the #RESET signal low.

Power-off sequence

Shut off the power supply in the following sequence (or simultaneously).

Power-off: Turn off the input signal → AVDD, TMVDD and VDDE (I/O) → PLLVDD and VDD (Internal)

Latch-up

The CMOS device may be in the latch-up condition. This is the phenomenon caused by conduction of the

parasitic PNPN junction (thyristor) contained in the CMOS IC, resulting in a large current between VDD and

VSS and leading to breakage.

Latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows

into the internal element, or when the voltage at the VDD pin exceeds the rated value and the internal element is

in the breakdown condition. In the latter case, even if the application of a voltage exceeding the rated value is

instantaneous, the current remains high between VDD and VSS once the device is in the latch-up condition. As

this may result in heat generation or smoking, the following points must be taken into consideration:

(1) The voltage level at the input / output must not exceed the range specified in the electrical characteristics.

In other words, it must be below the power-supply voltage and above VSS. The power-on timing should also

be taken into consideration.

(2) Abnormal noise must not be applied to the device.

(3) The potential at the unused input should be fixed at VDD, VDDE, TMVDD, AVDD, or VSS.

(4) No outputs should be shorted.

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MAP

I.5 Memory Map

Figure I.5.1 shows a memory map of the entire physical address space of the S1C33401. Figure I.5.2 shows a

memory map of internal memory and the internal I/O space of the S1C33401.

Area 13 0x02FF FFFF

0x0200 0000

Area 12 0x01FF FFFF

0x0180 0000

Area 11 0x017F FFFF

0x0100 0000

Area 10 0x00FF FFFF

0x00C0 0000

Area 9 0x00BF FFFF

0x0080 0000

Area 8 0x007F FFFF

0x0060 0000

Area 7 0x005F FFFF

0x0040 0000

Area 6 0x003F FFFF

0x0030 0000

Extended I/O

(RTC, etc.)

(Reserved for

extended I/O)

Area 5 0x002F FFFF

0x0020 0000

Area 4 0x001F FFFF

0x0010 0000

Area 3 0x000F FFFF

0x0008 0000

Internal RAM area

Area 2 0x0007 FFFF

0x0006 0000

Reserved

for debugging

Area 1 0x0005 FFFF

0x0002 0000

Internal I/O

256K bytes

Area 0 0x0001 FFFF

0x0000 0000

Area 22 0xFFFF FFFF

0x8000 0000

Area 21 0x7FFF FFFF

0x4000 0000

Area 20 0x3FFF FFFF

0x2000 0000

Area 19 0x1FFF FFFF

0x1000 0000

Area 18 0x0FFF FFFF

0x0C00 0000

Area 17 0x0BFF FFFF

0x0800 0000

Area 16 0x07FF FFFF

0x0600 0000

Area 15 0x05FF FFFF

0x0400 0000

Area 14 0x03FF FFFF

0x0300 0000

Internal RAM area

External Memory

16M bytes

External Memory

8M bytes

External Memory

8M bytes

External Memory

4M bytes

External Memory

4M bytes

External Memory

2M bytes

External Memory

2M bytes

External Memory

1M bytes

External Memory

1M bytes

External Memory

2G bytes

External Memory

1G bytes

External Memory

512M bytes

External Memory

256M bytes

External Memory

64M bytes

External Memory

64M bytes

External Memory

32M bytes

External Memory

32M bytes

External Memory

16M bytes

#CE10

#CE11

#CE10

#CE9

#CE8

#CE7

#CE6

#CE5

#CE4

#CE9

#CE8

#CE10

#CE7

#CE6

#CE5

#CE4

(Reserved)

Internal Areas External Areas

Usable as memory space

for SmartMedia (NAND flash),

CompactFlash, or PC Card.

Figure I.5.1 General Memory Map

I S1C33401 SPECIFICATIONS: MEMORY MAP

I-5-2 EPSON S1C33401 TECHNICAL MANUAL

Area 2 0x0007 FFFF

0x0006 0000

Reserved

for debugging

Area 0 0x0001 FFFF

0x0000 8000

0x0000 7FFF

0x0000 0000

A0RAM (32KB)

(Reserved)

Area 3 0x000F FFFF

0x0008 0400

0x0008 03FF

0x0008 0000

A3RAM (1KB)

(Reserved)

Area 1 0x0005 FFFF

0x0004 9000

0x0004 8FFF

0x0004 8000

0x0004 7FFF

0x0004 2000

0x0004 1FFF

0x0004 1000

0x0004 0FFF

0x0004 0000

0x0003 FFFF

0x0003 0000

0x0002 FFFF

0x0002 0000

Area 6 0x003F FFFF

0x0030 2000

0x0030 10FF

0x0030 0000

Extended I/O

(Reserved)

Mirror of internal I/O

(0x40000–0x4FFFF)

8-bit I/O (4KB)

(Reserved)

16-bit I/O (4KB)

Mirror of 16-bit I/O (4KB)

(Reserved)

Extended I/O

0x00301000–0x00301028

0x00300000–0x00300F20

16-bit I/O

0x000483C0–0x400083CC

0x00048380–0x000483A6

0x00048360–0x00048372

0x00048340–0x00048352

0x00048320–0x00048334

0x00048300–0x00048314

0x00048220–0x0004829C

0x00048200–0x00048205

0x00048180–0x000481DE

0x00048160–0x0004816C

0x00048140–0x0004815E

8-bit I/O

0x00040340–0x00040395

0x00040300–0x00040302

0x000402E0–0x000402F4

0x00040260–0x000402AF

0x000401E0–0x000401FF

0x00040180–0x00040188

0x00040160–0x0004017A

0x00040140–0x0004014F

Real Time Clock

Chip ID/Pin Status Control

Extended Bus Control Unit

Basic Bus Control Unit

Clock Management Unit (2)

Cache Control Unit

Memory Management Unit

High-Speed Bus Control Unit

High-Speed DMA

Intelligent DMA

16-bit Timer

Watchdog Timer

A/D Converter

I/O Ports

Card Interface

Debug Unit

Interrupt Controller

Serial Interface

Clock Management Unit (1)

8-bit Timer

Prescaler

Internal Areas

Figure I.5.2 Internal Area Map

The following describes the area configuration of the S1C33401.

For details of the logical space, address processing, and cache operation, see the description of the HBCU, MMU,

and CCU in Chapter II.

For details of area settings and accesses, see the description of the BBCU in Chapter III.

I.5.1 ROM and Boot Address

The S1C33401 does not contain ROM. When the chip is powered on or cold-reset, the boot address is set to

0x20000000 (initial value of TTBR). Therefore, use external ROM or flash memory in Area 20.

I.5.2 Area 0 (A0RAM)

Area 0 contains built-in 32KB high-speed RAM (A0RAM). Its location address ranges from 0x0 to 0x7FFF.

Since A0RAM is accessed directly from the HBCU without BBCU intervention, no wait cycles are inserted.

A0RAM is accessed in one cycle (with no wait cycle), regardless of whether accessed in units of bytes, half-words,

or words.

Moreover, due to a Harvard architecture, A0RAM can be accessed simultaneously with the fetching of instructions

from external memory (cache).

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S1C33401 TECHNICAL MANUAL EPSON I-5-3

MAP

Notes: • A0RAM cannot contain IDMA control words or be specified as the source or destination of

DMA transfer.

• Even when setting up the HBCU to enable the use of low-order 1GB mirror areas, Area 0 is

not mirrored.

• The addresses listed below are reserved for special purposes. If the function of any reserved

area is used, the user program must be prohibited from accessing that area.

0x0–0xF: Reserved for use as MON33 debugging area

0x10–0x1F: Reserved for use as MMU exception area

0x10: MMU exception vector address

0x18: Area in which PC is saved when MMU exception occurs

0x1C: Area in which R0 is saved when MMU exception occurs

I.5.3 Area 1 (Internal I/O)

Area 1 is allocated for the basic internal peripheral circuits of the C33 ADV. Addresses 0x40000 to 0x4FFFF are

used for the control registers, etc.; Addresses 0x30000 to 0x3FFFF are used to mirror said addresses.

The internal I/O area is divided into 4KB of the 8-bit device area (consisting of 0x40000 to 0x40FFF) and 4KB

of the 16-bit device area (consisting of 0x48000 to 0x48FFF). Furthermore, addresses 0x41000 to 0x41FFF are

configured as the mirror of the 16-bit device area. By using this mirror with the base address be set to 0x40000, the

entire internal I/O areas that contains both the 8-bit and 16-bit device areas can be accessed with two instructions (one

basic instruction with one ext instruction).

Area 1 is accessed in at least four cycles.

For details of the basic internal peripheral circuits mapped to this area, see Chapter IV, “C33 ADV Basic Peripheral

Block.” For details of a control register list, see “I/O Map” in the Appendix.

I.5.4 Area 2 (Debug Area)

Area 2 is a debugging-only area allocated for debugging resources. This area can only be accessed for write in

debug mode.

Make sure this area is not accessed from the user program or debugger.

I.5.5 Area 3 (A3RAM)

Area 3 contains built-in 1KB RAM (A3RAM). Its location address ranges from 0x80000 to 0x803FF.

A3RAM is accessed in two cycles (with one wait state, for random access) or one cycle (with no wait states, for

continuous access) from the dedicated interface on the high-speed bus without BBCU intervention.

A3RAM can contain IDMA control words and may also be specified as the source and destination of DMA

transfer.

I.5.6 Area 6 (Extended I/O)

Area 6 is allocated for the chip ID register, pin control registers, and RTC.

For details of how to set up the BBCU to use these registers or functions, see Chapter V, “S1C33401 Area 6

Extended Peripheral Block.”

Area 6 must be set for use as an internal device (by setting up the BBCU) before it can be accessed for these

functions. By switching the settings of this area between internal and external devices, the area may be used for a

combination of said functions and external devices.

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I-5-4 EPSON S1C33401 TECHNICAL MANUAL

I.5.7 External Memory Area

Areas 4 to 20 can be used for external memory and other external devices. Set up the BBCU or EBCU according to

specifications of the devices connected.

Although the internal address and internal data buses of the S1C33401 are both 32 bits wide, the maximum external

data bus width is 16 bits (D[15:0]) and maximum external address bus width is 26 bits (A[25:0]) due to the limited

number of pins available.

I.5.8 Limitations on Areas 0 to 6

Areas 0 to 6 are subject to the following usage limitations:

• Area 0 cannot contain IDMA control words or be specified as the source or destination of DMA transfer.

• Even when setting up the HBCU to enable the use of low-order 1GB mirror areas, Area 0 is not mirrored.

• Access to Areas 0 to 6 cannot be cached.

• Areas 0 to 6 are normally not the target of address conversion by the MMU. However, this 4MB space can be

forcibly made the target of MMU operation as other areas by setting UMDMEN (D1/0x48300) to 1.

∗ UMDMEN: MMU Forced Enable Bit in the Address Control Register (D1/0x48300)

• Areas 0 to 6 are normally not the target of multiplexing operation by using ASID. However, this 4MB space can

be forcibly made the target of multiplexing operation as other areas by setting UMDAEN (D2/0x48300) to 1.

∗ UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300)

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

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I.6 Electrical Characteristics

I.6.1 Absolute Maximum Rating

Item

Internal logic power voltage

PLL power voltage

RTC power voltage

I/O power voltage

P1x I/O power voltage

Analog power voltage

Input voltage

Analog input voltage

High-level output current

Low-level output current

Storage temperature

(VSS=PLLVSS=0V)

Symbol

PLLV

RTCV

DDE

TMV

STG

Rated value

-0.3 to +2.5

-0.3 to +4.0

-0.3 to VDDE+0.5

-0.3 to AVDD+0.3

-10

-40

-65 to +150

Unit

°C

Condition

1 pin

Total of all pins

1 pin

Total of all pins

∗

I.6.2 Recommended Operating Conditions

Item

Internal logic power voltage

PLL power voltage

RTC power voltage

I/O power voltage

P1x I/O power voltage

Analog power voltage

Input voltage

Analog input voltage

CPU operating clock frequency

Bus operating clock frequency

OSC3 oscillation frequency

OSC3 external input clock frequency

OSC1 oscillation frequency

Operating temperature

Input rise time (normal input)

Input fall time (normal input)

Input rise time (Schmitt input)

Input fall time (Schmitt input)

(VSS=PLLVSS=0V)

Symbol

PLLV

RTCV

DDE

TMV

CPU

BUS

OSC3

ECLK3

OSC1

tri

tfi

tri

tfi

Max.

1.95

3.60

VDDE

VDD

AVDD

–

Unit

MHz

kHz

°C

Condition

Typ.

1.80

–

32.768

–

Min.

1.65

2.70

VSS

–

-40

–

∗

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-2 EPSON S1C33401 TECHNICAL MANUAL

I.6.3 DC Characteristics

Item

Input leakage current

Off-state leakage current

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

Positive trigger input voltage

Negative trigger input voltage

Hysteresis voltage

Pull-up resistor

Pull-down resistor

High-level latching current

Low-level latching current

High-level reversal current

Low-level reversal current

Input pin capacitance

Output pin capacitance

I/O pin capacitance

(Unless otherwise specified: V

DDE=TMVDD=2.7V to 3.6V, VDD=1.65V to 1.95V, Ta=-40°C to +85°C)

Symbol

ILI

IOZ

VOH

VOL

VIH

VIL

VT+

VT-

RPU

RPD

IBHH

IBHL

IBHHO

IBHLO

CIO

Max.

–

0.4

–

0.7

2.7

1.8

–

288

144

346

144

-20

–

Unit

µA

kΩ

µA

Condition

IOH=-1.7mA (2mA Type),

IOH=-3.5mA (4mA Type),

VDD=Min.

IOL=1.7mA (2mA Type),

IOL=3.5mA (4mA Type), VDD=Min.

LVTTL level, VDDE=Max.

LVTTL level, VDDE=Min.

LVCMOS Schmitt

VI=0V 100kΩ Type

50kΩ Type

VI=VDDE 120kΩ Type

50kΩ Type

Pins with bus-hold latch, VI=1.9V, VDDE=Min.

Pins with bus-hold latch, VI=0.8V, VDDE=Min.

Pins with bus-hold latch, VI=0.8V, VDDE=Max.

Pins with bus-hold latch, VI=1.9V, VDDE=Max.

f=1MHz, VDDE=0V

Typ.

–

100

120

–

Min.

-5

VDD

-0.4

–

2.0

–

1.2

0.5

0.2

–

-350

300

–

∗

Note: See Section I.3.4, “Input/Output Cells and Input/Output Characteristics,” for pin characteristics.

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

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I.6.4 Current Consumption

Operating current

Item

Current consumption during

CPU running (cache off)

Current consumption during

CPU running (cache on)

Current consumption

in HALT mode

Current consumption

in HALT2 mode

(Unless otherwise specified: VDDE=3.3V, VDD=1.8V, VSS=0V, Ta=25°C)

Symbol

IDD1

IDD2

IDD3

IDD4

Max.

–

Unit

Condition

30MHz

50MHz

66MHz

30MHz

50MHz

66MHz

30MHz

50MHz

66MHz

30MHz

50MHz

66MHz

Typ.

Min.

–

∗

Current consumption measurement condition: VIH=VDDE, VIL=0V, output pins are open, VDD power current only

Typ. value measurement condition: VDDE=AVDD=3.3V, VDD=1.8V, Ta=25°C Typ. sample

∗ note)

No.

OSC3

OSC1

Off

CPU

Normal operation ∗1

HALT mode

HALT2 mode

Other peripheral circuits

Cache off, peripheral circuits off/PCLK supply off

Cache on, peripheral circuits off/PCLK supply off

Peripheral circuits off/PCLK supply off

∗1: The values of current consumption while the CPU is operating were measured when a JPEG encode

program was being executed in an external SRAM.

The following shows the number of external SRAM access cycles corresponding to each operating

frequency:

30MHz: 3 cycles (100ns)

50MHz: 5 cycles (100ns)

66MHz: 7 cycles (105ns)

Current consumption in SLEEP mode

Item

VDD current consumption

in SLEEP mode

VDDE + AVDD

current consumption

in SLEEP mode

(Unless otherwise specified: VDDE=3.3V, VDD=1.8V, VSS=0V, Ta=25°C)

Symbol

IDDSL

IDDSE

Max.

–

Unit

µA

Condition

Ta=25°C

Ta=85°C

Ta=25°C

Ta=85°C

Typ.

Min.

–

∗

Current consumption measurement condition: VIH=VDDE, VIL=0V, output pins are open

Typ. value measurement condition: VDDE=AVDD=3.3V, VDD=1.8V, Ta=25°C Typ. sample

Peripheral circuit operating currents

Item

RTC operating current

A/D converter operating current

OSC3 operating current

PLL operating current

SSCG operating current

(Unless otherwise specified: VDDE=AVDD=3.3V, VDD=RTCVDD=PLLVDD=1.8V, VSS=0V, Ta=25°C)

Symbol

IRTC

IAD

IOSC3

IPLL

ISSCG

Max.

–

Unit

µA

Condition

OSC1 oscillation: 32kHz

When A/D converter is enabled

OSC3 oscillation: 33MHz

PLL output clock: 50MHz

SSCG input clock: 50MHz

Typ.

300

0.6

0.4

Min.

–

∗

∗ note 5) RTCVDD power current consumption

6) AVDD power current consumption

7) VDD power current consumption

8) PLLVDD power current consumption

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-4 EPSON S1C33401 TECHNICAL MANUAL

I.6.5 A/D Converter Characteristics

Item

Resolution

Conversion time

Zero scale error

Full scale error

Integral linearity error

Differential linearity error

Permissible signal source impedance

Analog input capacitance

(Unless otherwise specified: VDDE=AVDD=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40°C to +85°C, ST[1:0]=11)

Symbol

–

Max.

–

1250

Unit

bit

µs

LSB

kΩ

Condition

Typ.

–

Min.

–

-2

-3

–

∗

∗ note 1) Indicates the minimum value when A/D clock = 2MHz.

Indicates the maximum value when A/D clock = 16kHz.

A/D conversion error

V[001]h = Ideal voltage at zero-scale point (=0.5LSB)

V'[001]h = Actual voltage at zero-scale point

V[3FF]h = Ideal voltage at full-scale point (=1022.5LSB)

V'[3FF]h = Actual voltage at full-scale point

1LSB =

1LSB' =

AVDD - VSS

210 - 1

V'[3FF]h - V'[001]h

210 - 2

V'[001]h

3FF

3FE

3FD

003

002

001

000VSS AVDD

Integral linearity error EL = [LSB]

VN' - VN

1LSB'

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

V'[3FF]h

V'[N]h

V'[N-1]h

N+1

N-1

N-2

Integral linearity error

Differential linearity error

Differential linearity error ED = - 1 [LSB]

V'[N]h - V'[N-1]h

1LSB'

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

V[001]h

(=0.5LSB)

V'[001]h

004

003

002

001

000

VSS

Zero scale error

Zero scale error EZS = [LSB]

(V'[001]h - 0.5LSB') - (V[001]h - 0.5LSB)

1LSB

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

V[3FF]h (=1022.5LSB)

V'[3FF]h

3FF

3FE

3FD

3FC

3FB

AVDD

Full scale error

Full scale error EFS = [LSB]

(V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB)

1LSB

Digital output (hex)

Analog input

Ideal conversion characteristic

Actual conversion characteristic

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

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I.6.6 Oscillation Characteristics

Oscillation characteristics change depending on conditions such as components used (oscillator, Rf, Rd, CG, CD)

and board pattern. Use the following characteristics as reference values. In particular, when a ceramic or crystal

oscillator is used, evaluate the components adequately under real operating conditions by mounting them on the

board before the external register (Rf, Rd) and capacitor (CG, CD) values are finally decided.

OSC1 crystal oscillation

Item

Oscillation start time

(Unless otherwise specified: RTCVDD=1.65V to 1.95V, VSS=0V, Ta=25°C)

Symbol

tSTA1

Max.

Unit

Condition

Typ.

Min. ∗

OSC3 crystal/ceramic oscillation

Note: A “crystal resonator that uses a fundamental” should be used for the OSC3 crystal oscillation

circuit.

Item

Oscillation start time

(Unless otherwise specified: VDD=1.65V to 1.95V, VSS=0V,

Ta=25°C)

Symbol

tSTA3

Max.

Unit

Condition

Typ.

Min.

∗

Recommended OSC3 ceramic resonators

Frequency

[MHz]

Ceramic resonator

product number (SMD type)

CSTCR5M00G55-R0

CSTCE10M0G55-R0

CSTCE20M0V53-R0

CSTCG33M0V51-R0

CSTCW33M0X51-R0

CG2 [pF]

(39)

(33)

(15)

(5)

(6)

CD2 [pF]

(39)

(33)

(15)

(5)

(6)

Rf [Ω]

33k

Rd [Ω]

Recommended component values Remarks

Ceramic resonators

manufactured by Murata

Manufacturing Co., Ltd.

note) CST∗∗ indicates the product that has built-in load capacitances (CG2, CD2).

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-6 EPSON S1C33401 TECHNICAL MANUAL

I.6.7 PLL Characteristics

Item

Input frequency

Output frequency

Multiplying factor

Output stabilization time

(Unless otherwise specified: PLLVDD=1.65V to 1.95V, PLLVSS=0V, Ta=-40°C to +85°C)

Symbol

fPLLIN

fPLLOUT

tPLL

Max.

200

Unit

MHz

times

µs

Condition

Typ.

Min.

∗

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

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I.6.8 AC Characteristics

I.6.8.1 Symbol Description

tCYC: Bus-clock cycle time

Indicates the cycle time of the bus clock.

I.6.8.2 AC Characteristics Measurement Condition

Signal detection level: Input signal High level VIH = VDDE - 0.4 V

Low level VIL = 0.4 V

Output signal High level VOH = 1/2 VDDE

Low level VOL = 1/2 VDDE

The following applies when OSC3 is external clock input:

Input signal High level VIH = 1/2 VDD

Low level VIL = 1/2 VDD

Input signal waveform: Rise time (10% → 90% VDD) 5 ns

Fall time (90% → 10% VDD) 5 ns

Output load capacitance: Pins other than SDCLK: CL = 50 pF

SDCLK pin: CL = 20 pF

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-8 EPSON S1C33401 TECHNICAL MANUAL

I.6.8.3 BBCU AC Characteristic Tables

External clock input characteristics

(Note) These AC characteristics apply to input signals from outside the IC.

The OSC3 input clock must be within VDD to VSS voltage range.

Item

High-speed clock cycle time

OSC3 clock input duty

OSC3 clock input rise time

OSC3 clock input fall time

BCLK high-level output delay time

BCLK low-level output delay time

(Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40°C to +85°C)

Symbol

tC3

tC3ED

tIF

tIR

tCD1

tCD2

Max.

500

Unit

Min.

∗

BCLK clock output characteristics

(Note) These AC characteristic values are applied only when the high-speed oscillation circuit is used.

Item

BCLK clock output duty

(Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40°C to +85°C)

Symbol

tCBD

Max.

Unit

Min.

∗

Bus access cycle

Item

Address delay time

#CEx delay time (1)

#CEx delay time (2)

Wait setup time

Wait hold time

Read signal delay time (1)

Read signal delay time (2)

Read data setup time

Read data hold time

Write signal delay time (1)

Write signal delay time (2)

Write data delay time (1)

Write data hold time

(Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40°C to +85°C)

Symbol

tAD

tCE1

tCE2

tWTS

tWTH

tRDD1

tRDD2

tRDS

tRDH

tWRD1

tWRD2

tWDD1

tWDH

Max.

–

Unit

Min.

–

∗

∗ note 1) This applies to the #BSH and #BSL timings.

When the RD start state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge.

When the WR start state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge.

When the WR end state -0.5 clock option is enabled, this value is the delay time from the BCLK falling edge.

External bus master

Item

#BUSREQ signal setup time

#BUSREQ signal hold time

#BUSACK signal output delay time

(Unless otherwise specified: VDDE=2.7V to 3.6V, VDD=1.65V to 1.95V, VSS=0V, Ta=-40°C to +85°C)

Symbol

tBRQS

tBRQH

tBAKD

Max.

Unit

Min.

∗

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I.6.8.4 BBCU AC Characteristic Timing Charts

Clock

OSC3

(High-speed clock)

tC3

BCLK

(Clock output)

tC3 (tCYC)

tC3H

tC3ED = tC3H/tC3

tCBD = tCBH/tCYC

BCLK

(Clock output)

tCYC

tCBH

tCD1 tCD2

tIF tIR

(1) When an external clock is input:

(2) When the high-speed oscillation circuit is used for the operating clock:

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-10 EPSON S1C33401 TECHNICAL MANUAL

SRAM read cycle

[Condition] Access cycle multiply-by factor: x1 Access-disable cycle: 1 clock

CE cycle: 3 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Disabled

RD end state: 1 clock

RD start Wait cycle

CE cycle

RD end Output disableAccess disable

BCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

ASTB

#WAIT

tCYC

tAD tAD

valid

tCE1 tCE2

valid

tRDD1 tRDD2

tRDS tRDH

tWTS tWTStWTH tWTH

SRAM write cycle

[Condition] Access cycle multiply-by factor: x1 Access-disable cycle: 1 clock

CE cycle: 3 clocks WR start state -0.5 clock option: Disabled

WR start state: 1 clock WR end state -0.5 clock option: Disabled

WR end state: 1 clock

WR start Wait cycle

CE cycle

WR end Access disable

BCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

ASTB

#WAIT

tCYC

tAD tAD

valid

tCE1 tCE2

tWDH

valid

tWRD1

tWDD1

tWRD2

tWTS tWTStWTH tWTH

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Burst ROM read cycle

[Condition] Access cycle multiply-by factor: x1 Access-disable cycle: 1 clock

CE cycle: 3 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Disabled

RD end state: 1 clock

RD start Page read cycle

CE cycle

RD end Output disableAccess disablePage read cycle Page read cycle

∗1

BCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

ASTB

tCYC

tAD

tAD tAD tAD tAD

tAD

valid

00 01 10 11

tCE1 tCE2

tAD

valid

tRDD1 tRDD2

tRDS

tRDH tRDH tRDH tRDH

tRDS tRDS

valid valid valid

∗1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and A[31:0]

signals.

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-12 EPSON S1C33401 TECHNICAL MANUAL

#BUSREQ, #BUSACK timing

BCLK

#BUSREQ

#BUSACK

tBRQS

Valid input

tBRQH

tBAKD

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I.6.8.5 SDRAM Interface AC Characteristics

SDRAM access cycle

Item

Command, address, write data setup time

Command, address, write data hold time

Read data setup time (1)

Read data setup time (2)

Read data hold time

(Unless otherwise specified: VDDE=3.0V to 3.6V, VDD=1.65V to 1.95V, Ta=-40°C to +85°C)

Symbol

tSS

tSH

tRDS1

tRDS2

tRDH

Max.

–

Unit

Min.

2.5

8.5

∗

∗ note 1) When SDCLK = CCLK × 1/1

2) When SDCLK = CCLK × 1/2, 1/4, or 1/8

I S1C33401 SPECIFICATIONS: ELECTRICAL CHARACTERISTICS

I-6-14 EPSON S1C33401 TECHNICAL MANUAL

[Condition] CAS latency = 2, Single read/write

Read cycle Write cycle

∗1: SDRAM internal precharge

tRDH

tRDS1

tRDS2

(write)

(read)

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[15:0]

RASa

0xF

CAS

0x0

RASa CAS

0x0

0xF 0xF

ACT

BANK0 BANK1

tSH tSS

tSH

tSS

tSS tSS

tSS

tSH tSS

tSH

tSS

tSH tSH

tSH

RASa RASa

valid valid

tSH tSS

tSH tSS tSH tSS

tSH tSS

tSH tSS tSH

tSS tSS

tSH

tSS tSS

tSH

tSH tSS

tSH

tSH tSS

tSH

tSS tSH

tSS

tSH

tSS tSS

tSH

tSS

tSH

tSH tSS tSH tSS tSH tSS tSH tSS

tSH tSS tSH tSS

tSH tSS

READA ∗1ACT ACT

WRITA ∗1

* Also when other SDRAM control commands including refresh are output, the output signals will be effective during the periods from the setup time tSS before the SDCLK rising

edge to the hold time tSH after the SDCLK rising edge.

I S1C33401 SPECIFICATIONS: BASIC EXTERNAL WIRING DIAGRAM

S1C33401 TECHNICAL MANUAL EPSON I-7-1

Wiring

I.7 Basic External Wiring Diagram

X'tal1

CG1

CD1

Rf1

Rd1

X'tal2

CG2

CD2

Rf2

Rd2

Crystal oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Drain resistor

Crystal oscillator

Ceramic oscillator

Gate capacitor

Drain capacitor

Feedback resistor

Drain resistor

32.768 kHz

10 pF

10 MΩ

0 Ω

33 MHz (Max.)

10 pF

1 MΩ

0 Ω

Note: The above table is simply an example, and is not guaranteed to work.

S1C33401

[The potential of the substrate

(back of the chip) is VSS.]

External

Bus

HSDMA

Serial I/O

A/D input

I/O

Timer

input/output

A[25:0]

D[15:0]

#RD

#WRL

#WRH

#BSL

#CExx

#WAIT

#BUSREQ

#BUSACK

#BUSGET

ACST

ASTB

R/W

CMU_CLK/BCLK

PSC_CLK

WDT_CLK

#NMI

SDCLK

SDCKE

DQMH

DQML

#SDCS

#SDRAS

#SDCAS

#SDWE

#SMRD

#SMWR

#IOWR

#IORD

#OE

#WE

#CFCE1

#CFCE2

#DMAREQx

#DMAACKx

#DMAENDx

SINx

SOUTx

#SCLKx

#SRDYx

#ADTRG

AINx

EXCLx

TMx

T8UFx

Pxx

SDRAM

Card

Debug

interface

VDD

PLLVDD

RTCVDD

VDDE

TMVDD

AVDD

#STBY

#RESET

OSC3

OSC4

OSC1

OSC2

TST0

TST1

SCANEN

BURNIN

VSS

DSIO

DCLK

DPCO

DST[2:0]

(DBT)

(DTS[4:0])

(DTD[7:0])

1.8 V

3.0/3.3 V

Rd2

Rd1

CD2

X'tal2 or CE

Rf2

CG2

CD1

X'tal1

Rf1

CG1

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Change

I.8 Changes from Core/Basic Peripheral

Functions

In the S1C33401, some standard functions incorporated in the C33 ADV macro are limited or changed as described

in this section. The contents of this manual described in Chapter II, “C33 ADV Core Block,” Chapter III, “C33

ADV Bus Block,” and Chapter IV, “C33 ADV Basic Peripheral Block,” commonly apply to the S1C33-series

microcomputers incorporating the C33 ADV macro. Therefore, be sure to understand the limitations or changes

specific to the S1C33401 described in this section before designing application systems.

I.8.1 Limitations on the BBCU and EBCU

Bus width

The C33 ADV supports 32-bit address and 32-bit data buses. In the S1C33401, the bus widths have been

changed due to the limited number of pins available, as shown below.

Internal address bus: 32 bits (not changed)

Internal data bus: 32 bits (not changed)

External address bus: Up to 26 bits

A0 to A17 are the dedicated address bus pins, whereas A18 to A25 are shared with I/O

ports (P47 to P40). (These pins are set for use as address bus pins by default.)

External data bus: 16 bits

Data bus pins D0 to D15 are available. Therefore, the external devices that can be

connected to the chip are limited to a maximum data width of 16 bits.

BBCU bus control signals

Since the external data bus is 16 bits wide, the pins listed below are nonexistent. The signals, however, are used

for accessing internal devices.

Nonexistent pins: #WRHL, #WRHH

EBCU SDRAM control signals

Since the external data bus is 16 bits wide, the pins listed below are nonexistent.

Nonexistent pins: DQM3, DQM2

I S1C33401 SPECIFICATIONS: CHANGES FROM CORE/BASIC PERIPHERAL FUNCTIONS

I-8-2 EPSON S1C33401 TECHNICAL MANUAL

I.8.2 Limitations on the A/D Converter

The A/D converter of the C33 ADV macro can handle analog inputs on up to eight channels. In the S1C33401,

however, only four channels (AIN0–AIN3) are supported. Although the control registers and control circuits for

eight channels are incorporated, conversion results on AIN4 to AIN7 have no effect.

Internal data bus

AVDD

Analog

input

decoder

Control circuit

AIN0

AIN1

AIN2

AIN3

(AIN4)

(AIN5)

(AIN6)

(AIN7)

#ADTRG

8-bit timer 0

16-bit timer 0

CMU

Prescaler Interrupt request

A/D converter input clock

Can be used in advanced mode

Conversion

completed

Out of

range

Analog

block

Successive

approximation

block

Data

Interrupt

control circuit

Control

registers

Ch0–Ch7

conversion

result buffers

Upper-limit/

lower-limit value

registers

Comparator

Figure I.8.2.1 A/D Converter in the S1C33401

Invalid control bits

The control bits shown below are ineffective.

OWE[7:4] (D[15:12]/0x48146)

ADF[7:4] (D[7:4]/0x48146)

AD4BUF[9:0] (D[9:0]/0x48150)

AD5BUF[9:0] (D[9:0]/0x48152)

AD6BUF[9:0] (D[9:0]/0x48154)

AD7BUF[9:0] (D[9:0]/0x48156)

Note: The control bits below are used to mask interrupts on each channel individually. To avoid

unnecessary interrupts from nonexistent channels, be sure to set these bits to 0 (initially set to 1).

INTMASK[7:4] (D[7:4]/0x4815C) = 0b0000

Control bits whose settings are limited

The control bits below are used to specify channel numbers. Although numbers 0 to 7 can be specified, only

numbers 0 to 3 are effective in the S1C33401. If numbers 4 to 7 are specified, the conversion results are not

effective.

CE[2:0] (D[13:11]/0x48142)

CS[2:0] (D[10:8]/0x48142)

ADCMP[2:0] (D[14:12]/0x48144)

I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING

S1C33401 TECHNICAL MANUAL EPSON I-9-1

Mount

I.9 Precautions on Mounting

The following shows the precautions when designing the board and mounting the IC.

Oscillation Circuit

• Oscillation characteristics change depending on conditions such as components used (oscillator, Rf, Rd, CG,

CD) and board pattern. In particular, when a ceramic or crystal oscillator is used, evaluate the components

adequately under real operating conditions by mounting them on the board before the external register (Rf, Rd)

and capacitor (CG, CD) values are finally decided.

• Disturbances of the oscillation clock due to noise may cause a malfunction. To prevent this, the following

points should be taken into consideration. In particular, the latest devices are more sensitive to noise, as they are

more finely processed.

The measures against noise for the OSC2 pin, and the components and lines connected to this pin is most

essential, and similar measures must also be taken for the OSC1 pin. The measures for the OSC1 and OSC2

pins are described below.

We recommend taking measures similar to those for the high-speed oscillation system, including the OSC3 and

OSC4 pins and the components and lines connected to these pins.

(1) Components that are connected to the OSC1 and OSC2 pins, such as oscillators, resistors, and capacitors,

should be connected in the shortest line.

(2) Whenever possible, configure digital signal lines with at least three millimeters clearance from the OSC1

and OSC2 pins and the components and lines connected to these pins. In particular, signals that are

switched frequently must not be placed near these pins, components, and lines. The same applies to all

layers on the multi-layered board as the distance between the layers is around 0.1 to 0.2 mm.

Furthermore, do not configure digital signal lines in parallel with these components and lines when

arranging them on the same or another layer of the board. Such an arrangement is strictly prohibited,

even with clearance of three millimeters or more. Also, avoid arranging digital signal lines across these

components and signal lines.

(3) Shield the OSC1 and OSC2 pins and lines connected to those pins as

well as the adjacent layers of the board using VSS.

As shown in the figure on the right, shield the wired layers as much as

possible.

Whenever possible, make the whole adjacent layers the ground layers,

or ensure there is adequate shielding to a radius of five millimeters

around the above pins and lines.

As described in (2), do not configure digital signal lines in parallel with

components and lines even if such precautionary measures are taken,

and avoid configuring signal lines that are switched frequently across

components and lines on other layers.

(4) When an external clock is supplied to the OSC1 or OSC3 pin, the clock source should be connected to the

OSC1 or OSC3 pin in the shortest line. Furthermore, do not connect anything else to the OSC2 or OSC4

pin.

(5) After taking the above precautions, check the output clock waveform while operating the actual application

program in the actual device.

To do this, measure the output of the CMU_CLK pins with an oscilloscope.

Check the waveform quality at the OSC3 or PLL output clock by measuring the CMU_CLK output. Ensure

that the frequencies are as designed and that there is no noise or jitters.

Check the waveform quality at the OSC1 clock by measuring the CMU_CLK output (after switching the

system clock source to OSC1). Scale up the ranges around the rising and falling edges of the clock pulse to

ensure that there is no noise, such as clock and spike, in the 100 ns ranges.

OSC2

OSC1

VSS

Sample VSS pattern

OSC1 and OSC2

I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING

I-9-2 EPSON S1C33401 TECHNICAL MANUAL

If conditions (1) to (3) are not satisfied, the OSC3 or PLL output may be jittery and the OSC1 output may

be noisy. When the OSC3 or PLL output is jittery, the operating frequency will be lowered. When the OSC1

output is noisy, operation of the timer using the OSC1 clock and the CPU core after the system clock is

switched to the OSC1 pin will be unstable.

Reset Circuit

• The power-on reset signal which is input to the #RESET pin changes depending on conditions (power rise time,

components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests

have been completed with the application product.

• In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components

such as capacitors and resistors should be connected to the #RESET pin in the shortest line.

Power Supply Circuit

• Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent

this:

(1) The power supply should be connected to the VDD, VDDE, VSS, AVDD, TMVDD, RTCVDD, PLLVDD and

PLLVSS pins with patterns as short and large as possible. In particular, the power supply for AVDD affects

A/D conversion precision.

(2) When connecting between the VDD and VSS pins with a bypass capacitor, the pins should be connected as

short as possible.

VDD

VSS

Bypass capacitor connection example

VDD

VSS

A/D Converter

• When the A/D converter is not used, the power supply pin AVDD for the analog system should be connected to

VDDE.

Arrangement of Signal Lines

• In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a

large current signal line near the circuits that are sensitive to noise such as the oscillation unit and analog input

unit.

• When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may

generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-

speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input

unit.

P70 (AIN0)

Large current signal line

High-speed signal line

OSC2, OSC4

OSC1, OSC3

VSS

Large current signal line

High-speed signal line

Prohibited pattern

I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING

S1C33401 TECHNICAL MANUAL EPSON I-9-3

Mount

Noise-Induced Erratic Operations

If erratic IC operations appear to be attributable to noise, consider the following five points.

(1) TST0 and TST1 pins

If these pins are exposed to high-level noise, the entire IC enters test mode or a high-impedance state and

becomes inoperable. In such cases, the IC will not be restored, even when the pin is returned to a low level.

Therefore, always make sure the TST0 and TST1 pins are connected to GND on the circuit board. Although

the IC contains internal pull-down resistors, it is susceptible to noise because these resistors are high

impedance (approximately 50 to 100 kΩ).

(2) DSIO pin

Exposure of this pin to low-level noise causes the IC to enter debug mode. In debug mode, the clock is

output from the DCLK pin and the DST2 pin is high, indicating that the IC is in debug mode.

In product versions, it is recommended that the DSIO pin be pulled high by connecting it directly to VDD or

through a resistor of 10 kΩ or less.

Although the IC contains internal pull-up resistors, it is susceptible to noise because these resistors are high

impedance (approximately 50 to 100 kΩ).

For details, refer to the “S1C33 Family Application Note.”

(3) #RESET pin

Low-level noise on this pin resets the IC. However, the IC may not always be reset normally, depending on

the input waveform.

Due to circuit design, this situation tends to occur when the reset input is in the high state, with high

impedance. For details, refer to the “S1C33 Family Application Note.”

(4) #NMI pin

Low-level noise on this pin causes an NMI interrupt. Due to the circuit design, this situation tends to occur

when the #NMI pin is in the high state, with high impedance. Lower the impedance of #NMI when it is

held high, or incorporate corrective measures into the software to protect against erratic operations.

(5) VDD, VSS, and VDDE power supplies

If noise lower than the rated voltage enters one of these power-supply lines, the IC may operate erratically.

Take corrective measures in board design; for example, by using solid patterns for power supply lines,

adding decoupling capacitors to eliminate noise, or incorporating surge/noise counteracting devices into the

power supply lines.

To confirm the above, use an oscilloscope capable of observing higher-frequency waveforms of 200 MHz. The

generation of fast noise may not be observed with a low-frequency oscilloscope.

If potential noise-induced erratic operations are detected through waveform observations using an oscilloscope,

connect the suspected pin to the GND or power supply with low impedance (1 kΩ or less) and check once

again. If erratic operations are no longer detected or occur at reduced frequency, or if different symptoms of

erratic operations are observed, said pin may with reasonably certainty be considered to be the source of the

erratic operations.

The TST0, TST1, DSIO, #RESET, and #NMI input circuits described above are designed to detect the edges

of the input signal (#NMI can be changed to level sense mode), so that even spike noise may result in erratic

operations. Among the digital signal circuits, these pins are most susceptible to noise.

In the design of the circuit board, take the following two points into consideration to protect the signal from

noise.

(A) The most important measure is to lower the signal-driving impedance, as described in each item above.

Connect pins to the power supply or GND, with impedance of 1 kΩ or less, preferably 0 Ω. In addition,

limit the length of the connected signal lines to approximately 5 cm.

(B) Parallel routing of said signal lines with other digital lines on the board is undesirable, since the noise

generated when the signal changes from high to low or vice versa may adversely affect signals. The signal

may be subject to the most noise when signal lines are laid between multiple signal lines whose states

change simultaneously. Take corrective measures by shortening the parallel distance (to several cm) or

separating signal lines (2 mm or more).

I S1C33401 SPECIFICATIONS: PRECAUTIONS ON MOUNTING

I-9-4 EPSON S1C33401 TECHNICAL MANUAL

Reference

Refer to Chapter 4, “The Basic S1C33 Chip Board Circuit,” in the “S1C33 Family Application Note” for more

detailed precautions on the power supply, oscillation, reset, memory, port, and debug.

Other

The 0.18 µm fine-pattern process is employed to manufacture this series of products.

Although the product is designed to meet EIAJ and MIL standards regarding basic IC reliability, please pay

careful attention to the following points when actually mounting the chip on a board.

Since all OSC pins are constructed to use the internal 0.18 µm transistors directly, the pins are susceptible

to mechanical damage during the board-mounting process. Moreover, the pins may also be susceptible to

electrical damage caused by such disturbances (listed below) whose electrical strength, varying gradually with

time, could exceed the absolute maximum rated voltage (2.5 V) of the IC:

(1) Electromagnetic induction noise from the utility power supply in the reflow process during board-mounting,

rework process after board-mounting, or individual characteristic evaluation (experimental confirmation),

and

(2) Electromagnetic induction noise from the tip of a soldering iron

Especially when using a soldering iron, make sure that the IC GND and soldering iron GND are at the same

potential before soldering.

S1C33401 Technical Manual

II C33 ADV CORE BLOCK

II C33 ADV CORE BLOCK: PREFACE

S1C33401 TECHNICAL MANUAL EPSON II-1-1

Preface

II.1 Preface

The C33 ADV Core Block consists of seven unit blocks.

C33 ADV CPU

HBCU

Oscillators/PLL

CCU

MMU

CMU

DBG

EBCU

(SDRAM Controller)

DMA

Peripheral

module

BBCU

(SRAM Controller)

A3RAM

(Area 3 RAM)

Bridge

A0RAM

(Area 0 No-Wait RAM)

Peripheral

module

Peripheral

module

Peripheral

module

C33 ADV Core Block

S1C33 Microcomputer

Bus Control Block

Peripheral Block

Extended Peripheral Block

Figure II.1.1 C33 ADV Core Block

II C33 ADV CORE BLOCK: PREFACE

II-1-2 EPSON S1C33401 TECHNICAL MANUAL

CPU 32-bit RISC-type CPU C33 ADV

CMU Clock Management Unit

Controls the oscillator circuit, PLL, and SSCG to generate the operating clock for the core block and

peripheral circuits, and an external bus clock. It also controls per-module clock supply on/off, external

reset/NMI input, and standby mode.

HBCU High-speed Bus Control Unit

Connected directly to the CPU; controls the MMU, CCU, internal memory (A0RAM), and internal

high-speed bus of the chip.

MMU Memory Management Unit

When the CPU accesses logical address space, this unit translates it into physical address at high speed.

CCU Cache Control Unit

Controls the 8KB instruction/data mixed-type cache.

DBG Debug Unit

This circuit is provided for debugging programs using the S5U1C33000H/S5U1C33001H (In-Circuit

Debugger for the S1C33 Family).

A0RAM Area 0 No-Wait RAM

For the standard S1C33 ADV models, a high-speed RAM is embedded in area 0. The RAM can be

accessed with no wait cycle inserted.

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-1

CPU

II.2 CPU

The C33 ADV Core CPU is a high-end RISC computer in the S1C33 series of Seiko Epson 32-bit microcomputers

featuring the extended functionality of the instruction set, with new instructions added, low power consumption,

and high processing speed.

The C33 ADV Core CPU includes as standard features the multiplier and the multiply-accumulate instructions that

conventionally were available as options in the S1C33 series. Combined with the newly added instructions, they

will help to accomplish multimedia-related processing easily.

What’s more, when the C33 ADV Core CPU is combined with a Memory Management Unit (MMU) and a Cache

Control Unit (CCU) to configure the CPU core, even faster and more advanced processing will be made possible.

As the C33 ADV Core CPU is upward object-code compatible with the C33 STD Core CPU, the software assets of

the user that have been amassed in the past can be effectively utilized.

II.2.1 Features

Processor type

• Seiko Epson original 32-bit RISC CPU

• 32-bit internal data processing

• Contains a 32-bit × 16-bit multiplier

Operating-clock frequency

• DC to 66 MHz (depending on the processor model)

Instruction set

• Instruction set useful for multimedia processing

• Code length 16-bit fixed length

• Number of instructions 164

• Execution cycle Main instructions executed in one cycle

Two to three instructions (including immediate-extended instructions) can

be executed in one clock cycle

• Extended immediate instructions Immediate extended up to 32 bits

Multimedia features

• Multiplication instructions Multiplications for 16 × 16, 32 × 16, and 32 × 32 bits supported

• Multiply-accumulate instructions Step/continuous multiply-accumulate operations for 16 × 16, 32 × 16, and

32 × 32 bits supported

• Loop instruction Specified range executed repeatedly

• Repeat instruction One instruction executed repeatedly

• Saturation instruction Rounded to minimum/maximum values

• Postshift function ALU instruction execution with postshift supported

• 32-bit general-purpose registers 16

• 32-bit special registers 15

• 32-bit multiply-accumulate operation registers 2 (included in the above special registers)

Memory space and external bus

• Instruction, data, and I/O coexisting linear space

• Up to 4G bytes of memory space

• Little endian format (can be switched to big endian)

II C33 ADV CORE BLOCK: CPU

II-2-2 EPSON S1C33401 TECHNICAL MANUAL

Interrupts

• Reset, NMI, and 128 external interrupts supported

• Four software exceptions

• Two instruction execution exceptions

• Direct branching from vector table to interrupt handler routine

• MMU exception

Reset

• Cold reset (all internal circuits reset)

• Hot reset (CPU TTBR register and port statuses retained)

Power-down mode

• HALT mode (only the ADV core turned off)

• HALT2 mode (ADV core, BBCU, EBCU, and DMA turned off)

• SLEEP mode (circuits other than RTC turned off)

Other

• MMU supported

• Caches supported

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-3

CPU

II.2.2 Registers

The C33 ADV Core CPU contains 16 general-purpose registers and 15 special registers.

R15

R14

R13

R12

R11

R10

R4 (ALR)

R5 (AHR)

bit 31 bit 0

General-purpose registers

USP

TTBR

LEA

SOR

SSP

bit 31

#15

#14

#13

#11

#10

#15

#14

#13

#12

#11

#10

bit 0

LSA

LCO

AHR

ALR

PSR

IDIR

DBBR

Special registers

Figure II.2.2.1 Registers

Table II.2.2.1 Register Access Rights

symbol

SSP ∗1

USP ∗1

DBBR ∗1

IDIR ∗1

DP ∗1

TTBR ∗1

SOR ∗1

LEA ∗1

LSA ∗1

LCO ∗1

AHR

ALR

SP ∗2

PSR

Name

Program counter

Supervisor stack pointer

User stack pointer

Debug base register

CPU identification register

Data pointer

Trap table base register

Shift out register

Loop end address register

Loop start address register

Loop count register

Arithmetic-operation high register

Arithmetic-operation low register

Stack pointer

Processor status register

Supervisor

mode

R/W

User

mode

R/W

∗3

∗1 New registers added to the C33 ADV Core CPU

∗2 When the SP register is referenced, either SSP or USP is referenced.

∗3 Some bits in the PSR cannot be accessed for writing in user mode.

II C33 ADV CORE BLOCK: CPU

II-2-4 EPSON S1C33401 TECHNICAL MANUAL

II.2.3 Instruction Set

Table II.2.3.1 S1C33-Series-Compatible Instructions

Classification

Arithmetic operation

Branch

Function

Addition between general-purpose registers

Addition of a general-purpose register and immediate

Addition of SP and immediate (with immediate zero-extended)

Addition with carry between general-purpose registers

Subtraction between general-purpose registers

Subtraction of general-purpose register and immediate

Subtraction of SP and immediate (with immediate zero-extended)

Subtraction with carry between general-purpose registers

Arithmetic comparison between general-purpose registers

Arithmetic comparison of general-purpose register and immediate

(with immediate zero-extended)

Signed integer multiplication (16 bits × 16 bits → 32 bits)

Unsigned integer multiplication (16 bits × 16 bits → 32 bits)

Signed integer multiplication (32 bits × 32 bits → 64 bits)

Unsigned integer multiplication (32 bits × 32 bits → 64 bits)

First step in signed integer division

First step in unsigned integer division

Execution of step division

Data correction for the result of signed integer division 1

Data correction for the result of signed integer division 2

PC relative conditional jump Branch condition: !Z & !(N ^ V)

Delayed branching possible

PC relative conditional jump Branch condition: !(N ^ V)

Delayed branching possible

PC relative conditional jump Branch condition: N ^ V

Delayed branching possible

PC relative conditional jump Branch condition: Z | N ^ V

Delayed branching possible

PC relative conditional jump Branch condition: !Z & !C

Delayed branching possible

PC relative conditional jump Branch condition: !C

Delayed branching possible

PC relative conditional jump Branch condition: C

Delayed branching possible

PC relative conditional jump Branch condition: Z | C

Delayed branching possible

PC relative conditional jump Branch condition: Z

Delayed branching possible

PC relative conditional jump Branch condition: !Z

Delayed branching possible

PC relative jump Delayed branching possible

Absolute jump Delayed branching possible

PC relative subroutine call Delayed call possible

Absolute subroutine call Delayed call possible

add

adc

sub

sbc

cmp

mlt.h

mltu.h

mlt.w

mltu.w

div0s

div0u

div1

div2s

div3s

jrgt

jrgt.d

jrge

jrge.d

jrlt

jrlt.d

jrle

jrle.d

jrugt

jrugt.d

jruge

jruge.d

jrult

jrult.d

jrule

jrule.d

jreq

jreq.d

jrne

jrne.d

jp.d

call

call.d

%rd,%rs

%rd,imm6

%sp,imm10

%rd,%rs

%rd,imm6

%sp,imm10

%rd,%rs

%rd,sign6

%rd,%rs

%rs

sign8

%rb

sign8

%rb

Mnemonic

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-5

CPU

Classification

Branch

Data transfer

System control

Immediate extension

Bit manipulation

Other

Function

Subroutine return

Delayed return possible

Return from interrupt or exception handling

Return from the debug processing routine

Software exception

Debug exception

General-purpose register (byte) → general-purpose register (sign-extended)

Memory (byte) → general-purpose register (sign-extended)

Postincrement possible

Stack (byte) → general-purpose register (sign-extended)

General-purpose register (byte) → memory

Postincrement possible

General-purpose register (byte) → stack

General-purpose register (byte) → general-purpose register (zero-extended)

Memory (byte) → general-purpose register (zero-extended)

Postincrement possible

Stack (byte) → general-purpose register (zero-extended)

General-purpose register (halfword) → general-purpose register (sign-extended)

Memory (halfword) → general-purpose register (sign-extended)

Postincrement possible

Stack (halfword) → general-purpose register (sign-extended)

General-purpose register (halfword) → memory

Postincrement possible

General-purpose register (halfword) → stack

General-purpose register (halfword) → general-purpose register (zero-extended)

Memory (halfword) → general-purpose register (zero-extended)

Postincrement possible

Stack (halfword) → general-purpose register (zero-extended)

General-purpose register (word) → general-purpose register

Immediate → general-purpose register (sign-extended)

Memory (word) → general-purpose register

Postincrement possible

Stack (word) → general-purpose register

General-purpose register (word) → memory

Postincrement possible

General-purpose register (word) → stack

No operation

HALT

SLEEP

Extend operand in the following instruction

Test a specified bit in memory data

Clear a specified bit in memory data

Set a specified bit in memory data

Invert a specified bit in memory data

Bytewise swap on byte boundary in word

Bitwise swap every byte in word

Multiply-accumulate operation 16 bits × 16 bits + 64 bits → 64 bits

Push general-purpose registers %rs–%r0 onto the stack

Pop data for general-purpose registers %rd–%r0 off the stack

ret

ret.d

reti

retd

int

brk

ld.b

ld.ub

ld.h

ld.uh

ld.w

nop

halt

slp

ext

btst

bclr

bset

bnot

swap

mirror

mac

pushn

popn

imm2

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%sp+imm6]

[%rb],%rs

[%rb]+,%rs

[%sp+imm6],%rs

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%sp+imm6]

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%sp+imm6]

[%rb],%rs

[%rb]+,%rs

[%sp+imm6],%rs

%rd,%rs

%rd,[%rb]

%rd,[%rb]+

%rd,[%sp+imm6]

%rd,%rs

%rd,sign6

%rd,[%rb]

%rd,[%rb]+

%rd,[%sp+imm6]

[%rb],%rs

[%rb]+,%rs

[%sp+imm6],%rs

imm13

[%rb],imm3

%rd,%rs

%rs

%rd

Mnemonic

II C33 ADV CORE BLOCK: CPU

II-2-6 EPSON S1C33401 TECHNICAL MANUAL

Table II.2.3.2 Function Extended Instructions

Classification

Logical operation

Shift and rotate

Data transfer

Other

Function

Logical AND between general-purpose

registers

Logical AND of general-purpose register and

immediate

Logical OR between general-purpose registers

Logical OR of general-purpose register and

immediate

Exclusive OR between general-purpose

registers

Exclusive OR of general-purpose register and

immediate

Logical inversion between general-purpose

registers (1's complement)

Logical inversion of general-purpose register

and immediate (1's complement)

Logical shift to the right

(Bits 0–31 shifted as specified by the register)

Logical shift to the right

(Bits 0–31 shifted as specified by immediate)

Logical shift to the left

(Bits 0–31 shifted as specified by the register)

Logical shift to the left

(Bits 0–31 shifted as specified by immediate)

Arithmetic shift to the right

(Bits 0–31 shifted as specified by the register)

Arithmetic shift to the right

(Bits 0–31 shifted as specified by immediate)

Arithmetic shift to the left

(Bits 0–31 shifted as specified by the register)

Arithmetic shift to the left

(Bits 0–31 shifted as specified by immediate)

Rotate to the right

(Bits 0–31 rotated as specified by the register)

Rotate to the right

(Bits 0–31 rotated as specified by immediate)

Rotate to the left

(Bits 0–31 rotated as specified by the register)

Rotate to the left

(Bits 0–31 rotated as specified by immediate)

Special register (word)

→ general-purpose register

General-purpose register (word)

→ special register

Search for bits whose value = 0

Search for bits whose value = 1

Extended function

Mode in which the V flag is

cleared after instruction

execution has been added.

For rotate/shift operation, it has

been made possible to shift

9–31 bits.

The number of special registers

that can be used to load data

has been increased.

The number of bits that can be

scanned has been increased to

32 bits.

and

xor

not

srl

sll

sra

sla

ld.w

scan0

scan1

%rd,%rs

%rd,sign6

%rd,%rs

%rd,sign6

%rd,%rs

%rd,sign6

%rd,%rs

%rd,sign6

%rd,%rs

%rd,imm5

%rd,%rs

%rd,imm5

%rd,%rs

%rd,imm5

%rd,%rs

%rd,imm5

%rd,%rs

%rd,imm5

%rd,%rs

%rd,imm5

%rd,%ss

%sd,%rs

%rd,%rs

Mnemonic

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-7

CPU

Table II.2.3.3 Instructions Added to the C33 ADV Core CPU

Classification

Arithmetic operation

Branch

Data transfer

System control

Multifunction

extension

Coprocessor control

Other

Function

Addition of DP register

Signed integer multiplication 32 bits × 16 bits → 64 bits

Multiply-accumulate operation 32 bits × 16 bits + 64 bits → 64 bits

Multiply-accumulate operation 32 bits × 32 bits + 64 bits → 64 bits

Single multiply-accumulate operation 16 bits × 16 bits + 64 bits → 64 bits

Single multiply-accumulate operation 32 bits × 16 bits + 64 bits → 64 bits

Single multiply-accumulate operation 32 bits × 32 bits + 64 bits → 64 bits

Signed integer division 32 bits / 32 bits → 16 bits ... 16 bits

Unsigned integer division 32 bits / 32 bits → 16 bits ... 16 bits

PC relative jump

Delayed branching possible

Return from MMU exception handler routine

Memory indirect (byte) → general-purpose register (sign-extended)

Memory indirect (byte) → general-purpose register (zero-extended)

Memory indirect (halfword) → general-purpose register (sign-extended)

Memory indirect (halfword) → general-purpose register (zero-extended)

Memory indirect (word) → general-purpose register

General-purpose register (byte) → memory indirect (sign-extended)

General-purpose register (halfword) → memory indirect (sign-extended)

General-purpose register (word) → memory indirect

Set a specified bit in PSR

Clear a specified bit in PSR

Execute following instructions for 3 operands

Conditional execution

Postshift

3 operands execution + postshift

Load data from coprocessor

Store data in coprocessor

Execute coprocessor

Load C, V, Z, and N flags from coprocessor

Clear ALR and AHR registers and MO flag to 0

Bytewise swap on halfword boundary in word

Push single general-purpose register

Pop single general-purpose register

Push special registers %ss–ALR onto the stack

Pop data for special registers %sd–ALR off the stack

Signed saturation processing of general-purpose register (byte)

Unsigned saturation processing of general-purpose register (byte)

Signed saturation processing of general-purpose register (halfword)

Unsigned saturation processing of general-purpose register (halfword)

Signed saturation processing of general-purpose register (word)

Unsigned saturation processing of general-purpose register (word)

Execute specified range (general-purpose register) the specified number of

times (general-purpose register)

Execute specified range (immediate) the specified number of times (general-

purpose register)

Execute specified range (immediate) the specified number of times (immediate)

Execute following instructions (as many times as specified by the general-

purpose register)

Execute following instructions (as many times as specified by the immediate)

add

mlt.hw

mac.hw

mac.w

mac1.h

mac1.hw

mac1.w

div.w

divu.w

jpr

jpr.d

retm

ld.b

ld.ub

ld.h

ld.uh

ld.w

ld.b

ld.h

ld.w

psrset

psrclr

ext

ld.c

do.c

ld.cf

macclr

swaph

push

pop

pushs

pops

sat.b

sat.ub

sat.h

sat.uh

sat.w

sat.uw

loop

repeat

%rd,%dp

%rd,%rs

%rs

%rd,%rs

%rs

%rb

%rd,[%dp+imm6]

[%dp+imm6],%rs

imm5

%rb

cond

op,imm2

%rb,op,imm2

%rd,imm4

imm4,%rs

imm6

%rd,%rs

%rs

%rd

%ss

%sd

%rd,%rs

%rc,%ra

%rc,imm4

imm4,imm4

%rc

imm4

Mnemonic

II C33 ADV CORE BLOCK: CPU

II-2-8 EPSON S1C33401 TECHNICAL MANUAL

II.2.4

Address Space and Logical to Physical Address Translation

II.2.4.1 Overview

The C33 ADV Core CPU supports a 4GB address space. Addresses output from the CPU can be translated into

other predefined addresses by the HBCU and MMU, so the CPU does not need to output the addresses that are

assigned to the actual ROM, RAM, and I/O devices. In other words, the CPU can access a 4GB linear logical

address space (virtual space) that is able to build with free memory configuration. The HBCU translates the logical

address output from the CPU into a physical address using the MMU and it sends the translated address to the

BBCU, which manages the physical address space, to access the actual device. The 4GB physical address space is

divided into 23 areas by the BBCU, and different memory or I/O devices can be mapped into each area.

The logical address output from the CPU is subjected to the five processes listed below by the HBCU, MMU, and

BBCU to finally generate the physical address.

1. Block process

2. ASID process

3. Address translation process

4. Mirroring process

5. Area process

Block 7

(512M bytes)

0xFFFF FFFF

0xE000 0000

Block 6

(512M bytes)

0xDFFF FFFF

0xC000 0000

Block 5

(512M bytes)

0xBFFF FFFF

0xA000 0000

Block 4

(512M bytes)

0x9FFF FFFF

0x8000 0000

Block 3

(512M bytes)

0x7FFF FFFF

0x6000 0000

Block 2

(512M bytes)

0x5FFF FFFF

0x4000 0000

Block 1

(512M bytes)

0x3FFF FFFF

0x2000 0000

Block 0

(512M bytes)

0x1FFF FFFF

0x0000 0000

Logical space HBCU, MMU, BBCU

Area 22

2G bytes

Area 21

1G bytes

Area 20

512M bytes

Areas 19–0

512M bytes

Physical space

Block processing

ASID processing

Address translation processing

Mirroring processing

Area processing

Figure II.2.4.1.1 Relationship between Logical and Physical Address Spaces

The following sections explain the outline of the address processing. For details of each process, see the HBCU,

MMU, and BBCU sections.

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-9

CPU

II.2.4.2 Address Processing

Address processing modules

Figure II.2.4.2.1 shows the functional modules that process addresses output from the CPU.

CPU

• Outputs logical

addresses to

access a 4GB

linear address

space.

BBCU

•

Decodes physical

addresses to

decide areas

(chip enable) to

access.

• Outputs the

physical address

with the generated

chip enable to

the external bus.

Memories

and

I/O devices

HBCU

• Divides the

logical space

into 8 blocks

and sets the

attribute for

each block.

• Configures

multiple virtual

spaces using

ASID.

MMU

• Translates

logical addresses

into physical

addresses.

• Performs mirror

processing.

CCU

• Physical address

cache after mirror

processing

Figure II.2.4.2.1 Functional Modules for Address Processing

Address processing flow

CPU

Output of a logical

address to access

a 4GB linear

address space

Setting use or not

use attributes for

MMU, ASID,

instruction cache,

data cache, and

write-back mode

Multiplexing 64

spaces using

6 bits of ASID

CPU output

Block 7 (0.5GB)

Block 6 (0.5GB)

Block 5 (0.5GB)

Block 4 (0.5GB)

Block 3 (0.5GB)

Block 2 (0.5GB)

Block 1 (0.5GB)

Block 0 (0.5GB)

Block processing

63 (64MB)

62 (64MB)

3 (64MB)

2 (64MB)

1 (64MB)

0 (64MB)

ASID processing

HBCU HBCU MMU HBCU

Setting the high-

order 3GB as the

mirror areas of

the low-order 1GB

Mirroring

1GB

Physical

address

cache

Mirror processing

Map 4KB or 64KB

of pages to any

desired physical

addresses

1M/64K (4KB/64KB)

3 (4KB/64KB)

2 (4KB/64KB)

1 (4KB/64KB)

0 (4KB/64KB)

Address translation

(when MMU is used)

When MMU is not used

Logical address Physical address

BBCU

Control of the #CE

signal, wait cycles,

and other access

conditions for each

area

Area 22

(2GB)

Area 21

(1GB)

Area 20

(512MB)

Areas 19–0

(512MB)

Area processing

Figure II.2.4.2.2 Contents of Address Processing

II C33 ADV CORE BLOCK: CPU

II-2-10 EPSON S1C33401 TECHNICAL MANUAL

Address processing for internal peripheral circuits and internal memories

Area 0

Areas 1, 2, and 3

Other than

areas 0–3

Block

processing

External

bus

CPU

ASID

processing MMU

processing

Mirror

processing

BBCU

A0RAM

Areas 1–3

peripherals/

memories

Peripherals/

memories

in area 6, etc.

Internal bus

Cache

Figure II.2.4.2.3 Differences on Accesses to Internal Areas and External Areas

Addresses that are mainly output to the external bus to access areas other than areas 0–6 are subject to the

address processing described above. Normally, ASID and MMU are disabled to use in areas 0–6. Furthermore,

these areas are not mirrored. Therefore, the address processing for areas 0–6 is different from the above

description.

A high-speed RAM (A0RAM) is mapped to area 0 and is accessed with no wait cycle using addresses output

from the CPU directly.

Areas 1, 2, and 3 are dedicated to the internal peripheral circuits and memories and block processing to mirror

processing are not performed. Addresses from the CPU pass through the internal bus and directly access the

internal modules mapped to areas 1–3.

Areas 4, 5, and 6 are external memory areas, note, however, that normally block processing to mirror processing

are not performed as in areas 1–3. Addresses from the CPU are directly passed to the BBCU and are output to

the external bus.

Area 6 is often used for embedded modules (model-specific circuits and extension peripheral circuits/

memories) other than the standard peripheral circuits mapped to area 1. Also in this case, addresses from the

CPU are directly passed to the BBCU to access area 6.

Areas 0–6 can be enabled to process their addresses with ASID and MMU by setting the HBCU in user mode

only. Note that these areas cannot be mirrored even in this case.

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-11

CPU

II.2.4.3 Block Processing

The HBCU divides the 4GB logical address space into eight 0.5GB blocks and manages the attributes shown below

(can be set with software) in each block.

1. MMU (address translation) Used/not used

2. ASID Used/not used

3. Instruction cache Used/not used

4. Data cache Used/not used

5. Write-back mode for cache Used/not used

When the CPU outputs a logical address, the HBCU controls the address processing according to the attributes in

the block that includes the address.

Block 7

(512M bytes)

0xFFFF FFFF

0xE000 0000

Block 7

attribute

Block 6

attribute

Block 5

attribute

Block 4

attribute

Block 3

attribute

Block 2

attribute

Block 1

attribute

Block 0

attribute

Block 6

(512M bytes)

0xDFFF FFFF

0xC000 0000

Block 5

(512M bytes)

0xBFFF FFFF

0xA000 0000

Block 4

(512M bytes)

0x9FFF FFFF

0x8000 0000

Block 3

(512M bytes)

0x7FFF FFFF

0x6000 0000

Block 2

(512M bytes)

0x5FFF FFFF

0x4000 0000

Block 1

(512M bytes)

0x3FFF FFFF

0x2000 0000

Block 0

(512M bytes)

0x1FFF FFFF

0x0000 0000

Area 22

2G bytes

Area 21

1G bytes

• MMU Used/Not used

• ASID Used/Not used

• Instruction cache Used/Not used

• Data cache Used/Not used

• Data cache write back Used/Not used

Area 20

512M bytes

Areas 19–0

512M bytes

Logical address space Physical address space

Block attribute (selectable in each block)

Figure II.2.4.3.1 Division of Logical Address Space into Blocks

II C33 ADV CORE BLOCK: CPU

II-2-12 EPSON S1C33401 TECHNICAL MANUAL

II.2.4.4 ASID Processing

The 6 high-order bits of the logical address is replaced with an ASID that can be specified with software to create

64MB × 64 multiple virtual spaces. When the block has the “ASID not used” attribute, this processing is bypassed.

Process 0

64MB

Process 1

64MB

Process 2

64MB

Process 3

64MB

Process 4

64MB

Process 5

64MB

Process 6

64MB

Process 7

64MB

0x1FFF FFFF

0x1C00 0000

0x1B0F FFFF

0x1800 0000

0x17FF FFFF

0x1400 0000

0x13FF FFFF

0x1000 0000

0x0FFF FFFF

0x0C00 0000

0x0B0F FFFF

0x0800 0000

0x07FF FFFF

0x0400 0000

0x03FF FFFF

0x0000 0000

Process 0

0x03FF FFFF

0x0000 0000

Logical address

• • • • • •

• • • • •

Block 0 Blocks 1, 2, 3, 4, 5, 6

Process 56

64MB

Process 57

64MB

Process 58

64MB

Process 59

64MB

Process 60

64MB

Process 61

64MB

Process 62

64MB

Process 63

64MB

0xFFFF FFFF

0xFC00 0000

0xFB0F FFFF

0xF800 0000

0xF7FF FFFF

0xF400 0000

0xF3FF FFFF

0xF000 0000

0xEFFF FFFF

0xEC00 0000

0xEB0F FFFF

0xE800 0000

0xE7FF FFFF

0xE400 0000

0xE3FF FFFF

0xE000 0000

Logical address Block 7

ASID = 0x0V[25:0]

Process 1

ASID = 0x1

Process 2

ASID = 0x2

Process 63

ASID = 0x3F

Figure II.2.4.4.1 Multiple Virtual Spaces using the ASID

II.2.4.5 MMU Processing (Address Translation)

The logical address is translated to a physical address in page (4KB or 64KB selectable) units.

The 20 high-order bits of the logical address for 4KB per page or the 16 high-order bits of logical address for 64KB

per page can be translated into a desired physical address.

The MMU hardware contains a 64-entry TLB that can be used as an address translation table for translating up

to 1M pages in 4KB per page or 64K pages in 64KB per page. The software (OS) manages the contents of the

translation table.

When the block has the “MMU not used” attribute, this processing is bypassed.

Page 0

Page 1

Page 2

Logical address Physical address

4KB or 64KB per page

(Page 1)

(Page 0)

(Page 2)

Logical addresses

are mapped to physical

addresses in page units.

Figure II.2.4.5.1 Address Translation

II C33 ADV CORE BLOCK: CPU

S1C33401 TECHNICAL MANUAL EPSON II-2-13

CPU

II.2.4.6 Mirror Processing

After the physical address has been decided, a mirror processing that creates 3 mirror areas of low-order 1GB

by replacing the 2 high-order bits of the address can be performed. A physical address area can be accessed with

different logical addresses, it makes it possible to use different block attributes.

The physical address cache in the CCU reads/writes data from/to the memory using the address after mirror

processing.

Blocks 6 and 7

(1G bytes)

Mirror area

Non-mirror area

Blocks 4 and 5

(1G bytes)

Mirror area

Blocks 2 and 3

(1G bytes)

Mirror area

Blocks 0 and 1

(1G bytes)

Effective area

0xFFFF FFFF

0xC010 0000

0xC00F FFFF

0xC000 0000

0xBFFF FFFF

0x8010 0000

0x800F FFFF

0x8000 0000

0x7FFF FFFF

0x4010 0000

0x400F FFFF

0x4000 0000

0x3FFF FFFF

0x0010 0000

0x0000 0000

Logical

address

Share physical addresses

0x100000 to 0x3FFFFFFF

Figure II.2.4.6.1 Address Space when Mirrors Area Set

II.2.4.7 Area Processing

The BBCU allows each area in the physical address space to be configured with connecting device type, bus access

timing parameters, and other conditions. Areas 4 to 22 are enabled to output the addresses externally to access

external devices.

Area 13 0x02FF FFFF

0x0200 0000

External Memory

16M bytes

Area 12 0x01FF FFFF

0x0180 0000

External Memory

8M bytes

Area 11 0x017F FFFF

0x0100 0000

External Memory

8M bytes

Area 10 0x00FF FFFF

0x00C0 0000

External Memory

4M bytes

Area 9 0x00BF FFFF

0x0080 0000

External Memory

4M bytes

Area 8 0x007F FFFF

0x0060 0000

External Memory

2M bytes

Area 7 0x005F FFFF

0x0040 0000

External Memory

2M bytes

Area 6 0x003F FFFF

0x0030 0000

External Memory

1M bytes

Area 5 0x002F FFFF

0x0020 0000

External Memory

1M bytes

Area 4 0x001F FFFF

0x0010 0000

External Memory

1M bytes

Area 3 0x000F FFFF

0x0008 0000

Internal RAM

512K bytes

Area 2 0x0007 FFFF

0x0006 0000

For debugging

128K bytes

Area 1 0x0005 FFFF

0x0002 0000

Internal I/O

256K bytes

Area 0 0x0001 FFFF

0x0000 0000

Internal RAM

128K bytes

Area 22 0xFFFF FFFF

0x8000 0000

External Memory

2G bytes

Area 21 0x7FFF FFFF

0x4000 0000

External Memory

1G bytes

Area 20 0x3FFF FFFF

0x2000 0000

External Memory

512M bytes

Area 19 0x1FFF FFFF

0x1000 0000

External Memory

256M bytes

Area 18 0x0FFF FFFF

0x0C00 0000

External Memory

64M bytes

Area 17 0x0BFF FFFF

0x0800 0000

External Memory

64M bytes

Area 16 0x07FF FFFF

0x0600 0000

External Memory

32M bytes

Area 15 0x05FF FFFF

0x0400 0000

External Memory

32M bytes

Area 14 0x03FF FFFF

0x0300 0000

External Memory

16M bytes

Figure II.2.4.7.1 Area Layout in Physical Address Space

II C33 ADV CORE BLOCK: CPU

II-2-14 EPSON S1C33401 TECHNICAL MANUAL

THIS PAGE IS BLANK.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-1

CMU

II.3 Clock Management Unit (CMU)

II.3.1 Overview of the CMU

The Clock Management Unit (CMU) controls the operating clock supplied to each functional block. The main

functions of the CMU are outlined below.

• Controls reset and NMI inputs

• Selects the system clock source (OSC3, PLL, or OSC1)

• Controls on/off of the OSC3 and OSC1 oscillator circuits

• Controls on/off and frequency multiplication rate of the PLL

• Controls SSCG

• Clock control corresponding to standby modes (SLEEP, HALT, and HALT2)

• Selects divide ratios of the core clock and peripheral circuit clock

• Selects an external bus clock

• Controls on/off of clock supply for each function block (manual/auto)

Through system clock selection, oscillator circuit, and PLL control, and core/peripheral circuit clock divide ratio

selection and clock on/off control for each functional block (with automatic control also possible), the CMU

enables the most suitable operating clock frequency to be selected for the processing involved, as well as to turn off

unnecessary clock supply, which combined with standby mode, helps to significantly reduce power consumption on

the chip.

OSC/PLL

control

and

selector Divider

(1/1, 1/2,

1/4, 1/8)

Core system

clock On/Off

control

Peripheral

system

clock On/Off

control

OSC3

oscillator

OSC1

oscillator

Reset/NMI

control

PLL

Core system clock (CCLK)

selector

To core and

bus control blocks

To peripheral block

CMU_CLK

NMI

RESET

CMU

External NMI

External Reset

CCLK

PCLK

Peripheral system clock (PCLK)

selector

External bus clock (CMU_CLK)

selector

Power-down

control

Figure II.3.1.1 CMU Block Diagram

Note: The clock automatic supply control function for each functional block is effective only when the

operating frequency is 50 MHz or lower. Do not use the clock automatic supply control function

when the operating frequency exceeds 50 MHz.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-2 EPSON S1C33401 TECHNICAL MANUAL

II.3.2 Reset Input and Initial Reset

The CMU also has a function to generate an internal reset signal from external reset input (#RESET).

II.3.2.1 Initial Reset Pins

Table II.3.2.1.1 lists the pins used to initially reset the chip.

Table II.3.2.1.1 Initial Reset Pins

Pin name

#RESET

#NMI

I/O

Function

Initial reset input pin (Low active)

Low: Resets the CPU.

NMI request input pin

This pin is also used for selecting a reset method.

High: Cold start

Low: Hot start

The S1C33 chip is reset by the low state (= 0) on the #RESET input pin, and starts operating when the reset signal

is released back to high (= 1). The core CPU and internal peripheral circuits are initialized while the reset signal is

kept low.

II.3.2.2 Cold Reset and Hot Reset

One of two reset methods (cold reset or hot reset) can be used to start the S1C33 chip. The #RESET and #NMI pins

are also used to specify either method.

Table II.3.2.2.1 shows the differences between cold reset and hot reset.

Table II.3.2.2.1 Differences between Cold Reset and Hot Reset

Setup contents

Reset condition

CPU: TTBR

CPU: PC

CPU: PSR

CPU: Other registers

CPU: Operating clock

Oscillation circuit

I/O pin status (0x40340–0x40395)

Other peripheral circuit

#RESET = low & #NMI = high #RESET = low & #NMI = low

Initialized to 0x20000000 Status is retained.

The vector at the TTBR boot address is loaded to the PC.

All the PSR bits are reset to 0.

Undefined

The CPU operates with the OSC3 clock.

Both the OSC1 and OSC3 circuits start oscillating.

Initialized Status is retained.

Initialized or undefined

Cold reset

Hot reset

Cold reset initializes the CPU and all internal peripheral circuits, and is therefore useful for power-on reset.

Hot reset initializes the CPU and internal peripheral circuits, but does not initialize the input/output ports and TTBR

of the CPU. Therefore, hot reset is useful when the chip must be reset while operating, with the input/output port

status retained.

Note, however, that the input signal to the #NMI pin used to specify a reset method should be applied at the timing

shown in Figure II.3.2.2.1.

(1) Cold reset (2) Hot reset

#NMI

#RESET

Cold reset is generated

(#RESET = low & #NMI = high)

#NMI must be set to high longer than

the reset pulse width.

#NMI

#RESET

Hot reset is generated

(#RESET = low & #NMI = low)

#NMI must be set to low longer than

the reset pulse width.

Figure II.3.2.2.1 Settings of #RESET and #NMI Pins

Note: Even if the #RESET pin is pulled low (= 0), the chip may not be reset unless supplied with a clock.

To confirm that the chip is reset, #RESET should be held low for at least 10 OSC3 clock cycles.

However, the input/output port pins are initialized by cold reset regardless of whether the chip is

supplied with a clock.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-3

CMU

II.3.2.3 Power-on Reset

When turning on the power for the chip, always be sure to cold reset the chip to ensure that it will start operating

normally.

Since the #RESET pin is a gate input, a power-on reset circuit should be configured external to the chip.

Initial reset (#RESET = 0) causes the high-speed (OSC3) oscillator circuit to start oscillating, and when the reset

signal is released back high, the CPU starts operating with the OSC3 clock. The high-speed (OSC3) oscillator

circuit requires a finite time until its oscillation stabilizes after it starts operating. To confirm that the CPU is started,

the initial reset can only be deasserted after this oscillation stabilization time elapses.

Note: The oscillation start time of the high-speed (OSC3) oscillator circuit varies with the device used,

board patterns, and operating environment. Therefore, sufficient time should be provided before

the reset signal is deasserted.

Power-on sequence

To ensure that the chip will operate normally, observe the timing requirements given below when turning on the

power for the chip.

I/O power voltage

VDDE, AVDD

Internal power voltage

VDD, PLLVDD

OSC3

#RESET

VDD min.

tVDD

tSTA3 tRST

Figure II.3.2.3.1 Power-on Sequence

(1) tVDD: The time until the power supply for the chip stabilizes after being turned on.

Turn on the power supplies in order of the following (or at the same time):

Internal core power supply (e.g., VDD, PLLVDD) → I/O power supply (e.g., VDDE, AVDD) → input

signal applied

(2) tSTA3: OSC3 oscillation start time

(3) tRST: Minimum reset pulse width

Make sure #RESET is held low (= 0) for at least 10 clock cycles after the OSC3 clock supplied to the CMU has

stabilized.

II.3.2.4 Boot Address

When the #RESET pin is released back high (= 1) after the reset period, the core CPU reads the reset vector (program

start address) from the boot address (0x20000000 set in the TTBR register at cold reset) and sets it in the Program

Counter (PC). The core CPU starts executing the program from that address.

The trap table that contains trap vectors for interrupts, etc., also begins by default with this boot address. (Refer to

the S1C33 Family C33 ADV Core CPU Manual.)

The base address of the trap table is set in TTBR, and can be changed to any 1KB boundary address.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-4 EPSON S1C33401 TECHNICAL MANUAL

II.3.2.5 Precautions to be Taken during Initial Reset

Core CPU

When initially reset, all internal registers of the core CPU (except PSR) become unstable. Therefore, these

registers must be initialized in a program. In particular, the Stack Pointer (SP) should always be initialized

before accessing the stack. Note that NMI requests are masked in hardware until data is written to the SP after

initial reset, to prevent erratic operation.

Internal RAM

The content of internal RAM becomes unstable when initially reset. Internal RAM must be initialized as

required.

High-speed (OSC3) oscillator circuit

When initially reset, the high-speed (OSC3) oscillator circuit starts oscillating, and when the reset signal is

deasserted, the CPU starts operating with the OSC3 clock. To prevent erratic operation due to an instable clock

when the chip is reset at power-on or while the high-speed (OSC3) oscillator circuit is idle, the reset signal

should not be deasserted until after oscillation stabilizes.

Low-speed (OSC1) oscillator circuit

When the chip is reset at power-on or while the low-speed (OSC1) oscillator circuit is idle, the low-speed

(OSC1) oscillator circuit also starts oscillating. The low-speed (OSC1) oscillator circuit requires a longer time

for oscillation to stabilize than the high-speed (OSC3) oscillator circuit. (See the electrical characteristics

table.) To prevent erratic operation due to an instable clock, the OSC1 clock should not be used until after this

stabilization time elapses.

Input/output ports and input/output pins

Cold reset initializes the control and data registers of the input/output ports.

When the chip is hot reset, the control registers and pins retain the status held before the reset. However, if these

pins are set for use as input/output pins for the internal peripheral circuit, the control registers of the peripheral

circuit are initialized or made unstable by initial reset and must, therefore, be set up back again in a program.

Other internal peripheral circuits

The control and data registers of other peripheral circuits are initialized or made unstable by initial reset,

regardless of the reset method (cold or hot reset). Therefore, these registers should be set up as required in a

program.

For details on how peripheral circuits are initialized by initial reset, see each I/O map or circuit description.

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CMU

II.3.3 NMI Input

The external NMI signal is input from the #NMI pin to the CMU, then forwarded to the CPU. For details about

NMI exception handling by the CPU, refer to the S1C33 Family C33 ADV Core CPU Manual.

II.3.3.1 NMI Detection Mode

The method of detecting whether to recognize NMI input by a falling edge or low level can be selected by using

NMIMD (D8/0x4836C).

∗ NMIMD: NMI Detection Mode Select Bit in the NMI Mode Register (D8/0x4836C)

When initially reset, NMIMD (D8/0x4836C) is set to 0, with falling edge detection mode selected. When NMI

input must be recognized by level, set NMIMD (D8/0x4836C) to 1.

Note: At least a 3-system clock width of low pulse is required to generate NMI even if falling edge

detection mode has been selected. After the NMI signal falls, maintain it at a low level for 3 or

more clock cycles.

II.3.3.2 NMI Flag

When an NMI request is detected by a falling edge or low level as selected above, the NMIF flag (D12/0x4836A) is

set to 1.

∗ NMIF: NMI Flag in the NMI Flag Register (D12/0x4836A)

This signal is forwarded to the CPU for generating an NMI exception. Writing a 1 to the bit (D12/0x4836A) resets

the previously set NMIF flag.

Notes: • The NMIF flag (D12/0x4836A) should always be reset by writing a 1 in the NMI exception

handler routine. Otherwise, an NMI exception may be generated again when the NMI

exception handler routine is terminated by the reti instruction.

• NMI cannot be nested. The CPU keeps NMI input masked out until the reti instruction is

executed after an NMI exception occurred.

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II-3-6 EPSON S1C33401 TECHNICAL MANUAL

II.3.4 Selecting the System Clock Source

The CMU has the following three clock inputs, one of which can be selected as the source clock (OSC) for the

system (core clock, peripheral circuit clock, and external bus clock).

1. OSC3 clock

This clock is generated by the OSC3 oscillator circuit or supplied from an external source through the OSC3

pin. The oscillation frequency/input frequency varies with each S1C33 model. For details about the OSC3

oscillator circuit, see “OSC3 Oscillator Circuits, PLL and SSCG” in Chapter IV, “C33 ADV Basic Peripheral

Block.”

The CMU control registers can be used for on/off control of the OSC3 oscillator circuit (see Section II.3.5).

2. OSC1 clock

This is the source clock (32.768 kHz, typ.) for the Real Time Clock (RTC). When high-speed operation is

unnecessary, this low-speed clock may be used to operate the system, thus helping to reduce power consumption

on the chip. For details about the OSC1 oscillator circuit, see “Real Time Clock (RTC)” in Chapter V, “Extension

Peripheral Circuit Block.”

The CMU control registers can be used for on/off control of the OSC1 oscillator circuit (see Section II.3.5).

3. PLL clock

This is the clock output by the PLL. The PLL multiplies the OSC3 clock frequency by a given value to generate

a clock for high-speed operation. The frequency multiplication rate that can be set depends on the upper-limit

operating clock frequency of each S1C33 model and the OSC3 oscillation frequency.

For details about the PLL, see “OSC3 Oscillator Circuits, PLL and SSCG” in Chapter IV, “C33 ADV Basic

Peripheral Block.” The CMU control registers can be used for on/off control of the PLL and to set the frequency

multiplication rate (see Section II.3.6).

The clock source can be selected as shown in Table II.3.4.1 by using OSCSEL[1:0] (D[3:2]/0x48360).

∗ OSCSEL[1:0]: OSC Clock Select Bits in the Core System Clock Control Register (D[3:2]/0x48360)

Table II.3.4.1 Selection of the System Clock Source

OSCSEL1

OSCSEL0

Clock source

PLL

OSC3

OSC1

OSC3

(Default: 0b00 = OSC3)

The clock source changed here is not reflected until after the CPU returns from SLEEP mode. Therefore, the slp

instruction must be executed once after setting OSCSEL[1:0] (D[3:2]/0x48360). Although the CPU returns from

SLEEP mode to normal operation by an external interrupt from a port, for example, several functions are provided

for use in clock source changes, thus automatically returning the CPU from SLEEP mode a certain time after slp

instruction execution or leaving the OSC3 oscillator circuit turned on during SLEEP mode. Section II.3.12, “Standby

Modes,” describes these methods of control in detail.

Notes: • The Core System Clock Control Register (0x48360) is write-protected. Before this and

other CMU control registers at addresses 0x40180–0x40188 and 0x48360–0x48372 can be

rewritten, write protection of these registers must be removed by writing data 0x0096 (HW)

to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to

addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system operation,

the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless

said CMU control registers must be rewritten.

• When clock sources are changed, the CMU control registers must be set so that the CMU

is supplied with a clock from the selected clock source upon returning from SLEEP mode

immediately after the change. Otherwise, the chip does not restart after the return from

SLEEP mode.

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CMU

II.3.5 Controlling the Oscillator Circuit

The SOSC3 (D1/0x48360) bit used for on/off control of OSC3 oscillation and the SOSC1 (D0/0x48360) bit for

on/off control of OSC1 oscillation are provided in the CMU control register. However, since the OSC3 and OSC1

oscillator circuits are not incorporated in the core block, see “OSC3 Oscillator Circuits, PLL and SSCG” in Chapter

IV, “C33 ADV Basic Peripheral Block,” for details of the OSC3 oscillator circuit, and “Real Time Clock (RTC)” in

Chapter V, “Extension Peripheral Circuit Block,” for details of the OSC1 oscillator circuit.

∗ SOSC3: High-speed Oscillation (OSC3) On/Off Bit in the Core System Clock Control Register (D1/0x48360)

∗ SOSC1: Low-speed Oscillation (OSC1) On/Off Bit in the Core System Clock Control Register (D0/0x48360)

Setting these bits to 0 turns off the respective oscillator circuits. Setting these bits to 1 turns on the respective

oscillator circuits for initiating clock output. When initially reset, both control bits are set to 1, with the oscillators

oscillating.

Notes: • The Core System Clock Control Register (0x48360) is write-protected. Before this and

other CMU control registers at addresses 0x40180–0x40188 and 0x48360–0x48372 can be

rewritten, write protection of these registers must be removed by writing data 0x0096 (HW)

to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to

addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system operation,

the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless

said CMU control registers must be rewritten.

• When SOSC3 (D1/0x48360) or SOSC1 (D0/0x48360) is set from 0 to 1, thus initiating

oscillation by the oscillator, a finite time is required until the oscillation stabilizes. Moreover, to

prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time

stipulated in the electrical characteristics table elapses.

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II-3-8 EPSON S1C33401 TECHNICAL MANUAL

II.3.6 Controlling the PLL

The PLL multiplies the OSC3 clock frequency by a given value to generate a source clock for high-speed operation.

PLL input clock frequency: 5 to 150 MHz

PLL output clock frequency: 20 to 200 MHz

Frequency-multiplication rate: 1 to 16 times

The PLL control bits are provided in the CMU control registers. However, since the PLL is not incorporated in the

core block, see “OSC3 Oscillator Circuits, PLL and SSCG” in Chapter IV, “C33 ADV Basic Peripheral Block,” for

details about the PLL.

II.3.6.1 On/Off Control of the PLL

PLLPOWR (D0/0x40184) can be used to turn the PLL on or off.

∗ PLLPOWR: PLL On/Off Control Bit in PLL Control Register 1 (D0/0x40184)

Setting PLLPOWR (D0/0x40184) to 1 initiates PLL operation. When initially reset, PLLPOWR (D0/0x40184) is

set to 0 (power-down mode), with the PLL turned off.

Note: Immediately after the PLL is started by setting PLLPOWR (D0/0x40184) to 1, an output clock

stabilization wait time is required (e.g., 200 µs in the S1C33401). When the clock source for the

system is switched over to the PLL, allow for this wait time after the PLL has turned on.

II.3.6.2 Setting the Frequency Multiplication Rate

The PLL frequency multiplication rate can be specified as shown in Table II.3.6.2.1 by using PLLN[3:0] (D[7:4]/

0x40184).

∗ PLLN[3:0]: PLL Multiplication Rate Setup Bits in PLL Control Register 1 (D[7:4]/0x40184)

Table II.3.6.2.1 PLL Frequency Multiplication Rates

PLLN3

PLLN2

Multiplication rate

x16

x15

x14

x13

x12

x11

x10

PLLN1

PLLN0

(Default: 0b0000 = x1)

PLL output clock frequency = PLL input clock frequency (OSC3) × multiplication rate

Notes: • The frequency multiplication rate that can be set depends on the upper-limit operating clock

frequency of each S1C33 model and the OSC3 oscillation frequency. When setting the

frequency multiplication rate, be sure not to exceed the upper-limit operating clock frequency.

• The frequency multiplication rate can only be set when the PLL is turned off (PLLPOWR (D0/

0x40184) = 0) and the clock source is other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0

–2). If the frequency multiplication rate is changed while the system is operating with the PLL

clock, the system may operate erratically.

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CMU

II.3.6.3 Other PLL Settings

V-Divider

To ensure that frequency fVCO obtained by <output frequency × W> falls within the range of 100 to 400

MHz, set the proper W value by using PLLV[1:0] (D[3:2]/0x40184). Lower value is better for low power

consumption.

∗ PLLV[1:0]: PLL V-Divider Setup Bits in PLL Control Register 1 (D[3:2]/0x40184)

Table II.3.6.3.1 Settings of the W Value

PLLV1

PLLV0

Not allowed

(Default: 0b01 = 2)

VCO Kv constant (VC value)

According to the range of fVCO frequencies obtained by <output frequency × W>, set the VCO Kv circuit

constant (VC value) by using PLLVC[3:0] (D[7:4]/0x40185).

∗ PLLVC[3:0]: PLL VCO Kv Setup Bits in PLL Control Register 2 (D[7:4]/0x40185)

Table II.3.6.3.2 Settings of the VC Value

PLLVC3

Other

PLLVC2

fVCO [MHz]

360 < fVCO ≤ 400

320 < fVCO ≤ 360

280 < fVCO ≤ 320

240 < fVCO ≤ 280

200 < fVCO ≤ 240

160 < fVCO ≤ 200

120 < fVCO ≤ 160

100 ≤ fVCO ≤ 120

Not allowed

PLLVC1

PLLVC0

(Default: 0b0001)

LPF resistance value (RS value)

According to the input clock (OSC3) frequency, set the LPF resistance value (RS value) of the PLL by using

PLLRS[3:0] (D[3:0]/0x40185).

∗ PLLRS[3:0]: PLL LPF Resistance Setup Bits in PLL Control Register 2 (D[3:0]/0x40185)

Table II.3.6.3.3 Settings of the RS Value

PLLRS3

Other

PLLRS2

fREFCK [MHz]

5 ≤ fREFCK < 20

20 ≤ fREFCK ≤ 150

Not allowed

PLLRS1

PLLRS0

(Default: 0b1000)

LPF capacitance value (CS value)

Bits to set the LPF capacitance value (CS value) is provided in the CMU control registers, PLLCS[1:0]/(D[7:6]/

0x40186). However, do not alter the value of these bits, and leave them as initially set (0b00).

∗ PLLCS[1:0]: PLL LPF Capacitance Setup Bits in PLL Control Register 3 (D[7:6]/0x40186)

Charge pump current value (CP value)

Bits to set the charge pump current value (CP value) is provided in the CMU control registers, PLLCP[4:0]/

(D[4:0]/0x40186). However, do not alter the value of these bits, and leave them as initially set (0b10000).

∗ PLLCP[4:0]: PLL Charge Pump Current Setup Bits in PLL Control Register 3 (D[4:0]/0x40186)

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II-3-10 EPSON S1C33401 TECHNICAL MANUAL

Table II.3.6.3.4 Example PLL Settings

PLL input clock (OSC3)

5 MHz

10 MHz

20 MHz

33 MHz

PLL output clock

65 MHz

60 MHz

40 MHz

60 MHz

40 MHz

60 MHz

40 MHz

66 MHz

PLLN[3:0]

x13, 0b1100

x12, 0b1011

x8, 0b0111

x6, 0b0101

x4, 0b0011

x3, 0b0010

x2, 0b0001

PLLV[1:0]

0b01

0b10

0b01

0b10

0b01

0b10

0b01

PLLVC[3:0]

0b0010

0b0001

0b0010

0b0001

0b0010

0b0001

0b0010

PLLRS[3:0]

0b1010

0b1000

Notes: • The PLL can only be set up when the PLL is turned off (PLLPOWR (D0/0x40184) = 0) and

the clock source is other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0–2). If settings are

changed while the system is operating with the PLL clock, the system may operate erratically.

• The PLL control registers are write-protected. Before these and other CMU control registers

at addresses 0x40180–0x40188 and 0x48360–0x48372 can be rewritten, write protection of

these registers must be removed by writing data 0x0096 (HW) to the Clock Control Protect

and 0x48360–0x48372 could lead to erratic system operation, the Clock Control Protect

registers must be rewritten.

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CMU

II.3.7 Control of the SSCG

The Spread Spectrum Clock Generator (SSCG) is a circuit used to reduce Electromagnetic Interference (EMI) noise

by spreading the spectrum (or performing SS modulation) for the PLL output clock signal. The SS modulation is

effective for all operating clocks for the core and peripheral circuits (except the RTC that uses the OSC1 clock)

when the PLL output clock has been selected as the system clock source and only this case has the effect of

reducing noise.

Note: When the OSC3 or OSC1 clock is selected as the system clock source, SS modulation is not

performed for the operating clock (system clock).

∗ About spectrum spread (SS modulation)

The SSCG performs SS modulation by adjusting the width of the high section of the input clock. This

adjustment is made by increasing or reducing the set value of the internal delay adjust circuit of the SSCG. The

maximum width within which the set value is changed constitutes the maximum frequency change width. The

relevant control register is used to set the upper-limit value of this width. In the SSCG, an interval timer adjusts

the interval at which the set value changes. The relevant control register is also used to set this interval (frequency

change cycle).

±0Input clock cycle

Maximum frequency change width

–Frequency change cycle

Figure II.3.7.1 SS Modulation

The SSCG control bits are provided in the control registers of the CMU. Note, however, that the SSCG is not built

into the core block. For details of the clock generator unit that includes the SSCG, see the description of the OSC3

oscillator circuit, PLL, and SSCG in Chapter IV, “C33 ADV Basic Peripheral Block.”

II.3.7.1 Turning the SSCG On/Off

The SSCG can be turned on or off by using SSMCON (D0/0x40187).

∗ SSMCON: SS Macro On/Off Control Bit in the SS Macro Control Register 1 (D0/0x40187)

Setting SSMCON (D0/0x40187) to 1 causes the SSCG to start operating. When initially reset, SSMCON (D0/

0x40187) is initialized to 0, with the SSCG turned off (bypassed).

Note: The SSCG is effective only when the PLL is selected as the system clock source. Furthermore,

the SSCG control registers cannot be set when the PLL is inactive.

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II-3-12 EPSON S1C33401 TECHNICAL MANUAL

II.3.7.2 Setting SS Modulation Parameters

As described in “About spectrum spread (SS modulation)” above, it is necessary to set the upper-limit value of the

maximum frequency change width and the frequency change cycle.

The maximum frequency change width should be set to the appropriate value according to the system clock

frequency as shown in Table II.3.7.2.1 using SSMCIDT[3:0] (D[3:0]/0x40188). The maximum frequency change

width will be about ±2% of the system clock by setting the appropriate value.

∗ SSMCIDT[3:0]: SS Macro Maximum Frequency Change Width Setting Bits in the SS Macro Control Register 2

(D[3:0]/0x40188)

Table II.3.7.2.1 Maximum Frequency Change Width Settings

SSMCIDT2

SSMCIDT1

System clock frequency f [MHz]

20.5 < f ≤ 21.7

21.7 < f ≤ 23.0

23.0 < f ≤ 24.5

24.5 < f ≤ 26.1

26.1 < f ≤ 28.0

28.0 < f ≤ 30.3

30.3 < f ≤ 32.8

32.8 < f ≤ 35.9

35.9 < f ≤ 39.6

39.6 < f ≤ 44.2

44.2 < f ≤ 49.9

49.9 < f ≤ 57.4

57.4 < f ≤ 66.0

–

SSMCIDT3

SSMCIDT0

(Default: 0b0000)

SSMCITM[3:0] (D[7:4]/0x40188) is used to set the frequency change cycle. However, always set it to 0b0001.

∗ SSMCITM[3:0]: SS Macro Interval Timer Setting Bits in the SS Macro Control Register 2 (D[7:4]/0x40188)

Notes: • The SS macro control registers are write-protected. Write protection for these registers and

other CMU control registers at addresses 0x40180–0x40188 and 0x48360–0x48372 to be

rewritten must be removed by writing 0x0096 (HW) to the Clock Control Protect Register

(0x4836E). Since unnecessary rewrites to addresses 0x40180–0x40188 and 0x48360–

0x48372 could cause the system to operate erratically, make sure that the data set in the

Clock Control Protect Register (0x4836E) is other than 0x0096 (HW), unless rewriting said

registers.

• SSMCIDT[3:0] (D[3:0]/0x40188) must be set according to the system clock frequency as

shown in Table II.3.7.2.1. Using the SSCG with an improper setting may cause a malfunction

of the IC.

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CMU

II.3.8 Setting the Core System Clock (CCLK)

CCLK is the operating clock for the CPU, core block (HBCU, MMU, CCU, and DBG), and modules connecting to

the high-speed bus (DMA, BBCU, EBCU, and internal RAM).

The source clock OSC for the system (selected by OSCSEL[1:0] (D[3:2]/0x48360)) is divided by 1 to 8 by a clock

frequency divider, generating four kinds of clocks. Select CCLK from those four clocks by using CCLKSEL[1:0]

(D[9:8]/0x48360).

∗ CCLKSEL[1:0]: Core Clock (CCLK) Select Bits in the Core System Clock Control Register (D[9:8]/0x48360)

Table II.3.8.1 Selecting CCLK

CCLKSEL1

CCLKSEL0

CCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

(Default: 0b00 = OSC•1/1)

CCLK can be selected at any time. However, since the clocks are switched over internally in the chip when all the

div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are required before the clocks are

actually changed after altering the register values.

Notes: • The Core System Clock Control Register (0x48360) is write-protected. Before this and

other CMU control registers at addresses 0x40180–0x40188 and 0x48360–0x48372 can be

rewritten, write protection of these registers must be removed by writing data 0x0096 (HW)

to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to

addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system operation,

the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless

said CMU control registers must be rewritten.

• When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide

ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios,

the CPU may not operate normally after returning from SLEEP mode.

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II.3.9 Setting the Peripheral Circuit Clock (PCLK)

PCLK is the operating clock for peripheral circuits. All modules except those clocked by CCLK basically use this

PCLK clock. The ITC, prescaler, A/D converter, serial interface, 16/8-bit timers, card interface, and input/output

ports all operate with the PCLK clock. Note that the RTC operates with only the 32-kHz OSC1 clock.

As for CCLK, select PCLK from the four clocks derived from the OSC by using PCLKSEL[1:0] (D[1:0]/0x48366).

∗ PCLKSEL[1:0]: Peripheral Clock (PCLK) Select Bits in the Peripheral and External Clock Output Control

Table II.3.9.1 Selecting PCLK

PCLKSEL1

PCLKSEL0

PCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

(Default: 0b00 = OSC•1/1)

PCLK can be selected at any time. However, since the clocks are switched over internally in the chip when all the

div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are required before the clocks are

actually changed after altering the register values.

Notes: • The Peripheral and External Clock Output Control Register (0x48366) is write-protected.

Before this and other CMU control registers at addresses 0x40180–0x40188 and 0x48360–

0x48372 can be rewritten, write protection of these registers must be removed by writing data

0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since unnecessary

rewrites to addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system

operation, the Clock Control Protect Register (0x4836E) should be set to other than 0x0096

(HW) unless said CMU control registers must be rewritten.

• When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide

ratio before executing the slp instruction. If CCLK and PCLK are set to different divide ratios,

the CPU may not operate normally after returning from SLEEP mode.

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CMU

II.3.10 Setting the External Clock Output (CMU_CLK)

CMU_CLK is an external output clock. This clock is used by functions other than the C33 ADV Core on the chip

or those external to the chip.

CMU_CLK can be selected from four clocks derived from OSC as for CCLK and PCLK, or can be the clock input

directly from the system clock source. Use CMUCLK[2:0] (D[10:8]/0x48366) to select a clock for CMU_CLK.

∗ CMUCLK[2:0]: External Clock Output (CMU_CLK) Select Bits in the Peripheral and External Clock Output

Control Register (D[10:8]/0x48366)

Table II.3.10.1 Selecting CMU_CLK

CMUCLK2

CMUCLK1

CMU_CLK

PLL

OSC1

OSC3

CCLK (before clock tree)

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

CMUCLK0

(Default: 0b000 = OSC•1/1)

CMU_CLK can be selected at any time. However, switching over the clocks creates hazards.

When CMU_CLK must be output to external devices, it is also necessary to select a port function. For details

on how to control clock output and the port to be used, see Section I.3.3, “Switching Over the Multiplexed Pin

Functions.”

Note: The Peripheral and External Clock Output Control Register (0x48366) is write-protected. Before

this and other CMU control registers at addresses 0x40180–0x40188 and 0x48360–0x48372 can

be rewritten, write protection of these registers must be removed by writing data 0x0096 (HW) to

the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites to addresses

0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system operation, the Clock

Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless said CMU

control registers must be rewritten.

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II.3.11 Controlling Clock Supply

To reduce power consumption on the chip, a function is provided to turn off clock supply independently for each

functional block. In addition to manual control in software, an automatic control function implemented in hardware

is also available.

II.3.11.1 Software Control of Clock Supply

Table II.3.11.1.1 lists the register bits used for on/off control of CCLK clock supply to the core system modules.

Table II.3.11.1.2 lists the register bits used for on/off control of PCLK clock supply to peripheral modules.

Table II.3.11.1.1 CCLK Clock Supply Control Bits

Module clock

DBG NOSTOP clock

DBG clock

HBCU clock

MMU clock

CCU clock

CPU clock

BBCU, EBCU NOSTOP clock

BBCU HB I/F clock

BBCU SRAM clock

BBCU DBG I/F clock

EBCU HB I/F clock

EBCU SDRAM clock

A3RAM clock

DMA clock

SAPB12C clock

SAPB1P clock

Control bit

DBGNCLK (D15)

DBGCLK (D8)

HBCUCLK (D3)

MMUCLK (D2)

CCUCLK (D1)

CPUCLK (D0)

BBEBNCLK (D11)

BBHBIFCLK (D10)

BBSRAMCLK (D9)

BBDBGIFCLK (D8)

EBCUHBCLK (D5)

EBCUSDCLK (D4)

A3RAMCLK (D3)

DMACLK (D2)

SAPB12CCLK (D1)

SAPB1PCLK (D0)

Control register

Core System Clock On/Off

(0x48362)

CCLK System Peripheral

Clock On/Off Register

(0x48370)

Table II.3.11.1.2 PCLK Clock Supply Control Bits

Module clock

Prescaler clock

A/D converter clock

Serial I/F clock

16-bit timer clock

8-bit timer clock

ITC clock

Interrupt generation clock

Watchdog timer clock

Card I/F clock

Port clock

Control bit

PSCCLK (D7)

ADCCLK (D6)

SIOCLK (D4)

T16CLK (D3)

T8CLK (D2)

ITCCLK (D0)

INTCLK (D4)

WDTCLK (D3)

CARDCLK (D2)

POT1CLK (D0)

Control register

Peripheral Clock

Control

(0x40180)

Peripheral Clock

Control

(0x40181)

When initially reset, these control bits are set to 1, with clocks supplied to each module. If any module is unused,

set the corresponding control bit to 0, thus turning the clock for that module off.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-17

CMU

II.3.11.2 Automatic Control of Clock Supply

The CCLK clock supply to the core system modules listed in Table II.3.11.2.1 can be automatically controlled in

hardware.

Table II.3.11.2.1 CCLK Clock Supply Automatic Control Enable Bits

Module clock

DBG clock

HBCU clock

MMU clock

CCU clock

CPU clock

BBCU HB I/F clock

BBCU SRAM clock

BBCU DBG I/F clock

EBCU HB I/F clock

EBCU SDRAM clock

A3RAM clock

DMA clock

SAPB12C clock

SAPB1P clock

Control bit

DBGAUTO (D8)

HBCUAUTO (D3)

MMUAUTO (D2)

CCUAUTO (D1)

CPUAUTO (D0)

BBHBIFAUTO (D10)

BBSRAMAUTO (D9)

BBDBGIFAUTO (D8)

EBCUHBAUTO (D5)

EBCUSDAUTO (D4)

A3RAMAUTO (D3)

DMAAUTO (D2)

SAPB12CAUTO (D1)

SAPB1PAUTO (D0)

Control register

Core System Clock

Automatic Control Register

(0x48364)

CCLK System Peripheral

Clock Automatic Control

(0x48372)

The automatic control function for any core system module can be enabled by setting the corresponding control bit

to 1, in which case clock supply for that module is turned on or off by hardware according to the module’s usage

condition. When initially reset, the automatic control function for only the DBG module is enabled (= 1), with the

automatic control function for all other modules disabled (= 0).

This automatic control function is enabled when the corresponding software control bit listed in Table II.3.11.1.1 is

set to 1 (clock supply turned on). When the software control bit for any module is 0 (clock supply turned off), clock

supply for that module is stopped regardless of how automatic control is set.

Notes: • The Core System Clock Control Registers (0x48362, 0x48364, 0x48370, and 0x48372) are

write-protected. Before these and other CMU control registers at addresses 0x40180–0x40188

and 0x48360–0x48372 can be rewritten, write protection of these registers must be removed

by writing data 0x0096 (HW) to the Clock Control Protect Register (0x4836E). Note that since

unnecessary rewrites to addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to

erratic system operation, the Clock Control Protect Register (0x4836E) should be set to other

than 0x0096 (HW) unless said CMU control registers must be rewritten.

• The clock supply to any module can only be stopped when the module is not operating or

unused. If clock supply to any module is stopped when the module is not operating or unused,

the chip may hang.

• The clock automatic control function is effective only when the operating frequency is 50 MHz

or less. Do not use the function when the chip is operating with a clock higher than 50 MHz.

• SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block.

SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop

these clocks as the register read/write operation cannot be performed.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-18 EPSON S1C33401 TECHNICAL MANUAL

II.3.12 Standby Modes

The C33 ADV supports three standby modes: HALT, HALT2, and SLEEP. Power consumption on the chip can be

greatly reduced by placing the CPU in one of these standby modes.

Moreover, the CPU must be placed in SLEEP mode before clock sources for the system (OSC3, OSC1, or PLL) are

switched over.

II.3.12.1 HALT Mode

When HALTMD (D1/0x48368) is set to 0 (default), the CPU suspends program execution upon executing the halt

instruction and enters HALT mode.

∗ HALTMD: HALT Mode Select Bit in the Clock Option Register (D1/0x48368)

In HALT mode, the CPU, CCU, MMU, HBCU, and A0RAM (area 0 no-wait RAM) all stop operating. The other

internal peripheral circuits remain in the state (idle or operating) held when the halt instruction was executed.

The CPU is released from HALT mode by initial reset, an NMI or other interrupt, or a forcible break from the

debugger.

II.3.12.2 HALT2 Mode

When HALTMD (D1/0x48368) is set to 1, the CPU suspends program execution upon executing the halt instruction

and enters HALT2 mode.

In HALT2 mode, the BBCU, EBCU, and DMA also stop operating, in addition to the CPU, CCU, MMU, HBCU,

and A0RAM. The other internal peripheral circuits remain in the state (idle or operating) held when the halt

instruction was executed.

The CPU is released from HALT2 mode by initial reset, an NMI or other interrupt, or a forcible break from the

debugger.

HALT and HALT2 modes are effective in reducing power consumption on the chip when running the CPU is

unnecessary, such as when waiting for external input or responses from peripheral circuits. When the CPU is

released from HALT/HALT2 mode by an interrupt, it enters a program executable state by trap processing and

executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the address for the

instruction next to halt is saved to the stack as a return address from the interrupt handling routine, so that the reti

instruction in the interrupt handling routine branches to the instruction next to halt.

The CPU is released from HALT/HALT2 mode when the interrupt controller (ITC) asserts the interrupt signal to

be sent to the CPU. In other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the

interrupt enable bits in the ITC is set to 1, the CPU can be released from HALT/HALT2 mode even if the PSR is set

to disable interrupts. However, in this case the CPU does not execute the interrupt handling routine.

The #NMI signal releases the CPU from HALT/HALT2 mode when it goes low level even if the NMI detection

mode has been set to edge detection mode.

II.3.12.3 SLEEP Mode

The CPU suspends program execution upon executing the slp instruction and enters SLEEP mode. In SLEEP mode,

the CPU stops operating and the CMU stops supplying a clock to each functional block. Therefore, all peripheral

circuits (except the oscillator circuit and RTC) stop operating. Note that before the CMU actually stops clock output

after initiating processing to enter SLEEP mode, up to 8 clock cycles of the source clock (OSC) then selected are

required.

The CPU is reawaken from SLEEP mode by initial reset, RTC interrupt, NMI, or other interrupt from an external

device (when WAKEUPWT = 1).

When the CPU is reawaken from SLEEP mode by an interrupt, it enters a program executable state by trap

processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the

address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so

that the reti instruction in the interrupt handling routine branches to the instruction next to slp.

Cause-of-interrupt flags in the interrupt controller (ITC) cannot be set in SLEEP mode as the clock is not supplied

to the ITC in SLEEP mode.

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CMU

Therefore, when the clock is not supplied to the ITC, the interrupt signals from the interrupt sources that have

been enabled to generate an interrupt are input to the CMU through the ITC and used to wake up the CPU from a

standby mode. In this case, the cause-of-interrupt flag is set after the clock has started supplying to the ITC. The

CPU can wake up from SLEEP mode by a cause of interrupt as described above even if the PSR is set to disable

interrupts, note however, that the CPU does not execute the interrupt handling routine.

The #NMI signal releases the CPU from SLEEP mode when it goes low level even if the NMI detection mode has

been set to edge detection mode.

Note: In SLEEP mode, there is a time lag between input of an interrupt signal for wakeup and the start

of the clock supply to the ITC, so a delay will occur until the interrupt controller (ITC) sets the

cause-of-interrupt flag. Therefore, no interrupt will occur if the interrupt signal is deasserted before

the clock is supplied to the ITC, as the cause-of-interrupt flag in the ITC is not set.

Furthermore, additional time is needed for the CPU to accept the interrupt request from the ITC,

the CPU may execute a few instructions that follow the slp instruction before it starts the interrupt

processing.

The same problem may occur when the CPU wakes up from SLEEP mode by NMI. No interrupt

will occur if the #NMI signal is deasserted before the clock is supplied, as the NMI flag is not set.

Stopping OSC3 oscillation and waiting for oscillation stabilization at wakeup

By default, neither the low-speed (OSC1) oscillator circuit nor the high-speed (OSC3) oscillator circuit

stops operating when in SLEEP mode. OSC3 oscillation can be made to stop during SLEEP mode by setting

OSC3OFF (D3/0x48368).

∗ OSC3OFF: OSC3 Disable During SLEEP in the Clock Option Register (D3/0x48368)

Setting OSC3OFF (D3/0x48368) to 1 causes OSC3 oscillation to stop during SLEEP mode. In this case, the

OSC3 oscillator circuit starts oscillating when the CPU is reawaken from SLEEP mode. However, since the

CPU may operate erratically if it starts operating with the OSC3 or PLL clock before the oscillation stabilizes,

an OSC oscillation start wait timer is provided to keep the CPU waiting a while before it starts operating. The

wait time can be set by using OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368).

∗ OSCTM[7:0]: OSC Oscillation Stabilization-Wait Timer in the Clock Option Register (D[15:8]/0x48368)

∗ TMHSP: Stabilization-Wait Timer High-Speed Mode Select Bit in the Clock Option Register (D2/0x48368)

Table II.3.12.3.1 Oscillation Stabilization Wait Time at Wakeup

TMHSP

OSCTM[7:0]

0x0

0x1

0x2

0xFF

0x0

0x1

0x2

0xFF

Time

800 ns

1.6 µs

0.204 ms

0.409 ms

0.819 ms

104.5 ms

Number of clocks

4080

8192

16384

(The time shown here is an example when operating with a 20 MHz OSC3.)

SLEEP control when clock sources are switched over

When the CPU reawakes from SLEEP mode, the clock sources (OSC3, OSC1, or PLL) also are switched over

depending on how OSCSEL[1:0] (D[3:2]/0x48360) is set. Before the clock sources can be switched over, the

CPU must be placed once in SLEEP mode, then released. Therefore, a function is provided that automatically

reawakes the CPU from SLEEP mode without using an interrupt, etc. To use this function, set WAKEUPWT

(D0/0x48368) to 0. (By default, it is set to 1.)

∗ WAKEUPWT: Wakeup-Wait Function Enable Bit in the Clock Option Register (D0/0x48368)

When the slp instruction is executed with WAKEUPWT (D0/0x48368) set to 0, the CPU automatically

reawakes from SLEEP mode several 10 clock cycles after that time, then restarts with the source clock selected

by OSCSEL[1:0] (D[3:2]/0x48360) after the oscillation stabilization time described above has elapsed.

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II-3-20 EPSON S1C33401 TECHNICAL MANUAL

The OSC oscillation start wait timer configured using OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/

0x48368) is effective even if WAKEUPWT (D0/0x48368) is 0. To restart the CPU in the shortest time possible,

set OSCTM[7:0] (D[15:8]/0x48368) to 0x0 and TMHSP (D2/0x48368) to 1.

When WAKEUPWT (D0/0x48368) is set to 1, the CPU is reawaken from SLEEP mode by initial reset, RTC

interrupt, NMI, or other interrupt from an external device.

For details about clock switchover and SLEEP control procedures, see Section II.3.13, “Clock Setup Procedure.”

II.3.12.4 Precautions

Interrupt

The standby mode is released by an interrupt from the ITC, NMI, or reset. Note that the ITC must be configured

so that the interrupt to be used for releasing the standby mode can be generated to the CPU. When the clock has

not been supplied to the ITC, the interrupt signal from the interrupt source that has been enabled to interrupt is

passed through the ITC and is input to the CMU. This signal is used to release the standby mode and to start

supplying clocks. The ITC can operate with the supplied clock in HALT or HALT2 mode, so the cause-of-

interrupt flag is set immediately after the interrupt source asserts the interrupt signal and the ITC requests an

interrupt to the CPU without a delay. In SLEEP mode, the ITC will be able to set the cause-of-interrupt flag

and to request an interrupt to the CPU after the CMU starts supplying the clock to the ITC. Therefore, the delay

in the interrupt request to the CPU after waking up from SLEEP mode may cause the CPU to execute a few

instructions that follows the slp instruction before the CPU executes the interrupt processing. Moreover, if the

interrupt source deasserts the interrupt signal before the CMU starts supplying the clock to the ITC, an interrupt

does not occur since the cause-of-interrupt flag is not set. The IE and IL[3:0] bits in the CPU's PSR register do

not affect the releasing of standby mode by an interrupt. For example, by setting the ITC to enable the interrupt

used for releasing and setting the IE bit to disable interrupts, the CPU can wake up from SLEEP mode without

an interrupt processing.

Oscillator circuits

When OSC3 oscillation is set to stop during SLEEP mode, the OSC3 oscillator circuit starts oscillating upon

exiting SLEEP mode. This is because the high-speed (OSC3) oscillator circuit requires a finite time before its

oscillation stabilizes after starting operation. To restart the CPU using the OSC3 or PLL as the source clock,

OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368) must be properly set so that the CPU starts

operating after this oscillation stabilization time elapses. When using the PLL, note that the PLL requires a

lock-in time (e.g., 200 µs in the S1C33401) after OSC3 oscillation has stabilized. The oscillation start time of

the high-speed (OSC3) oscillator circuit varies with the device used, board patterns, and operating environment.

Therefore, the set time above should have a sufficient allowance.

Bus and DMA

When in standby mode, the bus control unit stops operating after the bus cycle in progress is completed. All

chip enable signals become inactive.

In HALT mode, the BBCU is active, so the bus clock signals can be output and the DMA can also be run.

In HALT2 and SLEEP modes, BBCU is inactive, so no bus clock signals are output, nor is the DMA active.

Be sure to disable the HSDMA and IDMA before setting the chip in SLEEP mode (executing the slp

instruction). HALT and HALT2 mode can be set even if the HSDMA and/or IDMA are enabled.

Switching over the clock sources

Use the automatic SLEEP cancellation function when executing the slp instruction for switching over the clock

sources. When the SLEEP mode is cancelled, the OSC oscillation start wait timer that has been configured

using OSCTM[7:0] (D[15:8]/0x48368) starts operating with the clock source after switch over. Use the

switched clock frequency for calculating the oscillation wait time.

Other

The status of the core CPU registers and input/output ports are retained even during standby mode. The contents

of the control and data registers in internal peripheral circuits are also basically retained, but some contents are

altered upon entering SLEEP mode. See the description of each peripheral circuit.

When placing the CPU in SLEEP mode (with WAKEUPWT (D0/0x48368) = 1), be sure to set CCLK and

PCLK to the same divide ratio before executing the slp instruction. If CCLK and PCLK are set to different

divide ratios, the CPU may not operate normally after returning from SLEEP mode.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-21

CMU

II.3.13 Clock Setup Procedure

This section describes the procedure for setting up clocks or altering clock settings.

When initially reset, the clocks are set to the following states:

OSC3 oscillator circuit: On

PLL: Off

OSC1 oscillator circuit: On

System clock source: OSC3

CCLK: OSC3 divided by 1

PCLK: OSC3 divided by 1

CMU_CLK: OSC3 divided by 1

II.3.13.1 Changing the Clock Source from OSC3 to PLL

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. PLLPOWR (D0/0x40184) = 0

Turn off the PLL.

3. Setting PLL Control Register 1 (0x40184)

• PLLN[3:0] (D[7:4]) = 0b0000–0b1111

Set the frequency multiplication rate of the PLL (x1 to x16).

• PLLV[1:0] (D[3:2]) = 0b01–0b11

Set the W value of the PLL (2, 4 or 8).

4. Setting PLL Control Register 2 (0x40185)

• PLLVC[3:0] (D[7:4]) = 0b0001–0b1000

Set the VCO Kv circuit constant.

• PLLRS[3:0] (D[3:0]) = 0b1000 or 0b1010

Set the LPF resistance value.

5. PLLPOWR (D0/0x40184) = 1

Turn on the PLL.

6. OSCSEL[1:0] (D[3:2]/0x48360) = 0b11

Select the PLL for the clock source.

7. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = ∗ ∗ Set appropriate values so that the wait timer exceeds the stabilization time

• OSC3OFF (D3) = 0 of the PLL output clock (e.g. 200 µs in the S1C33401). Be aware that the

• TMHSP (D2) = ∗ wait timer operates with the PLL clock. For details about the PLL output

• HALTMD (D1) = 0 or 1 stabilization time, see “Electrical Characteristics.”

• WAKEUPWT (D0) = 0

This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed

without waiting for an interrupt.

8. Stop any peripheral circuits that are operating, except the RTC.

9. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens

from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using the

PLL as the clock source.

10. Newly setting the clock control registers again

Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required.

11. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

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II-3-22 EPSON S1C33401 TECHNICAL MANUAL

II.3.13.2 Changing the Clock Source from PLL to OSC3,

then Turning Off the PLL

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. OSCSEL[1:0] (D[3:2]/0x48360) = 0b00

Select OSC3 for the clock source.

3. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = 0x0

• OSC3OFF (D3) = 0

• TMHSP (D2) = 1

• HALTMD (D1) = 0 or 1

• WAKEUPWT (D0) = 0

This setting causes the CPU to automatically exit SLEEP mode and restart in the shortest time possible

(several 10 clock cycles) without waiting an interrupt.

4. Stop any peripheral circuits that are operating, except the RTC.

5. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakes

from SLEEP mode several 10 clock cycles after the slp instruction is executed, and restarts using OSC3 as the

clock source.

6. PLLPOWR (D0/0x40184) = 0

Turn off the PLL.

7. Newly setting the clock control registers again

Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required.

8. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

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CMU

II.3.13.3 Changing the Clock Source from OSC3 or PLL to OSC1,

then Turning Off OSC3 and PLL

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. SOSC1 (D0/0x48360) = 1

Turn on the OSC1 oscillator circuit if turned off.

3. OSCSEL[1:0] (D[3:2]/0x48360) = 0b01

Select OSC1 for the clock source.

4. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = ∗ ∗ Set appropriate values so that the wait timer exceeds the stabilization time

• OSC3OFF (D3) = 0 of OSC1 oscillation (e.g., 3 seconds in the S1C33401). Be aware that the

• TMHSP (D2) = ∗ wait timer operates with the OSC1 clock. For details about the OSC1

• HALTMD (D1) = 0 or 1 oscillation start time, see “Electrical Characteristics.”

• WAKEUPWT (D0) = 0

This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed

without waiting for an interrupt.

5. Stop any peripheral circuits that are operating.

6. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens

from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using OSC1

as the clock source.

7. PLLPOWR (D0/0x40184) = 0

Turn off the PLL.

8. SOSC3 (D1/0x48360) = 0

Turn off the OSC3 oscillator circuit.

9. Newly setting the clock control registers again

Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required.

10. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

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II-3-24 EPSON S1C33401 TECHNICAL MANUAL

II.3.13.4 Changing the Clock Source from OSC1 to OSC3

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. SOSC3 (D1/0x48360) = 1

Turn on the OSC3 oscillator circuit if turned off.

3. OSCSEL[1:0] (D[3:2]/0x48360) = 0b00

Select OSC3 for the clock source.

4. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = ∗ ∗ Set appropriate values so that the wait timer exceeds the stabilization time

• OSC3OFF (D3) = 0 of OSC3 oscillation (e.g., 25 ms in the S1C33401). Be aware that the

• TMHSP (D2) = ∗ wait timer operates with the OSC3 clock. For details about the OSC3

• HALTMD (D1) = 0 or 1 oscillation start time, see “Electrical Characteristics.”

• WAKEUPWT (D0) = 0

This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed

without waiting for an interrupt.

5. Stop any peripheral circuits that are operating, except the RTC.

6. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens

from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using OSC3

as the clock source.

7. Newly setting the clock control registers again

Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers newly again, as

required.

8. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

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S1C33401 TECHNICAL MANUAL EPSON II-3-25

CMU

II.3.13.5 Changing the Clock Source from OSC1 to PLL

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. SOSC3 (D1/0x48360) = 1

Turn on the OSC3 oscillator circuit if turned off.

3. Wait until OSC3 oscillation stabilizes (only when OSC3 has been turned on; e.g., 25 ms in the S1C33401). For

details about the OSC3 oscillation start time, see “Electrical Characteristics.”

4. PLLPOWR (D0/0x40184) = 0

Turn off the PLL.

5. Setting PLL Control Register 1 (0x40184)

• PLLN[3:0] (D[7:4]) = 0b0000–0b1111

Set the frequency multiplication rate of the PLL (x1 to x16).

• PLLV[1:0] (D[3:2]) = 0b01–0b11

Set the W value of the PLL (2, 4 or 8).

6. Setting PLL Control Register 2 (0x40185)

• PLLVC[3:0] (D[7:4]) = 0b0001–0b1000

Set the VCO Kv circuit constant.

• PLLRS[3:0] (D[3:0]) = 0b1000 or 0b1010

Set the LPF resistance value.

7. PLLPOWR (D0/0x40184) = 1

Turn on the PLL.

8. OSCSEL[1:0] (D[3:2]/0x48360) = 0b11

Select PLL for the clock source.

9. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = ∗ ∗ Set appropriate values so that the wait timer exceeds the stabilization time

• OSC3OFF (D3) = 0 of the PLL output clock (e.g. 200 µs in the S1C33401). Be aware that the

• TMHSP (D2) = ∗ wait timer operates with the PLL clock. For details about the PLL output

• HALTMD (D1) = 0 or 1 stabilization time, see “Electrical Characteristics.”

• WAKEUPWT (D0) = 0

This setting causes the CPU to automatically exit SLEEP mode and restart after the set time has passed

without waiting for an interrupt.

10. Stop any peripheral circuits that are operating, except the RTC.

11. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output. The CPU automatically reawakens

from SLEEP mode after the set time has passed from execution of the slp instruction, and restarts using the

PLL as the clock source.

12. Newly setting the clock control registers again

Newly alter the CCLK, PCLK, or CMU_CLK settings, and set other clock control registers again, as required.

13. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-26 EPSON S1C33401 TECHNICAL MANUAL

II.3.13.6 Turning Off OSC3 during SLEEP

To turn off OSC3 oscillation during SLEEP mode when operating with OSC3 or PLL as the clock source, follow

the control procedure described below.

1. If the current clock source is PLL, it must be changed to OSC3 and the PLL turned off (see note below).

See Section II.3.13.2, “Changing the Clock Source from PLL to OSC3, then Turning Off the PLL,” for the

procedure to change the clock source.

Stop PLL even if the current clock source is OSC3.

2. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

3. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) and TMHSP (D2)

Set the wait time until the oscillation stabilizes after exiting SLEEP mode.

Example: TMHSP = 1, OSCTM[7:0] = 0x40 (wait time = about 26 ms when OSC3 = 20 MHz)

• OSC3OFF (D3/0x48368) = 1

Turn off OSC3 oscillation when in SLEEP mode.

• WAKEUPWT (D0/0x48368) = 1

Set the CPU to awake from SLEEP mode by using an RTC interrupt, NMI, or other interrupt from an

external device.

4. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

5. Stop any peripheral circuits that are operating, except the RTC.

6. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output.

The CPU is reawaken from SLEEP mode by an RTC interrupt, forced break from the debugger, NMI, or other

interrupt from an external device. After the set oscillation start wait time elapses, the CPU restarts using the

same clock source (OSC3) that was selected before entering SLEEP mode.

7. If the application needs PLL as the clock source, change the clock source to PLL after the CPU wakes up with

the OSC3 clock (see note below).

See Section II.3.13.1, “Changing the Clock Source from OSC3 to PLL,” for the procedure to change the clock

source.

Note: To turn the OSC3 oscillation off in SLEEP mode, the conditions shown below must be satisfied

before entering SLEEP mode and at wakeup from SLEEP mode.

• The CPU operates with OSC3 as the clock source.

• The PLL has been turned off.

If both OSC3 and PLL turn on at wakeup from SLEEP mode and the CPU starts operating with

PLL as the clock source, the PLL operation may become unstable.

Therefore, to set PLL as the clock source, steps 1 and 7 above are required.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-27

CMU

II.3.13.7 SLEEP Keeping Oscillation On (without Clock Change)

To enter SLEEP mode without a clock source change and turning off the oscillation, follow the control procedure

described below. This is the control to reduce power consumption as much as possible by stopping the core and

peripheral functions, with no restart time penalty.

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. Setting the Clock Option Register (0x48368)

• OSCTM[7:0] (D[15:8]) = 0x0

• OSC3OFF (D3) = 0

• TMHSP (D2) = 1

• HALTMD (D1) = 0 or 1

• WAKEUPWT (D0) = 1

This setting causes the CPU to exit SLEEP mode using an RTC interrupt, NMI, or other interrupt from an

external device, and to restart in the shortest time possible (several 10 clock cycles).

3. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

4. Stop any peripheral circuits that are operating, except the RTC.

5. Execute the slp instruction.

The chip enters SLEEP mode and the CMU temporarily stops clock output.

The CPU is brought out of SLEEP mode by an RTC interrupt, forced break from the debugger, NMI, or other

interrupt from an external device, and it restarts using the clock source selected with OSCSEL[1:0] (D[3:2]/

0x48360).

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-28 EPSON S1C33401 TECHNICAL MANUAL

II.3.13.8 HALT/HALT2

To enter HALT/HALT2 mode, follow the control procedure described below. This is the control to reduce power

consumption by stopping the core.

1. Clock Control Protect Register (0x4836E) = 0x96

Disable write protection of the clock control registers.

2. Setting the Clock Option Register (0x48368)

• HALTMD (D1) = 0 Specifies HALT mode that stops the CPU, CCU, MMU, HBCU, and A0RAM.

= 1

Specifies HALT2 mode that stops DMA, BBCU, and EBCU as well as the modules above.

OSCTM[7:0] (D[15:8]), OSC3OFF (D3), TMHSP (D2), and WAKEUPWT (D0) are irrelevant to HALT/

HALT2 mode.

3. Clock Control Protect Register (0x4836E) = other than 0x96

Reenable write protection of the clock control registers.

4. Execute the halt instruction.

The chip enters HALT or HALT2 mode according to the setting of HALTMD (D1/0x48368).

The CPU exits from HALT/HALT2 mode by an interrupt, forced break from the debugger or NMI.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-29

CMU

II.3.14 Power-Down Control

The amount of current consumed on the chip varies significantly with the CPU operation mode, operating clock

frequency, and peripheral circuit to be operated. The following summarizes points on how to reduce power

consumption on the chip.

1. Reducing the operating clock frequency as much as possible

The CMU allows one of the three available clock sources to be selected, and the clock frequency to be set

independently for the core and peripheral circuit. (See II.3.4 to II.3.10.)

Reduce the operating clock frequency to as low a frequency as permitted for the intended processing content of

the system.

• When the OSC1 clock can suffice, turn off the PLL and OSC3, and use only OSC1 to operate the system.

• When the OSC3 clock can suffice (although high-speed processing is needed), turn off the PLL and use

OSC3 to operate the system.

• When the PLL is needed, use it with as small a frequency multiplication rate as possible.

• The divide ratios with which to generate CCLK and PCLK from the source clock can be selected separately.

Select the lowest divide ratios permitted for the intended processing content. For example, PCLK may be

fixed to 20 MHz for use in serial communication, whereas CCLK may be dynamically changed to 66 MHz

when used for multimedia processing or 10 MHz when used for key input processing. However, if the CPU

is to be placed in SLEEP mode, CCLK and PCLK should be set to the same divide ratio before executing the

slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate normally after

returning from SLEEP mode.

• Some peripheral circuits may use the prescaler, while others have an exclusive clock control function

incorporated in the module. For details, refer to the description of each peripheral circuit.

2. Turning off unnecessary clock supply

The CMU allows CCLK and PCLK supplies to be turned on or off independently for each functional block. (See

II.3.9.)

• Turn off clock supplies for unused functional blocks.

• Some peripheral circuits may use the prescaler, while others have an exclusive clock control function

incorporated in the module. For details, refer to the description of each peripheral circuit.

• The function used to automatically control clock supply to each block should be turned on while in use as

much as possible. However, this function is subject to limitations on operating clock frequency. It can only be

turned on when CCLK is 50 MHz or less.

3. Placing the CPU in standby mode

Place the CPU in standby mode by executing the halt or slp instruction as much as possible when, for example,

waiting for key input. (See II.3.12.)

•

Optimum power saving effects may be obtained by placing the CPU in SLEEP mode whenever OSC3 oscillation

is turned off. In such case, however, basically only the RTC can be used without other peripheral circuits.

• To wake CPU quickly from SLEEP mode with no oscillation stabilization time inserted, enter SLEEP mode

after setting OSC3 so that it does not stop in SLEEP mode. The core and peripheral circuits other than RTC

and OSC3 cell unit enter power-down state.

• When peripheral circuits must be operated, use the halt instruction to place the CPU in HALT mode (HALTMD

(D1/0x48368) = 0) or HALT2 mode (HALTMD (D1/0x48368) = 1). In HALT mode, the CPU, CCU, MMU,

HBCU, and A0RAM all stop operating. In HALT2 mode, the BBCU, EBCU, and DMA also stop operating,

in addition to the above. When the BBCU, EBCU, and DMA can be stopped, use HALT2 mode to obtain

better power saving effects.

4. Turning off unnecessary external port pull-ups

When input ports are driven to low level, their pull-up resistors consume some amount of current. Use the pull-

up control register provided for each S1C33 model to turn off unnecessary pull-ups. However, care should be

taken to prevent the input ports from becoming left open (floating state).

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-30 EPSON S1C33401 TECHNICAL MANUAL

II.3.15 Details of Control Registers

Table II.3.15.1 List of CMU Registers

Address

0x00040180

0x00040181

0x00040184

0x00040185

0x00040186

0x00040187

0x00040188

0x00048360

0x00048362

0x00048364

0x00048366

0x00048368

0x0004836A

0x0004836C

0x0004836E

0x00048370

0x00048372

Function

Control clock supply for peripheral circuit modules 1

Control clock supply for peripheral circuit modules 2

Set PLL constant 1, on/off control

Set PLL constant 2

Set PLL constant 3

Control SSCG on and off

Set SSCG parameters

Set core system clock

Control clock supply for core block modules

Automatically control clock supply for core block modules

Set peripheral circuit and external bus clocks

Configure standby mode

NMI status

Set NMI detection mode

Enable/disable write protection of clock control registers

Control clock supply for CCLK system peripheral

modules

Automatically control clock supply for CCLK system

peripheral modules

Peripheral Clock Control Register 1

(pCMU1_CLKCNTL_0)

Peripheral Clock Control Register 2

(pCMU1_CLKCNTL_1)

PLL Control Register 1 (pCMU1_PLL_CNTL0)

PLL Control Register 2 (pCMU1_PLL_CNTL1)

PLL Control Register 3 (pCMU1_PLL_CNTL2)

SS Macro Control Register 1 (pCMU1_SS_CNTL0)

SS Macro Control Register 2 (pCMU1_SS_CNTL1)

Core System Clock Control Register

(pCMU2_CNTL_CORE)

Core System Clock On/Off Register (pCMU2_SET)

Core System Clock Automatic Control Register

(pCMU2_AUTO)

Peripheral and External Bus Clock Control Register

(pCMU2_CNTL_PERI)

Clock Option Register (pCMU2_OPT)

NMI Flag Register (pCMU2_NMI_FLAG)

NMI Mode Register (pCMU2_NMI_MODE)

Clock Control Protect Register (pCMU2_PROTECT)

CCLK System Peripheral Clock On/Off Register

(pCMU2_CCLK_PERI)

CCLK System Peripheral Clock Automatic Control

Size

The following describes each CMU control register.

Addresses 0x40180 through 0x40188 are mapped to the 8-bit device area, and can be accessed in units of bytes.

Addresses 0x48360 through 0x48372 are mapped to the 16-bit device area, and can be accessed in units of

halfwords or bytes.

Note: The CMU registers (0x40180–0x40188, 0x48360–0x4836C, 0x48370, and 0x48372) are write-

protected. Before these register can be rewritten, write protection must be removed by writing

data 0x96 to the Clock Control Protect Register (0x4836E). Note that since unnecessary rewrites

to addresses 0x40180–0x40188 and 0x48360–0x48372 could lead to erratic system operation,

the Clock Control Protect Register (0x4836E) should be set to other than 0x0096 (HW) unless

said CMU control registers must be rewritten.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-31

CMU

0x40180: Peripheral Clock Control Register 1 (pCMU1_CLKCNTL_0)

Name

Address

PSCCLK

ADCCLK

–

SIOCLK

T16CLK

T8CLK

–

ITCCLK

Prescaler clock control

A/D converter clock control

reserved

Serial I/F clock control

16-bit timer clock control

8-bit timer clock control

reserved

ITC clock control

R/W

0040180

(B)

Peripheral

clock

control

(pCMU1

_CLKCNTL_0)

Protected

1On 0Off

1100

1On 0Off

Note: Although the clock control functions implemented by this register are incorporated, not all

peripheral circuits may be incorporated in some S1C33 models.

D7 PSCCLK: Prescaler Clock Control Bit

Controls clock (PCLK) supply to the prescaler.

1 (R/W): On (default)

0 (R/W): Off

D6 ADCCLK: A/D Converter Clock Control Bit

Controls clock (PCLK) supply to the A/D converter.

1 (R/W): On (default)

0 (R/W): Off

D5 Reserved

D4 SIOCLK: Serial Interface Clock Control Bit

Controls clock (PCLK) supply to the serial interface.

1 (R/W): On (default)

0 (R/W): Off

D3 T16CLK: 16-bit Timer Clock Control Bit

Controls clock (PCLK) supply to the 16-bit timer.

1 (R/W): On (default)

0 (R/W): Off

D2 T8CLK: 8-bit Timer Clock Control Bit

Controls clock (PCLK) supply to the 8-bit timer.

1 (R/W): On (default)

0 (R/W): Off

D1 Reserved

D0 ITCCLK: ITC Clock Control Bit

Controls clock (PCLK) supply to the ITC.

1 (R/W): On (default)

0 (R/W): Off

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-32 EPSON S1C33401 TECHNICAL MANUAL

0x40181: Peripheral Clock Control Register 2 (pCMU1_CLKCNTL_1)

Name

Address

–

INTCLK

WDTCLK

CARDCLK

–

POT1CLK

D7–5

reserved

Interrupt generation clock control

Watchdog timer clock control

Card I/F clock control

reserved

Port clock control

–

R/W

0 when being read.

0040181

(B)

–

Peripheral

clock

control

(pCMU1

_CLKCNTL_1)

Protected

1On 0Off

1100

Note: Although the clock control functions implemented by this register are incorporated, not all

peripheral circuits may be incorporated in some S1C33 models.

D[7:5] Reserved

D4 INTCLK: Interrupt Generation Clock Control Bit

Controls clock (PCLK) supply to the interrupt generation function module.

1 (R/W): On (default)

0 (R/W): Off

D3 WDTCLK: Watchdog Timer Clock Control Bit

Controls clock (PCLK) supply to the watchdog timer.

1 (R/W): On (default)

0 (R/W): Off

D2 CARDCLK: Card Interface Clock Control Bit

Controls clock (PCLK) supply to the card interface.

1 (R/W): On (default)

0 (R/W): Off

D1 Reserved

D0 POT1CLK: Port Clock Control Bit

Controls clock (PCLK) supply to the input/output port.

1 (R/W): On (default)

0 (R/W): Off

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-33

CMU

0x40184: PLL Control Register 1 (pCMU1_PLL_CNTL0)

Name

Address

1On 0Off

PLLN3

PLLN2

PLLN1

PLLN0

PLLV1

PLLV0

–

PLLPOWR

PLL multiplication rate setup

PLL V-divider setup

reserved

PLL on/off control

–

R/W

–

R/W

0 when being read.

0040184

(B)

PLL control

(pCMU1_PLL

_CNTL0)

Protected

PLLN[3:0]

1111

1110

0001

0000

Multiplication rate

x16

x15

PLLV[1:0]

Not allowed

–

Note: When D[7:2] in this register must be altered, turn off the PLL (PLLPOWR (D0) = 0) before

changing the bits.

D[7:4] PLLN[3:0]: PLL Multiplication Rate Setup Bits

Sets the frequency multiplication rate of the PLL. (Default: 0b0000 = x1)

PLL frequency multiplication rate = PLLN[3:0] + 1 (x1 to x16)

D[3:2] PLLV[1:0]: PLL V-Divider Setup Bits

Sets the W value so that the fVCO frequency obtained by <output clock frequency × W> falls within the

range of 100 to 400 MHz.

Table II.3.15.2 Settings of the W Value

PLLV1

PLLV0

Not allowed

(Default: 0b01 = 2)

D1 Reserved

D0 PLLPOWR: PLL On/Off Control Bit

Turns the PLL on or off.

1 (R/W): On

0 (R/W): Off (default)

Up to 200 µs is required before the output clock of the PLL stabilizes after PLLPOWR is set to 1.

Provide this wait time in a program before changing the clock source for the system to the PLL.

When not using the PLL, turn off the PLL (power-down mode) to reduce the amount of current

consumed on the chip.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-34 EPSON S1C33401 TECHNICAL MANUAL

0x40185: PLL Control Register 2 (pCMU1_PLL_CNTL1)

Name

Address

PLLVC3

PLLVC2

PLLVC1

PLLVC0

PLLRS3

PLLRS2

PLLRS1

PLLRS0

PLL VCO Kv setup

PLL LPF resistance setup

R/W

0040185

(B)

PLL control

(pCMU1_PLL

_CNTL1)

Protected

PLLVC[3:0]

1000

0111

0110

0101

0100

0011

0010

0001

Other

fVCO [MHz]

360 < fVCO ≤ 400

320 < fVCO ≤ 360

280 < fVCO ≤ 320

240 < fVCO ≤ 280

200 < fVCO ≤ 240

160 < fVCO ≤ 200

120 < fVCO ≤ 160

100 ≤ fVCO ≤ 120

Not allowed

PLLRS[3:0]

1010

1000

Other

fREFCK [MHz]

5 ≤ fREFCK < 20

20 ≤ fREFCK ≤ 150

Not allowed

Note: When this register must be altered, turn off the PLL (PLLPOWR (D0/0x40184) = 0) before

changing the bits.

D[7:4] PLLVC[3:0]: PLL VCO Kv Setup Bits

Sets the VCO Kv circuit constant (VC value) according to the range of fVCO frequencies obtained by

<output clock frequency × W>.

Table II.3.15.3 Settings of the VC Value

PLLVC3

Other

PLLVC2

fVCO [MHz]

360 < fVCO ≤ 400

320 < fVCO ≤ 360

280 < fVCO ≤ 320

240 < fVCO ≤ 280

200 < fVCO ≤ 240

160 < fVCO ≤ 200

120 < fVCO ≤ 160

100 ≤ fVCO ≤ 120

Not allowed

PLLVC1

PLLVC0

(Default: 0b0001)

D[3:0] PLLRS[3:0]: PLL LPF Resistance Setup Bits

Sets the LPF resistance value of the PLL (RS value) according to the input clock (OSC3) frequency.

Table II.3.15.4 Settings of the RS Value

PLLRS3

Other

PLLRS2

fREFCK [MHz]

5 ≤ fREFCK < 20

20 ≤ fREFCK ≤ 150

Not allowed

PLLRS1

PLLRS0

(Default: 0b1000)

Table II.3.15.5 Example PLL Settings

PLL input clock (OSC3)

5 MHz

10 MHz

20 MHz

33 MHz

PLL output clock

65 MHz

60 MHz

40 MHz

60 MHz

40 MHz

60 MHz

40 MHz

66 MHz

PLLN[3:0]

x13, 0b1100

x12, 0b1011

x8, 0b0111

x6, 0b0101

x4, 0b0011

x3, 0b0010

x2, 0b0001

PLLV[1:0]

0b01

0b10

0b01

0b10

0b01

0b10

0b01

PLLVC[3:0]

0b0010

0b0001

0b0010

0b0001

0b0010

0b0001

0b0010

PLLRS[3:0]

0b1010

0b1000

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-35

CMU

0x40186: PLL Control Register 3 (pCMU1_PLL_CNTL2)

Name

Address

PLLCS1

PLLCS0

PLLBYP

PLLCP4

PLLCP3

PLLCP2

PLLCP1

PLLCP0

PLL LPF capacitance setup

PLL bypass mode setup

PLL Charge Pump current setup

R/W

0040186

(B)

PLL control

(pCMU1_PLL

_CNTL2)

Protected

Fixed at "0" (default)

Fixed at "00" (default)

Fixed at "10000" (default)

Note: This register should be left as at initial reset, without altering its settings while in use.

D[7:6] PLLCS[1:0]: PLL LPF Capacitance Setup Bits

Sets the LPF capacitance value (CS value). (Default: 0b00)

D5 PLLBYP: PLL Bypass Mode Setup Bit

Sets PLL bypass mode. (Default: 0)

D[4:0] PLLCP[4:0]: PLL Charge Pump Current Setup Bits

Sets the charge pump current value (CP value). (Default: 0b10000)

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-36 EPSON S1C33401 TECHNICAL MANUAL

0x40187: SS Macro Control Register 1 (pCMU1_SS_CNTL0)

Name

Address

–

SSMCON

D7–1

reserved

SS macro On/Off

–

R/W

0 when being read.

0040187

(B)

SS macro

control register 1

(pCMU1_SS_CNTL0)

Protected

–

1On 0Off

D[7:1] Reserved

D0 SSMCON: SS Macro On/Off Control Bit

This bit turns the SSCG on or off.

1 (R/W): On

0 (R/W): Off (default)

Setting this bit to 1 causes the SSCG to start operating. Setting this bit to 0 causes the SSCG to stop, so

that the clock generator bypasses the SSCG.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-37

CMU

0x40188: SS Macro Control Register 2 (pCMU1_SS_CNTL1)

Name

Address

SSMCITM3

SSMCITM2

SSMCITM1

SSMCITM0

SSMCIDT3

SSMCIDT2

SSMCIDT1

SSMCIDT0

SS macro interval timer (ITM)

setting

SS macro maximum frequency

change width setting

R/W

0040188

(B)

SS macro

control

(pCMU1_SS_CNTL1)

Protected

0 to 0xF

D[7:4] SSMCITM[3:0]: SS Macro Interval Timer Setting Bits

These bits set the frequency change cycle in SS modulation of the SSCG. (See Section II.3.7, “Control

of the SSCG.”)

Always set these bits to 0b0001. (Default: 0b1111)

D[3:0] SSMCIDT[3:0]: SS Macro Maximum Frequency Change Width Setting Bits

These bits set the maximum frequency change width in SS modulation of the SSCG. (See Section

II.3.7, “Control of the SSCG.”)

Table II.3.15.6 Maximum Frequency Change Width Settings

SSMCIDT2

SSMCIDT1

System clock frequency f [MHz]

20.5 < f ≤ 21.7

21.7 < f ≤ 23.0

23.0 < f ≤ 24.5

24.5 < f ≤ 26.1

26.1 < f ≤ 28.0

28.0 < f ≤ 30.3

30.3 < f ≤ 32.8

32.8 < f ≤ 35.9

35.9 < f ≤ 39.6

39.6 < f ≤ 44.2

44.2 < f ≤ 49.9

49.9 < f ≤ 57.4

57.4 < f ≤ 66.0

–

SSMCIDT3

SSMCIDT0

(Default: 0b0000)

Note: SSMCIDT[3:0] must be set according to the system clock frequency as shown in Table

II.3.15.6. Using the SSCG with an improper setting may cause a malfunction of the IC.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-38 EPSON S1C33401 TECHNICAL MANUAL

0x48360: Core System Clock Control Register (pCMU2_CNTL_CORE)

Name

Address

–

CCLKSEL1

CCLKSEL0

–

OSCSEL1

OSCSEL0

SOSC3

SOSC1

D15–11

D10

D7–4

reserved

Core clock (CCLK) selection

reserved

OSC clock selection

High-speed oscillation (OSC3) On/Off

Low-speed oscillation (OSC1) On/Off

1On 0Off

–

R/W

–

R/W

0 when being read.

Writing 1 not allowed.

0 when being read.

0048360

(HW)

CCLKSEL[1:0] CCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

OSCSEL[1:0] Clock source

PLL

OSC3

OSC1

OSC3

–

Core system

clock control

(pCMU2_CNTL

_CORE)

Protected

–

D[15:11] Reserved

D10 Reserved (writing 1 to this bit prohibited)

D[9:8] CCLKSEL[1:0]: Core Clock (CCLK) Select Bits

CCLK is the operating clock for the CPU, core blocks (HBCU, MMU, CCU, and DBG), and modules

connecting to the high-speed bus (DMA, BBCU, EBCU, and internal RAM). It is derived from the

system’s source clock OSC (selected using OSCSEL[1:0] (D[3:2])) by dividing its frequency by a given

value. Use CCLKSEL[1:0] to select this clock divide ratio.

Table II.3.15.7 Selecting CCLK

CCLKSEL1

CCLKSEL0

CCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

(Default: 0b00)

CCLK can be selected at any time. However, since the clocks are switched over when internally in the

chip, all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, and up to 8 clock cycles are

required before the clocks are actually changed after altering the register values.

D[7:4] Reserved

D[3:2] OSCSEL[1:0]: OSC Clock Select Bits

Selects the clock source for the system (OSC).

Table II.3.15.8 Selecting the System Clock Source

OSCSEL1

OSCSEL0

Clock source

PLL

OSC3

OSC1

OSC3

(Default: 0b00)

The clock sources changed here are not switched over immediately, but are actually switched over

upon returning from SLEEP mode. Therefore, the CPU must be placed in SLEEP mode after setting up

OSCSEL[1:0].

Note: When clock sources are changed, the clock control registers must be set so that the CMU

is supplied with a clock from the selected clock source upon returning from SLEEP mode

immediately after the change. Otherwise, the chip does not restart after return from SLEEP

mode.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-39

CMU

D1 SOSC3: High-speed Oscillation (OSC3) On/Off Bit

Turns the OSC3 oscillator circuit on or off.

1 (R/W): On (default)

0 (R/W): Off

D0 SOSC1: Low-speed Oscillation (OSC1) On/Off Bit

Turns the OSC1 oscillator circuit on or off.

1 (R/W): On (default)

0 (R/W): Off

Note: When SOSC3 (D1) or SOSC1 (D0) is set from 0 to 1 for initiating oscillation by the oscillator, a

finite time is required until the oscillation stabilizes. To prevent erratic operation, do not use the

oscillator-derived clock until the oscillation start time stipulated in the electrical characteristics

table elapses.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-40 EPSON S1C33401 TECHNICAL MANUAL

0x48362: Core System Clock On/Off Register (pCMU2_SET)

Name

Address

DBGNCLK

–

DBGCLK

–

HBCUCLK

MMUCLK

CCUCLK

CPUCLK

D15

D14–9

D7–4

DBG NOSTOP clock On/Off

reserved

DBG clock On/Off

reserved

HBCU clock On/Off

MMU clock On/Off

CCU clock On/Off

CPU clock On/Off

1On 0Off

–

R/W

–

R/W

–

R/W

0 when being read.

0048362

(HW)

Core system

clock On/Off

(pCMU2_SET)

Protected

–

D15 DBGNCLK: DBG NOSTOP Clock On/Off Bit

Controls clock (NOSTOP) supply to the debug unit.

1 (R/W): On (default)

0 (R/W): Off

D[14:9] Reserved

D8 DBGCLK: DBG Clock On/Off Bit

Controls clock (CCLK) supply to the debug unit.

1 (R/W): On (default)

0 (R/W): Off

D[7:4] Reserved

D3 HBCUCLK: HBCU Clock On/Off Bit

Controls clock (CCLK) supply to the HBCU.

1 (R/W): On (default)

0 (R/W): Off

D2 MMUCLK: MMU Clock On/Off Bit

Controls clock (CCLK) supply to the MMU.

1 (R/W): On (default)

0 (R/W): Off

D1 CCUCLK: CCU Clock On/Off Bit

Controls clock (CCLK) supply to the CCU.

1 (R/W): On (default)

0 (R/W): Off

D0 CPUCLK: CPU Clock On/Off Bit

Controls clock (CCLK) supply to the CPU.

1 (R/W): On (default)

0 (R/W): Off

Note: Setting CPUCLK to 0 causes the CPU to stop operating, in which case the CPU can only be

restarted by initial reset.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-41

CMU

0x48364: Core System Clock Automatic Control Register (pCMU2_AUTO)

Name

Address

–

DBGAUTO

–

HBCUAUTO

MMUAUTO

CCUAUTO

CPUAUTO

D15–

D7–4

reserved

DBG clock automatic control

reserved

HBCU clock automatic control

MMU clock automatic control

CCU clock automatic control

CPU clock automatic control

1Enabled 0Disabled

–

R/W

–

R/W

0 when being read.

0048364

(HW)

Core system

clock automatic

control register

(pCMU2_AUTO)

Protected

–

D[15:9] Reserved

D8 DBGAUTO: DBG Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the debug

unit.

1 (R/W): Enable (default)

0 (R/W): Disable

D[7:4] Reserved

D3 HBCUAUTO: HBCU Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

HBCU.

1 (R/W): Enable

0 (R/W): Disable (default)

D2 MMUAUTO: MMU Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

MMU.

1 (R/W): Enable

0 (R/W): Disable (default)

D1 CCUAUTO: CCU Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the CCU.

1 (R/W): Enable

0 (R/W): Disable (default)

D0 CPUAUTO: CPU Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the CPU.

1 (R/W): Enable

0 (R/W): Disable (default)

Note: Do not use the clock automatic control function when the operating frequency exceeds 50 MHz.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-42 EPSON S1C33401 TECHNICAL MANUAL

0x48366: Peripheral and External Clock Output Control Register

(pCMU2_CNTL_PERI)

Name

Address

–

CMUCLK2

CMUCLK1

CMUCLK0

–

PCLKSEL1

PCLKSEL0

D15–11

D10

D7–2

reserved

External clock output (CMU_CLK)

selection

reserved

Peripheral clock (PCLK) selection

–

R/W

–

R/W

0 when being read.

∗ before clock tree

0 when being read.

0048366

(HW)

111

110

101

100

011

010

001

000

CMUCLK[2:0] CMU_CLK

PLL

OSC1

OSC3

CCLK(*)

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

PCLKSEL[1:0] PCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

–

Peripheral and

external clock

output control

(pCMU2_CNTL

_PERI)

Protected

–

D[15:11] Reserved

D[10:8] CMUCLK[2:0]: External Clock Output (CMU_CLK) Select Bits

CMU_CLK is the clock for the external bus. It can be selected from the eight clocks listed in Table

II.3.15.9.

Table II.3.15.9 Selecting CMU_CLK

CMUCLK2

CMUCLK1

CMU_CLK

PLL

OSC1

OSC3

CCLK (before clock tree)

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

CMUCLK0

(Default: 0b000)

CMU_CLK can be selected at any time. However, switching over the clocks creates hazards. When

CMU_CLK must be output to external devices, it is also necessary to select a port function. For details

on how to control clock output and about the port to be used, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

D[7:2] Reserved

D[1:0] PCLKSEL[1:0]: Peripheral Clock (PCLK) Select Bits

PCLK is the operating clock for peripheral circuits. It is derived from the system’s source clock OSC

(OSCSEL[1:0] (D[3:2]/0x48360)) by dividing its frequency by a given value. Use PCLKSEL[1:0] to

select this clock divide ratio.

Table II.3.15.10 Selecting PCLK

PCLKSEL1

PCLKSEL0

PCLK

OSC•1/8

OSC•1/4

OSC•1/2

OSC•1/1

(Default: 0b00)

PCLK can be selected at any time. However, since the clocks are switched over internally in the chip

when all the div-by-1 OSC to div-by-8 OSC clocks are in the high state, up to 8 clock cycles are

required before the clocks are actually changed after altering the register values.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-43

CMU

0x48368: Clock Option Register (pCMU2_OPT)

Name

Address

OSCTM7

OSCTM6

OSCTM5

OSCTM4

OSCTM3

OSCTM2

OSCTM1

OSCTM0

–

OSC3OFF

TMHSP

HALTMD

WAKEUPWT

D15

D14

D13

D12

D11

D10

D7–4

OSC oscillation stabilization-wait

timer

reserved

OSC3 disable during SLEEP

Wait-timer high-speed mode

HALT mode selection

Wakeup-wait function enable 1

Wait interrupt

0No wait

1HALT2 0HALT

1High speed 0Normal

1Stop 0Run

–

R/W

–

R/W

0 when being read.

0048368

(HW)

–

Clock option

(pCMU2_OPT)

Protected

0 to 255

D[15:8] OSCTM[7:0]: OSC Oscillation Stabilization-Wait Timer

Sets an oscillation stabilization wait time during which the CPU is kept waiting before it starts operating

upon returning from SLEEP mode. This wait time can be set in increments of 16 OSC clock cycles

when TMHSP (D2) = 1, or 8,192 clock cycles when TMHSP (D2) = 0. (Default: 0b00 = no wait time)

Table II.3.15.11 Oscillation Stabilization Wait Time at Wakeup

TMHSP

OSCTM[7:0]

0x0

0x1

0x2

0xFF

0x0

0x1

0x2

0xFF

Time

800 ns

1.6 µs

0.204 ms

0.409 ms

0.819 ms

104.5 ms

Number of clocks

4080

8192

16384

(The time shown here is an example when operating with a 20 MHz OSC3.)

When the OSC3 oscillation is to be turned off during SLEEP mode, make sure the wait time set by these

bits is equal to or greater than the OSC3 oscillation start time stipulated in the electrical characteristics

table.

Note: The OSC oscillation start wait timer operates with the operating clock activated after the

SLEEP mode is released. Therefore, use the switched clock frequency for calculating the

oscillation wait time to be set to OSCTM[7:0] when executing the slp instruction for switching

over the clock sources.

D[7:4] Reserved

D3 OSC3OFF: OSC3 Disable During SLEEP

Selects whether to turn off the OSC3 oscillator circuit during SLEEP mode.

1 (R/W): Stop

0 (R/W): Operating (default)

Continue operating OSC3 when entering SLEEP mode to switch over the clock sources (OSC), or turn

it off when entering SLEEP mode for power-down purposes.

D2 TMHSP: Stabilization-Wait Timer High-Speed Mode Select Bit

Sets count mode for the oscillation stabilization wait timer (OSCTM[7:0]).

1 (R/W): High-speed mode

0 (R/W): Normal mode (default)

The oscillation stabilization wait timer counts from 0 to 2M in units of 8,192 OSC clock cycles during

normal mode, or from 0 to 4,080 in units of 16 OSC clock cycles during high-speed mode. Select either

mode in which the OSC3 oscillation start time can be secured with the OSC frequency used.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-44 EPSON S1C33401 TECHNICAL MANUAL

D1 HALTMD: HALT Mode Select Bit

Selects the standby mode entered into by the halt instruction.

1 (R/W): HALT2 mode

0 (R/W): HALT mode (default)

In HALT mode, the CPU, CCU, MMU, HBCU, and A0RAM all stop operating. In HALT2 mode, the

BBCU, EBCU, and DMA also stop operating, in addition to the above. The other internal peripheral

circuits remain in the state (idle or operating) held when the halt instruction was executed.

D0 WAKEUPWT: Wakeup-Wait Function Enable Bit

Enables the SLEEP mode wakeup-wait function used for switching over the clocks.

1 (R/W): Wait an interrupt

0 (R/W): No wait (default)

When the slp instruction is executed while WAKEUPWT is set to 0, the CPU automatically reawakes

from SLEEP mode several 10 clock cycles after instruction execution, and restarts with the source clock

selected by OSCSEL[1:0] (D[3:2]/0x48360). Since even in this case the oscillation stabilization wait

time set by OSCTM[7:0] (D[15:8]) is effective, OSCTM[7:0] should be set to 0x0 when clocks must be

switched over in the shortest time possible.

When WAKEUPWT is set to 1, the CPU can only be reawaken from SLEEP mode by an interrupt

such as initial reset, RTC interrupt, forced break from the debugger, NMI, and other interrupt from an

external source.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-45

CMU

0x4836A: NMI Flag Register (pCMU2_NMI_FLAG)

Name

Address

–

NMIF

–

D15–13

D12

D11–0

reserved

NMI flag

reserved

NMI occurred

Not occurred

–

R/W

–

0 when being read.

Reset by writing 1.

Writing 1 not allowed.

004836A

(HW)

–

NMI flag register

(pCMU2_NMI_FLAG)

Protected

D[15:13] Reserved

D12 NMIF: NMI Flag

Indicates the status of whether NMI has occurred.

1 (R): NMI occurred

0 (R): No NMI occurred (default)

1 (W): Clear the flag (0)

0 (W): Has no effect

When an NMI request is detected at the #NMI pin, NMIF is set to 1 and an NMI exception is generated.

Writing a 1 resets the NMIF thus set.

Note: NMIF should always be reset by writing a 1 in the NMI exception handler routine. Otherwise,

an NMI exception may be generated again when the NMI exception handler routine is

terminated by the reti instruction.

D[11:0] Reserved (writing a 1 to these bits prohibited)

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-46 EPSON S1C33401 TECHNICAL MANUAL

0x4836C: NMI Mode Register (pCMU2_NMI_MODE)

Name

Address

–

NMIMD

–

D15–9

D7–0

reserved

NMI detection mode

reserved

Low level

Falling edge

–

R/W

–

0 when being read.

Writing 1 not allowed.

004836C

(HW)

–

NMI mode

(pCMU2_NMI_MODE)

Protected

D[15:9] Reserved

D8 NMIMD: NMI Detection Mode Select Bit

Selects the method of detecting whether to recognize NMI request input to #NMI by a falling edge or

low level.

1 (R/W): Low level

0 (R/W): Falling edge (default)

D[7:0] Reserved (writing a 1 to these bits prohibited)

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-47

CMU

0x4836E: Clock Control Protect Register (pCMU2_PROTECT)

Name

Address

–

Writing 10010110 (0x96)

removes the write protection of

the clock control registers

(0x40180–0x40188, 0x48360–

0x4836A, 0x48370, 0x48372).

Writing another value set the

write protection.

–

CLGP7

CLGP6

CLGP5

CLGP4

CLGP3

CLGP2

CLGP1

CLGP0

D15–8

reserved

Clock control register protect flag

–

R/W

0 when being read.

004836E

(HW)

Clock control

protect register

(pCMU2_PROTECT)

D[15:8] Reserved

D[7:0] CLGP[7:0]: Clock Control Register Protect Flag

Enables/disables write protection of the clock control registers (0x40180–0x40188, 0x48360–0x4836A

and 0x48370–0x48372).

0x96 (R/W): Disable write protection

Other than 0x96 (R/W): Write-protect the register (default: 0x0)

Before altering any clock control register, write data 0x96 to the register to disable write protection. If

this register is set to other than 0x96, even if an attempt is made to alter any clock control register by

executing a write instruction, the content of said register will not be altered even though the instruction

may have been executed without a problem. Once this register is set to 0x96, the clock control registers

can be rewritten any number of times until being reset to other than 0x96. When rewriting the clock

control registers has finished, this register should be set to other than 0x96 to prevent accidental writing

to the clock control registers.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-48 EPSON S1C33401 TECHNICAL MANUAL

0x48370: CCLK System Peripheral Clock On/Off Register

(pCMU2_CCLK_PERI)

Name

Address

–

BBEBNCLK

BBHBIFCLK

BBSRAMCLK

BBDBGIFCLK

–

EBCUHBCLK

EBCUSDCLK

A3RAMCLK

DMACLK

SAPB12CCLK

SAPB1PCLK

D15–12

D11

D10

D7–6

reserved

BBCU, EBCU NOSTOP On/Off

BBCU HB I/F clock On/Off

BBCU SRAM clock On/Off

BBCU DBG I/F clock On/Off

reserved

EBCU HB I/F clock On/Off

EBCU SDRAM clock On/Off

A3RAM clock On/Off

DMA clock On/Off

SAPB12C clock On/Off

SAPB1P clock On/Off

1On 0Off

–

R/W

–

R/W

0 when being read.

0048370

(HW)

CCLK system

peripheral

clock On/Off

(pCMU2_CCLK

_PERI)

Protected

–

D[15:12] Reserved

D11 BBEBNCLK: BBCU, EBCU NOSTOP Clock Control Bit

Controls clock (NOSTOP) supply to the BBCU and EBCU.

1 (R/W): On (default)

0 (R/W): Off

D10 BBHBIFCLK: BBCU HB Interface Clock Control Bit

Controls clock (CCLK) supply to the BBCU HB interface.

1 (R/W): On (default)

0 (R/W): Off

D9 BBSRAMCLK: BBCU SRAM Clock Control Bit

Controls clock (CCLK) supply to the BBCU SRAM interface.

1 (R/W): On (default)

0 (R/W): Off

D8 BBDBGIFCLK: BBCU DBG Interface Clock Control Bit

Controls clock (CCLK) supply to the BBCU DBG interface.

1 (R/W): On (default)

0 (R/W): Off

D[7:6] Reserved

D5 EBCUHBCLK: EBCU HB Interface Clock Control Bit

Controls clock (CCLK) supply to the EBCU HB interface.

1 (R/W): On (default)

0 (R/W): Off

D4 EBCUSDCLK: EBCU SDRAM Interface Clock Control Bit

Controls clock (CCLK) supply to the EBCU SDRAM interface.

1 (R/W): On (default)

0 (R/W): Off

D3 A3RAMCLK: A3RAM Clock Control Bit

Controls clock (CCLK) supply to internal RAM in area 3.

1 (R/W): On (default)

0 (R/W): Off

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-49

CMU

D2 DMACLK: DMA Clock Control Bit

Controls clock (CCLK) supply to the DMA block.

1 (R/W): On (default)

0 (R/W): Off

D1 SAPB12CCLK: SAPB12C Clock Control Bit

Controls SAPB12C clock supply.

1 (R/W): On (default)

0 (R/W): Off

D0 SAPB1PCLK: SAPB1P Clock Control Bit

Controls SAPB1P clock supply.

1 (R/W): On (default)

0 (R/W): Off

Note: SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block.

SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop these

clocks as the register read/write operation cannot be performed.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-50 EPSON S1C33401 TECHNICAL MANUAL

0x48372: CCLK System Peripheral Clock Automatic Control Register

(pCMU2_AUTO_CCLK_PERI)

Name

Address

–

BBHBIFAUTO

BBSRAMAUTO

BBDBGIFAUTO

–

EBCUHBAUTO

EBCUSDAUTO

A3RAMAUTO

DMAAUTO

SAPB12CAUTO

SAPB1PAUTO

D15–11

D10

D7–6

reserved

BBCU HB I/F clock auto control

BBCU SRAM clock auto control

BBCU DBG I/F clock auto control

reserved

EBCU HB I/F clock auto control

EBCU SDRAM clock auto control

A3RAM clock auto control

DMA clock auto control

SAPB12C clock auto control

SAPB1P clock auto control

1Enabled 0Disabled

–

R/W

–

R/W

0 when being read.

0048372

(HW)

CCLK system

peripheral

clock automatic

control register

(pCMU2_AUTO

_CCLK_PERI)

Protected

–

D[15:11] Reserved

D10 BBHBIFAUTO: BBCU HB Interface Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

BBCU HB interface.

1 (R/W): Enable

0 (R/W): Disable (default)

D9 BBSRAMAUTO: BBCU SRAM Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

BBCU SRAM interface.

1 (R/W): Enable

0 (R/W): Disable (default)

D8 BBDBGIFAUTO: BBCU DBG Interface Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

BBCU DBG interface.

1 (R/W): Enable

0 (R/W): Disable (default)

D[7:6] Reserved

D5 EBCUHBAUTO: EBCU HB Interface Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

EBCU HB interface.

1 (R/W): Enable

0 (R/W): Disable (default)

D4 EBCUSDAUTO: EBCU SDRAM Interface Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the

EBCU SDRAM interface.

1 (R/W): Enable

0 (R/W): Disable (default)

D3 A3RAMAUTO: A3RAM Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to internal

RAM in area 3.

1 (R/W): Enable

0 (R/W): Disable (default)

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

S1C33401 TECHNICAL MANUAL EPSON II-3-51

CMU

D2 DMAAUTO: DMA Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control clock (CCLK) supply to the DMA

block.

1 (R/W): Enable

0 (R/W): Disable (default)

D1 SAPB12CAUTO: SAPB12C Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control SAPB12C clock supply.

1 (R/W): Enable

0 (R/W): Disable (default)

D0 SAPB1PAUTO: SAPB1P Clock Automatic Control Bit

Enables/disables the hardware function used to automatically control SAPB1P clock supply.

1 (R/W): Enable

0 (R/W): Disable (default)

Notes: • Do not use the clock automatic control function when the operating frequency exceeds 50

MHz.

• SAPB12C is the clock for the registers in the C33 ADV Core Block and C33 ADV Bus Block.

SAPB1P is the clock for the registers in the C33 ADV Basic Peripheral Block. Do not stop

these clocks as the register read/write operation cannot be performed.

II C33 ADV CORE BLOCK: CLOCK MANAGEMENT UNIT (CMU)

II-3-52 EPSON S1C33401 TECHNICAL MANUAL

II.3.16 Precautions

Precautions regarding clock control

• The clock control registers (0x40180–0x40188, 0x48360–0x4836A and 0x48370–0x48372) are write-protected.

Before these registers can be rewritten, write protection must be removed by writing data 0x0096 (HW) to the Clock

Control Protect Register (0x4836E). Once write protection is removed, the clock control registers can be written

to any number of times until the protect register is reset to other than 0x0096 (HW). Note that since unnecessary

rewriting of the clock control registers could lead to erratic system operation, the Clock Control Protect Register

(0x4836E) should be set to other than 0x0096 (HW) unless the clock control registers must be rewritten.

• When clock sources are changed, the clock control registers must be set so that the CMU is supplied with a clock

from the selected clock source upon returning from SLEEP mode immediately after the change. Otherwise, the

chip may not restart after return from SLEEP mode.

Furthermore, note that the timer, which generates an oscillation stabilization wait time after the SLEEP mode is

released, operates with the clock after switching over. Be sure to use the correct clock frequency for calculating

the wait time to be set to OSCTM[7:0] (D[15:8]/0x48368) and TMHSP (D2/0x48368).

• When SOSC3 (D1/0x48360) or SOSC1 (D0/0x48360) is set from 0 to 1 for initiating oscillation by the oscillator,

a finite time is required until the oscillation stabilizes (e.g., 25 ms for OSC3 and 3 seconds for OSC1 in the

S1C33401). To prevent erratic operation, do not use the oscillator-derived clock until the oscillation start time

stipulated in the electrical characteristics table elapses.

• Immediately after the PLL is started by setting PLLPOWR (D0/0x40184) to 1, an output clock stabilization wait

time is required (e.g., 200 µs in the S1C33401). When the clock source for the system is switched over to the

PLL, allow for this wait time after the PLL has turned on.

• The frequency multiplication rate of the PLL that can be set depends on the upper-limit operating clock

frequency of each S1C33 model and the OSC3 oscillation frequency. When setting the frequency multiplication

rate, be sure not to exceed the upper-limit operating clock frequency.

• The PLL can only be set up when the PLL is turned off (PLLPOWR (D0/0x40184) = 0) and the clock source is

other than the PLL (OSCSEL[1:0] (D[3:2]/0x48360) = 0–2). If settings are changed while the system is operating

with the PLL clock, the system may operate erratically.

• When placing the CPU in SLEEP mode, be sure to set CCLK and PCLK to the same divide ratio before

executing the slp instruction. If CCLK and PCLK are set to different divide ratios, the CPU may not operate

normally after returning from SLEEP mode.

Precautions regarding reset input

• Even if the #RESET pin is pulled low (= 0), the chip may not be reset unless supplied with a clock. To reset the

chip for sure, #RESET should be held low for at least 10 OSC3 clock cycles. However, the input/output port pins

will be initialized by cold reset regardless of whether the chip is supplied with a clock.

• The oscillation start time of the high-speed (OSC3) oscillator circuit varies with the device used, board patterns,

and operating environment. Therefore, a sufficient time should be provided before the reset signal is deasserted.

Precautions regarding NMI input

• The NMIF flag (D12/0x4836A) set by an NMI request should always be reset by writing a 1 in the NMI

exception handler routine. Otherwise, an NMI exception may be generated again when the NMI exception

handler routine is terminated by the reti instruction.

• NMI cannot be nested. The CPU keeps NMI input masked out until the reti instruction is executed after an NMI

exception occurred.

Precautions regarding CCLK clock automatic control

Do not use the CCLK clock automatic control function that can be set using the registers at 0x48364 and

0x48372 when the operating frequency exceeds 50 MHz.

Precautions regarding SSCG control

• When using the SSCG, always set SSMCITM[3:0] (D[7:4]/0x40188) to 0b0001.

• SSMCIDT[3:0] (D[3:0]/0x40188) must be set according to the system clock frequency as shown in Table

II.3.7.2.1. Using the SSCG with an improper setting may cause a malfunction of the IC.

• The SSCG is effective only when the PLL is selected as the system clock source. Furthermore, the SSCG control

registers cannot be set when the PLL is inactive.

II C33 ADV CORE BLOCK: HIGH-SPEED BUS CONTROL UNIT (HBCU)

S1C33401 TECHNICAL MANUAL EPSON II-4-1

HBCU

II.4 High-Speed Bus Control Unit (HBCU)

II.4.1 Overview of the HBCU

The High-speed Bus Control Unit (HBCU), which is connected directly to the CPU core, mainly controls the

Cache Control Unit (CCU), Memory Management Unit (MMU), Area 0 Internal No-wait RAM (A0RAM), and bus

modules as it fetches instructions or read/writes data.

The following summarizes the main functions and features of the HBCU.

• Arbitrates bus access requests from the CPU for the cache, A0RAM or other area 0 internal memory, and bus

module.

• Manages a 4GB logical space by dividing it into eight 512MB blocks. Whether to use the cache and MMU,

selecting cache write-back or write-through, and whether to use ASID can be set independently for each block.

• Connected directly to the CPU via a 32-bit data bus, and operating with the same clock as the CPU (basically no-

wait), the HBCU supports high-speed data transfer between the CPU and the cache or A0RAM. Note that two

instructions can be fetched in one clock cycle.

• Capable of mirroring in 1GB units within the 4GB physical space and address processing for replacing the 6

high-order bits with ASID.

• Can read and write data to and from A0RAM at the same time while fetching instructions from the cache, for

high-speed processing.

• Can create 64MB × 64 multiple virtual spaces in the logical address space by using a 6-bit ASID.

C33 ADV CPU

HBCU

A0RAM

(Area 0 No-Wait RAM)

CCU Bus module

(BBCU, etc.)

External

memory

MMU

S1C33 Microcomputer

Figure II.4.1.1 HBCU

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II-4-2 EPSON S1C33401 TECHNICAL MANUAL

II.4.2 Outline of Address Processing

Address processing modules

Figure II.4.2.1 shows the functional modules that process addresses output from the CPU.

CPU

• Outputs logical

addresses to

access a 4GB

linear address

space.

BBCU

•

Decodes physical

addresses to

decide areas

(chip enable) to

access.

• Outputs the

physical address

with the generated

chip enable to

the external bus.

Memories

and

I/O devices

HBCU

• Divides the

logical space

into 8 blocks

and sets the

attribute for

each block.

• Configures

multiple virtual

spaces using

ASID.

MMU

• Translates

logical addresses

into physical

addresses.

• Performs mirror

processing.

CCU

• Physical address

cache after mirror

processing

Figure II.4.2.1 Functional Modules for Address Processing

Address processing flow

CPU

Output of a logical

address to access

a 4GB linear

address space

Setting use or not

use attributes for

MMU, ASID,

instruction cache,

data cache, and

write-back mode

Multiplexing 64

spaces using

6 bits of ASID

CPU output

Block 7 (0.5GB)

Block 6 (0.5GB)

Block 5 (0.5GB)

Block 4 (0.5GB)

Block 3 (0.5GB)

Block 2 (0.5GB)

Block 1 (0.5GB)

Block 0 (0.5GB)

Block processing

63 (64MB)

62 (64MB)

3 (64MB)

2 (64MB)

1 (64MB)

0 (64MB)

ASID processing

HBCU HBCU MMU HBCU

Setting the high-

order 3GB as the

mirror areas of

the low-order 1GB

Mirroring

1GB

Physical

address

cache

Mirror processing

Map 4KB or 64KB

of pages to any

desired physical

addresses

1M/64K (4KB/64KB)

3 (4KB/64KB)

2 (4KB/64KB)

1 (4KB/64KB)

0 (4KB/64KB)

Address translation

(when MMU is used)

When MMU is not used

Logical address Physical address

BBCU

Control of the #CE

signal, wait cycles,

and other access

conditions for each

area

Area 22

(2GB)

Area 21

(1GB)

Area 20

(512MB)

Areas 19–0

(512MB)

Area processing

Figure II.4.2.2 Contents of Address Processing

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HBCU

Address processing for internal peripheral circuits and internal memories

Area 0

Areas 1, 2, and 3

Other than

areas 0–3

Block

processing

External

bus

CPU

ASID

processing

MMU

processing

Mirror

processing

BBCU

A0RAM

Areas 1–3

peripherals/

memories

Peripherals/

memories

in area 6, etc.

Internal bus

Cache

Figure II.4.2.3 Differences on Accesses to Internal Areas and External Areas

Addresses that are mainly output to the external bus to access areas other than areas 0–6 are subject to the

address processing described above. Normally, ASID and MMU are disabled to use in areas 0–6. Furthermore,

these areas are not mirrored. Therefore, the address processing for areas 0–6 is different from the above

description.

A high-speed RAM (A0RAM) is mapped to area 0 and is accessed with no wait cycle using addresses output

from the CPU directly.

Areas 1, 2, and 3 are dedicated to the internal peripheral circuits and memories and block processing to mirror

processing are not performed. Addresses from the CPU pass through the internal bus and directly access the

internal modules mapped to areas 1–3.

Areas 4, 5, and 6 are external memory areas, note, however, that normally block processing to mirror processing

are not performed as in areas 1–3. Addresses from the CPU are directly passed to the BBCU and are output to

the external bus.

Area 6 is often used for embedded modules (model-specific circuits and extension peripheral circuits/

memories) other than the standard peripheral circuits mapped to area 1. Also in this case, addresses from the

CPU are directly passed to the BBCU to access area 6.

Areas 0–6 can be enabled to process their addresses with ASID and MMU by setting the HBCU in user mode

only. Note that these areas cannot be mirrored even in this case.

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II-4-4 EPSON S1C33401 TECHNICAL MANUAL

II.4.3 Managing the Address Space

The C33 ADV CPU has a 4GB address space (logical address space) based on the 32-bit internal address bus.

Conversely, the physical address space has actual devices mapped into it and is accessed by the #CE signal and an

external address bus. When the MMU is not used, the logical address equals the physical address. When the MMU

is used, access to a logical address not equal to the physical address is allowed.

For example, selecting whether to use the MMU collectively for the entire 4GB space may not always be effective

depending on usage conditions. Therefore, the HBCU divides this 4GB of logical space into eight 512MB blocks

from block 0 to block 7 (as shown in Figure II.4.3.1) for management purposes, thus allowing conditions to be set

individually for each block.

Block 7

(512M bytes)

0xFFFF FFFF

0xE000 0000

Block 7

attribute

Block 6

attribute

Block 5

attribute

Block 4

attribute

Block 3

attribute

Block 2

attribute

Block 1

attribute

Block 0

attribute

Block 6

(512M bytes)

0xDFFF FFFF

0xC000 0000

Block 5

(512M bytes)

0xBFFF FFFF

0xA000 0000

Block 4

(512M bytes)

0x9FFF FFFF

0x8000 0000

Block 3

(512M bytes)

0x7FFF FFFF

0x6000 0000

Block 2

(512M bytes)

0x5FFF FFFF

0x4000 0000

Block 1

(512M bytes)

0x3FFF FFFF

0x2000 0000

Block 0

(512M bytes)

0x1FFF FFFF

0x0000 0000

Area 22

2G bytes

Area 21

1G bytes

• MMU Used/Not used

• ASID Used/Not used

• Instruction cache Used/Not used

• Data cache Used/Not used

• Data cache write back Used/Not used

Area 20

512M bytes

Areas 19–0

512M bytes

Logical address space Physical address space

Block attribute (selectable in each block)

Figure II.4.3.1 Divided Logical Space and Relationship with Physical Space

(when not using the MMU, ASID, and mirror functions)

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HBCU

II.4.3.1 Contents of Individual Block Settings

The following settings can be made for each block individually by using the HBCU control registers.

1. Specifying whether to use the MMU

Whether to use the MMU can be specified for each block individually. When MMUENx (x = 0–7) is set to 1,

the MMU is used when accessing block ‘x’, with its logical address translated into the physical address. When

MMUENx = 0 (default), the logical address of block ‘x’ is used directly as the physical address to access the

corresponding device there.

∗ MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2•x)

2. Specifying whether to use the ASID

Whether to use the ASID can be specified for each block individually. When ASIDENx (x = 0–7) is set to 1, the

6 high-order bits of the logical address are replaced with ASID[5:0] (D[5:0]/0x48312) when accessing block ‘x’,

thereby creating multiple virtual spaces. When ASIDENx = 0 (default), the logical address of block ‘x’ is used

directly as is.

∗ ASIDENx: Block x ASID Enable Bit in the Block x Configuration Register (D5/0x48302 + 2•x)

The ASID and logical ASID values (used for comparison with the CPU address) also can be set by using the

respective bits in the HBCU registers, ASID[5:0] (D[5:0]/0x48312) and ASID_VA[5:0] (D[5:0]/0x48314).

∗ ASID[5:0]: ASID Bits in the ASID Setup Register (D[5:0]/0x48312)

∗ ASID_VA[5:0]: Logical ASID Bits in the Logical ASID Setup Register (D[5:0]/0x48314)

Moreover, if the cause of an ASID exception occurs, the selection of whether to generate an exception can be

set. Set AEXPEN (D4/0x48300) to 1 to generate an ASID exception; set it to 0 to not generate an exception.

∗ AEXPEN: ASID Exception Enable Bit in the Address Control Register (D4/0x48300)

3. Specifying whether to use the instruction cache

Whether to use the instruction cache can be specified for each block individually. When ICx (x = 0–7) is set to

1, the CCU is used to fetch instructions in block ‘x’. When ICx = 0 (default), all instructions in block ‘x’ are

fetched from an external device without using the cache.

∗ ICx: Block x Instruction Cache Enable Bit in the Block x Configuration Register (D0/0x48302 + 2•x)

4. Specifying whether to use the data cache

Whether to use the data cache can be specified for each block individually. When DCx (x = 0–7) is set to 1, the

CCU is used to read/write data in block ‘x’. When DCx = 0 (default), all data in block ‘x’ is read/written to and

from an external device without using the cache.

∗ DCx: Block x Data Cache Enable Bit in the Block x Configuration Register (D1/0x48302 + 2•x)

5. Selecting between write-back and write-through during cache write

Data cache write mode can be specified for each block individually. When using the data cache with WRMDx

(x = 0–7) set to 1, data write to block ‘x’ is performed in write-back mode. When WRMDx = 0 (default), data

write to block ‘x’ is performed in write-through mode. However, before write-back mode can be selected,

WBEN (D4/0x48340) in the CCU must be set to 1. When WBEN (D4/0x48340) = 0, all cache write operations

are performed in write-through mode, regardless of how WRMDx is set.

∗ WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2•x)

∗ WBEN: Write-Back Enable Bit in the Cache Configuration Register (D4/0x48340)

In write-back mode, data is only written to the cache, and memory is only updated when data in the cache is

replaced. In write-through mode, data is written to both the cache and memory.

Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are excluded from use of the MMU,

ASID, and cache.

For details about the MMU and ASID, see Section II.5, “Memory Management Unit (MMU).” For details about the

cache, see Section II.6, “Cache Control Unit (CCU).”

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II.4.3.2 Settings for the Entire Address Space

The following settings can be made for the entire 4GB address space.

1. Setting of a 1GB low-order mirror area

As shown in Figure II.4.3.2.1, a 1GB block consisting of blocks 2 and 3, blocks 4 and 5, or blocks 6 and 7

(for which the two high-order address bits are set to 0) can each be used as a mirror area of blocks 0 and 1.

However, the areas from 0x0 to 0x3FFFFF (areas 0 to 6) cannot be mirrored.

Blocks 6 and 7

(1G bytes) Mirror area

Non-mirror area

Blocks 4 and 5

(1G bytes) Mirror area

Blocks 2 and 3

(1G bytes) Mirror area

Blocks 0 and 1

(1G bytes)

Effective area

0xFFFF FFFF

0xC040 0000

0xC03F FFFF

0xC000 0000

0xBFFF FFFF

0x8040 0000

0x803F FFFF

0x8000 0000

0x7FFF FFFF

0x4040 0000

0x403F FFFF

0x4000 0000

0x3FFF FFFF

0x0040 0000

0x0000 0000

Logical

address

Share physical addresses

0x400000 to 0x3FFFFFFF

Figure II.4.3.2.1 Address Space when Mirrors Area Set

To use blocks 2 and 7 as a mirror area, set MIR (D0/0x48300) to 1. When not using any mirror areas, set MIR

(D0/0x48300) to 0 (default).

∗ MIR: Mirroring Enable Bit in the Address Control Register (D0/0x48300)

2. Forcible use of the MMU in user mode

Although selecting whether to use the MMU can be set individually for each block as described earlier,

it is possible to specify the forcible use of the MMU in the entire 4GB space during user mode by setting

UMDMEN (D1/0x48300) to 1.

∗ UMDMEN: MMU Forced Enable Bit in the Address Control Register (D1/0x48300)

Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are normally excluded from use

of the MMU. However, when UMDMEN (D1/0x48300) is set to 1, the MMU is forcibly used in that 4MB

space as well.

3. Forcible use of the ASID in user mode

Although selecting whether to use the ASID can be set individually for each block as for the MMU, it is

possible to specify the forcible use of the ASID in the entire 4GB space during user mode by setting UMDAEN

(D2/0x48300) to 1.

∗ UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300)

Of the 4GB space, area 6 and subsequent areas in block 0 (0x0 to 0x3FFFFF) are normally excluded from use

of the ASID. However, when UMDAEN (D2/0x48300) is set to 1, the ASID is forcibly used in that 4MB space

as well.

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S1C33401 TECHNICAL MANUAL EPSON II-4-7

HBCU

II.4.4 Bus Access

The HBCU controls the MMU, CCU, A0RAM, and bus module according to bus access requests from the CPU,

and arbitrates bus contention for those requests.

When a bus access request is output from the CPU, the HBCU decodes the 3 high-order address bits (VA[31:29])

to identify the target block (one of blocks 0 to 7). Next, the HBCU determines the following content of processing

from the register settings of said block, and sends a bus access request to the target unit.

• Cache access not using the MMU

• Cache access using the MMU

• External bus access not using the MMU

• External bus access using the MMU

• Internal memory access

II.4.4.1 Cache Access

When the instruction or data resides in the cache (a hit), reading is completed in one cycle (with address translation

performed at the same time when using the MMU), and writing is completed in two cycles. When accessed for

write, TAG memory of the CCU is read for comparison with the logical address from the CPU in the first cycle (with

address translation performed at the same time when using the MMU). When it is a hit, data is written in the next

cycle.

II.4.4.2 External Memory Access

When accessing external memory, the HBCU outputs a bus access request to the bus module. When use of the

MMU is enabled, the HBCU first uses the MMU to translate the address, then outputs a bus access request to the

bus module along with the translated address in the next cycle.

II.4.4.3 Area 0 Internal Memory Access

Access to internal memory in area 0 such as A0RAM (no-wait RAM in area 0) is completed in one cycle for both

read and write.

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II-4-8 EPSON S1C33401 TECHNICAL MANUAL

II.4.5 ASID and Multiple Virtual Spaces

The HBCU supports multiple virtual spaces configured by using an ASID (6-bit address space identifier).

The normal method of memory usage (single virtual space) handles 4GB of memory as one contiguous address

space, so that when a specific address in memory is accessed for read/write operation, data is always read from

or written to the same location (except when address translation information changes). This means that multiple

processes cannot be located in parallel in the same area unless using a time-multiplexed or similar other transfer

method.

Conversely, multiple virtual spaces supported by the HBCU can be considered to consist of up to 64 instances of

64MB spaces (i.e., processes) located in parallel in the same area. The ASID makes this possible. Before a logical

address is input to the MMU when using the ASID, its 6 high-order bits are replaced with an ASID. Therefore, even

when accessing the same address in memory, you can access another process by simply changing the ASID that is

specifiable in a register. In other words, the ASID serves as a process number representing one of multiple 64MB

processes.

Figure II.4.5.1 shows the conceptual diagram of a logical address space where the ASID is used.

Process 0

64MB

Process 1

64MB

Process 2

64MB

Process 3

64MB

Process 4

64MB

Process 5

64MB

Process 6

64MB

Process 7

64MB

0x1FFF FFFF

0x1C00 0000

0x1B0F FFFF

0x1800 0000

0x17FF FFFF

0x1400 0000

0x13FF FFFF

0x1000 0000

0x0FFF FFFF

0x0C00 0000

0x0B0F FFFF

0x0800 0000

0x07FF FFFF

0x0400 0000

0x03FF FFFF

0x0000 0000

Process 0

0x03FF FFFF

0x0000 0000

Logical address

• • • • •

Block 0

Process 56

64MB

Process 57

64MB

Process 58

64MB

Process 59

64MB

Process 60

64MB

Process 61

64MB

Process 62

64MB

Process 63

64MB

0xFFFF FFFF

0xFC00 0000

0xFB0F FFFF

0xF800 0000

0xF7FF FFFF

0xF400 0000

0xF3FF FFFF

0xF000 0000

0xEFFF FFFF

0xEC00 0000

0xEB0F FFFF

0xE800 0000

0xE7FF FFFF

0xE400 0000

0xE3FF FFFF

0xE000 0000

Logical address Block 7

ASID = 0x0V[25:0]

Process 1

ASID = 0x1

Process 2

ASID = 0x2

Process 63

ASID = 0x3F

• • • • • •

Blocks 1, 2, 3, 4, 5, 6

Figure II.4.5.1 Multiple Virtual Spaces using the ASID

To use the ASID, the ASID should be enabled for each block. To use the ASID in block ‘x’ (x = 0–7), set the

ASIDENx bit in the Block x Configuration Register to 1.

∗ ASIDENx: Block x ASID Enable Bit in the Block x Configuration Register (D5/0x48302 + 2•x)

Also set the ASIDUSE bit in the TAG part of the TLB in the MMU to 1 (see Section II.5 for details).

Although whether to use the ASID can be specified for each block independently, UMDAEN (D2/0x48300) may be

set to 1 to specify forcible use of the ASID for the entire 4GB space in user mode.

∗ UMDAEN: ASID Forced Enable Bit in the Address Control Register (D2/0x48300)

Of the 4GB space, area 0 to area 6 in block 0 (0x0 to 0x3FFFFF) are normally excluded from ASID use. However,

when UMDAEN (D2/0x48300) is set to 1, the ASID is forcibly used in that 4MB space as well.

The ASID and logical ASID values (used for comparison with the CPU address) can also be set by using ASID[5:0]

(D[5:0]/0x48312) and ASID_VA[5:0] (D[5:0]/0x48314), respectively.

∗ ASID[5:0]: ASID Bits in the ASID Setup Register (D[5:0]/0x48312)

∗ ASID_VA[5:0]: Logical ASID Bits in the Logical ASID Setup Register (D[5:0]/0x48314)

Setting AEXPEN (D4/0x48300) to 1 enables to generate an MMU exception if a space other than 64MB (0x0–

0x3FFFFFF) is accessed when ASID is used.

∗ AEXPEN: ASID Exception Enable Bit in the Address Control Register (D4/0x48300)

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S1C33401 TECHNICAL MANUAL EPSON II-4-9

HBCU

II.4.6 Address ASID and Mirror Processing

Before it outputs an address, the HBCU performs two kinds of processing according to register settings as follows:

1. When UMDAEN (D2/0x48300) or the ASIDENx (D5/0x48302 + 2•x) for block ‘x’ (x = 0–7) to access is set to

1, the HBCU replaces the 6 high-order address bits output by the CPU with the 6 ASID bits set in ASID[5:0]

(D[5:0]/0x48312).

2. When MIR (D0/0x48300) is set to 1, the HBCU sets the 2 high-order address bits to 0b00 for enabling the 1GB

mirroring function.

The block to access is determined by the 3 high-order address bits output by the CPU.

When ASIDENx (D5/0x48302 + 2•x) and MIR (D0/0x48300) are both set to 1, the 6 high-order address bits output

by the CPU are replaced with ASID bits before setting the 2 high-order address bits to 0b00.

Mirror processing is applied to physical addresses. Therefore, the address from the CPU is mirrored directly when

not using the MMU (or the ASID-replaced address when using the ASID). When using the MMU, the logical

address is translated into the physical address before being mirrored.

The address processing described in this section does not affect the discrimination of the block (0–7) in the logical

address space since block discrimination is performed immediately after the CPU output the logical address.

Figure II.4.6.1 shows the flow of processing from when the HBCU receives an address from the CPU until it

outputs an address to the relevant unit.

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II-4-10 EPSON S1C33401 TECHNICAL MANUAL

MMU access MMU and cache access (∗)

Cache access

Internal memory (A0RAM) access High-speed bus (bus module) access

yes

Analyze CPU output address

• get the block configuration register value from VA[31:29]

• judge the area number as 6 or less (VA[31:22]=0) from VA[31:22]

ASID forcibly enabled

in user mode

MMU forcibly enabled

in user mode

yes

ASID used

in target block

ASID used

in target block

yes

MMU used

in target block

(Area 1–6)

IC/DC used

in target block

yes

IC/DC used

in target block

Area 6–0

Area 0

yes

Mirror processing

VA[31:30] forcibly set to ‘00’

yes

VA[31:30] forcibly set to ‘00’ Mirror processing

VA[31:30] forcibly set to ‘00’

yes Mirror processing

Area 6–0

yes

Area 6–0

VA[31:26] replaced with ASID[5:0]

MMU forcibly enabled

in user mode

yes

∗ When mirroring is enabled, mirror processing is applied

only to the address to be sent to the cache.

Figure II.4.6.1 Flow of Address Processing in the HBCU

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HBCU

II.4.7 Details of Control Registers

Table II.4.7.1 List of HBCU Registers

Address

0x00048300

0x00048302

0x00048304

0x00048306

0x00048308

0x0004830A

0x0004830C

0x0004830E

0x00048310

0x00048312

0x00048314

Function

Set mirror, protect and forcible use of ASID/MMU, etc.

Set block 0

Set block 1

Set block 2

Set block 3

Set block 4

Set block 5

Set block 6

Set block 7

Set ASID

Set logical ASID

Address Control Register (pHBCU_ADR_CNT)

Block 0 Configuration Register (pHBCU_BLK0)

Block 1 Configuration Register (pHBCU_BLK1)

Block 2 Configuration Register (pHBCU_BLK2)

Block 3 Configuration Register (pHBCU_BLK3)

Block 4 Configuration Register (pHBCU_BLK4)

Block 5 Configuration Register (pHBCU_BLK5)

Block 6 Configuration Register (pHBCU_BLK6)

Block 7 Configuration Register (pHBCU_BLK7)

ASID Setup Register (pHBCU_ASID_SETUP)

Logical ASID Setup Register

(pHBCU_LOGIC_ASID)

Size

The following describes each HBCU control register.

The HBCU control registers are mapped in the 16-bit device area from 0x48300 to 0x48314, and can be accessed in

units of half-words or bytes.

Note: When setting the HBCU control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

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0x48300: Address Control Register (pHBCU_ADR_CNT)

Name

Address

–

HRUWP

AEXPEN

–

UMDAEN

UMDMEN

MIR

D15–6

reserved

HBCU register user write protect

ASID exception enable

reserved

ASID forced enable (user mode)

MMU forced enable (user mode)

Mirroring enable

1Protect 0

Write enabled

1Enabled 0Disabled

1Mirrored 0

Not mirrored

–

R/W

–

R/W

0 when being read.

0048300

(HW)

–

Address

control register

(pHBCU_ADR

_CNT)

D[15:6] Reserved

D5 HRUWP: HBCU Register User-Write-Protect Bit

Sets write protection of the HBCU registers.

1 (R/W): Write protect

0 (R/W): Write enable (default)

When this bit is set to 1, all HBCU registers (including this bit itself) are write-protected and cannot

be accessed for write operation in user mode. Setting this bit in supervisor mode to 0 removes write

protection.

D4 AEXPEN: ASID Exception Enable Bit

Enables the generation of ASID exceptions. The ASID exception is an MMU exception that occurs

when an address outside the 64MB space (0x0–0x3FFFFFF) is accessed.

1 (R/W): Enable

0 (R/W): Disable (default)

When this bit is set to 0, no exceptions are generated even when the cause of an ASID exception occurs.

D3 Reserved

D2 UMDAEN: ASID Forced Enable Bit

Selects whether to forcibly use the ASID in user mode for the entire 4GB logical space (including low-

order 4MB areas 0 to 6).

1 (R/W): Enable ASID

0 (R/W): Disable ASID (default)

When this bit is 0, the ASID enable/disable setting of each block is effective.

D1 UMDMEN: MMU Forced Enable Bit

Selects whether to forcibly use the MMU in user mode for the entire 4GB logical space (including low-

order 4MB areas 0 to 6).

1 (R/W): Enable MMU

0 (R/W): Disable MMU (default)

When this bit is 0, the MMU enable/disable setting of each block is effective.

D0 MIR: Mirroring Enable Bit

Sets blocks 2 and 3, blocks 4 and 5, or blocks 6 and 7 as a 1GB mirror area of blocks 0 and 1 by setting

the address A[31:30] to 0b00. However, the low-order 4MB space (areas 0 to 6) in block 0 is not

mirrored.

1 (R/W): Set mirror area

0 (R/W): Normal area (default)

For details about the MMU, see Section II.5, “Memory Management Unit (MMU).”

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HBCU

0x48302–0x48310: Block x Configuration Registers (pHBCU_BLKx)

Name

Address

–

ASIDENx

MMUENx

–

WRMDx

DCx

ICx

D15–6

reserved

Block x ASID enable

Block x MMU enable

reserved

Block x write-mode select

Block x data cache enable

Block x instruction cache enable

1Enabled 0Disabled

1Write-back 0

Write-through

1Used 0Not used

–

R/W

–

R/W

0 when being read.

0048302

0048310

(HW) –

Block x

configuration

(pHBCU_BLKx)

Note: The letter ‘x’ in bit names, etc., denotes a block number from 0 to 7.

0x48302 Block 0 Configuration Register (pHBCU_BLK0)

0x48304 Block 1 Configuration Register (pHBCU_BLK1)

0x48306 Block 2 Configuration Register (pHBCU_BLK2)

0x48308 Block 3 Configuration Register (pHBCU_BLK3)

0x4830A Block 4 Configuration Register (pHBCU_BLK4)

0x4830C Block 5 Configuration Register (pHBCU_BLK5)

0x4830E Block 6 Configuration Register (pHBCU_BLK6)

0x48310 Block 7 Configuration Register (pHBCU_BLK7)

D[15:6] Reserved

D5 ASIDENx: Block x ASID Enable Bit

Enables the ASID for use when accessing block ‘x’.

1 (R/W): Enable ASID

0 (R/W): Disable ASID (default)

When this bit is set to 1, the 6 high-order bits of the logical address output by the CPU to access block ‘x’

are replaced with the 6-bit ASID specified by ASID[5:0] (D[5:0]/0x48312). For block 0, however, even

if its ASID is enabled (ASIDEN0 = 1), the ASID is not used when accessing the low-order 4MB space

(areas 0 to 6), except when UMDAEN (D2/0x48300) = 1.

D4 MMUENx: Block x MMU Enable Bit

Enables the MMU for use when accessing block ‘x’.

1 (R/W): Enable MMU

0 (R/W): Disable MMU (default)

When this bit is set to 1, the logical address output by the CPU to access block ‘x’ is translated into the

physical address by the MMU before being output from the HBCU. For block 0, however, even if its

MMU is enabled (MMUEN0 = 1), the MMU is not used when accessing the low-order 4MB space (areas

0 to 6), except when UMDMEN (D1/0x48300) = 1.

D3 Reserved

D2 WRMDx: Block x Write-Mode Select Bit

Selects write mode (write-through or write-back) when writing to the data cache.

1 (R/W): Write-back mode

0 (R/W): Write-through mode (default)

In write-through mode, data is written to external memory at the same time it is written to the data

cache. In write-back mode, data is only written to the data cache, and when data in the cache is replaced

at a subsequent cache miss, the data is written to external memory.

This setting is effective only when the data cache is enabled for use in block ‘x’. Also note that before

using this bit to select write-back mode, WBEN (D4/0x48340) in the CCU must be set to 1 to enable

the write-back function.

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D1 DCx: Block x Data Cache Enable Bit

Selects whether to use the data cache when accessing block ‘x’.

1 (R/W): Use cache

0 (R/W): Do not use (default)

D0 ICx: Block x Instruction Cache Enable Bit

Selects whether to use the instruction cache when fetching instructions from block ‘x’.

1 (R/W): Use cache

0 (R/W): Do not use (default)

For details about the MMU, see Section II.5, “Memory Management Unit (MMU).” For details about the cache, see

Section II.6, “Cache Control Unit (CCU).”

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HBCU

0x48312: ASID Setup Register (pHBCU_ASID_SETUP)

Name

Address

–

0x0 to 0x3F

–

ASID5

ASID4

ASID3

ASID2

ASID1

ASID0

D15–6

reserved

ASID

–

R/W

0 when being read.

0048312

(HW)

ASID setup

(pHBCU_ASID

_SETUP)

D[15:6] Reserved

D[5:0] ASID[5:0]: ASID

Sets a 6-bit ASID (address space identifier). (Default: 0x0)

When ASID is enabled, the 6 high-order bits of the logical address output by the CPU are replaced with

the ASID specified by this register. Use of the ASID allows multiple virtual spaces (processes) to be

configured in 64MB units, where the ASID is used as a process number.

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0x48314: Logical ASID Setup Register (pHBCU_LOGIC_ASID)

Name

Address

–

0x0 to 0x3F

–

ASID_VA5

ASID_VA4

ASID_VA3

ASID_VA2

ASID_VA1

ASID_VA0

D15–6

reserved

Logical ASID

(compared with VA[31:26] output

from the CPU)

–

R/W

0 when being read.

0048314

(HW)

Logical ASID

setup register

(pHBCU_LOGIC

_ASID)

D[15:6] Reserved

D[5:0] ASID_VA[5:0]: Logical ASID

Sets a 6-bit logical ASID. (Default: 0x0)

When using ASID-based multiple virtual spaces, use these bits to set the 6 high-order bits of the logical

address of each process. The HBCU compares the 6 high-order address bits output by the CPU with

ASID_VA[5:0] before ASID processing, and if the bits do not match, generates an ASID exception.

However, this ASID exception is generated only when AEXPEN (D4/0x48300) is set to 1.

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HBCU

II.4.8 Precautions

• During MMU exception handling, the MMU is disabled.

During debug exception handling, MMU enable/disable and MMU exception generation conditions depend on

the settings in the debug unit.

When the MMU is disabled, even if the MMU exception handler routine is located in an area where the MMU is

enabled for use, no address translation is performed. Note that addresses are handled as physical addresses.

• To use the MMU for the entire 4GB space, set UMDMEN (D1/0x48300) to 1. To use the MMU for accessing

a specific block, set MMUENx (D4/0x48302 + 2•x) for that block to 1. Also be sure to set MEN (D0/0x48320)

in the MMU control register to 1. For the MMU to be used, both the HBCU and MMU must be set. For details

about the MMU, see Section II.5, “Memory Management Unit (MMU).”

• Mirror processing is applied to physical addresses.

When the MMU is used, the physical address translated by the MMU is processed for mirroring.

When mirroring, MMU, and cache are enabled, mirror processing is applied only to the address to be sent to the

cache. In this case, the cache TAG address is compared with the address that has been processed for mirroring

after translating into a physical address by the MMU.

• When forcible use of the MMU in user mode is enabled, setting of the ASIDEN0 (D5) in the Block 0

Configuration Register (0x48302) is applied to areas 6 to 0.

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THIS PAGE IS BLANK.

II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU)

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MMU

II.5 Memory Management Unit (MMU)

II.5.1 Overview of the MMU

The Memory Management Unit (MMU) uses the internal Translation Lookaside Buffer (TLB) to translate the

logical addresses supplied from the CPU via the HBCU into physical addresses. Consequently, programs and data

in physical memory can be assumed to be located in a given virtual memory space when executed or accessed.

Address translation is managed in units of pages, with the page size selectable from 4KB or 64KB.

The main features of the MMU are outlined below.

• With a 4-way set-associative method adopted, the MMU supports 16 entries per way for a total of 64 entries in

the TLB.

• Divides the 4GB logical address space into eight 512MB blocks, allowing the MMU to be enabled or disabled

for use in each block.

• Manages the logical address space in units of pages. The page size can be selected from 4KB or 64KB.

• Allows memory protection one page at a time by employing individual page protection or a user mode access

protection facility.

• Allows individual pages of the cache to be enabled or disabled simultaneously.

• Supports six distinct causes of MMU exceptions.

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II.5.2 Logical and Physical Address Spaces

The C33 ADV CPU has a 4GB memory space based on the 32-bit internal address bus.

II.5.2.1 Logical Address Space

With the MMU being used, the CPU can access virtual space to which actual devices are logically assigned.

Therefore, the 4GB memory space handled by the CPU is called the “logical address space.”

The 4GB logical address space is managed separately in eight 512MB divided blocks by the HBCU connected

directly to the CPU. Normally, the selection of whether to use the MMU is set in units of blocks. In this case, the

MMU cannot be enabled for use in the lower 4MB part of the address space (areas 0 to 6). However, setting up the

HBCU as required can forcibly enable MMU use in the entire 4GB space. In such case, the MMU is used for access

to this lower 4MB part of address space (areas 0 to 6).

II.5.2.2 Physical Address Space

Separate from the logical address space is a space (where actual devices are mapped) comprised of the BBCU

address bus and #CE signal. This is called the “physical address space.”

The physical address space is divided into 23 areas (areas 0 to 22). Areas 0 to 3 comprise an internal area (e.g.,

internal memory, internal I/O, debug area), whereas areas 4 and later comprise an external area that has external

#CE output. For details about the physical address space, see the section in Chapter III, “C33 ADV Bus Block,” that

describes the BBCU.

II.5.2.3 Relationship between Logical and Physical Address Spaces

Figure II.5.2.3.1 shows the relationship between the logical and physical address spaces.

Block 7

(512M bytes)

0xFFFF FFFF

0xE000 0000

Block 6

(512M bytes)

0xDFFF FFFF

0xC000 0000

Block 5

(512M bytes)

0xBFFF FFFF

0xA000 0000

Block 4

(512M bytes)

0x9FFF FFFF

0x8000 0000

Block 3

(512M bytes)

0x7FFF FFFF

0x6000 0000

Block 2

(512M bytes)

0x5FFF FFFF

0x4000 0000

Block 1

(512M bytes)

0x3FFF FFFF

0x2000 0000

Block 0

(512M bytes)

0x1FFF FFFF

0x0000 0000

Logical space HBCU, MMU, BBCU

Area 22

2G bytes

Area 21

1G bytes

Area 20

512M bytes

Areas 19–0

512M bytes

Physical space

Block processing

ASID processing

Address translation processing

Mirroring processing

Area processing

Figure II.5.2.3.1 Relationship between Logical and Physical Address Spaces

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MMU

The logical address output from the CPU is subjected to the five processes listed below by the HBCU, MMU, and

BBCU to finally generate the physical address.

1. Block process

2. ASID process

3. Address translation process

4. Mirroring process

5. Area process

The MMU is used for step 3 (address translation process). If the CPU accesses a logical block that has the “MMU

used” attribute, the MMU translates the logical addresses into physical addresses in units of pages (4KB or 64KB).

The 20 high-order bits of the logical address for 4KB per page or the 16 high-order bits of logical address for 64KB

per page can be translated into a desired physical address.

The MMU hardware contains a 64-entry TLB that can be used as an address translation table for translating up

to 1M pages in 4KB per page or 64K pages in 64KB per page. The software (OS) manages the contents of the

translation table.

When the block has the “MMU not used” attribute, this processing is bypassed.

Page 0

Page 1

Page 2

Logical address Physical address

4KB or 64KB per page

(Page 1)

(Page 0)

(Page 2)

Logical addresses

are mapped to physical

addresses in page units.

Figure II.5.2.3.2 Address Translation

For example, assume that the 64KB page size is selected and addresses 0x2000∗∗∗∗ are to be converted to 0xC0∗∗∗∗.

When the CPU accesses 64KB located at the beginning of block 1 (0x20000000–0x2000FFFF), the 64KB located

at the beginning of area 10 (0xC00000–0xC0FFFF) is accessed for read/write operation. (Address translation is

described in detail later.)

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II.5.3 Configuration of the MMU

The MMU incorporated in the C33 ADV Core Block uses a 4-way set-associative method. The TLB is 4-way

configured, having 16 entries per way. Therefore, the TLB has a total of 64 entries. Figure II.5.3.1 shows the

general configuration of the MMU.

LRU

Entry 0

Entry 1

Entry 2

Entry 3

Entry 4

Entry 5

Entry 6

Entry 7

Entry 8

Entry 9

Entry 10

Entry 11

Entry 12

Entry 13

Entry 14

Entry 15

TAG

DATA

Way 0 Way 0

Way 1 Way 1

Way 2 Way 2

Way 3 Way 3

Figure II.5.3.1 General Configuration of the MMU

II.5.3.1 TAG Part and DATA Part

The TLB consists of a TAG part and a DATA part, whose respective contents vary with the page size selected.

Figure II.5.3.1.1 shows the configuration of the TAG and DATA parts of the TLB.

TAG

For 4KB/page

CVA[31:16]

DATA

CA[31:12]

AP CE

16 bits

24 bits

20 bits

TAG

For 64KB/page

CVA[31:20]

DATA

CA[31:16]

invalid

CVA[31:16/20]

CA[31:12/16]

12 bits

4 bits

24 bits

ASIDUSE

WRP

UMP

ACP

VLD

ACC

DTY

: Comparison logical address

: Conversion physical address

: Use of ASID bit

: Write-protect bit

: User-protect bit

: Access-protect bit

: Cache enable bit

: Valid bit

: Access bit

: Dirty bit

0 = Not used

0 = Not protected

0 = Disabled

0 = Invalid

0 = Not accessed

0 = Not written

1 = Used

1 = Protected

1 = Enabled

1 = Valid

1 = Accessed

1 = Written

Initial value = Undefined

Initial value = 0

invalid

4 bits

16 bits

20 bits

Figure II.5.3.1.1 Configuration of the TLB

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MMU

TAG part

The TAG part consists of the information shown below.

The CVA (comparison address) can be confirmed and set using the MMU TAG Address Register (0x48328).

Other bits can be confirmed and set using the MMU Page Setting Register (0x4832A).

CVA (comparison address)

This is the address compared with the logical address supplied from the HBCU. The compared address bits

vary with the page size selected by the MMU. For 4KB per page, 16 CVA bits or CVA[31:16] are compared

with the 16 high-order bits of the logical address. For 64KB per page, 12 CVA bits or CVA[31:20] are

compared with the 12 high-order bits of the logical address.

Depending on whether the logical address and this comparison address match (a hit) or do not match (a

miss), the MMU performs the appropriate processing.

ASIDUSE (ASID use) bit

This bit specifies whether to use the ASID when translating addresses of the page specified in a TLB entry.

The MMU uses ASID when this bit is set to 1. The HBCU should also be set up accordingly for the ASID

to be used.

WRP (write protect) bit

This bit is used to write-protect the content of the page specified in a TLB entry. When this bit is set to 1,

the page is write-protected and its content cannot be altered regardless of whether the CPU is operating in

supervisor mode or user mode. The page can be accessed for read operation, however.

UMP (user mode access protect) bit

This bit protects the page specified in a TLB entry against access in user mode. When this bit is set to 1,

the page is disabled against read/write operation in user mode. The page can be accessed for read/write

operation in supervisor mode, however.

ACP (access protect) bit

This bit protects the page specified in a TLB entry against access. When this bit is set to 1, the page is

disabled against read/write operation in both supervisor mode and user mode.

CE (cache enable) bit

This bit specifies whether to use the CCU (cache) to access the page specified in a TLB entry. The MMU

uses the cache when this bit is set to 1. The HBCU and CCU should also be set up accordingly for the cache

to be used.

VLD (valid) bit

This bit indicates whether the content of the TAG part is valid. The content is valid when VLD = 1.

ACC (access) bit

This bit indicates whether the page specified in a TLB entry has been accessed for read/write operation.

When this bit is 1, it means that the page has been accessed.

DTY (dirty) bit

This bit indicates whether data has been written to the page specified in a TLB entry. When this bit is 1, it

means that data has been written to the page.

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DATA part

The DATA part is where the physical address is saved. The address bits saved in this part vary with the page

size selected.

For 4KB per page, the 20 high-order bits of the physical address (CA[31:12]) are saved.

For 64KB per page, the 16 high-order bits of the physical address (CA[31:16]) are saved.

The 12 low-order bits (for 4KB per page) or 16 low-order bits (for 64KB per page) of the physical address

consist of the same bit content as that of the logical address.

The content of the DATA part can be confirmed and set using the MMU 4KB Data Address Register (0x48324)

and MMU Common Data Address Register (0x48326).

II.5.3.2 LRU

Due to its 4-way configuration, the MMU can have up to four items of address translation information with the

same entry number. In case of an MMU miss, the address information contained in the MMU must be replaced

with one of the four ways selected. The LRU part holds that way number. Although LRU (Least Recently Used)

is the algorithm used to select the way that was least recently accessed, a pseudo-LRU algorithm with a simplified

circuit configuration is adopted for the MMU in the C33 ADV Core.

In case of an MMU hit, the LRU information held by the accessed entry is automatically updated.

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MMU

II.5.4 Settings and Operation of the MMU

II.5.4.1 Enabling the MMU

When initially reset, use of the MMU is disabled. To use the MMU, the following settings are required:

1. Setting up the HBCU

The HBCU manages the 4GB logical address space separately in eight 512MB blocks. Whether to use the

MMU can be selected for each block individually.

To use the MMU in block ‘x’ (x = 0–7), set the MMUENx bit (D4) in the Block x Configuration Register of the

HBCU to 1 (= enable).

∗ MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2•x)

For details about the HBCU, see Section II.4, “High-Speed Bus Control Unit (HBCU).”

2. Setting up the MMU

To use the MMU, MEN (D0/0x48320) in the MMU should also be set to 1.

∗ MEN: MMU Enable Bit in the MMU Control Register (D0/0x48320)

The MMU is enabled for use by the two settings above.

Note, however, that the MMU is disabled during MMU exception handling (PSR register ME bit = 1). Even if the

MMU exception handler routine is located in a block where the MMU is enabled for use, no address translation is

performed and logical addresses are handled directly as physical addresses.

When initially reset, all MMU registers are write-protected in user mode. The registers can only be read in user

mode, but can be both read and written to in supervisor mode. To set up the MMU registers in user mode, reset

MRUWP (D12/0x48320) by writing a 0 in supervisor mode to enable the registers for write operation in user mode.

∗ MRUWP: MMU Register User Write Protect Bit in the MMU Control Register (D12/0x48320)

II.5.4.2 Specifying a Page Size

Use 64KMD (D8/0x48320) to specify the page size of the MMU.

∗ 64KMD: Page Size Select Bit in the MMU Control Register (D8/0x48320)

The page size is 4KB when 64KMD (D8/0x48320) = 0 or 64KB when 64KMD (D8/0x48320) = 1.

II.5.4.3 ASID Processing

The ASID is used for two purposes: for using multiple virtual spaces, and generating entry numbers.

Using multiple virtual spaces

When an accessed block has been enabled for using the MMU and ASID in the HBCU, the HBCU replaces

the 6 high-order bits (VA[31:26]) of the logical address (hereafter the VA) output by the CPU with ASID[5:0]

(D[5:0]/0x48312) before forwarding it to the MMU. Because the 6 high-order bits VA[31:26] are replaced with

ASID, processes are handled as multiple virtual spaces (where the ASID is handled as a process ID).

In the HBCU, these bits are compared with the logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) before the

6 high-order bits VA[31:26] are replaced with ASID[5:0]. A mismatch means that access will be made to a

different process other than the one whose process ID is specified by the ASID. Therefore, an ASID exception

(one cause of an MMU exception) is generated.

Generating an entry number

When ASIDMIX (D4/0x48320) is set to 1, the 4-bit field in the logical address that indicates an entry number

(i.e., VA[15:12] for 4KB per page, VA[19:16] for 64KB per page) is combined with ASID to generate an entry

number.

∗ ASIDMIX: Entry Number Generation Mode Bit in the MMU Control Register (D4/0x48320)

The purpose of this operation is to prevent a reduction in the TLB hit rate when a specific entry is used for two or

more processes in multiple virtual spaces. Compared to the entry number generated from VA, the one generated

here is another entry number that includes ASID information. Distributed entries help to increase the hit rate.

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II.5.4.4 Address Translation

Figure II.5.4.4.1 shows the flow of 4KB-per-page address translation. Figure II.5.4.4.2 shows the flow of 64KB-

per-page address translation.

LRU

MUX

CMP0

CMP1 CMP2

CMP3

VA[31:0]

Entry 0

Entry 1

Entry 2

Entry 15

TAG DATA

Comparison address

ASID enable/disable information

Way selection

031

ASID[5:0]

VA[25:16] Entry[3:0]

VA[11:0]

VA[31:16] VA[15:12]

VA[11:0]

011121516252631

Logical address VA[31:0] from the CPU

Final physical address PA[31:0]

Note: CA denotes the translated address contained in the DATA part of the TLB.

When ASID is used

When ASID is not used

Way 0

Way 1

Way 0

Hit

Way 1

Way 2 Way 2

Way 3 Way 3

Entry No.

CA[31:12]

VA[11:0]

ASID processing (when ASIDENx = 1)

ASID processing (when ASIDMIX = 1)

Figure II.5.4.4.1 Flow of Address Translation (4KB Per Page)

LRU

MUX

CMP0

CMP1

CMP2

CMP3

VA[31:0]

Entry 0

Entry 1

Entry 2

Entry 15

TAG

DATA

Comparison address

031

ASID[5:0] VA[25:20] Entry[3:0]

VA[15:0]

VA[31:20]

VA[19:16] VA[15:0]

015161920252631

ASID enable/disable information

Way selection

Logical address VA[31:0] from the CPU

Final physical address PA[31:0]

Note: CA denotes the translated address contained in the DATA part of the TLB.

When ASID is used

When ASID is not used

Way 0

Way 1

Way 0

Hit

Way 1

Way 2 Way 2

Way 3 Way 3

Entry No.

CA[31:16] VA[15:0]

ASID processing

(when ASIDENx = 1)

ASID processing

(when ASIDMIX = 1)

Figure II.5.4.4.2 Flow of Address Translation (64KB Per Page)

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MMU

When the CPU accesses a block where the MMU is enabled for use, the block’s logical address is translated into a

physical address according to the procedure described below.

1. When ASID has been enabled for use in the HBCU, ASID processing is applied to the logical address VA from

the CPU as described above. Prior to ASID processing, VA[31:16] and ASID_VA[5:0] (D[5:0]/0x48314) are

compared, and if they do not match, an MMU exception is generated.

When ASID is disabled against use, the logical address from the CPU is translated directly as is.

2. The TAG part and DATA part information for 4 ways of TLB is read from the target entry.

When the page size is set to 4KB per page, VA[15:12] is the TLB entry number; for 64KB per page, VA[19:16]

is the TLB entry number.

3. The comparison address read from the TAG part is compared with the logical address received from the CPU.

For 4KB per page, comparison is made between CVA[31:16] and VA[31:16] from the CPU; for 64KB per page,

comparison is made between CVA[31:20] and VA[31:20].

Moreover, the ASID enable/disable information received from the HBCU is compared with the ASIDUSE bit in

the TAG part. Even when the compared addresses match, an MMU miss is assumed if the ASID enable/disable

information and ASIDUSE do not match.

4. When the compared addresses and ASID enable/disable information and ASIDUSE both match in one of four

ways, and the intended access does not violate the page protect information in the TAG part, an MMU hit is

assumed. Thus, the translated address (hereafter CA) read from the DATA part of the way that made a hit is

selected.

For 4KB per page, CA[31:12] + VA[11:0] is the final physical address; for 64KB per page, CA[31:16] +

VA[15:0] is the final physical address.

5. When the final physical address is determined, that address information is passed to the HBCU for use as the

address to access physical memory.

If no matching way is found in the address comparison in step 3, an MMU miss is assumed and an MMU exception

generated to the CPU. Even when a matching way is found in both address and ASID enable/disable comparisons,

if a page protect violation is found in step 4, an MMU exception is generated to the CPU. If an MMU exception

occurs, information about the cause of MMU exception, the way that generated the exception, the ways to be

replaced, logical address, etc. are set in respective registers. For details, see Section II.5.6, “MMU Exceptions.”

Figure II.5.4.4.3 shows an example of address translation in cases where the MMU, CCU, ASID, and mirror

processing are used in combination.

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II-5-10 EPSON S1C33401 TECHNICAL MANUAL

Block

ASID

Disabled

Enabled

Disabled

MMU

Enabled

Disabled

Cache

Disabled

Enabled

Disabled

CPU address Cache Physical Memory

Physical addressLogical address

Pro1

Pro2

Pro5

Pro3

Pro4

ASID processing

Pro1

Pro2

Pro4

Pro3

Pro5

Pro1

Pro2

Pro4

Pro3

Pro5

Pro1

Pro2

Pro4

Pro3

Pro5

Pro1

Pro2

Pro4

Pro3

Pro5

Pro1

Pro2

Pro4

Pro3

Pro5

Pro4

Pro3

Pro5

Cache

Area 10

Area 14

Area 20

(512MB)

Address translation processing

Mirror processing

A[31:30] = 00

as is

Pro3 and Pro4 used

separately by changing

ASID with a tact switch

as is

Figure II.5.4.4.3 Example of Address Translation

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MMU

II.5.5 Setting Up the TLB

The content of the TLB can be set and confirmed using the MMU registers.

When initially reset, all MMU registers are write-protected in user mode. The registers can only be read in user

mode, but can be both read and written to in supervisor mode. To set up the MMU registers in user mode, reset

MRUWP (D12/0x48320) by writing a 0 in supervisor mode to enable the registers for write operation in user mode.

∗ MRUWP: MMU Register User Write Protect Bit in the MMU Control Register (D12/0x48320)

Note: TLB initialization or alteration of TLB content pursuant to the occurrence of an MMU exception

should always be performed in an area where the MMU is not used.

II.5.5.1 Setting Up the TLB

Follow the method described below to set the TLB content.

1. Specifying the TLB to be set or altered

Specify the TLB entry number and way number to be set or altered by using ENT[3:0] (D[7:4]/0x48322) and

WAY[3:0] (D[3:0]/0x48322), respectively.

∗ ENT[3:0]: Entry Number Setting Bits in the MMU Entry Register (D[7:4]/0x48322)

∗ WAY[3:0]: Way Number Setting Bits in the MMU Entry Register (D[3:0]/0x48322)

The WAY0 to WAY3 bits correspond to ways 0 to 3, respectively. Always be sure to set one bit at a time. If two

or more bits are set, two or more ways will be altered at the same time.

2. Setting write information

Set the page setup information and comparison address to be written to the TAG part, and the translation

address to be written to the DATA part in each register as described below.

TAG part page setup information

The page setup information refers to the page protection setup, cache enable/disable, and other related

information in the TAG part. For the content of each bit, see Section II.5.3, “Configuration of the MMU.”

The MMU Page Setting Register (0x4832A) contains the control bits corresponding to each item of page

setup information. Use these bits to set the contents to be written to the TAG part.

TAG part comparison address

The TAG part comparison address should be set in the MMU TAG Address Register (0x48328). The

D[15:0] bits in this register correspond to CVA[31:16] of the comparison address. For 4KB per page, set all

16 bits in CVA[31:16]. For 64KB per page, only CVA[31:20] (D[15:4]) are effective, with the 4 low-order

bits ignored.

DATA part translation address

The DATA part translation address should be set in the MMU Common Data Address Register (0x48326).

This register corresponds to the 16 high-order address bits (CA[31:16]). For 64KB per page, this register

alone can be used to set the translation address. For 4KB per page, set the 16 high-order bits in this register

and the remaining 4 low-order bits (CA[15:12]) in D[15:12] of the MMU 4KB Data Address Register

(0x48324).

3. Writing to the TLB

To write to the TLB, use the available control bits separately for the TAG part and DATA part.

Writing to the TAG part

Write a 1 to TAGWR (D4/0x4832C). Then the page setup information and comparison address set in step 2

will be written to the TAG part in the entry and way specified in step 1.

∗ TAGWR: TAG Entry Write Bit in the TLB Control Register (D4/0x4832C)

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Writing to the DATA part

Write a 1 to DATWR (D0/0x4832C). Then the translation address set in step 2 will be written to the DATA

part in the entry and way specified in step 1.

∗ DATWR: DATA Entry Write Bit in the TLB Control Register (D0/0x4832C)

When the TAG part and DATA part must be set at the same time as when initializing the TLB, it is possible to

write a 1 to both TAGWR (D4/0x4832C) and DATWR (D0/0x4832C) at the same time. Writing a 0 to these bits

has no effect.

II.5.5.2 Confirming the Set Content of the TLB

The content of the TLB can be confirmed by following the method described below.

1. Specifying the TLB to confirm

Specify the TLB entry number and way number to confirm by using ENT[3:0] (D[7:4]/0x48322) and WAY[3:0]

(D[3:0]/0x48322), respectively.

∗ ENT[3:0]: Entry Number Setting Bits in the MMU Entry Register (D[7:4]/0x48322)

∗ WAY[3:0]: Way Number Setting Bits in the MMU Entry Register (D[3:0]/0x48322)

The WAY0 to WAY3 bits correspond to ways 0 to 3, respectively. Always be sure to set one bit at a time. If two

or more bits are set, a way cannot be specified correctly.

2. Reading out the TLB information

To read out the TLB information, use the control bits available separately for the TAG part and DATA part.

Reading out the TAG part

Write a 1 to TAGRD (D5/0x4832C).

∗ TAGRD: TAG Entry Read Bit in the TLB Control Register (D5/0x4832C)

As a result, the TAG part comparison address and page setup information in the entry/way specified in step

1 will be loaded in the MMU TAG Address Register (0x48328) and MMU Page Setting Register (0x4832A),

respectively.

Reading out the DATA part

Write a 1 to DATRD (D1/0x4832C).

∗ DATRD: DATA Entry Read Bit in the TLB Control Register (D1/0x4832C)

As a result, the 16 high-order bits (CA[31:16]) and 4 low-order bits (CA[15:12]) in the entry/way specified

in step 1 will be loaded in the MMU Common Data Address Register (0x48326) and D[15:12] of the MMU

4KB Data Address Register (0x48324), respectively. For 64KB per page, only the MMU Common Data

Address Register (0x48326) is effective. The MMU 4KB Data Address Register (0x48324) is used for 4KB

per page.

After the operation above, read the respective registers to confirm the TLB information. If necessary, the TAG

part and DATA part information can be loaded in the respective registers at one time by writing a 1 to both

TAGRD (D5/0x4832C) and DATRD (D1/0x4832C) at the same time. Writing a 0 to these bits has no effect.

II.5.5.3 Flushing the TLB

Flush means invalidating entries in the TLB. When the TLB is flushed, all VLD (valid), ACC (access), and DTY

(dirty) bits in the TAG part and the LRU are initialized to invalidate the TLB. The contents of the DATA part are not

cleared. To flush the TLB, write a 1 to FLUSH (D8/0x4832C).

∗ FLUSH: TLB Flush Control Bit in the TLB Control Register (D8/0x4832C)

Before flushing the TLB, always be sure to set MEN (D0/0x48320) to 0 to disable the MMU.

∗ MEN: MMU Enable Bit in the MMU Control Register (D0/0x48320)

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MMU

II.5.6 MMU Exceptions

II.5.6.1 Types of MMU Exceptions

There are six distinct causes of MMU exceptions for the C33 ADV Core as outlined below.

1. MMU access protect exception

This exception occurs for a violation of page protection when an attempt is made to read or write to an access-

protected page (TAG part ACP bit = 1). Since this exception is generated prior to memory access, no data is

read or written to the page in question.

When this exception occurs, exception status bit EXPACP (D5/0x4832E) is set to 1.

∗ EXPACP: MMU Access-Protect Exception Status Bit in the MMU Exception Status Register (D5/0x4832E)

2. MMU user mode protect exception

This exception occurs for a violation of page protection when an attempt is made to read or write to a user

mode-protected page (TAG part UMP bit = 1) in user mode. Since this exception is generated prior to memory

access, no data is read or written to the page in question.

When this exception occurs, exception status bit EXPUMP (D6/0x4832E) is set to 1.

∗ EXPUMP: MMU User-Mode-Protect Exception Status Bit in the MMU Exception Status Register (D6/0x4832E)

3. MMU write protect exception

This exception occurs for a violation of page protection when an attempt is made to write to a write-protected

page (TAG part WRP bit = 1). Since this exception is generated prior to memory access, no data is written to

the page.

When this exception occurs, exception status bit EXPWRP (D7/0x4832E) is set to 1.

∗ EXPWRP: MMU Write-Protect Exception Status Bit in the MMU Exception Status Register (D7/0x4832E)

4. ASID exception

This exception occurs for a violation of process protection when using ASID-based multiple virtual spaces in

a process to access an address space exceeding the 64MB boundary. Specifically, this exception occurs when

the logical address VA[31:26] and logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) do not match as compared

before VA[31:26] is replaced with ASID. Therefore, no data is read or written to the said address.

When this exception occurs, exception status bit EXPASID (D4/0x4832E) is set to 1.

∗ EXPASID: ASID Exception Status Bit in the MMU Exception Status Register (D4/0x4832E)

A request to the CPU for processing this exception is generated only when AEXPEN (D4/0x48300) in the

HBCU is set to 1 (default = 0). However, EXPASID (D4/0x4832E) is set to 1 whenever this exception occurs,

regardless of whether AEXPEN (D4/0x48300) is set.

5. MMU multi-hit exception

This exception occurs when multiple ways make a hit in address comparison. Since this exception is generated

prior to memory access, no data is read or written.

When this exception occurs, exception status bit EXPMLT (D3/0x4832E) is set to 1.

∗ EXPMLT: MMU Multi-Hit Exception Status Bit in the MMU Exception Status Register (D3/0x4832E)

The ways that made a hit can be confirmed using HITWAY[3:0] (D[11:8]/0x48322).

∗ HITWAY[3:0]: Hit Way Number Bits in the MMU Entry Register (D[11:8]/0x48322)

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6. MMU miss exception

This exception occurs due to one of the conditions listed below.

• A way matched in address comparison is not found

• The VLD bit in the TAG part has been set to 0.

• ASID enable/disable information in the HBCU is different from the ASIDUSE bit status in the TAG part.

In such case, the TLB must be replaced (i.e., set up its content again).

When this exception occurs, exception status bit EXPMISS (D2/0x4832E) is set to 1.

∗ EXPMISS: MMU Miss Exception Status Bit in the MMU Exception Status Register (D2/0x4832E)

The ways that require replacement can be confirmed using REPWAY[3:0] (D[15:12]/0x48322).

∗ REPWAY[3:0]: Replace Way Number Bits in the MMU Entry Register (D[15:12]/0x48322)

One signal line is available to forward MMU exception processing requests to the CPU. Therefore, this signal line

is commonly used for the above six causes of MMU exceptions. If any MMU exception occurs, read the MMU

Exception Status Register (0x4832E) in the MMU exception handler routine to determine the cause of occurrence.

II.5.6.2 MMU Exception Vector Address and Stack Area

Internal RAM addresses 0x00000010 through 0x0000001F in area 0 are reserved for use in case of MMU

exceptions.

0x00000010: MMU exception vector address is saved here (4 bytes).

0x00000018: PC is saved here at MMU exception occurrence (4 bytes).

0x0000001C: R0 is saved here at MMU exception occurrence (4 bytes).

To use the MMU, always be sure to set the vector address at 0x00000010 before enabling the MMU. Moreover,

because the internal RAM addresses in area 0 above are reserved for MMU use, do not use this internal RAM area

for any other purpose.

II.5.6.3 Processing when an MMU Exception Occurs

When an MMU exception occurs, the MMU sends an MMU exception request to the CPU, and simultaneously sets

the MMU exception occurrence status in each register as described below.

• The cause of the MMU exception that occurred is set in the MMU Exception Status Register (0x4832E).

• The logical address that caused the MMU exception to occur is set in the MMU Exception Address Registers 1

and 2 (0x48330 and 0x48332).

• The following items are set in the MMU Entry Register (0x48322):

- The entry number that caused the MMU exception to occur is set in ENT[3:0] (D[7:4]).

- One of the HITWAY[3:0] (D[11:8]) bits corresponding to the way number that caused the MMU exception to

occur is set. In case of multiple hits, the bits corresponding to all “hit” ways are set.

- If the cause of MMU exception is an MMU miss, the way number to be replaced is set in REPWAY[3:0]

(D[15:12]) and WAY[3:0] (D[3:0]).

When an MMU exception occurs, first read the MMU Exception Status Register (0x4832E) in the MMU exception

handling routine to confirm what caused the MMU exception to occur. The MMU exception status bits are not

automatically cleared. Always be sure to clear all status bits in MMU exception handling. If these bits remain set

when returning from the MMU exception handler routine, the same exception will reoccur.

Next, inspect the TLB information held when the exception occurred. The TLB should be altered to the appropriate

content. To return from the MMU exception handler routine, execute the retm instruction.

Figure II.5.6.3.1 shows the flow of processing performed when an MMU exception occurs.

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S1C33401 TECHNICAL MANUAL EPSON II-5-15

MMU

Set MMU exception information

in each register

Send an MMU exception request

to the CPU

Switch to supervisor mode

Save the PC to address 0x00000018

Save R0 to address 0x0000001C

Fetch the MMU exception vector

from address 0x00000010

Read the MMU register

to confirm the cause of exception

Clear all MMU exception status bits

Alter the TLB content

Restore R0 from address 0x0000001C

Restore the PC from address 0x00000018

Return to previous operating mode

Jump to the PC address

Execute the retm instruction

Jump to the vector address

MMU exception occurs

Processing in hardware

Processing in software

Processing in hardware

Figure II.5.6.3.1 Processing Flow when MMU Exception Occurs

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II-5-16 EPSON S1C33401 TECHNICAL MANUAL

II.5.7 Details of the Control Registers

Table II.5.7.1 List of MMU Registers

Address

0x00048320

0x00048322

0x00048324

0x00048326

0x00048328

0x0004832A

0x0004832C

0x0004832E

0x00048330

0x00048332

0x00048334

Function

Controls the entire MMU

Specifies way and entry numbers, and indicates status

Specifies DATA part translation address

(used only for 4KB per page)

Specifies DATA part translation address

(common to 4KB/64KB per page)

Sets TAG part comparison address

Specifies TAG part control bits

Controls TLB read/write

MMU exception status

16 low-order logical address bits

when MMU exception occurred

16 high-order logical address bits

when MMU exception occurred

6-bit LRU data

MMU Control Register (pMMU_CNTL)

MMU Entry Register (pMMU_ENTRY)

MMU 4KB Data Address Register

(pMMU_ADR_4K)

MMU Common Data Address Register

(pMMU_ADR_COM)

MMU TAG Address Register (pMMU_TAD_ADR)

MMU Page Setting Register (pMMU_PAGE_SETUP)

TLB Control Register (pMMU_TLB_CNTL)

MMU Exception Status Register

(pMMU_EXCP_STAT)

MMU Exception Address Register 1

(pMMU_EXP_ADR)

MMU Exception Address Register 2

MMU LRU Register (pMMU_LRU)

Size

The following describes each MMU control register.

The MMU control registers are mapped into the 16-bit device area from 0x48320 to 0x48334, and can be accessed

in units of half-words or bytes.

Note: When setting the MMU control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

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MMU

0x48320: MMU Control Register (pMMU_CNTL)

Name

Address

–

MRUWP

–

64KMD

–

ASIDMIX

–

MEN

D15–13

D12

D11–9

D7–5

D3–1

reserved

MMU register user write protect

reserved

Page size select

reserved

Entry number generation mode

reserved

MMU enable

1Protect 0

Write enabled

164KB 04KB

1Enabled 0Disabled

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

0048320

(HW)

–

MMU

control

(pMMU_CNTL)

1ASID mixed 0VA only

D[15:13] Reserved

D12 MRUWP: MMU Register User Write Protect Bit

Enables/disables write to the MMU registers in user mode.

1 (R/W): Disable write

0 (R/W): Enable write (default)

Even if this bit is 1, the MMU registers can always be accessed for write operation in supervisor mode.

To set up the MMU registers in user mode, reset this bit by writing a 0 in supervisor mode.

D[11:9] Reserved

D8 64KMD: Page Size Select Bit

Sets a page size.

1 (R/W): 64KB per page

0 (R/W): 4KB per page (default)

D[7:5] Reserved

D4 ASIDMIX: Entry Number Generation Mode Bit

Specifies whether to combine the address and ASID to generate an entry number.

1 (R/W): Combine

0 (R/W): Do not combine (default)

When this bit is set to 1, the 4-bit field in the logical address that indicates an entry number (i.e.,

VA[15:12] for 4KB per page, VA[19:16] for 64KB per page) is combined with ASID to generate an

entry number. This method helps increase the hit rate when using multiple virtual spaces. When this bit

is 0, only VA is used to generate an entry number.

D[3:1] Reserved

D0 MEN: MMU Enable Bit

Enables the MMU.

1 (R/W): Enable

0 (R/W): Disable (default)

To use the MMU, set this bit to 1. At the same time, the MMUENx bit in the HBCU register that sets

block ‘x’ (x = 0–7) in which the MMU is used must also be set to 1.

∗ MMUENx: Block x MMU Enable Bit in the Block x Configuration Register (D4/0x48302 + 2•x)

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0x48322: MMU Entry Register (pMMU_ENTRY)

Name

Address

REPWAY3

REPWAY2

REPWAY1

REPWAY0

HITWAY3

HITWAY2

HITWAY1

HITWAY0

ENT3

ENT2

ENT1

ENT0

WAY3

WAY2

WAY1

WAY0

D15

D14

D13

D12

D11

D10

Replace Way number

Hit Way number

Entry number setting

Way number setting

R/W

0048322

(HW)

0 to 15

MMU

entry

(pMMU_ENTRY)

1Way 3 0

–

1Way 2 0

–

1Way 1 0

–

1Way 0 0

–

1Way 3 0

–

1Way 2 0

–

1Way 1 0

–

1Way 0 0

–

1Way 3 0

–

1Way 2 0

–

1Way 1 0

–

1Way 0 0

–

D[15:12] REPWAY[3:0]: Replace Way Number Bits

Indicates the way to be replaced as determined from the LRU value. (Default: 0b0001)

The four bits REPWAY3 to REPWAY0 correspond to ways 3 through 0, respectively, with the bit for

the way to be replaced set to 1. If an MMU miss exception occurs, read these four bits to confirm the

way to be replaced. Writing to these four bits has no effect.

D[11:8] HITWAY[3:0]: Hit Way Number Bits

Indicates the way that made a hit when any cause of MMU exception occurs. (Default: 0b0000)

The four bits HITWAY3 to HITWAY0 correspond to ways 3 through 0, respectively, with the bit for the

way that made a hit set to 1. For a multi-hit exception, the bits for all ways that made a hit are set to 1.

Writing to these four bits has no effect.

D[7:4] ENT[3:0]: Entry Number Setting Bits

When setting or reading the content of the TLB, these bits are used to set the entry number (0 to 15) in

the TLB. (Default: 0b0000)

If any cause of exception occurs, the entry that was accessed at that point is automatically set. However,

these bits have no effect for ASID exceptions.

D[3:0] WAY[3:0]: Way Number Setting Bits

When setting or reading the content of the TLB, these bits are used to set the way number in the TLB.

(Default: 0b0000)

If any cause of exception occurs, the way to be replaced (same information as REPWAY[3:0]) is set. If

there is no cause of exception that occurred, the content set in these bits is read out directly as is.

The four bits WAY3 to WAY0 correspond to ways 3 through 0, respectively. When specifying any way,

always be sure to set one bit at a time. If two or more bits are set before writing to the TLB, the same

information will be written to all specified ways.

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MMU

0x48324: MMU 4KB Data Address Register (pMMU_ADR_4K)

0x48326: MMU Common Data Address Register (pMMU_ADR_COM)

Name

Address

CA15

CA14

CA13

CA12

–

D15

D14

D13

D12

D11–0

Translation physical address

A[15:12]

(effective in 4KB/page mode)

reserved

–

R/W

–0 when being read.

0048324

(HW)

–

0x0 to 0xF

MMU 4KB

data address

(pMMU_ADR_4K)

CA31

CA30

CA29

CA28

CA27

CA26

CA25

CA24

CA23

CA22

CA21

CA20

CA19

CA18

CA17

CA16

D15

D14

D13

D12

D11

D10

Translation physical address

A[31:16]

R/W

0048326

(HW)

0x0 to 0xFFFF

MMU common

data address

(pMMU_ADR_COM)

These two registers are used to save the translation address to be written to or read from the DATA part of the TLB.

(Default: 0x00000)

To set up the DATA part of the TLB, write the physical address derived from translation to these registers and set

DATWR (D0/0x4832C) to 1. To confirm the DATA part of the TLB, set DATRD (D1/0x4832C) to 1 and read the

physical address loaded in these registers. The entry/way set in the MMU Entry Register (0x48322) is the target

from or to which the address is read or written.

D[15:12]/0x48324 CA[15:12]: Translation Physical Address A[15:12]

Contains the 4 low-order bits of the physical address.

These four bits are only used for 4KB per page, and have no effect for 64KB per page.

D[15:0]/0x48326 CA[31:16]: Translation Physical Address A[31:16]

Contains the 16 high-order bits of the physical address.

These 16 bits are used for both 4KB per page and 64KB per page.

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0x48328: MMU TAG Address Register (pMMU_TAD_ADR)

Name

Address

CVA31

CVA30

CVA29

CVA28

CVA27

CVA26

CVA25

CVA24

CVA23

CVA22

CVA21

CVA20

CVA19

CVA18

CVA17

CVA16

D15

D14

D13

D12

D11

D10

Comparison address A[31:16]

in TAG

R/W

CVA[19:16] is not

effective in

64KB/page mode

0048328

(HW)

0x0 to 0xFFFF

MMU TAG

address

(pMMU_TAD_ADR)

D[15:0] CVA[31:16]: Comparison Address

These bits are used to save the comparison address to be written to or read from the TAG part of the

TLB. (Default: 0x0000)

This is the address compared with the logical address (or ASID + logical address) sent from the HBCU.

For 64KB per page, CVA[19:16] (D[3:0]) has no effect.

To set up the TAG part of the TLB, write the comparison address to this register and information on the

page control bits to the MMU Page Setting Register (0x4832A), then set TAGWR (D4/0x4832C) to

1. To confirm the comparison address set in the TAG part of the TLB, set TAGRD (D5/0x4832C) to 1,

then read the comparison address loaded in this register. The entry/way set in the MMU Entry Register

(0x48322) is the target from or to which the address is read or written.

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MMU

0x4832A: MMU Page Setting Register (pMMU_PAGE_SETUP)

Name

Address

–

ASIDUSE

–

UMP

ACP

VLD

ACC

DTY

D15–9

reserved

Use of ASID

reserved

Write protect

User mode access protect

Access protect

Cache enable

TLB entry valid bit

Page access bit

Dirty bit

1Used 0Not used

1Protected 0Enabled

1Valid 0Invalid

–

R/W

–

R/W

0 when being read.

004832A

(HW)

–

MMU

page

setting register

(pMMU_PAGE

_SETUP)

1Protected 0Enabled

1Enabled 0Disabled

1Accessed 0

Not accessed

1Written 0Not written

This register is used to save the status of page control bits to be written to or read from the TAG part of the TLB.

To set up the TAG part of the TLB, write information on the page control bits to this register and the comparison

address to the MMU TAG Address Register (0x48328), then set TAGWR (D4/0x4832C) to 1. To confirm the status

of page control bits in the TAG part of the TLB, set TAGRD (D5/0x4832C) to 1, then read the status of each bit set

in this register. The entry/way set in the MMU Entry Register (0x48322) is the target from or to which status is read

or written.

D[15:9] Reserved

D8 ASIDUSE: Use of ASID Bit

This bit is used to set or confirm the ASIDUSE bit in the TAG part of the TLB.

1 (R/W): Use ASID

0 (R/W): Do not use ASID (default)

ASID processing is controlled by the control bits in the HBCU. The ASIDUSE bit in the TAG part of

the TLB is used to confirm whether this bit is consistent with the ASID enable/disable information sent

from the HBCU. If inconsistent, even when the compared addresses match, an MMU miss is assumed.

D7 Reserved

D6 WP: Write-Protect Bit

This bit is used to set or confirm the WP bit in the TAG part of the TLB.

1 (R/W): Write protect

0 (R/W): Write enable (default)

The WP bit specifies to write-protect a page. When the WP bit in the TAG part is set to 1, the relevant

page is protected against write operation in both supervisor and user modes, so that an attempt to write

to said page generates an MMU write protect exception.

D5 UMP: User Mode Access-Protect Bit

This bit is used to set or confirm the UMP bit in the TAG part of the TLB.

1 (R/W): Disable access in user mode

0 (R/W): Enable access in user mode (default)

The UMP bit sets a supervisor mode-only page. When the UMP bit in the TAG part is set to 1, the

relevant page is disabled against access in user mode (for both read and write), so that an attempt to

access said page generates an MMU user mode protect exception.

D4 ACP: Access-Protect Bit

This bit is used to set or confirm the ACP bit in the TAG part of the TLB.

1 (R/W): Disable access

0 (R/W): Enable access (default)

The ACP bit specifies to protect a page. When the ACP bit in the TAG part is set to 1, the relevant

page is disabled against access in both supervisor and user modes (for both read and write), so that an

attempt to access said page generates an MMU access protect exception.

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II-5-22 EPSON S1C33401 TECHNICAL MANUAL

D3 CE: Cache Enable Bit

This bit is used to set or confirm the CE bit in the TAG part of the TLB.

1 (R/W): Use cache

0 (R/W): Do not use cache (default)

When the CE bit in the TAG part is set to 1 with the cache enabled in both HBCU and CCU, the HBCU

uses the cache when accessing a page for read/write operation.

D2 VLD: TLB Entry Valid Bit

This bit is used to set or confirm the VLD bit in the TAG part of the TLB.

1 (R/W): Valid entry

0 (R/W): Invalid entry (default)

When the VLD bit in the TAG part is set to 1, the relevant entry is used as valid. When the VLD bit is 0,

the entry is not used.

D1 ACC: Page Access Bit

This bit is used to set or confirm the ACC bit in the TAG part of the TLB.

1 (R/W): Accessed

0 (R/W): Not accessed (default)

The ACC bit in the TAG part is set to 1 when the relevant page is accessed (for read or write). It can be

set to 0 or 1 by this bit as required.

D0 DTY: Dirty Bit

This bit is used to set or confirm the DTY bit in the TAG part of the TLB.

1 (R/W): Written to page

0 (R/W): Not written to page (default)

The DTY bit in the TAG part is set to 1 when data is written to the relevant page. It can be set to 0 or 1

by this bit as required.

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S1C33401 TECHNICAL MANUAL EPSON II-5-23

MMU

0x4832C: TLB Control Register (pMMU_TLB_CNTL)

Name

Address

–

LRURD

LRUWR

–

FLUSH

–

TAGRD

TAGWR

–

DATRD

DATWR

D15–14

D13

D12

D11–9

D7–6

D3–2

reserved

LRU entry read

LRU entry write

reserved

TLB-flush control

reserved

TAG entry read

TAG entry write

reserved

DATA entry read

DATA entry write

1Read 0Invalid

1Clear V bits 0Invalid

–

0 when being read.

004832C

(HW)

–

1Write 0Invalid

1Read 0Invalid

1Write 0Invalid

–

TLB control

(pMMU_TLB_CNTL)

1Write 0Invalid

1Read 0Invalid

This register is used to set up and read out the TLB and LRU. Before read/write control by this register can be

exercised, the following settings are required:

1. Specifying the entry/way (when reading or writing)

Use the MMU Entry Register (0x48322) to specify.

2. Setting the content to be written to the TLB in the registers below (when writing TLB)

TAG part comparison address: MMU TAG Address Register (0x48328)

TAG part page control bits: MMU Page Setting Register (0x4832A)

DATA part physical address: MMU 4KB Data Address Register (0x48324) For 4KB per page only

MMU Common Data Address Register (0x48326)

When reading the TLB, read information is loaded in these registers.

3. Setting the content to be written to the LRU in the register below (when writing LRU information)

6-bit LRU data: MMU LRU Register (0x48334)

When reading the LRU, read information is loaded in this register.

Note: TLB/LRU initialization or the alteration of TLB/LRU content pursuant to the occurrence of an MMU

exception should always be performed in an area where the MMU is not used.

D[15:14] Reserved

D13 LRURD: LRU Entry Read Bit

Reads LRU information from the specified entry.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the LRU information in the entry specified in 1 above is read out,

and set in the MMU LRU Register (0x48334).

D12 LRUWR: LRU Entry Write Bit

Writes LRU information to the specified entry.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the information set in the MMU LRU Register (0x48334) in 3 above

is written to the entry specified in 1 above.

D[11:9] Reserved

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II-5-24 EPSON S1C33401 TECHNICAL MANUAL

D8 FLUSH: TLB Flush Control Bit

Clears all VLD (Valid) bits to invalidate the entire TLB.

1 (W): Clear all VLD bits in entire TLB

0 (W): Has no effect

0 (R): Always 0 when read (default)

D[7:6] Reserved

D5 TAGRD: TAG Entry Read Bit

Reads out information from the TAG part of the TLB.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the TAG part information in the entry/way specified in 1 above is

read out and set in the TAG part register listed in 2 above.

D4 TAGWR: TAG Entry Write Bit

Writes information to the TAG part of the TLB.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the information set in the TAG part register in 2 above is written to

the TAG part in the entry/way specified in 1 above.

D[3:2] Reserved

D1 DATRD: DATA Entry Read Bit

Reads information from the DATA part of the TLB.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the DATA part information in the entry/way specified in 1 above is

read out, and set in the DATA part register listed in 2 above.

D0 DATWR: DATA Entry Write Bit

Writes information to the DATA part of the TLB.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When this bit is set by writing a 1, the information set in the DATA part register in 2 above is written to

the DATA part in the entry/way specified in 1 above.

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S1C33401 TECHNICAL MANUAL EPSON II-5-25

MMU

0x4832E: MMU Exception Status Register (pMMU_EXCP_STAT)

Name

Address

–

ASMIR

ASRDWR

ASSVM

ASIRDA

ASASID

EXPWRP

EXPUMP

EXPACP

EXPASID

EXPMLT

EXPMISS

–

EXP

D15–13

D12

D11

D10

reserved

Mirrored access status

Read/write status

Supervisor/user mode status

Instruction fetch/data R/W status

ASID status

MMU write-protect exception

MMU user-mode-protect exception

MMU access-protect exception

ASID exception

MMU multi-hit exception

MMU miss exception

reserved

MMU exception (all causes)

1Mirrored 0

Not mirrored

Supervisor

0User

1Read 0Write

1Occurred 0

Not occurred

–

R/W

–

R/W

0 when being read.

004832E

(HW)

–

MMU

exception

status register

(pMMU_EXCP

_STAT)

1Used 0Not used

1Instruction 0Data

1Occurred 0

Not occurred

1Occurred 0

Not occurred

1Occurred 0

Not occurred

1Occurred 0

Not occurred

1Occurred 0

Not occurred

1Occurred 0

Not occurred

D[15:13] Reserved

D12 ASMIR: Mirrored Access Status Bit

Indicates whether the latest MMU access was made in a mirroring-enabled state.

1 (R): Mirrored

0 (R): Not mirrored (default)

1/0 (W): Has no effect

D11 ASRDWR: Read/Write Status Bit

Indicates whether read or write operation was performed in the latest MMU access.

1 (R): Read

0 (R): Write (default)

1/0 (W): Has no effect

D10 ASSVM: Supervisor/User Mode Status Bit

Indicates whether supervisor or user mode was used for the latest MMU access made.

1 (R): Supervisor mode

0 (R): User mode (default)

1/0 (W): Has no effect

D9 ASIRDA: Instruction Fetch/ Data Read-Write Status Bit

Indicates whether instruction fetch or data read/write operation was performed in the latest MMU

access.

1 (R): Instruction fetch

0 (R): Data read/write (default)

1/0 (W): Has no effect

D8 ASASID: ASID Status Bit

Indicates whether ASID was used in the latest MMU access.

1 (R): ASID used

0 (R): ASID not used (default)

1/0 (W): Has no effect

D7 EXPWRP: MMU Write-Protect Exception Status Bit

Indicates the status of whether an MMU write protect exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set when an attempt was made to write to a write-protected page (TAG part WRP bit = 1).

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II-5-26 EPSON S1C33401 TECHNICAL MANUAL

D6 EXPUMP: MMU User-Mode-Protect Exception Status Bit

Indicates the status of whether an MMU user mode protect exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set when an attempt was made to read or write to a user mode-protected page (TAG part

UMP bit = 1) in user mode.

D5 EXPACP: MMU Access-Protect Exception Status Bit

Indicates the status of whether an MMU access protect exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set when an attempt was made to read or write to an access-protected page (TAG part ACP

bit = 1) in either supervisor or user mode.

D4 EXPASID: ASID Exception Status Bit

Indicates the status of whether an ASID exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This exception is provided (when using multiple virtual spaces) to detect whether a process has

accessed an address space exceeding the 64KB boundary. This bit is set when the logical address

VA[31:26] and the logical ASID or ASID_VA[5:0] (D[5:0]/0x48314) do not match as compared before

VA[31:26] is replaced with ASID.

D3 EXPMLT: MMU Multi-Hit Exception Status Bit

Indicates the status of whether an MMU multi-hit exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set when two or more ways make a hit in address comparison.

D2 EXPMISS: MMU Miss Exception Status Bit

Indicates the status of whether an MMU miss exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set when no matching ways are found in address comparison.

D1 Reserved

D0 EXP: MMU Exception Status Bit

Indicates that an MMU exception occurred.

1 (R/W): Occurred

0 (R/W): Not occurred (default)

This bit is set to 1 when one of exception status bits in D[7:2] was set to 1. Conversely, when this bit is 0,

D[7:2] has no effect.

Notes: • The exception status bits (D[7:2] and D0) are not automatically cleared. Always be sure to

clear all status bits by writing a 0 in the exception handling routine. If these bits remain set

when the exception handler routine is terminated by the retm instruction, the MMU exception

will reoccur.

• There is only one signal line to forward MMU exception processing requests to the CPU.

Therefore, this signal line is commonly used for the six causes of exceptions. If any MMU

exception occurs, read the exception status bits in this register (D[7:2] and D0) to determine

the cause of the exception that occurred. If two or more causes of exceptions occur at the

same time, all corresponding status bits are set to 1.

• The MMU is disabled during MMU exception handling (PSR register ME bit = 1). Even if

the MMU exception handler routine is located in a block where the MMU is enabled for use,

no address translation is performed and logical addresses are handled directly as physical

addresses.

II C33 ADV CORE BLOCK: MEMORY MANAGEMENT UNIT (MMU)

S1C33401 TECHNICAL MANUAL EPSON II-5-27

MMU

0x48330: MMU Exception Address Register 1 (pMMU_EXP_ADR)

0x48332: MMU Exception Address Register 2

Name

Address

EA15

EA14

EA13

EA12

EA11

EA10

EA9

EA8

EA7

EA6

EA5

EA4

EA3

EA2

EA1

EA0

D15

D14

D13

D12

D11

D10

Exception occurred logical

address (low-order 16 bits)

0048330

(HW)

MMU exception

address

(pMMU_EXP_ADR)

EA31

EA30

EA29

EA28

EA27

EA26

EA25

EA24

EA23

EA22

EA21

EA20

EA19

EA18

EA17

EA16

D15

D14

D13

D12

D11

D10

Exception occurred logical

address (high-order 16 bits)

0048332

(HW)

MMU exception

address

These registers are used to save the logical address being sent from the HBCU (while being accessed by the CPU)

when an exception occurred. (Default: 0x00000000)

D[15:0]/0x48330 EA[15:0]: Exception Occurred Logical Address (low-order 16 bits)

These are the 16 low-order bits of the logical address, equivalent to address[15:0] output by the HBCU.

D[15:0]/0x48332 EA[31:16]: Exception Occurred Logical Address (high-order 16 bits)

These are the 16 high-order bits of the logical address, equivalent to address[31:16] output by the

HBCU.

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II-5-28 EPSON S1C33401 TECHNICAL MANUAL

0x48334: MMU LRU Register (pMMU_LRU)

Name

Address

–

LRU5

LRU4

LRU3

LRU2

LRU1

LRU0

D15–6

reserved

LRU information

–

R/W

0 when being read.

0048334

(HW)

MMU LRU

(pMMU_LRU)

–

D[15:6] Reserved

D[5:0] LRU[5:0]: LRU Information

These bits are used to save the LRU information to be written to or read from the specified entry. (Default:

0x0000)

To set LRU information, write the information to this register, then set LRUWR (D12/0x4832C) to 1.

To confirm the LRU information set in an entry, set LRURD (D13/0x4832C) to 1, then read the data

loaded in this register. The entry set in the MMU Entry Register (0x48322) is the target from or to

which the LRU information is read or written.

When an MMU exception occurs, the LRU information of the entry in which the exception occurs is

loaded to this register.

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S1C33401 TECHNICAL MANUAL EPSON II-5-29

MMU

II.5.8 Precautions

• To use the MMU in block ‘x’ (x = 0–7), the corresponding MMUENx bit (D4) in the Block x Configuration

be set to 1. Moreover, the MEN bit (D0) of the MMU Control Register (0x48320) in the MMU must also be set to 1.

Before the MMU can be used, the HBCU and MMU should both be set.

After writing data to the register, read the register to make sure that the contents have been set properly.

• To use the MMU in combination with the cache, TLB setup in the MMU is also required, in addition to the

settings above. To enable use of the cache for a page, set the corresponding CE bit (cache enable) in the TAG part

of the TLB to 1.

When the MMU is to be used, the CE bit for the relevant page is checked to determine whether the cache is

enabled. Whether the cache is enabled in the CCU and HBCU is then checked.

• TLB initialization or the alteration of TLB content pursuant to occurrence of an MMU exception should always

be performed in an area where the MMU is not used.

• The MMU is disabled during MMU exception handling (PSR register ME bit = 1). Note that even if the MMU

exception handler routine is located in a block where the MMU is enabled for use, no address translation is

performed and logical addresses are handled directly as physical addresses.

• When setting up the TLB, make sure that no physical addresses derived from address translation will fall within

the lower 4MB (i.e., areas 0 to 6).

Moreover, when mirroring is enabled in the HBCU (by setting MIR (D0/0x48300) to 1), the upper 3GB (1GB ×

3) in the 4GB space becomes a mirror area of each corresponding lower 1GB. In this case, also make sure that no

physical addresses derived from address translation by the TLB will fall within the lower 4MB in each 1GB area.

Note that the lower 4MB in each 1GB mirror are excluded from the object of mirroring and cannot be mirrored.

For details about mirroring, see Section II.4, “High-Speed Bus Control Unit (HBCU).”

• Be aware that external access is performed if the physical address translated by the MMU is an address in the

internal RAM area (area 0/3), internal I/O area (area 1), or debug area (area 2). The internal area will not be

accessed. For example, if the physical address translated by the MMU is address 0x0, the internal RAM is not

accessed and external access to address 0x0 is performed.

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THIS PAGE IS BLANK.

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

S1C33401 TECHNICAL MANUAL EPSON II-6-1

CCU

II.6 Cache Control Unit (CCU)

II.6.1 Overview of the CCU

The C33 ADV Core Block contains a Cache Control Unit (CCU) that includes an 8KB cache by physical addresses.

The CCU is a mixed type of instruction/data cache, and uses a 4-way set-associative method.

The following outlines the main features of the CCU.

• Physical address cache

• Uses a 4-way set-associative method, with 128 entries per way, for a total of 512 lines supported.

• Each line is comprised of 4 words (16 bytes).

• With the 4GB logical address space divided into eight 512MB blocks, instruction and data caches can be enabled

or disabled independently for each block.

• The method of writing to the cache can be selected from write-back and write-through modes.

• A function to lock a specified way is provided.

• The interrupt handler routine can be locked according to interrupt priority level.

• A forwarding function is included to transfer necessary instructions or data immediately to the CPU even during

refill.

* A unit of memory area in the cache is called a line; a set of four lines sharing address [10:4] is called an entry.

Four lines in one entry are physically referenced by Ways 0 to 3, whereas four words in one line are referenced

by W0–3.

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II-6-2 EPSON S1C33401 TECHNICAL MANUAL

II.6.2 Configuration of the Cache

The cache in the C33 ADV Core Block is a 4-way, set-associative cache.

The cache has 128 entries, with four lines (ways) per entry. Since 16 bytes (4 words) of data can be saved in one

line, the cache has a maximum storage capacity of 8KB. Figure II.6.2.1 shows the general configuration of the

cache.

LRU

Entry 0

Entry 1

Entry 2

Entry 3

Entry 126

Entry 127

TAG DATA

Way 0

Way 1

Way 2

Way 3 Way 3

Way 2

Way 1

Way 0

W0W1W2W3

Figure II.6.2.1 General Configuration of the Cache

II.6.2.1 TAG Part and DATA Part

Each line consists of a TAG part and a DATA part, as shown in Figure II.6.2.1.1.

The TAG part consists of 24 bits, and includes a 21-bit comparison address, D (dirty) bit, V (valid) bit, and L (lock)

bit.

D bit: Set to 1 by writing to the cache. However, this is effective only when writing to the cache is performed in

write-back mode, so that if the cache is written to in write-through mode, the D bit remains 0.

V bit: Set to 1 (valid) when the cache is refilled, and reset to 0 (invalid) when flushed.

L bit: Set to 1 when the entry is locked. A locked entry is not refilled.

The DATA part is comprised of 4 words (16 bytes). When only the instruction cache is enabled in the Cache

Configuration Register (0x48340), only instructions are saved in the DATA part. Conversely, when only the data

cache is enabled, only data is saved in the DATA part. Instruction and data caches can both be enabled at the same

time.

TAG

CPA[31:11]

DATA

21 bits

32 bits

24 bits

128 bits

CPA[31:11]

Lock bit

Valid bit

Dirty bit

Comparison physical address

Word (32-bit) data. 4 words/line

W3–W0

0 (default) = Not locked

0 (default) = Invalid

0 (default) = Not updated

1 = Locked (The L bit is provided only for Ways 1 and 3.)

1 = Valid

1 = Updated

Figure II.6.2.1.1 Structure of Cache Lines

II.6.2.2 LRU Part

Since the cache is a 4-way configuration, there are four lines of 4-word data with the same entry number. In case

of a cache miss, one of the four ways of cache must be selected and replaced. The LRU part holds the number of

the way to be replaced. Although LRU (Least Recently Used) is the algorithm used to select the way that was least

recently accessed, a pseudo-LRU algorithm with a simplified circuit configuration is adopted for the cache in the

C33 ADV Core.

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S1C33401 TECHNICAL MANUAL EPSON II-6-3

CCU

II.6.3 Settings and Operation of the Cache

II.6.3.1 Enabling the Cache

When initially reset, the cache is disabled. To use the cache, the following settings are required:

1. Setting up the HBCU

The HBCU manages the 4GB logical address space separately in eight 512MB blocks. Either or both the

instruction and data caches can be enabled or disabled for each block individually.

To use the data cache in block ‘x’, set the DCx bit (D1) in the HBCU Block x Configuration Register to 1 (=

enable). To use the instruction cache, set the ICx bit (D0) in the same register to 1.

∗ DCx: Block x Data Cache Enable Bit in the Block x Configuration Register (D1/0x48302 + 2•x)

∗ ICx: Block x Instruction Cache Enable Bit in the Block x Configuration Register (D0/0x48302 + 2•x)

For details about the HBCU, see Section II.4, “High-Speed Bus Control Unit (HBCU).”

Even though either or both caches are enabled in the CCU, the caches cannot be used unless enabled in the

HBCU as described above.

2. Setting up the CCU

To use the data and instruction caches, set the DC (D1/0x48340) and IC (D0/0x48340) in the CCU to 1,

respectively.

∗ DC: Data Cache Enable Bit in the Cache Configuration Register (D1/0x48340)

∗ IC: Instruction Cache Enable Bit in the Cache Configuration Register (D0/0x48340)

3. Setting up the MMU (only when using the MMU)

To use the MMU in combination with the cache, the TLB in the MMU must also be set up, in addition to the

settings in 1 and 2 above.

When setting up the TLB for a page requiring cache use, set the CE bit (cache enable) in the TAG part to 1.

∗ CE: Cache Enable Bit in the MMU Page Setting Register (D3/0x4832A)

II.6.3.2 Address Comparison and Cache Hit/Miss

Since the cache in the C33 ADV Core Block is a physical cache, the addresses handled by the cache are physical

addresses, and not logical addresses.

Seven bits of PA[10:4] in the physical address (hereafter PA) represent an entry number. PA[31:11] contains the

comparison address to be compared with the physical address for comparison use (CPA[31:11]) set in the TAG part

for four ways of cache in the entry selected by PA[10:4].

For cache access performed by using the MMU in combination with the cache, the logical address received from

the CPU is translated into a physical address (hereafter MPA) by the MMU before being compared. Two bits of

PA[3:2] are a block offset used to select one of four words in the DATA part.

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II-6-4 EPSON S1C33401 TECHNICAL MANUAL

LRU

MUX

CMP0 CMP1

CMP2 CMP3

Entry 0

Entry 1

Entry 2

Entry 127

TAG

DATA

Comparison address

Way selection

PA[31:11]

PA[10:4]

PA[3:2] PA[1:0]

11 10 4 3 2 1 031

Physical address PA[31:0] from the HBCU

Address from MMU

Hit data

Way 1

Way 0

W3 W2 W1 W0

Hit

Way 2

Way 3

Entry No. WO WO: Word offset

BO : Byte offset

D[31:0]

Way 0

Way 1

Way 2

Way 3

Figure II.6.3.2.1 Operation of the Entire Cache

The following describes cache operation until a cache hit or miss can be determined.

1. An entry number (0 to 127) is generated from PA[10:4].

2. Information on four ways of cache are read from the TAG part of the selected entry. At the same time, the word

data indicated by the block offset PA[3:2] (i.e., one of W0 to W3) for four ways of cache are read from the

DATA part.

3. When not using the MMU

CPA[31:11] in the TAG part for each way of cache and PA[31:11] are compared.

When using the MMU

CPA[31:11] is compared with the address derived from translation by the MMU, instead of PA[31:11] output

by the CPU. The compared address varies depending on page settings in the MMU, as shown below.

For 4KB per page: CPA[31:11] and MPA[31:12] + PA11 are compared.

For 64KB per page: CPA[31:11] and MPA[31:16] + PA[15:11] are compared.

4. When a matching way is found in step 3 and the V bit in the TAG part is 1 (= valid), a cache hit is assumed. The

way that made the hit is determined here. When no matching ways are found in step 3, a cache miss is assumed.

For example, when PA[10:4] = 0b0000010 and PA[3:2] = 0b10, and Way 0 is a hit, W2 in Way 0 in entry 2 is

accessed for read or write operation.

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II.6.3.3 Read Operation

The following describes cache operation when a cache hit or miss occurs during read operation.

For a cache hit

The 32-bit data in the “hit” way is transferred to the CPU, with LRU information in the relevant entry being

updated at the same time.

For a cache miss

No instructions or data are transferred to the CPU.

In case of a cache miss, the way of cache to be replaced (i.e., least recently accessed way) is determined from

the current LRU information. Updating the DATA part for the way of cache thus determined is called “refill.”

A refill is performed in units of 4 words (16 bytes), with the target instruction or data read out from relevant

external memory and written to the cache. At the same time, the target instruction or data is transferred to the

CPU, with the LRU information updated. Although a refill is performed for all 4 words, the instruction or data

needed by the CPU is transferred to the CPU immediately after being read out (before refill is completed). (This

is called the “forwarding” function.)

When the D bit in the TAG part is 1 in write-back mode, it means that data is being written to the cache. In this

case, a write-back operation is inserted to synchronize cache and memory contents because said contents are

not synchronous.

II.6.3.4 Write Operation

There are two write operation modes: write-through and write-back. These write modes are selected to set the

WBEN bit (D4/0x48340) in the CCU and the WRMDx bit provided for each block in the HBCU.

∗ WBEN: Write-Back Enable Bit in the Cache Configuration Register (D4/0x48340)

∗ WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2•x)

Table II.6.3.4.1 Write Mode Settings

WBEN

WRMDx

Write mode

Write-back mode

Write-through mode

Write operation and the write modes are only effective for the data cache, and have no effect on the instruction

cache.

Write-through mode

In write-through mode, data is written to the cache when a cache write occurs, and at the same time written to

the relevant external memory. Therefore, data integrity between the cache and memory is always guaranteed.

For a cache hit

A write cycle is issued for both cache and external memory. The LRU information is also updated.

For a cache miss

In case of a cache miss, data is not written to the cache, but only written to external memory. In this case,

the LRU information is not updated because no data is written to the cache. Also a refill operation is not

performed.

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Write-back mode

In write-back mode, data is only written to the cache when a cache write occurs, and not written to the relevant

external memory. Therefore, high-speed execution is possible because only the cache is accessed for a data

write operation.

When data is written to the cache in write-back mode, the D bit in the TAG part of the relevant entry is set to 1,

indicating that the cache and relevant external memory are not synchronous.

For a cache hit

Data is only written to the cache, and the D bit in the TAG part for the “hit” way of cache is set to 1. The

LRU information is also updated.

For a cache miss

In case of a cache miss, the way of cache to be replaced is first determined from the current LRU

information and the D bit in the TAG part for that way examined. When the D bit = 0, a refill operation is

performed directly on the cache since data in that way of cache is consistent with external memory. When

the D bit = 1, refill and write-back operations are performed since the cache data is inconsistent with the

external memory. The cache has a dedicated 4-word buffer for write-back use, and a write-back operation is

performed in the manner described below.

1. The 4-word data to be written back (one to be replaced) is transferred to the dedicated buffer.

2. The way of cache to be replaced is refilled. At this time, the data read out from external memory is

replaced with the write data before being written to the cache.

3. The content of the dedicated write-back buffer is written back to external memory.

In step 3 (after completing step 2 above), the cache is ready for use. Therefore, the cache can be accessed

while data is written from the buffer back to external memory.

II.6.3.5 Flush

Flush means invalidating a cache entry. There are two types: cache flush and lock flush. For details about lock

flush, see Section II.6.4, “Lock Function.”

Cache flush

In this type of flush, the V and D bits in the TAG part for all valid lines of the cache are cleared to 0 to

invalidate the lines and initialize the LRU in all entries. Even if there is any line whose D bit = 1, no data is

written back. The L bit in the TAG part is cleared to 0, so that all lines are unlocked. The content of the DATA

part is not cleared.

To execute a cache flush, write a 1 to CFLSH (D8/0x48346).

∗ CFLSH: Cache-Flush Control Bit in the Cache Control Register (D8/0x48346)

Before flushing the cache, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable the

cache.

The D bits are also cleared by a cache flush. Therefore, when the cache is used in write-back mode, always be

sure to check the D bit status of all entries and perform a software write-back operation (described later) before

flushing the cache.

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II.6.3.6 Setting Up the Cache

The cache can be set up or read out via the CCU control registers. Therefore, it is possible to flush only a specific

entry of the cache.

TAG part

For read

The TAG part in a specific cache entry can be read out following the procedure described below.

1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way. For

reading the TAG part, WO[1:0] (D[3:2]/0x48348) that specifies a word offset is ignored.

∗ ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348)

∗ WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342)

2. Write a 1 to TAGRD (D5/0x48346).

∗ TAGRD: TAG Entry Read Bit in the Cache Control Register (D5/0x48346)

As a result, information on the TAG part in the specified cache entry will be loaded into the Cache

Entry Control Register (0x48344) and Cache TAG Address Registers 1 and 2 (0x48348 and 0x4834A).

3. Read the Cache Entry Control Register (0x48344) and Cache TAG Address Registers 1 and 2 (0x48348

and 0x4834A) to get information on the TAG part in the specified cache entry.

Setting up (altering settings)

The procedure described below allows the settings of the TAG part in a specific cache entry to be set up or

altered.

1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way. For

setting the TAG part, WO[1:0] (D[3:2]/0x48348) that specifies a word offset is ignored.

2. Write the information to be set or altered with to the Cache Entry Control Register (0x48344) and

Cache TAG Address Registers 1 and 2 (0x48348 and 0x4834A).

3. Write a 1 to TAGWR (D4/0x48346).

∗ TAGWR: TAG Entry Write Bit in the Cache Control Register (D4/0x48346)

As a result, the TAG part in the specified cache entry will be set up or altered.

DATA part

For read

The DATA part in a specific cache entry can be read out following the procedure described below.

1. Use ENT[6:0] (D[10:4]/0x48348), WAY[1:0] (D[1:0]/0x48342), and WO[1:0] (D[3:2]/0x48348) to

specify an entry, a way, and a word offset.

∗ ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348)

∗ WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342)

∗ WO[1:0]: Word Offset in the Cache TAG Address Register 1 (D[3:2]/0x48348)

2. Write a 1 to DATRD (D1/0x48346).

∗ DATRD: DATA Entry Read Bit in the Cache Control Register (D1/0x48346)

As a result, the specified word data information in the specified cache entry will be loaded in Cache

Data Registers 1 and 2 (0x4834C and 0x4834E).

3. Read Cache Data Registers 1 and 2 (0x4834C and 0x4834E) to get the specified word data information

in the specified cache entry.

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Setting up (altering settings)

The procedure described below allows the settings of the DATA part in a specific cache entry to be set up or

altered.

1. Use ENT[6:0] (D[10:4]/0x48348), WAY[1:0] (D[1:0]/0x48342), and WO[1:0] (D[3:2]/0x48348) to

specify an entry, a way, and a word offset.

2. Write the information to be set or altered with to Cache Data Registers 1 and 2 (0x4834C and

0x4834E).

3. Write a 1 to the cache control register DATWR bit (D0/0x48346).

∗ DATWR: DATA Entry Write Bit in the Cache Control Register (D0/0x48346)

As a result, the specified word in the specified cache entry will be updated to the set (or altered) data.

II.6.3.7 Write-back in Software

A specific entry in the cache can be written back to memory in software. When written back in software, the D bit

in a specified entry does not matter. Cache content is written back even when the D bit = 0. Therefore, when cache

content must be written back in software, always be sure to read out the TAG part to check D bit status and specify

an entry whose D bit = 1 before performing a write-back operation.

The following describes how to write back in software.

1. Use ENT[6:0] (D[10:4]/0x48348) and WAY[1:0] (D[1:0]/0x48342) to specify an entry and a way.

∗ ENT[6:0]: Entry Number in the Cache TAG Address Register 1 (D[10:4]/0x48348)

∗ WAY[1:0]: Way Number in the Cache Way Number Select Register (D[1:0]/0x48342)

2. Write a 1 to WB (D9/0x48346).

∗ WB: Write-Back Control Bit in the Cache Control Register (D9/0x48346)

The above causes the specified entry in the cache to be written back to memory.

When the cache is flushed, all entries are flushed regardless of the D bit status of any entry. Therefore, before

flushing the cache, always be sure to check the D bit status of all entries and write back only those entries whose D

bit = 1.

For write-back in software, WBSTAT (D15/0x48346) may be checked to confirm whether a write-back operation is

being performed.

∗ WBSTAT: Write-Back Status Bit in the Cache Control Register (D15/0x48346)

When WBSTAT (D15/0x48346) = 1, it means that a write-back operation is underway; when 0, it means that a

write-back operation has been completed. This bit is only effective for write-back in software. When other cache

entries must be written back in succession, always be sure to monitor the status of WBSTAT (D15/0x48346) and

wait until it is cleared to 0 before writing a 1 to the WB bit.

Note: Be sure to disable the cache before performing a write-back operation in software.

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II.6.4 Lock Function

The cache in the C33 ADV Core Block has a lock function. The lock function refers to protecting a specified way in

the cache where a specific program or data has been loaded (Way 1 or 3 selectable by register) against replacement

in case of a cache miss. This function may be used, for example, when a specific program must be left intact as

cached in the cache, without ever being replaced.

The following describes the procedure for controlling the lock function.

1. Use LKWAY (D12/0x48340) to specify a way of the cache to be locked.

∗ LKWAY: Lock Way Select Bit in the Cache Configuration Register (D12/0x48340)

Way 3 is selected when LKWAY (D12/0x48340) = 0; Way 1 is selected when LKWAY (D12/0x48340) = 1.

2. Specify the type of lock (instruction lock or data lock).

Set IRLK (D8/0x48340) to 1 for instruction lock; set DLK (D9/0x48340) to 1 for data lock.

∗ IRLK: Instruction-Lock Enable Bit in the Cache Configuration Register (D8/0x48340)

∗ DLK: Data-Lock Enable Bit in the Cache Configuration Register (D9/0x48340)

Regardless of whether cached with instruction lock or data lock, the program or data can be used in both

instruction and data caches. For example, after placing a program in the cache as data with data lock, it is

possible to use the cached data as instruction cache.

A dedicated lock function is provided for interrupt processing. For details, see Section II.6.5, “Lock for

Interrupt Processing.”

3. Write a 1 to LKSTART (D11/0x48346) to start the locking sequence.

∗ LKSTART: Lock-Start Control Bit in the Cache Control Register (D11/0x48346)

Then, if the target program or data does not make a hit before the locking sequence ends, a miss is assumed and

the specified way (Way 3 or 1) refilled. (When a hit is made, operation is executed without a refill.) While the

specified way is being accessed, the L (lock) bit in the TAG part of the accessed entry is set to 1. When access

to the same entry is attempted a number of times, the entry is overwritten, so that only the information accessed

last is effective. Moreover, if the D bit in the TAG part is 1 when refilling the way, the way is written back as

well.

4. When the entire program or all data to be locked has been taken into the cache, write a 0 to LKSTART (D11/

0x48346) to end the locking sequence.

After that, cache entries whose L bit = 1 are excluded from the object to be replaced due to a cache miss, and

are thus protected against replacement.

To unlock a locked cache entry, perform a lock flush (as described later).

In the locking sequence start and end states, the specified locked way is handled internally in the chip as described

below.

In the lock start state: Only the locked way is the object of replacement.

(In case of a cache miss, only the locked way is replaced.)

In the lock end state: The locked way is excluded from the object of replacement.

(In case of a cache miss, all ways but the locked way are replaced.)

When any cache entry whose lock bit = 1 is accessed again during lock start, resulting in a cache miss, the locked

way of the cache is replaced. In other words, the L bit has no effect during lock start.

Lock flush

For all cache lines whose TAG part L bit = 1, the L bit is cleared to 0 to unlock the lines. The V and D bits are

not altered. Nor is the LRU initialized.

To execute a lock flush, write a 1 to LKFLSH (D10/0x48346).

∗ LKFLSH: Lock-Flush Control Bit in the Cache Control Register (D10/0x48346)

Before performing a lock flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to disable

the cache.

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II.6.5 Lock for Interrupt Processing

To support control of cache operation for interrupt processing, a dedicated register called the Interrupt Lock Setup

by interrupt priority level. Each bit in LKIL[15:0] (D[15:0]) of the Interrupt Lock Setup Register (0x48350)

corresponds to one interrupt priority level. For example, LKIL15 corresponds to interrupt priority level 15 (IL[3:0]

= 15). To lock any interrupt priority level, set the corresponding bit in this register to 1.

However, before this can be achieved, the area where the interrupt routine is located must be enabled for cache use.

If the area is disabled against cache use, this function has no effect.

Although only Way 1 and both the instruction and data caches can be locked for interrupt processing, this interrupt

processing lock function is functionally the same as the lock function described in the preceding section.

This function does not need to control LKWAY (D12/0x48340), IRLK (D8/0x48340), DLK (D9/0x48340), and

LKSTART (D11/0x48346).

The interrupt processing lock function works according to the following rules:

• The function is in the interrupt lock start state when the value of the PSR register IL[3:0] bits and LKIL[15:0]

(D[15:0]) in the Interrupt Lock Setup Register (0x48350) match.

During interrupt lock start, only Way 1 is the object of replacement. If the target program or data does not make a

hit, Way 1 is refilled and the TAG part L bit set to 1. (When a hit is made, operation is executed without a refill.)

• If the IL[3:0] value and LKIL[15:0] (D[15:0]/0x48350) do not match, the function enters the interrupt lock end

state.

In this state, Way 1 in the locked entry is excluded from the object of replacement, and thus protected against

subsequent replacement.

When this function is used, the interrupt routine is limited to Way 1 and ordinary programs can only use the three

other ways of the cache.

Use of this function for the following purposes will yield a high rate of performance.

1. To prevent ordinary programs from becoming replaced due to a cache miss occurring in the interrupt

routine

Since the interrupt routine is limited to Way 1, which only is refilled in case of a cache miss, ordinary programs

in the cache can be protected against a refill that would otherwise be applied.

For example, when all interrupt routines in use are set to be locked, Ways 0, 2, and 3 of the cache can all be

occupied by ordinary programs that do not include any interrupt routine, thus maintaining high performance

with an improved hit rate.

2. To protect a frequently used interrupt routine by placing it in the cache

This method of use is the same as using Way 1 of the cache as an interrupt routine-only, 2KB sized, instruction/

data-coexisting direct mapped cache. When the interrupt handling routine thus protected is small in terms of

program size (e.g., 2KB or less) and has interrupts generated at a high frequency, high performance can be

maintained because the interrupt routine and ordinary programs coexist in the cache.

Moreover, this function can also be applied to main routines, and not just interrupt routines. In such case, the parts

of a main routine that must be locked or not locked can be set respectively by using IL[3:0]. By setting up the

Interrupt Lock Setup Register (0x48350), any desired program in the main routine can be locked the same way as

for the lock function described in the preceding section by simply altering the PSR register IL[3:0] bits.

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II.6.6 Consistency of the Cache Data

The CCU in the C33 ADV Core Block does not have a snoop function (to maintain consistency between data in

the cache and data in external memory). Therefore, if the data is shared with bus masters other than the CPU, data

consistency should be guaranteed in software.

Especially for data transfers performed using the internal DMA controller of the chip, note that the MMU and

cache are not supported for DMA. In data transfers by the DMA controller, the cache enable register settings in the

HBCU and CCU are ignored, and data is always transferred to and from physical memory. Therefore, it should be

guaranteed in software that DMA transfer will not be performed to or from cacheable physical memory. Otherwise,

if DMA transfer must be performed to or from a cached area, always be sure to “flush” the cache. Especially when

the cache operates in write-back mode, perform write-back and cache-flush processing after disabling the cache

before starting DMA transfer. When DMA transfer is completed, reenable the cache to guarantee data consistency.

Furthermore, consistency between the instructions in the cache and in external memory cannot be maintained when

the instruction cache only is enabled and the CPU rewrites an instruction area by a data access. Perform a cache

flush also in this case. Write 1 to CFLSH (D8/0x48346) to flush the cache.

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II.6.7 Details of Control Registers

Table II.6.7.1 List of CCU Registers

Address

0x00048340

0x00048342

0x00048344

0x00048346

0x00048348

0x0004834A

0x0004834C

0x0004834E

0x00048350

0x00048352

Function

Controls the entire cache

Specifies way numbers

TAG part control bit

Flushes the cache or reads/writes entries

Specifies 5 low-order bits of TAG part comparison address,

entry number, and word offset

16 high-order bits of TAG part comparison address

16 low-order bits of specified word in DATA part

16 high-order bits of specified word in DATA part

Specifies the interrupt lock level

3-bit LRU data

Cache Configuration Register (pCCU_SETUP)

Cache Way Number Select Register

(pCCU_ENTRY)

Cache Entry Control Register

(pCCU_ENTRY_CNTL)

Cache Control Register (pCCU_CNTL)

Cache TAG Address Register 1 (pCCU_ADR)

Cache TAG Address Register 2

Cache Data Register 1 (pCCU_DATA)

Cache Data Register 2

Interrupt Lock Setup Register (pCCU_LOCK)

Cache LRU Register (pCCU_LRU)

Size

The following describes each CCU control register.

The CCU control registers are mapped into the 16-bit device area from 0x48340 to 0x48352, and can be accessed

in units of half-words or bytes.

Note: When setting the CCU control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

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0x48340: Cache Configuration Register (pCCU_SETUP)

Name

Address

–

LKWAY

–

DLK

IRLK

–

WBEN

–

D15–13

D12

D11–10

D7–5

D3–2

reserved

Lock way select

reserved

Data-lock enable

Instruction-lock enable

reserved

Write-back enable

reserved

Data cache enable

Instruction cache enable

1Way 1 0Way 3

1Enabled 0Disabled

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

0048340

(HW)

–

1Enabled 0Disabled

–

Cache

configuration

(pCCU_SETUP)

1Write-back 0

Write through

D[15:13] Reserved

D12 LKWAY: Lock-Way Select Bit

Selects the way of the cache to lock. (Default: indeterminate)

1 (R/W): Way 1

0 (R/W): Way 3

D[11:10] Reserved

D9 DLK: Data-Lock Enable Bit

Enables the function for locking the cache against data access.

1 (R/W): Enable

0 (R/W): Disable (default)

D8 IRLK: Instruction-Lock Enable Bit

Enables the function for locking the cache against instruction fetch.

1 (R/W): Enable

0 (R/W): Disable (default)

D[7:5] Reserved

D4 WBEN: Write-Back Enable Bit

Enables write-back mode.

1 (R/W): Write-back mode

0 (R/W): Write-through mode (default)

In write-through mode, data is written to the cache and external memory at the same time. In write-back

mode, data is only written to the cache, but not written to external memory unless the written data must

be replaced for a subsequent cache miss.

For the cache to be used in write-back mode, WBEN should be set to 1 and the WRMDx bit provided

separately in the HBCU block should also be set to 1. When WBEN = 0, the operation mode is fixed to

write-through mode and WRMDx = 1 has no effect.

∗ WRMDx: Block x Write-Mode Select Bit in the Block x Configuration Register (D2/0x48302 + 2•x)

D[3:2] Reserved

D1 DC: Data Cache Enable Bit

Enables the data cache. To use a cached area as the data cache, set this bit to 1. The data cache can be

used concurrently as an instruction cache.

1 (R/W): Enable

0 (R/W): Disable (default)

D0 IC: Instruction Cache Enable Bit

Enables the instruction cache. To use a cached area as the instruction cache, set this bit to 1. The

instruction cache can be used concurrently as a data cache.

1 (R/W): Enable

0 (R/W): Disable (default)

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0x48342: Cache Way Number Select Register (pCCU_ENTRY)

Name

Address

–

0 to 3

→ Way 0 to Way 3

–

WAY1

WAY0

D15–2

reserved

Way number

–

R/W

0 when being read.

0048342

(HW)

Cache way

number select

(pCCU_ENTRY)

D[15:2] Reserved

D[1:0] WAY[1:0]: Way Number

Specifies the way number in which to read or set up the TAG or DATA part of the cache.

Table II.6.7.2 Specifying Way Numbers

WAY1

WAY0

Way

Way 3

Way 2

Way 1

Way 0

(Default: 0b00 = Way 0)

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0x48344: Cache Entry Control Register (pCCU_ENTRY_CNTL)

Name

Address

–

VLD

DTY

D15–3

reserved

Lock bit control/status

Valid bit control/status

Dirty bit control/status

1Locked 0Unlocked

1Valid 0Invalid

–

R/W

0 when being read.

0048344

(HW)

1Updated 0Unchanged

Cache entry

control register

(pCCU_ENTRY

_CNTL)

D[15:3] Reserved

D2 LK: Lock Bit Control/Status Bit

When reading out an entry in the cache, this bit indicates the status of the TAG part L (lock) bit. When

setting up an entry in the cache, the value of this bit is set in the L bit.

1 (R/W): Entry in locked state

0 (R/W): Entry ready for refill (default)

When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part L bit is

set to the value of LK.

When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of LK is

set in the TAG part L bit.

D1 VLD: Valid Bit Control/Status Bit

When reading out an entry in the cache, this bit indicates the status of the TAG part V (valid) bit. When

setting up an entry in the cache, the value of this bit is set in the V bit.

1 (R/W): Entry valid

0 (R/W): Entry invalid (default)

When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part V bit is

set to the value of VLD.

When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of VLD is

set in the TAG part V bit.

D0 DTY: Dirty Bit Control/Status Bit

When reading out an entry in the cache, this bit indicates the status of the TAG part D (dirty) bit. When

setting up an entry in the cache, the value of this bit is set in the D bit.

1 (R/W): Data in entry updated

0 (R/W): Data in entry not updated (default)

When TAGRD (D5/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the TAG part D bit is

set to the value of DTY.

When TAGWR (D4/0x48346) is set to 1 after an entry and way number are specified with Cache TAG

Address Register 1 (0x48348) and Cache Way Number Select Register (0x48342), the value of DTY is

set in the TAG part D bit.

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0x48346: Cache Control Register (pCCU_CNTL)

Name

Address

–

WBSTAT

–

LRURD

LRUWR

LKSTART

LKFLSH

CFLSH

–

TAGRD

TAGWR

–

DATRD

DATWR

D15

D14

D13

D12

D11

D10

D7–6

D3–2

Write-back status

reserved

LRU entry read

LRU entry write

Lock-start control

Lock-flush control

Write-back control

Cache-flush control

reserved

TAG entry read

TAG entry write

reserved

DATA entry read

DATA entry write

1Underway 0Completed

1Lock flush 0Invalid

1Lock start 0Lock end

1Read 0Invalid

–

R/W

–

0 when being read.

0048346

(HW)

–

Cache control

(pCCU_CNTL)

1Cache flush 0Invalid

1Write back 0Invalid

1Write 0Invalid

1Read 0Invalid

1Write 0Invalid

1Read 0Invalid

1Write 0Invalid

D15 WBSTAT: Write-Back Status Bit

Indicates whether software-controlled write-back operation is being executed. This bit is effective only

for software write-back control.

1 (R): Write-back underway

0 (R): Write-back completed (default)

1/0 (W): Has no effect

This bit is set to 1 when starting a write-back operation by writing a 1 to the WB bit (D9) in this

D14 Reserved

D13 LRURD: LRU Entry Read Bit

Reads LRU information from the specified cache entry.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When LRURD is set to 1, LRU information is read from the entry of the cache specified by the

Cache TAG Address Register 1 (0x48348). The information read is loaded in the Cache LRU Register

(0x48352).

D12 LRUWR: LRU Entry Write Bit

Writes LRU information to the specified cache entry.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When LRUWR is set to 1, the LRU information set in the Cache LRU Register (0x48352) is written to

the entry of the cache specified by the Cache TAG Address Register 1 (0x48348).

D11 LKSTART: Lock-Start Control Bit

Controls lock start and lock end.

1 (R/W): Lock start

0 (R/W): Lock end/ normal operation (default)

Writing a 1 to LKSTART starts the locking sequence. Then, if the target program or data does not

make a hit until the locking sequence ends, the way (Way 3 or 1) specified by LKWAY (D12/0x48340)

is refilled. (When a hit is made, operation is executed without a refill.) When the specified way is

accessed, the L (lock) bit in the TAG part of the accessed entry is set to 1.

Then, when LKSTART is set to 0, the entry for which the L bit is set for the specified way is protected

against replacement in case of a cache miss. All entries in other ways and entries for which the L bit is

not set for the specified way are replaced normally as required.

To unlock, use LKFLSH (D10) to clear the L bit.

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

S1C33401 TECHNICAL MANUAL EPSON II-6-17

CCU

D10 LKFLSH: Lock-Flush Control Bit

Performs a lock flush.

1 (W): Execute lock flush

0 (W): Has no effect

0 (R): Always 0 when read (default)

Writing a 1 to LKFLSH clears (initializes) the L (lock) bit of all entries.

Before executing a lock flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to

disable the cache.

D9 WB: Write-Back Control Bit

Writes back the cache to memory.

1 (W): Execute write-back

0 (W): Has no effect

0 (R): Always 0 when read (default)

When WB is set to 1, the cache entry specified by Cache TAG Address Register 1 (0x48348) and the

Cache Way Number Select Register (0x48342) is written back to memory.

When other entries of the cache must be written back in succession, always be sure to monitor the status

of WBSTAT (D15) and wait until it is cleared to 0 before writing a 1 to the WB bit.

D8 CFLSH: Cache-Flush Control Bit

Performs a cache flush.

1 (W): Flush the cache

0 (W): Has no effect

0 (R): Always 0 when read (default)

Writing a 1 to CFLSH clears (initializes) the V (valid) bit, D (dirty) bit, L (lock) bit, and LRU in all

cache entries. Data in the cache is retained.

Before executing a cache flush, always be sure to set DC (D1/0x48340) and IC (D0/0x48340) to 0 to

disable the cache.

Also note that since a cache flush causes entries whose D bit = 1 to be flushed along with other “clean”

entries, always be sure to check the D bit status in all entries and use WB (D9) to write back the entries

whose D bit = 1 to memory.

D[7:6] Reserved

D5 TAGRD: TAG Entry Read Bit

Reads information from the TAG part in a specified cache entry.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified

by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348).

The information read is loaded in the Cache Entry Control Register and Cache TAG Address Registers

1 and 2.

D4 TAGWR: TAG Entry Write Bit

Writes information to the TAG part in a specified cache entry.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When TAGWR is set to 1, the TAG information set in the Cache Entry Control Register and Cache

TAG Address Registers 1 and 2 is written to the TAG part in the way/entry of the cache specified by the

Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348).

D[3:2] Reserved

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II-6-18 EPSON S1C33401 TECHNICAL MANUAL

D1 DATRD: DATA Entry Read Bit

Reads information from the DATA part in a specified cache entry.

1 (W): Read

0 (W): Has no effect

0 (R): Always 0 when read (default)

When DATRD is set to 1, information is read from the DATA part in the way/entry/word offset of the

cache specified by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register

1 (0x48348). The information read is loaded in the Cache Data Registers 1 and 2.

D0 DATWR: DATA Entry Write Bit

Writes information to the DATA part in a specified cache entry.

1 (W): Write

0 (W): Has no effect

0 (R): Always 0 when read (default)

When DATWR is set to 1, the DATA information set in the Cache Data Registers 1 and 2 is written to

the DATA part in the way/entry/word offset of the cache specified by the Cache Way Number Select

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

S1C33401 TECHNICAL MANUAL EPSON II-6-19

CCU

0x48348: Cache TAG Address Register 1 (pCCU_ADR)

Name

Address

–

TA15

TA14

TA13

TA12

TA11

ENT6

ENT5

ENT4

ENT3

ENT2

ENT1

ENT0

WO1

WO0

–

D15

D14

D13

D12

D11

D10

D1–0

Comparison address in cache

TAG (5 low-order bits)

Entry number

(ENT[6:0] = PA[10:4])

Word offset

reserved

–

R/W

–0 when being read.

0048348

(HW)

Cache TAG

address

(pCCU_ADR)

0 to 127

→ Entry 0 to Entry 127

0 to 3

→ W0 to W3

D[15:11] TA[15:11]: Comparison Address in Cache TAG (CPA[15:11])

Used along with Cache TAG Address Register 2 (0x4834A) to read or set the TAG part comparison

address. (Default: 0x00)

TA[15:11] corresponds to the 5 low-order bits of CPA[31:11] (CPA[15:11]).

When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified

by the Cache Way Number Select Register (0x48342) and this register, with the comparison address in

it loaded into this bit field.

When a comparison address is set in this bit field and TAGWR is set to 1, the address is written to the

TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342)

and this register.

D[10:4] ENT[6:0]: Entry Number

Specifies the entry in which to read or set up the TAG or DATA part of the cache. (Default: 0x00)

The data 0–127 set here specifies the entry number represented by PA[10:4].

D[3:2] WO[1:0]: Word Offset

Specifies a word offset in the DATA part to be read or set up.

Table II.6.7.3 Specifying Word Offsets

WO1

WO0

Word offset

(Default: 0b00 = W0)

D[1:0] Reserved

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

II-6-20 EPSON S1C33401 TECHNICAL MANUAL

0x4834A: Cache TAG Address Register 2

Name

Address

TA31

TA30

TA29

TA28

TA27

TA26

TA25

TA24

TA23

TA22

TA21

TA20

TA19

TA18

TA17

TA16

D15

D14

D13

D12

D11

D10

Comparison address in cache

TAG (16 high-order bits)

R/W

004834A

(HW)

Cache TAG

address

D[15:0] TA[31:16]: Comparison Address in Cache TAG (CPA[31:16])

Used along with Cache TAG Address Register 1 (0x48348) to read or set the TAG part comparison

address. (Default: 0x0000)

Cache TAG Address Register 2 corresponds to the 16 high-order bits of CPA[31:11] (CPA[31:16]).

When TAGRD is set to 1, information is read from the TAG part in the way/entry of the cache specified

by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348),

with the comparison address in it loaded into this bit field.

When a comparison address is set in this bit field and TAGWR is set to 1, the address is written to the

TAG part in the way/entry of the cache specified by the Cache Way Number Select Register (0x48342)

and Cache TAG Address Register 1 (0x48348).

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S1C33401 TECHNICAL MANUAL EPSON II-6-21

CCU

0x4834C: Cache Data Register 1 (pCCU_DATA)

0x4834E: Cache Data Register 2

Name

Address

CD15

CD14

CD13

CD12

CD11

CD10

CD9

CD8

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

D15

D14

D13

D12

D11

D10

Cache data (16 low-order bits) 0

R/W

004834C

(HW)

Cache data

(pCCU_DATA)

CD31

CD30

CD29

CD28

CD27

CD26

CD25

CD24

CD23

CD22

CD21

CD20

CD19

CD18

CD17

CD16

D15

D14

D13

D12

D11

D10

Cache data (16 high-order bits) 0

R/W

004834E

(HW)

Cache data

D[15:0]/0x4834C CD[15:0]: Cache Data (16 low-order bits)

D[15:0]/0x4834E CD[31:16]: Cache Data (16 high-order bits)

Used to read or set word data in the DATA part. (Default: 0x00000000)

Cache Data Registers 1 and 2 correspond to the 16 low-order bits and 16 high-order bits of word data,

respectively.

When DATRD is set to 1, the word data set in the way/entry/word offset specified by the Cache Way

Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348) is read out to these

registers.

When DATWR is set to 1, the data set in these registers is written to the way/entry/word offset specified

by the Cache Way Number Select Register (0x48342) and Cache TAG Address Register 1 (0x48348).

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

II-6-22 EPSON S1C33401 TECHNICAL MANUAL

0x48350: Interrupt Lock Setup Register (pCCU_LOCK)

Name

Address

LKIL15

LKIL14

LKIL13

LKIL12

LKIL11

LKIL10

LKIL9

LKIL8

LKIL7

LKIL6

LKIL5

LKIL4

LKIL3

LKIL2

LKIL1

LKIL0

D15

D14

D13

D12

D11

D10

Interrupt handler lock level

(compared with IL[3:0] in PSR)

R/W

0048350

(HW)

Interrupt lock

setup register

(pCCU_LOCK)

D[15:0] LKIL[15:0]

Set the bit corresponding to the interrupt level for the interrupt handler routine to be locked to 1. (Default:

0x0000)

Each bit in LKIL[15:0] corresponds to one interrupt priority level determined by the value of the PSR

being processed by the interrupt routine, the cache is only refilled in Way 1 and subsequently locked.

In hardware, the locking sequence starts when the PSR register IL[3:0] and LKIL[15:0] match, and

ends when interrupt levels do not match. The locked entry is excluded from the object of replacement

and protected in the cache.

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S1C33401 TECHNICAL MANUAL EPSON II-6-23

CCU

0x48352: Cache LRU Register (pCCU_LRU)

Name

Address

–

LRU2

LRU1

LRU0

D15–3

reserved

LRU information

–

R/W

0 when being read.

0048352

(HW)

Cache LRU

(pCCU_LRU)

–

D[15:3] Reserved

D[2:0] LRU[2:0]: LRU Information

These bits are used to save the LRU information to be written to or read from the specified entry. (Default:

0x0000)

To set LRU information, write the information to this register, then set LRUWR (D12/0x48346) to 1. To

confirm the LRU information set in an entry, set LRURD (D13/0x48346) to 1, then read the data loaded

in this register. The entry set in the Cache TAG Address Register 1 (0x48348) is the target from or to

which the LRU information is read or written.

II C33 ADV CORE BLOCK: CACHE CONTROL UNIT (CCU)

II-6-24 EPSON S1C33401 TECHNICAL MANUAL

II.6.8 Precautions

• To use the cache in block ‘x’ (x = 0–7), set the corresponding DCx bit (D1) or ICx bit (D0) in the HBCU Block x

Configuration Register (0x48302 + 2•x) to 1.

Moreover, set the DC bit (D1) or IC bit (D0) in the CCU Cache Configuration Register (0x48340) to 1.

When the cache is enabled in both the HBCU and CCU, the cache is made usable.

For example, to enable the instruction and data caches for block 0 and to use them in write-back mode,

1. Set the Block 0 Configuration Register (0x48302) to 0x0007,

2. Perform a cache flush by writing 0x0100 to the Cache Control Register (0x48346),

3. Set the Cache Configuration Register (0x48340) to 0x0013.

These settings activate the instruction and data caches in write-back mode.

Usage like this, enabling both the instruction and data caches and set them in write-back mode, is the most

effective to increase the cache performance.

• To use the MMU in combination with the cache, the TLB in the MMU must also be set up, in addition to the

settings above.

When setting up the TLB for a page involving cache use, set the CE bit (cache enable) in the TAG part to 1.

• When the lock function is used and lock control by LKSTART (D11/0x48346) and lock by interrupt level

overlap, Way 1 (supported for interrupt lock) takes preference over other locked ways. In this case, the

specification by LKWAY (D12/0x48340) = 1 (Way 3) has no effect.

• When the cache must be written back successively in software, always be sure to monitor the status of WBSTAT

(D15/0x48346) and wait until it is cleared to 0 before writing a 1 to the WB bit (D9/0x48346).

• Cache write mode (write-back or write-through mode) should be set by using both WRMDx (D2/0x48302 + 2•x,

x = block numbers 0 to 7) provided for each block in the HBCU and WBEN (D4/0x48340) provided in the CCU.

To use the cache in write-back mode, set both to 1 (= write-back mode). When WBEN in the CCU = 0, the cache

is fixed to write-through mode. This means that before WRMDx in the HBCU can be used to select write-back or

write-through mode for each block individually, WBEN must be set to 1 (= write-back mode).

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DBG

III

II.7 Debug Unit (DBG)

II.7.1 Overview of the DBG

The C33 ADV Core Block incorporates a Debug Unit (DBG) that supports the program debug function for on-chip

trace, break, and other operations.

The Debug Unit has debug pins that can be used to connect an ICD, thus facilitating an advanced software

development environment using a debugger on a PC.

Note: The DBG is not normally activated during device operation. To achieve a DBG-based software

development environment, the S5U1C33001H (In-Circuit Debugger for S1C33 Family) Ver. 4 or

later and S5U1C33001C (S1C33 Family C Compiler Package, GNU Version) Ver. 2.0 or later are

required separately in addition to an S1C33 target board.

II.7.2 Input/Output Pins of the DBG

The DBG has 20 ports for input/output signals to and from the debugger, and most of these input/output pins are

shared with general-purpose input/output ports.

Table II.7.2.1 List of Debug Signal Input/Output Pins

Pin name

DSIO

DCLK

DST2

DST[1:0]

DPCO

DBT

DTS[4:0]

DTD[7:0]

I/O

Essential/ Optional

Essential

Option for PC trace

Option for bus trace

Function

Serial input/output for debugging (with pull-up)

Clock output for debugging

Debug status output

PC output for debugging

Break trigger output for bus trace

Bus trace data status output

Bus trace data output

For details about general-purpose input/output ports that share the debugging signal pins, see the pin description in

Chapter I (specifications by model).

Notes: • During debugging, these pins should never be connected to other than the ICD.

• When a falling edge is detected on the DSIO pin, the CPU enters debug mode. To prevent the

CPU from becoming inadvertently placed in debug mode by false low pulse input when the

chip is reset or operating normally, the DSIO pin should be protected against noise.

II C33 ADV CORE BLOCK: DEBUG UNIT (DBG)

II-7-2 EPSON S1C33401 TECHNICAL MANUAL

II.7.3 Overview of Functions

The DBG operates in conjunction with development tools to support the functions described below. For details

about the debugging method, refer to the user’s manuals for the S5U1C33001H (In-Circuit Debugger for S1C33

Family) and the S5U1C33001C (S1C33 Family C Compiler Package, GNU Version).

1. Forcible break

A forcible beak allows the CPU to be placed in debug mode when the device is reset or executing a program.

2. Single step

The program is executed one instruction at a time. However, an undividable set of instructions (e.g., ext or

delayed branch instructions) are executed collectively.

3. Register read/write

4. Memory read/write

5. Flash memory erase/program

6. Software PC break

Implemented by embedded break instructions. This break is applied to the instructions in RAM.

7. Hardware PC break

An access address on the CPU instruction bus causes a break in the program. For prefetch, there is no break in

the program until immediately before execution.

Three hardware PC break channels are included. One is used for single-stepping C sources and temporary break

of the go command by the ICD; the other two channels are only usable by the user. When a range of addresses

is specified for PC trace, both channels are used for triggering the trace.

8. Data address break

An access address on the CPU data bus causes a break in the program. One such break is usable. A break

actually occurs after data is accessed.

9. PC trace

The output data on the DST and DPCO pins are saved on the ICD, with the PC trace information displayed in

soft analysis by the debugger.

The following describes the newly incorporated functions, beginning with the C33 ADV Core CPU.

10. Area break

Break and no-break can be set for each area in the physical memory space (areas 1 to 22) separately managed

by the BBCU. The bus master and R/W conditions can be selected using the internal functions of the chip.

11. Bus break

Access attempted via the CPU instruction or data bus, or BBCU bus causes a break in the program. An address,

data/instruction bit pattern (with bits maskable), R/W condition, and pass counter up to 2G counts can be set as

break conditions. For the BBCU, a bus master can also be specified.

12. Bus trace

The information listed below that is output using the bus trace pins is saved on the ICD, then displayed after

being analyzed by the debugger.

• Bus information about CPU instruction and data buses, and the BBCU bus

• Address

• Data/instruction pattern

• R/W

• Access size

• Bus master (for the BBCU)

13. Supervisor mode, MMU

Operation mode can be switched between supervisor mode and user mode.

The MMU state can be switched between active and inactive.

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DBG

III

II.7.4 Details of Control Registers

Table II.7.4.1 List of DBG Registers

Address

0x000402E8

0x000402EC

Function

Removes write protection for the Debug Signal Output

Control Register.

Controls trace signal outputs.

Debug Signal Output Control Write-Protect Register

Debug Signal Output Control Register

Size

The following describes each DBG control register.

The DBG control registers are mapped in the 8-bit device area from 0x402E0 to 0x402F4, and can be accessed in

units of bytes.

Notes: • This section describes only the registers (0x402E8, 0x402EC) that are used to switch

the debug pins to I/O port pins. Make sure that other registers are not accessed from the

application program.

• When setting the DBG control registers, be sure to write a 0, and not a 1, for all “reserved

bits.”

II C33 ADV CORE BLOCK: DEBUG UNIT (DBG)

II-7-4 EPSON S1C33401 TECHNICAL MANUAL

0x402E8: Debug Signal Output Control Write-Protect Register

Name

Address

Writing 01011001 (0x59)

removes the write protection of

the

Debug signal output control

(0x402EC).

Writing another value set the

write protection.

DBGOUTP7

DBGOUTP6

DBGOUTP5

DBGOUTP4

DBGOUTP3

DBGOUTP2

DBGOUTP1

DBGOUTP0

Debug signal output control

W0 when being read.

00402E8

(B)

Debug signal

output control

write-protect

D[7:0] DBGOUTP[7:0]: Debug Signal Output Control Write-Protect Flag

Removes write protection of the Debug Signal Output Control Register (0x402EC).

0x59 (W): Remove write protection

Other than 0x59 (W): Write-protect the register

0x00 (R): Always 0 when read

Before altering the Debug Signal Output Control Register (0x402EC), write 0x59 to this register for

removing write protection. If the register remains write-protected, its content is not altered even though

a write instruction may have been executed without causing any problem. When rewriting the Debug

Signal Output Control Register (0x402EC) has finished, this register should be set to other than 0x59 to

prevent accidental writing.

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DBG

III

0x402EC: Debug Signal Output Control Register

Name

Address

–

DBTOE

DPCTOE

D7–2

reserved

Bus trace signal output enable

PC trace signal output enable

–

R/W

0 when being read.

00402EC

(B)

Debug signal

output control

–

1Enabled 0Disabled

Note: This register is write protected. Before this register can be rewritten, write protection must be

removed by writing data 0x59 to the Debug Signal Output Control Write-Protect Register (0x402E8).

The Debug Signal Output Control Write-Protect Register (0x402E8) should be set to other than

0x59 unless this register must be rewritten.

D[7:2] reserved

D1 DBTOE: Bus Trace Signal Output Enable Bit

Enables bus trace signal output.

1 (R/W): Enable

0 (R/W): Disable (default)

Setting this bit to 1 enables DBT, DTD[7:0], and DTS[4:0] signal output. This is necessary when using

ICD3 (S5U1C33001H) to perform a bus trace.

When using the P82 to P97 pins as general-purpose I/O ports or peripheral I/O ports, do not alter this

bit to 0.

D0 DPCTOE: PC Trace Signal Output Enable Bit

Enables PC trace signal output.

1 (R/W): Enable (default)

0 (R/W): Disable

Setting this bit to 1 enables DPCO and DST[2:0] signal output. This is necessary when using ICD2/3

(S5U1C33000H/S5U1C33001H) to perform a debug operation.

When using the P65 to P67 pins as general-purpose I/O ports, set this bit to 0.

II C33 ADV CORE BLOCK: DEBUG UNIT (DBG)

II-7-6 EPSON S1C33401 TECHNICAL MANUAL

II.7.5 Precautions

• The DBG control registers are mapped to addresses 0x402E0 through 0x402F4 in area 1. Make sure that the

application program does not access registers other than 0x402E8 and 0x402EC.

• Addresses 0x60000 through 0x7FFFF in area 2 are reserved for the debug functions. This area is write-protected

when no break occurs, and enabled for write operation when a break occurs. Be careful not to write to area 2

from the debugger during a beak.

III

S1C33401 Technical Manual

III C33 ADV BUS BLOCK

III C33 ADV BUS BLOCK: PREFACE

S1C33401 TECHNICAL MANUAL EPSON III-1-1

III

Preface

III.1 Preface

The C33 ADV Bus Block consists of three bus modules connected to the high-speed bus controlled by the HBCU

of the C33 ADV Core Block.

C33 ADV CPU

HBCU

EBCU

(SDRAM Controller)

DMAC

BBCU

(SRAM Controller)

CCU

MMU

A3RAM

A0RAM

Extended internal

modules

External I/O devices

External memories

Bus Control Block

High-speed bus

Figure III.1.1 C33 ADV Bus Block

BBCU: Basic Bus Control Unit

Controls access to internal/external devices mapped to any of 19 divided areas in the physical memory space.

SRAM, ROM, burst ROM, or flash memory may be directly connected to the BBCU.

EBCU: Extended Bus Control Unit

Used to extend the BBCU functions, this module incorporates an SDRAM controller.

DMAC: DMA Controller

Controls DMA transfers. The DMAC in the C33 ADV consists of high-speed DMA (HSDMA) and intelligent

DMA (IDMA) units as in the C33 STD, but these units have more useful functions than in the predecessor.

III C33 ADV BUS BLOCK: PREFACE

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THIS PAGE IS BLANK.

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

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III

BBCU

III.2 Basic Bus Control Unit (BBCU)

III.2.1 Overview of the BBCU

The Basic Bus Control Unit (BBCU) is one of three bus modules connected to the high-speed bus controlled by the

HBCU. The BBCU manages the external memory space by dividing it into 19 areas. This module controls external

bus signals according to bus conditions set for each area as it accesses the connected memory or I/O device.

The BBCU functions and features are outlined below.

• Supports a 32-bit address bus and data bus.

• Controls external memory space as 19 divided areas (Areas 4 to 22).

• Allows various conditions (e.g., external/internal access, endian mode, interface mode, device type, device size,

number of access cycles) to be set for each area.

• Outputs 8 chip-enable signals (#CE4 to #CE11) corresponding to each external area.

• Supports two interface modes: A0 and BSL (with BSL mode for external memory only).

• Allows SRAM, ROM, burst ROM, or flash memory to be connected directly to the external bus.

• Allows wait states to be inserted from the external #WAIT pin (for SRAM type only).

• Arbitrates bus contention with external bus masters.

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III-2-2 EPSON S1C33401 TECHNICAL MANUAL

III.2.2 BBCU Pins

Table III.2.2.1 lists the pins used by the BBCU.

Table III.2.2.1 BBCU Pin List

Pin name

A[31:0]

D[31:0]

#CE11

#CE10

#CE9

#CE8

#CE7

#CE6

#CE5

#CE4

#RD

#BSLL (#BSL*)

#WRLL (#WRL*)/

#WR

#WRLH (#WRH*)/

#BSLH (#BSH*)

#WRHL/

#BSHL

#WRHH/

#BSHH

#BUSREQ

#BUSACK

#BUSGET

BCLK

#WAIT

ACST

ASTB

EA10MD

B32MD

I/O

Function

Address signal output pins (external address bus)

Data signal input/output pins (external data bus)

Area 11/12 chip enable signal output pin

Area 10/13/20 chip enable signal output pin

Area 9/22 chip enable signal output pin

Area 8/21 chip enable signal output pin

Area 7/19 chip enable signal output pin

Area 6/17/18 chip enable signal output pin

Area 5/15/16 chip enable signal output pin

Area 4/14 chip enable signal output pin

Read signal output pin

Least significant byte bus strobe signal output pin (when accessing BSL interfaced area)

Least significant byte write signal output pin (when accessing A0 interfaced area) /

Write signal output pin (when accessing BSL interfaced area)

2nd byte write signal output pin (when accessing A0 interfaced area) /

2nd byte bus strobe signal output pin (when accessing BSL interfaced area)

3rd byte write signal output pin (when accessing A0 interfaced area) /

3rd byte bus strobe signal output pin (when accessing BSL interfaced area)

Most significant byte write signal output pin (when accessing A0 interfaced area) /

Most significant byte bus strobe signal output pin (when accessing BSL interfaced area)

Bus request signal input pin

Bus request-acknowledge signal output pin

Bus status monitor signal output pin

BBCU clock output pin

External wait request input pin

Bus access status signal output pin

Address strobe signal output pin

Area 20 boot mode select pin (1: external ROM boot mode, 0: internal ROM boot mode)

X32 boot select pin (1: X32 boot, 0: normal boot)

* Signal names when only 16 data bus pins are available

Notes: • The above lists the input/output pins that can be accommodated by the BBCU. Depending on

the C33 ADV model used, the BBCU may have a different pin configuration.

- Address bus A[31:0] may consist of less than 32 pins.

- Data bus D[31:0] may only have 16 pins, D[15:0].

- All control signal pins may not be available for some C33 ADV models.

- Pin names may differ for some C33 ADV models.

For details of the pin configuration in each C33 ADV model, see Section I.3, “Pin Description.”

• Some control pins above are shared with general-purpose input/output ports or other

peripheral circuit input/output pins, so that functionality in the initial state may be set to other

than the BBCU. Before the BBCU signals assigned to these pins can be used, the functions of

these pins must be switched for the BBCU by setting each corresponding Port Function Select

For details on how to switch over the pin functions, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

• The bus control signals can be pulled high or forcibly driven low in software. For details on

how to control, see Section V.4, “Pin Control Registers.”

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

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BBCU

III.2.3 General Memory Map

The C33 ADV supports 4GB of physical address space, which is divided into 23 areas as shown in Figure III.2.3.1.

Area 13 0x02FF FFFF

0x0200 0000

External Memory

16M bytes

Area 12 0x01FF FFFF

0x0180 0000

External Memory

8M bytes

Area 11 0x017F FFFF

0x0100 0000

External Memory

8M bytes

Area 10 0x00FF FFFF

0x00C0 0000

External Memory

4M bytes

Area 9 0x00BF FFFF

0x0080 0000

External Memory

4M bytes

Area 8 0x007F FFFF

0x0060 0000

External Memory

2M bytes

Area 7 0x005F FFFF

0x0040 0000

External Memory

2M bytes

Area 6 0x003F FFFF

0x0030 0000

External Memory

1M bytes

Area 5 0x002F FFFF

0x0020 0000

External Memory

1M bytes

Area 4 0x001F FFFF

0x0010 0000

External Memory

1M bytes

Area 3 0x000F FFFF

0x0008 0000

Internal RAM

512K bytes

Area 2 0x0007 FFFF

0x0006 0000

For debugging

128K bytes

Area 1 0x0005 FFFF

0x0002 0000

Internal I/O

256K bytes

Area 0 0x0001 FFFF

0x0000 0000

Internal RAM

128K bytes

Area 22 0xFFFF FFFF

0x8000 0000

External Memory

2G bytes

Area 21 0x7FFF FFFF

0x4000 0000

External Memory

1G bytes

Area 20 0x3FFF FFFF

0x2000 0000

External Memory

512M bytes

Area 19 0x1FFF FFFF

0x1000 0000

External Memory

256M bytes

Area 18 0x0FFF FFFF

0x0C00 0000

External Memory

64M bytes

Area 17 0x0BFF FFFF

0x0800 0000

External Memory

64M bytes

Area 16 0x07FF FFFF

0x0600 0000

External Memory

32M bytes

Area 15 0x05FF FFFF

0x0400 0000

External Memory

32M bytes

Area 14 0x03FF FFFF

0x0300 0000

External Memory

16M bytes

Figure III.2.3.1 Physical Address Space of the C33 ADV

Areas 0 to 3 are internal areas of the chip.

Areas 4 to 22 are external memory areas (or modules built into the chip) accessed by #CEx signals output by the

BBCU.

When the Memory Management Unit (MMU) is used, the HBCU uses the MMU to convert logical addresses

output by the CPU into the physical addresses above before it sends the address to the BBCU. With initial settings,

the CPU must use the addresses above to access Areas 0 to 6 because the MMU cannot be used for these areas. (The

HBCU can be set up to make the entire area address-convertible by the MMU in user mode.) When the MMU is not

used, addresses output by the CPU are forwarded directly to the BBCU. For details of the HBCU and MMU, see

Section II.4, “High-Speed Bus Control Unit (HBCU),” and Section II.5, “Memory Management Unit (MMU).”

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

III-2-4 EPSON S1C33401 TECHNICAL MANUAL

III.2.4 Internal RAM Area (Areas 0 and 3)

Areas 0 and 3 are allocated to the internal RAM.

Area 3 0x000F FFFF

0x0008 0000

Internal RAM area

(1 wait in random

access)

512K bytes

I/F

Area 0 0x0001 FFFF

0x0000 0000

Internal high-speed

RAM area

(no-wait access)

128K bytes

HBCU

(No wait, 32-bit bus)

(1 wait,

32-bit bus) High-

speed

bus

Figure III.2.4.1 Areas 0 and 3

Area 0 is a 128KB space where high-speed RAM is located. This area is directly accessed from the HBCU in one

cycle (with no wait states), and transparent to the BBCU. Consequently, there are no access condition setup items

for this area.

Note: IDMA control words cannot be placed in Area 0.

Furthermore, Area 0 may not be specified as the source or destination of DMA transfer.

Area 3 is a 512KB space accessed directly from a dedicated interface on the high-speed bus, transparent to the

BBCU. There are no access condition setup items for this area.

Area 3 is accessed in two cycles (with one wait state, for random access) or one cycle (with no wait states, for

continuous access).

IDMA control words can be placed in Area 3, which may also be specified as the source or destination of DMA

transfer.

For details of the size and address of RAM actually built into the chip, see Section I.5, “Memory Map.”

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BBCU

III.2.5 Internal I/O and Debug Areas (Areas 1 and 2)

III.2.5.1 Internal I/O Area (Area 1)

Area 1 contains the basic internal peripheral circuits of the C33 ADV. Addresses 0x40000 to 0x4FFFF are used for

control registers; addresses 0x30000 to 0x3FFFF are the mirror of that area.

The internal I/O area is divided into an 8-bit device area comprised of 4KB from addresses 0x40000 to 0x40FFF

and a 16-bit device area comprised of 4KB from addresses 0x48000 to 0x48FFF. Furthermore, addresses 0x41000

to 0x41FFF are configured as the mirror of the 16-bit device area. By using this mirror with the base address set to

0x40000, the entire internal I/O area that contains both the 8-bit and 16-bit device areas can be accessed with two

instructions (one basic instruction with one ext instruction).

Area 1 0x0005 FFFF

0x0005 0000

0x0004 FFFF

0x0004 9000

0x0004 8FFF

0x0004 8000

0x0004 7FFF

0x0004 2000

0x0004 1FFF

0x0004 1000

0x0004 0FFF

0x0004 0000

0x0003 FFFF

0x0003 0000

0x0002 FFFF

0x0002 0000

Unused

Mirror area

Unused

8-bit device area

16-bit device area

(mirror)

Unused

Figure III.2.5.1.1 Configuration of Area 1

For details of the basic internal peripheral circuits mapped to this area, see Chapter IV, “C33 ADV Basic Peripheral

Block.” For a list of control registers, see the Appendix, “I/O Map.”

III.2.5.2 Debug Area (Area 2)

Area 2 is a debug-only area allocated for debugging resources. This area cannot be accessed for write operation

except in debug mode.

Accessing this area from user programs or debuggers is prohibited.

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

III-2-6 EPSON S1C33401 TECHNICAL MANUAL

III.2.6 External Memory Area (Areas 4 to 22)

Areas 4 to 22 comprise an external memory area accessible from the BBCU, to which external memory devices

may be connected. The device type and size, access timing conditions, and other information may be set for each

of these areas to be accessed. Aside from external devices, the user logic to be incorporated in the chip and other

extension circuits may be located in these areas.

III.2.6.1 External Memory Area and Chip Enable

The BBCU supports up to 32 bits of external address bus and 32 bits of an external data bus, allowing access to

the 4GB address space. The number of pins that are available on the chip is not always the same, with less than

32 address pins or only 16 data pins available for some C33 ADV models. See Section I.3, “Pin Description,” for

confirmation.

Areas to which internal devices are mapped can basically use a 32-bit address bus and data bus.

Eight chip-enable pins (#CE4 to #CE11) are provided for external access. Two or more areas are assigned to each

chip-enable signal. Table III.2.6.1.1 shows the relationship between the chip-enable pins and corresponding areas.

Table III.2.6.1.1 Relationship between Chip-Enable Pins and Corresponding Areas

#CE pin

#CE4

#CE5

#CE6

#CE7

#CE8

#CE9

#CE10

#CE11

Corresponding

area

Areas 4, 14

Areas 5, 15, 16

Areas 6, 17, 18

Areas 7, 19

Areas 8, 21

Areas 9, 22

Areas 10, 13, 20

Areas 11, 12

Area

Area 4

Area 5

Area 6

Area 7

Area 8

Area 9

Area 10

Area 11+12

Size

1MB

2MB

4MB

16MB

Area

Area 14

Area 15+16

Area 17+18

Area 19

Area 21

Area 22

Area 13

–

Size

16MB

64MB

128MB

256MB

1GB

2GB

16MB

–

Area

–

Area 20

–

Size

–

512MB

–

Usable size of area in continuous address range

The #CEx signal also becomes active when an address in any corresponding area is accessed.

III.2.6.2 Area 20 and Boot Mode

Area 20 (CE10 area) is an external memory area that includes a cold reset boot address (0x20000000). This area

supports two boot modes: Internal ROM boot and External ROM boot. The boot mode is selected depending on the

EA10MD pin status when the chip is reset, as shown below.

Table III.2.6.2.1 Area 20 Boot Mode Selection

EA10MD

Area 20 boot mode

External ROM boot mode

Internal ROM boot mode

The CPU boots from internal ROM mapped to Area 20. This ROM starts from address 0x20000000 and can be

read in one cycle.

External ROM boot mode

The CPU boots from external memory (e.g., ROM, flash, SRAM). External memory is accessed according to

the content of the CE10 area setup register.

Programs for internal ROM can be developed in external ROM boot mode. Note that X32 boot can also be activated

by setting external pin B32MD_R to 1 when reset.

Note: The EA10MD and B32MD pins are only available for C33 ADV models with built-in ROM.

Moreover, these pins may have different names for some C33 ADV models.

III.2.6.3 Extended I/O Area

All C33 ADV models in the S1C33 Family basically contain the basic peripheral circuits mapped to Area 1. Other

peripheral circuits may be mapped to one external memory area for extending functions. Normally, Area 6 is used

for this extended I/O area. For details of the extended peripheral circuits, see Chapter V.

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BBCU

III.2.6.4 Summary of Programmable External Memory Access Conditions

The following lists the parameters for external memory access that can be set/selected in the BBCU. See Sections

III.2.6.5 and III.2.6.6 for detailed information.

Common condition settings

The parameters listed below can be set up with software.

• ASTB pulse width (1 or 2 clocks) Figure III.2.6.4.1 <1>

• WAIT input control (enable or disable) Figure III.2.6.4.1 <2>

• Burst ROM page read cycle (1 to 16 clocks) Figure III.2.6.4.4 <3>

(Selectable only for the areas that support burst ROM)

Per-area condition settings

The parameters listed below can be set up in each area independently.

• Access to external device or internal device

• Endian mode (little endian or big endian)

• Interface mode (A0 mode or BSL mode)

• Device type (SRAM (BBCU) or SDRAM (EBCU))

• Burst ROM selection (CE10, CE8, CE5 areas only)

• Device size (8, 16, or 32 bit)

• Bus clock synchronization (synchronous or asynchronous) Figure III.2.6.4.1 <4>

(Bus access starts at the rising edge of BCLK in synchronous mode.)

• Access cycle multiplication CExMLT (1, 2, or 4) Figure III.2.6.4.1 <5>

(This parameter defines the basic cycle time. Almost all programmable parameters are set up as CExMLT ×

CCLK cycles.)

• CE cycle (1 to 16) Figures III.2.6.4.2 and III.2.6.4.3 <6>

• RD start state (1 to 4) Figure III.2.6.4.2 <7>

• RD start state option (-0.5 or 0 clocks) Figure III.2.6.4.2 <8>

• RD end state (0 to 3) Figure III.2.6.4.2 <9>

• WR start state (1 to 4) Figure III.2.6.4.3 <10>

• WR start state option (-0.5 or 0 clocks) Figure III.2.6.4.3 <11>

• WR end state (0 to 3) Figure III.2.6.4.3 <12>

• WR end state option (-0.5 or 0 clocks) Figure III.2.6.4.3 <13>

• Access disable cycle (0 to 3) Figures III.2.6.4.2 and III.2.6.4.3 <14>

• Output disable cycle (0 to 3) Figure III.2.6.4.2 <15>

CCLK

<5> CCLK × CExMLT

<4> BCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

<1> ASTB

<2> #WAIT

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Wait

cycle

∗1

∗1:In BCLK synchronous mode, the #CEx and A[31:0] signals are output preceding the rising edge of BCLK.

Other signal outputs and the bus access start at the rising edge of BCLK.

(Access cycle multiply-by factor (CExMLT): x2, BCLK: CCLK•1/4, Bus synchronization: enabled)

Figure III.2.6.4.1 SRAM Read Cycle Timing Parameters (a)

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III-2-8 EPSON S1C33401 TECHNICAL MANUAL

CCLK

A[31:0]

#CEx

#RD

D[31:0]

valid

RD start state <7>

∗1

<8> ∗1

∗1

∗1: When RD start state option (-0.5 clock) is enabled

CE cycle <6>

Access

disable

cycle

<14>

Output

disable

cycle

<15>

RD end state <9>

valid

Figure III.2.6.4.2 SRAM Read Cycle Timing Parameters (b)

∗1∗2

<11>

∗1

<13>

∗2

∗1

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

valid

WR start state <10>

CE cycle <6>

Access

disable

cycle

<14>

WR end state <12>

∗1: When WR start state option (-0.5 clock) is enabled

∗2: When WR end state option (-0.5 clock) is enabled

valid

Figure III.2.6.4.3 SRAM Write Cycle Timing Parameters

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

valid

00 01 10

valid (2)

valid (3)

valid (4)

RD start state

Access

disable

cycle

CE cycle

Inserted page read cycles

Page read

access

<3>

Page read

access

<3>

Page read

access

<3>

Output

disable

cycle

RD end state

∗1

∗1: When RD start state option (-0.5 clock) is enabled

valid (1)

Figure III.2.6.4.4 Burst ROM Read Cycle Timing Parameters

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BBCU

III.2.6.5 Common Condition Settings

The BBCU control registers are used to set external bus access conditions. This section describes the parameters

that are commonly set in all areas and the relevant control bits.

The BBCU control registers are initialized by an initial reset. These registers should be set up back again in

software to suit the external device configuration or specification as required.

For details of bus cycle operations, see Section III.2.9, “Bus Access Timing Chart.”

Table III.2.6.5.1 Common Parameter Settings

Setup item

WAIT enable

ASTB pulse width

Burst ROM page read cycle

Content

Enable external WAIT input

Disable external WAIT input

2 clocks × (CExMLT)

1 clock × (CExMLT)

16 clocks × (CExMLT)

Control bit settings

WAITEN (D0/0x48384) = 1

WAITEN (D0/0x48384) = 0 (default)

ASTBW (D2/0x48384) = 1

ASTBW (D2/0x48384) = 0 (default)

PGRD_CYC[3:0] (D[3:0]/0x48386) = 0

PGRD_CYC[3:0] (D[3:0]/0x48386) = 15 (default)

∗ CExMLT in the table above (where x = numeric values 4 to 11 corresponding to #CE4 to #CE11) is an integer

multiple (x1, x2 or x4) set for each area to extend access cycles.

WAIT enable

Wait requests from external devices using the external #WAIT pin can be enabled or disabled by setting

WAITEN (D0/0x48384) = 1 or 0. When enabled, wait cycles are inserted while the #WAIT signal remains

active (low) during access to external devices.

This wait cycle is effective only when accessing an area whose device type is selected as SRAM, and is not

inserted when accessing burst ROM or SDRAM.

Even for chips with an SRAM-type extension module mapped to any external memory area, this setting applies

to the internal #WAIT signal, allowing wait cycles to be inserted.

∗ WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384)

ASTB pulse width

The BBCU generates an address strobe (ASTB) pulse at the start of external bus access. The pulse width can be

set to one or two clocks (extended x1, x2 or x4 as set for each area) by using ASTBW (D2/0x48384).

The ASTB pulse can be output externally by setting up the relevant port. For details of port assignments and

how to switch over the port functions, see Section I.3.3, “Switching Over the Multiplexed Pin Functions.”

∗ ASTBW: ASTB Pulse Width Bit in the Bus Control Register (D2/0x48384)

Burst ROM page read cycle

Burst ROM may be connected to the CE5, CE8, and CE10 areas. A page read cycle occurs when any of these

areas receives a refill request from the cache or read request from the DMAC. You can set the number of page

read cycles from 1 to 16 clocks (extended x1, x2 or x4 as set for each area) by using PGRD_CYC[3:0] (D[3:0]/

0x48386).

∗ PGRD_CYC[3:0]: Number of Page Read Cycle Bits in the Common Cycle Control Register (D[3:0]/0x48386)

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III-2-10 EPSON S1C33401 TECHNICAL MANUAL

III.2.6.6 Per-Area Condition Settings

Bus access conditions can be set by area for each #CEx signal. Therefore, the same conditions for two or more

areas accommodated by the respective #CEx signals will be set.

This section describes the parameters to be set individually for each area and the relevant control bits.

The BBCU control registers are initialized by an initial reset. These registers should be set up back again in

software to suit the external device configuration or specification as required.

For details of bus cycle operation, see Section III.2.9, “Bus Access Timing Chart.”

Note: The control register and control bit configurations are the same for all CE4 to CE11 areas. The

control bit names begin with CE4 to CE11 to indicate the relevant areas, which in the description

below are commonly represented by CEx for all areas.

Table III.2.6.6.1 Per-area Parameter Settings

Setup item

External/internal access

Endian mode

Interface mode

Device type

Burst ROM selection

(CE10, CE8, CE5 areas only)

Device size

Bus clock synchronization

Access cycle multiplication

CE cycle

RD start state

RD start state option

(-0.5 clock)

RD end state

WR start state

WR start state option

(-0.5 clock)

WR end state

WR end state option

(-0.5 clock)

Content

Access internal device

Access external device

Big endian

Little endian

BSL mode

A0 mode

EBCU device (SDRAM)

BBCU device (SRAM)

Use Burst ROM

Do not use Burst ROM

32 bits

16 bits (connect to 16 high-order

data bus bits)

16 bits (connect to 16 low-order

data bus bits)

8 bits

Synchronous

Asynchronous

Multiplied by 4

Multiplied by 2

Multiplied by 1

16 clocks × (CExMLT)

8 clocks × (CExMLT)

1 clock × (CExMLT)

4 clocks × (CExMLT)

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

Enable

Disable

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

0 clocks × (CExMLT)

4 clocks × (CExMLT)

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

Enable

Disable

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

0 clocks × (CExMLT)

Enable

Disable

Control bit settings

CExIO (D13/REG_A) = 1

CExIO (D13/REG_A) = 0 (default)

CExBIG (D12/REG_A) = 1

CExBIG (D12/REG_A) = 0 (default)

CExBSL (D11/REG_A) = 1

CExBSL (D11/REG_A) = 0 (default)

CExEBCU (D10/REG_A) = 1

CExEBCU (D10/REG_A) = 0 (default)

BROM_CEx (D[6:4]/0x48384) = 1

BROM_CEx (D[6:4]/0x48384) = 0 (default)

CExDVSZ[1:0] (D[9:8]/REG_A) = 11

CExDVSZ[1:0] (D[9:8]/REG_A) = 10

CExDVSZ[1:0] (D[9:8]/REG_A) = 01 (default)

CExDVSZ[1:0] (D[9:8]/REG_A) = 00

CExBCKSYN (D5/REG_A) = 1 (default)

CExBCKSYN (D5/REG_A) = 0

CExMLT[1:0] (D[15:14]/REG_B) = 10 or 11 (default)

CExMLT[1:0] (D[15:14]/REG_B) = 01

CExMLT[1:0] (D[15:14]/REG_B) = 00

CExCE[3:0] (D[3:0]/REG_B) = 1111

CExCE[3:0] (D[3:0]/REG_B) = 0111 (default)

CExCE[3:0] (D[3:0]/REG_B) = 0000

CExRDSTAC[1:0] (D[7:6]/REG_B) = 11

CExRDSTAC[1:0] (D[7:6]/REG_B) = 10

CExRDSTAC[1:0] (D[7:6]/REG_B) = 01 (default)

CExRDSTAC[1:0] (D[7:6]/REG_B) = 00

CExRSTHCK (D2/REG_A) = 1

CExRSTHCK (D2/REG_A) = 0 (default)

CExRDENDC[1:0] (D[5:4]/REG_B) = 11

CExRDENDC[1:0] (D[5:4]/REG_B) = 10 (default)

CExRDENDC[1:0] (D[5:4]/REG_B) = 01

CExRDENDC[1:0] (D[5:4]/REG_B) = 00

CExWRSTAC[1:0] (D[11:10]/REG_B) = 11

CExWRSTAC[1:0] (D[11:10]/REG_B) = 10

CExWRSTAC[1:0] (D[11:10]/REG_B) = 01 (default)

CExWRSTAC[1:0] (D[11:10]/REG_B) = 00

CExWSTHCK (D4/REG_A) = 1

CExWSTHCK (D4/REG_A) = 0 (default)

CExWRENDC[1:0] (D[9:8]/REG_B) = 11

CExWRENDC[1:0] (D[9:8]/REG_B) = 10 (default)

CExWRENDC[1:0] (D[9:8]/REG_B) = 01

CExWRENDC[1:0] (D[9:8]/REG_B) = 00

CExWEDHCK (D3/REG_A) = 1

CExWEDHCK (D3/REG_A) = 0 (default)

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Setup item

Access disable cycle

Output disable cycle

Content

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

0 clocks × (CExMLT)

3 clocks × (CExMLT)

2 clocks × (CExMLT)

1 clock × (CExMLT)

0 clocks × (CExMLT)

Control bit settings

CExADISC[1:0] (D[13:12]/REG_B) = 11 (default)

CExADISC[1:0] (D[13:12]/REG_B) = 10

CExADISC[1:0] (D[13:12]/REG_B) = 01

CExADISC[1:0] (D[13:12]/REG_B) = 00

CExODISC[1:0] (D[1:0]/REG_A) = 11 (default)

CExODISC[1:0] (D[1:0]/REG_A) = 10

CExODISC[1:0] (D[1:0]/REG_A) = 01

CExODISC[1:0] (D[1:0]/REG_A) = 00

REG_A: CEx Area Configuration Register (0x48388 + 4•(x - 4))

REG_B: CEx Access Cycle Control Register (0x4838A + 4•(x - 4))

(where x = numeric values 4 to 11 corresponding to #CE4 to #CE11)

External/internal access

Any extension modules incorporated in the chip may be assigned an external memory area. Before an internal

device can be accessed, control bit CExIO (D13/0x48388 + 4•(x - 4)) for the assigned CEx area must be set to 1.

This control bit is initially set to 0 for external devices to be accessed.

∗ CExIO: External/Internal Access Setting Bit in the CEx Area Configuration Register (D13/0x48388 + 4•(x - 4))

Note: If a C33 ADV model with built-in ROM in CE10 area is started after setting external pin EA10MD

to 0, CE10IO (D13/0x483A0) defaults to 0 and internal ROM is accessed. (For EA10MD, see

Section III.2.6.2, “Area 20 and Boot Mode.”)

Endian mode

The halfword and word data in memory are accessed in little endian mode by default. When any external device

must be accessed in big endian mode, set CExBIG (D12/0x48388 + 4•(x - 4)) to 1.

∗ CExBIG: Endian Mode Select Bit in the CEx Area Configuration Register (D12/0x48388 + 4•(x - 4))

For details of the data size and endian mode-dependent bus operation, see Section III.2.7.3, “External Bus

Operation.”

Interface mode

The BBCU incorporates an SRAM-type bus interface, allowing A0 (default) or BSL to be selected as the

interface mode. To use the BSL-mode interface in the CEx area, set CExBSL (D11/0x48388 + 4•(x - 4)) to 1.

∗ CExBSL: External Interface Mode Select Bit in the CEx Area Configuration Register (D11/0x48388 + 4•(x - 4))

Table III.2.6.6.2 lists the bus control signal pins used in each interface mode.

Table III.2.6.6.2 Bus Control Signal Pins Used in A0 and BSL Modes

Pin name

#CEx

#RD

#BSLL(#BSL)

#WRLL(#WRL)

#WRLH(#WRH)

#WRHL

#WRHH

A0 mode (default)

#CEx

#RD

Unused

#WRLL(#WRL)

#WRLH(#WRH)

#WRHL

#WRHH

Little endian

#CEx

#RD

#BSLL(#BSL)

#WR

#BSLH(#BSH)

#BSHL

#BSHH

Big endian

#CEx

#RD

#BSLH(#BSH)

#WR

#BSLL(#BSL)

#BSHH

#BSHL

BSL mode

Device type

The device type (interface) to be connected can be selected for each CE area. Initially, the device type is

selected as SRAM type (BBCU SRAM interface) for all areas. To use SDRAM (EBCU SDRAM interface) in

the CEx area, set CExEBCU (D10/0x48388 + 4•(x - 4)) to 1.

∗ CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4•(x - 4))

Burst ROM may be used in the CE5, CE8, and CE10 areas. To use burst ROM in the CE10 area, for example,

set CE10EBCU (D10/0x483A0) to 0 and BROM_CE10 (D6/0x48384) to 1.

∗ BROM_CEx: CEx Area Burst ROM Select Bit in the Bus Control Register (D6/0x48384 for CE10,

D5 for CE8, D4 for CE5)

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III-2-12 EPSON S1C33401 TECHNICAL MANUAL

Table III.2.6.6.3 lists a combination of control bits and selected device types.

Table III.2.6.6.3 Selection of Device Types

CExEBCU

BROM_CEx *

Device type

SDRAM

Burst ROM *

SRAM

∗ Burst ROM may only be selected for the CE5, CE8, and CE10 areas.

Device size

Use CExDVSZ[1:0] (D[9:8]/0x48388 + 4•(x - 4)) to select a device size.

∗ CExDVSZ[1:0]: Device Size Select Bits in the CEx Area Configuration Register (D[9:8]/0x48388 + 4•(x - 4))

Table III.2.6.6.4 Selection of Device Sizes

CExDVSZ1

CExDVSZ0

Device size

32 bits

16 bits (16 high-order data bus bits)

16 bits (16 low-order data bus bits)

8 bits

Connected data bus

D[31:0] (Note)

D[31:16] (Note)

D[15:0]

D[7:0]

At an initial reset, the device size is initialized to 16 bits (16 low-order data bus bits).

Note: For C33 ADV models with 16 external data bus pins, D[15:0], 32 bits or 16 bits (16 high-order

data bus bits) may be selected for the device size only when using an internal device.

Bus clock synchronization

With initial settings, the read/write signals are output synchronized with BCLK. When external devices are

clocked by BCLK, use this setting. In this setting, bus access starts synchronously with the rising edge of

BCLK.

When CExBCKSYN (D5/0x48388 + 4•(x - 4)) is set to 0, read/write signals are output asynchronously with

BCLK. This setting helps reduce the bus cycle. The BBCU generates bus control signals synchronously with

CCLK.

See Figures III.2.6.4.1 and III.2.6.4.2 for differences between BCLK synchronous mode and BCLK

asynchronous mode.

∗ CExBCKSYN: Bus Clock Synchronization Select Bit in the CEx Area Configuration Register

(D5/0x48388 + 4•(x - 4))

Access cycle multiplication

The number of bus access-related cycles can be set for each area. These values are specified in terms of core

clock CCLK counts. However, to accommodate low-speed devices, the number of cycles set by the respective

control bits may be multiplied by 4 or 2. To specify this multiply-by factor, use CExMLT[1:0] (D[15:14]/

0x4838A + 4•(x - 4)). See Figure III.2.6.4.1 for a timing example.

∗ CExMLT[1:0]: Access Cycle Multiple Mode Select Bits in the CEx Access Cycle Control Register

(D[15:14]/0x4838A + 4•(x - 4))

Table III.2.6.6.5 Access Cycle Multiply-by Factors

CExMLT1

CExMLT0

Multiply-by factor

At an initial reset, the access cycle multiply-by factors are initialized to x4 for all areas.

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Timing parameters that can be set by control bits

Before how to set each timing parameter is described below, the following diagram shows the relationship

between these parameters and positioning in the bus cycle. (Example for BCLK asynchronous operation)

CCLK

A[31:0]

#CEx

#RD

D[31:0]

valid

RD start state

∗1

∗1: When RD start state option (-0.5 clock) is enabled

CE cycle

Access

disable

cycle

Output

disable

cycle

RD end state

valid

Figure III.2.6.6.1 SRAM Read Cycle Timing Parameters

∗1∗2

∗1

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

valid

WR start state

CE cycle

Access

disable

cycle

WR end state

∗1: When WR start state option (-0.5 clock) is enabled

∗2: When WR end state option (-0.5 clock) is enabled

valid

Figure III.2.6.6.2 SRAM Write Cycle Timing Parameters

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

valid

valid (2) valid (3)

valid (4)

RD start state

Access

disable

cycle

Page read

access

CE cycle

Page read

access

Inserted page read cycles

Page read

access

Output

disable

cycle

RD end state

∗1

∗1: When RD start state option (-0.5 clock) is enabled

valid (1)

Figure III.2.6.6.3 Burst ROM Read Cycle Timing Parameters

Each timing parameter is detailed below. Confirm that the parameters are set suited to specifications of the

connected devices.

Notes: • All bus control signals are generated while synchronized with CCLK even if BCLK

synchronous mode is selected. In BCLK synchronous mode, only the read/write signal is

asserted synchronously with the rising edge of BCLK and BCLK does not affect other timings.

• The CExMLT bit multiplies the number of cycles of only the timing parameters shown below by

1, 2, or 4.

CE cycle, RD start state, RD end state, WR start state, WR end state (0 to 3), access disable

cycle, and output disable cycle

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III-2-14 EPSON S1C33401 TECHNICAL MANUAL

CE cycle

The CE cycle is the period of time during which the #CEx signal is asserted (low) in one access made. Use

CExCE[3:0] (D[3:0]/0x4838A + 4•(x - 4)) to specify the number of CCLK clocks.

∗ CExCE[3:0]: CE Cycle Setup Bits in the CEx Access Cycle Control Register (D[3:0]/0x4838A + 4•(x - 4))

Table III.2.6.6.6 CE Cycle Settings

CExCE3

CExCE2

CE cycle

16 clocks

15 clocks

8 clocks

2 clocks

1 clock

CExCE1

CExCE0

The actual CE cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0] (D[15:14]/

0x4838A + 4•(x - 4)).

Note: The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in

CCLK clock units) minus the number of RD/WR start and end state clocks (read/write pulse width)

is equal to or less than 0, device operation for that cycle cannot be guaranteed. Furthermore, the

number of CE cycles must be set to two or more clocks (one clock cannot be specified).

RD/WR start state and -0.5 cycle option

The timing at which read and write signals are asserted can be set by using CExRDSTAC[1:0] (D[7:6]/0x4838A

+ 4•(x - 4)) and CExWRSTAC[1:0] (D[11:10]/0x4838A + 4•(x - 4)), respectively.

∗ CExRDSTAC[1:0]: Read Start State Setup Bits in the CEx Access Cycle Control Register

(D[7:6]/0x4838A + 4•(x - 4))

∗ CExWRSTAC[1:0]: Write Start State Setup Bits in the CEx Access Cycle Control Register

(D[11:10]/0x4838A + 4•(x - 4))

Table III.2.6.6.7 RD/WR Start State Settings

CExRDSTAC1

CExWRSTAC1

CExRDSTAC0

CExWRSTAC0

RD/WR start state

4 clocks

3 clocks

2 clocks

1 clock

This setting selects the number of CCLK clocks until the read/write signal becomes active (goes low). The

starting point of the RD/WR start state varies depending on the bus clock synchronization mode selected by

CExBCKSYN (D5/0x48388 + 4•(x - 4)).

When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 0), this setting

indicates the number of CCLK clocks from the first rise of BCLK (after the #CEx signal is asserted) to when

the read/write signal becomes active (goes low).

When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 1), this setting

indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when the read/write

signal becomes active (goes low).

At an initial reset, the RD/WR start state is initialized to two clocks.

The actual RD/WR start state equals this number of clocks multiplied by the factor set by CExMLT[1:0]

(D[15:14]/0x4838A + 4•(x - 4)).

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Moreover, an option available for the RD/WR start state allows the read/write signal to be asserted 0.5 cycle

before the set timing. To specify this option, set CExRSTHCK (D2/0x48388 + 4•(x - 4)) to 1 for read; set

CExWSTHCK (D4/0x48388 + 4•(x - 4)) to 1 for write. At an initial reset, these bits are initialized to 0, so that

the option is not effective.

∗ CExRSTHCK: RD Start State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register

(D2/0x48388 + 4•(x - 4))

∗ CExWSTHCK: WR Start State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register

(D4/0x48388 + 4•(x - 4))

Notes: • The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)) does not apply to the

RD/WR start state option (-0.5 clock).

• When the CCLK frequency is 49 MHz or higher, do not enable the RD/WR start state option

(-0.5 clock).

• If the WR start state option is specified when the actual WR start state is one clock, valid write

data will not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE).

At least one clock period is required before write data can be set up after #CE is asserted.

RD/WR end state and -0.5 cycle option

The timing at which read and write signals are deasserted can be set by using CExRDENDC[1:0] (D[5:4]/

0x4838A + 4•(x - 4)) and CExWRENDC[1:0] (D[9:8]/0x4838A + 4•(x - 4)), respectively.

∗ CExRDENDC[1:0]: Read End State Setup Bits in the CEx Area Cycle Control Register (D[5:4]/0x4838A + 4•(x - 4))

∗ CExWRENDC[1:0]: Write End State Setup Bits in the CEx Area Cycle Control Register (D[9:8]/0x4838A + 4•(x - 4))

Table III.2.6.6.8 RD/WR End State Settings

CExRDENDC1

CExWRENDC1

CExRDENDC0

CExWRENDC0

RD/WR end state

3 clocks

2 clocks

1 clock

0 clocks

This sets the number of clocks (in CCLK clock units) at which time the read/write signal becomes inactive (goes

high) before a separately specified CE cycle ends.

At an initial reset, the RD/WR end state is initialized to two clocks.

The actual RD/WR end state equals this number of clocks multiplied by the factor set by CExMLT[1:0]

(D[15:14]/0x4838A + 4•(x - 4)).

Moreover, an option available for the WR end state allows the write signal to be deasserted 0.5 cycle after the

set timing. To specify this option, set CExWEDHCK (D3/0x48388 + 4•(x - 4)) to 1. At an initial reset, this bit is

initialized to 0, so that the option is not effective.

∗ CExWEDHCK: WR End State Option (-0.5 clock) Select Bit in the CEx Area Configuration Register

(D3/0x48388 + 4•(x - 4))

Notes: • The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)) does not apply to the

WR end state option (-0.5 clock).

• When the CCLK frequency is 49 MHz or higher, do not enable the WR end state option (-0.5

clock).

• If the number of WR end state cycles is set to 0 clock by CExWRENDC[1:0] (D[9:8]/0x4838A

+ 4•(x - 4)), the WR end state option (-0.5 clock) is ignored.

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Access-disable cycle

To accommodate low-speed devices, an access-disable cycle can be inserted before the next CE cycle starts

after a data access (after the end of the preceding CE cycle). Use CExADISC[1:0] (D[13:12]/0x4838A + 4•(x - 4))

to make this setting.

∗ CExADISC[1:0]: Access Disable State Setup Bits in the CEx Access Cycle Control Register

(D[13:12]/0x4838A + 4•(x - 4))

Table III.2.6.6.9 Access-Disable Cycle Settings

CExADISC1

CExADISC0

Access disable cycle

3 clocks

2 clocks

1 clock

0 clocks

The access-disable cycle set here is inserted before the next CE cycle or an output-disable cycle starts after a

separately specified CE cycle ends.

At an initial reset, the access-disable cycle is initialized to three clocks.

The actual access-disable cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0]

(D[15:14]/0x4838A + 4•(x - 4)).

The following shows the conditions under which the access-disable cycle is inserted.

• The access-disable cycle is always inserted when accessing the CE area for either read or write access.

• The access-disable cycle is inserted immediately after a CE cycle (or any set RD/WR end state).

• The access-disable cycle is also inserted when accessing the same area successively (including when data

size > device size).

• For page read access to burst ROM, the access-disable cycle is inserted immediately after a CE cycle that

includes a series of page read cycles (or after any set RD end state).

• For burst transfer to other than burst ROM (four or eight consecutive words), the access-disable cycle is

inserted for every four or eight words transferred.

Output-disable cycle

To accommodate devices for which output takes a long time, an output-disable cycle can be inserted before the

next CE cycle starts after a data read operation. Use CExODISC[1:0] (D[1:0]/0x48388 + 4•(x - 4)) to make this

setting.

∗ CExODISC[1:0]: Output-Disable Cycle Configuration Bits in the CEx Area Configuration Register

(D[1:0]/0x48388 + 4•(x - 4))

Table III.2.6.6.10 Output-Disable Cycle Settings

CExODISC1

CExODISC0

Output disable cycle

3 clocks

2 clocks

1 clock

0 clocks

The output-disable cycle specified here is inserted before the next CE cycle starts after a separately specified

access-disable cycle ends (or after the end of the preceding CE cycle if no access-disable cycles are inserted).

At an initial reset, the output-disable cycle is initialized to three clocks.

The actual output-disable cycle equals this number of clocks multiplied by the factor set by CExMLT[1:0]

(D[15:14]/0x4838A + 4•(x - 4)).

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The following shows the conditions under which the output-disable cycle is inserted.

• The output-disable cycle is always inserted during read access.

• The output-disable cycle is inserted immediately after an access-disable cycle (or immediately after a CE

cycle if no access-disable cycles are set).

• For read access where data size > device size, the output-disable cycle is only inserted during the last access.

• For page read access to burst ROM and a burst read from other than burst ROM (four consecutive words), the

output-disable cycle is inserted in the last access made.

• No output-disable cycle is inserted during write access.

• No output-disable cycle is inserted during consecutive accesses to the same area.

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III-2-18 EPSON S1C33401 TECHNICAL MANUAL

III.2.7 Connection of External Devices and Bus Operation

III.2.7.1 Connecting External Devices

The following shows an example of connecting the S1C33 chip and SRAM.

S1C33

A[n:0]

D[7:0]

#CEx

#RD

#WRLL

SRAM

A[n:0]

I/O[7:0]

#CE

#OE

#WE

S1C33

A[n:0]

D[15:8]

#CEx

#RD

#WRLH

SRAM

A[n:0]

I/O[7:0]

#CE

#OE

#WE

Figure III.2.7.1.1 Example of 8-bit SRAM Connection with 8-bit Device Size

S1C33

A[n:1]

D[15:0]

#CEx

#RD

#WRLL

#WRLH

SRAM

A[n-1:0]

I/O[15:0]

#CE

#OE

#WEL

#WEH

S1C33

A[n:1]

D[15:0]

#CEx

#RD

#WR

#BSLL

#BSLH

SRAM

A[n-1:0]

I/O[15:0]

#CE

#OE

#WE

#LB

#UB

Figure III.2.7.1.2 Example of 16-bit SRAM Connection with 16-bit (lower) Device Size

S1C33

A[n:2]

D[15:0]

D[31:16]

#CEx

#RD

#WRLL

#WRLH

#WRHL

#WRHH

SRAM

A[n-2:0]

I/O[15:0]

#CE

#OE

#WEL

#WEH

S1C33

A[n:2]

D[15:0]

D[31:16]

#CEx

#RD

#WR

#BSLL

#BSLH

#BSHL

#BSHH

SRAM

A[n-2:0]

I/O[15:0]

#CE

#OE

#WE

#LB

#UB

A[n-2:0]

I/O[15:0]

#CE

#OE

#WEL

#WEH

A[n-2:0]

I/O[15:0]

#CE

#OE

#WE

#LB

#UB

Figure III.2.7.1.3 Example of 16-bit SRAM Connection with 32-bit Device Size

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III.2.7.2 Data Configuration in Memory

The C33 ADV system handles byte (8-bit), halfword (16-bit), and word (32-bit) data. To access data in memory,

addresses aligned to the boundary of the data size must be specified. Specifying other addresses generates address

misaligned exceptions.

Instructions (e.g., stack manipulating and branch instructions) that rewrite the content of the Stack Pointer (SP)

or Program Counter (PC) forcibly alter the address specified to a boundary address to prevent address misaligned

exceptions. For details of address misaligned exceptions, refer to the C33 ADV Core CPU Manual.

Table III.2.7.2.1 shows where each type of data is located in memory.

Table III.2.7.2.1 Data Locations in Memory

Data type

Byte

Halfword

Word

Location

Byte boundary (all addresses)

Halfword boundary (A[0] = 0)

Word boundary (A[1:0] = 0b00)

All halfword and word data in memory are accessed in little endian mode by default. You can switch little endian

mode to big endian mode for each CE area by setting CExBIG (D12/0x48388 + 4•(x - 4)) to 1.

∗ CExBIG: Endian Mode Select Bit in the CEx Area Configuration Register (D12/0x48388 + 4•(x - 4))

To increase memory efficiency, try locating the same type of data at contiguous addresses to reduce blank areas

created by positioning at boundary addresses as much as possible.

III.2.7.3 External Bus Operation

The external data bus size in the C33 ADV is 32 bits. Note, however, that standard S1C33 models have 16

external bus pins D[15:0]. Depending on the device size and data size of the instruction executed, two or more bus

operations may occur. Table III.2.7.3.1 shows bus operation in A0 mode; Table III.2.7.3.2 shows bus operation in

BSL mode.

For details on how to connect memory, see Section III.2.7.1, “Connecting External Devices.”

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Table III.2.7.3.1 Bus Operation in A0 Mode

Device

size

8 bits

16 bits

(lower)

16 bits

(higher)

32 bits

Data

size

Byte

Half

word

Word

Byte

Half

word

Word

Byte

Half

word

Word

Byte

Half

word

Word

R/W

Valid

signal

#WRLL

#RD

#WRLL

#RD

#WRLL

#RD

#WRLL

#WRLH

#RD

#WRL∗

#RD

#WRL∗

#RD

#WRLL

#WRLH

#RD

#WRL∗

#RD

#WRL∗

#RD

#WRLL

#WRLH

#WRHL

#WRHH

#RD

#WRL∗

#WRH∗

#RD

#WR∗∗

#RD

Little endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

D[15:8]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[7:0]

pins

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[23:16]

D[31:24]

D[7:0]

D[15:8]

D[23:16]

D[31:24]

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

Valid

signal

#WRLH

#RD

#WRLH

#RD

#WRLH

#RD

#WRLH

#WRLL

#RD

#WRL∗

#RD

#WRL∗

#RD

#WRLH

#WRLL

#RD

#WRL∗

#RD

#WRL∗

#RD

#WRLH

#WRLL

#WRHH

#WRHL

#RD

#WRH∗

#WRL∗

#RD

#WR∗∗

#RD

Big endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

pins

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[7:0]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[7:0]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

Access

count

1st

2nd

1st

2nd

1st

2nd

3rd

4th

1st

2nd

3rd

4th

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

3rd

4th

1st

2nd

3rd

4th

1st

2nd

1st

2nd

∗

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

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BBCU

Table III.2.7.3.2 Bus Operation in BSL Mode

Device

size

8 bits

16 bits

(lower)

16 bits

(higher)

32 bits

Data

size

Byte

Half

word

Word

Byte

Half

word

Word

Byte

Half

word

Word

Byte

Half

word

Word

R/W

Valid

signal

#BSLL

#RD

#BSLL

#RD

#BSLL

#RD

#BSLL

#BSLH

#RD

#BSL∗

#RD

#BSL∗

#RD

#BSLL

#BSLH

#RD

#BSL∗

#RD

#BSL∗

#RD

#BSLL

#BSLH

#BSHL

#BSHH

#RD

#BSL∗

#BSH∗

#RD

#BS∗∗

#RD

Little endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

D[15:8]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[7:0]

pins

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[23:16]

D[31:24]

D[7:0]

D[15:8]

D[23:16]

D[31:24]

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

Valid

signal

#BSLH

#RD

#BSLH

#RD

#BSLH

#RD

#BSLH

#BSLL

#RD

#BSL∗

#RD

#BSL∗

#RD

#BSLH

#BSLL

#RD

#BSL∗

#RD

#BSL∗

#RD

#BSLH

#BSLL

#BSHH

#BSHL

#RD

#BSH∗

#BSL∗

#RD

#BS∗∗

#RD

Big endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

pins

D[7:0]

D[15:8]

D[7:0]

D[15:8]

D[7:0]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[7:0]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

Access

count

1st

2nd

1st

2nd

1st

2nd

3rd

4th

1st

2nd

3rd

4th

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

3rd

4th

1st

2nd

3rd

4th

1st

2nd

1st

2nd

∗

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

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III-2-22 EPSON S1C33401 TECHNICAL MANUAL

III.2.8 BBCU Operating Clock and Bus Clock

III.2.8.1 Operating Clock of the BBCU

The BBCU is clocked by the core system clock (CCLK) generated by the CMU.

The bus control signals are generated synchronously with CCLK.

For details on how to set CCLK and control the clock, see Section II.3, “Clock Management Unit (CMU).”

Controlling supply of the BBCU operating clock

CCLK is supplied to the BBCU with default settings. There are four ways of supplying CCLK to the BBCU by

the CMU as detailed below. Use the respective control bits to turn off any unnecessary clock supplies to reduce

the amount of power consumed on the chip. Automatic control may also be applied for clock supplies 2 to 4.

1. BBCU, EBCU NOSTOP clock

This clock is used for controlling the entire high-speed bus. Turn this clock on when using any of the blocks

connected to the high-speed bus (e.g., the BBCU). The clock supply can be controlled by BBEBNCLK

(D11/0x48370).

∗ BBEBNCLK: BBCU, EBCU NOSTOP Control Bit in the CCLK System Peripheral Clock On/Off Register

(D11/0x48370)

2. BBCU HB interface clock

This clock is used for interfacing SRAM to the BBCU. Turn this clock on when using the SRAM interface,

regardless of whether external or internal (e.g., area 6). The clock supply can be controlled by BBHBIFCLK

(D10/0x48370). Use BBHBIFAUTO (D10/0x48372) to enable or disable the automatic control function.

∗ BBHBIFCLK: BBCU HB Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off

∗ BBHBIFAUTO: BBCU HB Interface Clock Automatic Control Bit in the CCLK System Peripheral Clock

Automatic Control Register (D10/0x48372)

3. BBCU SRAM clock

Like clock supply 2 above, this clock is used for interfacing SRAM to the BBCU. Turn this clock on when

using the SRAM interface. The clock supply can be controlled by BBSRAMCLK (D9/0x48370). Use

BBSRAMAUTO (D9/0x48372) to enable or disable the automatic control function.

∗ BBSRAMCLK: BBCU SRAM Clock Control Bit in the CCLK System Peripheral Clock On/Off Register

(D9/0x48370)

∗ BBSRAMAUTO: BBCU SRAM Clock Automatic Control Bit in the CCLK System Peripheral Clock

Automatic Control Register (D9/0x48372)

4. BBCU DBG interface clock

This clock is used for ICD-based debugging operation. Turn this clock on when debugging is performed

using an ICD. The clock supply can be controlled by BBDBGIFCLK (D8/0x48370). Use BBDBGIFAUTO

(D8/0x48372) to enable or disable the automatic control function.

∗ BBDBGIFCLK: BBCU DBG Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off

∗ BBDBGIFAUTO: BBCU DBG Interface Clock Automatic Control Bit in the CCLK System Peripheral

Clock Automatic Control Register (D8/0x48372)

Setting any of the above clock control bits (initially 1) to 0 turns off the corresponding clock supply to the

BBCU.

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BBCU

Setting both the clock control bit and automatic control bit (initially 0) for any clock supply to 1 enables the

automatic control function for that clock supply.

If the BBCU enters the IDLE state with the automatic control function enabled, clock-enable signal input to the

CMU is negated. Accordingly, the CMU stops clock supply to the BBCU. This state is called the power-down

mode of the BBCU. When an operation request to the BBCU is generated by any block, the BBCU immediately

reasserts the clock-enable signal. Clock supply from the CMU resumes one clock after the clock-enable signal

becomes active.

Note: The clock supply should be automatically controlled to reduce the amount of power consumed on

the chip. Note that some limits are imposed on the supported operating clock frequency, etc. For

details, see Section II.3, “Clock Management Unit (CMU).”

Clock state in standby mode

The supply of CCLK stops depending on the type of standby mode.

HALT mode: CCLK is supplied the same way as in normal mode.

HALT2 mode: The supply of CCLK stops.

SLEEP mode: The supply of CCLK stops.

Therefore, the BBCU also stops operating when in HALT2 or SLEEP mode.

III.2.8.2 Generation of the Bus Clock

The BBCU divides CCLK by a specified number to generate the bus clock (BCLK). This divide-by ratio is set by

using BCLKD[1:0] (D[1:0]/0x48380).

∗ BCLKD[1:0]: BCLK Setup Bits in the BCLK Divide Control Register (D[1:0]/0x48380)

Table III.2.8.2.1 BCLK (CCLK Divide-by Ratio) Settings

BCLKD1

BCLKD0

BCLK frequency

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

When initially reset, the BCLK clock is set to CCLK•1/8.

III.2.8.3 External Output of the Bus Clock

Standard specifications of the S1C33 series categorize BCLK output as an extended port function. Therefore,

before BCLK can be output to external devices, the pin function must be switched for BCLK output by using the

Function Select Register for the corresponding port. For details of the pins assigned to the BCLK output function

and how to switch the pin functions, see Section I.3.3, “Switching Over the Multiplexed Pin Functions.”

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III-2-24 EPSON S1C33401 TECHNICAL MANUAL

III.2.9 Bus Access Timing Chart

Note: Except for Figure III.2.9.4.2 in Section III.2.9.4, “BCLK Synchronous/Asynchronous Memory

Access Timing,” all timing charts shown here are for BCLK asynchronous access.

III.2.9.1 SRAM Read/Write Timing (with no External WAIT)

1. SRAM read timings with different CExMLT settings

[Example settings 1]

CE cycle: 6 clocks Access-disable cycle: 1 clock

RD start state: 2 clocks Output-disable cycle: 1 clock

RD end state: 2 clocks RD start state -0.5 clock option: Enabled

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Figure III.2.9.1.1 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x1)

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Figure III.2.9.1.2 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x2)

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Figure III.2.9.1.3 SRAM Read Timing in Example Settings 1 (where access cycle multiply-by factor (CExMLT) = x4)

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

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III

BBCU

2. SRAM read timings in A0 and BSL modes

[Example settings 2]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 3 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

#RD

D[31:16]

D[15:0]

#RDWR

(internal signal)

ASTB

valid (1)

invalid

valid (1)

RD start

CE cycle

Access

disable

Output

disable

RD end

RD start

CE cycle

Access

disable

RD end

valid (2)

invalid

Figure III.2.9.1.4 SRAM Read Timing in Example Settings 2 (for A0 Mode Halfword Read)

CCLK

A[31:0]

#CEx

#BSH∗

#BSL∗

#RD

D[31:16]

D[15:0]

#RDWR

(internal signal)

ASTB

valid (1)

invalid

valid (1)

RD start

CE cycle

Access

disable

Output

disable

RD end

RD start

CE cycle

Access

disable

RD end

valid (2)

invalid

Figure III.2.9.1.5 SRAM Read Timing in Example Settings 2 (for BSL Mode Halfword Read)

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III-2-26 EPSON S1C33401 TECHNICAL MANUAL

3. SRAM read timings with access disable or output disable cycle

[Example settings 3]

Access cycle multiply-by factor: x2 Access-disable cycle: 2 clocks

CE cycle: 4 clocks Output-disable cycle: 0 clocks

RD start state: 2 clocks RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Access

disable

RD end

Figure III.2.9.1.6 SRAM Read Timing in Example Settings 3

[Example settings 4]

Access cycle multiply-by factor: x2 Access-disable cycle: 0 clocks

CE cycle: 4 clocks Output-disable cycle: 2 clocks

RD start state: 2 clocks RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

Another #CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Output

disable

RD end

Figure III.2.9.1.7 SRAM Read Timing in Example Settings 4

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BBCU

4. SRAM read timings with different parameter combinations

[Example settings 5]

Access cycle multiply-by factor: x2 Access-disable cycle: 0 clocks

CE cycle: 7 clocks Output-disable cycle: 0 clocks

RD start state: 2 clocks RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

RD end

Figure III.2.9.1.8 SRAM Read Timing in Example Settings 5

[Example settings 6]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Enabled

RD end state: 0 clocks

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

RD start

CE cycle

Access

disable

Output

disable

Figure III.2.9.1.9 SRAM Read Timing in Example Settings 6

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III-2-28 EPSON S1C33401 TECHNICAL MANUAL

5. SRAM write timings with different CExMLT settings

[Example settings 7]

CE cycle: 6 clocks Access-disable cycle: 2 clocks

WR start state: 2 clocks WR start state -0.5 clock option: Enabled

WR end state: 2 clocks WR end state -0.5 clock option: Enabled

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

valid

WR start

CE cycle

Access

disable

WR end

Figure III.2.9.1.10 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x1)

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

valid

WR start

CE cycle

Access

disable

WR end

Figure III.2.9.1.11 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x2)

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

valid

WR start

CE cycle

Access

disable

WR end

Figure III.2.9.1.12 SRAM Write Timing in Example Settings 7 (where access cycle multiply-by factor (CExMLT) = x4)

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BBCU

6. SRAM write timings in A0 and BSL modes

[Example settings 8]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks WR start state -0.5 clock option: Disabled

WR start state: 1 clock WR end state -0.5 clock option: Disabled

WR end state: 1 clock

CCLK

A[31:0]

#CEx

#WRH∗

#WRL∗

D[31:16]

D[15:0]

#RDWR

(internal signal)

ASTB

valid (1)

invalid

valid (1)

WR start

CE cycle

Access

disable

WR end

WR start

CE cycle

Access

disable

WR end

valid (2)

invalid

Figure III.2.9.1.13 SRAM Write Timing in Example Settings 8 (for A0 Mode Halfword Write)

CCLK

A[31:0]

#CEx

#BSH∗

#BSL∗

#WR

D[31:16]

D[15:0]

#RDWR

(internal signal)

ASTB

valid (1)

invalid

valid (1)

WR start

CE cycle

Access

disable

WR end

WR start

CE cycle

Access

disable

WR end

valid (2)

invalid

Figure III.2.9.1.14 SRAM Write Timing in Example Settings 8 (for BSL Mode Halfword Write)

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III-2-30 EPSON S1C33401 TECHNICAL MANUAL

7. SRAM write timings with different parameter combinations

[Example settings 9]

Access cycle multiply-by factor: x2 Access-disable cycle: 0 clocks

CE cycle: 7 clocks WR start state -0.5 clock option: Enabled

WR start state: 2 clocks WR end state -0.5 clock option: Enabled

WR end state: 2 clocks

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

valid

WR start

CE cycle

WR end

Figure III.2.9.1.15 SRAM Write Timing in Example Settings 9

[Example settings 10]

Access cycle multiply-by factor: x2 Access-disable cycle: 2 clocks

CE cycle: 4 clocks WR start state -0.5 clock option: Disabled

WR start state: 2 clocks WR end state -0.5 clock option: Disabled

WR end state: 0 clocks

Access

disable

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

valid

WR start

CE cycle

Figure III.2.9.1.16 SRAM Write Timing in Example Settings 10

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BBCU

III.2.9.2 SRAM Read/Write Timing (with External WAIT)

A wait cycle can be inserted from external pin #WAIT only when the selected device type is SRAM, with WAITEN

(D0/0x48384) set to 1 (enabled).

∗ WAITEN: Wait Enable Bit in the Bus Control Register (D0/0x48384)

The external #WAIT signal is sampled on the rising edges of CCLK at one clock (CCLK) before the read or write

signal goes high. A wait state is entered while the #WAIT signal is sampled active (low), and subsequent operation

resumes when the #WAIT signal is sampled inactive (high).

Note: Within the BBCU, the #WAIT signal is sampled synchronously with the core system clock (CCLK).

Therefore, if the #WAIT signal is derived from BCLK, a wait request may not be input in time

during the sampling period, resulting in no wait cycles being inserted (especially with BCLK

asynchronous), depending on the relationship between CCLK and BCLK.

1. SRAM read timings with external WAIT input

[Example settings 11]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

#WAIT

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Wait

cycle

Figure III.2.9.2.1 SRAM Read Timing in Example Settings 11

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2. SRAM write timings with external WAIT input

[Example settings 12]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks WR start state -0.5 clock option: Disabled

WR start state: 1 clock WR end state -0.5 clock option: Disabled

WR end state: 1 clock

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

#WAIT

valid

WR start

CE cycle

Access

disable

WR end

Wait

cycle

Figure III.2.9.2.2 SRAM Write Timing in Example Settings 12

[Example settings 13]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks WR start state -0.5 clock option: Disabled

WR start state: 1 clock WR end state -0.5 clock option: Enabled

WR end state: 1 clock

CCLK

A[31:0]

#CEx

#WR∗∗

D[31:0]

#RDWR

(internal signal)

ASTB

#WAIT

valid

WR start

CE cycle

Access

disable

WR end

Wait

cycle

Figure III.2.9.2.3 SRAM Write Timing in Example Settings 13

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BBCU

III.2.9.3 Burst ROM Page Read Timing

A page read cycle occurs when the CE5, CE8, or CE10 area is set to burst ROM and accessed for either a “refill

request from the cache” or “load instruction from the DMAC.” Note that 16-bit and 32-bit types of burst ROM (flash)

are supported. When the device type is set to burst ROM, be sure to set a device size of either 16 bits or 32 bits.

1. Burst ROM read timings with different CExMLT settings

[Example settings 14]

CE cycle: 6 clocks Access-disable cycle: 1 clock

RD start state: 2 clocks Output-disable cycle: 1 clock

Page read cycle: 1 clock RD start state -0.5 clock option: Enabled

RD end state: 2 clocks

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01 10

valid (2) valid (3) valid (4)

valid (1)

RD startAccess

disable

Page read

access

CE cycle

Page read

access

Page read

access

Output

disable

RD end

Figure III.2.9.3.1 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x1)

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01 10

valid (2) valid (3) valid (4)

valid (1)

RD startAccess

disable

Page read

access

CE cycle

Page read

access

Page read

access

Output

disable

RD end

Figure III.2.9.3.2 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x2)

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01 10

valid (2) valid (3) valid (4)

valid (1)

RD startAccess

disable

Page read

access

CE cycle

Page read

access

Page read

access

Output

disable

RD end

Figure III.2.9.3.3 Page Read Timing in Example Settings 14 (where access cycle multiply-by factor (CExMLT) = x4)

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III-2-34 EPSON S1C33401 TECHNICAL MANUAL

2. Burst ROM read timings with access disable or output disable cycle

[Example settings 15]

Access cycle multiply-by factor: x2 RD end state: 1 clock

CE cycle: 3 clocks Access-disable cycle: 2 clocks

RD start state: 1 clock Output-disable cycle: 0 clocks

Page read cycle: 1 clock RD start state -0.5 clock option: Disabled

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01 10

valid (2) valid (3) valid (4)

valid (1)

RD start Access

disable

Page read

access

CE cycle

Page read

access

Page read

access

RD end

Figure III.2.9.3.4 Page Read Timing in Example Settings 15

[Example settings 16]

Access cycle multiply-by factor: x2 RD end state: 1 clock

CE cycle: 3 clocks Access-disable cycle: 0 clocks

RD start state: 1 clock Output-disable cycle: 2 clocks

Page read cycle: 1 clock RD start state -0.5 clock option: Disabled

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01 10

valid (2) valid (3) valid (4)

valid (1)

RD start Output

disable

Page read

access

CE cycle

Page read

access

Page read

access

RD end

Figure III.2.9.3.5 Page Read Timing in Example Settings 16

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BBCU

3. Burst ROM read timings with different parameter combinations

[Example settings 17]

Access cycle multiply-by factor: x2 RD end state: 1 clock

CE cycle: 4 clocks Access-disable cycle: 0 clocks

RD start state: 1 clock Output-disable cycle: 0 clocks

Page read cycle: 2 clocks RD start state -0.5 clock option: Disabled

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

01 10

valid (2) valid (3)

valid (4)

valid (1)

RD start

Page read

access

CE cycle

Page read

access

Page read

access

RD end

Figure III.2.9.3.6 Page Read Timing in Example Settings 17

[Example settings 18]

Access cycle multiply-by factor: x2 RD end state: 0 clocks

CE cycle: 4 clocks Access-disable cycle: 1 clock

RD start state: 2 clocks Output-disable cycle: 1 clock

Page read cycle: 1 clock RD start state -0.5 clock option: Enabled

CCLK

A[31:4]

A[3:2]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

ASTB

valid

00 01

valid (2)

valid (3)

valid (4)

valid (1)

RD start

Page read

access

CE cycle

Page read

access

Page read

access

Access

disable

Output

disable

Figure III.2.9.3.7 Page Read Timing in Example Settings 18

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III.2.9.4 BCLK Synchronous/Asynchronous Memory Access Timing

[Example settings 19]

Access cycle multiply-by factor: x2 Access-disable cycle: 1 clock

CE cycle: 4 clocks Output-disable cycle: 1 clock

RD start state: 1 clock RD start state -0.5 clock option: Disabled

RD end state: 1 clock

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

BCLK

valid

RD start

CE cycle

Access

disable

Output

disable

RD end

Figure III.2.9.4.1 BCLK Asynchronous Read Access (CExBCKSYN = 0)

CCLK

A[31:0]

#CEx

#RD

D[31:0]

#RDWR

(internal signal)

BCLK

valid

RD start

(Note)

CE cycle

Access

disable

Output

disable

RD end

Figure III.2.9.4.2 BCLK Synchronous Read Access (CExBCKSYN = 1)

∗ CExBCKSYN: Bus Clock Synchronization Select Bit in the CEx Area Configuration Register (D5/0x48388 +

4•(x - 4))

Note: Although the address, #CEx, and other signals become active asynchronously with the rising

edges of BCLK for BCLK synchronous access, the actual access cycle starts from the rising edge

of BCLK.

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BBCU

III.2.9.5 SRAM Access when Device Size < Data Size

[Example settings 20]

Access cycle multiply-by factor: x1 Output-disable cycle: 1 clock

CE cycle: 4 clocks RD start state -0.5 clock option: Disabled

RD start state: 1 clock Device size: 16 bits

RD end state: 1 clock Data size: 32 bits

Access-disable cycle: 1 clock

1. 32-bit data read from 16-bit SRAM device

CCLK

A[31:0]

#CEx

#RD

D[15:0]

valid A valid A + 2

valid

Figure III.2.9.5.1 32-bit Data Read from 16-bit SRAM Device

In the diagram above, a 16-bit SRAM device connected to the bus is accessed in units of words (in 32 bits). For

example, the HBCU supplies address “valid A” to the BBCU, which accesses internal SRAM twice in units of

16 bits to compose 32-bit data before the data is passed to the HBCU. Each 16-bit access timing is the same as

the normal read/write timing.

2. 32-bit data read from 16-bit burst ROM

CCLK

A[31:0]

#CEx

#RD

D[15:0]

valid A valid A + 2

valid

Figure III.2.9.5.2 32-bit Data Read from 16-bit Burst ROM

The timing chart above shows a case where data is read from 16-bit burst ROM by a single, 32-bit read

operation. Although instructions from the HBCU, etc. are for a single transfer, when the target device is burst

ROM, 16-bit data is read twice by a page read operation to compose 32-bit data.

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III-2-38 EPSON S1C33401 TECHNICAL MANUAL

III.2.10 External Bus Requests and Release of Bus Control

Although the BBCU and EBCU (SDRAMC) normally manage the external bus in the C33 ADV, the C33 ADV

allows bus control to be released to external bus masters. Setting EBUSMST (D1/0x48384) to 1 enables this

function (since it is disabled by default).

∗ EBUSMST: External Bus Master Enable Bit in the Bus Control Register (D1/0x48384)

The #BUSREQ and #BUSACK pins are used to control the release of bus control to external bus masters.

The following shows the sequence in which bus control is released.

1. The external bus master device requesting bus control drives the #BUSREQ pin low.

2. The BBCU always monitors the #BUSREQ pin status, so that when the pin is driven low, the BBCU drives the

#BUSACK pin low after completion of the bus cycle being executed to let the EBCU (SDRAMC) terminate the

bus cycle being executed. The BBCU also places the signals shown below in the high-impedance state.

A[31:0], D[31:0], #CE4–#CE11, #RD, #WRLL(#WRL), #WRLH(#WRH), #WRHL, #WRHH

3. One cycle after the #BUSACK pin is driven low, the external bus master starts its own bus cycle. The external

bus master must hold the #BUSREQ pin low until its bus cycle is completed.

4. After completion of the required bus cycle, the external bus master places the bus in the high-impedance state

to return the #BUSREQ pin back high.

5. The BBCU drives the #BUSACK pin back high two cycles after detecting the return of the #BUSREQ pin to

high, and resumes processing after the elapse of one clock period.

CCLK

#BUSREQ

#BUSACK

D[31:0]

A[31:0]

#RD, #WR∗∗

The S1C33

terminates the bus

cycle being executed. 1 cycle 1 cycle

The S1C33

controls bus cycles.

The external bus master

controls bus cycles.

2 cycles

1 cycle

Sync

Figure III.2.10.1 External Bus Release Timing

When bus control must be returned to the BBCU or EBCU while an external bus master retains bus control (e.g.,

SDRAM refresh request for the EBCU), the BBCU or EBCU drives the #BUSGET pin high. External bus masters

should always monitor the #BUSGET pin status, and when the #BUSGET pin is detected high, the external bus

master concerned should terminate the bus cycle and return the #BUSREQ pin to high. When required processing is

completed and the #BUSGET pin returns to low, external bus masters can request bus control again. For reference

information, see the bus release sequence for when SDRAM refresh occurs, as described in Section III.3.6.4,

“SDRAM Refresh Request when External Bus is Released.”

Note: The #BUSREQ, #BUSACK, and #BUSGET pins are shared with general-purpose input/output

ports or other peripheral circuit input/output pins. In the initial state, these pins are normally set for

other than the bus request function.

Before the #BUSREQ, #BUSACK, and #BUSGET signals can be used, the pin functions must be

switched over by using the Port Function Select Register for the respective pins.

For details about the pin functions and how to switch over, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

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BBCU

III.2.11 Control Register Details

Table III.2.11.1 BBCU Register List

Address

0x00048380

0x00048384

0x00048386

0x00048388

0x0004838A

0x0004838C

0x0004838E

0x00048390

0x00048392

0x00048394

0x00048396

0x00048398

0x0004839A

0x0004839C

0x0004839E

0x000483A0

0x000483A2

0x000483A4

0x000483A6

Function

Sets BCLK.

Selects burst ROM and enables external bus

master and external WAIT.

Sets page read cycle.

Sets CE4 area device information.

Sets CE4 area access timing conditions.

Sets CE5 area device information.

Sets CE5 area access timing conditions.

Sets CE6 area device information.

Sets CE6 area access timing conditions.

Sets CE7 area device information.

Sets CE7 area access timing conditions.

Sets CE8 area device information.

Sets CE8 area access timing conditions.

Sets CE9 area device information.

Sets CE9 area access timing conditions.

Sets CE10 area device information.

Sets CE10 area access timing conditions.

Sets CE11 area device information.

Sets CE11 area access timing conditions.

BCLK Divide Control Register (pBBCU_BCLK_DIV)

Bus Control Register (pBBCU_BUSCTL)

Common Cycle Control Register (pBBCU_CM_CYC)

CE4 Area Configuration Register (pBBCU_CE4SET)

CE4 Access Cycle Control Register (pBBCU_CE4ACCNT)

CE5 Area Configuration Register (pBBCU_CE5SET)

CE5 Access Cycle Control Register (pBBCU_CE5ACCNT)

CE6 Area Configuration Register (pBBCU_CE6SET)

CE6 Access Cycle Control Register (pBBCU_CE6ACCNT)

CE7 Area Configuration Register (pBBCU_CE7SET)

CE7 Access Cycle Control Register (pBBCU_CE7ACCNT)

CE8 Area Configuration Register (pBBCU_CE8SET)

CE8 Access Cycle Control Register (pBBCU_CE8ACCNT)

CE9 Area Configuration Register (pBBCU_CE9SET)

CE9 Access Cycle Control Register (pBBCU_CE9ACCNT)

CE10 Area Configuration Register (pBBCU_CE10SET)

CE10 Access Cycle Control Register (pBBCU_CE10ACCNT)

CE11 Area Configuration Register (pBBCU_CE11SET)

CE11 Access Cycle Control Register (pBBCU_CE11ACCNT)

Size

Each BBCU control register is described below.

The BBCU control registers are mapped to the 16-bit device area at addresses 0x48380 to 0x483A6, and can be

accessed in units of halfwords or bytes.

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III-2-40 EPSON S1C33401 TECHNICAL MANUAL

0x48380: BCLK Divide Control Register (pBBCU_BCLK_DIV)

Name

Address

–

BCLKD1

BCLKD0

D15–2

reserved

BCLK setup (CCLK division ratio)

–

R/W

Writing 1 not allowed.

0048380

(HW)

BCLKD[1:0] BCLK

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

BCLK divide

control register

(pBBCU_BCLK

_DIV)

–

D[15:2] Reserved

D[1:0] BCLKD[1:0]: BCLK Setup Bits

BCLK is the clock for external buses and generated from the core system clock (CCLK) by being

divided by a specified number. BCLKD[1:0] is used to select this divide-by ratio.

Table III.2.11.2 Selection of BCLK

BCLKD1

BCLKD0

BCLK frequency

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

(Default: 0b11 = CCLK•1/8)

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BBCU

0x48384: Bus Control Register (pBBCU_BUSCTL)

Name

Address

–

BROM_CE10

BROM_CE8

BROM_CE5

–

ASTBW

EBUSMST

WAITEN

D15–7

reserved

CE10 area burst ROM select

CE8 area burst ROM select

CE5 area burst ROM select

reserved

ASTB pulse width

External bus master enable

Wait enable

1Used 0Not used

12 clocks 01 clock

1Enabled 0Disabled

–

R/W

–

R/W

Writing 1 not allowed.

0048384

(HW)

–

BUS control

(pBBCU_BUSCTL)

–

D[15:7] Reserved

D6 BROM_CE10: CE10 Area Burst ROM Select Bit Note 1

This bit specifies the use of burst ROM in the CE10 area (Areas 10, 13, 20). This setting is only

effective when CE10EBCU (D10/0x483A0) = 0.

1 (R/W): Use burst ROM

0 (R/W): Do not use burst ROM (default)

D5 BROM_CE8: CE8 Area Burst ROM Select Bit Note 1

This bit specifies the use of burst ROM in the CE8 area (Areas 8, 21). This setting is only effective

when CE8EBCU (D10/0x48398) = 0.

1 (R/W): Use burst ROM

0 (R/W): Do not use burst ROM (default)

D4 BROM_CE5: CE5 Area Burst ROM Select Bit Note 1

This bit specifies the use of burst ROM in the CE5 area (Areas 5, 15, 16). This setting is only effective

when CE5EBCU (D10/0x4838C) = 0.

1 (R/W): Use burst ROM

0 (R/W): Do not use burst ROM (default)

Note 1: Write-accessing the area for which burst ROM is the device type selected by BROM_CE10,

BROM_CE8, or BROM_CE5 executes an SRAM-type write cycle. In this case, wait control by

the #WAIT signal is effective.

D3 Reserved

D2 ASTBW: ASTB Pulse Width Bit

This bit selects the pulse width of the address strobe (ASTB) output by the BBCU when starting

external bus access.

1 (R/W): 2 clocks

0 (R/W): 1 clock (default)

The ASTB pulse can be externally output by setting the relevant port as required. For details about

port assignments and how to switch over the port functions, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

Note: The actual pulse width equals this selected number of clocks multiplied by the factor set by

CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)).

D1 EBUSMST: External Bus Master Enable Bit

This bit enable/disables the function to release bus control to external bus masters.

1 (R/W): Enable

0 (R/W): Disable (default)

D0 WAITEN: Wait Enable Bit

This bit enables or disables wait control exercised using the #WAIT signal (#WAIT pin input) by

external/internal devices.

1 (R/W): Enable

0 (R/W): Disable (default)

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III-2-42 EPSON S1C33401 TECHNICAL MANUAL

0x48386: Common Cycle Control Register (pBBCU_CM_CYC)

Name

Address

–

PGRD_CYC3

PGRD_CYC2

PGRD_CYC1

PGRD_CYC0

D15–4

reserved

Number of read cycles in page

mode

–

R/W

Writing 1 not allowed.

0048386

(HW)

1111

0000

PGRD_CYC[3:0]

# of clocks

16 × (CExMLT)

1 × (CExMLT)

Common cycle

control register

(pBBCU_CM_CYC)

–

D[15:4] Reserved

D[3:0] PGRD_CYC[3:0]: Number of Page Read Cycle Bits

These bits set the number of clocks that comprise a page read cycle for read operation from burst ROM

connected to the CE5, CE8, or CE10 area. A page read cycle occurs when a refill request from the

cache or read request from the DMAC is received.

Table III.2.11.3 Page Read Cycle Settings

PGRD_CYC3

PGRD_CYC2

Page read cycle

16 clocks

15 clocks

14 clocks

13 clocks

12 clocks

11 clocks

10 clocks

9 clocks

8 clocks

7 clocks

6 clocks

5 clocks

4 clocks

3 clocks

2 clocks

1 clock

PGRD_CYC1

PGRD_CYC0

(Default: 0b1111 = 16 clocks)

Note: The actual cycle equals this selected number of clocks multiplied by the factor set by

CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)).

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

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BBCU

0x48388–0x483A4: CEx Area Configuration Registers (pBBCU_CExSET)

Name

Address

–

CExIO

CExBIG

CExBSL

CExEBCU

CExDVSZ1

CExDVSZ0

–

CExBCKSYN

WSTHCK

WEDHCK

CExRSTHCK

ODISC1

ODISC0

D15–14

D13

D12

D11

D10

D7–6

reserved

External/internal access setting

Endian mode select

External I/F mode select

Device type select

Device size select

reserved

Bus clock synchronization select

WR start state option (-0.5 clk)

WR end state option (-0.5 clk)

RD start state option (-0.5 clk)

Output disable cycle configuration

–

R/W

–

R/W

0 when being read.

0048388

00483A4

(HW)

CExDVSZ[1:0] Size

32 bits

16 bits (upper)

16 bits (lower)

8 bits

ODISC[1:0]

# of clocks

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

0 clocks

CEx area

configuration

(pBBCU_CExSET)

–

1Internal 0External

1Big endian 0

Little endian

1BSL mode 0A0 mode

EBCU device

BBCU device

1Sync. 0

Async.

1Enabled 0Disabled

Note: The letter ‘x’ in bit names, etc. denotes the CE area number (4 to 11).

0x48388 CE4 Area Configuration Register (pBBCU_CE4SET)

0x4838C CE5 Area Configuration Register (pBBCU_CE5SET)

0x48390 CE6 Area Configuration Register (pBBCU_CE6SET)

0x48394 CE7 Area Configuration Register (pBBCU_CE7SET)

0x48398 CE8 Area Configuration Register (pBBCU_CE8SET)

0x4839C CE9 Area Configuration Register (pBBCU_CE9SET)

0x483A0 CE10 Area Configuration Register (pBBCU_CE10SET)

0x483A4 CE11 Area Configuration Register (pBBCU_CE11SET)

D[15:14] Reserved

D13 CExIO: External/Internal Access Setting Bit

This bit selects use of the CEx area for an external device or internal device.

1 (R/W): Internal device

0 (R/W): External device (default)

D12 CExBIG: Endian Mode Select Bit

This bit selects endian mode for the CEx area.

1 (R/W): Big endian

0 (R/W): Little endian (default)

D11 CExBSL: External Interface Mode Select Bit

This bit selects interface mode (A0 or BSL) for the CEx area.

1 (R/W): BSL mode

0 (R/W): A0 mode (default)

Table III.2.11.4 Bus Control Signal Pin Functions in A0/BSL Mode

Pin name

#CEx

#RD

#BSLL(#BSL)

#WRLL(#WRL)

#WRLH(#WRH)

#WRHL

#WRHH

A0 mode (default)

#CEx

#RD

Unused

#WRLL(#WRL)

#WRLH(#WRH)

#WRHL

#WRHH

Little endian

#CEx

#RD

#BSLL(#BSL)

#WR

#BSLH(#BSH)

#BSHL

#BSHH

Big endian

#CEx

#RD

#BSLH(#BSH)

#WR

#BSLL(#BSL)

#BSHH

#BSHL

BSL mode

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D10 CExEBCU: Device Type Select Bit

This bit selects the device type for the CEx area.

1 (R/W): EBCU device (SDRAM)

0 (R/W): BBCU device (SRAM, default)

Burst ROM can be selected as the device type for the CE5, CE8, or CE10 area by setting this bit to 0

and BROM_CEx (D[6:4]/0x48384) to 1.

Table III.2.11.5 Selection of Device Type

CExEBCU

BROM_CEx *

Device type

SDRAM

Burst ROM *

SRAM

∗ Burst ROM can only be selected for the CE5, CE8, and CE10 areas.

D[9:8] CExDVSZ[1:0]: Device Size Select Bits

This bit selects the device size for the CEx area.

Table III.2.11.6 Selection of Device Size

CExDVSZ1

CExDVSZ0

Device size

32 bits

16 bits (16 high-order data bus bits)

16 bits (16 low-order data bus bits)

8 bits

Connected data bus

D[31:0] (Note)

D[31:16] (Note)

D[15:0]

D[7:0]

(Default: 0b01 = 16 bits (16 low-order data bus bits))

Note: For C33 ADV models with 16 external data bus pins, D[15:0], 32 bits or 16 bits (16 high-order

data bus bits) may be selected for the device size only when using an internal device.

D[7:6] Reserved

D5 CExBCKSYN: Bus Clock Synchronization Select Bit

This bit selects whether read/write signals are to be output synchronously with BCLK.

1 (R/W): Synchronous (default)

0 (R/W): Asynchronous

With initial settings, read/write signals are output synchronously with BCLK. Be sure to use external

devices connected to the system and clocked by BCLK with this setting.

When this bit is set to 0, read/write signals are output asynchronously with BCLK. This setting may

result in reduced bus cycles. In the BBCU, bus control signals are generated synchronously with CCLK.

D4 CExWSTHCK: WR Start State Option (-0.5 clock) Select Bit

This bit selects the WR start state option. When this option is selected, the write signal is asserted 0.5

cycle before the set timing.

1 (R/W): Enable the option

0 (R/W): Disable the option (default)

Notes: • If this option is specified when the actual WR start state is one clock, valid write data will not

be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least

one clock period is required before write data can be set up after #CE is asserted.

• The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)) does not apply to

the WR start state option (-0.5 clock).

• When the CCLK frequency is 49 MHz or higher, do not enable the WR start state option

(-0.5 clock).

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BBCU

D3 CExWEDHCK: WR End State Option (-0.5 clock) Select Bit

This bit selects the WR end state option. When this option is selected, the write signal is asserted 0.5

cycle after the set timing.

1 (R/W): Enable the option

0 (R/W): Disable the option (default)

Notes: • The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)) does not apply to

the WR end state option (-0.5 clock).

• When the CCLK frequency is 49 MHz or higher, do not enable the WR end state option (-0.5

clock).

• If the number of WR end state cycles is set to 0 clock by CExWRENDC[1:0] (D[9:8]/0x4838A

+ 4•(x - 4)), the WR end state option (-0.5 clock) is ignored.

D2 CExRSTHCK: RD Start State Option (-0.5 clock) Select Bit

This bit selects the RD start state option. When this option is selected, the read signal is asserted 0.5

cycle before the set timing.

1 (R/W): Enable the option

0 (R/W): Disable the option (default)

Notes: • The multiply-by factor set by CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)) does not apply to

the RD start state option (-0.5 clock).

• If the CCLK frequency is 49 MHz or higher, do not enable the RD start state option (-0.5

clock).

D[1:0] CExODISC[1:0]: Output-Disable Cycle Configuration Bits

These bits set the number of output-disable cycles to be inserted before the next CE cycle begins after

data read operation.

Table III.2.11.7 Output-Disable Cycle Settings

CExODISC1

CExODISC0

Output disable cycle

3 clocks

2 clocks

1 clock

0 clocks

(Default: 0b11 = 3 clocks)

The output-disable cycle specified here is inserted before the next CE cycle starts after completion of a

separately specified access-disable cycle (or after the end of the preceding CE cycle if no access-disable

cycles are inserted).

The following shows the conditions when the output-disable cycle is inserted.

• The output-disable cycle is always inserted during read access.

• The output-disable cycle is inserted immediately after an access-disable cycle (or immediately after a

CE cycle if no access-disable cycles are set).

• For read access where data size > device size, the output-disable cycle is only inserted during the last

access.

• For page read access to burst ROM and burst read access from other than burst ROM (four

consecutive words), the output-disable cycle is inserted in the last access made.

• No output-disable cycle is inserted during write access.

• No output-disable cycle is inserted during consecutive access to the same area.

Note: The actual cycle equals this selected number of clocks multiplied by the factor set by

CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)).

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

III-2-46 EPSON S1C33401 TECHNICAL MANUAL

0x4838A–0x483A6: CEx Access Cycle Control Registers (pBBCU_CExACCNT)

Name

Address

CExMLT1

CExMLT0

ADISC1

ADISC0

WRSTAC1

WRSTAC0

WRENDC1

WRENDC0

CExRDSTAC1

CExRDSTAC0

CExRDENDC1

CExRDENDC0

CExCE3

CExCE2

CExCE1

CExCE0

D15

D14

D13

D12

D11

D10

Access cycle multiple mode

select

Access disable state setup

Write start state setup

Write end state setup

Read start state setup

Read end state setup

CE cycle setup

R/W

004838A

00483A6

(HW)

1∗

CExMLT[1:0] Multiple mode

ADISC[1:0]

# of clocks

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

0 clocks

CEx access

cycle control

(pBBCU

_CExACCNT)

CExWRSTAC[1:0]

# of clocks

4 × (CExMLT)

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

WRENDC[1:0]

# of clocks

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

0 clocks

RDENDC[1:0]

# of clocks

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

0 clocks

1111

0000

CExCE[3:0] # of clocks

16 × (CExMLT)

1 × (CExMLT)

RDSTAC[1:0]

# of clocks

4 × (CExMLT)

3 × (CExMLT)

2 × (CExMLT)

1 × (CExMLT)

Note: The letter ‘x’ in bit names, etc. denotes the CE area number (4 to 11).

0x4838A CE4 Access Cycle Control Register (pBBCU_CE4ACCNT)

0x4838E CE5 Access Cycle Control Register (pBBCU_CE5ACCNT)

0x48392 CE6 Access Cycle Control Register (pBBCU_CE6ACCNT)

0x48396 CE7 Access Cycle Control Register (pBBCU_CE7ACCNT)

0x4839A CE8 Access Cycle Control Register (pBBCU_CE8ACCNT)

0x4839E CE9 Access Cycle Control Register (pBBCU_CE9ACCNT)

0x483A2 CE10 Access Cycle Control Register (pBBCU_CE10ACCNT)

0x483A6 CE11 Access Cycle Control Register (pBBCU_CE11ACCNT)

D[15:14] CExMLT[1:0]: Access Cycle Multiple Mode Select Bits

These bits set the multiply-by factor applied to the number of clocks that specify various access cycle

timings. Various cycles specified by a number of clocks for each area are specified in terms of core

clock CCLK counts. The duration of respective cycles can be multiplied by 1, 2, or 4.

Table III.2.11.8 Access Cycle Multiply-by Factors

CExMLT1

CExMLT0

Multiply-by factor

(Default: 0x11 = x4)

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

S1C33401 TECHNICAL MANUAL EPSON III-2-47

III

BBCU

D[13:12] CExADISC[1:0]: Access Disable State Setup Bits Note 1

These bits set the access-disable cycle inserted before the next CE cycle begins after data access (after

the end of the preceding CE cycle).

Table III.2.11.9 Access-Disable Cycle Settings

CExADISC1

CExADISC0

Access disable cycle

3 clocks

2 clocks

1 clock

0 clocks

(Default: 0b11 = 3 clocks)

The access-disable cycle set here is inserted before the next CE cycle or an output-disable cycle starts

after completion of a separately specified CE cycle.

The following shows the conditions when the access-disable cycle is inserted.

• The access-disable cycle is always inserted when accessing the CE area for either read or write.

• The access-disable cycle is inserted immediately after a CE cycle (or after any RD/WR end state set).

• The access-disable cycle is also inserted when accessing the same area successively (including when

data size > device size).

• For page read access to burst ROM, the access-disable cycle is inserted immediately after a CE cycle

that includes a series of page read cycles (or after any RD end state set).

• For burst transfer to other than burst ROM (four or eight consecutive words), the access-disable cycle

is inserted for every four or eight words transferred.

D[11:10] CExWRSTAC[1:0]: Write Start State Setup Bits Note 1

These bits set the timing at which the write signal is asserted.

Table III.2.11.10 WR Start State Settings

CExWRSTAC1

CExWRSTAC0

WR start state

4 clocks

3 clocks

2 clocks

1 clock

(Default: 0b01 = 2 clocks)

This setting selects the number of CCLK clocks until the write signal becomes active (goes low). The

starting point of the WR start state varies depending on the bus clock synchronization mode selected by

CExBCKSYN (D5/0x48388 + 4•(x - 4)).

When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 0), this

setting indicates the number of CCLK clocks from the first rise of BCLK after assertion of the #CEx

signal to when the write signal becomes active (goes low).

When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 1), this

setting indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when

the write signal becomes active (goes low).

The write signal can be asserted 0.5 cycle before the set timing by setting CExWSTHCK (D4/0x48388

+ 4•(x - 4)) to 1.

Note that if this option is specified when the actual WR start state is one clock, valid write data will

not be prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock

period is required before write data can be set up after #CE is asserted.

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

III-2-48 EPSON S1C33401 TECHNICAL MANUAL

D[9:8] CExWRENDC[1:0]: Write End State Setup Bits Note 1

These bits set the timing at which the write signal is deasserted.

Table III.2.11.11 WR End State Settings

CExWRENDC1

CExWRENDC0

WR end state

3 clocks

2 clocks

1 clock

0 clocks

(Default: 0b10 = 2 clocks)

Set the number of clocks (in CCLK clock units) during which the write signal becomes inactive (goes

high) before a separately specified CE cycle ends.

The write signal can be deasserted 0.5 cycle after the set timing by setting CExWEDHCK (D3/0x48388

+ 4•(x - 4)) to 1.

D[7:6] CExRDSTAC[1:0]: Read Start State Setup Bits Note 1

These bits set the timing at which the read signal is asserted.

Table III.2.11.12 RD Start State Settings

CExRDSTAC1

CExRDSTAC0

RD start state

4 clocks

3 clocks

2 clocks

1 clock

(Default: 0b01 = 2 clocks)

This setting selects the number of CCLK clocks until the read signal becomes active (goes low). The

starting point of the RD start state varies depending on the bus clock synchronization mode selected by

CExBCKSYN (D5/0x48388 + 4•(x - 4)).

When bus clock asynchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 0), this

setting indicates the number of CCLK clocks from the first rise of BCLK after assertion of the #CEx

signal to when the read signal becomes active (goes low).

When bus clock synchronous mode is selected (CExBCKSYN (D5/0x48388 + 4•(x - 4)) = 1), this

setting indicates the number of CCLK clocks from assertion (falling edge) of the #CEx signal to when

the read signal becomes active (goes low).

The read signal can be asserted 0.5 cycle before the set timing by setting CExRSTHCK (D2/0x48388 +

4•(x - 4)) to 1.

D[5:4] CExRDENDC[1:0]: Read End State Setup Bits Note 1

These bits set the timing at which the read signal is deasserted.

Table III.2.11.13 RD End State Settings

CExRDENDC1

CExRDENDC0

RD end state

3 clocks

2 clocks

1 clock

0 clocks

(Default: 0b10 = 2 clocks)

Set the number of clocks (in CCLK clock units) during which the read signal becomes inactive (goes

high) before a separately specified CE cycle ends.

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

S1C33401 TECHNICAL MANUAL EPSON III-2-49

III

BBCU

D[3:0] CExCE[3:0]: CE Cycle Setup Bits Notes 1 and 2

These bits specify the CE cycle or period during which the #CEx signal is asserted (low) in one access

by the number of CCLK clocks.

Table III.2.11.14 CE Cycle Settings

CExCE3

CExCE2

CE cycle

16 clocks

15 clocks

14 clocks

13 clocks

12 clocks

11 clocks

10 clocks

9 clocks

8 clocks

7 clocks

6 clocks

5 clocks

4 clocks

3 clocks

2 clocks

1 clock

CExCE1

CExCE0

(Default: 0b0111 = 8 clocks)

The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in CCLK

clock units) minus the number of RD/WR start and end state clocks (read/write pulse width) is equal to

or less than 0, device operation for that cycle cannot be guaranteed.

Note 1: The actual cycle equals this selected number of clocks multiplied by the factor set by

CExMLT[1:0] (D[15:14]/0x4838A + 4•(x - 4)).

Note 2: Do not set the number of CE cycles to one clock (CExCE[3:0] = 0b0000). It must be set to two

or more clocks.

III C33 ADV BUS BLOCK: BASIC BUS CONTROL UNIT (BBCU)

III-2-50 EPSON S1C33401 TECHNICAL MANUAL

III.2.12 Precautions

• Although various access timings are set by specifying the number of clocks using the registers common to all

areas and registers for specific areas, the actual number of cycles applied to the access performed equals this

specified number of clocks multiplied by the factor set by the CExMLT bit provided for each area.

Note that when the RD/WR start state and WR end state -0.5 clock options are enabled, the access timing is only

adjusted by 0.5 clock, regardless of what multiplying factor is set by the CExMLT bit.

• Note that in a system where A0 and BSL-mode SRAMs coexist in the memory map, executing write or read

access in BSL mode followed by write access in A0 mode (with access-disable and output-disable cycles for the

BSL-mode area both set to 0 clock) may corrupt the data in A0-mode SRAM. If such access is likely to occur,

make sure the access-disable cycle for the BSL-mode area is set to 1 or more.

• When the CCLK frequency is 49 MHz or higher, do not enable the RD/WR start state and WR end state options

(-0.5 clock).

• If the WR start state option is specified when the actual WR start state is one clock, valid write data will not be

prepared when the write signal is asserted (0.5 cycle after assertion of #CE). At least one clock period is required

before write data can be set up after #CE is asserted.

• The CE cycle includes the RD/WR start state and RD/WR end state. If the CE cycle (specified in CCLK clock

units) minus the number of RD/WR start and end state clocks (read/write pulse width) is equal to or less than 0,

device operation for that cycle cannot be guaranteed.

Furthermore, do not set the number of CE cycles to one clock (CExCE[3:0] = 0b0000). It must be set to two or

more clocks.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-1

III

EBCU

III.3 Extended Bus Control Unit (EBCU)

III.3.1 Overview of the EBCU

The Extended Bus Control Unit (EBCU) is one of the bus modules connected to the high-speed bus controlled by

the HBCU, with a built-in SDRAM controller. When accessing an “EBCU device” area selected in the BBCU, the

EBCU’s SDRAM interface is used as the external bus interface.

The functions and features of the EBCU are outlined below.

• SDRAM directly connected interface

• SDRAM supported area: Can be mapped to one of areas 4 to 22 (CE areas CE4 to CE11).

• Data bus width: 16 or 32 bits

• Bank address: Up to four banks are accommodated (with BS[1:0] output possible).

• Burst length: Fixed to 1 (Burst read/write is performed by issuing commands successively.)

• CAS latency: 1, 2 or 3

• Wrap type: Sequential wrap supported

• Write mode: Single write operation supported

• Switchable row/column address multiplexed widths

• Capable of self-refresh and auto-refresh

• Programmable refresh period

• Programmable timing conditions (precharge time, active command period, write recovery time, and RAS-CAS

delay time) using control registers

• Write in units of bytes via DQM pin possible

• Selectable bank active modes (with or without auto-precharge)

• Selectable SDRAM clock output (always or only at access)

EBCU

(SDRAM Controller)

Internal bus arbiter

HBCU

Port

DMA controller

BBCU

(SRAM Controller)

External bus

SDRAM

control signals

Figure III.3.1.1 Relationship between the EBCU and BBCU

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-2 EPSON S1C33401 TECHNICAL MANUAL

III.3.2 EBCU Pins

Table III.3.2.1 lists the pins used by the EBCU.

Table III.3.2.1 EBCU Pin List

Pin name

A[17:0]

D[31:0]

SDCKE

SDCLK

#SDCS

#SDRAS

#SDCAS

#SDWE

DQM0(DQML*)

DQM1(DQMH*)

DQM2

DQM3

I/O

Function

Bank select and address signal output pins (external address bus)

Data signal input/output pins (external data bus)

SDRAM clock-enable signal output pin

SDRAM clock output pin

SDRAM chip select signal output pin

SDRAM row address strobe signal output pin

SDRAM column address strobe signal output pin

SDRAM write signal output pin

SDRAM data (to select least significant byte) input/output mask signal output pin

SDRAM data (to select second byte) input/output mask signal output pin

SDRAM data (to select third byte) input/output mask signal output pin

SDRAM data (to select most significant byte) input/output mask signal output pin

* Signal names when only 16 data bus pins are available

Notes: • The list above indicates the input/output pins that the EBCU can accommodate. Depending on

the C33 ADV model used, the EBCU may have a different pin configuration as follows:

- Address bus A[17:0] may consist of less than 18 pins.

- Data bus D[31:0] may only have 16 pins, D[15:0].

- All control signal pins may not be available for some C33 ADV models.

- Pin names may be different for some C33 ADV models.

For details of the pin configuration of each C33 ADV model, see Section I.3, “Pin Description.”

• Some control pins above are shared with general-purpose input/output ports or other

peripheral circuit input/output pins, so that functionality in the initial state may be set to other

than the EBCU. Before the EBCU signals assigned to these pins can be used, the functions of

these pins must be switched for the EBCU by setting each corresponding Port Function Select

For details of pin functions and how to switch over, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-3

III

EBCU

III.3.3 Configuration of SDRAM

III.3.3.1 SDRAM Area

The EBCU requires that SDRAM be located in only one of the CE4 to CE11 areas to ensure proper control.

The BBCU manages the memory areas of the C33 ADV, so that before SDRAM can be used, it must be enabled

for use by setting the relevant BBCU register. Since the device type can be selected for each CE area by register bit

CExEBCU (D10/0x48388 + 4•(x - 4)) of the BBCU, set the corresponding CExEBCU (D10/0x48388 + 4•(x - 4)) to

1 for the area where SDRAM is to be used.

∗ CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4•(x - 4))

With initial settings, SRAM type (SRAM interface of the BBCU) is selected as the device type for all areas. For

details of the areas, see Section III.2, “Basic Bus Control Unit (BBCU).”

Note: Since SDRAM can only be used in one area, do not set CExEBCU (D10/0x48388 + 4•(x - 4)) to 1

for other areas. Furthermore, an external SRAM device cannot be mapped to the area configured

for SDRAM.

III.3.3.2 Setting SDRAM Size and Address

The table below lists the conditions related to SDRAM size and address that the EBCU can accommodate.

Table III.3.3.2.1 SDRAM Size/Address Related Setup Items

Setup item

Device size

Bank address

Column address width

Row address width

Endian mode

Content

32 bits

16 bits (connect to the 16 high-

order data bus bits)

16 bits (connect to the 16 low-

order data bus bits)

Up to four banks can be

accommodated

11 bits (2K)

10 bits (1K)

9 bits (512)

8 bits (256)

14 bits (16K)

13 bits (8K)

12 bits (4K)

11 bits (2K)

Big endian

Little endian

Control bit settings

DVSIZ[1:0] (D[13:12]/0x483C6) = 11

DVSIZ[1:0] (D[13:12]/0x483C6) = 10

DVSIZ[1:0] (D[13:12]/0x483C6) = 01 (default)

–

CAW[1:0] (D[9:8]/0x483C6) = 11

CAW[1:0] (D[9:8]/0x483C6) = 10

CAW[1:0] (D[9:8]/0x483C6) = 01 (default)

CAW[1:0] (D[9:8]/0x483C6) = 00

RAW[1:0] (D[11:10]/0x483C6) = 11

RAW[1:0] (D[11:10]/0x483C6) = 10

RAW[1:0] (D[11:10]/0x483C6) = 01 (default)

RAW[1:0] (D[11:10]/0x483C6) = 00

BIG (D15/0x483C6) = 1

BIG (D15/0x483C6) = 0 (default)

Device size

The SDRAM device size (data bit width) can be selected from 16 or 32 bits by using DVSIZ[1:0] (D[13:12]/

0x483C6). 8-bit devices cannot be used.

∗ DVSIZ[1:0]: SDRAM Device Size Select Bits in the SDRAM Option Register (D[13:12]/0x483C6)

Table III.3.3.2.2 Selection of SDRAM Device Size

DVSIZ1

DVSIZ0

Device size

32 bits

16 bits (16 high-order data bus bits)

16 bits (16 low-order data bus bits)

Settings prohibited

Connected data bus

D[31:0] (Note)

D[31:16] (Note)

D[15:0]

–

Note: For C33 ADV models with 16 external data bus pins, D[15:0], neither “32 bits” nor “16 bits (16

high-order data bus bits)” can be selected as the device size of external SDRAM.

When initially reset, the device size is initialized to 16 bits (16 low-order data bus bits).

Although the BBCU registers also have control bits CExDVSZ[1:0] (D[9:8]/0x48388 + 4•(x - 4)) to select the

device size for each area, this control bit for the area for which EBCU type (SDRAM) is selected as the device

type is disabled.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-4 EPSON S1C33401 TECHNICAL MANUAL

SDRAM address configuration

The following shows the relationship between the CPU addresses and the bank, column, and row addresses.

When 16-bit SDRAM is selected (DVSIZ[1:0] (D[13:12]/0x483C6) = 01 or 10)

A(m+n+2) A(m+n+1)

Bank address

A(m+n) · · · · · A(m+1)

Row address

A(m) · · · · · A1 A0

DQMColumn address

When 32-bit SDRAM is selected (DVSIZ[1:0] (D[13:12]/0x483C6) = 11)

A(m+n+3) A(m+n+2)

Bank address

A(m+n+1) · · · · · A(m+2)

Row address

A(m+1) · · · · · A2 A1 A0

DQMColumn address

m: Column address size (in bits)

n: Row address size (in bits)

Figure III.3.3.2.1 SDRAM Addresses

All high-order address bits not used due to memory size are fixed to 0.

Bank address

The SDRAM interface of the EBCU supports up to four banks of SDRAM. The 2 high-order bits of the

SDRAM address are used as the bank address, as shown in Figure III.3.3.2.1, “SDRAM Addresses.”

Column address width

The column address width is set by CAW[1:0] (D[9:8]/0x483C6).

∗ CAW[1:0]: Column Address Width Bits in the SDRAM Option Register (D[9:8]/0x483C6)

Table III.3.3.2.3 Column Address Width Settings

CAW1

CAW0

Column address width

11 bits (2K)

10 bits (1K)

9 bits (512)

8 bits (256)

When initially reset, the column address width is initialized to 9 bits (512).

Figure III.3.3.2.2 shows the different column address output formats due to selected device size and column

address width.

a10

a11

a10

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0Pin

CAW = 8 bits

CAW = 9 bits

CAW = 10 bits

CAW = 11 bits

Device size (DVSIZ) = 16 bits

a10

a12

a10

A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0Pin

CAW = 8 bits

CAW = 9 bits

CAW = 10 bits

CAW = 11 bits

Device size (DVSIZ) = 32 bits

a11

The set value of BACTMD (D4/0x483C6) is reflected in AP, with precharge and read/write operation controlled as

shown below.

<Precharge> AP = 0: Single bank precharge, AP = 1: All bank precharge

<Read/write> AP = 0: Read/write without auto-precharge, AP = 1: Read/write with auto-precharge

Figure III.3.3.2.2 Column Address Output Formats

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-5

III

EBCU

Row address width

The row address width is set by RAW[1:0] (D[11:10]/0x483C6).

∗ RAW[1:0]: Row Address Width Bits in the SDRAM Option Register (D[11:10]/0x483C6)

Table III.3.3.2.4 Row Address Width Settings

RAW1

RAW0

Row address width

14 bits (16K)

13 bits (8K)

12 bits (4K)

11 bits (2K)

When initially reset, the row address width is initialized to 12 bits (4K).

Figure III.3.3.2.3 shows the different row address output formats due to selected device size, column address

width, and row address width.

a16

a17

a18

a19

a20

a21 a15 a14 a13 a12 a11 a10 a9 0

a16

a17

a18

a19

a20

a21

a22

a23

a24 a15 a14 a13 a12 a11 a10 a9 0

A13A14A15A16A17 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0Pin

CAW = 8 bits

RAW = 11 bits

RAW = 14 bits

CAW = 9 bits

RAW = 11 bits

RAW = 14 bits

CAW = 10 bits

RAW = 11 bits

RAW = 14 bits

CAW = 11 bits

RAW = 11 bits

RAW = 14 bits

a16

a17

a18

a19

a20

a22 a15 a14 a13 a12 a11 a10 0

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25 a15 a14 a13 a12 a11 a10 0

a16

a17

a18

a19

a20

a22

a23 a15 a14 a13 a12 a11 0

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25

a26 a15 a14 a13 a12 a11 0

a16

a17

a18

a19

a20

a22

a23

a24 a15 a14 a13 a12 0

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25

a26

a27 a15 a14 a13 a12 0

Device size (DVSIZ) = 16 bits

a16

a17

a18

a19

a20

a21 a15 a14 a13 a12 a11 a10 00

a16

a17

a18

a19

a20

a21

a22

a23

a24 a15 a14 a13 a12 a11 a10 00

A13A14A15A16A17 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0Pin

CAW = 8 bits

RAW = 11 bits

RAW = 14 bits

CAW = 9 bits

RAW = 11 bits

RAW = 14 bits

CAW = 10 bits

RAW = 11 bits

RAW = 14 bits

CAW = 11 bits

RAW = 11 bits

RAW = 14 bits

a16

a17

a18

a19

a20

a22 a15 a14 a13 a12 a11 00

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25 a15 a14 a13 a12 a11 00

a16

a17

a18

a19

a20

a22

a23 a15 a14 a13 a12 00

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25

a26 a15 a14 a13 a12 00

a16

a17

a18

a19

a20

a22

a23

a24 a15 a14 a13 00

a16

a17

a18

a19

a20

a21

a22

a23

a24

a25

a23

a24

a25

a26

a27

a25

a26

a27

a28 a15 a14 a13 00

Device size (DVSIZ) = 32 bits

Figure III.3.3.2.3 Row Address Output Formats

Endian mode

The half-word and word data in SDRAM are accessed in little endian mode by default. When SDRAM must be

accessed in big endian mode, set BIG (D15/0x483C6) to 1.

∗ BIG: Endian Mode Select Bit in the SDRAM Option Register (D15/0x483C6)

Although the BBCU registers also have control bits CExBIG (D12/0x48388 + 4•(x - 4)) to select endian mode

for each area, this control bit for the area for which EBCU type (SDRAM) is selected as the device type is

disabled.

For bus operations in each data size and endian mode, see Section III.3.3.5, “Bus Operations of SDRAM.”

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-6 EPSON S1C33401 TECHNICAL MANUAL

III.3.3.3 Configuration of SDRAM Chips

Table III.3.3.3.1 shows the configuration of SDRAM chips determined by settings made above.

Table III.3.3.3.1 Example Configuration of SDRAM Chips

Device size

(DVSIZ[1:0] value)

32 bits (11)

16 bits (01 or 10)

Column address width /

size (CAW[1:0] value)

8 bits / 256 (00)

9 bits / 512 (01)

10 bits / 1K (10)

11 bits / 2K (11)

SDRAM configuration

1M × 8 bits × 4 banks × 4

1M × 16 bits × 4 banks × 1

1M × 8 bits × 4 banks × 2

4M × 16 bits × 4 banks × 1

8M × 16 bits × 4 banks × 1

16M × 16 bits × 4 banks × 1

32M × 16 bits × 4 banks × 1

Row address width / size

(RAW[1:0] value)

12 bits / 4K (01)

13 bits / 8K (10)

14 bits / 16K (11)

Memory size

16M bytes

8M bytes

32M bytes

64M bytes

128M bytes

256M bytes

III.3.3.4 Example Connection of SDRAMs

A few examples of how to connect SDRAMs are shown below.

S1C33

A[15:14]

A[13:1]

D[15:0]

SDCLK

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

DQM1(DQMH)

DQM0(DQML)

SDRAM

32M × 16 bits (4 banks)

(RAS: 13 bits, CAS: 10 bits)

A[14:13] (BS[1:0])

A[12:0]

DQ[15:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQMU

DQML

Figure III.3.3.4.1 Example of Connecting 64-MB SDRAM (16-bit Bus Width)

S1C33

A[14:13]

A[12:1]

D[15:0]

SDCLK

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

DQM1(DQMH)

DQM0(DQML)

SDRAM

4M × 16 bits (4 banks)

(RAS: 12 bits, CAS: 8 bits)

A[13:12] (BS[1:0])

A[11:0]

DQ[15:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQMU

DQML

S1C33

A[14:13]

A[12:1]

D[15:8]

D[7:0]

SDCLK

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

DQM1(DQMH)

DQM0(DQML)

SDRAM

4M × 8 bits (4 banks) × 2

(RAS: 12 bits, CAS: 8 bits)

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

Figure III.3.3.4.2 Example of Connecting 8-MB SDRAM (16-bit Bus Width)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-7

III

EBCU

S1C33

A[15:14]

A[13:2]

D[31:24]

D[23:16]

D[15:8]

D[7:0]

SDCLK

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

DQM3

DQM2

DQM1

DQM0

SDRAM

1M × 8 bits (4 banks) × 4

(RAS: 12 bits, CAS: 8 bits)

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

A[13:12] (BS[1:0])

A[11:0]

DQ[7:0]

CLK

CKE

#CS

#RAS

#CAS

#WE

DQM

Figure III.3.3.4.3 Example of Connecting 16-MB SDRAM (32-bit Bus Width)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-8 EPSON S1C33401 TECHNICAL MANUAL

III.3.3.5 Bus Operations of SDRAM

The external data bus of the C33 ADV is 32 bits wide. (External pins for some C33 ADV models may be 16 bits,

D[15:0].) Depending on the device size and data size of the instruction executed, two or more bus operations may

occur. Table III.3.3.5.1 shows bus operations in the SDRAM area.

Table III.3.3.5.1 Bus Operations

Device

size

16 bits

(lower)

16 bits

(higher)

32 bits

Data

size

Byte

Half

word

Word

Byte

Half

word

Word

Byte

Half

word

Word

R/W

Valid

signal

DQM0

DQM1

Read

DQM[1:0]

Read

DQM[1:0]

Read

DQM2

DQM3

Read

DQM[3:2]

Read

DQM[3:2]

Read

DQM0

DQM1

DQM2

DQM3

Read

DQM[1:0]

DQM[3:2]

Read

DQM[3:0]

Read

Little endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

D[15:8]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[7:0]

pins

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

Valid

signal

DQM0

DQM1

Read

DQM[1:0]

Read

DQM[1:0]

Read

DQM3

DQM2

Read

DQM[3:2]

Read

DQM[3:2]

Read

DQM3

DQM2

DQM1

DQM0

Read

DQM[3:2]

DQM[1:0]

Read

DQM[3:0]

Read

Big endian

D[31:24]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

–

D[23:16]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

pins

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[15:8]

–

D[15:8]

D[7:0]

pins

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

–

D[7:0]

Access

count

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

1st

2nd

3rd

4th

1st

2nd

3rd

4th

1st

2nd

1st

2nd

∗

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

D[31:0]

D[15:0]

D[31:16]

D[15:0]

D[31:16]

D[15:0]

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

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III

EBCU

III.3.4 EBCU Operating Clock and SDRAM Clock

III.3.4.1 Operating Clock of the EBCU

The EBCU is clocked by the core system clock (CCLK) generated by the CMU.

For details on how to set CCLK and control the clock, see Section II.3, “Clock Management Unit (CMU).”

Controlling the supply of the EBCU operating clock

CCLK is supplied to the EBCU with default settings. There are three ways that the CMU supplies CCLK to

the EBCU. Turn off any unnecessary means of clock supply by using the respective control bits to reduce the

amount of power consumed on the chip. Moreover, automatic control may be applied for clock supplies 2 and 3.

1. BBCU, EBCU NOSTOP clock

This clock is used for overall control of the high-speed bus. Turn this clock on when using any of the

blocks (e.g., BBCU or EBCU) connected to the high-speed bus. The clock supply can be controlled by

BBEBNCLK (D11/0x48370).

∗ BBEBNCLK: BBCU, EBCU NOSTOP Control Bit in the CCLK System Peripheral Clock On/Off Register

(D11/0x48370)

2. EBCU HB interface clock

This clock is used for interfacing SDRAM to the EBCU. Turn this clock on to use the SDRAM interface.

The clock supply can be controlled by EBCUHBCLK (D5/0x48370). Use EBCUHBAUTO (D5/0x48372)

to enable or disable the automatic control function.

∗ EBCUHBCLK: EBCU HB Interface Clock Control Bit in the CCLK System Peripheral Clock On/Off

∗ EBCUHBAUTO: EBCU HB Interface Clock Automatic Control Bit in the CCLK System Peripheral Clock

Automatic Control Register (D5/0x48372)

3. EBCU SDRAM clock

Like clock supply 2 above, this clock is used for interfacing SDRAM to the EBCU. Turn this clock on

to use the SDRAM interface. The clock supply can be controlled by EBCUSDCLK (D4/0x48370). Use

EBCUSDAUTO (D4/0x48372) to enable or disable the automatic control function.

∗ EBCUSDCLK: EBCU SDRAM Clock Control Bit in the CCLK System Peripheral Clock On/Off Register

(D4/0x48370)

∗ EBCUSDAUTO: EBCU SDRAM Clock Automatic Control Bit in the CCLK System Peripheral Clock

Automatic Control Register (D4/0x48372)

Setting any of the clock control bits above (initially 1) to 0 turns off the corresponding clock supply to the EBCU.

Setting both the clock control bit and automatic control bit (initially 0) to 1 for any clock supply enables the

automatic control function for that clock supply.

If the EBCU enters the IDLE state while the automatic control function is enabled, clock-enable signal input

to the CMU is negated. As a result, the CMU stops supplying a clock to the EBCU. This state is called power-

down mode of the EBCU. When any block generates an operation request to the EBCU, the EBCU immediately

reasserts the clock-enable signal. Clock supply from the CMU is resumed one clock after the clock-enable

signal becomes active.

Note: The clock supply should be automatically controlled to reduce the amount of power consumed on

the chip. However, limitations are imposed on the supported operating clock frequency, etc. For

details, see Section II.3, “Clock Management Unit (CMU).”

Clock state in standby mode

The supply of CCLK stops depending on type of standby mode.

HALT mode: CCLK is supplied the same way as in normal mode.

HALT2 mode: The supply of CCLK stops.

SLEEP mode: The supply of CCLK stops.

Therefore, the EBCU also stops operating when in HALT2 and SLEEP modes. Because clock output to

SDRAM is turned off, make sure SDRAM is set to self-refresh mode before entering these modes.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-10 EPSON S1C33401 TECHNICAL MANUAL

III.3.4.2 Generation of SDRAM Clock

The EBCU divides CCLK by a specific number to generate the SDRAM clock (SDCLK). This divide-by ratio is set

by using SDCLKD[1:0] (D[1:0]/0x483C0).

∗ SDCLKD[1:0]: SDCLK Setup Bits in the SDCLK Divide and Refresh Mode Register (D[1:0]/0x483C0)

Table III.3.4.2.1 SDCLK (CCLK Divide-by Ratio) Settings

SDCLKD1

SDCLKD0

SDCLK frequency

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

When initially reset, the SDCLK frequency is set to CCLK•1/8.

The SDCLK thus generated is output from the SDCLK pin.

Normally, SDCLK output is an extended port function. Therefore, before SDCLK can be output, the pin function

must be switched for SDCLK output by using the Function Select Register for the relevant port. For details of

which pins are assigned the SDCLK output function and how to switch over the pin functions, see Section I.3.3,

“Switching Over the Multiplexed Pin Functions.”

SDCLK is always output to SDRAM, not just during SDRAM access. SDCLK output can be turned off when not

accessing SDRAM by writing 1 to SDCLKS (D4/0x483C0).

∗ SDCLKS: SDCLK Output Control Bit in the SDCLK Divide and Refresh Mode Register (D4/0x483C0)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

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III

EBCU

III.3.5 Setting SDRAM Access Conditions

The SDRAM interface allows the following access conditions to be selected. For details of settings related to

SDRAM size and address, see Section III.3.3, “Configuration of SDRAM.”

Table III.3.5.1 SDRAM Access Conditions

Setup item

Command hold time

Bank active mode

CAS latency

Burst length

tRCD

(RAS-CAS delay time)

tWR

(Write recovery time)

tRP

(Precharge time)

tRFC

(Auto-refresh cycle time)

Content

3 clocks (CCLK)

2 clocks

1 clock

0 clocks

Enable (full bank active)

Disable

Fixed at 1

4 clocks (SDCLK)

3 clocks

2 clocks

1 clock

4 clocks (SDCLK)

3 clocks

2 clocks

1 clock

4 clocks (SDCLK)

3 clocks

2 clocks

1 clock

12 clocks (SDCLK)

8 clocks

1 clock

Control bit settings

CMDHLD[1:0] (D[1:0]/0x483C6) = 11

CMDHLD[1:0] (D[1:0]/0x483C6) = 10

CMDHLD[1:0] (D[1:0]/0x483C6) = 01

CMDHLD[1:0] (D[1:0]/0x483C6) = 00 (default)

BACTMD (D4/0x483C6) = 1

BACTMD (D4/0x483C6) = 0 (default)

CL[2:0] (D[6:4]/0x483CA) = 011

CL[2:0] (D[6:4]/0x483CA) = 010 (default)

CL[2:0] (D[6:4]/0x483CA) = 001

–

TRCD[1:0] (D[1:0]/0x483C8) = 11

TRCD[1:0] (D[1:0]/0x483C8) = 10

TRCD[1:0] (D[1:0]/0x483C8) = 01 (default)

TRCD[1:0] (D[1:0]/0x483C8) = 00

TWR[1:0] (D[5:4]/0x483C8) = 11

TWR[1:0] (D[5:4]/0x483C8) = 10

TWR[1:0] (D[5:4]/0x483C8) = 01

TWR[1:0] (D[5:4]/0x483C8) = 00 (default)

TRP[1:0] (D[9:8]/0x483C8) = 11

TRP[1:0] (D[9:8]/0x483C8) = 10

TRP[1:0] (D[9:8]/0x483C8) = 01 (default)

TRP[1:0] (D[9:8]/0x483C8) = 00

TRFC[3:0] (D[15:12]/0x483C8) = 1011

TRFC[3:0] (D[15:12]/0x483C8) = 0111 (default)

TRFC[3:0] (D[15:12]/0x483C8) = 0000

Command hold time

The command hold time refers to the period from the rise time of SDCLK after command output to when

command output is negated. This is specified by a number of CCLK clocks using CMDHLD[1:0] (D[1:0]/

0x483C6).

∗ CMDHLD[1:0]: Command Hold Time Setup Bits in the SDRAM Option Register (D[1:0]/0x483C6)

Table III.3.5.2 Command Hold Time

CMDHLD1

CMDHLD0

Command hold time

(in units of CCLK clocks)

3 clocks

2 clocks

1 clock

0 clocks

CCLK•1/8 (11)

CCLK•1/4 (10)

CCLK•1/2 (01)

CCLK•1/1 (00)

SDCLK (SDCLKD[1:0] setting)

: Settings accepted; ×: Settings prohibited

When initially reset, the command hold time is initialized to 0 clock.

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III-3-12 EPSON S1C33401 TECHNICAL MANUAL

CCLK

SDCLK

CMDHLD[1:0] = 00

CMDHLD[1:0] = 01

CMDHLD[1:0] = 10

CMDHLD[1:0] = 11

(When SDCLK is set as CCLK•1/8)

Command

output

ACT

READA

Command hold time

Figure III.3.5.1 Command Hold Time

Delaying command outputs in the CCLK clock cycle units using this function helps easy timing adjustment

between the SDCLK clock and command output including the printed circuit board conditions. Note that

adjustment of the command hold time does not affect the data receive timing in the C33 ADV.

The values that can be set for the command hold time are subject to limitations depending on the relationship

between CCLK and SDCLK, as shown in Table III.3.5.2.

Bank active mode

SDRAM in the C33 ADV supports read/write commands with and without auto-precharge.

With initial settings, a read/write command (READA/WRITA) with auto-precharge is issued and banks are

precharged internally in SDRAM after the read/write cycle.

Writing 1 to BACTMD (D4/0x483C6) enables bank active mode, so that a read/write command (READ/WRIT)

without auto-precharge can be issued. In this case, banks are not precharged after the read/write cycle and

remain active. Therefore, when accessing the same row address in the same bank, a READ/WRIT command

is issued directly, without issuing an active (ACTV) command. To access a different row address in the same

bank, a precharge (PRE) command is issued, followed by an ACTV command, then a READ/WRIT command.

In bank active mode, therefore, banks are only precharged when a different row address is accessed or SDRAM

refreshed.

∗ BACTMD: SDRAM Bank Active Mode Select Bit in the SDRAM Option Register (D4/0x483C6)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-13

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EBCU

SDRAM timing parameters that can be set by control bits

Before describing how to set each timing parameter, the following diagram shows the relationship between

these parameters and positions in the bus cycle.

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

SDRAM read/write cycle

SDRAM burst read/write cycle

Auto-refresh cycle

ACT

BANK0 BANK1

RASa RASa

RASa CAS

∗1

∗1: SDRAM internal precharge

RASa CAS

0x00xF 0x0 0xF0xF

ACT ACT∗1

READA WRITA

valid valid

CAS latency <1>

Read cycle

Write cycle

tRP <4>

tRP <4> tRP <4>

tRCD <2>

tRCD <2> tRCD <2>

tRCD <2>

tRP <4>

tWR <3>

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

Refresh cycle

tRFC <5>

REFA ACT

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS#2

CAS#3 CAS#4

CAS#1

∗1

0x00xF 0x0 0xF

READA

READ

valid

Write cycle

RAS

ACT

BANK#

RAS

CAS#1 CAS#2 CAS#3 CAS#4

∗1

WRITA

WRIT

valid valid valid valid

0xF

Figure III.3.5.2 SDRAM Timing Parameters

Each timing parameter is detailed below. Be sure to set parameters as suited for specifications of the connected

device.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-14 EPSON S1C33401 TECHNICAL MANUAL

CAS latency (Figure III.3.5.2 <1>)

CAS latency refers to the number of SDCLK clocks until data is output from SDRAM after issuing a read

(READ/READA) command. For the EBCU’s SDRAM interface, CAS latency can be set from 1 to 3 by using

CL[2:0] (D[6:4]/0x483CA).

∗ CL[2:0]: CAS Latency Setting Bits in the SDRAM Mode Register (D[6:4]/0x483CA)

Table III.3.5.3 CAS Latency Settings

CL2

CL1

∗

CAS latency

Reserved

CL0

∗

When initially reset, CAS latency is initialized to 2.

tRCD (RAS-CAS delay time) (Figure III.3.5.2 <2>)

tRCD refers to the time (in units of SDCLK clocks) before a read/write command is issued after an active (ACTV)

command issuance. tRCD can be set from 1 to 4 clocks by using TRCD[1:0] (D[1:0]/0x483C8).

∗ TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8)

Table III.3.5.4 tRCD Settings

TRCD1

TRCD0

tRCD

4 clocks

3 clocks

2 clocks

1 clock

When initially reset, tRCD is initialized to 2 clocks.

tWR (write recovery time) (Figure III.3.5.2 <3>)

tWR refers to the time (in units of SDCLK clocks) until banks are precharged after a write cycle. tWR can be set

from 1 to 4 clocks by using TWR[1:0] (D[5:4]/0x483C8).

∗ TWR[1:0]: tWR Setup Bits in the SDRAM Access Control Register (D[5:4]/0x483C8)

Table III.3.5.5 tWR Settings

TWR1

TWR0

tWR

4 clocks

3 clocks

2 clocks

1 clock

When initially reset, tWR is initialized to 1 clock.

tRP (precharge time) (Figure III.3.5.2 <4>)

tRP refers to the time (in units of SDCLK clocks) until an active (ACTV) command is issued after precharge. tRP

can be set from 1 to 4 clocks by using TRP[1:0] (D[9:8]/0x483C8).

∗ TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8)

Table III.3.5.6 tRP Settings

TRP1

TRP0

tRP

4 clocks

3 clocks

2 clocks

1 clock

When initially reset, tRP is initialized to 2 clocks.

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III

EBCU

tRFC (auto-refresh cycle time) (Figure III.3.5.2 <5>)

tRFC refers to the time (in units of SDCLK clocks) until the next command is issued after issuing an auto-refresh

command. tRFC can be set from 1 to 12 clocks by using TRFC[3:0] (D[15:12]/0x483C8).

∗ TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8)

Table III.3.5.7 tRFC Settings

TRFC3

TRFC2

RFC

Reserved

12 clocks

11 clocks

10 clocks

9 clocks

8 clocks

7 clocks

6 clocks

5 clocks

4 clocks

3 clocks

2 clocks

1 clock

TRFC1

∗

TRFC0

∗

When initially reset, tRFC is initialized to 8 clocks.

Note: The refresh period (RFPOD[7:0] (D[7:0]/0x483C4)) should be longer than tRFC + 1. Otherwise

the bus will be fully occupied by the auto-refresh cycle, so neither read nor write cycles can be

inserted.

∗ RFPOD[7:0]: Refresh Period Setup Bits in the Refresh Period Register (D[7:0]/0x483C4)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-16 EPSON S1C33401 TECHNICAL MANUAL

III.3.6 Control and Operation of SDRAM Interface

III.3.6.1 Initializing SDRAM

To use SDRAM, it must be initialized by following the procedure below after switching power on.

1. Setting SDRAM interface pins

Switch over the pins shared with general-purpose input/output ports or other peripheral functions for SDRAM

use by setting the relevant Port Function Select Register. For details of pin functions and how to switch over,

see Section I.3.3, “Switching Over the Multiplexed Pin Functions.”

2. Setting up the BBCU (for selection of device type)

Select EBCU type (SDRAM) as the device type of the CEx area (x = 4 to 11) to which SDRAM is connected

by writing 1 to CExEBCU (D10/0x48388 + 4•(x - 4)).

∗ CExEBCU: Device Type Select Bit in the CEx Area Configuration Register (D10/0x48388 + 4•(x - 4))

3. Initializing the EBCU registers

Set up the EBCU registers in the following order:

(1) Refresh Period Register (0x483C4)

Set the auto-refresh cycle.

(2) Refresh Counter Register (0x483C2)

Set the initial value of the auto-refresh counter.

(3) SDRAM Option Register (0x483C6)

Set SDRAM size/address-related parameters.

(4) SDRAM Access Control Register (0x483C8)

Set SDRAM access timing parameters.

(5) SDCLK Divide and Refresh Mode Register (0x483C0)

Set SDCLK.

4. Wait after SDRAM power-on

After the power to SDRAM is turned on, the NOP state (#SDCS = 1) must be maintained for a certain time (e.g.,

100 µs) or more. Because this time varies with each SDRAM, refer to the specifications of SDRAM being used.

5. Executing an SDRAM initial sequence

Execute an initial sequence for SDRAM by writing to INISQC (D15) while setting a CAS latency value in

CL[2:0] (D[6:4]) in the SDRAM Mode Register (0x483CA). For other bits in the SDRAM Mode Register

(0x483CA), be sure to set the values specified in the I/O map.

∗ INISQC: Initial Sequence Control Bit in the SDRAM Mode Register (D15/0x483CA)

∗ CL[2:0]: CAS Latency Setting Bits in the SDRAM Mode Register (D[6:4]/0x483CA)

Normally, write 1 to INISQC (D15/0x483CA). In this case, the following commands are sent to SDRAM to

execute the initial sequence:

(1) PALL: All bank precharge command

(2) REFA: Refresh command (8 times)

(3) MRS: Mode register set command

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-17

III

EBCU

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

PALL

0xF 0xF

REFA MRSREFA

8 refresh commands are executed

Initial sequence

valid

Figure III.3.6.1.1 SDRAM Initial Sequence

Writing 0 to INISQC (D15/0x483CA) has a different effect whereby only the MRS command is sent to

SDRAM.

Executing the MRS command completes SDRAM initialization so that SDRAM is ready for read/write

operations.

Note: Do not read data from the SDRAM immediately after the MRS command is executed as it may

cause a malfunction.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-18 EPSON S1C33401 TECHNICAL MANUAL

III.3.6.2 Read/Write Operations

Read cycle

The SDRAM interface of the EBCU supports burst read and single read operations.

However, since the burst length is fixed to 1, 4-word transfer instructions or data bus widths smaller than the

access size (e.g., cache refill or IDMA load instructions) are accommodated by outputting the #SDCAS and

address signals successively.

Read commands with and without auto-precharge are both supported.

For read operation with auto-precharge (when BACTMD (D4/0x483C6) = 0), a READA command is issued

and banks are automatically precharged internally in SDRAM after the read cycle.

∗ BACTMD: SDRAM Bank Active Mode Select Bit in the SDRAM Option Register (D4/0x483C6)

For read operation without auto-precharge (when BACTMD (D4/0x483C6) = 1), a READ command is issued,

but banks are not precharged after the read cycle. Consequently, the banks remain active, and to access the

same row address in the same bank, a READ command is issued directly, without issuing the ACTV (active)

command. To access a different row address in the same bank, a PRE (single bank precharge) command is

issued, followed by the ACTV command, then a READ command. For read operation without precharge, banks

are precharged only when a different row address in the same bank is accessed or SDRAM refreshed.

The following symbols represent the cycles used in SDRAM read timing charts:

Tr: ACTV command cycle

Tcw: ACTV-READ/READA commands interval wait cycle ∗1

Tc: READ/READA command cycle

Tlat: CAS latency cycle

Tp(c): Precharge (SDRAM internal precharge)-ACTV commands interval cycle ∗2

Tidle: Idle cycle

*1: Set by TRCD[1:0] (D[1:0]/0x483C8). A Tcw cycle is inserted when TRCD[1:0] is set to 2 or more clocks.

∗ TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8)

*2: Set by TRP[1:0] (D[9:8]/0x483C8). No commands can be issued to the same SDRAM during this period.

∗ TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8)

The following shows the timings of read cycles.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-19

III

EBCU

Single read cycle with auto-precharge (32-bit data read through 32-bit bus)

Example of single read cycle 1

Auto-precharge: Included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS

∗1

∗1: SDRAM internal precharge

0x00xF

0xF

READA

valid

Tcw

Tlat

Tpc

Tidle

Figure III.3.6.2.1 Single Read Cycle (1)

Example of single read cycle 2

Auto-precharge: Included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS

∗1

∗1: SDRAM internal precharge

0x00xF

0xF

READA

valid

Tcw

Tlat

Tpc

Tidle

Figure III.3.6.2.2 Single Read Cycle (2)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-20 EPSON S1C33401 TECHNICAL MANUAL

Single read cycle with auto-precharge (32-bit data read through 16-bit bus)

Example of single read cycle 3

Auto-precharge: Included

CAS latency: 2

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

CAS#1

CAS#2

∗1

∗1: SDRAM internal precharge

0011

READ READA

valid

Tcw

Tc1

Tc2

Tlat

Tpc

Tidle

Figure III.3.6.2.3 Single Read Cycle (3)

Example of single read cycle 4

Auto-precharge: Included

CAS latency: 1

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

CAS#1

CAS#2

∗1

∗1: SDRAM internal precharge

0011

READ READA

valid

Tcw

Tc1

Tc2

Tlat

Tpc Tidle

Figure III.3.6.2.4 Single Read Cycle (4)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-21

III

EBCU

Single read cycle without auto-precharge (32-bit data read through 32-bit bus)

Example of single read cycle 5

Auto-precharge: Not included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

RAS CAS

0x00xF

0xF

READ

valid

Tcw

Tlat

Tidle

Figure III.3.6.2.5 Single Read Cycle (5)

Example of single read cycle 6

Auto-precharge: Not included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

RAS CAS

0x00xF 0xF

READ

valid

Tcw

Tlat

Tidle

Figure III.3.6.2.6 Single Read Cycle (6)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-22 EPSON S1C33401 TECHNICAL MANUAL

Single read cycle without auto-precharge (32-bit data read through 16-bit bus)

Example of single read cycle 7

Auto-precharge: Not included

CAS latency: 2

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

CAS#1 CAS#2

0011

READ READ

valid

Tcw

Tc1Tc2

Tlat Tlat

Tidle

Figure III.3.6.2.7 Single Read Cycle (7)

Example of single read cycle 8

Auto-precharge: Not included

CAS latency: 1

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

RAS CAS#1

CAS#2

0011 11

READ READ

valid

Tcw

Tc1

Tc2

Tlat

Tidle

Figure III.3.6.2.8 Single Read Cycle (8)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-23

III

EBCU

Successive single read from different banks

Example of single read cycle 9

Auto-precharge: Included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#∗

RAS∗

RAS∗CAS

∗1

∗1: SDRAM internal precharge

0x00xF

READA

valid

Tcw

Tlat

Tpc

Tidle

ACT

BANK#∗

RAS∗

CAS

∗1

0x00xF

0xF

READA

valid

Tcw

Tlat Tlat

Tpc Tidle

Figure III.3.6.2.9 Single Read Cycle (9)

Example of single read cycle 10

Auto-precharge: Included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#∗

RAS∗

CAS

∗1

∗1: SDRAM internal precharge

0x00xF

READA

valid

Tr Tcw

Tlat Tpc

Tidle

ACT

BANK#∗

RAS∗

CAS

∗1

0x00xF

0xF

READA

valid

Tr Tcw

Tlat

Tpc

Tidle

Figure III.3.6.2.10 Single Read Cycle (10)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-24 EPSON S1C33401 TECHNICAL MANUAL

Successive single read from same row address in same bank

Example of single read cycle 11

Auto-precharge: Not included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#1

RAS

CASa

0x00xF

READ

valid

Tcw

Tlat

Tidle Tidle

BANK#1

CASb

0x00xF

0xF

READ

valid

Tlat Tlat Tidle

Figure III.3.6.2.11 Single Read Cycle (11)

Example of single read cycle 12

Auto-precharge: Not included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#1

RAS

RAS CASa

0x00xF

READ

valid

Tcw

Tlat Tidle Tidle

BANK#1

CASb

0x00xF

0xF

READ

valid

Tlat

Tidle

Figure III.3.6.2.12 Single Read Cycle (12)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-25

III

EBCU

Successive single read from different row addresses in same bank

Example of single read cycle 13

Auto-precharge: Not included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#1

RASa

CAS

0x00xF

READ

valid

Tcw

Tlat

Tidle Tp Tpc

ACT

PRE

BANK#1

RASb

RASb CAS

0x0

0xF 0xF

READ

valid

Tcw

Tlat

Tidle

Figure III.3.6.2.13 Single Read Cycle (13)

Example of single read cycle 14

Auto-precharge: Not included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#1

RASa

CAS

0x00xF

READ

valid

Tcw

Tlat

Tidle Tp Tpc

ACT

PRE

BANK#1

RASb

RASb CAS

0x0

0xF

READ

valid

Tcw Tc

Tlat

Tidle

Figure III.3.6.2.14 Single Read Cycle (14)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-26 EPSON S1C33401 TECHNICAL MANUAL

Burst read cycle with auto-precharge

Example of burst read cycle 1

(For cache refill and loading from IDMA instruction)

Auto-precharge: Included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS#2

CAS#3 CAS#4

CAS#1

∗1

∗1: SDRAM internal precharge

0x00xF

0xF

READA

READ

valid

Tcw

Tc2

Tc3

Tc4

Tlat

Tpc

Tidle

RAS

Figure III.3.6.2.15 Burst Read Cycle (1)

Example of burst read cycle 2

(For cache refill and loading from IDMA instruction)

Auto-precharge: Included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS#2

CAS#3

CAS#4

CAS#1

∗1

∗1: SDRAM internal precharge

0x00xF

0xF

READA

READ

valid

Tcw

Tc1

Tc2

Tc3Tc

4Tlat

Tpc

Tidle

RAS

Figure III.3.6.2.16 Burst Read Cycle (2)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-27

III

EBCU

Burst read cycle without auto-precharge

Example of burst read cycle 3

(For cache refill and loading from IDMA instruction)

Auto-precharge: Not included

CAS latency: 2

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS#2

CAS#3

CAS#4

CAS#1

∗1: SDRAM internal precharge

0x00xF

0xF

READ

valid

Tcw

Tc1

Tc2

Tc3Tc

4Tlat

Tlat

Tidle

RAS

Figure III.3.6.2.17 Burst Read Cycle (3)

Example of burst read cycle 4

(For cache refill and loading from IDMA instruction)

Auto-precharge: Not included

CAS latency: 1

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS#2

CAS#3 CAS#4

CAS#1

∗1: SDRAM internal precharge

0x00xF

0xF

READ

valid

Tcw

Tc1

Tc2

4Tlat Tidle

RAS

Figure III.3.6.2.18 Burst Read Cycle (4)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-28 EPSON S1C33401 TECHNICAL MANUAL

Write cycle

The SDRAM interface of the EBCU supports burst write and single write operations.

However, since the burst length is fixed to 1, 4-word transfer instructions or data bus widths smaller than the

access size (e.g., cache write-back or IDMA store instructions) are accommodated by outputting the #SDCAS

and address signals successively.

Write commands with and without auto-precharge are both supported.

For write operation with auto-precharge (when BACTMD (D4/0x483C6) = 0), a WRITA command is issued

and banks are automatically precharged internally in SDRAM after the write cycle.

For write operation without auto-precharge (when BACTMD (D4/0x483C6) = 1), a WRIT command is issued,

but banks are not precharged after the write cycle. Consequently, the banks remain active, and to access the

same row address in the same bank, a WRIT command is issued directly, without issuing the ACTV (active)

command.

To access a different row address in the same bank, a PRE (single bank precharge) command is issued, followed

by the ACTV command, then a WRIT command. For write operation without precharge, banks are precharged

only when a different row address in the same bank is accessed or SDRAM refreshed.

The following symbols represent the cycles used in SDRAM write timing charts:

Tr: ACTV command cycle

Tcw: ACTV-WRIT/WRITA commands interval wait cycle ∗1

Tc: WRIT/WRITA command cycle

Twrc: Write recovery cycle ∗2

Tp(c): Precharge (SDRAM internal precharge)-ACTV commands interval cycle ∗3

Tidle: Idle cycle

∗1: Set by TRCD[1:0] (D[1:0]/0x483C8). A Tcw cycle is inserted when TRCD[1:0] is set to 2 or more clocks.

∗ TRCD[1:0]: tRCD Setup Bits in the SDRAM Access Control Register (D[1:0]/0x483C8)

∗2: Set by TWR[1:0] (D[5:4]/0x483C8). No commands can be issued to the same bank during this period.

∗ TWR[1:0]: tWR Setup Bits in the SDRAM Access Control Register (D[5:4]/0x483C8)

∗3: Set by TRP[1:0] (D[9:8]/0x483C8). No commands can be issued to the same SDRAM during this period.

∗ TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8)

The following shows the timings of write cycles.

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-29

III

EBCU

Single write cycle with auto-precharge (32-bit data write through 32-bit bus)

Example of single write cycle 1

Auto-precharge: Included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

CAS

∗1

∗1: SDRAM internal precharge

0x00xF

0xF

WRIT

valid

Tcw

Twrc

Tpc

Tidle

Figure III.3.6.2.19 Single Write Cycle (1)

Single write cycle with auto-precharge (32-bit data write through 16-bit bus)

Example of single write cycle 2

Auto-precharge: Included

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

CAS#1

CAS#2

∗1

∗1: SDRAM internal precharge

0011

WRIT

WRITA

valid

Tcw

Tc1

Tc2

Twrc

Tpc Tidle

Figure III.3.6.2.20 Single Write Cycle (2)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-30 EPSON S1C33401 TECHNICAL MANUAL

Single write cycle without auto-precharge (32-bit data write through 32-bit bus)

Example of single write cycle 3

Auto-precharge: Not included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#

RAS

RAS CAS

0x00xF 0xF

WRIT

valid

Tcw

Twrc

Tidle

Figure III.3.6.2.21 Single Write Cycle (3)

Single write cycle without auto-precharge (32-bit data write through 16-bit bus)

Example of single write cycle 4

Auto-precharge: Not included

Data bus width: 16 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[1:0]

D[15:0]

ACT

BANK#

RAS

0011

WRIT

Tcw

Tc1

Tc2

Twrc

Tidle

CAS#1

CAS#2

valid

Figure III.3.6.2.22 Single Write Cycle (4)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

S1C33401 TECHNICAL MANUAL EPSON III-3-31

III

EBCU

Successive single write to different banks

Example of single write cycle 5

(For successive single write operations)

Auto-precharge: Included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#∗

RAS∗

RAS∗CAS

∗1

∗1: SDRAM internal precharge

0x00xF

WRITA

valid

Tr Tcw

Twrc Tpc

Tidle

ACT

BANK#∗

RAS∗

RAS∗CAS

∗1

0x00xF

0xF

WRIT

valid

Tr Tcw Tc

Twrc Tpc

Tidle

Figure III.3.6.2.23 Single Write Cycle (5)

Successive single write to same row address in same bank

Example of single write cycle 6

Auto-precharge: Not included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#0

RAS

RAS CASa CASb

0x0 0xF 0x00xF

0xF

WRIT

valid

Tcw Tc

Twrc Tc

Twrc

Tidle

Figure III.3.6.2.24 Single Write Cycle (6)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-32 EPSON S1C33401 TECHNICAL MANUAL

Successive single write to different row addresses in same bank

Example of single write cycle 7

Auto-precharge: Not included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#1

RASa

CAS

PRE

0x00xF

WRIT

valid

Tcw

Twrc

Tpc

ACT

BANK#1

RASb

CAS

0x00xF

0xF

WRIT

valid

Tr Tcw

Tc Twrc Tidle

Figure III.3.6.2.25 Single Write Cycle (7)

Burst write cycle with auto-precharge

Example of burst write cycle 1

(For cache write-back and store from IDMA instruction)

Auto-precharge: Included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM0

D[7:0]

ACT

BANK#

RAS

CAS#1 CAS#2 CAS#3 CAS#4

∗1

∗1: SDRAM internal precharge

WRITA

WRIT

Tr Tcw Tc1Tc2Tc3Tc4Twrc Tpc Tidle

valid valid valid valid

Figure III.3.6.2.26 Burst Write Cycle (1)

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EBCU

Burst write cycle without auto-precharge

Example of burst write cycle 2

(For cache write-back and store from IDMA instruction)

Auto-precharge: Not included

Data bus width: 32 bits

Access: 32-bit data

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM0

D[7:0]

ACT

BANK#

RAS

CAS#1 CAS#2 CAS#3 CAS#4

WRIT

Tr Tcw Tc1Tc2Tc3Tc4Twrc Tidle

valid valid valid valid

Figure III.3.6.2.27 Burst Write Cycle (2)

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III-3-34 EPSON S1C33401 TECHNICAL MANUAL

Combination cycle

The following shows the timing of a read/write combination cycle.

Example of read/write cycle with precharge

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#0

RAS∗

RAS∗CAS

∗1

∗1: SDRAM internal precharge

0x00xF

READA

valid

Bank 0 read cycle Bank 0 read cycle

Bank 1 write cycle

Tcw Tc Tlat

Tlat

Tpc

Tidle

ACT

BANK#1

RAS∗

CAS

∗1

0x00xF

WRITA

valid

Tcw

Twrc

Tpc

Tidle

ACT

BANK#0

RAS∗

CAS

∗1

0x0

0xF

READA

valid

Tr Tcw

Tlat

Tpc

Tidle

0xF

Figure III.3.6.2.28 Read/Write Cycle with Precharge

Example of read/write cycle without precharge

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

BS[1:0]

A10/AP

A[∗:0]

DQM[3:0]

D[31:0]

ACT

BANK#0

RASa

RASa CAS

0x00xF

READ

valid

Tcw

Tlat Tlat

Tidle

BANK#1

CAS

0x0

READ

valid

Tlat

Tidle

ACT

BANK#1

RASb

RASb CAS

0x00xF 0xF

WRIT

valid

Tcw Tc

Twrc

PRE

Tpc

ACT

BANK#0

RASc

RASc CAS

0x00xF 0xF

WRIT

valid

Tr Tcw

Twrc

Tidle

Bank 0 read cycle

Bank 0 write cycle

Bank 1 write cycle

Same row address in bank 1

Another row address in bank 0

Bank 1 read cycle

Figure III.3.6.2.29 Read/Write Cycle without Precharge

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EBCU

III.3.6.3 SDRAM Refresh

The EBCU contains an SDRAM refresh controller that supports auto-refresh and self-refresh operations. Setting

RFSH (D8/0x483C0) to 1 enables the SDRAM refresh function. Moreover, RFSHMD (D9/0x483C0) selects

whether to perform auto-refresh (RFSHMD = 0) or self-refresh (RFSHMD = 1).

∗ RFSH: Refresh Enable Bit in the SDCLK Divide and Refresh Mode Register (D8/0x483C0)

∗ RFSHMD: Refresh Mode Select Bit in the SDCLK Divide and Refresh Mode Register (D9/0x483C0)

Auto-refresh

Auto-refresh is the function used to refresh SDRAM by periodically issuing PALL (all bank precharge) and

REFA (auto refresh) commands. The refresh controller incorporates an 8-bit refresh counter and a register to set

a refresh period, thus enabling programmable refresh period settings.

Setting up auto-refresh

To perform auto-refresh, the following settings are required:

1. Setting the refresh counter

Set RCKS (D10/0x483C0) to select the clock with which to run the refresh counter.

RCKS = 1: SDCLK•1/16

RCKS = 0: SDCLK•1/1 (default)

∗ RCKS: Refresh Counter Clock Select Bit in the SDCLK Divide and Refresh Mode Register (D10/0x483C0)

As an approximate guide for clock selection, select SDCLK•1/1 when SDCLK is 10 MHz or less; select

SDCLK•1/16 when SDCLK exceeds 10 MHz.

2. Setting a refresh period

Set a refresh period (value to compare with the refresh counter) in RFPOD[7:0] (D[7:0]/0x483C4).

∗ RFPOD[7:0]: Refresh Period Setup Bits in the Refresh Period Register (D[7:0]/0x483C4)

The set value of RFPOD[7:0] (D[7:0]/0x483C4) is calculated as follows:

RFPOD[7:0] = refresh period (µs) ÷ refresh counter clock cycle (µs)

For example, when the maximum refresh period of SDRAM used is 64 ms and the number of refresh cycles

(row address size) is 4,096, then one cycle (64 ms/4,096) equals 15.625 µs. When the refresh counter clock

frequency is 10 MHz, the clock period is 0.1 µs.

RFPOD[7:0] = 15.625 (µs) ÷ 0.1 (µs) = 156.25

Therefore, the value to be set in RFPOD[7:0] (D[7:0]/0x483C4) is 156 or less. To ensure that the refresh

requirements of SDRAM are always met, subtract a margin from the calculated value when setting a refresh

period in the register.

3. Starting an auto-refresh cycle

Set RFSHMD (D9/0x483C0) to 0 and RFSH (D8/0x483C0) to 1.

Auto-refresh operation

The following describes the operation of the SDRAM refresh controller.

1. When values 0 and 1 are written to RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0), respectively, the

controller starts an auto-refresh cycle.

2. The 8-bit refresh counter starts counting synchronously with the refresh counter clock set by RCKS (D10/

0x483C0). Because the content of the refresh counter is not cleared at this time, the counter starts counting

from the current value (initially set to 0).

3. The refresh counter value is compared with the value of RFPOD[7:0] (D[7:0]/0x483C4) and when both

match, the controller issues PALL and REFA commands to refresh SDRAM. The refresh counter is cleared

at this time, and restarts counting from 0.

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III-3-36 EPSON S1C33401 TECHNICAL MANUAL

4. If the refresh counter overflows before its value matches that of RFPOD[7:0] (D[7:0]/0x483C4) as when it

starts counting from a value larger than that of RFPOD[7:0] (D[7:0]/0x483C4), the counter is simply reset

to 0 and starts counting all over again. In this case, SDRAM is not refreshed.

5. When value 0 is written to RFSH (D8/0x483C0) or value 1 is written to RFSHMD (D9/0x483C0), the

refresh counter stops and the auto-refresh cycle is aborted.

Reading and initializing the refresh counter

The value of the refresh counter can be read out from RFCTR[7:0] (D[7:0]/0x483C2). Moreover, the refresh

counter can be set to any desired value by writing to RFCTR[7:0] (D[7:0]/0x483C2). In this way, the first

period after starting an auto-refresh cycle can be reduced to any desired length. When refresh commands must

be sent to SDRAM immediately, set the smallest value approximating that of RFPOD[7:0] (D[7:0]/0x483C4) in

RFCTR[7:0] (D[7:0]/0x483C2) before starting auto-refresh.

∗ RFCTR[7:0]: Refresh Counter Bits in the Refresh Counter Register (D[7:0]/0x483C2)

Note: Before writing the initial value to RFCTR[7:0] (D[7:0]/0x483C2), be sure to stop the counter by

writing 0 to RFSH (D8/0x483C0). Otherwise, values may not be correctly written to the count

Timing chart

Figure III.3.6.3.1 shows the timing of an auto-refresh cycle. The following symbols represent the cycles used in

timing charts:

Tp(c): Precharge-ACTV/REFA commands interval cycle ∗1

Trfa: REFA command cycle

Taw: REFA-ACTV/REFA commands interval cycle ∗2

∗1: Set by TRP[1:0] (D[9:8]/0x483C8).

∗ TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8)

∗2: Set by TRFC[3:0] (D[15:12]/0x483C8).

∗ TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8)

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

PAL/PRE REFA

Tpc

Trfa

Taw

Figure III.3.6.3.1 Auto-Refresh Cycle

Self-refresh

Self-refresh is a kind of standby mode where the refresh timing and refresh address are generated internally in

SDRAM. When self-refresh mode is entered, SDCLK output to SDRAM can be turned off, helping to reduce

the amount of current consumed on the chip. Select this mode when SDRAM is to be placed in a standby state.

When the chip is to be set in HALT2 or SLEEP mode with the clock turned off, always be sure to select self-

refresh mode for SDRAM.

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Starting self-refresh operation

To perform self-refresh, the following settings are required:

1. Enabling self-refresh

Set RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0) both to 1.

2. Issuing a self-refresh command

Write 1 to SELF (D0/0x483CC).

∗ SELF: Self-refresh Entry/Exit Control Bit in the Self-refresh Control Register (D0/0x483CC)

As a result, the SDCKE signal goes low (= 0) and SDRAM enters self-refresh mode. SDRAM cannot be

accessed while in self-refresh mode.

Stopping self-refresh

Follow the procedure below to disable self-refresh. This control must be executed in other than SDRAM.

1. Turning SDCLK output on

If SDCLK output to SDRAM was turned off during self-refresh, turn it back on again.

2. Stopping self-refresh

Write 0 to SELF (D0/0x483CC).

3. Starting auto-refresh

Start auto-refresh by following the procedure above. For the initial auto-refresh to be performed after

stopping self-refresh, set the smallest value approximating that of RFPOD[7:0] (D[7:0]/0x483C4) in

RFCTR[7:0] (D[7:0]/0x483C2) to ensure that SDRAM will be refreshed immediately.

Note that command issuance to SDRAM is disabled, however, for the interval time set by TRFC[3:0]

(D[15:12]/0x483C8) after self-refresh has stopped.

Note: Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF

(D0/0x483CC) to 1 when already 1 or setting 0 when already 0 is prohibited because such bit

manipulation may cause the SDRAM controller to operate erratically.

Timing chart

Figure III.3.6.3.2 shows the timing of a self-refresh cycle. The following symbols represent the cycles used in

timing charts:

Tp(c): Precharge-ACTV/REFA commands interval cycle ∗1

Tref: REFS command cycle

Taw: REFA-ACTV/REFA commands interval cycle ∗2

∗1: Set by TRP[1:0] (D[9:8]/0x483C8).

∗ TRP[1:0]: tRP Setup Bits in the SDRAM Access Control Register (D[9:8]/0x483C8)

∗2: Set by TRFC[3:0] (D[15:12]/0x483C8).

∗ TRFC[3:0]: tRFC Setup Bits in the SDRAM Access Control Register (D[15:12]/0x483C8)

SDCLK

Command

SDCKE

#SDCS

#SDRAS

#SDCAS

#SDWE

Tpc

Tref

Idle

Texit

Taw

Figure III.3.6.3.2 Self-Refresh Cycle

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III-3-38 EPSON S1C33401 TECHNICAL MANUAL

III.3.6.4 SDRAM Refresh Request when External Bus is Released

Although the BBCU and EBCU (SDRAMC) normally manage external buses in the C33 ADV, the C33 ADV

allows bus control to be released to external bus masters. For details, see Section III.2.10, “External Bus Requests

and Release of Bus Control.”

The following describes how SDRAM refresh requests are processed when bus control is released to external bus

masters.

Refresh requests from the SDRAM refresh controller have higher priority than requests from external bus masters

for bus control. For this reason, if a refresh request is made while an external bus master has bus control, the

external bus master must release bus control. The following shows the bus control release sequence followed at

such time.

1. A refresh request is made.

2. The EBCU drives the #BUSGET pin low one clock after a refresh request is generated by the SDRAM refresh

controller.

3. The external bus master with bus control always monitors the #BUSGET pin status, so that when #BUSGET is

detected low, the bus master terminates the bus cycle in progress and drives the #BUSREQ pin back high.

4. The EBCU returns the #BUSGET pin high two cycles after detecting that the #BUSREQ pin is high.

5. For the external bus master to request bus control again, it must confirm that the #BUSGET pin is high before

sending a request to the BBCU/EBCU.

CCLK

SDRAM

refresh request

#BUSGET

#BUSREQ

#BUSACK

1 cycle

2 cycles

1 cycle

Sync

SDRAM refresh request

generated

Bus release request to

external bus master

The external bus

master terminates the

bus cycle being executed.

Bus control

being released

SDRAM refreshThe external bus master

controls bus cycles.

Figure III.3.6.4.1 External Bus Release Timing

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III.3.7 SDRAM Commands

The SDRAM is controlled by commands that are comprised of a combination of high or low logic level signals.

Table III.3.7.1 lists the commands output by the SDRAM controller.

Table III.3.7.1 List of the Supported SDRAM Commands

Function

Deselect

No Operation

Bank Active

Read without Auto-Precharge

Read with Auto-Precharge

Write without Auto-Precharge

Write with Auto-Precharge

Single Bank Precharge

Precharge All

Auto Refresh

Self Refresh

Mode Register Set

Symbol

DESL

NOP

ACTV

READ

READA

WRIT

WRITA

PRE

PALL

REFA

REFS

MRS

SDCKE

BA[1:0]

A10

Axx

Row

Column

#SDCS

#SDRAS

#SDCAS

#SDWE

Command

Pins

V = valid, X = don’t care, L = low level, H = high level

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-40 EPSON S1C33401 TECHNICAL MANUAL

III.3.8 Control Register Details

Table III.3.8.1 EBCU Register List

Address

0x000483C0

0x000483C2

0x000483C4

0x000483C6

0x000483C8

0x000483CA

0x000483CC

Function

Sets SDCLK and refresh mode.

Refresh counter

Sets refresh period.

Sets SDRAM.

Sets SDRAM access timing parameters.

Sets SDRAM operation mode.

Controls self-refresh.

SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF)

Refresh Counter Register (pEBCU_RFTIM)

Refresh Period Register (pEBCU_RFPOD)

SDRAM Option Register (pEBCU_SDOPT)

SDRAM Access Control Register (pEBCU_SDACR)

SDRAM Mode Register (pEBCU_SDMOD)

Self-refresh Control Register (pEBCU_SLFEX)

Size

The following describes each EBCU control register.

The EBCU control registers are mapped to the 16-bit device area at addresses 0x483C0 to 0x483CC, and can be

accessed in units of half-words or bytes.

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EBCU

0x483C0: SDCLK Divide and Refresh Mode Register (pEBCU_DIVRF)

Name

Address

–

RCKS

RFSHMD

RFSH

–

SDCLKS

–

SDCLKD1

SDCLKD0

D15–11

D10

D7–5

D3–2

reserved

Refresh counter clock select

Refresh mode select

Refresh enable

reserved

SDCLK output during idle

reserved

SDCLK setup

(CCLK division ratio)

–

R/W

–

R/W

–

R/W

0 when being read.

1Enabled 0Disabled

00483C0

(HW)

SDCLKD[1:0] SDCLK

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

SDCLK divide

and refresh

mode

(pEBCU_DIVRF)

–

SDCLK•1/16

0SDCLK•1/1

1Self-refresh 0

Auto-refresh

1Stopped 0Output

D[15:11] Reserved

D10 RCKS: Refresh Counter Clock Select Bit

This bit sets the count clock for the refresh counter (0x483C2).

1 (R/W): SDCLK•1/16

0 (R/W): SDCLK•1/1 (default)

As an approximate guide for clock selection, select SDCLK•1/1 when SDCLK is 10 MHz or less; select

SDCLK•1/16 when SDCLK exceeds 10 MHz.

D9 RFSHMD: Refresh Mode Select Bit

This bit selects refresh mode.

1 (R/W): Self-refresh

0 (R/W): Auto-refresh (default)

Select auto-refresh while using SDRAM. To execute auto-refresh, set a refresh period in the Refresh

Period Register (0x483C4) and set this bit to 0 and RFSH (D8) to 1, respectively.

Before the chip can be set to HALT2 or SLEEP mode (where SDCLK output is turned off), SDRAM

must be set to self-refresh mode. To select self-refresh mode for SDRAM, set this bit and RFSH (D8)

both to 1 and write 1 to SELF (D0/0x483CC).

D8 RFSH: Refresh Enable Bit

This bit enables the refresh function.

1 (R/W): Enable

0 (R/W): Disable (default)

Setting this bit to 1 enables the SDRAM refresh controller, so that the refresh operation set by

RFSHMD (D9) can be controlled.

D[7:5] Reserved

D4 SDCLKS: SDCLK Output Control Bit

This bit selects whether to output SDCLK to SDRAM when it is not being accessed.

1 (R/W): Do not output

0 (R/W): Output (default)

D[3:2] Reserved

D[1:0] SDCLKD[1:0]: SDCLK Setup Bits

SDCLK is the clock for SDRAM, and is generated from the core system clock (CCLK) by dividing it

by a given number. Use SDCLKD[1:0] to select this divide-by ratio.

Table III.3.8.2 Selection of SDCLK

SDCLKD1

SDCLKD0

SDCLK frequency

CCLK•1/8

CCLK•1/4

CCLK•1/2

CCLK•1/1

(Default: 0b11 = CCLK•1/8)

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0x483C2: Refresh Counter Register (pEBCU_RFTIM)

Name

Address

–

0 to 0xFF

–

RFCTR7

RFCTR6

RFCTR5

RFCTR4

RFCTR3

RFCTR2

RFCTR1

RFCTR0

D15–8

reserved

Refresh counter

–

R/W

0 when being read.

00483C2

(HW)

Refresh

counter

(pEBCU_RFTIM)

D[15:8] Reserved

D[7:0] RFCTR[7:0]: Refresh Counter Bits

These bits allow the refresh counter value to be read and its initial value set. (Default: 0x00)

When an auto-refresh cycle is started by writing 0 to RFSHMD (D9/0x483C0) and 1 to RFSH (D8/

0x483C0), the refresh counter starts counting synchronously with the refresh counter clock set by

RCKS (D10/0x483C0).

When the refresh counter value matches the value of RFPOD[7:0] (D[7:0]/0x483C4), the SDRAM

controller issues PALL and REFA commands to refresh SDRAM. The refresh counter is cleared at this

time, and restarts counting from 0.

If the refresh counter overflows before its value matches that of RFPOD[7:0] (D[7:0]/0x483C4) as

when counting is started from a value greater than that of RFPOD[7:0] (D[7:0]/0x483C4), the counter

is simply reset to 0 and starts counting all over again. In this case, SDRAM is not refreshed.

When value 0 is written to RFSH (D8/0x483C0) or value 1 is written to RFSHMD (D9/0x483C0), the

refresh counter stops and the auto-refresh cycle is aborted.

If the first refresh period must be reduced, set the smallest value approximating that of RFPOD[7:0]

(D[7:0]/0x483C4) in this register before starting auto-refresh.

Note: Before writing the initial value to RFCTR[7:0] (D[7:0]/0x483C2), be sure to stop the counter

by writing 0 to RFSH (D8/0x483C0). Values may not be correctly written to the count register

while the counter is operating.

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EBCU

0x483C4: Refresh Period Register (pEBCU_RFPOD)

Name

Address

–

0 to 0xFF

–

RFPOD7

RFPOD6

RFPOD5

RFPOD4

RFPOD3

RFPOD2

RFPOD1

RFPOD0

D15–8

reserved

Refresh period setup

(number of cycles)

–

R/W

0 when being read.

00483C4

(HW)

Refresh period

(pEBCU_RFPOD)

D[15:8] Reserved

D[7:0] RFPOD[7:0]: Refresh Period Setup Bits

These bits set a refresh period. (Default: 0x00)

The value set in these bits is compared with the refresh counter and when both values match, refresh

commands are sent to SDRAM. The refresh counter is cleared at this time, and restarts counting from 0.

See the description of the Refresh Counter Register (0x483C2) for details.

Calculate the set value (maximum value) from the equation below and subtract a margin from the

calculated value before writing a refresh period to this register.

RFPOD[7:0] = refresh period (µs) ÷ refresh counter clock cycle (µs)

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0x483C6: SDRAM Option Register (pEBCU_SDOPT)

Name

Address

BIG

–

DVSIZ1

DVSIZ0

RAW1

RAW0

CAW1

CAW0

–

BACTMD

–

CMDHLD1

CMDHLD0

D15

D14

D13

D12

D11

D10

D7–5

D3–2

Endian mode select

reserved

SDRAM device size select

Row address width

Column address width

reserved

SDRAM bank active mode select

reserved

Command hold time setup

(number of CCLK clocks)

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

00483C6

(HW)

DVSIZ[1:0] Size

32 bits

16 bits (upper)

16 bits (lower)

reserved

RAW[1:0] Size

14 bits (16K)

13 bits (8K)

12 bits (4K)

11 bits (2K)

CMDHLD[1:0]

# of clocks

3 clocks

2 clocks

1 clock

0 clocks

SDRAM option

(pEBCU_SDOPT)

–

1Big endian 0

Little endian

1Full bank 0No bank

CAW[1:0] Size

11 bits (2K)

10 bits (1K)

9 bits (512)

8 bits (256)

D15 BIG: Endian Mode Select Bit

This bit selects endian mode in which to access SDRAM.

1 (R/W): Big endian

0 (R/W): Little endian (default)

Note that endian mode selected for the same area by the BBCU register is not effective.

D14 Reserved

D[13:12] DVSIZ[1:0]: SDRAM Device Size Select Bits

These bits select the device size (data bus width) of SDRAM.

Table III.3.8.3 Selection of SDRAM Device Size

DVSIZ1

DVSIZ0

Device size

32 bits

16 bits (16 high-order data bus bits)

16 bits (16 low-order data bus bits)

Settings prohibited

Connected data bus

D[31:0] (Note)

D[31:16] (Note)

D[15:0]

–

(Default: 0b01 = 16 bits (16 low-order data bus bits))

Note: For C33 ADV models with 16 external data bus pins, D[15:0], neither “32 bits” nor “16 bits (16

high-order data bus bits)” can be selected as the device size of external SDRAM.

D[11:10] RAW[1:0]: Row Address Width Bits

These bits set the row address width.

Table III.3.8.4 Row Address Width Settings

RAW1

RAW0

Row address width

14 bits (16K)

13 bits (8K)

12 bits (4K)

11 bits (2K)

(Default: 0b01 = 12 bits)

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EBCU

D[9:8] CAW[1:0]: Column Address Width Bits

These bits set the column address width.

Table III.3.8.5 Column Address Width Settings

CAW1

CAW0

Column address width

11 bits (2K)

10 bits (1K)

9 bits (512)

8 bits (256)

(Default: 0b01 = 9 bits)

D[7:5] Reserved

D4 BACTMD: SDRAM Bank Active Mode Select Bit

This bit selects bank active mode (whether to perform auto-precharge).

1 (R/W): Without auto-precharge

0 (R/W): With auto-precharge (default)

Setting this bit to 0 issues a read/write command with auto-precharge (READA/WRITA), so that banks

are precharged internally in SDRAM after the read/write cycle.

Setting this bit to 1 issues a read/write command without auto-precharge (READ/WRIT). In this case,

banks are not precharged after the read/write cycle and remain active. Therefore, when accessing the

same row address in the same bank, a READ/WRIT command is issued directly, without issuing an

active (ACTV) command. When accessing a different row address in the same bank, a precharge (PRE)

command is issued, followed by an ACTV command, then a READ/WRIT command.

D[3:2] Reserved

D[1:0] CMDHLD[1:0]: Command Hold Time Setup Bits

These bits set the command hold time in units of CCLK clocks. The command hold time refers to the

time from the rise of SDCLK after command output to when command output is negated. The selection

of values here is subject to limitations imposed by the settings of SDCLKD[1:0] (D[1:0]/0x483C0).

Table III.3.8.6 Command Hold Time

CMDHLD1

CMDHLD0

Command hold time

(in units of CCLK clocks)

3 clocks

2 clocks

1 clock

0 clocks

CCLK•1/8 (11)

CCLK•1/4 (10)

CCLK•1/2 (01)

CCLK•1/1 (00)

SDCLK (SDCLKD[1:0] setting)

: Settings accepted; ×: Settings prohibited

(Default: 0b00 = 0 clocks)

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III-3-46 EPSON S1C33401 TECHNICAL MANUAL

0x483C8: SDRAM Access Control Register (pEBCU_SDACR)

Name

Address

TRFC3

TRFC2

TRFC1

TRFC0

–

TRP1

TRP0

–

TWR1

TWR0

–

TRCD1

TRCD0

D15

D14

D13

D12

D11–10

D7–6

D3–2

tRFC (auto-refresh cycle time)

setup (number of SDCLK clocks)

reserved

tRP (precharge time) setup

(number of SDCLK clocks)

reserved

tWR (write-recovery time) setup

(number of SDCLK clocks)

reserved

tRCD (RAS-CAS delay time) setup

(number of SDCLK clocks)

–

R/W

–

R/W

–

R/W

–

R/W

0 when being read.

00483C8

(HW) 11∗∗

1011

0111

0000

TRFC[3:0] # of clocks

reserved

12 clocks

8 clocks

1 clock

TRP[1:0] # of clocks

4 clocks

3 clocks

2 clocks

1 clock

SDRAM access

control

(pEBCU_SDACR)

–

TWR[1:0] # of clocks

4 clocks

3 clocks

2 clocks

1 clock

–

TRCD[1:0] # of clocks

4 clocks

3 clocks

2 clocks

1 clock

–

D[15:12] TRFC[3:0]: tRFC Setup Bits

These bits set tRFC (auto-refresh cycle time).

tRFC refers to the time (in units of SDCLK clocks) until the next command is issued after issuing an

auto-refresh command.

Table III.3.8.7 tRFC Settings

TRFC3

TRFC2

RFC

Reserved

12 clocks

11 clocks

10 clocks

9 clocks

8 clocks

7 clocks

6 clocks

5 clocks

4 clocks

3 clocks

2 clocks

1 clock

TRFC1

∗

TRFC0

∗

(Default: 0b0111 = 8 clocks)

D[11:10] Reserved

D[9:8] TRP[1:0]: tRP Setup Bits

These bits set tRP (precharge time).

tRP refers to the time (in units of SDCLK clocks) until the active command is issued after precharge.

Table III.3.8.8 tRP Settings

TRP1

TRP0

tRP

4 clocks

3 clocks

2 clocks

1 clock

(Default: 0b01 = 2 clocks)

D[7:6] Reserved

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EBCU

D[5:4] TWR[1:0]: tWR Setup Bits

These bits set tWR (write recovery time).

tWR refers to the time (in units of SDCLK clocks) until banks are precharged after a write cycle.

Table III.3.8.9 tWR Settings

TWR1

TWR0

tWR

4 clocks

3 clocks

2 clocks

1 clock

(Default: 0b00 = 1 clock)

D[3:2] Reserved

D[1:0] TRCD[1:0]: tRCD Setup Bits

These bits set tRCD (RAS-CAS delay time).

tRCD refers to the time (in units of SDCLK clocks) before a read/write command is issued after issuing

the active command.

Table III.3.8.10 tRCD Settings

TRCD1

TRCD0

tRCD

4 clocks

3 clocks

2 clocks

1 clock

(Default: 0b01 = 2 clocks)

III C33 ADV BUS BLOCK: EXTENDED BUS CONTROL UNIT (EBCU)

III-3-48 EPSON S1C33401 TECHNICAL MANUAL

0x483CA: SDRAM Mode Register (pEBCU_SDMOD)

Name

Address

INISQC

–

WMODE

–

CL2

CL1

CL0

BL2

BL1

BL0

D15

D14–10

D8–7

Initial sequence control

reserved

CAS latency

reserved

–

R/W

–

R/W

0 when being read.

00483CA

(HW)

1∗∗

011

010

001

000

CL[2:0] CAS latency

reserved

SDRAM mode

(pEBCU_SDMOD)

–

Fixed at 1

Fixed at 0

Fixed at 000

Init. sequence

MRS only

D15 INISQC: Initial Sequence Control Bit

This bit executes the initial sequence after SDRAM power is turned on.

1 (R/W): Execute initial sequence

0 (R/W): Only execute MRS command (default)

After turning SDRAM power on, normally maintain the NOP state (#SDCS = 1) for a certain time (e.g.,

100 µs) or more before writing 1 to this bit to execute the initial sequence. When this bit is set to 1, the

following commands are sent to SDRAM:

(1) PALL: All bank precharge command

(2) REFA: Refresh command (8 times)

(3) MRS: Mode register set command

When the MRS command is executed, SDRAM initialization is completed to ready SDRAM for read/

write operations.

Writing 0 to this bit has a different effect, whereby only the MRS command is sent to SDRAM.

D[14:10] Reserved

D9 WMODE: Reserved

Do not set this bit to other than 1.

D[8:7] Reserved

D[6:4] CL[2:0]: CAS Latency Setting Bits

These bits set CAS latency.

CAS latency refers to the number of SDCLK clocks until data is output from SDRAM after issuing a

read (READ/READA) command.

Table III.3.8.11 CAS Latency Settings

CL2

CL1

∗

CAS latency

Reserved

CL0

∗

(Default: 0b010 = 2 clocks)

D3 BT: Reserved

Do not set this bit to other than 0.

D[2:0] BL[2:0]: Reserved

Do not set these bits to other than 0b000.

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EBCU

0x483CC: Self-refresh Control Register (pEBCU_SLFEX)

Name

Address

–

SELF

D15–1

reserved

Self-refresh entry/exit control

–

R/W

0 when being read.

Do not set 1 to 1 or 0

to 0.

00483CC

(HW)

Self-refresh

control

(pEBCU_SLFEX)

–

1Entry 0

Exit

D[15:1] Reserved

D0 SELF: Self-refresh Entry/Exit Control Bit

This bit controls the entry into and exit from self-refresh mode.

1 (R/W): Start self-refresh

0 (R/W): Stop self-refresh (default)

To place SDRAM in self-refresh mode, set RFSHMD (D9/0x483C0) and RFSH (D8/0x483C0) both to

1 to enable refresh command issuance, then write 1 to this bit.

As a result, the SDCKE signal goes low (= 0) and SDRAM enters self-refresh mode. SDRAM cannot

be accessed while in self-refresh mode.

To stop self-refresh, write 0 to this bit.

Start auto-refresh after stopping self-refresh.

Note that command issuance to SDRAM is disabled, however, for the interval time set by TRFC[3:0]

(D[15:12]/0x483C8) after self-refresh stops.

Note: Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF

(D0/0x483CC) to 1 when already 1 or setting 0 when already 0 is prohibited because such bit

manipulation may cause the SDRAM controller to operate erratically.

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III-3-50 EPSON S1C33401 TECHNICAL MANUAL

III.3.9 Precautions

• Clock output to SDRAM is turned off in HALT2 or SLEEP mode. Therefore, before entering these modes, be

sure to set SDRAM to self-refresh mode.

• Do not write the same value to SELF (D0/0x483CC) that is currently set there. Setting SELF (D0/0x483CC) to 1

when already 1 or setting 0 when already 0 is prohibited because such bit manipulation may cause the SDRAM

controller to operate erratically.

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HSDMA

III.4 High-Speed DMA (HSDMA)

III.4.1 Functional Outline of HSDMA

The C33 ADV Bus Block contains four channels of HSDMA (High-Speed DMA) circuits that support dual-address

transfer and single-address transfer methods.

Since the control registers required for the DMA function are built into the chip, DMA requests for data transfer

can be responded to instantaneously.

Note: Channels 0 to 3 are configured in the same way and have the same functionality. Signal and

control bit names are assigned channel numbers 0 to 3 to distinguish them from other channels.

In this manual, however, channel numbers 0 to 3 are designated with an ‘x’ except where they

must be distinguished, as the explanation is the same for all channels.

Dual-address transfer

In this method, a source address and a destination address for DMA transfer can be specified and a DMA

transfer is performed in two phases. The first phase reads data at the source address into the on-chip temporary

Unlike IDMA (Intelligent DMA), which has transfer information in memory, this DMA method does not

support a DMA link function but allows high-speed data transfers because it is not necessary to read transfer

information from a memory.

Memory,

I/O

Data transfer

(1)

(1) Transfer data is read from the source memory or I/O device.

(2) Transfer data is written to the destination memory or I/O device.

(2)

Destination

Memory,

I/O

Source

HSDMA

Ch.0

Ch.1

Ch.2

Ch.3

ITC

End of DMA

DMA request

#DMAREQx

BBCU/

EBCU

#DMAENDx

Address busDMA address bus

DMA data transfer

request signal

Transfer count

end signal

DMA data transfer

acknowledge signal

Hardware/software

trigger

Data bus

Figure III.4.1.1 Dual-Address Transfer Method

The features of dual-address transfer are outlined below.

• Source External memory and internal memory except Area 0 (including peripheral area)

• Destination External memory and internal memory except Area 0 (including peripheral area)

• Transfer data size 8, 16, or 32 bits

• Trigger 1. Software trigger (register control)

2. Hardware trigger (external trigger input, causes of interrupts)

• Transfer mode 1. Single transfer (one unit of data is transferred by one trigger)

2. Successive transfer (specified number of data are transferred by one trigger)

3. Block transfer (data block of the specified size is transferred by one trigger)

• Transfer address control The source and/or destination addresses can be incremented or decremented in

units of the transfer data size upon completion of transfer.

In successive or block transfers, the address can be reset to the initial value upon

completion of transfer.

• #DMAEND output Goes low at the last access of data transfer by each trigger.

Note: A0RAM (no-wait RAM built into area 0) cannot be specified as the source or destination for DMA

transfer. A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) can be

used for dual-address transfer.

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III-4-2 EPSON S1C33401 TECHNICAL MANUAL

Timing chart of dual-address mode

(1) SRAM

Address

#CE(src)

#CE(dst)

#RD

#WR∗

#DMAEND

Source address

Read cycle Write cycle

Destination address

Figure III.4.1.2 #DMAEND Signal Output Timing (SRAM, standard settings)

(2) SDRAM

SDCLK

Address

#SDCS(src)

#SDCS(dst)

#SDRAS

#SDCAS

#SDWE

#DMAEND

RAS

CAS

Read cycle

Write cycle

RAS

CAS

ACT

READ

ACT

WRIT

Figure III.4.1.3 #DMAEND Signal Output Timing (SDRAM, standard settings)

Notes: • Two or more access cycles are generated when the device size of the external memory is

smaller than the transfer data size. In this case, the #DMAEND signal is asserted over these

cycles.

• The #DMAEND signal is not asserted when a peripheral I/O register located in area 1 is

specified as the destination of transfer.

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HSDMA

Single-address transfer

In this method, data transfers that are normally accomplished by executing data read and write operations back-

to-back are executed on the external bus collectively at one time, thus further speeding up the transfer operation.

The #DMAACKx and #DMAENDx signals are used to control data transfer.

Unlike dual-address transfer, this method does not allow memory to memory data transfer but data transfers can

be performed in minimum cycles.

External

I/O

#RD/#WR

Data transfer

External

memory,

external or

internal

I/O

HSDMA

Ch.0

Ch.1

Ch.2

Ch.3

ITC

End of DMA

DMA reception

DMA request

#DMAREQx

BBCU

#DMAENDx

#DMAACKx

Address busDMA address bus

DMA data transfer

request signal

Transfer count

end signal

Bus control signals

DMA data transfer

acknowledge signal

Hardware/software

trigger

Data bus

Figure III.4.1.4 Single-Address Transfer Method

The features of single-address transfer are outlined below.

• Source/destination 1. Between an external I/O and an external memory (except SDRAM)

2. Between an external I/O and another external I/O

3. Between an external I/O and an internal I/O (except peripheral block in area 1)

• Transfer data size 8, 16, or 32 bits

• Trigger 1. Software trigger (register control)

2. Hardware trigger (external trigger input, causes of interrupts)

• Transfer mode 1. Single transfer (one unit of data is transferred by one trigger)

2. Successive transfer (specified number of data are transferred by one trigger)

3. Block transfer (data block of the specified size is transferred by one trigger)

• Transfer address control The source and/or destination addresses can be incremented or decremented in

units of the transfer data size upon completion of transfer.

In successive or block transfers, the address can be reset to the initial value upon

completion of transfer.

• #DMAEND output Goes low at the last access of data transfer by each trigger.

• #DMAACK output Output for accessing the external I/O in every cycle during transfer.

Notes: • A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the internal

peripheral I/O registers (area 1) cannot be used for single-address transfer.

• Single-address mode does not allow data transfer between memory devices. An external logic

circuit is required to perform single-address transfer between memory devices.

• Single-address mode does not support the external memory area that is configured for

SDRAM.

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III-4-4 EPSON S1C33401 TECHNICAL MANUAL

Timing chart of single-address mode

(1) SRAM

Address

#CE

#RD

#WR∗

#DMAACK

#DMAEND

Memory address

Read/write cycle

Figure III.4.1.5 #DMAACK/#DMAEND Signal Output Timing (SRAM, standard settings)

(2) SDRAM

The single-address mode does not support SDRAM.

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HSDMA

III.4.2 I/O Pins of HSDMA

Table III.4.2.1 lists the I/O pins used for HSDMA.

Table III.4.2.1 I/O Pins of HSDMA

Pin name

#DMAREQ0

#DMAREQ1

#DMAREQ2

#DMAREQ3

#DMAACK0

#DMAACK1

#DMAACK2

#DMAACK3

#DMAEND0

#DMAEND1

#DMAEND2

#DMAEND3

I/O

Function

DMA transfer request input pin for HSDMA Ch.0

DMA transfer request input pin for HSDMA Ch.1

DMA transfer request input pin for HSDMA Ch.2

DMA transfer request input pin for HSDMA Ch.3

DMA acknowledge signal output pin for HSDMA Ch.0

DMA acknowledge signal output pin for HSDMA Ch.1

DMA acknowledge signal output pin for HSDMA Ch.2

DMA acknowledge signal output pin for HSDMA Ch.3

End-of-transfer signal output pin for HSDMA Ch.0

End-of-transfer signal output pin for HSDMA Ch.1

End-of-transfer signal output pin for HSDMA Ch.2

End-of-transfer signal output pin for HSDMA Ch.3

#DMAREQx (DMA request input pin)

This pin is used to input a DMA request signal from an external peripheral circuit. One data transfer operation

is performed by this trigger (either the rising edge or the falling edge of the signal can be selected). The

#DMAREQ0 to #DMAREQ3 pins correspond to channel 0 to channel 3, respectively.

In addition to this external input, software trigger or a cause of interrupt can be selected for the HSDMA trigger

source using the register in the interrupt controller.

#DMAACKx (DMA acknowledge signal output pin for single-address mode)

This signal is output to indicate that a DMA request has been acknowledged by the DMA controller.

In single-address mode, the I/O device that is the source or destination of transfer outputs data to the external

bus or takes in data from the external data synchronously with this signal.

The #DMAACK0 to #DMAACK3 pins correspond to channel 0 to channel 3, respectively.

This signal is not output in dual-address mode.

See Figure III.4.1.5 for the waveform of the #DMAACKx signal.

#DMAENDx (End-of-transfer signal output pin)

This signal is output to indicate that the number of data transfer operations that is set in the control register have

been completed. The #DMAEND0 to #DMAEND3 pins correspond to channel 0 to channel 3, respectively.

The waveform of the #DMAENDx signal is the same as the #CEx signal.

Notes: • The list above indicates the input/output pins that the HSDMA can accommodate. All control

signal pins may not be available for some C33 ADV models.

For details of the pin configuration of each C33 ADV model, see Section I.3, “Pin Description.”

• The control pins above are shared with general-purpose input/output ports or other peripheral

circuit input/output pins, so that functionality in the initial state may be set to other than the

HSDMA. Before the HSDMA signals assigned to these pins can be used, the functions of

these pins must be switched for the HSDMA by setting each corresponding Port Function

Select Register.

For details of pin functions and how to switch over, see Section I.3.3, “Switching Over the

Multiplexed Pin Functions.”

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III-4-6 EPSON S1C33401 TECHNICAL MANUAL

III.4.3 Programming Control Information

The HSDMA operates according to the control information set in the registers.

Note that some control bits change their functions according to the address mode.

The following explains how to set the contents of control information. Before using HSDMA, make each the

settings described below.

III.4.3.1 Standard Mode and Advanced Mode

The HSDMA in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV HSDMA has

two operating modes, the standard (STD) mode of which functions are compatible with the existing C33 STD

models and an advanced (ADV) mode allowing use of the extended functions. Table III.4.3.1.1 shows differences

between standard mode and advanced mode.

Table III.4.3.1.1 Differences between Standard Mode and Advanced Mode

Function

Source/destination address bit width

Word (32-bit) data transfer

Address decrement function with initialization

Advanced mode

32 bits

Available

Standard mode

28 bits

Unavailable

To configure the HSDMA in advanced mode, set HSDMAADV (D0/0x4829C) to 1. The control registers (0x48262

–0x4829A) for the extended functions are enabled to write after this setting. At initial reset, HSDMAADV (D0/

0x4829C) is set to 0 and the HSDMA enters standard mode.

∗ HSDMAADV: Standard/Advanced Mode Select Bit in the HSDMA STD/ADV Mode Select Register (D0/0x4829C)

The following descriptions unless otherwise specified are common contents for both modes. The extended functions

in advanced mode are explained assuming that HSDMAADV (D0/0x4829C) has been set to 1.

Notes: • Be sure to use the control registers for advanced mode when the HSDMA is set to advanced

mode.

• The standard or advanced mode currently set is applied to all the HSDMA channels. It cannot

be selected for each channel individually.

III.4.3.2 Setting the Registers in Dual-Address Mode

Make sure that the HSDMA channel is disabled (HSx_EN (D0/0x4822C + 0x10•x) = 0) before setting the control

information.

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

Address mode

The address mode select bit DUALMx (D15/0x48222 + 0x10•x) should be set to 1 (dual-address mode). This

bit is set to 0 (single-address mode) at initial reset.

∗ DUALMx: Ch.x Address Mode Select Bit in the HSDMA Ch.x Control Register (D15/0x48222 + 0x10•x)

Transfer mode

A transfer mode should be set using DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x).

∗ DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup

The following three transfer modes are available:

Single transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) = 00, default)

In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data of the

specified size. If data transfer need to be performed a number of times as set by the transfer counter, an equal

number of triggers are required.

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HSDMA

Successive transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) = 01)

In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer

counter. The transfer counter is decremented to 0 each time data is transferred.

Block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) = 10)

In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of the

size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x). If a block transfer need to be performed a number of

times as set by the transfer counter, an equal number of triggers are required.

Transfer data size

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

DATSIZEx (D14/0x48226 + 0x10•x) is used to set the unit size of data to be transferred.

A half-word size (16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default).

∗ DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

In advanced mode, WORDSIZEx (D0/0x48262 + 0x10•x) is provided to select word size (32 bits) in addition to

half-word size and byte size that can be selected using DATSIZEx (D14/0x48226 + 0x10•x).

∗ WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode

(D0/0x48262 + 0x10•x)

Table III.4.3.2.1 Transfer Data Size Selectable in Advanced Mode

WORDSIZEx

Transfer data size

Word (32 bits)

Half-word (16 bits)

Byte (8 bits)

DATSIZEx

Block length

When using block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) = 10), the data block length (in

units of the selected transfer data size) should be set using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x).

∗ BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register

(D[7:0]/0x48220 + 0x10•x)

Note: When performing data transfer in block transfer mode, the block size must not be set to 0.

In single transfer and successive transfer modes, BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) is used as bits 7–0

of the transfer counter.

Transfer counter

Block transfer mode

In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] (D[15:8]/0x48220 +

0x10•x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10•x).

∗ TCx_L[7:0]: Ch.x Transfer Counter [7:0] Bits in the HSDMA Ch.x Transfer Counter Register

(D[15:8]/0x48220 + 0x10•x)

∗ TCx_H[7:0]: Ch.x Transfer Counter [15:8] Bits in the HSDMA Ch.x Control Register (D[7:0]/0x48222 + 0x10•x)

Single transfer and successive transfer modes

In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using

BLKLENx[7:0] (D[7:0]/0x48220 + 0x10 •x), TCx_L[7:0] (D[15:8]/0x48220 + 0x10 •x) and TCx_H[7:0]

(D[7:0]/0x48222 + 0x10•x).

Note: The transfer count thus set is decremented according to the transfers performed. If the transfer

count is set to 0, it is decremented to all Fs by the first transfer performed. This means that you

have set the maximum value that is determined by the number of bits available.

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III-4-8 EPSON S1C33401 TECHNICAL MANUAL

Source and destination addresses

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

In standard mode, a 28-bit source address and a 28-bit destination address for DMA transfer can be

specified using SxADRL[15:0] (D[15:0]/0x48224 + 0x10•x), SxADRH[11:0] (D[11:0]/0x48226 + 0x10•x),

DxADRL[15:0] (D[15:0]/0x48228 + 0x10•x) and DxADRH[11:0] (D[11:0]/0x4822A + 0x10•x).

∗ SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register

(D[15:0]/0x48224 + 0x10•x)

∗ SxADRH[11:0]: Ch.x Source Address[27:16] in the HSDMA Ch.x High-Order Source Address Setup

∗ DxADRL[15:0]: Ch.x Destination Address[15:0] in the HSDMA Ch.x Low-Order Destination Address Setup

∗ DxADRH[11:0]: Ch.x Destination Address[27:16] in the HSDMA Ch.x High-Order Destination Address

Setup Register (D[11:0]/0x4822A + 0x10•x)

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

In advanced mode, a 32-bit source address and a 32-bit destination address for DMA transfer can be

specified using SxADRL[15:0] (D[15:0]/0x48264 + 0x10•x), SxADRH[15:0] (D[15:0]/0x48266 + 0x10•x),

DxADRL[15:0] (D[15:0]/0x48268 + 0x10•x) and DxADRH[15:0] (D[15:0]/0x4826A + 0x10•x).

∗ SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register

for ADV mode (D[15:0]/0x48264 + 0x10•x)

∗ SxADRH[15:0]: Ch.x Source Address[31:16] in the HSDMA Ch.x High-Order Source Address Setup

∗ DxADRL[15:0]: Ch.x Destination Address[15:0] in the HSDMA Ch.x Low-Order Destination Address Setup

∗ DxADRH[15:0]: Ch.x Destination Address[31:16] in the HSDMA Ch.x High-Order Destination Address

Setup Register for ADV mode (D[15:0]/0x4826A + 0x10•x)

Note: In advanced mode, be sure to use the control registers for advanced mode to set source/

destination addresses.

Address increment/decrement control

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

The source and/or destination addresses can be incremented or decremented when one data transfer is

completed. SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) (for source address) and DxIN[1:0] (D[13:12]/0x4822A +

0x10•x) (for destination address) are used to set this function.

∗ SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

∗ DxIN[1:0]: Ch.x Destination Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

SxIN[1:0]/DxIN[1:0] = 00: address fixed (default)

The address is not changed by a data transfer performed. Even when transferring multiple data, the transfer

data is always read/write from/to the same address.

SxIN[1:0]/DxIN[1:0] = 01: address decremented without initialization

The address is decremented by an amount equal to the specified data size when one data transfer is

completed. The address that has been decremented during transfer does not return to the initial value.

SxIN[1:0]/DxIN[1:0] = 10: address incremented with initialization

The address is incremented by an amount equal to the specified data size when one data transfer is

completed. In single transfer mode, the address that has been incremented during transfer does not return to

the initial value. In successive transfer modes, the incremented address returns to the initial value when the

specified number of transfers is completed. In block transfer mode, the incremented address returns to the

initial value when the block transfer is completed.

SxIN[1:0]/DxIN[1:0] = 11: address incremented without initialization

The address is incremented by an amount equal to the specified data size when one data transfer is

completed. The address that has been incremented during transfer does not return to the initial value.

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HSDMA

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

The address control conditions set using SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) and DxIN[1:0] (D[13:12]/

0x4822A + 0x10•x) are effective in advanced mode. Furthermore, advanced mode allows selection of “Address

decremented with initialization.” This condition can be selected using the SxID (D4/0x48262 + 0x10•x) and

DxID (D5/0x48262 + 0x10•x).

∗ SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D4/0x48262 + 0x10•x)

∗ DxID: Ch.x Destination Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D5/0x48262 + 0x10•x)

When SxID (D4/0x48262 + 0x10•x) and/or DxID (D5/0x48262 + 0x10•x) are set to 0 (default), the conditions

selected using SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) and/or DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) are

effective. When SxID (D4/0x48262 + 0x10•x) and/or DxID (D5/0x48262 + 0x10•x) are set to 1, “Address

decremented with initialization” is selected.

SxID/DxID = 1: address decremented with initialization

The address is decremented by an amount equal to the specified data size when one data transfer is

completed. In single transfer mode, the address that has been decremented during transfer does not return to

the initial value. In successive transfer modes, the decremented address returns to the initial value when the

specified number of transfers is completed. In block transfer mode, the decremented address returns to the

initial value when the block transfer is completed.

III.4.3.3 Setting the Registers in Single-Address Mode

Make sure that the HSDMA channel is disabled (HSx_EN (D0/0x4822C + 0x10•x) = 0) before setting the control

information.

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

Address mode

The address mode select bit DUALMx (D15/0x48222 + 0x10•x) should be set to 0 (single-address mode). This

bit is set to 0 at initial reset.

∗ DUALMx: Ch.x Address Mode Select Bit in the HSDMA Ch.x Control Register (D15/0x48222 + 0x10•x)

Transfer mode

A transfer mode should be set using DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x).

∗ DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup

Table III.4.3.3.1 Transfer Mode

DxMOD1

DxMOD0

Mode

Invalid

Block transfer mode

Successive transfer mode

Single transfer mode

Refer to the explanation in Section III.4.3.2, “Setting the Registers in Dual-Address Mode.”

Direction of transfer

The direction of data transfer should be set using DxDIR (D14/0x48222 + 0x10•x).

∗ DxDIR: Ch.x Transfer Direction Control Bit in the HSDMA Ch.x Control Register (D14/0x48222 + 0x10•x)

Memory write operations (data transfer from I/O device to memory) are specified by writing 1 and memory

read operations (data transfer from memory to I/O device) are specified by writing 0.

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Transfer data size

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

DATSIZEx (D14/0x48226 + 0x10•x) is used to set the unit size of data to be transferred.

A half-word size (16 bits) is assumed if this bit is 1 and a byte size (8 bits) is assumed if this bit is 0 (default).

∗ DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

In advanced mode, WORDSIZEx (D0/0x48262 + 0x10•x) is provided to select a word size (32 bits) in addition

to a half-word size and byte size that can be selected using DATSIZEx (D14/0x48226 + 0x10•x).

∗ WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode

(D0/0x48262 + 0x10•x)

Table III.4.3.3.2 Transfer Data Size Selectable in Advanced Mode

WORDSIZEx

Transfer data size

Word (32 bits)

Half-word (16 bits)

Byte (8 bits)

DATSIZEx

DATSIZEx (D14/0x48226 + 0x10•x) and WORDSIZEx (D0/0x48262 + 0x10•x) are used to set the unit size of

data to be transferred.

Block length

When using block transfer mode (DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) = 10), the data block length (in

units of the selected transfer data size) should be set using BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x).

∗ BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register (D[7:0]/0x48220 + 0x10•x)

In single transfer and successive transfer modes, BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) are used as bits 7–

0 of the transfer counter.

Note: When performing data transfer in block transfer mode, the block size must not be set to 0.

Transfer counter

Block transfer mode

In block transfer mode, up to 16 bits of transfer count can be specified using TCx_L[7:0] (D[15:8]/0x48220 +

0x10•x) and TCx_H[7:0] (D[7:0]/0x48222 + 0x10•x).

∗ TCx_L[7:0]: Ch.x Transfer Counter [7:0] Bits in the HSDMA Ch.x Transfer Counter Register

(D[15:8]/0x48220 + 0x10•x)

∗ TCx_H[7:0]: Ch.x Transfer Counter [15:8] Bits in the HSDMA Ch.x Control Register (D[7:0]/0x48222 + 0x10•x)

Single transfer and successive transfer modes

In single transfer and successive transfer modes, up to 24 bits of transfer count can be specified using

BLKLENx[7:0] (D[7:0]/0x48220 + 0x10 •x), TCx_L[7:0] (D[15:8]/0x48220 + 0x10 •x) and TCx_H[7:0]

(D[7:0]/0x48222 + 0x10•x).

Memory address

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

In standard mode, SxADRL[15:0] (D[15:0]/0x48224 + 0x10•x) and SxADRH[11:0] (D[11:0]/0x48226 + 0x10•x)

are used to specify a 28-bit memory address.

∗ SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register

(D[15:0]/0x48224 + 0x10•x)

∗ SxADRH[11:0]: Ch.x Source Address[27:16] in the HSDMA Ch.x High-Order Source Address Setup

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HSDMA

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

In advanced mode, SxADRL[15:0] (D[15:0]/0x48264 + 0x10•x) and SxADRH[15:0] (D[15:0]/0x48266 + 0x10

•x) are used to specify a 32-bit memory address.

∗ SxADRL[15:0]: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register

for ADV mode (D[15:0]/0x48264 + 0x10•x)

∗ SxADRH[15:0]: Ch.x Source Address[31:16] in the HSDMA Ch.x High-Order Source Address Setup

Note: In advanced mode, be sure to use the control registers for advanced mode to set a memory

address.

In single-address mode, data transfer is performed between the memory connected to the system interface and

an external I/O device. The I/O device is accessed directly by the #DMAACKx signal, so it is unnecessary to

specify an address. DxADRL[15:0] (D[15:0]/0x48268 + 0x10•x) and DxADRH[15:0] (D[11:0]/0x4826A +

0x10•x) are not used in single-address mode.

Address increment/decrement control

Standard mode (HSDMAADV (D0/0x4829C) = 0, default)

The memory addresses can be incremented or decremented when one data transfer is completed. SxIN[1:0]

(D[13:12]/0x48226 + 0x10•x) is used to set this function.

∗ SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

Table III.4.3.3.3 Address Control

SxIN1

SxIN0

Address control

Increment without initialization

Increment with initialization

Decrement without initialization

Fixed

Advanced mode (HSDMAADV (D0/0x4829C) = 1)

The address control condition set using SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) is effective in advanced mode.

Furthermore, advanced mode allows selection of “Address decremented with initialization.” This condition can

be selected using the SxID (D4/0x48262 + 0x10•x).

∗ SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D4/0x48262 + 0x10•x)

When SxID (D4/0x48262 + 0x10•x) is set to 0 (default), the condition selected using SxIN[1:0] (D[13:12]/

0x48226 + 0x10•x) is effective. When SxID (D4/0x48262 + 0x10•x) is set to 1, “Address decremented with

initialization” is selected.

Refer to the explanation in Section III.4.3.2, “Setting the Registers in Dual-Address Mode.”

DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) and DxID (D5/0x48262 + 0x10•x) are not used in single-address

mode.

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III.4.4 Enabling/Disabling DMA Transfer

The HSDMA transfer is enabled by writing 1 to HSx_EN (D0/0x4822C + 0x10•x).

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

However, the control information must always be set correctly before enabling a DMA transfer.

Note that the control information cannot be set when HSx_EN (D0/0x4822C + 0x10•x) = 1.

When HSx_EN (D0/0x4822C + 0x10•x) is set to 0, HSDMA requests are no longer accepted.

When a DMA transfer is completed (transfer counter = 0), HSx_EN (D0/0x4822C + 0x10•x) is reset to 0 to disable

the following trigger inputs.

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HSDMA

III.4.5 Trigger Source

A HSDMA trigger source for each channel can be selected from among 15 types using HSDxS[3:0] (D[7:0]/0x40298,

D[7:0]/0x40299). This function is supported by the interrupt controller.

∗ HSD0S[3:0]: Ch.0 Trigger Set-Up Bits in the HSDMA Ch.0–1 Trigger Set-Up Register (D[3:0]/0x40298)

∗ HSD1S[3:0]: Ch.1 Trigger Set-Up Bits in the HSDMA Ch.0–1 Trigger Set-Up Register (D[7:4]/0x40298)

∗ HSD2S[3:0]: Ch.2 Trigger Set-Up Bits in the HSDMA Ch.2–3 Trigger Set-Up Register (D[3:0]/0x40299)

∗ HSD3S[3:0]: Ch.3 Trigger Set-Up Bits in the HSDMA Ch.2–3 Trigger Set-Up Register (D[7:4]/0x40299)

Table III.4.5.1 shows the setting value and the corresponding trigger source.

Table III.4.5.1 HSDMA Trigger Source

Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

Ch.0 trigger source

Software trigger

#DMAREQ0 input (falling edge)

#DMAREQ0 input (rising edge)

Port 0 input

Port 4 input

8-bit timer 0 underflow

16-bit timer 0 compare B

16-bit timer 0 compare A

16-bit timer 4 compare B

16-bit timer 4 compare A

Serial I/F Ch.0 Rx buffer full

Serial I/F Ch.0 Tx buffer empty

A/D conversion completion

Port 8 input

Port 12 input

Ch.1 trigger source

Software trigger

#DMAREQ1 input (falling edge)

#DMAREQ1 input (rising edge)

Port 1 input

Port 5 input

8-bit timer 1 underflow

16-bit timer 1 compare B

16-bit timer 1 compare A

16-bit timer 5 compare B

16-bit timer 5 compare A

Serial I/F Ch.1 Rx buffer full

Serial I/F Ch.1 Tx buffer empty

A/D conversion completion

Port 9 input

Port 13 input

Ch.2 trigger source

Software trigger

#DMAREQ2 input (falling edge)

#DMAREQ2 input (rising edge)

Port 2 input

Port 6 input

8-bit timer 2 underflow

16-bit timer 2 compare B

16-bit timer 2 compare A

16-bit timer 6 compare B

16-bit timer 6 compare A

Serial I/F Ch.2 Rx buffer full

Serial I/F Ch.2 Tx buffer empty

A/D conversion completion

Port 10 input

Port 14 input

Ch.3 trigger source

Software trigger

#DMAREQ3 input (falling edge)

#DMAREQ3 input (rising edge)

Port 3 input

Port 7 input

8-bit timer 3 underflow

16-bit timer 3 compare B

16-bit timer 3 compare A

16-bit timer 7 compare B

16-bit timer 7 compare A

Serial I/F Ch.3 Rx buffer full

Serial I/F Ch.3 Tx buffer empty

A/D conversion completion

Port 11 input

Port 15 input

By selecting a cause of interrupt with the HSDMA trigger set-up register, the HSDMA channel is invoked when

the selected interrupt factor occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable register,

IDMA request register, interrupt priority register) do not affect this invocation. The cause of interrupt that invokes

HSDMA sets the cause-of-interrupt flag. and HSDMA does not reset the flag. Consequently, when the DMA

transfer is completed (even if the transfer counter is not 0), an interrupt request to the CPU will be generated if the

interrupt has been enabled. To generate an interrupt only when the transfer counter reaches 0, disable the interrupt

by the cause of interrupt that invokes HSDMA and use the HSDMA transfer completion interrupt.

When software trigger is selected, the HSDMA channel can be invoked by writing 1 to HSTx (Dx/0x4029A).

∗ HSTx: Ch.x Software Trigger Bit in the HSDMA Software Trigger Register (Dx/0x4029A)

When the selected trigger occurs, the trigger flag is set to 1 to invoke the HSDMA channel.

The HSDMA starts a DMA transfer if it has been enabled and the trigger flag is cleared by the hardware at the

same time. This makes it possible to queue the HSDMA triggers that have been generated.

The trigger flag can be read and cleared using HSx_TF (D0/0x4822E + 0x10•x).

∗ HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10•x)

By writing 1 to this bit, the set trigger flag can be cleared if the DMA transfer has not been started.

When this bit is read, 1 indicates that the flag is set and 0 indicates that the flag is cleared.

Note: The following shows the priority order of channels when DMA triggers with the same interrupt

level occur in two or more HSDMA and IDMA channels.

Priority

Channel

High ← → Low

HSDMA Ch.0 > Ch.1 > Ch.2 > Ch.3 > IDMA software trigger > IDMA hardware trigger

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III.4.6 Operation of HSDMA

An HSDMA channel starts data transfer by the selected trigger source.

Make sure that transfer conditions and a trigger source are set and the HSDMA channel is enabled before starting a

DMA transfer.

III.4.6.1 Operation in Dual-Address Mode

In dual-address mode, both the source and destination addresses are accessed according to the bus condition set by

the BBCU and EBCU.

HSDMA has three transfer modes, in each of which data transfer operates differently. The following describes the

operation of HSDMA in each transfer mode.

Single transfer mode (dual-address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 00 operates

in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring

one data unit of the size set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262 + 0x10•x).

If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of

triggers are required.

∗ DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup

∗ DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup

∗ WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode

(D0/0x48262 + 0x10•x)

The operation of HSDMA in single transfer mode is shown by the flow chart in Figure III.4.6.1.1.

START

END

Data read from source

(1 byte, 1 half word or 1 word)

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Data write to destination

(1 byte, 1 half word or 1 word)

Transfer counter - 1

Set cause-of-interrupt flag

FHDMx

Transfer

counter = 0

Increment/decrement

address ∗

∗: according to SxIN/DxIN or

SxID/DxID settings

Figure III.4.6.1.1 Operation Flow in Single Transfer Mode

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(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared and then data of the

size set in the control information is read from the source address.

∗ HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10•x)

(2) The read data is written to the destination address.

(3) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10•

x)/DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) or SxID (D4/0x48262 + 0x10•x)/DxID (D5/0x48262 + 0x10•x)

settings. ∗1

∗ SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

∗ DxIN[1:0]: Ch.x Destination Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

∗ SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D4/0x48262 + 0x10•x)

∗ DxID: Ch.x Destination Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D5/0x48262 + 0x10•x)

(4) The transfer counter is decremented.

(5) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

∗1: In standard mode, SxID (D4/0x48262 + 0x10•x) and DxID (D5/0x48262 + 0x10•x) are both fixed at 0.

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Successive transfer mode (dual-address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 01 operates

in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set

by the transfer counter. The transfer counter is decremented to 0 by one transfer executed.

The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure III.4.6.1.2.

START

END

Transfer counter - 1

Transfer

counter = 0

Increments/decrements

address ∗

∗: according to SxIN/DxIN or

SxID/DxID settings

Data read from source

(1 byte, 1 half word or 1 word)

Data write to destination

(1 byte, 1 half word or 1 word)

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Set cause-of-interrupt flag

FHDMx

Restores initial values to

address ∗

∗: according to SxIN/DxIN or

SxID/DxID settings

Figure III.4.6.1.2 Operation Flow in Successive Transfer Mode

(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared and then data of the

size set in the control information is read from the source address.

(2) The read data is written to the destination address.

(3) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10•

x)/DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) or SxID (D4/0x48262 + 0x10•x)/DxID (D5/0x48262 + 0x10•x)

settings. ∗1

(4) The transfer counter is decremented.

(5) Steps (1) to (4) are repeated until the transfer counter reaches 0.

(6) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10•x)/DxIN[1:0] (D[13:12]/

0x4822A + 0x10•x) is 10 or SxID (D4/0x48262 + 0x10•x)/DxID (D5/0x48262 + 0x10•x) is 1. ∗1

(7) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗1: In standard mode, SxID (D4/0x48262 + 0x10•x) and DxID (D5/0x48262 + 0x10•x) are both fixed at 0.

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Block transfer mode (dual-address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 10 operates

in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring

one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x). If a block transfer needs to be

performed a number of times as set by the transfer counter, an equal number of triggers are required.

The operation of HSDMA in block transfer mode is shown by the flow chart in Figure III.4.6.1.3.

∗ BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register

(D[7:0]/0x48220 + 0x10•x)

START

END

Block size - 1

Restores initial values to

block size and address ∗

Block

size = 0

1-block transfer

Transfer counter - 1

Transfer

counter = 0

∗: according to SxIN/DxIN or

SxID/DxID settings

Data read from source

(1 byte, 1 half word or 1 word)

Data write to destination

(1 byte, 1 half word or 1 word)

Increments/decrements

address ∗

∗: according to SxIN/DxIN or

SxID/DxID settings

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Set cause-of-interrupt flag

FHDMx

Figure III.4.6.1.3 Operation Flow in Block Transfer Mode

(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared and then data of the

size set in the control information is read from the source address.

(2) The read data is written to the destination address.

(3) The address is incremented or decremented and BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) is decremented.

(4) Steps (1) to (3) are repeated until BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) reaches 0.

(5) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10•x)/DxIN[1:0] (D[13:12]/

0x4822A + 0x10•x) is 10 or SxID (D4/0x48262 + 0x10•x)/DxID (D5/0x48262 + 0x10•x) is 1. ∗1

(6) The transfer counter is decremented.

(7) Steps (1) to (6) are repeated until the transfer counter reaches 0.

(8) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗1: In standard mode, SxID (D4/0x48262 + 0x10•x) and DxID (D5/0x48262 + 0x10•x) are both fixed at 0.

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III.4.6.2 Operation in Single-Address Mode

In single-address mode, data read/write operations are performed simultaneously. The data transfer direction (read

from I/O device → write to memory or read from memory → write to I/O device) is set using DxDIR (D14/0x48222

+ 0x10•x)

∗ DxDIR: Ch.x Transfer Direction Control Bit in the HSDMA Ch.x Control Register (D14/0x48222 + 0x10•x)

Single-address mode has three transfer modes, in each of which data transfer operates differently. The following

describes the operation of HSDMA in single-transfer mode.

#DMAACKx signal output and bus operation

When the HSDMA circuit accepts the DMA request, it outputs a low-level pulse from the #DMAACKx pin and

starts bus operation for the memory at the same time.

The contents of this bus operation are as follows:

• Data transfer from I/O device to memory (DxDIR (D14/0x48222 + 0x10•x) = 1)

The address that has been set in the memory address register is output to the address bus.

A write operation is performed under the interface conditions set on the area to which the memory at the

destination of transfer belongs. The data bus is left floating.

The external I/O device outputs the transfer data onto the data bus using the #DMAACKx signal as the read

signal. The memory takes in this data using the write signal.

• Data transfer from memory to an I/O device (DxDIR (D14/0x48222 + 0x10•x) = 0, default)

The address that has been set in the memory address register is output to the address bus.

A read operation is performed under the interface conditions set on the area to which the memory at the source

of transfer belongs.

The memory outputs the transfer data onto the data bus using the read signal.

The external I/O device takes in the data from the data bus using the #DMAACKx signal as the write signal.

The number of bus operations for a DMA transfer is decided according to the transfer data size and I/O device

size as shown in the table below.

Table III.4.6.2.1 Number of Bus Operations Per DMA Transfer

Transfer data size

32 bits

16 bits

Other

Number of bus operations

I/O device size

8 bits

16 bits

8 bits

Notes: • A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the internal

peripheral I/O registers (area 1) cannot be used for single-address transfer.

• Single-address mode does not allow data transfer between memory devices. An external logic

circuit is required to perform single-address transfer between memory devices.

• Single-address mode does not support the external memory area that is configured for

SDRAM.

#DMAENDx signal output

When the transfer counter reaches 0, the end-of-transfer signal is output from the #DMAENDx pin indicating

that a specified number of transfers has been completed. At the same time, the cause-of-interrupt (completion

of HSDMA) is generated.

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HSDMA

Single transfer mode (single address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 00 operates

in single transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring

one data unit of the size set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262 + 0x10•x).

If a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of

triggers are required.

∗ DxMOD[1:0]: Ch.x Transfer Mode Select Bits in the HSDMA Ch.x High-Order Destination Address Setup

∗ DATSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x High-Order Source Address Setup

∗ WORDSIZEx: Ch.x Transfer Data Size Select Bit in the HSDMA Ch.x Control Register for ADV mode

(D0/0x48262 + 0x10•x)

The operation of HSDMA in single transfer mode is shown by the flow chart in Figure III.4.6.2.1.

START

END

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Transfer counter - 1

Set cause-of-interrupt flag

FHDMx

Transfer

counter = 0

Increment/decrement

address ∗

∗: according to SxIN or

SxID settings

Data read from source and

data write to destination

(1 byte, 1 half word or 1 word)

Figure III.4.6.2.1 Operation Flow in Single Transfer Mode

(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared. Data of the size

set in the control information is read from the external memory or I/O device according to the specified

direction and is written to the I/O device or external memory. ∗1

∗ HSx_TF: Ch.x Trigger Flag Status/Clear Bit in the HSDMA Ch.x Trigger Flag Register (D0/0x4822E + 0x10•x)

(2) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) or

SxID (D4/0x48262 + 0x10•x) settings. ∗2

∗ SxIN[1:0]: Ch.x Source Address Control Bits in the HSDMA Ch.x High-Order Source Address Setup

∗ SxID: Ch.x Source Address Control Bit in the HSDMA Ch.x Control Register for ADV mode

(D4/0x48262 + 0x10•x)

(3) The transfer counter is decremented.

(4) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

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∗1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the

external memory read/write address is delivered from the memory address registers in the control

information SxADRL and SxADRH.

∗ SxADRL: Ch.x Source Address[15:0] in the HSDMA Ch.x Low-Order Source Address Setup Register

(STD mode: D[15:0]/0x48224 + 0x10•x, ADV mode: D[15:0]/0x48264 + 0x10•x)

∗ SxADRH: Ch.x Source Address (high-order bits) in the HSDMA Ch.x High-Order Source Address Setup

∗2: In standard mode, SxID (D4/0x48262 + 0x10•x) is fixed at 0.

Successive transfer mode (single address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 01 operates

in successive transfer mode. In this mode, a data transfer is performed by one trigger a number of times as set

by the transfer counter. The transfer counter is decremented to 0 by one transfer executed.

The operation of HSDMA in successive transfer mode is shown by the flow chart in Figure III.4.6.2.2.

START

END

Transfer counter - 1

Transfer

counter = 0

Increments/decrements

address ∗

∗: according to SxIN or

SxID settings

Data read from source and

data write to destination

(1 byte, 1 half word or 1 word)

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Set cause-of-interrupt flag

FHDMx

Restores initial values to

address ∗

∗: according to SxIN or

SxID settings

Figure III.4.6.2.2 Operation Flow in Successive Transfer Mode

(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared. Data of the size

set in the control information is read from the external memory or I/O device according to the specified

direction and is written to the I/O device or external memory. ∗1

(2) The addresses are incremented or decremented according to the SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) or

SxID (D4/0x48262 + 0x10•x) settings. ∗2

(3) The transfer counter is decremented.

(4) Steps (1) to (3) are repeated until the transfer counter reaches 0.

(5) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) is 10 or SxID (D4/0x48262

+ 0x10•x) is 1. ∗2

(6) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the

external memory read/write address is delivered from the memory address registers in the control

information SxADRL and SxADRH.

∗2: In standard mode, SxID (D4/0x48262 + 0x10•x) is fixed at 0.

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HSDMA

Block transfer mode (single address mode)

The channel for which DxMOD[1:0] (D[15:14]/0x4822A + 0x10•x) in control information is set to 10 operates

in block transfer mode. In this mode, a transfer operation invoked by one trigger is completed after transferring

one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x). If a block transfer needs to be

performed a number of times as set by the transfer counter, an equal number of triggers are required.

The operation of HSDMA in block transfer mode is shown by the flow chart in Figure III.4.6.2.3.

∗ BLKLENx[7:0]: Ch.x Block Length Bits in the HSDMA Ch.x Transfer Counter Register

(D[7:0]/0x48220 + 0x10•x)

START

END

Block size - 1

Restores initial values to

block size and address ∗

Block

size = 0

1-block transfer

Transfer counter - 1

Transfer

counter = 0

∗: according to SxIN or

SxID settings

Increments/decrements

address ∗

∗: according to SxIN or

SxID settings

Clear trigger flag HSx_TF

to accept next trigger

Clear HSDMA enable bit

HSx_EN

Set cause-of-interrupt flag

FHDMx

Data read from source and

data write to destination

(1 byte, 1 half word or 1 word)

Figure III.4.6.2.3 Operation Flow in Block Transfer Mode

(1) When a trigger is accepted, the trigger flag HSx_TF (D0/0x4822E + 0x10•x) is cleared. Data of the size

set in the control information is read from the external memory or I/O device according to the specified

direction and is written to the I/O device or external memory. ∗1

(2) The address is incremented or decremented and BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) is decremented.

(3) Steps (1) to (2) are repeated until BLKLENx[7:0] (D[7:0]/0x48220 + 0x10•x) reaches 0.

(4) The address returns to the initial value if SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) is 10 or SxID (D4/0x48262

+ 0x10•x) is 1. ∗2

(5) The transfer counter is decremented.

(6) Steps (1) to (5) are repeated until the transfer counter reaches 0.

(7) The HSDMA enable bit HSx_EN (D0/0x4822C + 0x10•x) is cleared and HSDMA cause-of-interrupt flag in

ITC is set when the transfer counter reaches 0.

∗1: The data bus is placed in high-impedance state during reading from the I/O device. Furthermore, the

external memory read/write address is delivered from the memory address registers in the control

information SxADRL and SxADRH.

∗2: In standard mode, SxID (D4/0x48262 + 0x10•x) is fixed at 0.

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III.4.7 Interrupt Function of HSDMA

The DMA controller can generate an interrupt when the transfer counter in each HSDMA channel reaches 0.

Furthermore, channels 0 and 1 can invoke IDMA using their cause of interrupt.

Control registers of the interrupt controller

Table III.4.7.1 shows the control registers of the interrupt controller that are provided for each channel.

Table III.4.7.1 Control Registers of Interrupt Controller

Channel

Ch. 0

Ch. 1

Ch. 2

Ch. 3

Cause-of-interrupt flag

FHDM0(D0/0x40281)

FHDM1(D1/0x40281)

FHDM2(D2/0x40281)

FHDM3(D3/0x40281)

Interrupt priority register

PHSD0L[2:0](D[2:0]/0x40263)

PHSD1L[2:0](D[6:4]/0x40263)

PHSD2L[2:0](D[2:0]/0x40264)

PHSD3L[2:0](D[6:4]/0x40264)

Interrupt enable register

EHDM0(D0/0x40271)

EHDM1(D1/0x40271)

EHDM2(D2/0x40271)

EHDM3(D3/0x40271)

The HSDMA controller sets the HSDMA cause-of-interrupt flag to 1 when the transfer counter reaches 0 after

completing a series of HSDMA transfers. If the corresponding bit of the interrupt enable register is set to 1 at

this time, an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register

bit set to 0. The HSDMA cause-of-interrupt flag is always set to 1 when the data transfer in each channel is

completed no matter what value the interrupt enable register bit is set to. (This is true even when it is set to 0.)

The interrupt priority register sets an interrupt priority level (0 to 7). An interrupt request to the CPU is accepted

only when there is no other interrupt request of higher priority. Furthermore, it is only when the PSR's IE bit = 1

(interrupt enable) and the set value of IL is smaller than the HSDMA interrupt level which is set in the interrupt

priority register that the CPU actually accepts a HSDMA interrupt. For details about the interrupt control

Intelligent DMA

Intelligent DMA (IDMA) can be invoked by the end-of-transfer interrupt source of channels 0 and 1 of

HSDMA. The following shows the IDMA channels set in HSDMA:

IDMA channel

Channel 0 end-of-transfer interrupt: 0x05

Channel 1 end-of-transfer interrupt: 0x06

Before IDMA can be invoked, the corresponding bits of the IDMA request and IDMA enable registers must be

set to 1. Settings of transfer conditions on the IDMA side are also required.

Table III.4.7.2 Control Bits for IDMA Transfer

Channel

Ch. 0

Ch. 1

IDMA request bit

RHDM0(D4/0x40290)

RHDM1(D5/0x40290)

IDMA enable bit

DEHDM0(D4/0x40294)

DEHDM1(D5/0x40294)

If the IDMA request and enable bits are set to 1, IDMA is invoked through generation of a cause of interrupt.

No interrupt request is generated at that point. An interrupt request is generated after the DMA transfer is

completed. The registers can also be set so as not to generate an interrupt, with only a DMA transfer performed.

For details on IDMA transfers and interrupt control upon completion of IDMA transfer, refer to Section III.5,

“Intelligent DMA (IDMA).”

Trap vector

The trap vector addresses for causes of interrupt in each channel are set by default as follows:

Channel 0 end-of-transfer interrupt: 0x20000058

Channel 1 end-of-transfer interrupt: 0x2000005C

Channel 2 end-of-transfer interrupt: 0x20000060

Channel 3 end-of-transfer interrupt: 0x20000064

Note that the trap table base address can be modified using the TTBR register.

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HSDMA

III.4.8 HSDMA Operating Clock

The HSDMA circuit is clocked by the core system clock (CCLK) generated by the CMU.

For details on how to set CCLK and control the clock, see Section II.3, “Clock Management Unit (CMU).”

Controlling the supply of the HSDMA operating clock

CCLK is supplied to the DMA controller with default settings. When DMA transfer is not performed, the clock

supply can be turned off using DMACLK (D2/0x48370) to reduce the amount of power consumed on the chip.

Moreover, the clock automatic control function may be enabled using DMAAUTO (D2/0x48372).

∗ DMACLK: DMA Clock Control Bit in the CCLK System Peripheral Clock On/Off Register (D2/0x48370)

∗ DMAAUTO: DMA Clock Automatic Control Bit in the CCLK System Peripheral Clock Automatic Control

Setting DMACLK (D2/0x48370) to 0 (initially 1) turns off the corresponding clock supply to the DMA

controller.

Setting both the clock control bit and automatic control bit (initially 0) to 1 enables the automatic control

function for the clock supply.

If the DMA controller enters the IDLE state while the automatic control function is enabled, clock-enable

signal input to the CMU is negated. As a result, the CMU stops supplying a clock to the DMA controller. This

state is called power-down mode of the DMA controller. When any block generates an operation request to the

DMA controller, the DMA controller immediately reasserts the clock-enable signal. Clock supply from the

CMU is resumed one clock after the clock-enable signal becomes active.

Note: The clock supply should be automatically controlled to reduce the amount of power consumed on

the chip. However, limitations are imposed on the supported operating clock frequency, etc. For

details, see Section II.3, “Clock Management Unit (CMU).”

Clock state in standby mode

The supply of CCLK stops depending on type of standby mode.

HALT mode: CCLK is supplied the same way as in normal mode.

HALT2 mode: The supply of CCLK stops.

SLEEP mode: The supply of CCLK stops.

Therefore, the DMA controller also stops operating when in HALT2 and SLEEP modes.

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III.4.9 Details of Control Registers

Table III.4.9.1 List of HSDMA Registers

Address

0x00048220

0x00048222

0x00048224

0x00048226

0x00048228

0x0004822A

0x0004822C

0x0004822E

0x00048230

0x00048232

0x00048234

0x00048236

0x00048238

0x0004823A

0x0004823C

0x0004823E

0x00048240

0x00048242

0x00048244

0x00048246

0x00048248

0x0004824A

0x0004824C

0x0004824E

0x00048250

0x00048252

0x00048254

0x00048256

0x00048258

0x0004825A

0x0004825C

0x0004825E

Function

Sets Ch.0 low-order transfer counter data and block

length.

Sets Ch.0 address mode and high-order transfer

counter data.

Sets Ch.0 low-order source address.

Sets Ch.0 high-order source address, transfer data

size, and source address inc/dec condition.

Sets Ch.0 low-order destination address.

Sets Ch.0 high-order destination address, transfer

mode, and destination address inc/dec condition.

Enables Ch.0 DMA transfer.

Ch.0 trigger status

Sets Ch.1 low-order transfer counter data and block

length.

Sets Ch.1 address mode and high-order transfer

counter data.

Sets Ch.1 low-order source address.

Sets Ch.1 high-order source address, transfer data

size, and source address inc/dec condition.

Sets Ch.1 low-order destination address.

Sets Ch.1 high-order destination address, transfer

mode, and destination address inc/dec condition.

Enables Ch.1 DMA transfer.

Ch.1 trigger status

Sets Ch.2 low-order transfer counter data and block

length.

Sets Ch.2 address mode and high-order transfer

counter data.

Sets Ch.2 low-order source address.

Sets Ch.2 high-order source address, transfer data

size, and source address inc/dec condition.

Sets Ch.2 low-order destination address.

Sets Ch.2 high-order destination address, transfer

mode, and destination address inc/dec condition.

Enables Ch.2 DMA transfer.

Ch.2 trigger status

Sets Ch.3 low-order transfer counter data and block

length.

Sets Ch.3 address mode and high-order transfer

counter data.

Sets Ch.3 low-order source address.

Sets Ch.3 high-order source address, transfer data

size, and source address inc/dec condition.

Sets Ch.3 low-order destination address.

Sets Ch.3 high-order destination address, transfer

mode, and destination address inc/dec condition.

Enables Ch.3 DMA transfer.

Ch.3 trigger status

HSDMA Ch.0 Transfer Counter Register (pHS0_CNT)

HSDMA Ch.0 Control Register

HSDMA Ch.0 Low-Order Source Address Setup Register

(pHS0_SADR)

HSDMA Ch.0 High-Order Source Address Setup

HSDMA Ch.0 Low-Order Destination Address Setup

HSDMA Ch.0 High-Order Destination Address Setup

HSDMA Ch.0 Enable Register (pHS0_EN)

HSDMA Ch.0 Trigger Flag Register (pHS0_TF)

HSDMA Ch.1 Transfer Counter Register (pHS1_CNT)

HSDMA Ch.1 Control Register

HSDMA Ch.1 Low-Order Source Address Setup Register

(pHS1_SADR)

HSDMA Ch.1 High-Order Source Address Setup

HSDMA Ch.1 Low-Order Destination Address Setup

HSDMA Ch.1 High-Order Destination Address Setup

HSDMA Ch.1 Enable Register (pHS1_EN)

HSDMA Ch.1 Trigger Flag Register (pHS1_TF)

HSDMA Ch.2 Transfer Counter Register (pHS2_CNT)

HSDMA Ch.2 Control Register

HSDMA Ch.2 Low-Order Source Address Setup Register

(pHS2_SADR)

HSDMA Ch.2 High-Order Source Address Setup

HSDMA Ch.2 Low-Order Destination Address Setup

HSDMA Ch.2 High-Order Destination Address Setup

HSDMA Ch.2 Enable Register (pHS2_EN)

HSDMA Ch.2 Trigger Flag Register (pHS2_TF)

HSDMA Ch.3 Transfer Counter Register (pHS3_CNT)

HSDMA Ch.3 Control Register

HSDMA Ch.3 Low-Order Source Address Setup Register

(pHS3_SADR)

HSDMA Ch.3 High-Order Source Address Setup

HSDMA Ch.3 Low-Order Destination Address Setup

HSDMA Ch.3 High-Order Destination Address Setup

HSDMA Ch.3 Enable Register (pHS3_EN)

HSDMA Ch.3 Trigger Flag Register (pHS3_TF)

Size

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HSDMA

Address

0x00048262

0x00048264

0x00048266

0x00048268

0x0004826A

0x00048272

0x00048274

0x00048276

0x00048278

0x0004827A

0x00048282

0x00048284

0x00048286

0x00048288

0x0004828A

0x00048292

0x00048294

0x00048296

0x00048298

0x0004829A

0x0004829C

Function

Selects Ch.0 ADV mode functions.

Sets Ch.0 low-order source address for ADV mode.

Sets Ch.0 high-order source address for ADV mode.

Sets Ch.0 low-order destination address for ADV

mode.

Sets Ch.0 high-order destination address for ADV

mode.

Selects Ch.1 ADV mode functions.

Sets Ch.1 low-order source address for ADV mode.

Sets Ch.1 high-order source address for ADV mode.

Sets Ch.1 low-order destination address for ADV

mode.

Sets Ch.1 high-order destination address for ADV

mode.

Selects Ch.2 ADV mode functions.

Sets Ch.2 low-order source address for ADV mode.

Sets Ch.2 high-order source address for ADV mode.

Sets Ch.2 low-order destination address for ADV

mode.

Sets Ch.2 high-order destination address for ADV

mode.

Selects Ch.3 ADV mode functions.

Sets Ch.3 low-order source address for ADV mode.

Sets Ch.3 high-order source address for ADV mode.

Sets Ch.3 low-order destination address for ADV

mode.

Sets Ch.3 high-order destination address for ADV

mode.

Selects standard or advanced mode.

HSDMA Ch.0 Control Register (pHS0_ADVMODE) for

ADV mode

HSDMA Ch.0 Low-Order Source Address Setup Register

(pHS0_AD_SADR) for ADV mode

HSDMA Ch.0 High-Order Source Address Setup

HSDMA Ch.0 Low-Order Destination Address Setup

HSDMA Ch.0 High-Order Destination Address Setup

HSDMA Ch.1 Control Register (pHS1_ADVMODE) for

ADV mode

HSDMA Ch.1 Low-Order Source Address Setup Register

(pHS1_AD_SADR) for ADV mode

HSDMA Ch.1 High-Order Source Address Setup

HSDMA Ch.1 Low-Order Destination Address Setup

HSDMA Ch.1 High-Order Destination Address Setup

HSDMA Ch.2 Control Register (pHS2_ADVMODE) for

ADV mode

HSDMA Ch.2 Low-Order Source Address Setup Register

(pHS2_AD_SADR) for ADV mode

HSDMA Ch.2 High-Order Source Address Setup

HSDMA Ch.2 Low-Order Destination Address Setup

HSDMA Ch.2 High-Order Destination Address Setup

HSDMA Ch.3 Control Register (pHS3_ADVMODE) for

ADV mode

HSDMA Ch.3 Low-Order Source Address Setup Register

(pHS3_AD_SADR) for ADV mode

HSDMA Ch.3 High-Order Source Address Setup

HSDMA Ch.3 Low-Order Destination Address Setup

HSDMA Ch.3 High-Order Destination Address Setup

HSDMA STD/ADV Mode Select Register

(pHS_CNTLMODE)

Size

The following describes each HSDMA control register.

The HSDMA control registers are mapped in the 16-bit device area from 0x48220 to 0x4829C, and can be accessed

in units of half-words or bytes.

Note: When setting the HSDMA control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-26 EPSON S1C33401 TECHNICAL MANUAL

0x48220–0x48250: HSDMA Ch.x Transfer Counter Registers (pHSx_CNT)

Name

Address

TCx_L7

TCx_L6

TCx_L5

TCx_L4

TCx_L3

TCx_L2

TCx_L1

TCx_L0

BLKLENx7

BLKLENx6

BLKLENx5

BLKLENx4

BLKLENx3

BLKLENx2

BLKLENx1

BLKLENx0

D15

D14

D13

D12

D11

D10

Ch.x transfer c

ounter[7:0]

(block transfer mode)

Ch.x transfer counter[15:8]

(single/successive transfer mode)

Ch.

block length

(block transfer mode)

Ch.x transfer counter[7:0]

(single/successive transfer mode)

R/W

0048220

0048250

(HW)

HSDMA Ch.x

transfer

counter

(pHSx_CNT)

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48220 HSDMA Ch.0 Transfer Counter Register (pHS0_CNT)

0x48230 HSDMA Ch.1 Transfer Counter Register (pHS1_CNT)

0x48240 HSDMA Ch.2 Transfer Counter Register (pHS2_CNT)

0x48250 HSDMA Ch.3 Transfer Counter Register (pHS3_CNT)

D[15:8] TCx_L[7:0]: Ch.x Transfer Counter Bits

Set the data transfer count. (Default: 0x00)

In block transfer mode, TCx_L[7:0] is bits[7:0] of the transfer counter. In single or successive transfer

mode, TCx_L[7:0] is bits[15:8] of the transfer counter.

This counter is decremented each time a DMA transfer in the corresponding channel is performed.

When the counter reaches 0, a cause of interrupt is generated. In single-address mode, the end-of-

transfer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a

DMA request is accepted and the counter is decremented to 0xFFFF (or 0xFFFFFF).

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing and reading to

and from the counter.

D[7:0] BLKLENx[7:0]: Ch.x Block Length Bits

In block transfer mode, these bits are used to specify a transfer block size. (Default: 0x00)

A transfer operation invoked by one trigger is completed after transferring one block of data of the size

set by BLKLENx[7:0].

In single or successive transfer mode, these bits are used to specify the 8 low-order bits of the transfer

counter.

Note: When performing data transfer in block transfer mode, the block size must not be set to 0.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

S1C33401 TECHNICAL MANUAL EPSON III-4-27

III

HSDMA

0x48222–0x48252: HSDMA Ch.x Control Registers

Name

Address

–

DUALMx

DxDIR

–

TCx_H7

TCx_H6

TCx_H5

TCx_H4

TCx_H3

TCx_H2

TCx_H1

TCx_H0

D15

D14

D13–8

Ch.x address mode selection

D) Invalid

S) Ch.x transfer direction control

reserved

Ch.x transfer counter[15:8]

(block transfer mode)

Ch.x transfer counter[23:16]

(single/successive transfer mode)

1Dual addr 0Single addr

Memory WR

Memory RD

–

R/W

–

R/W

–

R/W

0 when being read.

0048222

0048252

(HW)

HSDMA Ch.x

control register

Note:

D) Dual address

mode

S) Single

address

mode

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48222 HSDMA Ch.0 Control Register

0x48232 HSDMA Ch.1 Control Register

0x48242 HSDMA Ch.2 Control Register

0x48252 HSDMA Ch.3 Control Register

D15 DUALMx: Ch.x Address Mode Select Bit

Select an address mode.

1 (R/W): Dual-address mode

0 (R/W): Single-address mode (default)

When 1 is written to DUALMx, the HSDMA channel enters dual-address mode that allows specification

of source and destination addresses. When 0 is written, the HSDMA channel enters single-address

mode for high-speed data transfer between the external memory and an I/O device.

D14 DxDIR: Ch.x Transfer Direction Control Bit

Control the direction of data transfer in single-address mode.

1 (R/W): Memory write

0 (R/W): Memory read (default)

Data transfer from an external I/O device to external memory (or an external/internal I/O) is performed

by writing 1 to DxDIR. Data transfer from external memory (or an external/internal I/O) to an external

I/O is performed by writing 0.

This bit is effective only in single-address mode.

D[13:8] Reserved

D[7:0] TCx_H[7:0]: Ch.x Transfer Counter Bits

Set the data transfer count. (Default: 0x00)

In block transfer mode, TCx_H[7:0] is bits[15:8] of the transfer counter. In single or successive transfer

mode, TCx_H[7:0] is bits[23:16] of the transfer counter.

This counter is decremented each time a DMA transfer in the corresponding channel is performed.

When the counter reaches 0, a cause of interrupt is generated. In single-address mode, the end-of-

transfer signal is output from the #DMAENDx pin at the same time. Even when the counter is 0, a

DMA request is accepted and the counter is decremented to 0xFFFF (or 0xFFFFFF).

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing and reading to

and from the counter.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-28 EPSON S1C33401 TECHNICAL MANUAL

0x48224–0x48254: HSDMA Ch.x Low-Order Source Address Setup

Registers (pHSx_SADR)

Name

Address

SxADRL15

SxADRL14

SxADRL13

SxADRL12

SxADRL11

SxADRL10

SxADRL9

SxADRL8

SxADRL7

SxADRL6

SxADRL5

SxADRL4

SxADRL3

SxADRL2

SxADRL1

SxADRL0

D15

D14

D13

D12

D11

D10

D) Ch.x source address[15:0]

S) Ch.x memory address[15:0]

R/W

0048224

0048254

(HW)

HSDMA Ch.x

low-order

source address

setup register

(pHSx_SADR)

Note:

D) Dual address

mode

S) Single

address

mode

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48224 HSDMA Ch.0 Low-Order Source Address Setup Register (pHS0_SADR)

0x48234 HSDMA Ch.1 Low-Order Source Address Setup Register (pHS1_SADR)

0x48244 HSDMA Ch.2 Low-Order Source Address Setup Register (pHS2_SADR)

0x48254 HSDMA Ch.3 Low-Order Source Address Setup Register (pHS3_SADR)

D[15:0] SxADRL[15:0]: Ch.x Source Address[15:0] (for standard mode)

In dual-address mode, these bits are used to specify a source address. In single-address mode, an

external memory address at the destination or source of transfer is specified.

Use SxADRL[15:0] to set the 16 low-order bits of the address.

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing or reading to

and from these registers.

The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) or

SxID (D4/0x48262 + 0x10•x)) according to the transfer data size each time a DMA transfer in the

corresponding channel is performed.

Notes: • The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses

even if they are located in the area for which the MMU is enabled for use.

• The following areas cannot be used for DMA transfer:

Dual-address mode: Area 0 (A0RAM), Area 2

Single-address mode: Area 0 (A0RAM), Area 1 (peripherals), Area 2, Area 3 (A3RAM)

• Single-address mode does not allow data transfer between memory devices.

• Single-address mode does not support the external memory area that is configured for

SDRAM.

• Use SxADRL[15:0] (D[15:0]/0x48264 + 0x10•x) and SxADRH[15:0] (D[15:0]/0x48266 +

0x10•x) for specifying an address in advanced mode.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

S1C33401 TECHNICAL MANUAL EPSON III-4-29

III

HSDMA

0x48226–0x48256: HSDMA Ch.x High-Order Source Address Setup

Registers

Name

Address

–

DATSIZEx

SxIN1

SxIN0

SxADRH11

SxADRH10

SxADRH9

SxADRH8

SxADRH7

SxADRH6

SxADRH5

SxADRH4

SxADRH3

SxADRH2

SxADRH1

SxADRH0

D15

D14

D13

D12

D11

D10

reserved

Ch.x transfer data size

D) Ch.x source address control

S) Ch.x memory address control

D) Ch.x source address[27:16]

S) Ch.x memory address[27:16]

–

R/W

0 when being read.

0048226

0048256

(HW)

1Half word 0Byte

HSDMA Ch.x

high-order

source address

setup register

Note:

D) Dual address

mode

S) Single

address

mode

SxIN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

–

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48226 HSDMA Ch.0 High-Order Source Address Setup Register

0x48236 HSDMA Ch.1 High-Order Source Address Setup Register

0x48246 HSDMA Ch.2 High-Order Source Address Setup Register

0x48256 HSDMA Ch.3 High-Order Source Address Setup Register

D15 Reserved

D14 DATSIZEx: Ch.x Transfer Data Size Select Bit

Select the data size to be transferred.

1 (R/W): Half-word

0 (R/W): Byte (default)

The transfer data size is set to 16 bits by writing 1 to DATSIZEx and set to 8 bits by writing 0.

Note: In advanced mode, this bit is effective when WORDSIZEx (D0/0x48262 + 0x10•x) = 0. The

setting of this bit is ignored when WORDSIZEx (D0/0x48262 + 0x10•x) = 1 and the transfer

data size is set to 32 bits.

In standard mode, this bit is always effective regardless of the WORDSIZEx (D0/0x48262 +

0x10•x) setting.

D[13:12] SxIN[1:0]: Ch.x Source Address Control Bits

Control the incrementing or decrementing of the memory address.

Table III.4.9.2 Address Control

SxIN1

SxIN0

Address control

Increment without initialization

Increment with initialization

Decrement without initialization

Fixed

(Default: 0b00)

In dual-address mode, this setting applies to the source address. In single-address mode, this setting

applies to the external memory address.

When “Fixed” (00) is selected, the source address is not changed by a data transfer performed. Even

when transferring multiple data, the transfer data is always read from the same address.

When “Increment without initialization” (11) is selected, the source address is incremented by an

amount equal to the data size set by DATSIZEx (D14) or WORDSIZEx (D0/0x48262 + 0x10•x) when

one data transfer is completed.

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III-4-30 EPSON S1C33401 TECHNICAL MANUAL

When “Decrement without initialization” (01) is selected, the source address is decremented in the

same way.

When “Increment with initialization” (10) is selected, the source address is incremented by an amount

equal to the data size set by DATSIZEx (D14) or WORDSIZEx (D0/0x48262 + 0x10•x) when one data

transfer is completed. In single transfer mode, the address that has been incremented during transfer

does not return to the initial value. In successive transfer modes, the incremented address returns to

the initial value when the specified number of transfers is completed. In block transfer mode, the

incremented address returns to the initial value when the block transfer is completed.

Note: In advanced mode, these bits are effective when SxID (D4/0x48262 + 0x10•x) = 0. The

setting of these bits is ignored when SxID (D4/0x48262 + 0x10•x) = 1 and “Decrement with

initialization” is selected.

In standard mode, this bit is always effective regardless of the SxID (D4/0x48262 + 0x10•x)

setting.

D[11:0] SxADRH[11:0]: Ch.x Source Address[27:16] (for standard mode)

In dual-address mode, these bits are used to specify 12 high-order bits of source address. In single-

address mode, 12 high-order bits of external memory address at the destination or source of transfer is

specified.

See SxADRL[15:0] (D[15:0]/0x48224 + 0x10•x) for more information.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

S1C33401 TECHNICAL MANUAL EPSON III-4-31

III

HSDMA

0x48228–0x48258: HSDMA Ch.x Low-Order Destination Address Setup

Registers (pHSx_DADR)

Name

Address

DxADRL15

DxADRL14

DxADRL13

DxADRL12

DxADRL11

DxADRL10

DxADRL9

DxADRL8

DxADRL7

DxADRL6

DxADRL5

DxADRL4

DxADRL3

DxADRL2

DxADRL1

DxADRL0

D15

D14

D13

D12

D11

D10

D) Ch.x destination address[15:0]

S) Invalid

R/W

0048228

0048258

(HW)

HSDMA Ch.x

low-order

destination

address setup

(pHSx_DADR)

Note:

D) Dual address

mode

S) Single

address

mode

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48228 HSDMA Ch.0 Low-Order Destination Address Setup Register (pHS0_DADR)

0x48238 HSDMA Ch.1 Low-Order Destination Address Setup Register (pHS1_DADR)

0x48248 HSDMA Ch.2 Low-Order Destination Address Setup Register (pHS2_DADR)

0x48258 HSDMA Ch.3 Low-Order Destination Address Setup Register (pHS3_DADR)

D[15:0] DxADRL[15:0]: Ch.x Destination Address[15:0] (for standard mode)

In dual-address mode, these bits are used to specify a destination address.

Use DxADRL[15:0] to set the 16 low-order bits of the address.

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing or reading to

and from these registers.

The address is incremented or decremented (as set by DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) or

DxID (D5/0x48262 + 0x10•x)) according to the transfer data size each time a DMA transfer in the

corresponding channel is performed.

Notes: • In single-address mode, these bits are not used.

• The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses

even if it is located in the area for which the MMU is enabled to use.

• The following areas cannot be specified for destination addresses:

Area 0 (A0RAM), Area 2

• Use DxADRL[15:0] (D[15:0]/0x48268 + 0x10•x) and DxADRH[15:0] (D[15:0]/0x4826A +

0x10•x) for specifying an address in advanced mode.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-32 EPSON S1C33401 TECHNICAL MANUAL

0x4822A–0x4825A: HSDMA Ch.x High-Order Destination Address Setup

Registers

Name

Address

DxMOD1

DxMOD0

DxIN1

DxIN0

DxADRH11

DxADRH10

DxADRH9

DxADRH8

DxADRH7

DxADRH6

DxADRH5

DxADRH4

DxADRH3

DxADRH2

DxADRH1

DxADRH0

D15

D14

D13

D12

D11

D10

Ch.x transfer mode

D) Ch.x destination address

control

S) Invalid

D) Ch.x destination

address[27:16]

S) Invalid

R/W

004822A

004825A

(HW)

HSDMA Ch.x

high-order

destination

address setup

Note:

D) Dual address

mode

S) Single

address

mode

DxMOD[1:0] Mode

Invalid

Block

Successive

Single

DxIN[1:0] Inc/dec

Inc.(no init)

Inc.(init)

Dec.(no init)

Fixed

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x4822A HSDMA Ch.0 High-Order Destination Address Setup Register

0x4823A HSDMA Ch.1 High-Order Destination Address Setup Register

0x4824A HSDMA Ch.2 High-Order Destination Address Setup Register

0x4825A HSDMA Ch.3 High-Order Destination Address Setup Register

D[15:14] DxMOD[1:0]: Ch.x Transfer Mode Select Bits

Select a transfer mode.

Table III.4.9.3 Transfer Mode

DxMOD1

DxMOD0

Mode

Invalid

Block transfer mode

Successive transfer mode

Single transfer mode

(Default: 0b00)

In single transfer mode, a transfer operation invoked by one trigger is completed after transferring one

unit of data of the size set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262 +

0x10•x). In successive transfer mode, data transfer operations are performed by one trigger a number of

times as set by the transfer counter. In block transfer mode, a transfer operation invoked by one trigger

is completed after transferring one block of data of the size set by BLKLENx[7:0] (D[7:0]/0x48220 +

0x10•x).

D[13:12] DxIN[1:0]: Ch.x Destination Address Control Bits

Control the incrementing or decrementing of the memory address.

Table III.4.9.4 Address Control

DxIN1

DxIN0

Address control

Increment without initialization

Increment with initialization

Decrement without initialization

Fixed

(Default: 0b00)

In dual-address mode, this setting applies to the destination address.

When “Fixed” (00) is selected, the destination address is not changed by a data transfer performed.

Even when transferring multiple data, the transfer data is always written to the same address.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

S1C33401 TECHNICAL MANUAL EPSON III-4-33

III

HSDMA

When “Increment without initialization” (11) is selected, the destination address is incremented by an

amount equal to the data size set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262

+ 0x10•x) when one data transfer is completed.

When “Decrement without initialization” (01) is selected, the destination address is decremented in the

same way.

When “Increment with initialization” (10) is selected, the destination address is incremented by an

amount equal to the data size set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262

+ 0x10•x) when one data transfer is completed. In single transfer mode, the address that has been

incremented during transfer does not return to the initial value. In successive transfer modes, the

incremented address returns to the initial value when the specified number of transfers is completed.

In block transfer mode, the incremented address returns to the initial value when the block transfer is

completed.

In single-address mode, these bits are not used.

Note: In advanced mode, these bits are effective when DxID (D5/0x48262 + 0x10•x) = 0. The

setting of these bits is ignored when DxID (D5/0x48262 + 0x10•x) = 1 and “Decrement with

initialization” is selected.

In standard mode, this bit is always effective regardless of the DxID (D5/0x48262 + 0x10•x)

setting.

D[11:0] DxADRH[11:0]: Ch.x Destination Address[27:16] (for standard mode)

In dual-address mode, these bits are used to specify 12 high-order bits of destination address.

See DxADRL[15:0] (D[15:0]/0x48228 + 0x10•x) for more information.

In single-address mode, these bits are not used.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-34 EPSON S1C33401 TECHNICAL MANUAL

0x4822C–0x4825C: HSDMA Ch.x Enable Registers (pHSx_EN)

Name

Address

–

HSx_EN

D15–1

reserved

Ch.x enable 1Enable 0Disable

–

R/W

0 when being read.

004822C

004825C

(HW)

HSDMA Ch.x

enable register

(pHSx_EN)

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x4822C HSDMA Ch.0 Enable Register (pHS0_EN)

0x4823C HSDMA Ch.1 Enable Register (pHS1_EN)

0x4824C HSDMA Ch.2 Enable Register (pHS2_EN)

0x4825C HSDMA Ch.3 Enable Register (pHS3_EN)

D[15:1] Reserved

D0 HSx_EN: Ch.x Enable Bit

Enable a DMA transfer.

1 (R/W): Enable

0 (R/W): Disable (default)

DMA transfer is enabled by writing 1 to this bit.

HSDMA is placed in a state ready to accept a DMA request from the #DMAREQx pin or by the

selected trigger source. DMA transfer is disabled by writing 0 to this bit.

When DMA transfers are completed (transfer counter = 0), HSx_EN is cleared by the hardware.

Be sure to disable DMA transfers (HSx_EN = 0) before setting the transfer condition.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

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III

HSDMA

0x4822E–0x4825E: HSDMA Ch.x Trigger Flag Registers (pHSx_TF)

Name

Address

–

HSx_TF

D15–1

reserved

Ch.x trigger flag clear (writing)

Ch.x trigger flag status (reading)

1Clear 0

No operation

1Set 0Cleared

–

R/W

0 when being read.

004822E

004825E

(HW)

HSDMA Ch.x

trigger flag

(pHSx_TF)

Note: The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x4822E HSDMA Ch.0 Trigger Flag Register (pHS0_TF)

0x4823E HSDMA Ch.1 Trigger Flag Register (pHS1_TF)

0x4824E HSDMA Ch.2 Trigger Flag Register (pHS2_TF)

0x4825E HSDMA Ch.3 Trigger Flag Register (pHS3_TF)

D[15:1] Reserved

D0 HSx_TF: Ch.x Trigger Flag Clear/Status Bit

These bits are used to check and clear the trigger flag status.

1 (R): Trigger flag has been set

0 (R): Trigger flag has been cleared (default)

1 (W): Clear trigger flag

0 (W): Has no effect

The trigger flag is set when a trigger is input to the HSDMA channel and is cleared when the HSDMA

channel starts a data transfer. By reading HSx_TF, the flag status can be checked. Writing 1 to HSx_TF

clears the trigger flag if the DMA transfer has not been started.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-36 EPSON S1C33401 TECHNICAL MANUAL

0x48262–0x48292: HSDMA Ch.x Control Registers (pHSx_ADVMODE)

for ADV mode

Name

Address

–

DxID

SxID

–

WORDSIZEx

D15–6

D3–1

reserved

Ch.x destination address control

S) Invalid

D) Ch.

source address control

S) Ch.

memory address control

reserved

Ch.

transfer data size

1Decrement

(with init.)

0DxIN[1:0]

setting

1Decrement

(with init.)

0SxIN[1:0]

setting

–

R/W

–

R/W

0 when being read.

0048262

0048292

(HW)

HSDMA Ch.x

control register

(pHSx_ADVMODE)

for ADV mode

Note:

D) Dual mode

S) Single mode 1Word 0DATSIZEx

setting

Notes: • This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1).

• The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48262 HSDMA Ch.0 Control Register (pHS0_ADVMODE)

0x48272 HSDMA Ch.1 Control Register (pHS1_ADVMODE)

0x48282 HSDMA Ch.2 Control Register (pHS2_ADVMODE)

0x48292 HSDMA Ch.3 Control Register (pHS3_ADVMODE)

D[15:6] Reserved

D5 DxID: Ch.x Destination Address Control Bit

Enable the address decrement function with initialization for destination address.

1 (R/W): Decrement with initialization

0 (R/W): DxIN[1:0] setting is effective (default)

When this bit is set to 1 in dual-address mode, the destination address decrement function with

initialization is enabled. The destination address is decremented by an amount equal to the data size

set by DATSIZEx (D14/0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262 + 0x10•x) when one data

transfer is completed. In single transfer mode, the address that has been decremented during transfer

does not return to the initial value. In successive transfer modes, the decremented address returns

to the initial value when the specified number of transfers is completed. In block transfer mode, the

decremented address returns to the initial value when the block transfer is completed.

When this bit is set to 0, the condition set by DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) is effective.

In single-address mode, this bit is not used.

D4 SxID: Ch.x Source Address Control Bit

Enable the address decrement function with initialization for source address.

1 (R/W): Decrement with initialization

0 (R/W): SxIN[1:0] setting (default)

In dual-address mode, this setting applies to the source address. In single-address mode, this setting

applies to the external memory address.

When this bit is set to 1, the address decrement function with initialization is enabled. The source/

external memory address is decremented by an amount equal to the data size set by DATSIZEx (D14/

0x48226 + 0x10•x) or WORDSIZEx (D0/0x48262 + 0x10•x) when one data transfer is completed.

In single transfer mode, the address that has been decremented during transfer does not return to the

initial value. In successive transfer modes, the decremented address returns to the initial value when the

specified number of transfers is completed. In block transfer mode, the decremented address returns to

the initial value when the block transfer is completed.

When this bit is set to 0, the condition set by SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) is effective.

D[3:1] Reserved

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

S1C33401 TECHNICAL MANUAL EPSON III-4-37

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HSDMA

D0 WORDSIZEx: Ch.x Transfer Data Size Select Bit

Select the data size to be transferred.

1 (R/W): Word

0 (R/W): DATSIZEx setting is effective (default)

The transfer data size is set to 32 bits by writing 1 to this bit. When this bit is set to 0, the size set by

DATSIZEx (D14/0x48226 + 0x10•x) is effective.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-38 EPSON S1C33401 TECHNICAL MANUAL

0x48264–0x48296: HSDMA Ch.x Source Address Setup Registers

(pHSx_AD_SADR) for ADV mode

Name

Address

SxADRL15

SxADRL14

SxADRL13

SxADRL12

SxADRL11

SxADRL10

SxADRL9

SxADRL8

SxADRL7

SxADRL6

SxADRL5

SxADRL4

SxADRL3

SxADRL2

SxADRL1

SxADRL0

D15

D14

D13

D12

D11

D10

D) Ch.x source address[15:0]

S) Ch.x memory address[15:0]

R/W

0048264

0048294

(HW)

HSDMA Ch.x

low-order

source address

setup register

(pHSx_AD_SADR)

for ADV mode

Note:

D) Dual address

mode

S) Single

address

mode

SxADRH15

SxADRH14

SxADRH13

SxADRH12

SxADRH11

SxADRH10

SxADRH9

SxADRH8

SxADRH7

SxADRH6

SxADRH5

SxADRH4

SxADRH3

SxADRH2

SxADRH1

SxADRH0

D15

D14

D13

D12

D11

D10

D) Ch.x source address[31:16]

S) Ch.x memory address[31:16]

R/W

0048266

0048296

(HW)

HSDMA Ch.x

high-order

source address

setup register

for ADV mode

Note:

D) Dual address

mode

S) Single

address

mode

Notes: • This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1).

• The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48264 HSDMA Ch.0 Low-Order Source Address Setup Register (pHS0_AD_SADR)

0x48266 HSDMA Ch.0 High-Order Source Address Setup Register for ADV mode

0x48274 HSDMA Ch.1 Low-Order Source Address Setup Register (pHS1_AD_SADR)

0x48276 HSDMA Ch.1 High-Order Source Address Setup Register for ADV mode

0x48284 HSDMA Ch.2 Low-Order Source Address Setup Register (pHS2_AD_SADR)

0x48286 HSDMA Ch.2 High-Order Source Address Setup Register for ADV mode

0x48294 HSDMA Ch.3 Low-Order Source Address Setup Register (pHS3_AD_SADR)

0x48296 HSDMA Ch.3 High-Order Source Address Setup Register for ADV mode

D[15:0]/0x48264–0x48294 SxADRL[15:0]: Ch.x Low-Order Source Address[15:0]

D[15:0]/0x48266–0x48296 SxADRH[15:0]: Ch.x High-Order Source Address[31:16]

In dual-address mode, these bits are used to specify a 32-bit source address. In single-address mode, a

32-bit external memory address at the destination or source of transfer is specified.

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing or reading to

and from these registers.

The address is incremented or decremented (as set by SxIN[1:0] (D[13:12]/0x48226 + 0x10•x) or

SxID (D4/0x48262 + 0x10•x)) according to the transfer data size each time a DMA transfer in the

corresponding channel is performed.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

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HSDMA

Notes: • The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses

even if it is located in the area for which the MMU is enabled to use.

• The following areas cannot be used for DMA transfer:

Dual-address mode: Area 0 (A0RAM), Area 2

Single-address mode: Area 0 (A0RAM), Area 1 (peripherals), Area 2, Area 3 (A3RAM)

• Single-address mode does not allow data transfer between memory devices.

• Single-address mode does not support the external memory area that is configured for

SDRAM.

• Use SxADRL[15:0] (D[15:0]/0x48224 + 0x10•x) and SxADRH[11:0] (D[11:0]/0x48226 +

0x10•x) for specifying an address in standard mode.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-40 EPSON S1C33401 TECHNICAL MANUAL

0x48268–0x4829A: HSDMA Ch.x Destination Address Setup Registers

(pHSx_ADV_DADR) for ADV mode

Name

Address

DxADRL15

DxADRL14

DxADRL13

DxADRL12

DxADRL11

DxADRL10

DxADRL9

DxADRL8

DxADRL7

DxADRL6

DxADRL5

DxADRL4

DxADRL3

DxADRL2

DxADRL1

DxADRL0

D15

D14

D13

D12

D11

D10

D) Ch.x destination address[15:0]

S) Invalid

R/W

0048268

0048298

(HW)

HSDMA Ch.x

low-order

destination

address setup

(pHSx_ADV_DADR)

for ADV mode

Note:

D) Dual address

mode

S) Single

address

mode

DxADRH15

DxADRH14

DxADRH13

DxADRH12

DxADRH11

DxADRH10

DxADRH9

DxADRH8

DxADRH7

DxADRH6

DxADRH5

DxADRH4

DxADRH3

DxADRH2

DxADRH1

DxADRH0

D15

D14

D13

D12

D11

D10

Ch.x destination address[31:16]

S) Invalid

R/W

004826A

004829A

(HW)

HSDMA Ch.x

high-order

destination

address setup

for ADV mode

Note:

D) Dual address

mode

S) Single

address

mode

Notes: • This register is effective only in advanced mode (HSDMAADV (D0/0x4829C) = 1).

• The letter ‘x’ in bit names, etc., denotes a channel number from 0 to 3.

0x48268 HSDMA Ch.0 Low-Order Destination Address Setup Register (pHS0_ADV_DADR)

0x4826A HSDMA Ch.0 High-Order Destination Address Setup Register for ADV mode

0x48278 HSDMA Ch.1 Low-Order Destination Address Setup Register (pHS1_ADV_DADR)

0x4827A HSDMA Ch.1 High-Order Destination Address Setup Register for ADV mode

0x48288 HSDMA Ch.2 Low-Order Destination Address Setup Register (pHS2_ADV_DADR)

0x4828A HSDMA Ch.2 High-Order Destination Address Setup Register for ADV mode

0x48298 HSDMA Ch.3 Low-Order Destination Address Setup Register (pHS3_ADV_DADR)

0x4829A HSDMA Ch.3 High-Order Destination Address Setup Register for ADV mode

D[15:0]/0x48268–0x48298 DxADRL[15:0]: Ch.x Destination Address[15:0]

D[15:0]/0x4826A–0x4829A DxADRH[15:0]: Ch.x Destination Address[31:16]

In dual-address mode, these bits are used to specify a 32-bit destination address.

Be sure to disable DMA transfers (HSx_EN (D0/0x4822C + 0x10•x) = 0) before writing or reading to

and from these registers.

The address is incremented or decremented (as set by DxIN[1:0] (D[13:12]/0x4822A + 0x10•x) or

DxID (D5/0x48262 + 0x10•x)) according to the transfer data size each time a DMA transfer in the

corresponding channel is performed.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

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HSDMA

Notes: • In single-address mode, these bits are not used.

• The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses

even if it is located in the area for which the MMU is enabled to use.

• The following areas cannot be specified for destination addresses:

Area 0 (A0RAM), Area 2

• Use DxADRL[15:0] (D[15:0]/0x48228 + 0x10•x) and DxADRH[11:0] (D[11:0]/0x4822A +

0x10•x) for specifying an address in standard mode.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

III-4-42 EPSON S1C33401 TECHNICAL MANUAL

0x4829C: HSDMA STD/ADV Mode Select Register (pHS_CNTLMODE)

Name

Address

–

HSDMAADV

D15–1

reserved

Standard mode/advanced mode

select

–

R/W

0 when being read.

004829C

(HW)

HSDMA

STD/ADV mode

select register

(pHS_CNTLMODE)

–

1Advanced

mode

Standard

mode

D[15:1] Reserved

D0 HSDMAADV: Standard/Advanced Mode Select Bit

Select standard or advanced mode.

1 (R/W): Advanced mode

0 (R/W): Standard mode (default)

The HSDMA in the C33 ADV models is extended from that of the C33 STD models. The C33 ADV

HSDMA has two operating modes, standard (STD) mode of which functions are compatible with the

existing C33 STD models and an advanced (ADV) mode allowing use of the extended functions. Table

III.4.9.5 shows differences between standard mode and advanced mode.

Table III.4.9.5 Differences between Standard Mode and Advanced Mode

Function

Source/destination address bit width

Word (32-bit) data transfer

Address decrement function with initialization

Advanced mode

32 bits

Available

Standard mode

28 bits

Unavailable

To configure the HSDMA in advanced mode, set this bit to 1. The control registers (0x48262–0x4829A)

for the extended functions are enabled to write after this setting.

Notes: • Be sure to use the control registers for advanced mode when the HSDMA is set to advanced

mode.

• Standard or advanced mode currently set is applied to all the HSDMA channels. It cannot

be selected for each channel individually.

III C33 ADV BUS BLOCK: HIGH-SPEED DMA (HSDMA)

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III

HSDMA

III.4.10 Precautions

• When setting the transfer conditions, always make sure the DMA controller is inactive (HSx_EN (D0/0x4822C +

0x10•x) = 0).

∗ HSx_EN: Ch.x Enable Bit in the HSDMA Ch.x Enable Register (D0/0x4822C + 0x10•x)

• After an initial reset, the cause-of-interrupt flag (FHDMx (Dx/0x40281)) becomes indeterminate. Always be sure

to reset the flag to prevent interrupts or IDMA requests from being generated inadvertently.

∗ FHDMx: HSDMA Ch.x Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (Dx/0x40281)

• To prevent an interrupt from being generated repeatedly for the same source, be sure to reset the cause-of-

interrupt flag before setting up the PSR again or executing the reti instruction.

• HSDMA is given higher priority over IDMA (intelligent DMA) and the CPU. However, since HSDMA and

IDMA share the same circuit, HSDMA cannot gain the bus ownership while an IDMA transfer is under way.

Requests for HSDMA invocation that have occurred during an IDMA transfer are kept pending until the IDMA

transfer is completed.

A request for IDMA invocation or an interrupt request that has occurred during a HSDMA transfer are accepted

after completion of the HSDMA transfer.

• In dual-address mode, A0RAM (no-wait RAM built into area 0) cannot be specified as the source or destination

for DMA transfer. A3RAM (area 3 built-in RAM) and the internal peripheral I/O registers (area 1) can be used

for dual-address transfer.

• In single-address mode, A0RAM (no-wait RAM built into area 0), A3RAM (area 3 built-in RAM) and the

internal peripheral I/O registers (area 1) cannot be used for DMA transfer.

• Single-address mode does not allow data transfer between memory devices. An external logic circuit is required

to perform single-address transfer between memory devices.

• Single-address mode does not support the external memory area that is configured for SDRAM.

• The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if they are

located in the area for which the MMU is enabled for use.

• Be sure to disable the HSDMA before setting the chip in SLEEP mode (executing the slp instruction). HALT and

HALT2 mode can be set even if the HSDMA is enabled.

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III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

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III

IDMA

III.5 Intelligent DMA (IDMA)

III.5.1 Functional Outline of IDMA

The C33 ADV Bus Block contains an intelligent DMA (IDMA), a function that allows control information to be

programmed in RAM. Up to 128 channels can be programmed, including 31 channels that are invoked by a cause

of interrupt that occurs in some internal peripheral circuit. Although an additional overhead for loading and storing

control information in RAM may be incurred, this intelligent DMA supports such functions as successive transfers,

block transfers, and linking to another IDMA. IDMA is invoked by a cause of interrupt that occurs in some internal

peripheral circuit or a software trigger, thereby performing a data transfer according to the control information in

RAM. When the transfer is completed, IDMA can generate an interrupt or invoke another IDMA according to link

settings.

Intelligent DMA transfer

Memory,

I/O

(1) The control information stored in the memory is loaded into the IDMA temporary register.

(2) Transfer data is read from the source memory or I/O device.

(3) Transfer data is written to the destination memory or I/O device.

(4) The updated control information in the IDMA temporary register is written back to the memory.

(3)

Destination

Memory,

I/O

(2) (4) (1)

Source

A3RAM or

external

RAM

Control information

Control information transfer

Data transfer

IDMA

ITC

DMA request

#DMAREQx

BBCU

Load/store

(Software

trigger)

Address busDMA address bus

DMA control information

data bus

DMA data transfer

request signal

DMA data transfer

acknowledge signal

DMA control information

transfer request signal

DMA control information

transfer acknowledge signal

Hardware trigger

IDMA Ch. number

Data bus

Figure III.5.1.1 Data and Control Information Flow in Intelligent DMA Transfer

The features of IDMA are outlined below.

• Controller Equivalent to the HSDMA dual-address transfer controller

• Number of channels 128 channels

• Control information Programmable in the RAM

The information table can be stored in the internal memory except A0RAM (no-

wait RAM built into area 0) or in the external RAM.

• Source External memory and internal memory except Area 0 (including peripheral area)

• Destination External memory and internal memory except Area 0 (including peripheral area)

• Transfer data size 8, 16, or 32 bits

• Trigger 1. Software trigger (register control)

2. Hardware trigger (external trigger input, causes of interrupts)

• Transfer mode 1. Single transfer (one unit of data is transferred by one trigger)

2. Successive transfer (specified number of data are transferred by one trigger)

3. Block transfer (data block of the specified size is transferred by one trigger)

• Transfer address control The source and/or destination addresses can be incremented or decremented in

units of the transfer data size upon completion of transfer. In successive or block

transfers, the address can be reset to the initial value upon completion of transfer.

• Programmable link function Any channel can be linked with another to perform data transfer by multiple

channels sequentially.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-2 EPSON S1C33401 TECHNICAL MANUAL

C33 ADV extended functions

In the C33 ADV DMA controller, some IDMA functions have been extended from those of the C33 STD. Table

III.5.1.1 shows differences between C33 STD IDMA and C33 ADV IDMA.

Table III.5.1.1 Differences between C33 STD IDMA and C33 ADV IDMA

Function

Source/destination address bit width

Transfer counter (for single/successive transfer)

Transfer counter (for block transfer)

Block size setup bit width

Transfer data size

Address decrement function with initialization

Control information size per channel

Control information base address

C33 ADV IDMA

32 bits

20 bits

12 bits

32 bits, 16 bits, 8 bits

Available

4 words (128 bits)

32 bits (4-word alignment)

C33 STD IDMA

28 bits

24 bits

16 bits

8 bits

16 bits, 8 bits

Unavailable

3 words (96 bits)

28 bits (word alignment)

Note that the item layout in the control information has been changed along with this functional extension.

Furthermore, the control information is no longer placed in the area 0 built-in RAM (A0RAM).

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IDMA

III.5.2 Programming Control Information

The intelligent DMA operates according to the control information prepared in RAM. Note that the control

information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0) cannot be used to store

control information.

The control information is 4 words (16 bytes) per channel in size, and must be located at continuous addresses

beginning with the base address that is set in the software application as the starting address of channel 0.

Consequently, an area of 512 words (2,048 bytes) in RAM is required in order for all of 128 channels to be used.

The following explains how to set the base address and the contents of control information. Before using IDMA,

make each the settings described below.

III.5.2.1 Setting the Base Address

Set the starting address of control information (starting address of channel 0) to DBASEL[15:0] (D[15:0]/0x48200)

for 16 low-order bits and DBASEH[15:0] (D[15:0]/0x48202) for 16 high-order address bits.

∗ DBASEL[15:0]: IDMA Low-order Base Address Bits in the IDMA Base Address Register 0 (D[15:0]/0x48200)

∗ DBASEH[15:0]: IDMA High-order Base Address Bits in the IDMA Base Address Register 1 (D[15:0]/0x48202)

When initially reset, the base address is set to 0x200003A0.

Notes: • The control information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0)

cannot be used to store control information.

• The address you set in the IDMA base address register must always be 4-word units boundary

address.

• Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base

address. Writing to the IDMA base address register is ignored when the DMA transfer

is enabled (IDMAEN (D0/0x48205) = 1). When the register is read, the read data is

indeterminate.

∗ IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205)

III.5.2.2 Control Information

Write the control information for the IDMA channels used to RAM.

The addresses at which the control information of each channel is placed are determined by the base address and a

channel number.

Starting address of channel = base address + (channel number × 16 [bytes])

Note: The control information must be written only when the channel to be set does not start a DMA

transfer. If a DMA transfer starts when the control information is being written to the RAM, proper

transfer cannot be performed. Reading the control information can always be done.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-4 EPSON S1C33401 TECHNICAL MANUAL

The contents of control information (4 words) in each channel are shown in the table below.

Table III.5.2.2.1 IDMA Control Information

Word

1st

2nd

3rd

4th

Bit

D31

D30–24

D23–18

D17–16

D15

D14–12

D11

D10–8

D7–6

D5–4

D3–1

D31–12

D11–0

D31–0

Function

IDMA link enable 1 = Enabled, 0 = Disabled

IDMA link field

–

Data size control (Do not set to 11.)

DATSIZ1 DATSIZ0 Setting contents

1 0 Word (32 bits)

0 1 Half-word (16 bits)

0 0 Byte (8 bits)

–

Source address control (Do not set to others.)

SRINC2 SRINC1 SRINC0 Setting contents

100Address decrement with initialization

(address is reset in successive or block transfer mode)

0 1 1 Address increment without initialization

(address is not reset)

0 1 0 Address increment with initialization

(address is reset in successive or block transfer mode)

0 0 1 Address decrement without initialization

(address is not reset)

0 0 0 Address fixed

–

Destination address control (Do not set to others.)

DSINC2 DSINC1 DSINC0 Setting contents

100Address decrement with initialization

(address is reset in successive or block transfer mode)

0 1 1 Address increment without initialization

(address is not reset)

0 1 0 Address increment with initialization

(address is reset in successive or block transfer mode)

0 0 1 Address decrement without initialization

(address is not reset)

0 0 0 Address fixed

–

Transfer mode (Do not set to 11.)

DMOD1 DMOD0 Setting contents

1 0 Block transfer mode

0 1 Successive transfer mode

0 0 Single transfer mode

–

End-of-transfer interrupt enable 1 = Enabled, 0 = Disabled

Transfer counter (block transfer mode)

Transfer counter - 20 high-order bits (single or successive transfer mode)

Block size (block transfer mode)

Transfer counter - 12 low-order bits (single or successive transfer mode)

Source address

Destination address

Name

LNKEN

LNKCHN[6:0]

reserved

DATSIZ[1:0]

reserved

SRINC[2:0]

reserved

DSINC[2:0]

reserved

DMOD[1:0]

reserved

DINTEN

TC[19:0]

BLKLEN[11:0]

SRADR[31:0]

DSADR[31:0]

LNKEN: IDMA link enable (D31/1st word)

If this bit remains set (= 1), the IDMA channel that is set in the IDMA link field is invoked after the completion

of a DMA transfer in this channel. DMA transfers in multiple channels can be performed successively by

merely triggering the first channel to be executed. There is no limit to the number of channels linked. Set this

link in order of the IDMA channels you want to be executed.

If this bit is 0, IDMA is completed by merely executing a DMA transfer in this channel.

LNKCHN[6:0]: IDMA link field (D[30:24]/1st word)

If you want IDMA to be linked, set the channel numbers (0 to 127) to be executed next.

The data in this field is valid only when LNKEN = 1.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

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IDMA

DATSIZ[1:0]: Data size control (D[17:16]/1st word)

Set the unit size of data to be transferred.

Table III.5.2.2.2 Transfer Data Size

DATSIZ1

DATSIZ0

Transfer data size

Invalid

Word (32 bits)

Half-word (16 bits)

Byte (8 bits)

SRINC[2:0]: Source address control (D[14:12]/1st word)

Set the source address control condition.

• SRINC[2:0] = 000: Address fixed

The source address is not changed by a data transfer performed. Even when transferring multiple data, the

transfer data is always read from the same address.

• SRINC[2:0] = 011: Address increment without initialization (address is not reset)

The source address is incremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. The address that has been incremented during transfer does not return to the initial

value.

• SRINC[2:0] = 001: Address decrement without initialization (address is not reset)

The source address is decremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. The address that has been decremented during transfer does not return to the initial

value.

• SRINC[2:0] = 010: Address increment with initialization

(address is reset in successive or block transfer mode)

The source address is incremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. In single transfer mode, the address that has been incremented during transfer

does not return to the initial value. In successive transfer modes, the incremented address returns to the

initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the

incremented address returns to the initial value when the block transfer is completed.

• SRINC[2:0] = 100: Address decrement with initialization

(address is reset in successive or block transfer mode)

The source address is decremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. In single transfer mode, the address that has been decremented during transfer

does not return to the initial value. In successive transfer modes, the decremented address returns to the

initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the

decremented address returns to the initial value when the block transfer is completed.

• SRINC[2:0] = Other than above: settings are prohibited

Note: In single transfer mode, the address does not return to the initial value even if a condition with

address initialization is specified.

DSINC[2:0]: Destination address control (D[10:8]/1st word)

Set the destination address control condition.

• DSINC[2:0] = 000: Address fixed

The destination address is not changed by a data transfer performed. Even when transferring multiple data,

the transfer data is always written to the same address.

• DSINC[2:0] = 011: Address increment without initialization (address is not reset)

The destination address is incremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. The address that has been incremented during transfer does not return to the initial

value.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-6 EPSON S1C33401 TECHNICAL MANUAL

• DSINC[2:0] = 001: Address decrement without initialization (address is not reset)

The destination address is decremented by an amount equal to the data size set by DATSIZ when one data

transfer is completed. The address that has been decremented during transfer does not return to the initial

value.

• DSINC[2:0] = 010: Address increment with initialization

(address is reset in successive or block transfer mode)

The destination address is incremented by an amount equal to the data size set by DATSIZ when one

data transfer is completed. In single transfer mode, the address that has been incremented during transfer

does not return to the initial value. In successive transfer modes, the incremented address returns to the

initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the

incremented address returns to the initial value when the block transfer is completed.

• DSINC[2:0] = 100: Address decrement with initialization

(address is reset in successive or block transfer mode)

The destination address is decremented by an amount equal to the data size set by DATSIZ when one

data transfer is completed. In single transfer mode, the address that has been decremented during transfer

does not return to the initial value. In successive transfer modes, the decremented address returns to the

initial value when the specified number of transfers is completed (CNT = 0). In block transfer mode, the

decremented address returns to the initial value when the block transfer is completed.

• DSINC[2:0] = Other than above: settings are prohibited

Note: In single transfer mode, the address does not return to the initial value even if a condition with

address initialization is specified.

DMOD[1:0]: Transfer mode (D[5:4]/1st word)

Use these bits to set the desired transfer mode.

The transfer modes are outlined below (to be detailed later):

• DMOD[1:0] = 00: Single transfer mode

In this mode, a transfer operation invoked by one trigger is completed after transferring one unit of data

of the size set by DATSIZ. If data transfer need to be performed a number of times as set by the transfer

counter, an equal number of triggers are required.

• DMOD[1:0] = 01: Successive transfer mode

In this mode, data transfer operations are performed by one trigger a number of times as set by the transfer

counter. The transfer counter is decremented to 0 each time data is transferred.

• DMOD[1:0] = 10: Block transfer mode

In this mode, a transfer operation invoked by one trigger is completed after transferring one block of data of

the size set by BLKLEN. If a block transfer need to be performed a number of times as set by the transfer

counter, an equal number of triggers are required.

• DMOD[1:0] = 11: Settings are prohibited

DINTEN: End-of-transfer interrupt enable (D0/1st word)

If this bit is left set (= 1), when the transfer counter reaches 0, an interrupt request to the CPU is generated

based on the cause-of-interrupt flag by which IDMA has been invoked.

If this bit is 0, no interrupt request to the CPU is generated even when the transfer counter has reached 0.

TC[19:0]: Transfer counter (D[31:12]/2nd word)

In block transfer mode, a transfer count can be specified using up to 20 bits. Set this value here.

In single transfer and successive transfer modes, a transfer count can be specified using up to 32 bits. Set a

20-bit high-order value here.

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IDMA

BLKLEN[11:0]: Block size/transfer counter (D[11:0]/2nd word)

In block transfer mode, set the size of a block that is transferred in one operation (in units of DATSIZ). In single

transfer and successive transfer modes, set an 12-bit low-order value for the transfer count here.

Note: The transfer count and block size thus set is decremented according to the transfers performed. If

the transfer count is set to 0, it is decremented to all Fs by the first transfer performed. This means

that you have set the maximum value that is determined by the number of bits available.

SRADR[31:0]: Source address (D[31:0]/3rd word)

Use these bits to set the starting address at the source of transfer. The content set here is updated according to

the setting of SRINC.

DSADR[31:0]: Destination address (D[31:0]/4th word)

Use these bits to set the starting address at the destination of transfer. The content set here is updated according

to the setting of DSINC.

Notes: • The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses

even if it is located in the area for which the MMU is enabled to use.

• Area 0 (A0RAM) and Area 2 cannot be used for IDMA transfer and storing control information.

• Since the control information is placed in RAM, it can be rewritten. However, before rewriting

the content of this information, make sure that no DMA transfer is generated in the channel

whose information you are going to rewrite.

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III.5.3 IDMA Invocation

The triggers by which IDMA is invoked have the following three causes:

1. Cause of interrupt in internal peripheral circuits (hardware trigger)

2. Trigger in the software application

3. Link setting

Enabling/disabling DMA transfer

The IDMA controller is enabled by writing 1 to the IDMA enable bit IDMAEN (D0/0x48205), and is ready to

accept the triggers described above. However, before enabling a DMA transfer, be sure to set the base address

and the control information for the channel to be invoked correctly. If IDMAEN (D0/0x48205) is set to 0, no

IDMA invocation request is accepted.

∗ IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205)

IDMA invocation by a cause of interrupt in internal peripheral circuits

Some internal peripheral circuits that have an interrupt generating function can invoke IDMA by a cause

of interrupt in that circuit. The IDMA channel numbers corresponding to such IDMA invocation are

predetermined. The relationship between the causes of interrupt that have this function and the IDMA channels

is shown in Table III.5.3.1.

Table III.5.3.1 Interrupt Causes Used to Invoke IDMA

Peripheral circuit

I/O Ports

High-speed DMA

16-bit timers 0–5

8-bit timers 0–3

Serial interface

Ch.0–Ch.1

A/D converter

I/O Ports

8-bit timers 4–5

Serial interface

Ch.2–Ch.3

Cause of interrupt

Port input 0

Port input 1

Port input 2

Port input 3

Ch.0, end of transfer

Ch.1, end of transfer

Timer 0 comparison B

Timer 0 comparison A

Timer 1 comparison B

Timer 1 comparison A

Timer 2 comparison B

Timer 2 comparison A

Timer 3 comparison B

Timer 3 comparison A

Timer 4 comparison B

Timer 4 comparison A

Timer 5 comparison B

Timer 5 comparison A

Timer 0 underflow

Timer 1 underflow

Timer 2 underflow

Timer 3 underflow

Ch.0 receive buffer full

Ch.0 transmit buffer empty

Ch.1 receive buffer full

Ch.1 transmit buffer empty

End of A/D conversion

Port input 4

Port input 5

Port input 6

Port input 7

Timer 4 underflow

Timer 5 underflow

Ch.2 receive buffer full

Ch.2 transmit buffer empty

Ch.3 receive buffer full

Ch.3 transmit buffer empty

IDMA enable bit

DEP0 (D0/0x40294)

DEP1 (D1/0x40294)

DEP2 (D2/0x40294)

DEP3 (D3/0x40294)

DEHDM0 (D4/0x40294)

DEHDM1 (D5/0x40294)

DE16TU0 (D6/0x40294)

DE16TC0 (D7/0x40294)

DE16TU1 (D0/0x40295)

DE16TC1 (D1/0x40295)

DE16TU2 (D2/0x40295)

DE16TC2 (D3/0x40295)

DE16TU3 (D4/0x40295)

DE16TC3 (D5/0x40295)

DE16TU4 (D6/0x40295)

DE16TC4 (D7/0x40295)

DE16TU5 (D0/0x40296)

DE16TC5 (D1/0x40296)

DE8TU0 (D2/0x40296)

DE8TU1 (D3/0x40296)

DE8TU2 (D4/0x40296)

DE8TU3 (D5/0x40296)

DESRX0 (D6/0x40296)

DESTX0 (D7/0x40296)

DESRX1 (D0/0x40297)

DESTX1 (D1/0x40297)

DEADE (D2/0x40297)

DEP4 (D4/0x40297)

DEP5 (D5/0x40297)

DEP6 (D6/0x40297)

DEP7 (D7/0x40297)

DE8TU4 (D0/0x4029C)

DE8TU5 (D1/0x4029C)

DESRX2 (D2/0x4029C)

DESTX2 (D3/0x4029C)

DESRX3 (D4/0x4029C)

DESTX3 (D5/0x4029C)

IDMA request bit

RP0 (D0/0x40290)

RP1 (D1/0x40290)

RP2 (D2/0x40290)

RP3 (D3/0x40290)

RHDM0 (D4/0x40290)

RHDM1 (D5/0x40290)

R16TU0 (D6/0x40290)

R16TC0 (D7/0x40290)

R16TU1 (D0/0x40291)

R16TC1 (D1/0x40291)

R16TU2 (D2/0x40291)

R16TC2 (D3/0x40291)

R16TU3 (D4/0x40291)

R16TC3 (D5/0x40291)

R16TU4 (D6/0x40291)

R16TC4 (D7/0x40291)

R16TU5 (D0/0x40292)

R16TC5 (D1/0x40292)

R8TU0 (D2/0x40292)

R8TU1 (D3/0x40292)

R8TU2 (D4/0x40292)

R8TU3 (D5/0x40292)

RSRX0 (D6/0x40292)

RSTX0 (D7/0x40292)

RSRX1 (D0/0x40293)

RSTX1 (D1/0x40293)

RADE (D2/0x40293)

RP4 (D4/0x40293)

RP5 (D5/0x40293)

RP6 (D6/0x40293)

RP7 (D7/0x40293)

R8TU4 (D0/0x4029B)

R8TU5 (D1/0x4029B)

RSRX2 (D2/0x4029B)

RSTX2 (D3/0x4029B)

RSRX3 (D4/0x4029B)

RSTX3 (D5/0x4029B)

IDMA Ch.

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IDMA

Peripheral circuit

I/O Ports

16-bit timers 6–9

Cause of interrupt

Port input 8

Port input 9

Port input 10

Port input 11

Port input 12

Port input 13

Port input 14

Port input 15

Timer 6 comparison B

Timer 6 comparison A

Timer 7 comparison B

Timer 7 comparison A

Timer 8 comparison B

Timer 8 comparison A

Timer 9 comparison B

Timer 9 comparison A

IDMA enable bit

DEP8 (D0/0x402AE)

DEP9 (D1/0x402AE)

DEP10 (D2/0x402AE)

DEP11 (D3/0x402AE)

DEP12 (D4/0x402AE)

DEP13 (D5/0x402AE)

DEP14 (D6/0x402AE)

DEP15 (D7/0x402AE)

DE16TU6 (D0/0x402AF)

DE16TC6 (D1/0x402AF)

DE16TU7 (D2/0x402AF)

DE16TC7 (D3/0x402AF)

DE16TU8 (D4/0x402AF)

DE16TC8 (D5/0x402AF)

DE16TU9 (D6/0x402AF)

DE16TC9 (D7/0x402AF)

IDMA request bit

RP8 (D0/0x402AC)

RP9 (D1/0x402AC)

RP10 (D2/0x402AC)

RP11 (D3/0x402AC)

RP12 (D4/0x402AC)

RP13 (D5/0x402AC)

RP14 (D6/0x402AC)

RP15 (D7/0x402AC)

R16TU6 (D0/0x402AD)

R16TC6 (D1/0x402AD)

R16TU7 (D2/0x402AD)

R16TC7 (D3/0x402AD)

R16TU8 (D4/0x402AD)

R16TC8 (D5/0x402AD)

R16TU9 (D6/0x402AD)

R16TC9 (D7/0x402AD)

IDMA Ch.

These causes of interrupt are used in common for interrupt requests and IDMA invocation requests.

To invoke IDMA upon the occurrence of a cause of interrupt, set the corresponding bits of the IDMA request

and IDMA enable registers shown in the table by writing 1. Then when a cause of interrupt occurs, an interrupt

request to the CPU is kept pending and the corresponding IDMA channel is invoked.

The cause-of-interrupt flag that has been set to 1 remains set until the DMA transfer invoked by it is completed.

If the following two conditions are met when one DMA transfer is completed, an interrupt request is generated

without resetting the cause-of-interrupt flag.

• The transfer counter has reached 0.

• DINTEN in control information is set to 1 (interrupt enabled).

In this case, the IDMA request register is cleared to 0. Therefore, if IDMA needs to be invoked when a cause of

interrupt occurs next time, this register must be set up again. To prevent unwanted IDMA requests from being

generated, this setting must be performed before enabling interrupts and after resetting the cause-of-interrupt

flag. The IDMA enable bit is not cleared and remains set to 1.

If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that

no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain

set to 1.

When DINTEN in control information has been set to 0, the cause-of-interrupt flag is reset even if the transfer

counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the

IDMA enable bit is cleared.

If the IDMA request register bit is left reset to 0, the relevant cause of interrupt generates an interrupt request

and not an IDMA request.

The control registers (interrupt enable register and interrupt priority register) corresponding to the cause of

interrupt do not affect IDMA invocation. IDMA can be invoked even if the interrupt enable bit in ITC is set to

0 (interrupt disabled). However, these register must be set to enable the interrupt when generating the interrupt

after completing the DMA transfer.

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IDMA invocation by a trigger in the software application

All IDMA channels for which control information is set, including those corresponding to causes of interrupt

described above, can be invoked by a trigger in the software application.

When the IDMA channel number to be invoked (0 to 127) is written to DCHN[6:0] (D[6:0]/0x48204) and

DSTART (D7/0x48204) is set to 1 after setting IDMAEN (D0/0x48205) to 1, the specified IDMA channel

starts a DMA transfer.

∗ DCHN[6:0]: IDMA Channel Number Set-up Bits in the IDMA Start Register (D[6:0]/0x48204)

∗ DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204)

DSTART remains set (= 1) during a DMA transfer and is reset to 0 in hardware when one DMA transfer

operation is completed.

Do not modify these bits during a DMA transfer.

If DINTEN is set to 1 (interrupt enabled), an interrupt factor for the completion of IDMA transfer is generated

when one DMA transfer is completed.

IDMA invocation by link setting

If LNKEN in the control information is set to 1 (link enabled), the IDMA channel that is set in the IDMA link

field “LNKCHN” is invoked successively after a DMA transfer in the link-enabled channel is completed.

The interrupt request by the first channel is generated after transfers in all linked channels are completed if the

interrupt conditions are met.

To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in

the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must

be set to 1.

IDMA invocation request during a DMA transfer

An IDMA invocation request to another channel that is generated during a DMA transfer is kept pending until

the DMA transfer that was being executed at the time is completed. Since an invocation request is not cleared,

new requests will be accepted when the DMA transfer under execution is completed.

An IDMA invocation request to the same channel cannot be accepted while the channel is executing a DMA

transfer because the same cause of interrupt is used. Therefore, an interval longer than the DMA transfer period

is required when invoking the same channel.

IDMA invocation request when DMA transfer is disabled

An IDMA invocation request generated when IDMAEN (D0/0x48205) is 0 (DMA transfer disabled) is kept

pending until IDMAEN (D0/0x48205) is set to 1. Since an invocation request is not cleared, it is accepted when

DMA transfer is enabled.

Simultaneous generation of a software trigger and a hardware trigger

When a software trigger and the hardware trigger for the same channel are generated simultaneously, the

software trigger starts IDMA transfer. The IDMA transfer by the hardware trigger is executed after the DMA

transfer by the software trigger is completed.

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IDMA

III.5.4 Operation of IDMA

IDMA has three transfer modes, in each of which data transfer operates differently. Furthermore, a cause of

interrupt is processed differently depending on the type of trigger. IDMA supports only dual-address transfers. It

does not support single-address transfers. The following describes the operation of IDMA in each transfer mode

and how an interrupt factor is processed for each type of trigger.

III.5.4.1 Single Transfer Mode

The channels for which DMOD in control information is set to 00 operate in single transfer mode. In this mode, a

transfer operation invoked by one trigger is completed after transferring one data unit of the size set by DATSIZ. If

a data transfer needs to be performed a number of times as set by the transfer counter, an equal number of triggers

are required. The operation of IDMA in single transfer mode is shown by the flow chart in Figure III.5.4.1.1.

START

END

Calculates address of

control information

Loads channel

control information

Transfers one unit of data

Transfer counter - 1

Saves channel

control information

IDMA interrupt processing

(if interrupt is enabled)

Transfer

counter = 0

Base address + (Channel number × 16)

Bn (4 words) :n = 1–4

C (Data read from source of transfer)

D (Data write to destination of transfer)

Fn (4 words) :n = 1–4

Trigger

B1 B2

B3 B4 CDEF1 F2

Figure III.5.4.1.1 Operation Flow in Single Transfer Mode

(1) When a trigger is accepted, the address for control information is calculated from the base address and channel

number.

(2) Control information is read from the calculated address into the internal temporary register.

(3) Data of the size set in the control information is read from the source address.

(4) The read data is written to the destination address.

(5) The address is incremented or decremented and the transfer counter is decremented.

(6) The modified control information is written to RAM.

(7) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.

Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit

________________________________________________________________________________________

Transfer counter ≠ 0: Reset (0) Not changed (1) Not changed (1)

Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1)

Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0)

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III.5.4.2 Successive Transfer Mode

The channels for which DMOD in control information is set to 01 operate in successive transfer mode. In this

mode, a data transfer is performed by one trigger a number of times as set by the transfer counter. The transfer

counter is decremented to 0 by one transfer executed. The operation of IDMA in successive transfer mode is shown

by the flow chart in Figure III.5.4.2.1.

START

END

Calculates address of

control information

Loads channel

control information

Transfers one unit of data

Transfer counter - 1

Saves channel

control information

IDMA interrupt processing

(if interrupt is enabled)

Transfer

counter = 0

Base address + (Channel number × 16)

Bn (4 words) :n = 1–4

C (Data read from source of transfer)

D (Data write to destination of transfer)

Gn (4 words) :n = 1–4

Trigger

B1 B2 B3

G2 G3

Restores initial values

to address ∗F∗: according to SRINC/DSINC

settings

Figure III.5.4.2.1 Operation Flow in Successive Transfer Mode

(1) When a trigger is accepted, the address for control information is calculated from the base address and channel

number.

(2) Control information is read from the calculated address into the internal temporary register.

(3) Data of the size set in the control information is read from the source address.

(4) The read data is written to the destination address.

(5) The address is incremented or decremented and the transfer counter is decremented.

(6) Steps (3) to (5) are repeated until the transfer counter reaches 0.

(7) If SRINC and/or DSINC are 010 or 100, the address is recycled to the initial value.

(8) The modified control information is written to RAM.

(9) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.

Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit

________________________________________________________________________________________

Transfer counter ≠ 0: Reset (0) Not changed (1) Not changed (1)

Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1)

Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0)

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IDMA

III.5.4.3 Block Transfer Mode

The channels for which DMOD in control information is set to 10 operate in block transfer mode. In this mode,

a transfer operation invoked by one trigger is completed after transferring one block of data of the size set by

BLKLEN. If a block transfer needs to be performed a number of times as set by the transfer counter, an equal

number of triggers are required.

The operation of IDMA in block transfer mode is shown by the flow chart in Figure III.5.4.3.1.

START

END

Calculates address of

control information

Loads channel

control information

Transfers one unit of data

Block size - 1

Restores initial values to

block size and address ∗

IDMA interrupt processing

(if interrupt is enabled)

Block

size = 0

Base address + (Channel number × 16)

Bn (4 words) :n = 1–4

C (Data read from source of transfer)

D (Data write to destination of transfer)

1-block transfer

Trigger

AB1 B2

H2 H4

Transfer counter - 1

Saves channel

control information

Transfer

counter = 0

Hn (4 words) :n = 1–4

∗: according to SRINC/DSINC

settings

Figure III.5.4.3.1 Operation Flow in Block Transfer Mode

(1) When a trigger is accepted, the address for control information is calculated from the base address and channel

number.

(2) Control information is read from the calculated address into the internal temporary register.

(3) Data of the size set in the control information is read from the source address.

(4) The read data is written to the destination address.

(5) The address is incremented or decremented and BLKLEN is decremented.

(6) Steps (3) to (5) are repeated until BLKLEN reaches 0.

(7) If SRINC and/or DSINC are 010 or 100, the address is recycled to the initial value.

(8) The transfer counter is decremented.

(9) The modified control information is written to RAM.

(10) In the case of a hardware trigger, the interrupt control bits are processed before completing IDMA.

Condition Cause-of-interrupt flag IDMA request bit IDMA enable bit

________________________________________________________________________________________

Transfer counter ≠ 0: Reset (0) Not changed (1) Not changed (1)

Transfer counter = 0, DINTEN = 1: Not changed (1) Reset (0) Not changed (1)

Transfer counter = 0, DINTEN = 0: Reset (0) Not changed (1) Reset (0)

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III.5.4.4 Cause-of-Interrupt Processing by Trigger Type

When invoked by a cause of interrupt

The cause-of-interrupt flag by which IDMA has been invoked remains set even during a DMA transfer.

If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is

completed, the cause of interrupt that has invoked IDMA is not reset and an interrupt request is generated. At

the same time, the IDMA request register is cleared to 0. The IDMA enable bit is not cleared and remains set to 1.

If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that

no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain

set to 1.

When DINTEN has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer

counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the

IDMA enable bit is cleared.

Trigger by cause of interrupt

Data transfer

Transfer counter

DINTEN

IDMA request bit

IDMA enable bit

Cause-of-interrupt flag

Interrupt request

Figure III.5.4.4.1 Operation when Invoked by Cause of Interrupt

When IDMA is invoked by a cause of interrupt, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) will

not be set.

∗ FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281)

When invoked by a software trigger

If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is

completed, FIDMA (D4/0x40281) is set, thereby generating an interrupt request.

If the transfer counter is not 0 or DINTEN = 0 (interrupt disabled), FIDMA (D4/0x40281) is not set.

If the cause-of-interrupt flag for the same channel is set during a software-triggered transfer, the IDMA

invocation request by that cause-of-interrupt flag is kept pending. However, the cause-of-interrupt flag will be

reset when the current execution is completed, so there will be no DMA transfer by the cause-of-interrupt flag.

2 1 0

Software trigger

Data transfer

Transfer counter

DINTEN

FIDMA (D4/0x40281)

Interrupt request

1 0

Figure III.5.4.4.2 Operation when Invoked by Software Trigger

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III.5.5 Linking

If the IDMA channel number to be executed next is set in the IDMA link field LNKCHN of control information

and LNKEN is set to 1 (link enabled), DMA successive transfer in that IDMA channel can be performed.

An example of link setting is shown in Figure III.5.5.1.

Ch.3Trigger

After transfer TC = 0

LNKEN = 1

LNKCHN = 5

DMOD = 01

DINTEN = 1

TC = 1024

Ch.5

TC = 7

LNKEN = 1

LNKCHN = 7

DMOD = 00

DINTEN = 1

TC = 8

Ch.7

TC = 0

LNKEN = 0

LNKCHN = 9

DMOD = 10

DINTEN = 1

TC = 1

Figure III.5.5.1 Example of Link Setting

For the above example, IDMA operates as described below.

For trigger in hardware

(1) The IDMA channel 3 is invoked by a cause of interrupt and the DMA transfer that is set is performed.

Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and

DINTEN is set to 1, the cause-of-interrupt flag by which the channel 3 has been invoked remains set.

(2) Next, a DMA transfer is performed via the linked IDMA channel 5. Channel 5 is set for single transfer mode

and the transfer counter in this transfer is decremented by 1.

(3) Finally, a DMA transfer in IDMA channel 7 is performed. Although the channel 7 is set for block transfer

mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers

to be performed is 1.

(4) Since the cause-of-interrupt flag that has invoked IDMA channel 3 in (1) remains set, an interrupt is generated

when the IDMA transfer (channel 7) in (3) is completed. The transfer result does not affect the cause-of-

interrupt flag of channel 3.

To generate an interrupt at the end of an IDMA transfer, the DINTEN (end-of-transfer interrupt enable) bits in

the IDMA control information for the first IDMA channel to be invoked and all the channels to be linked must

be set to 1.

For trigger in the software application

(1) The IDMA channel 3 is invoked by a software trigger DSTART (D7/0x48204) and the DMA transfer that is set

is performed.

Since the IDMA is operating in successive transfer mode and the transfer counter is decremented to 0 and

DINTEN is set to 1, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) is set when the transfer is

completed.

∗ DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204)

∗ FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281)

(2) Next, a DMA transfer is performed in the linked IDMA channel 5. The channel 5 is set for the single transfer

mode and the transfer counter in this transfer is decremented by 1.

(3) Finally, a DMA transfer in IDMA channel 7 is performed. Although channel 7 is set for the block transfer

mode, the transfer counter is decremented to 0 when the transfer is completed because the number of transfers

to be performed is 1. The completion of this transfer also causes FIDMA (D4/0x40281) to be set to 1. However,

FIDMA (D4/0x40281) has already been set when the transfer is completed in (1) above.

(4) Since FIDMA (D4/0x40281) is set, an interrupt request is generated here. In cases when IDMA has been

invoked by a trigger in the software application, if the transfer counter in any one of the linked channels is

decremented to 0 and DINTEN for that channel is set to 1, an interrupt request for the completion of IDMA

transfer is generated when a transfer operation in each of the linked channels is completed. The channel in

which an interrupt request has been generated can be verified by reading out the transfer counter.

Transfer operations in each channel are performed as described earlier.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-16 EPSON S1C33401 TECHNICAL MANUAL

III.5.6 Interrupt Function of Intelligent DMA

IDMA can generate an interrupt that causes invocation of IDMA and an interrupt for the completion of IDMA

transfer itself.

Interrupt when invoked by a cause of interrupt

If the corresponding bits of the IDMA request and interrupt enable registers are left set (= 1), assertion of an

interrupt request is kept pending even when the enabled cause of interrupt has occurred and the IDMA channel

assigned to that cause of interrupt is invoked.

If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer is

completed, the cause of interrupt that has invoked IDMA is not reset and an interrupt request is generated. At

the same time, the IDMA request register is cleared to 0. The IDMA enable bit is not cleared and remains set to 1.

If the transfer counter is not 0, the cause-of-interrupt flag is reset when the DMA transfer is completed, so that

no interrupt is generated. In this case, the IDMA request bit and IDMA enable bit are not cleared and remain

set to 1.

When DINTEN has been set to 0 (interrupt disabled), the cause-of-interrupt flag is reset even if the transfer

counter reaches 0, so that no interrupt is generated. In this case, the IDMA request bit is not cleared but the

IDMA enable bit is cleared.

When IDMA is invoked by a cause of interrupt, the IDMA cause-of-interrupt flag FIDMA (D4/0x40281) will

not be set.

For details about the causes of interrupt that can be used to invoke IDMA and the interrupt control registers,

refer to the descriptions of the peripheral circuits in this manual.

Note that the priority levels of causes of interrupt are set by the interrupt priority register. Refer to Section IV.2,

“Interrupt Controller (ITC).” However, when compared between IDMA and interrupt requests, IDMA is given

higher priority over the other. Consequently, even when a cause of interrupt occurring during an IDMA transfer

has higher priority than the cause of interrupt that invoked the IDMA transfer, an interrupt request for it or a

new IDMA invocation request is not accepted until after the current IDMA transfer is completed.

Software-triggered interrupts

If the transfer counter is decremented to 0 and DINTEN = 1 (interrupt enabled) when one DMA transfer

operation is completed, FIDMA (D4/0x40281) is set, thereby generating an interrupt request. If the transfer

counter is not 0 or DINTEN = 0 (interrupt disabled), FIDMA (D4/0x40281) is not set.

IDMA interrupt control register in the interrupt controller

The following control bits are used to control an interrupt for the completion of IDMA transfer:

∗ FIDMA: IDMA Cause-of-Interrupt Flag in the DMA Interrupt Cause Flag Register (D4/0x40281)

∗ EIDMA: IDMA Interrupt Enable Bit in the DMA Interrupt Enable Register (D4/0x40271)

∗ PDM[2:0]: IDMA Interrupt Level Bits in the IDMA Interrupt Priority Register (D[2:0]/0x40265)

When a DMA transfer in the IDMA channel invoked by a trigger in the software application or subsequent

link is completed and the transfer counter is decremented to 0, the cause-of-interrupt flag for the completion of

IDMA transfer is set to 1. However, this requires as a precondition that interrupt be enabled (DINTEN = 1) in

the control information for that channel. If the interrupt enable register bit remains set (= 1) when the flag is set,

an interrupt request is generated. Interrupts can be disabled by leaving the interrupt enable register bit cleared (=

0). Use the interrupt priority register to set interrupt priority levels (0 to 7). An interrupt request to the CPU is

accepted on condition that no other interrupt request of higher priority is generated.

Furthermore, it is only when the PSR's IE bit = 1 (interrupt enabled) and the set value of IL is smaller than

the IDMA interrupt level which is set by the interrupt priority register that the CPU actually accepts an IDMA

interrupt request.

For details about these interrupt control registers, and for information on device operation when an interrupt

occurs, refer to Section IV.2, “Interrupt Controller (ITC).”

Trap vector

The trap vector address for an interrupt upon completion of IDMA transfer by default is set to 0x20000068.

The trap table base address can be changed using the TTBR registers.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

S1C33401 TECHNICAL MANUAL EPSON III-5-17

III

IDMA

III.5.7 Details of Control Registers

Table III.5.7.1 List of IDMA Registers

Address

0x00048200

0x00048202

0x00048204

0x00048205

Function

Sets 16 low-order bits of IDMA base address.

Sets 16 high-order bits of IDMA base address.

Invokes an IDMA channel.

Enables IDMA.

IDMA Base Address Register 0 (pIDMABASE)

IDMA Base Address Register 1

IDMA Start Register (pIDMA_START)

IDMA Enable Register (pIDMA_EN)

Size

The following describes each IDMA control register.

The IDMA control registers are mapped in the 16-bit device area from 0x48200 to 0x48205, and can be accessed in

units of half-words or bytes.

Note: When setting the IDMA control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-18 EPSON S1C33401 TECHNICAL MANUAL

0x48200: IDMA Base Address Register 0 (pIDMABASE)

0x48202: IDMA Base Address Register 1

Name

Address

DBASEL15

DBASEL14

DBASEL13

DBASEL12

DBASEL11

DBASEL10

DBASEL9

DBASEL8

DBASEL7

DBASEL6

DBASEL5

DBASEL4

DBASEL3

DBASEL2

DBASEL1

DBASEL0

D15

D14

D13

D12

D11

D10

IDMA base address

low-order 16 bits

(Initial value: 0x200003A0)

R/W

Fix at 0.

0048200

(HW)

IDMA

base address

(pIDMABASE)

DBASEH15

DBASEH14

DBASEH13

DBASEH12

DBASEH11

DBASEH10

DBASEH9

DBASEH8

DBASEH7

DBASEH6

DBASEH5

DBASEH4

DBASEH3

DBASEH2

DBASEH1

DBASEH0

D15

D14

D13

D12

D11

D10

IDMA base address

high-order 16 bits

(Initial value: 0x200003A0)

R/W

0048202

(HW)

IDMA

base address

Specify the starting address of the control information to be placed in RAM.

At initial reset, the base address is set to 0x200003A0.

D[15:0]/0x48200 DBASEL[15:0]: IDMA Low-order Base Address Bits

Use DBASEL to set the 16 low-order bits of the base address.

D[15:0]/0x48202 DBASEH[15:0]: IDMA High-order Base Address Bits

Use DBASEH to set the 16 high-order bits of the base address.

In the C33 ADV IDMA, the DBASEH[15:12] bits have been added to extend the base address into 32

bits.

Notes: • The control information must be placed in A3RAM (area 3) or an external RAM. A0RAM (area 0)

cannot be used to store control information.

• The address you set in the IDMA base address registers must always be 4-word units

boundary address.

• These registers cannot be read or written in bytes. The registers must be accessed in words

for read/write operations to address 0x48200, or in half-words for read/write operations to

addresses 0x48200 and 0x48202. Write operations in half-words must be performed in order

of 0x48200 and 0x48202. Read operations in half-words may be performed in any order.

• Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base

address. Writing to the IDMA base address register is ignored when the DMA transfer

is enabled (IDMAEN (D0/0x48205) = 1). When the register is read, the read data is

indeterminate.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

S1C33401 TECHNICAL MANUAL EPSON III-5-19

III

IDMA

0x48204: IDMA Start Register (pIDMA_START)

Name

Address

0 to 127

DSTART

DCHN6

DCHN5

DCHN4

DCHN3

DCHN2

DCHN1

DCHN0

IDMA start

IDMA channel number

1IDMA start 0Stop 0

R/W

0048204

(B)

IDMA start

(pIDMA_START)

D7 DSTART: IDMA Start Control Bit

Use this bit for software trigger and for monitoring the operation of IDMA.

1 (W): Start IDMA

0 (W): Has no effect

1 (R): Operating (only when invoked by software trigger)

0 (R): Idle (default)

When DSTART is set to 1, it functions as a software trigger, invoking the IDMA channel that is set in

the DCHN register.

D[6:0] DCHN[6:0]: IDMA Channel Number Setting Bits

Set the channel numbers (0 to 127) to be invoked by software trigger. (Default: 0)

Note: Do not start an IDMA transfer and change the IDMA channel number simultaneously. When

setting DCHN[6:0], write 0 to DSTART.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-20 EPSON S1C33401 TECHNICAL MANUAL

0x48205: IDMA Enable Register (pIDMA_EN)

Name

Address

–

IDMAEN

D7–1

reserved

IDMA enable (for software trigger) 1Enabled 0Disabled

–

R/W

0 when being read.

0048205

(B)

IDMA enable

(pIDMA_EN)

D[7:1] Reserved

D0 IDMAEN: IDMA Enable Bit

Enable a IDMA transfer.

1 (R/W): Enable

0 (R/W): Disable (default)

IDMA transfer is enabled by writing 1 to this bit and is disabled by writing 0.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

S1C33401 TECHNICAL MANUAL EPSON III-5-21

III

IDMA

III.5.8 Precautions

• The control information must be placed in A3RAM (area 3) or an external RAM. Area 0 (A0RAM) and Area 2

cannot be used for IDMA transfer and storing control information.

• The address you set in the IDMA base address registers must always be 4-word units boundary address.

• Be sure to disable DMA transfers (IDMAEN (D0/0x48205) = 0) before setting the base address. Writing to the

IDMA base address register is ignored when the DMA transfer is enabled (IDMAEN (D0/0x48205) = 1). When

the register is read, the read data is indeterminate.

∗ IDMAEN: IDMA Enable Bit in the IDMA Enable Register (D0/0x48205)

• Do not start an IDMA transfer and change the IDMA channel number simultaneously. When setting DCHN[6:0]

(D[6:0]/0x48204), write 0 to DSTART (D7/0x48204).

∗ DCHN[6:0]: IDMA Channel Number Set-up Bits in the IDMA Start Register (D[6:0]/0x48204)

∗ DSTART: IDMA Start Control Bit in the IDMA Start Register (D7/0x48204)

• The MMU and cache are not used for DMA transfer. Be sure to specify physical addresses even if it is located in

the area for which the MMU is enabled to use.

• Since the control information is placed in RAM, it can be rewritten. However, before rewriting the content of this

information, make sure that no DMA transfer is generated in the channel whose information you are going to

rewrite.

• Since the C33 ADV core performs look-ahead operations, do not specify another channel immediately after a

software trigger has invoked a channel.

• Be sure to disable the IDMA before setting the chip in SLEEP mode (executing the slp instruction). HALT and

HALT2 mode can be set even if the IDMA is enabled.

III C33 ADV BUS BLOCK: INTELLIGENT DMA (IDMA)

III-5-22 EPSON S1C33401 TECHNICAL MANUAL

THIS PAGE IS BLANK.

S1C33401 Technical Manual

IV C33 ADV BASIC PERIPHERAL

BLOCK

IV C33 ADV BASIC PERIPHERAL BLOCK: PREFACE

S1C33401 TECHNICAL MANUAL EPSON IV-1-1

Preface

IV.1 Preface

The S1C33 microcomputers using the C33 ADV Core Macro incorporate a basic peripheral circuit block in which

the basic peripheral circuits are integrated.

Chapter IV describes each peripheral circuit included in this basic peripheral circuit block. Since the descriptions

that follow are for standard specifications common to S1C33 microcomputers, some functions may not be available

or additional functions may be included, depending on the specific C33 model used. For details, see Section I.8,

“Changes from Core/Basic Peripheral Functions.”

Bridge

HBCU

CMU

C33 ADV CPU

8-bit timers

(T8)

OSC3

oscillator,

PLL, SSCG

Card interface

(CARD)

16-bit timers

(T16)

Watchdog

timer

(WDT)

Serial

interface

(SIO)

I/O ports

(PORT)

Prescaler

(PSC)

Interrupt

controller

(ITC)

A/D converter

(ADC)

Standard Peripheral Block

High-speed bus

Figure IV.1.1 Configuration of the C33 ADV Basic Peripheral Circuit Block

IV C33 ADV BASIC PERIPHERAL BLOCK: PREFACE

IV-1-2 EPSON S1C33401 TECHNICAL MANUAL

The following circuit modules are built into the basic peripheral circuit block:

Interrupt controller (ITC)

Controls all interrupts except NMI.

OSC3 oscillator circuit, PLL and SSCG

These circuits generate the system source clock.

Prescaler (PSC)

This programmable frequency divider generates operating clocks for the 8-bit and 16-bit timers, and A/D

converter.

8-bit timer (T8)

Standard specifications incorporate six-channel, 8-bit timers that can be used to generate clocks for internal/

external devices or periodic interrupts at designated intervals.

16-bit timer (T16)

Standard specifications incorporate 10-channel, 16-bit timers that can be used as event counters or to generate

clocks for external output, periodic interrupts at designated intervals, or PWM waveforms compliant with DA16

mode.

Watchdog timer (WDT)

This 30-bit watchdog timer generates nonmaskable interrupts (NMI) when not reset for a set period or more.

Serial interface with FIFO (SIO)

This serial interface with FIFO enables the selection of asynchronous or clock-synchronized communication

mode, as well as an IrDA interface.

Card interface (CARD)

Generates control signals for NAND flash (SmartMedia), CompactFlash, and PC Card interfaces.

Input/output ports (PORT)

Standard specifications support 63 input/output ports. When not being used for the input/output of other

peripheral circuits, these port pins can be used as general-purpose input/output ports.

A/D converter (ADC)

This 10-bit A/D converter can accommodate eight analog inputs.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-1

ITC

IV.2 Interrupt Controller (ITC)

The C33 ADV macro contains an interrupt controller, making it possible to control all interrupts generated by

the internal peripheral circuits. This section explains the functions of this interrupt controller centering around

the method for controlling maskable interrupts. For details about the various causes and conditions under which

interrupts are generated, refer to the description of each peripheral circuit in this manual.

IV.2.1 Outline of Interrupt Functions

IV.2.1.1 Maskable Interrupts

The ITC can handle 64 kinds of maskable interrupts. Table IV.2.1.1.1 shows the trap table in the C33 ADV macro.

Table IV.2.1.1.1 Trap Table

IDMA

Ch.

–

Priority

High

↑

↓

Low

Vector number

(Hex address)

0(Base)

1–3

4(Base+10)

6(Base+18)

0x0 or 0x60000

7(Base+1C)

8–11

12(Base+30)

13(Base+34)

14(Base+38)

15(Base+3C)

16(Base+40)

17(Base+44)

18(Base+48)

19(Base+4C)

20(Base+50)

21(Base+54)

22(Base+58)

23(Base+5C)

24(Base+60)

25(Base+64)

26(Base+68)

27–29

30(Base+78)

31(Base+7C)

32–33

34(Base+88)

35(Base+8C)

36–37

38(Base+98)

39(Base+9C)

40–41

42(Base+A8)

43(Base+AC)

44–45

46(Base+B8)

47(Base+BC)

48–49

50(Base+C8)

51(Base+CC)

52(Base+D0)

53(Base+D4)

54(Base+D8)

55(Base+DC)

Exception/interrupt name

(peripheral circuit)

Reset

reserved

Division by zero

reserved

Address misaligned exception

Debugging exception

NMI

reserved

Software exception 0

Software exception 1

Software exception 2

Software exception 3

Port input interrupt 0

Port input interrupt 1

Port input interrupt 2

Port input interrupt 3

Key input interrupt 0

Key input interrupt 1

High-speed DMA Ch.0

High-speed DMA Ch.1

High-speed DMA Ch.2

High-speed DMA Ch.3

Intelligent DMA

reserved

16-bit timer 0

reserved

16-bit timer 1

reserved

16-bit timer 2

reserved

16-bit timer 3

reserved

16-bit timer 4

reserved

16-bit timer 5

8-bit timers 0–3

Cause of exception/interrupt

Low input to the reset pin

–

Division instruction

–

Memory access instruction

brk instruction, etc.

Low input to the #NMI pin

–

int instruction

Edge (rising or falling) or level (High or Low)

Rising or falling edge

High-speed DMA Ch.0, end of transfer

High-speed DMA Ch.1, end of transfer

High-speed DMA Ch.2, end of transfer

High-speed DMA Ch.3, end of transfer

Intelligent DMA, end of transfer

–

Timer 0 compare-match B

Timer 0 compare-match A

–

Timer 1 compare-match B

Timer 1 compare-match A

–

Timer 2 compare-match B

Timer 2 compare-match A

–

Timer 3 compare-match B

Timer 3 compare-match A

–

Timer 4 compare-match B

Timer 4 compare-match A

–

Timer 5 compare-match B

Timer 5 compare-match A

Timer 0 underflow

Timer 1 underflow

Timer 2 underflow

Timer 3 underflow

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-2 EPSON S1C33401 TECHNICAL MANUAL

IDMA

Ch.

–

Priority

High

↑

↓

Low

Vector number

(Hex address)

56(Base+E0)

57(Base+E4)

58(Base+E8)

60(Base+F0)

61(Base+F4)

62(Base+F8)

63(Base+FC)

64(Base+100)

65(Base+104)

66–67

68(Base+110)

69(Base+114)

70(Base+118)

71(Base+11C)

72(Base+120)

73(Base+124)

74–75

76(Base+130)

77(Base+134)

78(Base+138)

80(Base+140)

81(Base+144)

82(Base+148)

84(Base+150)

85(Base+154)

86(Base+158)

87(Base+15C)

88(Base+160)

89(Base+164)

90(Base+168)

91(Base+16C)

92–93

94(Base+178)

95(Base+17C)

96–97

98(Base+188)

99(Base+18C)

100–101

102(Base+198)

103(Base+19C)

104

–

105

106(Base+1A8)

107(Base+1AC)

Exception/interrupt name

(peripheral circuit)

Serial interface Ch.0

reserved

Serial interface Ch.1

A/D converter

RTC

reserved

Port input interrupt 4

Port input interrupt 5

Port input interrupt 6

Port input interrupt 7

8-bit timers 4–5

reserved

Serial interface Ch.2

reserved

Serial interface Ch.3

reserved

Port input interrupt 8

Port input interrupt 9

Port input interrupt 10

Port input interrupt 11

Port input interrupt 12

Port input interrupt 13

Port input interrupt 14

Port input interrupt 15

reserved

16-bit timer 6

reserved

16-bit timer 7

reserved

16-bit timer 8

reserved

16-bit timer 9

Cause of exception/interrupt

Receive error

Receive buffer full

Transmit buffer empty

–

Receive error

Receive buffer full

Transmit buffer empty

Result out of range (upper-limit and lower-limit)

End of conversion

1/64 second, 1 second, 1 minuet, or 1 hour

count up

–

Edge (rising or falling) or level (High or Low)

Timer 4 underflow

Timer 5 underflow

–

Receive error

Receive buffer full

Transmit buffer empty

–

Receive error

Receive buffer full

Transmit buffer empty

–

Edge (rising or falling) or level (High or Low)

–

Timer 6 compare-match B

Timer 6 compare-match A

–

Timer 7 compare-match B

Timer 7 compare-match A

–

Timer 8 compare-match B

Timer 8 compare-match A

–

Timer 9 compare-match B

Timer 9 compare-match A

Contents of table

“Vector number (Address)” indicates the trap table's vector number. The numerals in parentheses show an

offset (in bytes) from the starting address (Base) of the trap table. The starting address (Base) of the trap table

by default is the boot address, 0x20000000 set at an initial reset. This address can be changed using the TTBR

“Exception/interrupt name (peripheral circuit)” indicates that interrupt levels can be programmed for each

peripheral circuit written.

“Cause of exception/interrupt” indicates the cause of the interrupt occurring in each interrupt system.

“IDMA Ch.” indicates that a cause of interrupt which has a numeric value in this column can start up the

intelligent DMA (IDMA) to transfer data when a cause of interrupt occurs. The numeric value indicates the

IDMA's channel number. Causes of interrupt that do not have a numeric value here cannot start up the IDMA.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-3

ITC

“Priority” indicates the priority of interrupts in cases when all interrupt systems are set to the same interrupt

level. If two or more causes of interrupt occur simultaneously, interrupt requests are accepted in order of highest

priority. Interrupt priority varies depending on the interrupt levels set in each interrupt system. However, the

priorities of causes of interrupt in the same interrupt system are fixed in the order that they are written here.

Maskable interrupt generating conditions

A maskable interrupt to the CPU occurs when all of the conditions described below are met.

• The interrupt enable register for the cause of interrupt that has occurred is set to 1.

• The IE (Interrupt Enable) bit of the Processor Status Register (PSR) in the CPU is set to 1.

• The cause of interrupt that has occurred has a higher priority level than the value that is set in the PSR's

Interrupt Level (IL). (The interrupt levels can be set using the interrupt priority register in each interrupt

system.)

• No other cause of trap having higher priority, such as NMI, has occurred.

• The cause of interrupt does not invoke IDMA (the IDMA request bit is set to 0).

When a cause of interrupt occurs, the corresponding cause-of-interrupt flag is set to 1 and the flag remains

set until it is reset in the software program. Therefore, in no cases can the generated cause of interrupt be

inadvertently cleared even if the above conditions are not met when the cause of interrupt has occurred. The

interrupt will occur when the above conditions are met.

However, when the cause of interrupt invokes IDMA, the cause of interrupt is reset if the following condition is

met.

• The IDMA transfer counter is not 0.

• Interrupts are disabled in the IDMA control information even if the transfer counter is 0.

If two or more maskable causes of interrupt occur simultaneously, the cause of interrupt that has the highest

priority is allowed to signal an interrupt request to the CPU. The other interrupts with lower priorities are kept

pending until the above conditions are met.

The PSR and interrupt control register will be detailed later.

For details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in

this manual.

IV.2.1.2 Causes of Interrupt and Intelligent DMA

Several causes of interrupt can be set so that they can invoke IDMA startup. When one of these causes of interrupt

occurs, IDMA is started up before an interrupt request to the CPU. The interrupt request to the CPU is generated

after IDMA is completed. (The interrupt request can be disabled by a program.)

IDMA is always started up regardless of how the PSR is set. For details, refer to Section IV.2.5, “IDMA

Invocation.”

IV.2.1.3 Nonmaskable Interrupt (NMI)

The nonmaskable interrupt (NMI) can be generated by controlling the #NMI pin or using the internal watchdog

timer. The vector number of NMI is 7, with the vector address set to the trap table's starting address + 28 bytes.

This interrupt is prioritized over other interrupts and is unconditionally accepted by the CPU.

However, since this interrupt may operate erratically if it occurs before the stack pointer (SP) is set up, it is masked

in hardware until a write to the SP is completed after an initial reset.

For controlling the #NMI input, refer to Section II.3.3, “NMI Input.”

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-4 EPSON S1C33401 TECHNICAL MANUAL

IV.2.1.4 Interrupt Processing by the CPU

The CPU keeps sampling interrupt requests every cycle. When the CPU accepts an interrupt request, it enters trap

processing after completing execution of the instruction that was being executed.

The following lists the contents executed in trap processing.

(1) The PSR and the current program counter (PC) value are saved to the stack.

(2) The IE bit of the PSR is reset to 0 (following maskable interrupts are disabled).

(3) The IL of the PSR is set to the priority level of the accepted interrupt (NMI does not have its interrupt level

changed).

(4) The vector of the generated cause of interrupt is loaded into the PC, thus executing the interrupt processing

routine.

Thus, once an interrupt is accepted, all maskable interrupts that may follow are disabled in (2). Multiple interrupts

can also be handled by setting the IE bit to 1 in the interrupt processing routine. In this case, since the IL has been

changed in (3), only an interrupt that has a higher priority than that of the currently processed interrupt is accepted.

When the interrupt processing routine is terminated by the reti instruction, the PSR is restored to its previous status

before the interrupt has occurred. The program restarts processing after branching to the instruction next to the one

that was being executed when the interrupt occurred.

IV.2.1.5 Clearing Standby Mode by Interrupts

The standby modes (HALT, HALT2, and SLEEP) are cleared by an NMI or a maskable interrupt.

All maskable interrupts can be used to clear HALT/HALT2 mode. However, DMA interrupt cannot be used in

HALT2 mode.

In SLEEP mode, since the clock supply to the peripheral circuit is disabled, interrupts from the peripheral circuits

except RTC and I/O ports cannot be used.

Interrupts that can be used to clear basic HALT mode: NMI and all maskable interrupts

Interrupts that can be used to clear HALT2 mode: NMI and all maskable interrupts (except DMA interrupts)

Interrupts that can be used to clear SLEEP mode: NMI, I/O port interrupts, and RTC interrupt

When the CPU is released from HALT/HALT2 mode by an interrupt, it enters a program executable state by trap

processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the

address for the instruction next to halt is saved to the stack as a return address from the interrupt handling routine,

so that the reti instruction in the interrupt handling routine branches to the instruction next to halt.

The CPU is released from HALT/HALT2 mode when the ITC asserts the interrupt signal to be sent to the CPU. In

other words, when a cause-of-interrupt flag of the interrupts that have been enabled by the interrupt enable bits in

the ITC is set to 1, the CPU can be released from HALT/HALT2 mode even if the PSR is set to disable interrupts.

However, in this case the CPU does not execute the interrupt handling routine.

The #NMI signal releases the CPU from HALT/HALT2 mode when it goes low level even if the NMI detection

mode has been set to edge detection mode (refer to Section II.3, “Clock Management Unit (CMU)”).

When the CPU is reawaken from SLEEP mode by an interrupt, it enters a program executable state by trap

processing and executes an interrupt handling routine for the interrupt generated. In trap processing of the CPU, the

address for the instruction next to slp is saved to the stack as a return address from the interrupt handling routine, so

that the reti instruction in the interrupt handling routine branches to the instruction next to slp.

Cause-of-interrupt flags in the interrupt controller (ITC) cannot be set in SLEEP mode as the clock is not supplied

to the ITC in SLEEP mode.

Therefore, when the clock is not supplied to the ITC, the interrupt signals from the interrupt sources that have

been enabled to generate an interrupt are input to the CMU through the ITC and used to wake up the CPU from a

standby mode. In this case, the cause-of-interrupt flag is set after the clock has started supplying to the ITC. The

CPU can wake up from SLEEP mode by a cause of interrupt as described above even if the PSR is set to disable

interrupts, note however, that the CPU does not execute the interrupt handling routine.

The #NMI signal releases the CPU from SLEEP mode when it goes low level even if the NMI detection mode has

been set to edge detection mode.

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ITC

Notes: • In SLEEP mode, there is a time lag between input of an interrupt signal for wakeup and the

start of the clock supply to the ITC, so a delay will occur until the interrupt controller (ITC) sets

the cause-of-interrupt flag. Therefore, no interrupt will occur if the interrupt signal is deasserted

before the clock is supplied to the ITC, as the cause-of-interrupt flag in the ITC is not set.

Furthermore, additional time is needed for the CPU to accept the interrupt request from the

ITC, the CPU may execute a few instructions that follow the slp instruction before it starts the

interrupt processing.

The same problem may occur when the CPU wakes up from SLEEP mode by NMI. No

interrupt will occur if the #NMI signal is deasserted before the clock is supplied, as the NMI

flag is not set.

• If the cause of interrupt used to restart from the standby mode has been set to invoke the

IDMA, the IDMA is started up by that interrupt.

If an interrupt to be generated upon completion of IDMA is disabled at the setting of the IDMA

side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the

next interrupt request is generated.

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IV.2.2 Trap Table

The C33 ADV CPU allows the base (starting) address of the trap table to be set by the TTBR register.

After an initial reset, the TTBR register is set to 0x20000000.

Therefore, even when the trap table position is changed, it is necessary that at least the reset vector be written to the

above address.

Bits 9 to 0 in the TTBR register are fixed at 0. Therefore, the trap table starting address always begins with a 1KB

boundary address.

The TTBR register can be written only in supervisor mode to prevent them from being inadvertently rewritten.

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ITC

IV.2.3 ITC Operating Clock

The ITC is clocked by the peripheral circuit clock (PCLK) generated by the CMU.

For details on how to set PCLK and control the clock, see Section II.3, “Clock Management Unit (CMU).”

Controlling supply of the ITC operating clock

PCLK is supplied to the ITC with default settings. There are two ways of supplying PCLK to the ITC by the

CMU as detailed below. Use the respective control bits to turn off any unnecessary clock supplies to reduce the

amount of power consumed on the chip.

1. ITC clock

When this clock supply is turned off, the ITC registers except the interrupt cause flag registers and IDMA

related registers (interrupt priority registers, interrupt enable registers, and DMA trigger setup registers)

are disabled for writing. However, the cause-of-interrupt flags can be set by the corresponding interrupt

request signals from the peripheral circuit, thus interrupt requests to the CPU can also be generated if the

interrupt has been enabled. The cause-of-interrupt flag can be cleared by software. Moreover, HSDMA

can be invoked normally. IDMA cannot be invoked. However, an interrupt sets the IDMA request bit when

the IDMA enable bit has been set to 1 (IDMA request enabled). (The IDMA does not activate even if the

IDMA request bit is set.)

The clock supply can be controlled by ITCCLK (D0/0x40180).

∗ ITCCLK: ITC Clock Control Bit in the Peripheral Clock Control Register 1 (D0/0x40180)

2. Interrupt generation clock

This clock is used to generate interrupt requests to the CPU. When this clock supply is turned off, the

function to generate interrupt requests to the CPU stops and writing to the interrupt cause flag registers (to

clear the flag) is disabled.

The clock supply can be controlled by INTCLK (D4/0x40181).

∗ INTCLK: Interrupt Generation Clock Control Bit in the Peripheral Clock Control Register 2 (D4/0x40181)

Setting any of the above clock control bits (initially 1) to 0 turns off the corresponding clock supply to the ITC.

Clock state in standby mode

The supply of PCLK stops depending on the type of standby mode.

HALT mode: PCLK is supplied the same way as in normal mode.

HALT2 mode: PCLK is supplied the same way as in normal mode.

SLEEP mode: The supply of PCLK stops.

Therefore, the ITC also stops operating when in SLEEP mode.

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IV.2.4 Control of Maskable Interrupts

IV.2.4.1 Structure of the Interrupt Controller

The interrupt controller is configured as shown in Figure IV.2.4.1.1.

CPU interrupt

priority judgment

(with interrupt level)

Interrupt vector

generator

Cause-of-interrupt flag

Interrupt enable

IDMA request

IDMA enable

Interrupt request

Interrupt level

Interrupt vector

Key input x

HSDMA x

#DMAREQx input

Software trigger

16-bit timer x

8-bit timer x

Serial I/F x

A/D

Port input x

RTC

IDMA

CPU

ITC

IDMA request

priority judgment

(without interrupt level)

IDMA channel number

generator

Cause-of-interrupt flag

Interrupt enable

IDMA request

IDMA enable

IDMA request

IDMA channel number

IDMA completion

Reset A

Reset B

Reset C

Ch.x HSDMA request

HSDMA trigger

selection circuit

IDMA

HSDMA

Ch.x

Causes of

interrupt

•

Figure IV.2.4.1.1 Configuration of Interrupt Controller

The following sections explain the functions of the registers used to control interrupts.

IV.2.4.2 Processor Status Register (PSR)

The PSR is a special register incorporated in the core CPU and contains control bits to enable or disable an interrupt

request to the CPU.

Interrupt Enable (IE) bit: PSR[4]

This bit is used to enable or disable an interrupt request to the CPU. When this bit is set to 1, the CPU is

enabled to accept a maskable interrupt request. When this bit is reset to 0, no maskable interrupt request is

accepted by the CPU.

When the CPU accepts an interrupt request (or some other trap occurs), it saves the PSR to the stack and resets

the IE bit to 0. Consequently, no maskable interrupt request occurring thereafter will be accepted unless the IE

bit is set to 1 in software program or the interrupt (trap) processing routine is terminated by the reti instruction.

The IE bit is initialized to 0 (interrupts disabled) by an initial reset.

Interrupt Level (IL): PSR[11:8]

The IL bits disable the interrupts whose priorities are below the set interrupt level. For example, if the interrupt

level set in the IL is 3, the interrupts whose priorities are set below 3 in the interrupt priority register (described

later) are not accepted by the CPU even if the IE bit is set to 1. The IL and the interrupt priority register together

allow you to control the interrupt priorities in each interrupt system. For details about the interrupt levels, refer

to Section IV.2.4.4, “Interrupt Priority Register and Interrupt Levels.”

When the CPU accepts a maskable interrupt request, it saves the PSR to the stack and sets the IL to the accepted

interrupt's priority level. Therefore, even when the IE bit is set to 1 in the interrupt processing routine, no

interrupts whose priority levels are equal or below that of the interrupt currently being processed are accepted

unless the IL is rewritten.

The IL is restored to its previous status when the interrupt processing routine is terminated by the reti

instruction.

The IL is rewritten for only maskable interrupts and not for any other traps (except a reset).

The IL is set to level 0 (that is, all interrupts above level 1 are enabled) by an initial reset.

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ITC

Note: As the C33 ADV Core CPU function, the IL allows interrupt levels to be set in the range of 0 to

15. However, since the interrupt priority register in the ITC consists of three bits, interrupt levels in

each interrupt system can only be set for up to 8.

IV.2.4.3 Cause-of-Interrupt Flag and Interrupt Enable Register

A cause-of-interrupt flag and an interrupt enable register are provided for each cause of maskable interrupt.

Cause-of-interrupt flag

The cause-of-interrupt flag is set to 1 when the corresponding cause of interrupt occurs. Reading the flag

enables you to determine what caused an interrupt, making it unnecessary to resort to the CPU's trap processing.

The cause-of-interrupt flag is reset by writing data in software. Note that the method by which this flag is reset

can be selected from the software application using either of the two methods described below. This selection is

accomplished using RSTONLY (D0/0x4029F).

∗ RSTONLY: Cause-of-Interrupt Flag Reset Method Select Bit in the Flag Set/Reset Method Select Register

(D0/0x4029F)

• Reset-only method (default)

This method is selected (RSTONLY (D0/0x4029F) = 1) when initially reset.

With this method, the cause-of-interrupt flag is reset by writing 1. Although multiple cause-of-interrupt flags

are located at the same address of the interrupt control register, the cause-of-interrupt flags for which 0 has been

written can be neither set nor reset. Therefore, this method ensures that only a specific cause-of-interrupt flag is

reset.

However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that a cause-of-interrupt

flag that has been set to 1 is reset by writing.

In this method, no cause-of-interrupt flag can be set in the software application.

• Read/write method

This method is selected by writing 0 to RSTONLY (D0/0x4029F).

When this method is used, cause-of-interrupt flags can be read and written as for other registers. Therefore,

the flag is reset by writing 0 and set by writing 1. In this case, all cause-of-interrupt flags for which 0 has been

written are reset. Even in a read-modify-write operation, a cause of interrupt can occur between the read and

the write, so be careful when using this method.

Since cause-of-interrupt flags are not initialized by an initial reset, be sure to reset them before enabling

interrupts.

Notes: • Even when a maskable interrupt request is accepted by the CPU and control branches off

to the interrupt processing routine, the cause-of-interrupt flag is not reset. Consequently, if

control is returned from the interrupt processing routine by the reti instruction without resetting

the cause-of-interrupt flag in a program, the same cause of interrupt occurs again.

• When the reti instruction is executed immediately after a cause-of-interrupt flag is reset, the

CPU may execute an interrupt processing again even if no interrupt to be processed next is

occurred. This problem is caused by a time lag from execution of an instruction (ld, etc.) for

resetting the cause-of-interrupt flag until the interrupt request signal to the CPU is negated,

which is occurred due to the pipeline processing in the ITC to generate interrupt requests to

the CPU using PCLK and the bus-processing pipeline. Care should be taken especially when

PCLK is slower than CCLK.

To avoid this problem, after the cause-of-interrupt flag is reset (by writing with the ld or other

instruction), read the interrupt cause flag register before executing the reti instruction. This

makes it possible to return from the interrupt handler routine after the interrupt request to the

CPU is negated.

For details about cause of interrupt generating conditions, refer to the description of each peripheral circuit in

this manual.

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Interrupt enable register

This register controls the output of an interrupt request to the CPU. Only when the interrupt enable bit of this

of interrupt. If the bit is set to 0, no interrupt request is made to the CPU even when the corresponding cause of

interrupt occurs.

Interrupt enable bits can be read and written as for other registers. Therefore, the interrupt enable bit is reset by

writing 0 and set by writing 1. By reading this register, its setup status can be checked at any time.

Settings of the interrupt enable register do not affect the operation of cause-of-interrupt flags, so when a cause

of interrupt occurs the cause-of-interrupt flag is set to 1 even if the corresponding interrupt enable bit is set to 0.

When initially reset, the interrupt enable register is set to 0 (interrupts are disabled).

In cases when IDMA is started up by occurrence of a cause of interrupt or when clearing standby mode (HALT

or SLEEP mode) too, the corresponding interrupt enable bit must be set to 1.

The interrupt controller outputs an interrupt request to the CPU when the following conditions are met:

• A cause of interrupt has occurred and the cause-of-interrupt flag is set to 1.

• The bit of the interrupt enable register for the cause of interrupt that has occurred is set to 1 (interrupt enable).

• The bit of the IDMA request register for the cause of interrupt that has occurred is set to 0 (interrupt request).

If two or more causes of interrupt occur simultaneously, the cause of interrupt that has the highest priority is

allowed to signal an interrupt request to the CPU. (See the following section.)

When these conditions are met, the interrupt controller outputs an interrupt request signal to the CPU along with

the setup content (interrupt level) of the interrupt priority register for the generated interrupt system and its vector

number.

These signals remain asserted until the cause-of-interrupt flag is reset to 0 or the corresponding bit of the interrupt

enable register is set to 0 (interrupts are disabled) or until some other cause of interrupt of higher priority occurs.

They are not cleared if the CPU simply accepts the interrupt request.

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ITC

IV.2.4.4 Interrupt Priority Register and Interrupt Levels

The interrupt priority register is a 3-bit register provided for each interrupt system. It allows the interrupt levels

of a given interrupt system to be set in the range of 0 to 7. The default priorities shown in Table IV.2.1.1.1 can be

modified according to system requirements by this setting.

The value set in this register is used by the interrupt controller and the CPU as described below.

Roles of the interrupt priority register in the interrupt controller

If two or more causes of interrupt that have been enabled by the interrupt enable register occur simultaneously,

the cause of interrupt in the interrupt system whose interrupt priority register contains the greatest value is

allowed by the interrupt controller to signal an interrupt request to the CPU.

If a cause of interrupt occurs in two or more interrupt systems having the same value, the interrupt priority is

resolved according to the default priorities in Table IV.2.1.1.1. Causes of interrupt in the same interrupt system

also have their priorities resolved according to the order in Table IV.2.1.1.1.

Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the CPU.

When outputting an interrupt request signal to the CPU, the interrupt controller outputs the content of the

interrupt priority register to the CPU along with it.

If another cause of interrupt of higher priority occurs during outputting an interrupt request signal, the interrupt

controller changes the vector number and interrupt level to those of the new cause of interrupt before they are

output to the CPU. The first interrupt request is left pending.

Roles of the interrupt priority register in CPU processing

The CPU compares the content of the interrupt priority register received from the interrupt controller with the

interrupt level that is set in the IL of the PSR to determine whether or not to accept the interrupt request.

IE bit = 1 & IL < interrupt priority register: the interrupt request is accepted

IE bit = 1 & IL ≥ interrupt priority register: the interrupt request is rejected

Before interrupts can be controlled by an interrupt level, the interrupt disabling level must be written to the IL.

For example, if the value written to the IL is 3, only the interrupts whose interrupt levels written in the interrupt

priority register are 4 or more will be accepted.

When an interrupt is accepted, the interrupt level that is set in its interrupt priority register is written to the IL.

As a result, the interrupt requests below that interrupt level can no longer be accepted.

If the interrupt priority register for an interrupt is set to 0, the interrupt is disabled. However, invoking IDMA

by means of a cause of interrupt works fine.

Notes: • As the C33 ADV Core CPU function, the IL allows interrupt levels to be set in the range of 0

to 15. However, since the interrupt priority register in the ITC consists of three bits, interrupt

levels in each interrupt system can only be set for up to 8.

• Multiple interrupts can also be handled by rewriting the interrupt level to the IL in the interrupt

processing routine. However, if the interrupt level of the IL is set below the current level and

the IE is set to enable interrupts before resetting the cause-of-interrupt flag after an interrupt

has occurred, the same interrupt may occur again.

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IV.2.5 IDMA Invocation

The causes of interrupt for which IDMA channel numbers are written in Table IV.2.1.1.1 have the function to

invoke the intelligent DMA (IDMA).

IDMA request register

The IDMA request register is used to specify the cause of interrupt that invoke an IDMA transfer. If an IDMA

request bit is set to 1, the IDMA request will be generated when the corresponding cause of interrupt occurs.

When the IDMA request bit is set to 0, the corresponding cause of interrupt does not invoke IDMA and a

normal interrupt processing will be performed. The IDMA request register is set to 0 by an initial reset.

The method by which this register is set can be selected from the software application using either of the two

methods described below. This selection is accomplished using IDMAONLY (D1/0x4029F).

∗ IDMAONLY: IDMA Request Register Set Method Select Bit in the Flag Set/Reset Method Select Register

(D1/0x4029F)

• Set-only method (default)

This method is selected (IDMAONLY (D1/0x4029F) = 1) when initially reset.

With this method, an IDMA request bit is set by writing 1. Although multiple IDMA request bits are located

in the IDMA request register, the IDMA request bits for which 0 has been written can be neither set nor reset.

Therefore, this method ensures that only a specific IDMA request bit is set.

However, when using read-modify-write instructions (e.g., bset, bclr, or bnot), note that an IDMA request bit

that has been set to 1 is not reset by writing.

• Read/write method

This method is selected by writing 0 to IDMAONLY (D1/0x4029F).

When this method is used, IDMA request bits can be read and written as for other registers. Therefore, the

IDMA request bit is reset by writing 0 and set by writing 1. In this case, all IDMA request bits for which 0

has been written are reset. Even in a read-modify-write operation, an IDMA request bit can be reset by the

hardware between the read and the write, so be careful when using this method.

IDMA enable register

To perform IDMA transfer using a cause of interrupt, the corresponding bit of the IDMA enable register must

be set to 1. If this bit is set to 0, the cause of interrupt cannot invoke the IDMA channel. The IDMA enable

The IDMA enable register allows selection of a set method (set-only method or read/write method) similar

to the IDMA request register. This selection is accomplished using DENONLY (D2/0x4029F). See the above

explanation for the set method.

∗ DENONLY: IDMA Enable Register Set Method Select Bit in the Flag Set/Reset Method Select Register

(D2/0x4029F)

Invoking IDMA

Before IDMA can be invoked by the occurrence of a cause of interrupt, the corresponding bits of the IDMA

request and IDMA enable registers must be set to 1. Then when a cause of interrupt occurs, the interrupt

request to the CPU is made pending and the corresponding IDMA channel is invoked. The DMA transfer is

performed according to the control information of that IDMA channel. The interrupt level set by the interrupt

priority register of the ITC does not affect the IDMA invocation. The IDMA request can be accepted even

if the interrupt level of the CPU is higher than the set value of the interrupt priority register. However, when

generating the interrupt request to the CPU after the IDMA transfer is completed, the interrupt is controlled

using the interrupt level set by the interrupt priority register.

An IDMA invocation request is accepted even when the interrupt enable register and PSR of the CPU is set to

disable interrupts. It is also necessary that the control information for the IDMA channel has been set.

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ITC

Interrupt after IDMA transfer

To generate an interrupt after completion of IDMA transfer:

The interrupt request that has been kept pending can be generated after completion of the DMA transfer.

In this case, the interrupt must be enabled by the IDMA control information (DINTEN = 1) in addition to the

interrupt controller and the PSR register settings.

However, if the transfer counter set for the selected IDMA channel does not reach the terminal count of 0 after

the number of transfers set have been performed, the cause-of-interrupt flag is reset and no interrupt request is

generated. The transfer counter is decremented by 1 for each transfer performed.

If the transfer counter is decremented to 0 when DINTEN is set to 1, the cause-of-interrupt flag is not reset and

the IDMA request bit is cleared to 0. An interrupt request is generated if other interrupt conditions are met.

The IDMA request bit must be set up again in order for IDMA to be invoked when a cause of interrupt occurs

next time as well. To ensure that no unwanted IDMA request occurs, this setup must be performed after

resetting the cause-of-interrupt flag.

Figure IV.2.5.1 shows the hardware sequence when DINTEN is set to 1.

IDMA trigger (cause-of-interrupt flag)

Transfer counter

Data transfer

Reset A signal

(reset cause-of-interrupt flag)

Reset B signal

(reset IDMA request bit)

IDMA request bit

Interrupt request

Figure IV.2.5.1 Sequence when DINTEN = 1

To disable an interrupt after completion of IDMA transfer:

If an interrupt has been disabled in the IDMA control information (DINTEN = 0), the interrupt is not generated

since the cause-of-interrupt flag is reset when the transfer counter becomes 0.

In this case, the IDMA request bit remains set to 1 without being cleared. However, the IDMA enable bit is

cleared, so the following IDMA request by the same cause of interrupt will be disabled.

Figure IV.2.5.2 shows the hardware sequence when DINTEN is set to 0.

IDMA trigger (cause-of-interrupt flag)

Transfer counter

Data transfer

Reset A signal

(reset cause-of-interrupt flag)

Reset B signal

(reset IDMA request bit)

Reset C signal

(reset IDMA enable bit)

IDMA request bit

IDMA enable bit

"1"

Figure IV.2.5.2 Sequence when DINTEN = 0

For details on IDMA, refer to Section III.5, “Intelligent DMA (IDMA).”

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IV.2.6 HSDMA Invocation

Some causes of interrupt can invoke high-speed DMAs (HSDMA).

HSDMA trigger set-up register

The DMA block contains four channel of HSDMA circuit. Each channel allows selection of a cause of interrupt

as the trigger. HSDxS[3:0] (0x40298–0x40299) is used for this selection.

∗ HSD0S[3:0]: Ch.0 Trigger Set-up Bits in the HSDMA Ch.0–1 Trigger Set-up Register (D[3:0]/0x40298)

∗ HSD1S[3:0]: Ch.1 Trigger Set-up Bits in the HSDMA Ch.0–1 Trigger Set-up Register (D[7:4]/0x40298)

∗ HSD2S[3:0]: Ch.2 Trigger Set-up Bits in the HSDMA Ch.2–3 Trigger Set-up Register (D[3:0]/0x40299)

∗ HSD3S[3:0]: Ch.3 Trigger Set-up Bits in the HSDMA Ch.2–3 Trigger Set-up Register (D[7:4]/0x40299)

Table IV.2.6.1 shows the setting value and the corresponding trigger source.

Table IV.2.6.1 HSDMA Trigger Source

Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

Ch.0 trigger source

Software trigger

#DMAREQ0 input (falling edge)

#DMAREQ0 input (rising edge)

Port 0 input

Port 4 input

8-bit timer 0 underflow

16-bit timer 0 compare B

16-bit timer 0 compare A

16-bit timer 4 compare B

16-bit timer 4 compare A

Serial I/F Ch.0 Rx buffer full

Serial I/F Ch.0 Tx buffer empty

A/D conversion completion

Port 8 input

Port 12 input

Ch.1 trigger source

Software trigger

#DMAREQ1 input (falling edge)

#DMAREQ1 input (rising edge)

Port 1 input

Port 5 input

8-bit timer 1 underflow

16-bit timer 1 compare B

16-bit timer 1 compare A

16-bit timer 5 compare B

16-bit timer 5 compare A

Serial I/F Ch.1 Rx buffer full

Serial I/F Ch.1 Tx buffer empty

A/D conversion completion

Port 9 input

Port 13 input

Ch.2 trigger source

Software trigger

#DMAREQ2 input (falling edge)

#DMAREQ2 input (rising edge)

Port 2 input

Port 6 input

8-bit timer 2 underflow

16-bit timer 2 compare B

16-bit timer 2 compare A

16-bit timer 6 compare B

16-bit timer 6 compare A

Serial I/F Ch.2 Rx buffer full

Serial I/F Ch.2 Tx buffer empty

A/D conversion completion

Port 10 input

Port 14 input

Ch.3 trigger source

Software trigger

#DMAREQ3 input (falling edge)

#DMAREQ3 input (rising edge)

Port 3 input

Port 7 input

8-bit timer 3 underflow

16-bit timer 3 compare B

16-bit timer 3 compare A

16-bit timer 7 compare B

16-bit timer 7 compare A

Serial I/F Ch.3 Rx buffer full

Serial I/F Ch.3 Tx buffer empty

A/D conversion completion

Port 11 input

Port 15 input

Invoking HSDMA

By selecting a cause of interrupt with the HSDMA trigger set-up register, the HSDMA channel is invoked

when the selected cause of interrupt occurs. The interrupt control bits (cause-of-interrupt flag, interrupt enable

The interrupt request to the CPU by the cause of interrupt that invokes HSDMA is output two clocks (PCLK)

after the HSDMA request, so the DMA transfer and interrupt handling are performed concurrently when the

CPU runs with the instructions in the cache. However, when the interrupt handler contains an instruction that

accesses a peripheral circuit, the execution of the instruction is pending until the DMA transfer is completed

since the bus is used by the HSDMA.

Before HSDMA can be invoked by the occurrence of a cause of interrupt, it is necessary that DMA be enabled

on the HSDMA side by setting the control register for HSDMA transfer.

For details about HSDMA, refer to Section III.4, “High-Speed DMA (HSDMA).”

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ITC

IV.2.7 Details of Control Registers

Table IV.2.7.1 List of ITC Registers

Address

0x00040260

0x00040261

0x00040262

0x00040263

0x00040264

0x00040265

0x00040266

0x00040267

0x00040268

0x00040269

0x0004026A

0x0004026B

0x0004026C

0x0004026D

0x0004026E

0x00040270

0x00040271

0x00040272

0x00040273

0x00040274

0x00040275

0x00040276

0x00040277

0x00040278

0x00040279

0x00040280

0x00040281

0x00040282

0x00040283

0x00040284

0x00040285

0x00040286

0x00040287

0x00040288

0x00040289

0x00040290

0x00040291

0x00040292

Function

Sets interrupt level for port input 0–1 interrupts.

Sets interrupt level for port input 2–3 interrupts.

Sets interrupt level for key input interrupts.

Sets interrupt level for HSDMA Ch.0–1 interrupts.

Sets interrupt level for HSDMA Ch.2–3 interrupts.

Sets interrupt level for IDMA interrupts.

Sets interrupt level for

16-bit timer 0–1

interrupts.

Sets interrupt level for

16-bit timer 2–3

interrupts.

Sets interrupt level for

16-bit timer 4–5

interrupts.

Sets interrupt level for 8-bit timer and serial I/F Ch.0

interrupts.

Sets interrupt level for serial I/F Ch.1 and A/D

converter interrupts.

Sets interrupt level for RTC interrupts.

Sets interrupt level for port input 4–5 interrupts.

Sets interrupt level for port input 6–7 interrupts.

Sets interrupt level for serial I/F Ch.2–3 interrupts.

Enables

key input and port input 0–3

interrupts.

Enables DMA interrupts.

Enables 16-bit timer 0–1 interrupts.

Enables 16-bit timer 2–3 interrupts.

Enables 16-bit timer 4–5 interrupts.

Enables

8-bit timer 0–3

interrupts.

Enables serial I/F Ch.0–1 interrupts.

Enables port input 4–7, RTC and A/D interrupts.

Enables

8-bit timer 4–5

interrupts.

Enables serial I/F Ch.2–3 interrupts.

Indicates/resets key input and port input 0–3

interrupt

status.

Indicates/resets DMA

interrupt status.

Indicates/resets 16-bit timer 0–1

interrupt status.

Indicates/resets 16-bit timer 2–3

interrupt status.

Indicates/resets 16-bit timer 4–5

interrupt status.

Indicates/resets 8-bit timer 0–3

interrupt status.

Indicates/resets serial I/F Ch.0–1

interrupt status.

Indicates/resets port input 4–7, RTC and A/D

converter interrupt status.

Indicates/resets 8-bit timer 4–5

interrupt status.

Indicates/resets serial I/F Ch.2–3

interrupt status.

Sets

IDMA invocation by

port input 0–3, HSDMA

Ch.0–1 and 16-bit timer 0.

Sets

IDMA invocation by

16-bit timer 1–4.

Sets

IDMA invocation by

16-bit timer 5, 8-bit timer 0–3

and serial I/F Ch.0.

Port Input 0–1 Interrupt Priority Register (pINT_PR01L)

Port Input 2–3 Interrupt Priority Register (pINT_PR23L)

Key Input Interrupt Priority Register (pINT_PK01L)

HSDMA Ch.0–1 Interrupt Priority Register

(pINT_PHSD01L)

HSDMA Ch.2–3 Interrupt Priority Register

(pINT_PHSD23L)

IDMA Interrupt Priority Register (pINT_PDM)

16-bit Timer 0–1 Interrupt Priority Register (pINT_P16T01)

16-bit Timer 2–3 Interrupt Priority Register (pINT_P16T23)

16-bit Timer 4–5 Interrupt Priority Register (pINT_P16T45)

8-bit Timer, Serial I/F Ch.0

Interrupt Priority Register

(pINT_P8T_PSI00)

Serial I/F Ch.1, A/D

Interrupt Priority Register

(pINT_PSI01_PAD)

RTC

Interrupt Priority Register

(pINT_PCTM)

Port Input 4–5

Interrupt Priority Register

(pINT_PR45L)

Port Input 6–7

Interrupt Priority Register

(pINT_PR67L)

Serial I/F Ch.2–3

Interrupt Priority Register

(pINT_PSI0203)

Key Input, Port Input 0–3 Interrupt Enable Register

(pINT_EK01_EP03)

DMA Interrupt Enable Register (pINT_EDMA)

16-bit Timer 0–1 Interrupt Enable Register (pINT_E16T01)

16-bit Timer 2–3 Interrupt Enable Register (pINT_E16T23)

16-bit Timer 4–5 Interrupt Enable Register (pINT_E16T45)

8-bit Timer 0–3 Interrupt Enable Register (pINT_E8T03)

Serial I/F Ch.0–1 Interrupt Enable Register (pINT_ESIF01)

Port Input 4–7, RTC, A/D Interrupt Enable Register

(pINT_EP47_ECT_EAD)

8-bit Timer 4–5 Interrupt Enable Register (pINT_E8T45)

Serial I/F Ch.2–3 Interrupt Enable Register (pINT_ESIF23)

Key Input, Port Input 0–3 Interrupt Cause Flag Register

(pINT_FK01_FP03)

DMA Interrupt Cause Flag Register (pINT_FDMA)

16-bit Timer 0–1 Interrupt Cause Flag Register

(pINT_F16T01)

16-bit Timer 2–3 Interrupt Cause Flag Register

(pINT_F16T23)

16-bit Timer 4–5 Interrupt Cause Flag Register

(pINT_F16T45)

8-bit Timer 0–3 Interrupt Cause Flag Register

(pINT_F8T03)

Serial I/F Ch.0–1 Interrupt Cause Flag Register

(pINT_FSIF01)

Port Input 4–7, RTC, A/D Interrupt Cause Flag Register

(pINT_FP47_FCT_FAD)

8-bit Timer 4–5 Interrupt Cause Flag Register

(pINT_F8T45)

Serial I/F Ch.2–3 Interrupt Cause Flag Register

(pINT_FSIF23)

Port Input 0–3, HSDMA Ch.0–1, 16-bit Timer 0

IDMA

Request Register (pIDMAREQ_RP03_RHS_R16T0)

16-bit Timer 1–4 IDMA Request Register

(pIDMAREQ_R16T14)

16-bit Timer 5, 8-bit Timer 0–3, Serial I/F Ch.0 IDMA

Request Register (pIDMAREQ_R16T5_R8T_RSIF0)

Size

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-16 EPSON S1C33401 TECHNICAL MANUAL

Address

0x00040293

0x00040294

0x00040295

0x00040296

0x00040297

0x00040298

0x00040299

0x0004029A

0x0004029B

0x0004029C

0x0004029F

0x000402A0

0x000402A1

0x000402A2

0x000402A3

0x000402A4

0x000402A5

0x000402A6

0x000402A7

0x000402A8

0x000402A9

0x000402AA

0x000402AB

0x000402AC

0x000402AD

0x000402AE

0x000402AF

Function

Sets

IDMA invocation by

serial I/F Ch.1, A/D

converter, and port input 4–7.

Enables

IDMA requests by

port input 0–3, HSDMA

Ch.0–1, and 16-bit timer 0.

Enables

IDMA requests by

16-bit timer 1–4.

Enables

IDMA requests by

16-bit timer 5, 8-bit timer

0–3, and Serial I/F Ch.0.

Enables

IDMA requests by

serial I/F Ch.1, A/D

converter, and port input 4–7.

Selects HSDMA Ch.0–1 trigger sources.

Selects HSDMA Ch.2–3 trigger sources.

Invokes HSDMA.

Sets

IDMA invocation by

8-bit timer 4–5 and serial I/F

Ch.2–3.

Enables

IDMA requests by

8-bit timer 4–5 and serial

I/F Ch.2–3.

Selects flag set/reset method.

Sets interrupt level for port input 8–9 interrupts.

Sets interrupt level for port input 10–11 interrupts.

Sets interrupt level for port input 12–13 interrupts.

Sets interrupt level for port input 14–15 interrupts.

Sets interrupt level for 16-bit timer 6–7 interrupts.

Sets interrupt level for 16-bit timer 8–9 interrupts.

Enables port input 8–15 interrupts.

Enables

16-bit timer 6–7

interrupts.

Enables

16-bit timer 8–9

interrupts.

Indicates/resets port input 8–15

interrupt status.

Indicates/resets 16-bit timer 6–7

interrupt status.

Indicates/resets 16-bit timer 8–9

interrupt status.

Sets

IDMA invocation by

port input 8–15.

Sets

IDMA invocation by

16-bit timer 6–9.

Enables

IDMA requests by

port input 8–15.

Enables

IDMA requests by

16-bit timer 6–9.

Serial I/F Ch.1, A/D, Port Input 4–7 IDMA Request

Port Input 0–3, HSDMA Ch.0–1, 16-bit Timer 0

IDMA Enable Register (pIDMAEN_DEP03_DEHS_DE16T0)

16-bit Timer 1–4 IDMA Enable Register

(pIDMAEN_DE16T14)

16-bit Timer 5, 8-bit Timer 0–3, Serial I/F Ch.0 IDMA

Enable Register (pIDMAEN_DE16T5_DE8T_DESIF0)

Serial I/F Ch.1, A/D, Port Input 4–7 IDMA Enable

HSDMA Ch.0–1 Trigger Set-up Register

(pHSDMA_HTGR1)

HSDMA DMA Ch.2–3 Trigger Set-up Register

(pHSDMA_HTGR2)

HSDMA Software Trigger Register

(pHSDMA_HSOFTTGR)

8-bit Timer 4–5, Serial I/F Ch.2–3 IDMA Request Register

(pIDMAREQ_R8T45_RSIF23)

8-bit Timer 4–5, Serial I/F Ch.2–3 IDMA Enable Register

(pIDMAEN_DE8T45_DESIF23)

Flag Set/Reset Method Select Register (pRST_RESET)

Port Input 8–9 Interrupt Priority Register (pINT_PR89L)

Port Input 10–11 Interrupt Priority Register

(pINT_PR1011L)

Port Input 12–13 Interrupt Priority Register

(pINT_PR1213L)

Port Input 14–15 Interrupt Priority Register

(pINT_PR1415L)

16-bit Timer 6–7 Interrupt Priority Register

(pINT_P16T67)

16-bit Timer 8–9 Interrupt Priority Register

(pINT_P16T89)

Port Input 8–15 Interrupt Enable Register (pINT_EP815)

16-bit Timer 6–7 Interrupt Enable Register (pINT_E16T67)

16-bit Timer 8–9 Interrupt Enable Register (pINT_E16T89)

Port Input 8–15 Interrupt Cause Flag Register

(pINT_FP815)

16-bit Timer 6–7 Interrupt Cause Flag Register

(pINT_F16T67)

16-bit Timer 8–9 Interrupt Cause Flag Register

(pINT_F16T89)

Port Input 8–15 IDMA Request Register

(pIDMAREQ_RP815)

16-bit Timer 6–9 IDMA Request Register

(pIDMAREQ_R16T69)

Port Input 8–15 IDMA Enable Register

(pIDMAEN_DEP815)

16-bit Timer 6–9 IDMA Enable Register

(pIDMAEN_DE16T69)

Size

The following describes each ITC control register.

The ITC control registers are mapped in the 8-bit device area from 0x40260 to 0x402AF, and can be accessed in

units of bytes.

Note: When setting the ITC control registers, be sure to write a 0, and not a 1, for all “reserved bits.”

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-17

ITC

0x40260: Port Input 0–1 Interrupt Priority Register (pINT_PR01L)

Name

Address

–

0 to 7

–

PP1L2

PP1L1

PP1L0

–

PP0L2

PP0L1

PP0L0

reserved

Port input 1 interrupt level

reserved

Port input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040260

(B)

Port input 0–1

interrupt

priority register

(pINT_PR01L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PP1L[2:0]: Port Input 1 Interrupt Level Bits

Sets the priority level of the port input 1 interrupt.

D3 Reserved

D[2:0] PP0L[2:0]: Port Input 0 Interrupt Level Bits

Sets the priority level of the port input 0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-18 EPSON S1C33401 TECHNICAL MANUAL

0x40261: Port Input 2–3 Interrupt Priority Register (pINT_PR23L)

Name

Address

–

0 to 7

–

PP3L2

PP3L1

PP3L0

–

PP2L2

PP2L1

PP2L0

reserved

Port input 3 interrupt level

reserved

Port input 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040261

(B)

Port input 2–3

interrupt

priority register

(pINT_PR23L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PP3L[2:0]: Port Input 3 Interrupt Level Bits

Sets the priority level of the port input 3 interrupt.

D3 Reserved

D[2:0] PP2L[2:0]: Port Input 2 Interrupt Level Bits

Sets the priority level of the port input 2 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-19

ITC

0x40262: Key Input Interrupt Priority Register (pINT_PK01L)

Name

Address

–

0 to 7

–

PK1L2

PK1L1

PK1L0

–

PK0L2

PK0L1

PK0L0

reserved

Key input 1 interrupt level

reserved

Key input 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040262

(B)

Key input

interrupt

priority register

(pINT_PK01L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PK1L[2:0]: Key Input 1 Interrupt Level Bits

Sets the priority level of the key input 1 interrupt.

D3 Reserved

D[2:0] PK0L[2:0]: Key Input 0 Interrupt Level Bits

Sets the priority level of the key input 0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-20 EPSON S1C33401 TECHNICAL MANUAL

0x40263: HSDMA Ch.0–1 Interrupt Priority Register (pINT_PHSD01L)

Name

Address

–

0 to 7

–

PHSD1L2

PHSD1L1

PHSD1L0

–

PHSD0L2

PHSD0L1

PHSD0L0

reserved

HSDMA Ch.1

interrupt level

reserved

HSDMA Ch.0

interrupt level

–

R/W

–

R/W

0 when being read.

0040263

(B)

HSDMA Ch.0–1

interrupt

priority register

(pINT_PHSD01L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PHSD1L[2:0]: HSDMA Ch.1 Interrupt Level Bits

Sets the priority level of the HSDMA Ch.1 interrupt.

D3 Reserved

D[2:0] PHSD0L[2:0]: HSDMA Ch.0 Interrupt Level Bits

Sets the priority level of the HSDMA Ch.0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-21

ITC

0x40264: HSDMA Ch.2–3 Interrupt Priority Register (pINT_PHSD23L)

Name

Address

–

0 to 7

–

PHSD3L2

PHSD3L1

PHSD3L0

–

PHSD2L2

PHSD2L1

PHSD2L0

reserved

HSDMA Ch.3

interrupt level

reserved

HSDMA Ch.2

interrupt level

–

R/W

–

R/W

0 when being read.

0040264

(B)

HSDMA Ch.2–3

interrupt

priority register

(pINT_PHSD23L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PHSD3L[2:0]: HSDMA Ch.3 Interrupt Level Bits

Sets the priority level of the HSDMA Ch.3 interrupt.

D3 Reserved

D[2:0] PHSD2L[2:0]: HSDMA Ch.2 Interrupt Level Bits

Sets the priority level of the HSDMA Ch.2 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-22 EPSON S1C33401 TECHNICAL MANUAL

0x40265: IDMA Interrupt Priority Register (pINT_PDM)

Name

Address

–

0 to 7

–

PDM2

PDM1

PDM0

D7–3

reserved

IDMA interrupt level

–

R/W

0 when being read.

0040265

(B)

IDMA interrupt

priority register

(pINT_PDM)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D[7:3] Reserved

D[2:0] PDM[2:0]: IDMA Interrupt Level Bits

Sets the priority level of the IDMA interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-23

ITC

0x40266: 16-bit Timer 0–1 Interrupt Priority Register (pINT_P16T01)

Name

Address

–

0 to 7

–

P16T12

P16T11

P16T10

–

P16T02

P16T01

P16T00

reserved

16-bit timer 1 interrupt level

reserved

16-bit timer 0 interrupt level

–

R/W

–

R/W

0 when being read.

0040266

(B)

16-bit timer 0–1

interrupt

priority register

(pINT_P16T01)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] P16T1[2:0]: 16-bit Timer 1 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 1 interrupt.

D3 Reserved

D[2:0] P16T0[2:0]: 16-bit Timer 0 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-24 EPSON S1C33401 TECHNICAL MANUAL

0x40267: 16-bit Timer 2–3 Interrupt Priority Register (pINT_P16T23)

Name

Address

–

0 to 7

–

P16T32

P16T31

P16T30

–

P16T22

P16T21

P16T20

reserved

16-bit timer 3 interrupt level

reserved

16-bit timer 2 interrupt level

–

R/W

–

R/W

0 when being read.

0040267

(B)

16-bit timer 2–3

interrupt

priority register

(pINT_P16T23)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] P16T3[2:0]: 16-bit Timer 3 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 3 interrupt.

D3 Reserved

D[2:0] P16T2[2:0]: 16-bit Timer 2 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 2 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-25

ITC

0x40268: 16-bit Timer 4–5 Interrupt Priority Register (pINT_P16T45)

Name

Address

–

0 to 7

–

P16T52

P16T51

P16T50

–

P16T42

P16T41

P16T40

reserved

16-bit timer 5 interrupt level

reserved

16-bit timer 4 interrupt level

–

R/W

–

R/W

0 when being read.

0040268

(B)

16-bit timer 4–5

interrupt

priority register

(pINT_P16T45)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] P16T5[2:0]: 16-bit Timer 5 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 5 interrupt.

D3 Reserved

D[2:0] P16T4[2:0]: 16-bit Timer 4 Interrupt Level Bits

Sets the priority levels of the 16-bit timer 4 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-26 EPSON S1C33401 TECHNICAL MANUAL

0x40269: 8-bit Timer, Serial I/F Ch.0 Interrupt Priority Register

(pINT_P8T_PSI00)

Name

Address

–

0 to 7

–

PSIO02

PSIO01

PSIO00

–

P8TM2

P8TM1

P8TM0

reserved

Serial interface Ch.0

interrupt level

reserved

8-bit timer 0–5 interrupt level

–

R/W

–

R/W

0 when being read.

0040269

(B)

8-bit timer,

serial I/F Ch.0

interrupt

priority register

(pINT_P8T_PSI00)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PSIO0[2:0]: Serial Interface Ch.0 Interrupt Level Bits

Sets the priority levels of the serial interface Ch.0 interrupt.

D3 Reserved

D[2:0] P8TM[2:0]: 8-bit Timer 0–5 Interrupt Level Bits

Sets the priority levels of the 8-bit timer 0–5 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-27

ITC

0x4026A: Serial I/F Ch.1, A/D Interrupt Priority Register (pINT_PSI01_PAD)

Name

Address

–

0 to 7

–

PAD2

PAD1

PAD0

–

PSIO12

PSIO11

PSIO10

reserved

A/D converter interrupt level

reserved

Serial interface Ch.1

interrupt level

–

R/W

–

R/W

0 when being read.

004026A

(B)

Serial I/F Ch.1,

A/D interrupt

priority register

(pINT_PSI01_PAD)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PAD[2:0]: A/D Converter Interrupt Level Bits

Sets the priority levels of the A/D converter interrupt.

D3 Reserved

D[2:0] PSIO1[2:0]: Serial Interface Ch.1 Interrupt Level Bits

Sets the priority levels of the serial interface Ch.1 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-28 EPSON S1C33401 TECHNICAL MANUAL

0x4026B: RTC Interrupt Priority Register (pINT_PCTM)

Name

Address

–

0 to 7

–

PCTM2

PCTM1

PCTM0

D7–3

reserved

RTC interrupt level

–

R/W

Writing 1 not allowed.

004026B

(B)

RTC interrupt

priority register

(pINT_PCTM)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D[7:3] Reserved

D[2:0] PCTM[2:0]: RTC Interrupt Level Bits

Sets the priority level of the RTC interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-29

ITC

0x4026C: Port Input 4–5 Interrupt Priority Register (pINT_PR45L)

Name

Address

–

0 to 7

–

PP5L2

PP5L1

PP5L0

–

PP4L2

PP4L1

PP4L0

reserved

Port input 5 interrupt level

reserved

Port input 4 interrupt level

–

R/W

–

R/W

0 when being read.

004026C

(B)

Port input 4–5

interrupt

priority register

(pINT_PR45L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PP5L[2:0]: Port Input 5 Interrupt Level Bits

Sets the priority level of the port input 5 interrupt.

D3 Reserved

D[2:0] PP4L[2:0]: Port Input 4 Interrupt Level Bits

Sets the priority level of the port input 4 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-30 EPSON S1C33401 TECHNICAL MANUAL

0x4026D: Port Input 6–7 Interrupt Priority Register (pINT_PR67L)

Name

Address

–

0 to 7

–

PP7L2

PP7L1

PP7L0

–

PP6L2

PP6L1

PP6L0

reserved

Port input 7 interrupt level

reserved

Port input 6 interrupt level

–

R/W

–

R/W

0 when being read.

004026D

(B)

Port input 6–7

interrupt

priority register

(pINT_PR67L)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PP7L[2:0]: Port Input 7 Interrupt Level Bits

Sets the priority level of the port input 7 interrupt.

D3 Reserved

D[2:0] PP6L[2:0]: Port Input 6 Interrupt Level Bits

Sets the priority level of the port input 6 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-31

ITC

0x4026E: Serial I/F Ch.2–3 Interrupt Priority Register (pINT_PSI0203)

Name

Address

–

0 to 7

–

PSIO32

PSIO31

PSIO30

–

PSIO22

PSIO21

PSIO20

reserved

Serial interface Ch.3

interrupt level

reserved

Serial interface Ch.2

interrupt level

–

R/W

–

R/W

0 when being read.

004026E

(B)

Serial I/F

Ch.2–3

interrupt

priority register

(pINT_PSI0203)

This register is used to set an interrupt priority level. (Default: indeterminate)

The priority level can be set in the range of 0 to 7.

If the level is set below the IL value of the PSR, no interrupt is generated.

D7 Reserved

D[6:4] PSIO3[2:0]: Serial Interface Ch.3 Interrupt Level Bits

Sets the priority levels of the serial interface Ch.3 interrupt.

D3 Reserved

D[2:0] PSIO2[2:0]: Serial Interface Ch.2 Interrupt Level Bits

Sets the priority levels of the serial interface Ch.2 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-32 EPSON S1C33401 TECHNICAL MANUAL

0x40270: Key Input, Port Input 0–3 Interrupt Enable Register

(pINT_EK01_EP03)

Name

Address

–

EK1

EK0

EP3

EP2

EP1

EP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

––

–

R/W

0 when being read.

0040270

(B) 1Enabled 0Disabled

Key input,

port input 0–3

interrupt

enable register

(pINT_EK01_EP03)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:6] Reserved

D5 EK1: Key Input 1 Interrupt Enable Bit

Enables or disables the key input 1 interrupt.

D4 EK0: Key Input 0 Interrupt Enable Bit

Enables or disables the key input 0 interrupt.

D3 EP3: Port Input 3 Interrupt Enable Bit

Enables or disables the port input 3 interrupt.

D2 EP2: Port Input 2 Interrupt Enable Bit

Enables or disables the port input 2 interrupt.

D1 EP1: Port Input 1 Interrupt Enable Bit

Enables or disables the port input 1 interrupt.

D0 EP0: Port Input 0 Interrupt Enable Bit

Enables or disables the port input 0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-33

ITC

0x40271: DMA Interrupt Enable Register (pINT_EDMA)

Name

Address

–

EIDMA

EHDM3

EHDM2

EHDM1

EHDM0

D7–5

reserved

IDMA

HSDMA Ch.3

HSDMA Ch.2

HSDMA Ch.1

HSDMA Ch.0

––

–

R/W

0 when being read.

0040271

(B) 1Enabled 0Disabled

DMA interrupt

enable register

(pINT_EDMA)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:5] Reserved

D4 EIDMA: IDMA Enable Interrupt Bit

Enables or disables the IDMA interrupt.

D3 EHDMA3: HSDMA Ch.3 Interrupt Enable Bit

Enables or disables the HSDMA Ch.3 interrupt.

D2 EHDMA2: HSDMA Ch.2 Interrupt Enable Bit

Enables or disables the HSDMA Ch.2 interrupt.

D1 EHDMA1: HSDMA Ch.1 Interrupt Enable Bit

Enables or disables the HSDMA Ch.1 interrupt.

D0 EHDMA0: HSDMA Ch.0 Interrupt Enable Bit

Enables or disables the HSDMA Ch.0 interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-34 EPSON S1C33401 TECHNICAL MANUAL

0x40272: 16-bit Timer 0–1 Interrupt Enable Register (pINT_E16T01)

Name

Address

E16TC1

E16TU1

–

E16TC0

E16TU0

–

D5–4

D1–0

16-bit timer 1 comparison A

16-bit timer 1 comparison B

reserved

16-bit timer 0 comparison A

16-bit timer 0 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040272

(B)

1Enabled 0Disabled

16-bit timer 0–1

interrupt

enable register

(pINT_E16T01)

–

1Enabled 0Disabled

–

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D7 E16TC1: 16-bit Timer 1 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 1 comparison A interrupt.

D6 E16TU1: 16-bit Timer 1 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 1 comparison B interrupt.

D[5:4] Reserved

D3 E16TC0: 16-bit Timer 0 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 0 comparison A interrupt.

D2 E16TU0: 16-bit Timer 0 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 0 comparison B interrupt.

D[1:0] Reserved

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-35

ITC

0x40273: 16-bit Timer 2–3 Interrupt Enable Register (pINT_E16T23)

Name

Address

E16TC3

E16TU3

–

E16TC2

E16TU2

–

D5–4

D1–0

16-bit timer 3 comparison A

16-bit timer 3 comparison B

reserved

16-bit timer 2 comparison A

16-bit timer 2 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040273

(B)

1Enabled 0Disabled

16-bit timer 2–3

interrupt

enable register

(pINT_E16T23)

–

1Enabled 0Disabled

–

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D7 E16TC3: 16-bit Timer 3 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 3 comparison A interrupt.

D6 E16TU3: 16-bit Timer 3 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 3 comparison B interrupt.

D[5:4] Reserved

D3 E16TC2: 16-bit Timer 2 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 2 comparison A interrupt.

D2 E16TU2: 16-bit Timer 2 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 2 comparison B interrupt.

D[1:0] Reserved

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-36 EPSON S1C33401 TECHNICAL MANUAL

0x40274: 16-bit Timer 4–5 Interrupt Enable Register (pINT_E16T45)

Name

Address

E16TC5

E16TU5

–

E16TC4

E16TU4

–

D5–4

D1–0

16-bit timer 5 comparison A

16-bit timer 5 comparison B

reserved

16-bit timer 4 comparison A

16-bit timer 4 comparison B

reserved

–

R/W

–

R/W

–

0 when being read.

0040274

(B)

1Enabled 0Disabled

16-bit timer 4–5

interrupt

enable register

(pINT_E16T45)

–

1Enabled 0Disabled

–

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D7 E16TC5: 16-bit Timer 5 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 5 comparison A interrupt.

D6 E16TU5: 16-bit Timer 5 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 5 comparison B interrupt.

D[5:4] Reserved

D3 E16TC4: 16-bit Timer 4 Comparison A Interrupt Enable Bit

Enables or disables the 16-bit timer 4 comparison A interrupt.

D2 E16TU4: 16-bit Timer 4 Comparison B Interrupt Enable Bit

Enables or disables the 16-bit timer 4 comparison B interrupt.

D[1:0] Reserved

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-37

ITC

0x40275: 8-bit Timer 0–3 Interrupt Enable Register (pINT_E8T03)

Name

Address

–

E8TU3

E8TU2

E8TU1

E8TU0

D7–4

reserved

8-bit timer 3 underflow

8-bit timer 2 underflow

8-bit timer 1 underflow

8-bit timer 0 underflow

––

–

R/W

0 when being read.

0040275

(B) 1Enabled 0Disabled

8-bit timer 0–3

interrupt

enable register

(pINT_E8T03)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:4] Reserved

D3 E8TU3: 8-bit Timer 3 Underflow Interrupt Enable Bit

Enables or disables the 8-bit timer 3 underflow interrupt.

D2 E8TU2: 8-bit Timer 2 Underflow Interrupt Enable Bit

Enables or disables the 8-bit timer 2 underflow interrupt.

D1 E8TU1: 8-bit Timer 1 Underflow Interrupt Enable Bit

Enables or disables the 8-bit timer 1 underflow interrupt.

D0 E8TU0: 8-bit Timer 0 Underflow Interrupt Enable Bit

Enables or disables the 8-bit timer 0 underflow interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-38 EPSON S1C33401 TECHNICAL MANUAL

0x40276: Serial I/F Ch.0–1 Interrupt Enable Register (pINT_ESIF01)

Name

Address

–

ESTX1

ESRX1

ESERR1

ESTX0

ESRX0

ESERR0

D7–6

reserved

SIF Ch.1 transmit buffer empty

SIF Ch.1 receive buffer full

SIF Ch.1 receive error

SIF Ch.0 transmit buffer empty

SIF Ch.0 receive buffer full

SIF Ch.0 receive error

––

–

R/W

0 when being read.

0040276

(B) 1Enabled 0Disabled

Serial I/F

Ch.0–1

interrupt

enable register

(pINT_ESIF01)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:6] Reserved

D5 ESTX1: SIF Ch.1 Transmit Buffer Empty Interrupt Enable Bit

Enables or disables the SIF Ch.1 transmit buffer empty interrupt.

D4 ESRX1: SIF Ch.1 Receive Buffer Full Interrupt Enable Bit

Enables or disables the SIF Ch.1 receive buffer full interrupt.

D3 ESERR1: SIF Ch.1 Receive Error Interrupt Enable Bit

Enables or disables the SIF Ch.1 receive error interrupt.

D2 ESTX0: SIF Ch.0 Transmit Buffer Empty Interrupt Enable Bit

Enables or disables the SIF Ch.0 transmit buffer empty interrupt.

D1 ESRX0: SIF Ch.0 Receive Buffer Full Interrupt Enable Bit

Enables or disables the SIF Ch.0 receive buffer full interrupt.

D0 ESERR0: SIF Ch.0 Receive Error Interrupt Enable Bit

Enables or disables the SIF Ch.0 receive error interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-39

ITC

0x40277: Port Input 4–7, RTC, A/D Interrupt Enable Register

(pINT_EP47_ECT_EAD)

Name

Address

–

EP7

EP6

EP5

EP4

ECTM

EADE

EADC

reserved

Port input 7

Port input 6

Port input 5

Port input 4

RTC

A/D conversion completion

A/D upper/lower limit

––

–

R/W

0 when being read.

0040277

(B) 1Enabled 0Disabled

Port input 4–7,

RTC, A/D

interrupt

enable register

(pINT_EP47_ECT

_EAD)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D7 Reserved

D6 EP7: Port Input 7 Interrupt Enable Bit

Enables or disables the port input 7 interrupt.

D5 EP6: Port Input 6 Interrupt Enable Bit

Enables or disables the port input 6 interrupt.

D4 EP5: Port Input 5 Interrupt Enable Bit

Enables or disables the port input 5 interrupt.

D3 EP4: Port Input 4 Interrupt Enable Bit

Enables or disables the port input 4 interrupt.

D2 ECTM: RTC Interrupt Enable Bit

Enables or disables the RTC interrupt.

D1 EADE: A/D Conversion Completion Interrupt Enable Bit

Enables or disables the A/D conversion completion interrupt.

D0 EADC: A/D Upper/Lower Limit Interrupt Enable Bit

Enables or disables the A/D upper/lower limit interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-40 EPSON S1C33401 TECHNICAL MANUAL

0x40278: 8-bit Timer 4–5 Interrupt Enable Register (pINT_E8T45)

Name

Address

–

E8TU5

E8TU4

D7–2

reserved

8-bit timer 5 underflow

8-bit timer 4 underflow

–

R/W

0 when being read.

0040278

(B)

8-bit timer 4–5

interrupt

enable register

(pINT_E8T45)

–

Enabled Disabled

1 0

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:2] Reserved

D1 E8TU5: 8-bit Timer 5 Underflow Interrupt Enable Bit

Enables or disables interrupt generation of the 8-bit timer 5 underflow interrupt.

D0 E8TU4: 8-bit Timer 4 Underflow Interrupt Enable Bit

Enables or disables interrupt generation of the 8-bit timer 4 underflow interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-41

ITC

0x40279: Serial I/F Ch.2–3 Interrupt Enable Register (pINT_ESIF23)

Name

Address

–

ESTX3

ESRX3

ESERR3

ESTX2

ESRX2

ESERR2

D7–6

reserved

SIF Ch.3 transmit buffer empty

SIF Ch.3 receive buffer full

SIF Ch.3 receive error

SIF Ch.2 transmit buffer empty

SIF Ch.2 receive buffer full

SIF Ch.2 receive error

––

–

R/W

0 when being read.

0040279

(B) 1Enabled 0Disabled

Serial I/F

Ch.2–3

interrupt

enable register

(pINT_ESIF23)

Each bit in this register enables or disables an interrupt to the CPU.

1 (R/W): Interrupt enabled

0 (R/W): Interrupt disabled (default)

Interrupts are enabled when the corresponding bits of this register are set to 1 and are disabled when the bits are set

to 0.

For the causes of interrupt used to request IDMA invocation or clear the standby mode, the corresponding interrupt

enable register bit must be set for interrupt enable.

D[7:6] Reserved

D5 ESTX3: SIF Ch.3 Transmit Buffer Empty Interrupt Enable Bit

Enables or disables the SIF Ch.3 transmit buffer empty interrupt.

D4 ESRX3: SIF Ch.3 Receive Buffer Full Interrupt Enable Bit

Enables or disables the SIF Ch.3 receive buffer full interrupt.

D3 ESERR3: SIF Ch.3 Receive Error Interrupt Enable Bit

Enables or disables the SIF Ch.3 receive error interrupt.

D2 ESTX2: SIF Ch.2 Transmit Buffer Empty Interrupt Enable Bit

Enables or disables the SIF Ch.2 transmit buffer empty interrupt.

D1 ESRX2: SIF Ch.2 Receive Buffer Full Interrupt Enable Bit

Enables or disables the SIF Ch.2 receive buffer full interrupt.

D0 ESERR2: SIF Ch.2 Receive Error Interrupt Enable Bit

Enables or disables the SIF Ch.2 receive error interrupt.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

IV-2-42 EPSON S1C33401 TECHNICAL MANUAL

0x40280: Key Input, Port Input 0–3 Interrupt Cause Flag Register

(pINT_FK01_FP03)

Name

Address

–

FK1

FK0

FP3

FP2

FP1

FP0

D7–6

reserved

Key input 1

Key input 0

Port input 3

Port input 2

Port input 1

Port input 0

––

–

R/W

0 when being read.

0040280

(B) 1Occurred 0

Not occurred

Key input,

port input 0–3

interrupt cause

flag register

(pINT_FK01_FP03)

Each bit in this register is a cause-of-interrupt flag to indicate the interrupt cause occurrence status. The flag that

has been set can be reset by writing. (Default: indeterminate)

1 (R): Cause of interrupt has occurred

0 (R): No cause of interrupt has occurred

When written using the reset-only method (default)

1 (W): Flag is reset

0 (W): Has no effect

When written using the read/write method

1 (W): Flag is set

0 (W): Flag is reset

The cause-of-interrupt flag is set to 1 when a cause of interrupt occurs in each peripheral circuit.

If the following conditions are met at this time, an interrupt is generated to the CPU:

1. The corresponding bit of the interrupt enable register is set to 1.

2. No other interrupt request of higher priority has occurred.

3. The IE bit of the PSR is set to 1 (interrupt enabled).

4. The corresponding interrupt priority register is set to a level higher than the CPU's interrupt level (IL).

When using a cause of interrupt to request IDMA, note that even when the above conditions are met, no interrupt

request to the CPU is generated for the cause of interrupt that has occurred. If interrupts are enabled at the setting

of IDMA, an interrupt is generated under the above conditions after the data transfer by IDMA is completed.

The cause-of-interrupt flag is always set to 1 when a cause of interrupt occurs no matter how the interrupt enable

and interrupt priority registers are set.

In order for the next interrupt to be accepted after interrupt generation, the cause-of-interrupt flag must be reset

and the PSR must be set up again (by setting the IL below the level indicated by the interrupt priority register and

setting the IE bit to 1 or executing the reti instruction).

The cause-of-interrupt flag can only be reset by a write instruction in the software application. If the PSR is again

set up to accept interrupts (or the reti instruction is executed) without resetting the cause-of-interrupt flag, the same

interrupt may occur again. Note also that the value to be written to reset the flag is 1 when using the reset-only

method (RSTONLY (D0/0x4029F) = 1) and 0 when using the read/write method (RSTONLY (D0/0x4029F) = 0).

Be careful not to confuse these two conditions.

The cause-of-interrupt flag becomes indeterminate when initially reset, so be sure to reset the flag in the software

application.

IV C33 ADV BASIC PERIPHERAL BLOCK: INTERRUPT CONTROLLER (ITC)

S1C33401 TECHNICAL MANUAL EPSON IV-2-43