LMH6642, LMH6643, LMH6644
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SNOS966P –MAY 2001–REVISED MARCH 2013
LMH6642/LMH6643/LMH6644 Low Power, 130MHz, 75mA Rail-to-Rail Output Amplifiers
Check for Samples: LMH6642,LMH6643,LMH6644
1FEATURES DESCRIPTION
The LMH664X family true single supply voltage
2(VS= ±5V, TA= 25°C, RL= 2kΩ, AV= +1. Typical feedback amplifiers offer high speed (130MHz), low
Values Unless Specified). distortion (−62dBc), and exceptionally high output
•−3dB BW (AV= +1) 130MHz current (approximately 75mA) at low cost and with
• Supply Voltage Range 2.7V to 12.8V reduced power consumption when compared against
existing devices with similar performance.
• Slew Rate (1), (AV=−1) 130V/µs Input common mode voltage range extends to 0.5V
• Supply Current (no load) 2.7mA/amp below V−and 1V from V+. Output voltage range
• Output Short Circuit Current +115mA/−145mA extends to within 40mV of either supply rail, allowing
• Linear Output Current ±75mA wide dynamic range especially desirable in low
• Input Common Mode Volt. 0.5V Beyond V−, 1V voltage applications. The output stage is capable of
approximately 75mA in order to drive heavy loads.
from V+Fast output Slew Rate (130V/µs) ensures large peak-
• Output Voltage Swing 40mV from Rails to-peak output swings can be maintained even at
• Input Voltage Noise (100kHz) 17nV/√Hz higher speeds, resulting in exceptional full power
• Input Current Noise (100kHz) 0.9pA/√Hz bandwidth of 40MHz with a 3V supply. These
characteristics, along with low cost, are ideal features
• THD (5MHz, RL= 2kΩ, VO= 2VPP, AV= +2) for a multitude of industrial and commercial
−62dBc applications.
• Settling Time 68ns Careful attention has been paid to ensure device
• Fully Characterized for 3V, 5V, and ±5V stability under all operating voltages and modes. The
• Overdrive Recovery 100ns result is a very well behaved frequency response
characteristic (0.1dB gain flatness up the 12MHz
• Output Short Circuit Protected (2) under 150Ωload and AV= +2) with minimal peaking
• No Output Phase Reversal with CMVR (typically 2dB maximum) for any gain setting and
Exceeded under both heavy and light loads. This along with fast
settling time (68ns) and low distortion allows the
APPLICATIONS device to operate well in ADC buffer, and high
frequency filter applications as well as other
• Active Filters applications.
• CD/DVD ROM This device family offers professional quality video
• ADC Buffer Amp performance with low DG (0.01%) and DP (0.01°)
• Portable Video characteristics. Differential Gain and Differential
• Current Sense Buffer Phase characteristics are also well maintained under
heavy loads (150Ω) and throughout the output
(1) Slew rate is the average of the rising and falling slew rates. voltage range. The LMH664X family is offered in
(2) Output short circuit duration is infinite for VS< 6V at room single (LMH6642), dual (LMH6643), and quad
temperature and below. For VS> 6V, allowable short circuit
duration is 1.5ms. (LMH6644) options.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
AV = +1
AV = +5
AV = +10
AV = +2
10k 100k 1M 10M 100M 500M
-3
-2
-1
0
+1
+2
+3
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±1.5V
RL = 2k
VOUT = 0.2VPP
100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
AV = +2
RF = RL = 2k
±5V
4VPP
±2.5V
2VPP
6.0
8.0
0.0
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Closed Loop Gain vs. Frequency for Various Gain Large Signal Frequency Response
Figure 1. Figure 2.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
ESD Tolerance 2KV (3)
200V (4)
1000V (5)
VIN Differential ±2.5V
Output Short Circuit Duration See (6),(7)
Supply Voltage (V+- V−) 13.5V
Voltage at Input/Output pins V++0.8V, V−−0.8V
Input Current ±10mA
Storage Temperature Range −65°C to +150°C
Junction Temperature (8) +150°C
Soldering Information Infrared or Convection Reflow (20 sec) 235°C
Wave Soldering Lead Temp.(10 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human body model, 1.5kΩin series with 100pF.
(4) Machine Model, 0Ωin series with 200pF.
(5) CDM: Charge Device Model
(6) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(7) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(8) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
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Operating Ratings (1)
Supply Voltage (V+– V−) 2.7V to 12.8V
Junction Temperature Range (2) −40°C to +85°C
Package Thermal Resistance (2) (θJA) 5-Pin SOT-23 265°C/W
8-Pin SOIC 190°C/W
8-Pin VSSOP 235°C/W
14-Pin SOIC 145°C/W
14- Pin TSSOP 155°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
3V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 3V, V−= 0V, VCM = VO= V+/2, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
BW −3dB BW AV= +1, VOUT = 200mVPP 80 115 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain Flatness AV= +2, RL= 150Ωto V+/2, 19 MHz
RL= 402Ω, VOUT = 200mVPP
PBW Full Power Bandwidth AV= +1, −1dB, VOUT = 1VPP 40 MHz
enInput-Referred Voltage Noise f = 100kHz 17 nV/√Hz
f = 1kHz 48
inInput-Referred Current Noise f = 100kHz 0.90 pA/√Hz
f = 1kHz 3.3
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV=−1, −48 dBc
RL= 100Ωto V+/2
DG Differential Gain VCM = 1V, NTSC, AV= +2 0.17
RL=150Ωto V+/2 %
RL=1kΩto V+/2 0.03
DP Differential Phase VCM = 1V, NTSC, AV= +2 0.05
RL=150Ωto V+/2 deg
RL=1kΩto V+/2 0.03
CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: 47 dB
Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load, 68 ns
VS= 5V
SR Slew Rate (3) AV=−1, VI= 2VPP 90 120 V/µs
VOS Input Offset Voltage For LMH6642 and LMH6644 ±1 ±5
±7 mV
For LMH6643 ±1 ±3.4
±7
TC VOS Input Offset Average Drift See (4) ±5 µV/°C
IBInput Bias Current See (5) −1.50 −2.60 µA
−3.25
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance 3 MΩ
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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3V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 3V, V−= 0V, VCM = VO= V+/2, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
CIN Common Mode Input 2 pF
Capacitance
CMVR Input Common-Mode Voltage CMRR ≥50dB −0.5 −0.2
Range −0.1 V
1.8 2.0
1.6
CMRR Common Mode Rejection Ratio VCM Stepped from 0V to 1.5V 72 95 dB
AVOL Large Signal Voltage Gain VO= 0.5V to 2.5V 80 96
RL= 2kΩto V+/2 75 dB
VO= 0.5V to 2.5V 74 82
RL= 150Ωto V+/2 70
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 2.90 2.98 V
High RL= 150Ωto V+/2, VID = 200mV 2.80 2.93
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 75 mV
Low RL= 150Ωto V+/2, VID =−200mV 75 150
ISC Output Short Circuit Current Sourcing to V+/2 50 95
VID = 200mV (6) 35 mA
Sinking to V+/2 55 110
VID =−200mV (6) 40
IOUT Output Current VOUT = 0.5V from either supply ±65 mA
+PSRR Positive Power Supply Rejection V+= 3.0V to 3.5V, VCM = 1.5V 75 85 dB
Ratio
ISSupply Current (per channel) No Load 2.70 4.00 mA
4.50
(6) Short circuit test is a momentary test. See Note 7 under 5V Electrical Characteristics.
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
BW −3dB BW AV= +1, VOUT = 200mVPP 90 120 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain Flatness AV= +2, RL= 150Ωto V+/2, 15 MHz
Rf= 402Ω, VOUT = 200mVPP
PBW Full Power Bandwidth AV= +1, −1dB, VOUT = 2VPP 22 MHz
enInput-Referred Voltage Noise f = 100kHz 17 nV/√Hz
f = 1kHz 48
inInput-Referred Current Noise f = 100kHz 0.90 pA/√Hz
f = 1kHz 3.3
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV= +2 −60 dBc
DG Differential Gain NTSC, AV= +2 0.16
RL=150Ωto V+/2 %
RL= 1kΩto V+/2 0.05
DP Differential Phase NTSC, AV= +2 0.05
RL= 150Ωto V+/2 deg
RL= 1kΩto V+/2 0.01
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto V+/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: 47 dB
Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load 68 ns
SR Slew Rate (3) AV=−1, VI= 2VPP 95 125 V/µs
VOS Input Offset Voltage For LMH6642 and LMH6644 ±1 ±5
±7 mV
For LMH6643 ±1 ±3.4
±7
TC VOS Input Offset Average Drift See (4) ±5 µV/°C
IBInput Bias Current See (5) −1.70 −2.60 µA
−3.25
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance 3 MΩ
CIN Common Mode Input 2 pF
Capacitance
CMVR Input Common-Mode Voltage CMRR ≥50dB −0.5 −0.2
Range −0.1 V
3.8 4.0
3.6
CMRR Common Mode Rejection Ratio VCM Stepped from 0V to 3.5V 72 95 dB
AVOL Large Signal Voltage Gain VO= 0.5V to 4.50V 86 98
RL= 2kΩto V+/2 82 dB
VO= 0.5V to 4.25V 76 82
RL= 150Ωto V+/2 72
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 4.90 4.98 V
High RL= 150Ωto V+/2, VID = 200mV 4.65 4.90
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 100 mV
Low RL= 150Ωto V+/2, VID =−200mV 100 150
ISC Output Short Circuit Current Sourcing to V+/2 55 115
VID = 200mV (6)(7) 40 mA
Sinking to V+/2 70 140
VID =−200mV (6)(7) 55
IOUT Output Current VO= 0.5V from either supply ±70 mA
+PSRR Positive Power Supply Rejection V+= 4.0V to 6V 79 90 dB
Ratio
ISSupply Current (per channel) No Load 2.70 4.25 mA
5.00
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) Short circuit test is a momentary test. See Note 7.
(7) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
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±5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 5V, V−=−5V, VCM = VO= 0V, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto ground. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
BW −3dB BW AV= +1, VOUT = 200mVPP 95 130 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain Flatness AV= +2, RL= 150Ωto V+/2, 12 MHz
Rf= 806Ω, VOUT = 200mVPP
PBW Full Power Bandwidth AV= +1, −1dB, VOUT = 2VPP 24 MHz
enInput-Referred Voltage Noise f = 100kHz 17 nV/√Hz
f = 1kHz 48
inInput-Referred Current Noise f = 100kHz 0.90 pA/√Hz
f = 1kHz 3.3
THD Total Harmonic Distortion f = 5MHz, VO= 2VPP, AV= +2 −62 dBc
DG Differential Gain NTSC, AV= +2 0.15
RL= 150Ωto V+/2 %
RL= 1kΩto V+/2 0.01
DP Differential Phase NTSC, AV= +2 0.04
RL= 150Ωto V+/2 deg
RL= 1kΩto V+/2 0.01
CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: 47 dB
Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load, 68 ns
VS= 5V
SR Slew Rate (3) AV=−1, VI= 2VPP 100 135 V/µs
VOS Input Offset Voltage For LMH6642 and LMH6644 ±1 ±5
±7 mV
For LMH6643 ±1 ±3.4
±7
TC VOS Input Offset Average Drift See (4) ±5 µV/°C
IBInput Bias Current See (5) −1.60 −2.60 µA
−3.25
IOS Input Offset Current 20 800 nA
1000
RIN Common Mode Input Resistance 3 MΩ
CIN Common Mode Input 2 pF
Capacitance
CMVR Input Common-Mode Voltage CMRR ≥50dB −5.5 −5.2
Range −5.1 V
3.8 4.0
3.6
CMRR Common Mode Rejection Ratio VCM Stepped from −5V to 3.5V 74 95 dB
AVOL Large Signal Voltage Gain VO=−4.5V to 4.5V, 88 96
RL= 2kΩ84 dB
VO=−4.0V to 4.0V, 78 82
RL= 150Ω74
VOOutput Swing RL= 2kΩ, VID = 200mV 4.90 4.96 V
High RL= 150Ω, VID = 200mV 4.65 4.80
Output Swing RL= 2kΩ, VID =−200mV −4.96 −4.90 V
Low RL= 150Ω, VID =−200mV −4.80 −4.65
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
N/C
+
-
OUTPUT
V-
+IN
V+
-IN
+-
1
2
3
5
4
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for at TJ= 25°C, V+= 5V, V−=−5V, VCM = VO= 0V, VID (input differential
voltage) as noted (where applicable) and RL= 2kΩto ground. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
ISC Output Short Circuit Current Sourcing to Ground 60 115
VID = 200mV (6)(7) 35 mA
Sinking to Ground 85 145
VID =−200mV (6)(7) 65
IOUT Output Current VO= 0.5V from either supply ±75 mA
PSRR Power Supply Rejection Ratio (V+, V−) = (4.5V, −4.5V) to (5.5V, 78 90 dB
−5.5V)
ISSupply Current (per channel) No Load 2.70 4.50 mA
5.50
(6) Short circuit test is a momentary test. See Note 7.
(7) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
Connection Diagram
Figure 3. 5-Pin SOT-23 (LMH6642) Figure 4. 8-Pin SOIC (LMH6642)
Top View Top View
Package Number DBV0005A Package Number D0008A
Figure 5. SOIC and VSSOP 8-Pin Figure 6. 14-Pin SOIC and 14-Pin TSSOP
(LMH6643) (LMH6644)
Top View Top View
Package Number DGK0008A Package Numbers D0014A, PW0014A
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10k 100k 1M 10M 100M 500M
-4
-2
0
GAIN (dB)
FREQUENCY (Hz)
VS = ±5V
RL = 2k
AV = +1
VOUT = 0.2VPP
-40°C
85°C
25°C
100k 1M 10M 200M
FREQUENCY (Hz)
6.5
GAIN (dB)
6.0
AV = +2
RF = 2k
RL = 150
VO = 0.2VPP
±1.5V
5.5
7.0
5.0
±2.5V
±5V
AV = +1
AV = +5
AV = +10
AV = +2
10k 100k 1M 10M 100M 500M
-3
-2
-1
0
+1
+2
+3
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±1.5V
RL = 2k
VOUT = 0.2VPP
10k 100k 1M 10M 100M 500M
-6
-4
-2
0
GAIN (dB)
FREQUENCY (Hz)
-40°C
25°C
85°C
VS = ±1.5V
RL = 2k
AV = +1
VO = 0.2VPP
10k 100k 1M 10M 100M 500
M
-3
-2
-1
0
+1
+2
+3
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±5V
RL = 2k
VOUT = 0.2VPP
AV = +5
AV = +1
AV = +2
AV = +10
100k 1M 10M 200M
FREQUENCY (Hz)
-2
-1
0
GAIN (dB)
-3
VS = ±2.5V
VS = ±5V
VS = ±1.5V
VS = ±1.5V
VS = ±2.5V
VS = ±5V
AV = +1
RL = 2k
VOUT = 0.2VPP
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Typical Performance Characteristics
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
Closed Loop Frequency Response for Various Supplies Closed Loop Gain vs. Frequency for Various Gain
Figure 7. Figure 8.
Closed Loop Gain vs. Frequency for Various Gain Closed Loop Frequency Response for Various Temperature
Figure 9. Figure 10.
Closed Loop Gain
vs.
Frequency for Various Supplies Closed Loop Frequency Response for Various Temperature
Figure 11. Figure 12.
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100k 1M 10M 100M
FREQUENCY (Hz)
0
1
2
3
VOUT (VPP)
VS = 3V
AV = -1
RL = 2k
RL = 100:
100K 1M 10M 100M
FREQUENCY (Hz)
0
1
2
3
4
5
VOUT (VPP)
VS = 5V
AV = -1
Rf = 2k
RL = 2K to VS/2
100K 1M 10M 200M
FREQUENCY (Hz)
-0.1
+0.1
GAIN (dB)
0
VO = 0.4VPP
AV = +2
RF = 806:
RL = 150:
±5V
±2.5V
±1.5V
+0.2
+0.3
PHASE (deg)
-155
-65
-20
+25
±1.5V
±2.5V
±5V
GAIN
PHASE
-110
100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
AV = +2
RF = RL = 2k
±5V
4VPP
±2.5V
2VPP
6.0
8.0
0.0
100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
VO = 0.2VPP
AV = +2
RF = RL = 2k
±5
V
±2.5V
±1.5V
6.0
8.0
0.0
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Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
Closed Loop Small Signal Frequency Response for Various
Large Signal Frequency Response Supplies
Figure 13. Figure 14.
Closed Loop Frequency Response for Various Supplies ±0.1dB Gain Flatness for Various Supplies
Figure 15. Figure 16.
VOUT (VPP) for THD < 0.5% VOUT (VPP) for THD < 0.5%
Figure 17. Figure 18.
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0 1 2 3 4 5
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
HD3 (dBc)
VOUT (VPP)
VS = 5V
AV = -1
RL = 2k to VS/2
5MHz
10MHz
0.0 1.0 2.0 3.0 4.0 5.0
-20
-30
-40
-50
-60
-70
-80
-90
HD2 (dBc)
VOUT (VPP)
VS = 5V, AV = +2
RL = 2k: & 100: to VS/2
100:,1MHz
100:5MHz 2k:, 5MHz
2k:, 10MHz
100:, 10MHz
0 1 2 3 4 5
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
HD2 (dBc)
VOUT (VPP)
5MHz
10MHz
VS = 5V
AV = -1
RL = 2k to VS/2
10k 100k 1M 10M 150M
FREQUENCY (Hz)
-20
0
20
40
60
80
GAIN (dB)
PHASE (Deg)
40
20
0
60
VS = ±5V
RL = 2k -40°C
85°C
25°C
GAIN
PHASE
100k 1M 10M 100M
FREQUENCY (Hz)
0
4
7
10
VOUT (VPP)
VS = ±5V
AV = -1
RL = 100:
8
9
6
5
3
2
1
RL =
2K
FREQUENCY (Hz)
10k 100k 1M 10M 150M
-20
0
20
40
60
80
GAIN (dB)
PHASE (Deg)
40
20
0
60
VS = ±1.5V
RL= 2k
-40°C
85°C
25°C
PHASE
GAIN
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
VOUT (VPP) for THD < 0.5% Open Loop Gain/Phase for Various Temperature
Figure 19. Figure 20.
Open Loop Gain/Phase for Various Temperature HD2 (dBc) vs. Output Swing
Figure 21. Figure 22.
HD3 (dBc) vs. Output Swing HD2 vs. Output Swing
Figure 23. Figure 24.
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Product Folder Links: LMH6642 LMH6643 LMH6644
25°C
85°C
110 100 1K
ISINK (mA)
0.01
0.1
1
10
VOUT FROM V- (V)
-40°C
VS=±1.5V
110 100 1k
ISOURCE (mA)
0.01
0.1
1
10
VOUT FROM V+ (V)
85°C
25°C
-40°C
VS = ±1.5V
±0.1% SETTLING TIME
0.5 1 1.5 2
INPUT STEP AMPLITUDE (VPP)
0
10
20
30
40
50
60
70
80
VS = 5V
AV = -1
Rf = RL = 2k
CL = 8pF
10 100 1K 10K 100K
FREQUENCY (Hz)
1
10
100
1k
1M
100
10
1
0.1
Hz)
en (nV/
Hz)
in (pA/
CURRENT
VOLTAGE
5.0
HD3 (dBc)
0.0 1.0 2.0 3.0 4.0
-20
-30
-40
-50
-60
-70
-80
-90
VOUT (VPP)
VS = 5V, AV = +2
RL = 2k: &100: to VS/2
100:,1MHz
100:,
5MHz
2k:,5MHz
2k:,10MHz
100:, 10MHz
0 1 2 3 4 5
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
THD (dBc)
VOUT (VPP)
5MHz
10MHz
RL = 2k TO VS/2
VS = 5V
AV = -1
LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P –MAY 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
HD3 vs. Output Swing THD (dBc) vs. Output Swing
Figure 25. Figure 26.
Settling Time vs. Input Step Amplitude (Output Slew and
Settle Time) Input Noise vs. Frequency
Figure 27. Figure 28.
VOUT from V+vs. ISOURCE VOUT from V−vs. ISINK
Figure 29. Figure 30.
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0 20 40 60 80 100 120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOUT FROM V+ (V)
ISOURCING (mA)
VS = ±2.5V
25°C
85°C
-40°C
0 20 40 60 80 100 120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOUT FROM V- (V)
ISINK(mA)
25°C
85°C
-40°C
VS = ±2.5
VS (V)
2 3 4 5 6 7 8 9 10
0
180
ISC (mA)
20
40
60
80
100
120
140
160
-40°C, Source
25°C, Source
85°C, Source
-40°C, Sink
25°C, Sink
85°C, Sink
23 4 5 6 7 8 9 10
VS (V)
20
40
60
80
100
120
140
160
VOUT FROM SUPPLY (mV)
-40°C, Sourcing
25°C, Sourcing
85°C, Sourcing
25°C, Sinking
85°C, Sinking
-40°C, Sinking
RL = 150:
110 100 1k
ISOURCE (mA)
0.01
0.1
1
10
VOUT FROM V+ (V)
85°
C
25°C
-40°C
85°C
-40°C
VS = ±5V
110 100 1k
ISINK (mA)
0.01
0.1
1
10
VOUT FROM V- (V)
85°C
25°C
-40°C
VS = ±5V
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
VOUT from V+vs. ISOURCE VOUT from V−vs. ISINK
Figure 31. Figure 32.
Swing vs. VSShort Circuit Current (to VS/2) vs. VS
Figure 33. Figure 34.
Output Sinking Saturation Voltage vs. IOUT Output Sourcing Saturation Voltage vs. IOUT
Figure 35. Figure 36.
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-2 0 2 4 6 8 10
VCM (V)
-2
-1.5
-1
-0.5
0
0.5
1.0
1.5
2
VOS (mV)
-40°C
25°C
85°C
VS = 10V
1k 10k 100k 1M 10M
FREQUENCY (Hz)
30
40
50
60
70
80
90
100
CT (rej) (dB)
Receive CH.: AV = +2, Rf = Rg = 510
30
40
50
60
70
100
CMRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
80
90
10M
VS = 5V
AV = +6
1k 100k 10M
FREQUENCY (Hz)
0.01
1
1000
ZOUT (:)
100M
1M
10k
100
10
0.1
AV = +1
10k 100k 1M 10M 100M
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
PSRR (dB)
+ PSRR
- PSRR
VS = 5V
AV = +10
LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P –MAY 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
Closed Loop Output Impedance vs. Frequency AV= +1 PSRR vs. Frequency
Figure 37. Figure 38.
CMRR vs. Frequency Crosstalk Rejection vs. Frequency (Output to Output)
Figure 39. Figure 40.
VOS vs. VOUT (Typical Unit) VOS vs. VCM (Typical Unit)
Figure 41. Figure 42.
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2 4 6 8 10 12
0
5
10
15
20
25
30
35
40
45
50
IOS (nA)
VS (V)
-40°C
25°C
85°C
-2 0 2 4 6 8 10
VCM (V)
-0.5
0.5
1
1.5
2
2.5
3
3.5
4
IS (mA) (PER CHANNEL)
-40°C
25°C
85°C
VS = 10V
0
2 4 6 8 10 12
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
85°C
53 7 9
-1000
2 4 6 8 10 12
-1900
-1800
-1700
-1600
-1500
-1400
-1300
-1200
-1100
IB (nA)
VS (V)
-40°C
25°C
85°C
2 4 6 8 10 12
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
-40°C
2 4 6 8 10 11
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
25°C
9
7
5
3
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
VOS vs. VS(for 3 Representative Units) VOS vs. VS(for 3 Representative Units)
Figure 43. Figure 44.
VOS vs. VS(for 3 Representative Units) IBvs. VS
Figure 45. Figure 46.
IOS vs. VSISvs. VCM
Figure 47. Figure 48.
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40 mV/DIV 10.0 ns/DIV
VS = ±5V
VO = 100mVPP
AV = +1, RL = 2k
40 mV/DIV 10 ns/DIV
VS = 3V
VO = 100mVPP
RL = 2k to VS/2
AV = +1
400 mV/DIV 40.0 nS/DIV
VS=±1.5V
VO=2VPP
AV= -1
RL=2k
4 /DIV
VS = ±5V
VO = 8VPP
RL= 2k
AV = +2
AV = +1
200.0 ns/DIV
2 4 6 8 10 12
1
2
3
4
IS (mA) (PER CHANNEL)
VS (V)
85°C
-40°C
25°C
VS = 3V
VO = 100mVPP
RL = 2k to VS/2
AV = -1
40 mV/DIV 20 ns/DIV
LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P –MAY 2001–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
ISvs. VSSmall Signal Step Response
Figure 49. Figure 50.
Large Signal Step Response Large Signal Step Response
Figure 51. Figure 52.
Small Signal Step Response Small Signal Step Response
Figure 53. Figure 54.
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2 V/DIV 100 ns/DIV
AV = -1 VS = ±5V
VOUT = 8VPP RL = 2K:
2 V/DIV
VS = ±5V
VO = 8VPP
AV = +2
RL = 2k
40.0 ns/DIV
VS = ±5V
VO = 2VPP
RL = 2k
AV = -1
400 mV/DIV 20 ns/DIV
VS = ±5V
VO = 200mVPP
AV = +2,
RL = 2k
40 mV/DIV 20.0 ns/DIV
VS = ±5V
VO = 100mVPP
RL = 2k
AV = -1
20 ns/DIV
40 mV/DIV
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TJ= 25°C, V+= +5, V−=−5V, RF= RL= 2kΩ. Unless otherwise specified.
Small Signal Step Response Small Signal Step Response
Figure 55. Figure 56.
Large Signal Step Response Large Signal Step Response
Figure 57. Figure 58.
Large Signal Step Response
Figure 59.
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VOUT (VPP)
1V/DIV 200 ns/DIV
VS = ±2.5V
AV = +1
V+
V-
Output
Input
LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P –MAY 2001–REVISED MARCH 2013
APPLICATION INFORMATION
CIRCUIT DESCRIPTION
The LMH664X family is based on proprietary VIP10 dielectrically isolated bipolar process.
This device family architecture features the following:
• Complimentary bipolar devices with exceptionally high ft(∼8GHz) even under low supply voltage (2.7V) and
low bias current.
• A class A-B “turn-around” stage with improved noise, offset, and reduced power dissipation compared to
similar speed devices (patent pending).
• Common Emitter push-push output stage capable of 75mA output current (at 0.5V from the supply rails) while
consuming only 2.7mA of total supply current per channel. This architecture allows output to reach within
milli-volts of either supply rail.
• Consistent performance over the entire operating supply voltage range with little variation for the most
important specifications (e.g. BW, SR, IOUT, etc.)
• Significant power saving (∼40%) compared to competitive devices on the market with similar performance.
Application Hints
This Op Amp family is a drop-in replacement for the AD805X family of high speed Op Amps in most applications.
In addition, the LMH664X will typically save about 40% on power dissipation, due to lower supply current, when
compared to competition. All AD805X family’s guaranteed parameters are included in the list of LMH664X
guaranteed specifications in order to ensure equal or better level of performance. However, as in most high
performance parts, due to subtleties of applications, it is strongly recommended that the performance of the part
to be evaluated is tested under actual operating conditions to ensure full compliance to all specifications.
With 3V supplies and a common mode input voltage range that extends 0.5V below V−, the LMH664X find
applications in low voltage/low power applications. Even with 3V supplies, the −3dB BW (@ AV= +1) is typically
115MHz with a tested limit of 80MHz. Production testing guarantees that process variations with not compromise
speed. High frequency response is exceptionally stable confining the typical −3dB BW over the industrial
temperature range to ±2.5%.
As can be seen from the typical performance plots, the LMH664X output current capability (∼75mA) is enhanced
compared to AD805X. This enhancement, increases the output load range, adding to the LMH664X’s versatility.
Because of the LMH664X’s high output current capability attention should be given to device junction
temperature in order not to exceed the Absolute Maximum Rating.
This device family was designed to avoid output phase reversal. With input overdrive, the output is kept near
supply rail (or as closed to it as mandated by the closed loop gain setting and the input voltage). See Figure 60:
Figure 60. Input and Output Shown with CMVR Exceeded
However, if the input voltage range of −0.5V to 1V from V+is exceeded by more than a diode drop, the internal
ESD protection diodes will start to conduct. The current in the diodes should be kept at or below 10mA.
Output overdrive recovery time is less than 100ns as can be seen from Figure 61 plot:
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IN+ IN-
R R
V-
V+
V+V+
V-
VIN (1 V/DIV)
VOUT (2 V/DIV)
VS=±5V, VIN=5VPP
AV=+5, RF=RL=2k
2 V/DIV 100 ns/DIV
LMH6642, LMH6643, LMH6644
SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
Figure 61. Overload Recovery Waveform
INPUT AND OUTPUT TOPOLOGY
All input / output pins are protected against excessive voltages by ESD diodes connected to V+and V-rails (see
Figure 62). These diodes start conducting when the input / output pin voltage approaches 1Vbe beyond V+or V-
to protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is
provided by the two resistors (R in Figure 62), in conjunction with the string of anti-parallel diodes connected
between both bases of the input stage. The combination of these resistors and diodes reduces excessive
differential input voltages approaching 2Vbe. The most common situation when this occurs is when the device is
used as a comparator (or with little or no feedback) and the device inputs no longer follow each other. In such a
case, the diodes may conduct. As a consequence, input current increases and the differential input voltage is
clamped. It is important to make sure that the subsequent current flow through the device input pins does not
violate the Absolute Maximum Ratings of the device. To limit the current through this protection circuit, extra
series resistors can be placed. Together with the built-in series resistors of several hundred ohms, these external
resistors can limit the input current to a safe number (i.e. < 10mA). Be aware that these input series resistors
may impact the switching speed of the device and could slow down the device.
Figure 62. Input Equivalent Circuit
SINGLE SUPPLY, LOW POWER PHOTODIODE AMPLIFIER
The circuit shown in Figure 63 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application.
This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the
photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the
Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single
supply operation. With 5V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
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200 mV/DIV 20 ns/DIV
+
-
Vbias
Cd10
-
200pF
Photodiode Rd
C1
100nF Q1
2N3904
R5
510:
R2
1.8k:
D1
1N4148
R3
1k:
R11
910
:R10
1k:
-1mAPP
Cf
5pF
Rf
1k:
VCC =
+5V
Rbias
Photodiode
Equivalent
Circuit
Id×100k:
Vout
+5V
x
SQRT GBWP/(2SRF ˜CIN)
fP =
CF =SQRT (CIN)/(2S˜GBWP ˜RF)
LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P –MAY 2001–REVISED MARCH 2013
No matter how low an Rfis selected, there is a need for Cfin order to stabilize the circuit. The reason for this is
that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional
phase shift to the signal fed back to the inverting node. Cfwill function as a zero in the feedback path counter-
acting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cfsuch that the Op Amp
open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a
theoretical 45° phase margin.
(1)
where GBWP is the Gain Bandwidth Product of the Op Amp
Optimized as such, the I-V converter will have a theoretical pole, fp, at:
(2)
With Op Amp input capacitance of 3pF and an estimate for Q1 output capacitance of about 3pF as well, CIN =
6pF. From the typical performance plots, LMH6642/6643 family GBWP is approximately 57MHz. Therefore, with
Rf= 1k, from Equation 1 and Equation 2 above.
Cf=∼4.1pF and fp= 39MHz
Figure 63. Single Supply Photodiode I-V Converter
For this example, optimum Cfwas empirically determined to be around 5pF. This time domain response is shown
in Figure 64 below showing about 9ns rise/fall times, corresponding to about 39MHz for fp. The overall supply
current from the +5V supply is around 5mA with no load.
Figure 64. Converter Step Response (1VPP, 20 ns/DIV)
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SNOS966P –MAY 2001–REVISED MARCH 2013
www.ti.com
PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT VALUES SECTION
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 for more information). Texas Instruments suggests the
following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device Package Evaluation Board PN
LMH6642MF 5-Pin SOT-23 LMH730216
LMH6642MA 8-Pin SOIC LMH730227
LMH6643MA 8-Pin SOIC LMH730036
LMH6643MM 8-Pin VSSOP LMH730123
LMH6644MA 14-Pin SOIC LMH730231
LMH6644MT 14-Pin TSSOP LMH730131
Another important parameter in working with high speed/high performance amplifiers, is the component values
selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage
because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to
the device or a by-product of the board layout and component placement. Either way, keeping the resistor values
lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors could
load down nodes and will contribute to higher overall power dissipation.
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SNOS966P –MAY 2001–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision O (March 2013) to Revision P Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com 9-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6642MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
42MA
LMH6642MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
42MA
LMH6642MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A64A
LMH6642MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A
LMH6642MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A
LMH6643MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH66
43MA
LMH6643MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
43MA
LMH6643MAX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMH66
43MA
LMH6643MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
43MA
LMH6643MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 A65A
LMH6643MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A
LMH6643MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A
LMH6644MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA
LMH6644MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA
LMH6644MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
44MT
LMH6644MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
44MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Nov-2013
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
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(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6642MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6642MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6642MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6642MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6643MAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6643MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6644MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMH6644MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6642MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6642MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6642MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6642MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6643MAX SOIC D 8 2500 367.0 367.0 35.0
LMH6643MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6644MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMH6644MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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