VCXO JITTER ATTENUATOR & ICS814252I-02
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 1 ICS814252CKI-02 REV. A OCTOBER 5, 2007
PRELIMINARY
FEMTOCLOCK™ MULTIPLIER
GENERAL DESCRIPTION
The ICS814252I-02 is a member of the
HiperClockS™ family of high performance clock
solutions from IDT. The ICS814252I-02 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
PIN ASSIGNMENT
HiPerClockS™
ICS
FEATURES
•Two LVDS outputs
Each output supports independent frequency selection at
25MHz, 125MHz, 156.25MHz and 312.5MHz
•Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
•Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
•VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
•FemtoClock frequency multiplier provides low jitter, high
frequency output
•Absolute pull range: 50ppm
•FemtoClock VCO frequency: 625MHz
•RMS phase jitter @ 125MHz, using a 25MHz crystal
(10kHz – 20MHz): 1.2ps (typical)
•3.3V supply voltage
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
nQB
QB
VDDO
nQA
QA
GND
ODASEL_0
ICS814252I-02
PDSEL_2
PDSEL_1
PDSEL_0
VDD
VDDA
ODBSEL_1
ODBSEL_0
ODASEL_1
nCLK1
CLK1
VDD
nCLK0
CLK0
XTAL_OUT
XTAL_IN
VDDX
LF1
LF0
ISET
GND
CLK_SEL
VDD
RESERVED
GND
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 2 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
BLOCK DIAGRAM
Charge
Pump
VCXO
Phase
Detector
Output
Divider
00 = 25
01 = 5
10 = 4
11 = 2
VCXO Feedback Divider
÷3125
VCXO Input
Pre-Divider
VCXO Jitter Attenuation PLL
XTAL_IN
XTAL_OUT
LF1
LF0
ISET
Loop
Filter
ODASEL_[1:0]
CLK0
PDSEL_[2:0]
nCLK0
0
1
25MHz
2
QB
nQB
QB
nQB
Output
Divider
00 = 25
01 = 5
10 = 4
11 = 2
ODBSEL_[1:0]
2
FemtoClock PLL
625MHz
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
CLK1
nCLK1
CLK_SEL
Pulldown
Pullup
QA
nQA
Q
nQ
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 3 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
2,10FL,1FL golanA
tuptuO/tupnI .snipedonnoitcennocretlifpooL
3TESI golanA
tuptuO/tupnI .
nipgnittestnerrucpmupegrahC
,81,8,4
42 DNGrewoP.dnuorgylppusrewoP
5LES_KLCtupnInwodlluP .1KLCn/1KLCstcelesHGIHn
ehW.tceleskcolctupnI
.slevelecafretniLTTVL/SOMCVL.0KLCn/0KLCstceles,WOLnehW
72,21,6V
DD
rewoP.snipylppusrewoperoC
7DEVRESERdevreseR.tcennoctonoD.nipdevreseR
,9
,01
11
,2_LESDP
,1_LESDP
0_LESDP
tupnIpull
uP .slevelecafretniLTTVL/SOMCVL.sniptcelesredivid-erP
.A3elbaTeeS
31V
ADD
rewoP.nipylppusgolanA
,41
51
,1_LESBDO
0_LESBDO tupnInwodlluP .B3elbaTeeS.tuptuoBknaBrofsniptcelesycneuqerF
.s
levelecafretniLTTVL/SOMCVL
,61
71
,1_LESADO
0_LESADO tupnInwodlluP .B3elbaTeeS.tuptuoAknaBrofsniptcelesycneu
qerF
.slevelecafretniLTTVL/SOMCVL
02,91AQn,AQtuptuO .slevelecafretniSDVL.stuptuokcolcAknaBlaitnereffiD
12V
ODD
rewoP.nipylppusrewoptuptuO
32,22BQn,BQtuptuO .slevelecafretniSDVL.stuptuokcolcBknaBlaitnereffiD
521KLCntupnI /
pulluP
nwodlluP
V.tupnikcolclaitnereffidgnitrevnI
DD
tfelnehwegatlovsaib2/
.gnitaolf
621KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
820KLCntupnI /pulluP
nwo
dlluP
V.tupnikcolclaitnereffidgnitrevnI
DD
tfelnehwegatlovsaib2/
.gnitaolf
920KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
,03
13
,TUO_LATX
NI_LAT
XtupnI .tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoehtsiTUO_LATX
23V
XDD
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:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaT
eeS.srotsisertupnilanretniotrefer
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 4 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
stupnI eulaVrediviD-erP
2_LESDP1_LESDP0_LESDP
000 1
00 1 391
010 652
011 0342
10 0 5213
10 1 0279
110 52651
111 )tluafed(04491
stupnI eulaVrediviDtuptuO
1_LESxDO0_LESxDO
00 )tluafed(52
01 5
10 4
11 2
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 5 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 3C. FREQUENCY FUNCTION TABLE
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ycneuqerF
)zHM(
rediviD-erP
eulaV
OXCV
ycneuqerF
)zHM(
kcolCotmeF
rediviDkcabdeeF
eulaV
kcolcotmeF
ycneuqer
FOCV
)zHM(
rediviDtuptuO
eulaV
ycneuqerFtuptuO
)zHM(
800.0152525265252
800.0152525265 521
800.0152525264 52.651
800.0152525262 5.213
445.13
9152525265252
445.139152525265 521
445.139152525264 52.651
445.139152525262 5.213
840.265252525265252
840.265252525265 521
840.265252525264 52.651
840.26525
2525262 5.213
44.91034252525265252
44.91034252525265 521
44.91034252525264 52.651
44.91034252525262 5.213
52521352525265252
52521352525265 521
52521352525264 52
.651
52521352525262 5.213
67.77027952525265252
67.77027952525265 521
67.77027952525264 52.651
67.77027952525262 5.213
5215265152525265252
52152651525252
65 521
5215265152525264 52.651
5215265152525262 5.213
25.5510449152525265252
25.5510449152525265 521
25.5510449152525264 52.651
25.5510449152525262 5.2
13
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 6 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V±5%, TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θJA 37°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Character istics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
DD
01.0–3.3V
DD
V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
V
XDD
egatloVylppuSpmuPegrahC 531.33.3564.3V
I
DD
I+
XDD
tnerruCylppuSrewoP 661Am
I
ADD
tnerruCylppuSgolanA 01Am
I
ODD
tnerruCylppuStuptuO 53Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
tupnIegatloVhgiH2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tupnI
tnerruChgiH
,LES_KLC
,]1:0[_LESADO
]1:0[_LESBDO
V
DD
V=
NI
V564.3=051Aµ
]2:0{LESDPV
DD
V=
NI
V564.3=5Aµ
I
LI
tupnI
tnerruCwoL
,LES_KLC
,]1:0[_LESADO
]1:0[_LESBDO
V
DD
V,V564.3=
NI
V0=5-Aµ
]2:0{LESDPV
DD
V,V564.3=
NI
V0=051-Aµ
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 7 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DO
egatloVtuptuOlaitnereffiD 053Vm
ΔV
DO
V
DO
egnahCedutingaM 04Vm
V
SO
egatloVtesffO 54.1V
ΔV
SO
V
SO
egnahCedutingaM 05Vm
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI ,0KLCn/0KLC
1KLCn/1KLC V
NI
V=
DD
V564.3=051Aµ
I
LI
tnerruCwoLtupnI 1KLC,0KLCV
NI
V,V0=
DD
V564.3=5-Aµ
1KLCn,0KLCnV
NI
V,V0=
DD
V564.3=051-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV
DD
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsixKLCn,xKLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
NI
ycneuqerFtupnI 800.025.551zHM
f
TUO
ycneuqerFtuptuO 525.213zHM
t)Ø(tij ;)modnaR(rettiJesahPSMR
1ETON
zHM521f
,TUO
latsyrczHM52
:egnaRnoitargetnI
zHM02–zHk01
2.1sp
t)o(ks3,2ETON;wekStuptuO 03sp
cdoelcyCytuDtuptuO 05%
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02054sp
t
KCOL
emiTkcoLLLP 001sm
.htdiwdnabpooldimehtrofstnenopmocretlifpoolehtgnisuycneuqerfemasehttastuptuohtiwdezire
tcarahC
otrefeR .elbaTnoitceleShtdiwdnaBpooLLLP-OXCV
.tolPesioNesahPehtotreferesaelP:1ETON
.56dradnatSCED
EJhtiwecnadroccanidenifedsiretemarapsihT:2ETON
.snoitdnocdaollauqehtiwdnaegatlovylppusemasehttastuptuo
neewtebwekssadenifeD:3ETON
.stniopssorclaitnereffidtuptuoehttaderusaeM
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 8 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
PHASE JITTER
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
3.3V±5%
POWER SUPPLY
+–
Float GND
LVDS
VDD,
VDDO,
VDDX
OUTPUT SKEW
VDDA
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
V
CMR
Cross Points
V
PP
GND
nCLK0,
nCLK1
VDD
CLK0,
CLK1
t
sk(o)
FOUTx
FOUTy
nFOUTx
nFOUTy
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
QA, QB
nQA, nQB
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OUTPUT VOLTAGE SETUP
➤
➤
➤
100
out
out
LVD S
DC Input VOD/Δ VOD
VDD
out
out
LVD S
DC Input
➤
➤
➤
V
OS
/Δ V
OS
V
DD
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 9 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS814252I-02 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDX, VDDA, and VDDO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a 0.01µF bypass capacitor should be con-
nected to each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
V
DD
V
DDX
V
DDA
3.3V
10Ω
10Ω
10µF.01µF
.01µF
10µF.01µF
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 10 ICS813252CKI-02 REV. A OCTOBER 5, 2007
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
HIPERCLOCKS LVHSTL DRIVER
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in Figure
3A, the input termination applies for IDT HiPerClockS open emitter
LVHSTL drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
HCSL
*R3 33
*R4 33
CLK
nCLK
2.5V 3.3V
Zo = 50Ω
Zo = 50Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60Ω
Zo = 60Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 11 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
CLK/nCLK INPUTS
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 12 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
3.3V LVDS DRIVER T ERMINATION
A general LVDS interface is shown in Figure 5. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 13 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must
be taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with
the package, it is recommended that a metal-canned package
like HC49 be used. Generally, a metal-canned package has a
larger pulling range than a surface mounted device (SMD). For
crystal selection information, refer to the VCXO Crystal Selection
Application Note.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal CL is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
CRYSTAL CHARACTERISTICS
VCXO CHARACTERISTICS TABLE
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the crystal specification. In either case, the absolute tuning range
is reduced. The correct value of CL is dependant on the
characteristics of the VCXO. The recommended CL in the Crystal
Parameter T able balances the tuning range by centering the tuning
curve.
The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS
and CP values for recommended high, mid and low loop bandwidth
configurations. The device has been characterized using these
parameters. For other configurations, refer to the Loop Filter
Component Selection for VCXO Based PLLs Application Note.
The crystal and external loop
filter components should be
kept as close as possible to the
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
R
S
CS
CP
RSET
CTUNE
CTUNE
25MHz
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IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 14 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS814252I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS814252I-02 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•Power (core)MAX = VDD_MAX * ((IDD_MAX + IDDX_MAX) + IDDA_MAX + IDDO_MAX) = 3.465V * (166mA + 10mA + 35mA) = 731mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.731W * 37°C/W = 112°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 32-LEAD VFQFN, FORCED CONVECTION
θθ
θθ
θJA vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 15 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS814252I-02 is: 6579
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θθ
θθ
θJA vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 16 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
TABLE 8. PACKAGE DIMENSIONS
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
Reference Document: JEDEC Publication 95, MO-220
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3A .feR52.0
b81.052.003.0
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8
DCISAB00.5
2D 52.152.252.3
ECISAB00.5
2E 52.152.252.3
eCISAB05.0
L03.004.005.0
NOTE: The above mechanical package drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package
dimensions are in Table 8 below.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER 17 ICS814252CKI-02 REV. A OCTOBER 5, 2007
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 9. ORDERING INFORMATION
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Innovate with IDT and accelerate your future networks. Contact:
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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER PRELIMINARY
