PRELIMINARY ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER GENERAL DESCRIPTION FEATURES The ICS814252I-02 is a member of the ICS HiperClockSTM family of high performance clock HiPerClockSTM solutions from IDT. The ICS814252I-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClockTM frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. * Two LVDS outputs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz * Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz * Attenuates the phase jitter of the input clock by using a lowcost pullable fundamental mode VCXO crystal * VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection * FemtoClock frequency multiplier provides low jitter, high frequency output * Absolute pull range: 50ppm * FemtoClock VCO frequency: 625MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (10kHz - 20MHz): 1.2ps (typical) * 3.3V supply voltage * -40C to 85C ambient operating temperature PIN ASSIGNMENT * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages nCLK1 VDD CLK1 CLK0 nCLK0 XTAL_OUT VDDX XTAL_IN 32 31 30 29 28 27 26 25 LF1 1 24 GND LF0 2 23 nQB ISET 3 22 QB GND 4 21 VDDO CLK_SEL 5 20 nQA ICS814252I-02 VDD 6 19 QA RESERVED 7 18 GND GND 8 17 ODASEL_0 ODASEL_1 ODBSEL_0 ODBSEL_1 VDD VDDA PDSEL_0 PDSEL_1 PDSEL_2 9 10 11 12 13 14 15 16 32-Lead VFQFN 5mm x 5mm x 0.925 package body K Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 1 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY BLOCK DIAGRAM VCXO Input Pre-Divider CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Pulldown 0 1 000 = 1 001 = 193 010 = 256 011 = 2430 100 = 3125 101 = 9720 110 = 15625 111 = 19440 XTAL_OUT XTAL_IN LF1 ISET PDSEL_[2:0] Pullup LF0 Loop Filter Output Divider QA Q 00 = 25 01 = 5 10 = 4 11 = 2 25MHz Phase Detector nQA nQ 2 VCXO Charge Pump VCXO Feedback Divider /3125 VCXO Jitter Attenuation PLL FemtoClock PLL 625MHz Output Divider QB 00 = 25 01 = 5 10 = 4 11 = 2 nQB 2 IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 2 ODASEL_[1:0] ODBSEL_[1:0] ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Analog Input/Output Analog Input/Output 1, 2 LF1, LF0 3 ISET 4, 8, 18, 24 G ND Power 5 CLK_SEL Input 6, 12, 27 V DD Power 7 9, 10 , 11 13 14, 15 16, 17 19, 20 RESERVED PDSEL_2, PDSEL_1, PDSEL_0 VDDA ODBSEL_1, ODBSEL_0 ODASEL_1, ODASEL_0 QA, nQA Reser ved Input Power Input Input Output Description Loop filter connection node pins. Charge pump current setting pin. Power supply ground. Pulldown Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels. Core power supply pins. Reser ved pin. Do not connect. Pullup Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A. Analog supply pin. Frequency select pins for Bank B output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Frequency select pins for Bank A output. See Table 3B. Pulldown LVCMOS/LVTTL interface levels. Differential Bank A clock outputs. LVDS interface levels. 21 VDDO Power Output power supply pin. 22, 23 QB, nQB Output 25 nCLK1 Input 26 CLK1 Input 28 nCLK0 Input 29 30, 31 CLK0 XTAL_OUT, XTAL_IN Input Differential Bank B clock outputs. LVDS interface levels. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 bias voltage when left floating. Non-inver ting differential clock input. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. 32 VDDX Power Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Input Power supply pin for VCXO charge pump. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 3 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY TABLE 3A. PRE-DIVIDER FUNCTION TABLE Inputs Pre-Divider Value PDSEL_2 PDSEL_1 PDSEL_0 0 0 0 1 0 0 1 193 0 1 0 256 0 1 1 2430 1 0 0 3125 1 0 1 9720 1 1 0 15625 1 1 1 19440 (default) TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE Inputs ODxSEL_1 ODxSEL_0 0 0 Output Divider Value 25 (default) 0 1 5 1 0 4 1 1 2 IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 4 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY TABLE 3C. FREQUENCY FUNCTION TABLE Input Frequency (MHz) 0.008 0.008 1 VCXO Frequency (MHz) 25 FemtoClock Feedback Divider Value 25 Femtoclock VCO Frequency (MHz) 625 1 25 25 Pre-Divider Value Output Divider Value Output Frequency (MHz) 25 25 625 5 12 5 0.008 1 25 25 625 4 156.25 0.008 1 25 25 62 5 2 312.5 1.544 193 25 25 625 25 25 1.544 193 25 25 62 5 5 125 1.544 19 3 25 25 625 4 156.25 1.544 193 25 25 62 5 2 312.5 2.048 256 25 25 625 25 25 2.048 256 25 25 625 5 125 2.048 25 6 25 25 625 4 156.25 2.048 256 25 25 625 2 312.5 19.44 2430 25 25 625 25 25 19.44 2430 25 25 625 5 12 5 19.44 2430 25 25 625 4 156.25 19.44 2430 25 25 625 2 312.5 25 3125 25 25 625 25 25 25 3125 25 25 625 5 125 25 3125 25 25 625 4 156.25 25 3125 25 25 625 2 312.5 77.76 9720 25 25 625 25 25 77.76 9720 25 25 625 5 125 77.76 9720 25 25 625 4 156.25 77.76 9720 25 25 625 2 312.5 125 15625 25 25 625 25 25 125 15625 25 25 625 5 12 5 125 1562 5 25 25 625 4 156.25 125 1562 5 25 25 625 2 312.5 155.52 19440 25 25 625 25 25 155.52 19440 25 25 625 5 12 5 155.52 19440 25 25 625 4 156.25 155.52 19440 25 25 625 2 312.5 IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 5 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V5%, TA = -40C TO 85C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.10 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDX Charge Pump Supply Voltage IDD + IDDX Power Supply Current 166 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 35 mA V TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V5%, TA = -40C TO 85C Symbol Parameter Maximum Units VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current VDD = VIN = 3.465V 15 0 A VDD = VIN = 3.465V 5 A IIL Input Low Current Test Conditions CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL{0:2] CLK_SEL, ODASEL_[0:1], ODBSEL_[0:1] PDSEL{0:2] IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER Minimum Typical VDD = 3.465V, VIN = 0V -5 A VDD = 3.465V, VIN = 0V -150 A 6 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical Maximum Units 150 A CLK0/nCLK0, CLK1/nCLK1 CLK0, CLK1 VIN = 0V, VDD = 3.465V -5 A nCLK0, nCLK1 VIN = 0V, VDD = 3.465V -150 A IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VIN = VDD = 3.465V 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. 1.3 V VDD - 0.85 V Maximum Units TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V5%, TA = -40C TO 85C Symbol Parameter Test Conditions Minimum Typical VOD Differential Output Voltage 350 mV VOD VOD Magnitude Change 40 mV VOS Offset Voltage VOS VOS Magnitude Change 1.45 V 50 mV TABLE 5. AC CHARACTERISTICS, VDD = VDDO = VDDX = 3.3V5%, TA = -40C TO 85C Symbol Parameter fIN Input Frequency fOUT Output Frequency t jit(O) RMS Phase Jitter (Random); NOTE 1 t sk(o) odc t R / tF Output Rise/Fall Time Test Conditions 125MHz fOUT, 25MHz cr ystal Integration Range: 10kHz - 20MHz Minimum Typical Maximum Units 0.008 155.52 MHz 25 312.5 MHz 1.2 ps Output Skew; NOTE 2, 3 30 ps Output Duty Cycle 50 % 20% to 80% 450 PLL Lock Time 100 tLOCK Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth. Refer to VCXO-PLL Loop Bandwidth Selection Table. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions. Measured at the output differential cross points. IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 7 ps ms ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD SCOPE VDD, VDDO, VDDA VDDX 3.3V5% POWER SUPPLY + Float GND - Qx nCLK0, nCLK1 LVDS V V Cross Points PP nQx CMR CLK0, CLK1 GND DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nFOUTx FOUTx Phase Noise Mask nFOUTy FOUTy f1 Offset Frequency tsk(o) f2 RMS Jitter = Area Under the Masked Phase Noise Plot OUTPUT SKEW PHASE JITTER nQA, nQB 80% 80% QA, QB VSW I N G Clock Outputs t PW 20% 20% tR t PERIOD tF t PW odc = x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD OUTPUT RISE/FALL TIME VDD VDD out out DC Input LVDS 100 VOS/ VOS out DIFFERENTIAL OUTPUT VOLTAGE SETUP OUTPUT VOLTAGE SETUP IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER VOD/ VOD LVDS DC Input out 8 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES 3.3V As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS814252I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDX, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin. VDD .01F 10 VDDX 10 .01F 10F VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 9 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS813252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50 R4 120 Zo = 60 CLK CLK Zo = 50 Zo = 60 nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional - R3 and R4 can be 0 FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 10 ICS813252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. PRELIMINARY OUTPUTS: LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. CLK/nCLK INPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE) IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 11 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 5. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 5. TYPICAL LVDS DRIVER TERMINATION IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 12 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY VCXO-PLL EXTERNAL COMPONENTS the crystal specification. In either case, the absolute tuning range is reduced. The correct value of C L is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than LF0 LF1 ISET RS CP RSET CS XTAL_IN CTUNE 25MHz XTAL_OUT CTUNE VCXO CHARACTERISTICS TABLE Symbol Parameter Typical Unit kVCXO VCXO Gain 15700 Hz/V CV_LOW Low Varactor Capacitance 9.9 pF CV_HIGH High Varactor Capacitance 22.2 pF VCXO-PLL LOOP BANDWIDTH SELECTION TABLE Bandwidth Crystal Frequency (MHz) RS (k ) CS (F) CP (F) RSET (k ) 10Hz (Low) 25MHz 121 1.0 0.01 9.09 90Hz (Mid) 25MHz 22 1 0.1 0.001 2.21 300Hz (High) 25MHz 680 0.1 0.0001 2.21 CRYSTAL CHARACTERISTICS Symbol Parameter Minimum Mode of Operation fN Frequency fT Frequency Tolerance fS Frequency Stability Operating Temperature Range CL Shunt Capacitance CO /C1 Pullability Ratio ESR Equivalent Series Resistance Maximum 25 Units MHz -40 Load Capacitance CO Typical Fundamental IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER ppm 20 ppm 85 C 10 pF 4 pF 22 0 24 0 20 Drive Level Aging @ 25C 20 1 mW 3 per year ppm 13 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS814252I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS814252I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * ((IDD_MAX + IDDX_MAX) + IDDA_MAX + IDDO_MAX) = 3.465V * (166mA + 10mA + 35mA) = 731mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.731W * 37C/W = 112C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 32-LEAD VFQFN, FORCED CONVECTION JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 14 0 1 2.5 37.0C/W 32.4C/W 29.0C/W ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 37.0C/W 32.4C/W 29.0C/W TRANSISTOR COUNT The transistor count for ICS814252I-02 is: 6579 IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 15 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN NOTE: The above mechanical package drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL 32 N A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b 0.18 0.25 8 NE 5.00 BASIC D 1.25 2.25 1.25 2.25 3.25 0.50 BASIC e L 3.25 5.00 BASIC E E2 0.30 8 ND D2 MAXIMUM 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 16 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 814252CKI-02 ICS4252CI02 32 Lead VFQFN tray -40C to 85C 814252CKI-02T ICS4252CI02 32 Lead VFQFN 2500 tape & reel -40C to 85C 814252CKI-02LF ICS452CI02L 32 Lead "Lead-Free" VFQFN tray -40C to 85C 814252CKI-02LFT ICS452CI02L 32 Lead "Lead-Free" VFQFN 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM VCXO JITTER ATTENUATOR/MULTIPLIER 17 ICS814252CKI-02 REV. A OCTOBER 5, 2007 ICS814252I-02 VCXO JITTER ATTENUATOR & FEMTOCLOCKTM MULTIPLIER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA