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April 1st, 2010
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RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 1 of 12
R1RP0408D Series
4M High Speed SRAM (512-kword × 8-bit)
REJ03C0112-0200
Rev. 2.00
Dec.1.2008
Description
The R1RP0408D Series is a 4-Mbit high speed static RAM organized 512-k word × 8-bit. It has realized
high speed access time by employing CMOS process (6-transistor memory cell) and high speed circu it
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in
400-mil 36-pin plastic SOJ.
Features
• Single 5.0 V supply: 5.0 V ± 10%
• Access time: 10 ns / 12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 140mA /130mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current : 5 mA (max)
: 1.0 mA (max) (L-version)
• Data retention current: 0.5 mA (max) (L-version)
• Data retention voltage: 2 V (min) (L-version)
• Center VCC and VSS type pin out
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 2 of 12
Ordering Information
Type No. Access time Package
R1RP0408DGE-0PR 10 ns 400-mil 36-pin plastic SOJ (36P0K)
R1RP0408DGE-2PR 12 ns
R1RP0408DGE-2LR 12 ns
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
VCC
VSS
I/O3
I/O4
WE#
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE#
I/O8
I/O7
VSS
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
(Top View)
36-pin SOJ
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 3 of 12
Pin Description
Pin name Function
A0 to A18 Address input
I/O1 to I/O8 Data input/output
CS# Chip select
OE# Output enable
WE# Write enable
VCC Power supply
VSS Ground
NC No connection
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 4 of 12
Block Diagram
I/O1
.
.
.
I/O8
WE#
Input
data
control
Column I/O
Column decoder
1024-row × 32-column ×
16-block × 8-bit
(4,194,304 bits)
Row
decoder
OE#
CS#
CS
CS
VCC
VSS
CS
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
A8 A9 A18 A16 A17 A0 A2 A4 A15
(LSB) (MSB)
(LSB)
(MSB)
Internal
voltage
generator
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 5 of 12
Operation Table
CS# OE# WE# Mode VCC current I/O Ref. cycle
H × × Standby ISB, ISB1 High-Z
L H H Output disable ICC High-Z
L L H Read ICC D
OUT Read cycle (1) to (3)
L H L Write ICC D
IN Write cycle (1)
L L L Write ICC D
IN Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.5 to +7.0 V
Voltage on any pin relative to VSS V
T −0.5*1 to VCC + 0.5*2 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg −55 to +125 °C
Storage temperature under bias Tbias −10 to +85 °C
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC*3 4.5 5.0 5.5 V
V
SS*4 0 0 0 V
Input voltage VIH 2.2 V
CC + 0.5*2 V
V
IL −0.5*1 0.8 V
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage w i th a ll VCC pins must be on the same level.
4. The supply voltage w i th a ll VSS pins must be on the same level.
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 6 of 12
DC Char ac ter istics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, VSS = 0 V)
Parameter Symbol Min Max Unit Test conditions
Input leakage current IILII 2 µA VIN = VSS to VCC
Output leakage current IILOI 2 µA VIN = VSS to VCC
10nscycle ICC 140 mA Operation power supply
current 12nscycle ICC 130 mA
Min cycle
CS# = VIL, lOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current ISB 40 mA Min cycle, CS# = VIH,
Other inputs = VIH/VIL
I
SB1 5 mA f = 0 M H z
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
*1 1.0*1
Output voltage VOL 0.4 V IOL = 8 mA
V
OH 2.4 V IOH = −4 mA
Note: 1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Max Unit Test conditions
Input capacitance*1 C
IN 6 pF VIN = 0 V
Input/output capacitance*1 C
I/O 8 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 7 of 12
AC Char ac ter istics
(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and outpu t timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
D
OUT
255 Ω
480 Ω
5 V
5 pF
Output load (B)
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
OW
)
Output load (A)
1.5 V
30 pF
D
OUT
RL = 50 Ω
Zo = 50 Ω
Read Cycle
R1RP0408D
10ns version 12ns version
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 10 12 ns
Address access time tAA 10 12 ns
Chip select access time tACS 10 12 ns
Output enable to output valid tOE 5 6 ns
Output hold from address change tOH 3
3 ns
Chip select to output in low-Z tCLZ 3 3 ns 1
Output enable to output in low-Z tOLZ 0 0 ns 1
Chip deselect to output in high-Z tCHZ 5 6 ns 1
Output disable to output in high-Z tOHZ 5 6 ns 1
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 8 of 12
Write Cycle
R1RP0408D
10ns version 12ns version
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 10 12 ns
Address valid to end of write tAW 7 8 ns
Chip select to end of write tCW 7 8 ns 9
Write pulse width tWP 7 8 ns 8
Address setu p time tAS 0 0 ns 6
Write recovery time tWR 0 0 ns 7
Data to write time overlap tDW 5 6 ns
Data hold from write time tDH 0
0 ns
Write disable to output in low-Z tOW 3 3 ns 1
Output disable to output in high-Z tOHZ 5 6 ns 1
Write enable to output in high-Z tWHZ 5 6 ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS# or WE# going low.
7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. tWP is measured from the beginning of write to the
end of write.
9. tCW is measured from the later of CS# going low to the end of write.
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 9 of 12
Timing Waveforms
Read Timing Wavefo rm (1) (WE# = VIH)
tAA
tACS
tRC
tOE
tCLZ
Valid data
Address
CS#
DOUT
Valid address
High impedance
tOHZ
OE#
tOH
tCHZ
tOLZ
Read Timing Wavefo rm (2) (WE# = VIH, CS# = VIL, OE# = VIL)
t
AA
t
RC
Valid data
Address
D
OUT
Valid address
t
OH
t
OH
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 10 of 12
Read Timing Wavefo rm (3) (WE# = VIH, CS# = VIL, OE# = VIL)*2
Valid data
CS#
D
OUT
High
impedance
High
impedance
t
CLZ
t
ACS
t
RC
t
CHZ
Write Timing Waveform (1) (WE# Controlled)
Address
WE#*3
DOUT
DIN
tWC
tWP
tWR
tCW
tDW tDH
Valid address
tAW
Valid data
tAS
CS#*3
tOHZ
*4*4
OE#
High impedance*5
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 11 of 12
Write Timing Waveform (2) (CS# Controlled)
Address
WE# *3
DOUT
DIN
tWC
tWP
tWR
tCW
tDW tDH
Valid address
tAW
Valid data
tAS
CS# *3
tWHZ tOW
*4*4
High impedance*5
R1RP0408D Series
RJE03C0112-0200 Rev.2.00,
Dec.1.2008, page 12 of 12
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter Symbol Min Max Unit Test conditions
VCC for data retention VDR 2.0 V VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current ICCDR 500 µA VCC = 3 V, VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data
retention time tCDR 0 ns See retention waveform
Operation recovery time tR 5 ms
Low VCC Data Rete ntion Timing Waveform
CC
V
2.2 V
4.5 V
0 V
CS#
t
CDR
t
R
DR
V
Data retention mode
V
CC
≥ CS# ≥ V
CC
− 0.2 V
Revision History R1RP0408D Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.01 Sep. 30, 2003 Initial issue
1.00 Mar.12.2004 Deletion of Preliminary
2.00 Dec.01.2008
P1
P2
P7
P8/P9
Part Number 10ns Version Adding
Features Access time 10ns and operating current 140mA adding
Order Information Type No R1RP0408DGE-0PR Adding
DC Characteristics Operating power supply current 10ns parame ter addin g
AC Characteristics Read ,Write parameter 10ns parameter adding
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
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undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Colophon .7.2
