UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
Single Channel High-Speed, Low-Side Gate Driver
(with 4-A Peak Source and 4-A Peak Sink)
Check for Samples: UCC27517,UCC27516
1FEATURES APPLICATIONS
• Low-Cost, Gate-Driver Device Offering • Switch-Mode Power Supplies
Superior Replacement of NPN and PNP • DC-to-DC Converters
Discrete Solutions • Companion Gate Driver Devices for Digital
• 4-A Peak Source and 4-A Peak Sink Power Controllers
Symmetrical Drive • Solar Power, Motor Control, UPS
• Fast Propagation Delays (13-ns typical) • Gate Driver for Emerging Wide Band-Gap
• Fast Rise and Fall Times (9-ns and 7-ns Power Devices (such as GaN)
typical)
• 4.5-V to 18-V Single Supply Range DESCRIPTION
The UCC27516 and UCC27517 single-channel, high-
• Outputs Held Low During VDD UVLO (ensures speed, low-side gate driver devices are capable of
glitch free operation at power-up and power- effectively driving MOSFET and IGBT power
down) switches. Using a design that inherently minimizes
• TTL and CMOS Compatible Input Logic shoot-through current, UCC27516 and UCC27517
Threshold (independent of supply voltage) are capable of sourcing and sinking high, peak-
• Hysteretic Logic Thresholds for High Noise current pulses into capacitive loads offering rail-to-rail
drive capability and extremely small propagation
Immunity delay typically 13 ns.
• Dual Input Design (choice of an inverting (IN-
pin) or non-inverting (IN+ pin) driver The UCC27516 and UCC27517 provides 4-A source,
4-A sink (symmetrical drive) peak-drive current
configuration) capability at VDD = 12 V.
– Unused Input Pin can be Used for Enable
or Disable Function The UCC27516 and UCC27517 is designed to
operate over a wide VDD range of 4.5 V to 18 V and
• Output Held Low when Input Pins are Floating wide temperature range of -40°C to 140°C. Internal
• Input Pin Absolute Maximum Voltage Levels Under Voltage Lockout (UVLO) circuitry on VDD pin
Not Restricted by VDD Pin Bias Supply holds output low outside VDD operating range. The
Voltage capability to operate at low voltage levels such as
• Operating Temperature Range of -40°C to below 5 V, along with best in class switching
characteristics, is especially suited for driving
140°C emerging wide band-gap power switching devices
• 5-Pin DBV (SOT-23) and 6-Pin DRS (3 mm x 3 such as GaN power semiconductor devices.
mm WSON with exposed thermal pad)
Package Options
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
Q1
IN+
4.5 V to 18 V
Non-Inverting Input
1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
Inverting Input
V+
C1
R1
VIN-
Q1
R1
4.5 V to 18 V
V+
C1
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
Typical Application Diagrams
DESCRIPTION (CONT.)
UCC27516 and UCC27517 features a dual-input design which offers flexibility of implementing both inverting (IN-
pin) and non-inverting (IN+ pin) configuration with the same device. Either IN+ or IN- pin can be used to control
the state of the driver output. The unused input pin can be used for enable and disable function. For safety
purpose, internal pull-up and pull-down resistors on the input pins ensure that outputs are held low when input
pins are in floating condition. Hence the unused input pin cannot be left floating and needs to be properly biased
to ensure that driver output is in enabled for normal operation.
The input pin threshold of the UCC27516 and UCC27517 devices are based on TTL and CMOS-compatible low-
voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and
low thresholds offers excellent noise immunity.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)(2)
OPERATING
PEAK CURRENT INPUT THRESHOLD
PART NUMBER PACKAGE TEMPERATURE RANGE,
(SOURCE/SINK) LOGIC TA
CMOS/TTL-Compatible
4-A/4-A
UCC27516DRS WSON 6 pin (low voltage, independent -40°C to 140°C
(Symmetrical Drive) of VDD bias voltage)
CMOS/TTL-Compatible
4-A/4-A
UCC27517DBV SOT-23 5 pin (low voltage, independent -40°C to 140°C
(Symmetrical Drive) of VDD bias voltage)
(1) For the most current package and ordering information, see Package Option Addendum at the end of this document.
(2) All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be
compatible with either lead free or Sn/Pb soldering operations. DRS package is rated MSL level 2.
Table 1. UCC2751x Product Family Summary
PART NUMBER PACKAGE PEAK CURRENT INPUT THRESHOLD LOGIC
(SOURCE/SINK)
UCC27511DBV(1) SOT-23, 6 pin 4-A/8-A CMOS/TTL-Compatible
(Asymmetrical Drive) (low voltage, independent of VDD
UCC27512DRS (1) 3 mm x 3 mm WSON, 6 pin bias voltage)
UCC27516DRS 3 mm x 3 mm WSON, 6 pin 4-A/4-A
(Symmetrical Drive)
UCC27517DBV SOT-23, 5 pin
UCC27518DBV (1) SOT-23, 5 pin CMOS
(follows VDD bias voltage)
UCC27519DBV (1) SOT-23, 5 pin
(1) Visit www.ti.com for the latest product datasheet.
2Copyright © 2012, Texas Instruments Incorporated
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Supply voltage range VDD -0.3 20
DC -0.3 VDD + 0.3 V
OUT voltage Repetitive pulse less than 200 ns(4) -2 VDD + 0.3
Output continuous current IOUT_DC (source/sink) 0.3 A
Output pulsed current (0.5 µs) IOUT_pulsed(source/sink) 4
IN+, IN-(5) -0.3 20
Human Body Model, HBM 4000 V
ESD Charged Device Model, CDM 1000
Operating virtual junction temperature range, TJ-40 150
Storage temperature range, TSTG -65 150 °C
Soldering, 10 sec. 300
Lead temperature Reflow 260
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(4) Values are verified by characterization on bench.
(5) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.
THERMAL INFORMATION UCC27516 UCC27517
THERMAL METRIC(1) WSON SOT-23 DBV UNITS
6 PINS 5 PINS
θJA Junction-to-ambient thermal resistance(2) 85.6 217.6
θJCtop Junction-to-case (top) thermal resistance(3) 100.1 85.8
θJB Junction-to-board thermal resistance(4) 58.6 44.0 °C/W
ψJT Junction-to-top characterization parameter(5) 7.5 4.0
ψJB Junction-to-board characterization parameter(6) 58.7 43.2
θJCbot Junction-to-case (bottom) thermal resistance(7) 23.7 n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
NOTE
Under identical power dissipation conditions, the DRS package will allow to maintain a
lower die temperature than the DBV. θJA metric should be used for comparison of power
dissipation capability between different packages (Refer to the APPLICATION
INFORMATION Section).
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
Supply voltage range, VDD 4.5 12 18 V
Operating junction temperature range -40 140 °C
Input voltage, IN+ and IN- 0 18 V
ELECTRICAL CHARACTERISTICS
VDD = 12 V, TA= TJ= -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal.
PARAMETER TEST CONDITION MIN TYP MAX UNITS
BIAS Currents
IN+ = VDD, IN- = GND 40 100 160
IDD(off) Startup current VDD = 3.4 V IN+ = IN- = GND or IN+ = IN- = VDD 25 75 145 µA
IN+ = GND, IN- = VDD 20 60 115
Under Voltage Lockout (UVLO)
TA= 25°C 3.91 4.20 4.5
VON Supply start threshold TA= -40°C to 140°C 3.70 4.20 4.65 V
Minimum operating
VOFF 3.45 3.9 4.35
voltage after supply start
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
Inputs (IN+, IN-)
Input signal high Output high for IN+ pin,
VIN_H 2.2 2.4
threshold Output low for IN- pin
Output low for IN+ pin, V
VIN_L Input signal low threshold 1.0 1.2
Output high for IN- pin
VIN_HYS Input signal hysteresis 1.0
Source/Sink Current
Source/sink peak
ISRC/SNK CLOAD = 0.22 µF, FSW = 1 kHz -4/+4 A
current(1)
Outputs (OUT)
VDD = 12 V 50 90
IOUT = -10 mA
VDD-High output voltage
VOH VDD = 4.5 V 60 130
IOUT = -10 mA mV
VDD = 12 5 10
IOUT = 10 mA
VOL Low output voltage VDD = 4.5 V 6 12
IOUT = 10 mA
VDD = 12 V 5.0 7.5
IOUT = -10 mA
Output pull-up
ROH resistance(2) VDD = 4.5 V 5.0 11.0
IOUT = -10 mA Ω
VDD = 12 V 0.5 1.0
IOUT = 10 mA
Output pull-down
ROL resistance VDD = 4.5 V 0.6 1.2
IOUT = 10 mA
(1) Ensured by Design.
(2) ROH represents on-resistance of P-Channel MOSFET in pull-up structure of the UCC27516 and UCC27517's output stage.
4Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
tD1 tD1
Low
90%
10%
IN- pin
OUTPUT
High
INPUT
(IN+ pin)
Low
High
tf
tr
tD1 tD1
Low
90%
10%
IN- pin
OUTPUT
High
INPUT
(IN+ pin)
Low
High
tf
tr
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, TA= TJ= -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal.
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Switching Time
VDD = 12 V 8 12
CLOAD = 1.8 nF
tRRise time(3) VDD = 4.5 V 16 22
CLOAD = 1.8 nF
VDD = 12 V 7 11
CLOAD = 1.8 nF
tFFall time(3) VDD=4.5V 7 11
CLOAD = 1.8 nF ns
VDD = 12 V 4 13 23
5-V input pulse CLOAD = 1.8 nF
IN+ to output propagation
tD1 delay(3) VDD = 4.5 V 4 15 26
5-V input pulse CLOAD = 1.8 nF
VDD = 12 V 4 13 23
CLOAD = 1.8 nF
IN- to output propagation
tD2 delay(3) VDD = 4.5 V 4 19 30
CLOAD = 1.8 nF
(3) See timing diagrams in Figure 1,Figure 2,Figure 3 and Figure 4.
Figure 1. Non-Inverting Configuration
(PWM Input to IN+ pin (IN- pin tied to GND))
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Product Folder Link(s): UCC27517 UCC27516
tD2 tD2
90%
10%
OUTPUT
Low
ENABLE
(IN- pin)
High
Low
High
INPUT
(IN+ pin)
tr
tf
tD2 tD2
90%
10%
OUTPUT
Low
ENABLE
(IN- pin)
High
Low
High
INPUT
(IN+ pin)
tr
tf
Low
90%
10%
ENABLE
(IN+ pin)
OUTPUT
tD1
High
tD1
Low
High
INPUT
(IN- pin)
trtf
Low
90%
10%
ENABLE
(IN+ pin)
OUTPUT
tD1
High
tD1
Low
High
INPUT
(IN- pin)
trtf
tD2 tD2
90%
10%
OUTPUT
Low
High
IN+ pin
Low
High
INPUT
(IN- pin)
tftr
tD2 tD2
90%
10%
OUTPUT
Low
High
IN+ pin
Low
High
INPUT
(IN- pin)
tftr
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
Figure 2. Inverting Configuration
(PWM input to IN- pin (IN+ pin tied to VDD))
Figure 3. Enable and Disable Function Using IN+ Pin
(Enable and disable signal applied to IN+ pin, PWM input to IN- pin)
Figure 4. Enable and Disable Function Using IN- Pin
(Enable and disable signal applied to IN- pin, PWM input to IN+ pin)
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Product Folder Link(s): UCC27517 UCC27516
1
2
3
6
5
4
IN-
GND
GND
IN+
OUT
VDD
IN-
VDD OUT
GND
IN+
1
2
3
5
4IN-
VDD OUT
GND
IN+
1
2
3
5
4
3
4
2
1
5
200 kW
VDD 230 kW
UVLO
VDD
VDD
VDD
OUT
IN+
IN-
GND
6
1
2
4
5
200 kW
VDD 230 kW
UVLO
VDD
VDD
VDD
OUT
IN+
IN-
GND
3 GND
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
DEVICE INFORMATION
UCC27516 Functional Block Diagram
UCC27517 Functional Block Diagram
UCC27517 DBV
(Top View)
UCC27516 DRS
(Top View)
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Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
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TERMINAL FUNCTIONS (UCC27516)
TERMINAL I/O FUNCTION
PIN NUMBER NAME
Inverting Input:When the driver is used in non-inverting configuration connect IN- to
1 IN- I GND in order to enable output, OUT held LOW if IN- is unbiased or floating.
Ground:All signals referenced to this pin. It is recommended to connect pin 2 and pin
2, 3 GND - 3 on PCB as close to the device as possible.
4 VDD I Bias supply input.
5 OUT I Sourcing/Sinking Current Output of Driver
Non-Inverting Input:When the driver is used in inverting configuration connect IN+
6 IN+ O to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating.
TERMINAL FUNCTIONS (UCC27517)
TERMINAL I/O FUNCTION
PIN NUMBER NAME
1 VDD I Bias supply input.
Ground. All signals referenced to this pin. For the UCC27516, it is recommended to
2 GND - connect pin 2 and pin 3 on PCB as close to the device as possible.
Non-inverting input. When the driver is used in inverting configuration connect IN+
3 IN+ I to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating
Inverting input. When the driver is used in non-inverting configuration connect IN- to
4 IN- I GND in order to enable output, OUT held LOW if IN- is unbiased or floating
5 OUT O Sourcing/Sinking current output of driver.
Table 2. Device Logic Table
IN+ PIN IN- PIN OUT PIN
LLL
L H L
H L H
H H L
x(1) Any L
Any x(1) L
(1) x = Floating Condition
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SLUSAY4B – MARCH 2012–REVISED JUNE 2012
TYPICAL CHARACTERISTICS
START-UP CURRENT OPERATING SUPPLY CURRENT
vs vs
TEMPERATURE TEMPERATURE (Output Switching)
Figure 5. Figure 6.
SUPPLY CURRENT UVLO THRESHOLD VOLTAGE
vs vs
TEMPERATURE (Output in DC On/Off condition) TEMPERATURE
Figure 7. Figure 8.
INPUT THRESHOLD OUTPUT PULL-UP RESISTANCE
vs vs
TEMPERATURE TEMPERATURE
Figure 9. Figure 10.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT PULL-DOWN RESISTANCE RISE TIME
vs vs
TEMPERATURE TEMPERATURE
Figure 11. Figure 12.
FALL TIME INPUT TO OUTPUT PROPAGATION DELAY
vs vs
TEMPERATURE TEMPERATURE
Figure 13. Figure 14.
OPERATING SUPPLY CURRENT PROPAGATION DELAYS
vs vs
FREQUENCY SUPPLY VOLTAGE
Figure 15. Figure 16.
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Product Folder Link(s): UCC27517 UCC27516
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UCC27516
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SLUSAY4B – MARCH 2012–REVISED JUNE 2012
TYPICAL CHARACTERISTICS (continued)
RISE TIME FALL TIME
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 17. Figure 18.
APPLICATION INFORMATION
Introduction
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers and the gates of the power semiconductor devices. Further,
gate drivers are indispensable when sometimes it is just not feasible to have the PWM controller directly drive
the gates of the switching devices. With advent of digital power, this situation will be often encountered since the
PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively turning on a
power switch. A level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V)
in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based
on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove
inadequate with digital power since they lack level-shifting capability. Gate drivers effectively combine both the
level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-
frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-
drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in
controllers by moving gate charge power losses into itself. Finally, emerging wide band-gap power device
technologies such as GaN based switches, which are capable of supporting very high switching frequency
operation, are driving very special requirements in terms of gate drive capability. These requirements include
operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance
packages with good thermal capability. In summary gate-driver devices are extremely important components in
switching power combining benefits of high-performance, low cost, component count and board space reduction
and simplified system design.
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UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
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UCC2751x Product Family
The UCC2751x family of gate driver products (Table 3) represent Texas Instruments’ latest generation of single-
channel, low-side high-speed gate driver devices featuring high-source/sink current capability, industry best-in-
class switching characteristics and a host of other features (Table 4) all of which combine to ensure efficient,
robust and reliable operation in high-frequency switching power circuits.
Table 3. UCC2751x Product Family Summary
PEAK CURRENT
PART NUMBER PACKAGE INPUT THRESHOLD LOGIC
(SOURCE/SINK)
UCC27511DBV(1) SOT-23, 6 pin 4-A/8-A
(Asymmetrical Drive) CMOS/TTL-Compatible
UCC27512DRS (1) 3 mm x 3 mm WSON, 6 pin (low voltage, independent of VDD
UCC27516DRS 3 mm x 3 mm WSON, 6 pin bias voltage)
UCC27517DBV SOT-23, 5 pin 4-A/4-A
(Symmetrical Drive)
UCC27518DBV (1) SOT-23, 5 pin CMOS
(follows VDD bias voltage)
UCC27519DBV (1) SOT-23, 5 pin
(1) Visit www.ti.com for the latest product datasheet.
Table 4. UCC2751x Family of Features and Benefits
FEATURE BENEFIT
High Source/Sink Current Capability High current capability offers flexibility in employing UCC2751x
4 A/8 A (Asymmetrical) – UCC27511/2 family of devices to drive a variety of power switching devices at
4 A/4 A (Symmetrical) – UCC27516/7 varying speeds
Best-in-class 13-ns (typ) Propagation delay Extremely low pulse transmission distortion
Expanded VDD Operating range of 4.5 V to 18 V Flexibility in system design
Low VDD operation ensures compatibility with emerging wide band-
Expanded Operating Temperature range of -40°C to 140°C gap power devices such as GaN
(See Electrical Characteristics table)
VDD UVLO Protection Outputs are held low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down
Outputs held low when input pins (INx) in floating condition Safety feature, especially useful in passing abnormal condition tests
during safety certification
Ability of input pins (and enable pin in UCC27518/9) to handle System simplification, especially related to auxiliary bias supply
voltage levels not restricted by VDD pin bias voltage architecture
Split output structure in UCC27511 (OUTH, OUTL) Allows independent optimization of turn-on and turn-off speeds
Strong sink current (8 A) and low pull-down impedance (0.375 Ω) in High immunity to C x dV/dt Miller turn-on events
UCC27511/2
CMOS/TTL compatible input threshold logic with wide hysteresis in Enhanced noise immunity, while retaining compatibility with
UCC27511/2/6/7 microcontroller logic level input signals (3.3 V, 5 V) optimized for
digital power
CMOS input threshold logic in UCC27518/9 (VIN_H – 70% VDD, Well suited for slow input voltage signals, with flexibility to program
VIN_L – 30% VDD) delay circuits (RCD)
12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
1
2
3
5
4
IN-
GND
GND
OUT
VDD
UCC27516
V+
Q1
R1
4.5 V to 18 V
IN-
C1
1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
VIN-
Q1
R1
4.5 V to 18 V
V+
C1
IN+ 4
1
2
3
5
4
VDD
GND
IN+
OUT
IN-
UCC27517
Q1
IN+
4.5 V to 18 V
V+
C1
R1
1
2
3
5
4
IN-
GND
GND
IN+
VDD
UCC27516
Q1
R1
4
OUT
VIN+
VIN+
4.5 V to 18 V
C1
UCC27517
UCC27516
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SLUSAY4B – MARCH 2012–REVISED JUNE 2012
Typical Application Diagram
Typical application diagrams of the UCC27516 and UCC27517 devices are shown below illustrating use in non-
inverting and inverting driver configurations.
Figure 19. Using Non-Inverting Input
(IN- is grounded to the enable output)
Figure 20. Using Inverting Input
(IN+ is tied to VDD enable output)
NOTE
The UCC27516 features two ground pins, pin 2 and pin 3. It is recommended to tie both
pins together using PCB trace as close as possible to the device.
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Product Folder Link(s): UCC27517 UCC27516
VDD ThresholdVDD
IN+
OUT
IN -
VDD ThresholdVDD
IN+
OUT
IN -
VDD Threshold
IN-
OUT
IN+
VDD Threshold
IN-
OUT
IN+
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
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VDD and Undervoltage Lockout
The UCC2751x devices have internal Under Voltage LockOut (UVLO) protection feature on the VDD pin supply
circuit blocks. Whenever the driver is in UVLO condition (i.e. when VDD voltage less than VON during power up
and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of the
status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps prevent
chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the
VDD bias voltage when the system commences switching and there is a sudden increase in IDD. The capability to
operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially
suited for driving emerging GaN wide bandgap power semiconductor devices.
For example, at power up, the UCC2751x driver output remains LOW until the VDD voltage reaches the UVLO
threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the non-inverting
operation (PWM signal applied to IN+ pin) shown below, the output remains LOW until the UVLO threshold is
reached, and then the output is in-phase with the input. In the inverting operation (PWM signal applied to IN- pin)
shown below the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with
the input. In both cases, the unused input pin must be properly biased to enable the output. It is worth noting that
in these devices the output turns to high state only if IN+ pin is high and IN- pin is low after the UVLO threshold
is reached.
Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR
should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by
the load. The parallel combination of capacitors should present a low impedance characteristic for the expected
current levels and switching frequencies in the application.
Figure 21. Power-Up (non-inverting drive) Figure 22. Power-Up (inverting drive)
Operating Supply Current
The UCC27516 and UCC27517 features very low quiescent IDD currents. The typical operating supply current in
Under Voltage LockOut (UVLO) state and fully-on state (under static and switching conditions) are summarized
in Figure 5,Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state
(DC high or DC low, refer Figure 7) represents lowest quiescent IDD current when all the internal logic circuits of
the device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT
current due to switching and finally any current related to pull-up resistors on the unused input pin. For example
when the inverting input pin is pulled low additional current is drawn from VDD supply through the pull-up
resistors (refer to DEVICE INFORMATION for the device Block Diagram). Knowing the operating frequency (fSW)
and the MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated
as product of QGand fSW.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias
voltages under 1.8-nF switching load is provided in Figure 15. The strikingly linear variation and close correlation
with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device attesting to
its high-speed characteristics.
14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
Input Stage
The input pins of the UCC27516 and UCC27517 devices are based on a TTL/CMOS compatible input threshold
logic that is independent of the VDD supply voltage. With typ high threshold = 2.2 V and typ low threshold = 1.2
V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V and 5-V
digital power controllers. Wider hysteresis (typ 1 V) offers enhanced noise immunity compared to traditional TTL
logic implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control
of the input pin threshold voltage levels which eases system design considerations and ensures stable operation
across temperature. The very low input capacitance on these pins reduces loading and increases switching
speed.
The device features an important safety function wherein, whenever any of the input pins are in a floating
condition, the output of the respective channel is held in the low state. This is achieved using VDD pull-up
resistors on all the inverting inputs (IN- pin) or GND pull-down resistors on all the non-inverting input pins (IN+
pin), (refer to DEVICE INFORMATION for the device Block Diagram).
The device also features a dual input configuration with two input pins available to control the state of the output.
The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin
(IN-). The state of the output pin is dependent on the bias on both the IN+ and IN- pins. Refer to the input/output
logic truth table (Table 2) and the Typical Application Diagrams, (Figure 19 and Figure 20), for additional
clarification.
Once an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly
biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating
condition because whenever any input pin is left in a floating condition the output is disabled for safety purposes.
Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as explained
below.
• In order to drive the device in a non-inverting configuration, apply the PWM control input signal to IN+ pin. In
this case, the unused input pin, IN-, must be biased low (eg. tied to GND) in order to enable the output.
– Alternately, the IN- pin can be used to implement the enable/disable function using an external logic
signal. OUT is disabled when IN- is biased high and OUT is enabled when IN- is biased low.
• In order to drive the device in an inverting configuration, apply the PWM control input signal to IN- pin. In this
case, the unused input pin, IN+, must be biased high (eg. tied to VDD) in order to enable the output.
– Alternately, the IN+ pin can be used to implement the enable/disable function using an external logic
signal. OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
• Finally, it is worth noting that the output pin can be driven into a high state ONLY when IN+ pin is biased high
and IN- input is biased low.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a mechanical socket or PCB layout is not optimal:
• High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since
the device features just one GND pin which may be referenced to the power ground, this may modify the
differential voltage between input pins and GND and trigger an unintended change of output state. Because
of fast 13-ns propagation delay, this can ultimately result in high-frequency oscillations, which increases
power dissipation and poses risk of damage.
• 1-V input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
• In the worst case, when a slow input signal is used and PCB layout is not optimal, it may be necessary to add
a small capacitor (1 nF) between input pin and ground very close to the driver device. This helps to convert
the differential mode noise with respect to the input logic circuitry into common mode noise and avoid
unintended change of output state.
If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly
recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCC27517 UCC27516
VCC
ROH
ROL
Gate
Voltage
Boost
Narrow Pulse at
each Turn On
Anti Shoot-
Through
Circuitry
Input Signal
RNMOS, Pull Up
OUT
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
Enable Function
As mentioned earlier, an enable/disable function can be easily implemented in the UCC27516 and UCC27517
using the unused input pin. When IN+ is pulled down to GND or IN- is pulled down to VDD, the output is
disabled. Thus IN+ pin can be used like an enable pin that is based on active high logic, while IN- can be used
like an enable pin that is based on active low logic.
Output Stage
The UCC27516 and UCC27517 are capable of delivering 4-A source, 4-A sink (symmetrical drive) at VDD = 12
V. The output stage of the UCC27516 and UCC27517 devices are illustrated in Figure 23. The UCC27516 and
UCC27517 devices features a unique architecture on the output stage which delivers the highest peak source
current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the
power switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pull-up
structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-
Channel MOSFET during a narrow instant when the output changes state from low to high, the gate-driver device
is able to deliver a brief boost in the peak-sourcing current enabling fast turn on.
Figure 23. UCC2751x Gate Driver Output Structure
The ROH parameter (see ELECTRICAL CHARACTERISTICS) is a DC measurement and it is representative of
the on-resistance of the P-Channel device only, since the N-Channel device is turned on only during output
change of state from low to high. Thus the effective resistance of the hybrid pull-up stage is much lower than
what is represented by ROH parameter. The pull-down structure is composed of a N-Channel MOSFET only. The
ROL parameter (see ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of
true impedance of the pull-down stage in the device. In the UCC27516 and UCC27517, the effective resistance
of the hybrid pull-up structure is approximately 1.4 x ROL.
The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS
output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode
clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current
without either damage to the device or logic malfunction.
16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
OFF ON
SW G DD SW
OFF GATE ON GATE
R R
P = Q V f ( + )
(R +R ) (R +R )
´ ´ ´
2
G LOAD DD SW g DD SW
P C V f Q V f= =
2
G LOAD DD SW
P C V f=
2
G LOAD DD
1
E C V
2
=
DISS DC SW
P P P= +
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
Power Dissipation
Power dissipation of the gate driver has two portions as shown in equation below:
(1)
The DC portion of the power dissipation is PDC = IQx VDD where IQis the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections etc and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through
etc). The UCC27516 and UCC27517 features very low quiescent currents (less than 1 mA, refer Figure 7) and
contains internal logic to eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the
total power dissipation within the gate driver can be safely assumed to be negligible.
The power dissipated in the gate-driver package during switching (PSW) depends on the following factors:
• Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOH drop-out).
• Switching frequency.
• Use of external gate resistors.
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
(2)
Where CLOAD is load capacitor and VDD is bias voltage feeding the driver.
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by the following:
(3)
where ƒSW is the switching frequency.
The switching load presented by a power MOSFET/IGBT can be converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between
the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC,
to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that
must be dissipated when charging a capacitor. This is done by using the equation, QG= CLOAD x VDD, to provide
the following equation for power:
(4)
This power PGis dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or
off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is
dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed
between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the
use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and
external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher
resistance component). Based on this simplified analysis, the driver power dissipation during switching is
calculated as follows:
(5)
where ROFF = ROL and RON (effective resistance of pull-up structure) = 1.4 x ROL.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
Low Propagation Delays
The UCC27516 and UCC27517 driver devices feature best-in-class input-to-output propagation delay of 13 ns
(typ) at VDD = 12 V. This promises the lowest level of pulse transmission distortion available from industry
standard gate driver devices for high-frequency switching applications. As seen in Figure 14, there is very little
variation of the propagation delay with temperature and supply voltage as well, offering typically less than 20-ns
propagation delays across the entire range of application conditions.
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is summarized in the Thermal Information section of the
datasheet. For detailed information regarding the thermal information table, please refer to the Application Note
from Texas Instruments entitled IC Package Thermal Metrics (Texas Instruments Literature Number SPRA953A).
The UCC27516 and UCC27517 devices are offered in SOT-23, 5-pin package (DBV) and 3 mm x 3 mm, WSON
6-pin package with exposed thermal pad (DRS), respectively. The thermal information table summarizes the
thermal performance metrics related to the two packages. θJA metric should be used for comparison of power
dissipation between different packages. Under identical power dissipation conditions, the DRS package will
maintain a lower die temperature than the DBV. The ψJT and ψJB metrics should be used when estimating the die
temperature during actual application measurements.
The DRS is a better thermal package overall because it has the exposed thermal pad and is able to sink heat to
the PCB better than the DBV. The thermal pad in DRS package provides designers with an ability to create an
excellent heat removal sub-system from the vicinity of the device, thus helping to maintain a lower junction
temperature. This pad should be soldered to the copper on the printed circuit board directly underneath the
device package. Then a printed circuit board designed with thermal lands and thermal vias completes a very
efficient heat removal subsystem. In such a design, the heat is extracted from the semiconductor junction
through the thermal pad, which is then efficiently conducted away from the location of the device on the PCB
through the thermal network. This helps to maintain a lower board temperature near the vicinity of the device
leading to an overall lower device junction temperature.
In comparison, for the DBV package, heat removal has to occur primarily through the leads of the device and the
PCB traces connected to the leads.
Note that the exposed pad in DRS package is not directly connected to any leads of the package. However, it is
electrically and thermally connected to the substrate of the device which is the ground of the device. It is
recommended to externally connect the exposed pads to GND in PCB layout for better EMI immunity.
18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
www.ti.com
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
PCB Layout
Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27516 and UCC27517 gate driver incorporates short-propagation
delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at
the gate of power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current
capability is even higher (4-A/4-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing
if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly
recommended when designing with these high-speed drivers.
• Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the output pins and the gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD
during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and
chip capacitors is highly recommended.
• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at two instances – during turn-on and turn-off transients, which will induce
significant voltage transients on the output pin of the driver device and gate of the power switch.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM
controller etc at one, single point. The connected paths should be as short as possible to reduce inductance
and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
• In noisy environments, it may be necessary to tie the unused input pin of UCC27516 and UCC27517 to VDD
(in case of IN+) or GND (in case of IN-) using short traces in order to ensure that the output is enabled and to
prevent noise from causing malfunction in the output.
• The UCC27516 device offers two ground pins, pin 2 and pin 3. It is extremely important to short the two pins
together using the PCB trace. The shortest trace should be located as close as possible to the device.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): UCC27517 UCC27516
UCC27517
UCC27516
SLUSAY4B – MARCH 2012–REVISED JUNE 2012
www.ti.com
REVISION HISTORY
Changes from Original ( March 2012) to Revision A Page
• Changed marketing status from Advanced Information to Final, (RTM date, March 2012). ................................................ 1
Changes from Revision A (March 2012) to Revision B Page
• Added UCC27516 device. .................................................................................................................................................... 1
• Added UCC27516 ordering information. ............................................................................................................................... 2
• Added DC and repetitive pulse rates to OUT voltage. ......................................................................................................... 3
• Changed Human Body Model max value from 2000 V to 400V. .......................................................................................... 3
• Changed Charged Device Model max value from 500 V to 100 V. ...................................................................................... 3
• Added note 5. ....................................................................................................................................................................... 3
• Added UCC27516 block diagram. ........................................................................................................................................ 7
• Added GND, ground definition. ............................................................................................................................................. 8
• Deleted note one from selection. ........................................................................................................................................ 12
• Added UCC27516 application diagrams. ............................................................................................................................ 13
• Added Thermal Information description. ............................................................................................................................. 18
• Added PCB layout bullet. .................................................................................................................................................... 19
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): UCC27517 UCC27516
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27516DRSR ACTIVE SON DRS 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27516DRST ACTIVE SON DRS 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC27517DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27517DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27516DRSR SON DRS 6 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
UCC27517DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
UCC27517DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27516DRSR SON DRS 6 3000 367.0 367.0 35.0
UCC27517DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
UCC27517DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jul-2012
Pack Materials-Page 2
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