Wide Supply Range, Rail-to-Rail
Output Instrumentation Amplifier
AD8227
Rev. 0
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
TOP VIEW
(Not to Scale)
07759-001
FEATURES
Gain set with 1 external resistor
Gain range: 5 to 1000
Input voltage goes below ground
Inputs protected beyond supplies
Very wide power supply range
Single supply: 2.2 V to 36 V
Dual supply: ±1.5 V to ±18 V
Bandwidth (G = 5): 250 kHz
CMRR (G = 5): 100 dB minimum (B Grade)
Input noise: 24 nV/√Hz
Typical supply current: 350 μA
Specified temperature: −40°C to +125°C
8-lead SOIC and MSOP packages
APPLICATIONS
Industrial process controls
Bridge amplifiers
Medical instrumentation
Portable data acquisition
Multichannel systems
PIN CONFIGURATION
–IN
1
R
G2
R
G3
+IN
4
+V
S
8
V
OUT
7
REF
6
–V
S
5
AD8227
Figure 1.
Table 1. Instrumentation Amplifiers by Category1
General
Purpose
Zero
Drift
Military
Grade
Low
Power
High Speed
PGA
AD8220 AD8231 AD620 AD627 AD8250
AD8221 AD8290 AD621 AD623 AD8251
AD8222 AD8293 AD524 AD8223 AD8253
AD8224 AD8553 AD526 AD8226
AD8228 AD8556 AD624 AD8227
AD8295 AD8557
1 See www.analog.com for the latest selection of instrumentation amplifiers.
GENERAL DESCRIPTION
The AD8227 is a low cost, wide supply range instrumentation
amplifier that requires only one external resistor to set any gain
between 5 and 1000.
The AD8227 is designed to work with a variety of signal voltages.
A wide input range and rail-to-rail output allow the signal to
make full use of the supply rails. Because the input range can
also go below the negative supply, small signals near ground can
be amplified without requiring dual supplies. The AD8227
operates on supplies ranging from ±1.5 V to ±18 V (2.2 V to
36 V single supply).
The robust AD8227 inputs are designed to connect to real-
world sensors. In addition to its wide operating range, the
AD8227 can handle voltages beyond the rails. For example,
with a ±5 V supply, the part is guaranteed to withstand ±35 V
at the input with no damage. Minimum as well as maximum
input bias currents are specified to facilitate open wire detection.
The AD8227 is ideal for multichannel, space-constrained
applications. With its MSOP package and 125°C temperature
rating, the AD8227 thrives in tightly packed, zero airflow designs.
The AD8227 is available in 8-pin MSOP and SOIC packages.
It is fully specified for −40°C to +125°C operation.
For a similar instrumentation amplifier with a gain range of 1 to
1000, see the AD8226.
AD8227
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 19
Architecture ................................................................................. 19
Gain Selection ............................................................................. 19
Reference Terminal .................................................................... 20
Input Voltage Range ................................................................... 20
Layout .......................................................................................... 20
Input Bias Current Return Path ............................................... 21
Input Protection ......................................................................... 21
Radio Frequency Interference (RFI) ........................................ 21
Applications Information .............................................................. 22
Differential Drive ....................................................................... 22
Precision Strain Gage ................................................................. 22
Driving an ADC ......................................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
5/09—Revision 0: Initial Version
AD8227
Rev. 0 | Page 3 of 24
SPECIFICATIONS
+VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 2.
Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO VCM = −10 V to +10 V
DC to 60 Hz
G = 5 90 100 dB
G = 10 96 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
5 kHz
G = 5 80 80 dB
G = 10 86 86 dB
G = 100 86 86 dB
G = 1000 86 86 dB
NOISE Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI 24 25 24 25 nV/√Hz
Output Voltage Noise, eNO 310 315 310 315 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 5 1.5 1.5 μV p-p
G = 10 0.9 0.9 μV p-p
G = 100 to 1000 0.5 0.5 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI V
S = ±5 V to ±15 V 200 100 μV
Average Temperature Drift TA = −40°C to +125°C 0.2 2 0.2 1 μV/°C
Output Offset, VOSO V
S = ±5 V to ±15 V 1000 500 μV
Average Temperature Drift TA = −40°C to +125°C 2 10 2 5 μV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G = 5 90 100 dB
G = 10 96 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1
TA = +25°C 5 20 27 5 20 27 nA
T
A = +125°C 5 15 25 5 15 25 nA
T
A = −40°C 5 30 35 5 30 35 nA
Average Temperature Drift TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 1.5 nA
T
A = +125°C 1.5 1.5 nA
T
A = −40°C 2 2 nA
Average Temperature Drift TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 60 60 kΩ
IIN 12 12 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
AD8227
Rev. 0 | Page 4 of 24
Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5 250 250 kHz
G = 10 200 200 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz
Settling Time 0.01% 10 V step
G = 5 14 14 μs
G = 10 15 15 μs
G = 100 35 35 μs
G = 1000 275 275 μs
Slew Rate2
G = 5 to 100 0.8 0.8 V/μs
GAIN3
G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error VOUT = −10 V to +10 V
G = 5 0.04 0.02 %
G = 10 to 1000 0.3 0.15 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 5 RL ≥ 2 kΩ 10 10 ppm
G = 10 RL ≥ 2 kΩ 15 15 ppm
G = 100 RL ≥ 2 kΩ 15 50 ppm
G = 1000 RL ≥ 2 kΩ 750 150 ppm
Gain vs. Temperature TA = −40°C to +125°C
G = 5 5 5 ppm/°C
G > 5 −100 −100 ppm/°C
INPUT VS = ±1.5 V to +36 V
Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Operating Voltage Range4TA = +25°C −VS − 0.1 +VS − 0.8 −VS − 0.1 +VS − 0.8 V
T
A = +125°C −VS − 0.05 +VS − 0.6 −VS − 0.05 +VS − 0.6 V
T
A = −40°C −VS − 0.15 +VS − 0.9 −VS − 0.15 +VS − 0.9 V
Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing
RL = 10 kΩ to ground TA = −40°C to +85°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V
T
A = +85°C to +125°C −VS + 0.2 +VS − 0.3 −VS + 0.2 +VS − 0.3 V
RL = 100 kΩ to ground TA = −40°C to +125°C −VS + 0.1 +VS − 0.1 −VS + 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Dual-supply operation ±1.5 ±18 ±1.5 ±18 V
Quiescent Current TA = +25°C 350 425 350 425 μA
T
A = −40°C 250 325 250 325 μA
T
A = +85°C 450 525 450 525 μA
T
A = +125°C 525 600 525 600 μA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 The input stage uses pnp transistors, so input bias current always flows into the part.
2 At high gains, the part is bandwidth limited rather than slew rate limited.
3 For G > 5, gain error specifications do not include the effects of External Resistor RG.
4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the
section for more information. Input Voltage Range
AD8227
Rev. 0 | Page 5 of 24
+VS = 2.7 V, −VS = 0 V, VREF = 0 V, TA = 25°C, G = 5, RL = 10 k, specifications referred to input, unless otherwise noted.
Table 3.
Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION RATIO VCM = 0 V to 1.7 V
DC to 60 Hz
G = 5 90 100 dB
G = 10 96 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
5 kHz
G = 5 80 80 dB
G = 10 86 86 dB
G = 100 86 86 dB
G = 1000 86 86 dB
NOISE Total noise:
eN = √(eNI2 + (eNO/G)2)
Voltage Noise, 1 kHz
Input Voltage Noise, eNI 25 28 25 28 nV/√Hz
Output Voltage Noise, eNO 310 330 310 330 nV/√Hz
RTI f = 0.1 Hz to 10 Hz
G = 5 1.5 1.5 μV p-p
G = 10 0.8 0.8 μV p-p
G = 100 to 1000 0.5 0.5 μV p-p
Current Noise f = 1 kHz 100 100 fA/√Hz
f = 0.1 Hz to 10 Hz 3 3 pA p-p
VOLTAGE OFFSET Total offset voltage:
VOS = VOSI + (VOSO/G)
Input Offset, VOSI V
S = 0 V to 1.7 V 200 100 μV
Average Temperature Drift TA = −40°C to +125°C 0.2 2 0.2 1 μV/°C
Output Offset, VOSO V
S = 0 V to 1.7 V 1000 500 μV
Average Temperature Drift TA = −40°C to +125°C 2 10 2 5 μV/°C
Offset RTI vs. Supply (PSR) VS = 0 V to 1.7 V
G = 5 90 100 dB
G = 10 96 105 dB
G = 100 105 110 dB
G = 1000 105 110 dB
INPUT CURRENT
Input Bias Current1
TA = +25°C 5 20 27 5 20 27 nA
T
A = +125°C 5 15 25 5 15 25 nA
T
A = −40°C 5 30 35 5 30 35 nA
Average Temperature Drift TA = −40°C to +125°C 70 70 pA/°C
Input Offset Current TA = +25°C 1.5 1.5 nA
T
A = +125°C 1.5 1.5 nA
T
A = −40°C 2 2 nA
Average Temperature Drift TA = −40°C to +125°C 5 5 pA/°C
REFERENCE INPUT
RIN 60 60 kΩ
IIN 12 12 μA
Voltage Range −VS +VS −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.01 %
AD8227
Rev. 0 | Page 6 of 24
Test Conditions/ A Grade B Grade
Parameter Comments Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 5 250 250 kHz
G = 10 200 200 kHz
G = 100 50 50 kHz
G = 1000 5 5 kHz
Settling Time 0.01% 2 V step
G = 5 6 6 μs
G = 10 6 6 μs
G = 100 30 30 μs
G = 1000 275 275 μs
Slew Rate2
G = 5 to 10 0.6 0.6 V/μs
GAIN3
G = 5 + (80 kΩ/RG)
Gain Range 5 1000 5 1000 V/V
Gain Error
G = 5 VOUT = 0.8 V to 1.8 V 0.04 0.04 %
G = 10 to 1000 VOUT = 0.2 V to 2.5 V 0.3 0.3 %
Gain vs. Temperature TA = −40°C to +125°C
G = 5 5 5 ppm/°C
G > 5 −100 −100 ppm/°C
INPUT −VS = 0 V; +VS = 2.7 V to
36 V
Impedance
Differential 0.8||2 0.8||2 GΩ||pF
Common Mode 0.4||2 0.4||2 GΩ||pF
Operating Voltage Range4TA = +25°C −0.1 +VS − 0.7 −0.1 +VS − 0.7 V
T
A = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V
T
A = +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V
Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V
OUTPUT
Output Swing TA = −40°C to +125°C
RL = 2 kΩ to 1.35 V 0.2 +VS − 0.2 0.2 +VS − 0.2 V
RL = 10 kΩ to 1.35 V 0.1 +VS − 0.1 0.1 +VS − 0.1 V
Short-Circuit Current 13 13 mA
POWER SUPPLY
Operating Range Single-supply operation 2.2 36 2.2 36 V
Quiescent Current +VS = 2.7 V
T
A = +25°C 325 400 325 400 μA
T
A = −40°C 250 325 250 325 μA
T
A = +85°C 425 500 425 500 μA
T
A = +125°C 475 550 475 550 μA
TEMPERATURE RANGE −40 +125 −40 +125 °C
1 Input stage uses pnp transistors, so input bias current always flows into the part.
2 At high gains, the part is bandwidth limited rather than slew rate limited.
3 For G > 5, gain error specifications do not include the effects of External Resistor RG.
4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the
section for more information. Input Voltage Range
AD8227
Rev. 0 | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Output Short-Circuit Current Indefinite
Maximum Voltage at −IN or +IN −VS + 40 V
Minimum Voltage at −IN or +IN +VS − 40 V
REF Voltage ±VS
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature 140°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for a device in free air.
Table 5.
Package θJA Unit
8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W
8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W
ESD CAUTION
AD8227
Rev. 0 | Page 8 of 24
TOP VIEW
(Not to Scale)
07759-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
1
R
G2
R
G3
+V
S
8
V
OUT
7
REF
6
+IN
4
–V
S
5
AD8227
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN Negative Input.
2, 3 RG Gain Setting Pins. Place a gain resistor between these two pins.
4 +IN Positive Input.
5 −VS Negative Supply.
6 REF Reference. This pin must be driven by low impedance.
7 VOUT Output.
8 +VS Positive Supply.
AD8227
Rev. 0 | Page 9 of 24
0
–900 –600 –300 0 300 600 900
OUTPUT V
OS
(µV)
07759-003
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted.
500
400
300
200
100
HITS
MEAN: 15.9
SD: 196.50
Figure 3. Typical Distribution of Output Offset Voltage
700
600
500
400
300
200
100
HITS
1000
800
600
400
200
0
–0.9 –0.6 –0.3 0 0.3 0.6 0.9
INPUT V
OS
DRIFT (µV)
HITS
07759-006
MEAN: 0.0668
SD: 0.065827
Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100
0
–6 –4 –2 0 2 4 6
OUTPUT VOS DRIFT (µV)
07759-004
MEAN: –0.701
SD: 0.676912
Figure 4. Typical Distribution of Output Offset Voltage Drift
1000
800
600
400
200
HITS
1000
800
600
400
200
0
16 18 20 22 24 26
POSITIVE I
BIAS
(nA)
HITS
07759-007
MEAN: 20.4
SD: 0.5893
Figure 7. Typical Distribution of Input Bias Current
0
–200 –150 –100 –50 0 50 100 150 200
INPUT V
OS
(µV)
07759-005
MEAN: –5.90
SD: 15.8825
Figure 5. Typical Distribution of Input Offset Voltage
1000
800
600
400
200
0
–0.9 –0.6 –0.3 0 0.3 0.6 0.9
I
OS
(nA)
HITS
07759-008
MEAN: –0.027
SD: 0.079173
Figure 8. Typical Distribution of Input Offset Current
AD8227
Rev. 0 | Page 10 of 24
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V)
COMMON-MO DE VOLT AGE ( V)
07759-009
+0.0 2V , –0. 3V
+0. 02V, –0 .15V
+0. 02V, + 1.35V
+0.02V, +1.5V V
REF
= 0V
V
REF
= 1. 35V
+1.35V, –0.3V + 2.67V, –0.15V
+2.7V, 0V
+2.67V, +1.2V
+2.7V, +1.1V
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 2.7 V, G = 5
5
4
3
2
1
0
–1
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUT P UT VO LTAGE (V)
COMM O N-M O DE VO LT AG E (V )
07759-010
+0. 02V, –0.3V
+0.01 V, –0. 05V
+0.02V, +4V
+0. 02V , +4.25V
+2. 5V, –0.3V +4. 96V , –0.05V
+4.96V, +0.2V
+4.96V, +3.75V
+4.96V, +3.5V
V
REF
= 0V
V
REF
= 2. 5V
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 5 V, G = 5
6
4
2
0
–2
–4
–6–6 –4 –2 0 2 4 6
OUTPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
07759-011
–4.98V, +3.7V 0V, +4.2V
0V, –5.3V
–4.97V , –4. 8V
+4.96V, +3.7V
+4. 96V, –4.8V
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±5 V, G = 5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
07759-012
+0. 02V, –0 .25V
+0.02V, +1.35V
+0.02V, +1.5V
+1. 35V, –0.3V
+0.02 V, –0. 3V
+2.67V, – 0.25V
+2. 67V, –0 .25V
+2.67V, +1.2V
+2.67V, +1.1V
V
REF
= 0V
V
REF
= 1. 35V
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 2.7 V, G = 100
5
4
3
2
1
0
–1
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
07759-013
+0.02V, +4.25V
+0.02V, +4V +4.96V, +3.75V
+4.96V, +3.5V
+4. 96V , –0. 25V
+4.9 6V, –0. 2V
+0.02V, –0.3V
+0. 02V , –0. 25V
+2. 5V , –0. 3V
V
REF
= 0V
V
REF
= 2. 5V
Figure 13. Input Common-Mode Voltage vs. Output Voltage,
Single Supply, Vs = 5 V, G = 100
6
4
2
0
–2
–4
–6–6–4–20246
OUTPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
07759-014
–4.96V , +3.75V 0V, +4.2V
0V, –5.3V
–4.96V , –5. 1V
+4. 96V, + 3.25V
+4.96V, –5.1V
Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±5 V, G = 100
AD8227
Rev. 0 | Page 11
20
15
10
5
0
–5
–10
–15
–20
–20 –15 –10 –5 0 5 10 15 20
COMMON-MODE VOLTAGE (V)
59-015
of 24
OUTPUT VOLTAGE (V)
077
–14.96V, +12.7V +14.94V, +12.7V
0V, +14.2V
–14.96V, –13.8V +14.94V, –13.8V
0V, –15.3V
VS = ±15V
VS = ±12V
0V, –12.3V
0V, +11.2V
–11.96V,
+10V
–11.96V,
–11.1V
+11.94V,
–11.1V
+11.94V,
+10V
16
–16
14
–14
12
–12
10
–10
8
–8
6
–6
4
–4
2
–2
0
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
07759-018
V
S
= ±15V, G = 5
V
OUT
I
IN
Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±15 V, G = 5
20
15
10
5
0
–5
–10
COMMON-MODE VOLTAGE (V)
–15
–20
–20 –15 –10 –5 0 5 10 15 20
59-016
OUTPUT VOLTAGE (V)
077
–14.96V, +12.7V +14.94V, +12.7V
0V, +14.2V
–14.96V, –14V +14.94V, –14V
0V, –15.3V
0V, –12.3V
–11.96V,
–11.3V
+11.94V,
–11.3V
0V, +11.2V
–11.96V,
+10V
+11.94V,
+10V
VS = ±15V
VS = ±12V
Figure 16. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, Vs = ±15 V, G = 100
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
Figure 18. Input Overvoltage Performance, G = 5, Vs = ±15 V
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
07759-019
V
S
= 2.7V, G = 100
V
OUT
I
IN
Figure 19. Input Overvoltage Performance, G = 100, Vs = 2.7 V
0.25
0
–0.5
–0.6
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
07759-017
V
S
= 2.7V, G = 5
V
OUT
I
IN
Figure 17. Input Overvoltage Performance, G = 5, Vs = 2.7 V
16
14
–14
12
–12
10
–10
8
–8
6
–6
4
–4
2
–2
0
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
OUTPUT VOLTAGE (V)
INPUT CURRENT (mA)
–16 –0.5
–40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
07759-020
V
S
= ±15V, G = 100
V
OUT
I
IN
Figure 20. Input Overvoltage Performance, G = 100, Vs = ±15 V
AD8227
Rev. 0 | Page 12 of 24
33
31
29
27
25
23
21
19
140
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
NEGATIVE PSRR (dB)
07759-024
17
15
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT BIAS CURRENT (nA)
759-021
COMMON-MODE VOLTAGE (V)
07
–0.14V
+4.23V
Figure 21. Input Bias Current vs. Common-Mode Voltage, Vs = 5 V
40
35
30
25
20
15
10
5
0
–16 –12 –8 –4 0 4 8 12 16
INPUT BIAS CURRENT (nA)
9-022
COMMON-MODE VOLTAGE (V)
0775
–15.01V
+14.03V
Figure 22. Input Bias Current vs. Common-Mode Voltage, Vs = ±15 V
160
140
120
100
80
60
40
POSITIVE PSRR (dB)
20
0
0.1 1 10 100 1k 10k 100k
FREQUENCY (Hz)
07759-023
G = 1000
G = 100
G = 10
G = 5
Figure 23. Positive PSRR vs. Frequency, RTI
G = 5
G = 1000
G = 100
G = 10
Figure 24. Negative PSRR vs. Frequency
70
60
50
40
30
20
10
0
–10
–20
–30
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
GAIN (dB)
07759-025
G = 1000
G = 100
G = 10
G = 5
Figure 25. Gain vs. Frequency, VS = ±15 V
70
60
50
40
30
20
10
0
–10
–20
GAIN (dB)
–30
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
07759-026
G = 1000
G = 100
G = 10
G = 5
Figure 26. Gain vs. Frequency, VS = 2.7 V
AD8227
Rev. 0 | Page 13
160
140
120
100
80
60
40
20
0
0.1 1 10 100 1k 10k 100k
CMRR (dB)
9-027
of 24
FREQUENCY (Hz)
0775
G = 1000
G = 100 G = 10
G = 5
35
30
25
20
15
10
150
125
100
75
50
25
0
5
–45 –30 –15 0 15 30 45 60 75 90 105 120 135
TEMPERATURE (°C)
INPUT BIAS CURRENT (nA)
INPUT OFFSET CURRENT (pA)
07759-030
V
S
= ±15V
V
REF
= 0V
–IN BIAS CURRENT
+IN BIAS CURRENT
OFFSET CURRENT
Figure 27. CMRR vs. Frequency, RTI
160
140
120
100
80
60
40
CMRR (dB)
Figure 30. Input Bias Current and Offset Current vs. Temperature
20
0
0.1 1 10 100 1k 10k 100k
759-028
FREQUENCY (Hz)
07
G = 1000
G = 100 G = 10
G = 5
Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance
0.3
0.2
0.1
0
–0.1
–0.2
CHANGE IN INPUT OFFSET (µV)
300
200
100
0
–100
–200
–300
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
GAIN ERROR (µV/V)
07759-031
Figure 31. Gain Error vs. Temperature, G = 5
10
8
6
4
2
0
–2
–4
–6
–8
CMRR (µV/V)
–10
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
07759-032
Figure 32. CMRR vs. Temperature, G = 5
–0.3
0 10 20 30 40 50 60 70 80 90 100 110 120
WARM-UP TIME (s)
07759-029
Figure 29. Change in Input Offset Voltage vs. Warm-Up Time
AD8227
Rev. 0 | Page 14 of 24
+V
S
–0.2
–0.4
–0.6
–0.8
–V
S
–0.2
–0.4
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
15
10
5
0
–5
–10
–15
100 1k 10k 100k
LOAD (Ω)
OUTPUT VOLTAGE SWING (V)
07759-036
–0.6
–0.8
2 4 6 8 10 12 14 16 18
759-033
SUPPLY VOLTAGE (±V
S
)
07
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 33. Input Voltage Limit vs. Supply Voltage
+V
S
–0.1
–0.2
–0.3
–0.4
+0.4
+0.3
+0.2
–40°C
+25°C
+85°C
+105°C
+125°C
–V
S
+0.1
2 4 6 8 10 12 14 16 18
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
759-034
SUPPLY VOLTAGE (±V
S
)
07
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
+V
S
–0.2
–0.4
+0.4
–0.6
+0.6
–0.8
+0.8
–1.0
+1.0
–1.2
+1.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
Figure 36. Output Voltage Swing vs. Load Resistance
+V
S
–V
S
–0.2
–0.4
–0.6
–0.8
+0.8
+0.6
+0.4
+0.2
0.01 0.1 1 10
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
07759-037
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 37. Output Voltage Swing vs. Output Current
40
30
20
10
0
–10
–20
–30
NONLINEARITY (10ppm/DIV)
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
07759-038
–V
S
+0.2
2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V
S
)
07759-035
–40°C
+25°C
+85°C
+105°C
+125°C
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
G = 5
Figure 38. Gain Nonlinearity, G = 5, RL ≥ 2 kΩ
AD8227
Rev. 0 | Page 15 of 24
40
30
20
10
0
–10
–20
–30
–40
–10 –8 –6 –4 –2 0 2 4 6 8 10
NONLINEARITY (10ppm/DIV)
9-039
1k
100
10
1 10 100 1k 10k 100k
FREQUENCY (Hz)
NOISE (nV/
OUTPUT VOLTAGE (V)
0775
G = 10
Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ
160
120
80
40
0
–40
–80
–120
–160
–10–8–6–4–2 0 2 4 6 8 10
NONLINEARITY (40ppm/DIV)
9-040
OUTPUT VOLTAGE (V)
0775
G = 100
Figure 40. Gain Nonlinearity, G = 100, RL ≥ 2 kΩ
400
300
200
100
0
–100
–200
NONLINEARITY (100ppm/DIV)
–300
–400
–10–8–6–4–2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
07759-041
G = 1000
Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ
Hz)
07759-042
G = 5 (67nV/ Hz)
G = 10 (40nV/ Hz)
G = 100 (26nV/ Hz)
G = 1000 (25nV/ Hz)
BANDWIDTH
LIMITED
Figure 42. Voltage Noise Spectral Density vs. Frequency
G = 1000, 200nV/DIV
G = 5, 1µV/DIV
7759-0430
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 5, G = 1000
1k
100
NOISE (fA/
10
1 10 100 1k 10k
FREQUENCY (Hz)
07759-044
Figure 44. Current Noise Spectral Density vs. Frequency
Hz)
AD8227
Rev. 0 | Page 16 of 24
7759-0450
1s/DIV1.5pA/DIV
Figure 45. 0.1 Hz to 10 Hz Current Noise
5V/DIV
13.8µs TO 0.01%
16.8µs TO 0.001%
0.002%/DIV
07759-048
40µs/DIV
30
25
20
15
10
5
0
100 1k 10k 100k 1M
OUTPUT VOLTAGE (V p-p)
07759-046
FREQUENCY (Hz)
Figure 46. Large-Signal Frequency Response
07759-047
13.4µs TO 0.01%
16.6µs TO 0.001%
5V/DIV
40µs/DIV
0.002%/DIV
Figure 47. Large-Signal Pulse Response and Settling Time, G = 5,
10 V Step, VS = ±15 V
Figure 48. Large-Signal Pulse Response and Settling Time, G = 10,
10 V Step, VS = ±15 V
5V/DIV
35µs TO 0.01%
50µs TO 0.001%
0.002%/DIV
07759-049
40µs/DIV
Figure 49. Large-Signal Pulse Response and Settling Time, G = 100,
10 V Step, VS = ±15 V
07759-050
5V/DIV
275µs TO 0.01%
350µs TO 0.001%
0.002%/DIV
200µs/DIV
Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000,
10 V Step, VS = ±15 V
AD8227
Rev. 0 | Page 17 of 24
759-05107
07759-053
20mV/DIV 4µs/DIV 20mV/DIV 20µs/DIV
Figure 51. Small-Signal Pulse Response, G = 5, RL = 10 kΩ, CL = 100 pF
07759-052
20mV/DIV 4µs/DIV
Figure 52. Small-Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF
Figure 53. Small-Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF
07759-054
20mV/DIV 100µs/DIV
Figure 54. Small-Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF
AD8227
Rev. 0 | Page 18 of 24
07759-055
340
330
320
310
300
290
0 2 4 6 8 1012141618
SUPPLY VOLTAGE (±V
S
)
SUPPLY CURRENT (µA)
07759-057
20mV/DIV 4µs/DIV
NO LOAD
C
L
= 47pF
C
L
= 100pF
C
L
= 147pF
Figure 55. Small-Signal Pulse Response with Various Capacitive Loads,
G = 5, RL = Infinity
Figure 57. Supply Current vs. Supply Voltage
35
30
25
20
15
10
5
0
2 4 6 8 10 12 14 16 18 20
STEP SIZE (V)
SETTLING TIME (µs)
07759-056
SETTLED TO 0.001%
SETTLED TO 0.01%
Figure 56. Settling Time vs. Step Size, VS = ±15 V, Dual Supply
AD8227
Rev. 0 | Page 19 of 24
THEORY OF OPERATION
A3
R2
8kΩ
R1
8kΩ
A1 A2 Q2Q1 –IN
+IN
+V
S
–V
S
R3
50kΩ
R4
10kΩ
R5
10kΩ
R
B
R
B
+V
S
–V
S
V
OUT
REF
07759-058
NODE 1
NODE 2
R
G
+V
S
–V
S
V
BIAS
+V
S
–V
S
NODE 4NODE 3
R6
50kΩ
DIFFERENCE
AMPLIFIER STAGEGAIN STAGE
ESD AND
OVERVOLTAGE
PROTECTION
ESD AND
OVERVOLTAGE
PROTECTION
–V
S
Figure 58. Simplified Schematic
ARCHITECTURE
The AD8227 is based on the classic three op amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes
the common-mode voltage and provides additional amplifica-
tion. Figure 58 shows a simplified schematic of the AD8227.
The first stage works as follows. To maintain a constant voltage
across the bias resistor, RB, Amplifier A1 must keep Node 3 at a
constant diode drop above the positive input voltage. Similarly,
Amplifier A2 keeps Node 4 at a constant diode drop above the
negative input voltage. Therefore, a replica of the differential
input voltage is placed across the gain setting resistor, RG. The
current that flows across this resistance must also flow through
the R1 and R2 resistors, creating a gained differential signal
between the A2 and A1 outputs. Note that, in addition to a
gained differential signal, the original common-mode signal,
shifted a diode drop up, is also still present.
The second stage is a difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage
removes the common-mode signal from the amplified
differential signal and gains it by 5.
The transfer function of the AD8227 is
VOUT = G × (VIN+ − VIN−) + VREF
where:
GR
Gk80
5+=
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8227. The gain can be calculated by referring to Table 7 or
by using the following gain equation:
5
k80
−
=
G
RG
Table 7. Gains Achieved Using Common Resistor Values
Standard Table Value of RG Calculated Gain
No resistor 5
100 kΩ 5.8
49.9 kΩ 6.6
26.7 kΩ 8
20 kΩ 9
16 kΩ 10
10 kΩ 13
5.36 kΩ 19.9
2 kΩ 45
1.78 kΩ 49.9
1 kΩ 85
845 Ω 99.7
412 Ω 199
162 Ω 499
80.6 Ω 998
The AD8227 defaults to G = 5 when no gain resistor is used.
The tolerance and gain drift of the RG resistor should be added
to the specifications of the AD8227 to determine the total gain
accuracy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
AD8227
Rev. 0 | Page 20 of 24
REFERENCE TERMINAL
The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8227 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For best performance, source impedance to the REF terminal
should be kept below 2 Ω. As shown in Figure 58, the reference
terminal, REF, is at one end of a 50 k resistor. Additional imped-
ance at the REF terminal adds to this 50 k resistor and results
in amplification of the signal connected to the positive input.
The amplification from the additional RREF can be calculated as
follows:
6(50 k + RREF)/(60 k + RREF)
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INCORRECT
V
CORRECT
AD8227
OP1177
–
+
V
07759-059
REF
AD8227
REF
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
Most instrumentation amplifiers have a very limited output
voltage swing when the common-mode voltage is near the
upper or lower limit of the part’s input range. The AD8227 has
very little of this limitation. See Figure 9 through Figure 16 for
the input common-mode range vs. output voltage of the part.
LAYOUT
To ensure optimum performance of the AD8227 at the PCB
level, care must be taken in the design of the board layout. The
pins of the AD8227 are arranged in a logical manner to aid in
this task.
8
7
6
1
2
3
5
4
–IN
R
G
R
G
+V
S
V
OUT
REF
–V
S
+IN
TOP VIEW
(Not to Scale)
AD8227
07759-060
Figure 60. Pinout Diagram
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To keep CMRR over
frequency high, the input source impedance and capacitance of
each path should be closely matched. Additional source resis-
tance in the input path (for example, for input protection) should
be placed close to the in-amp inputs, which minimizes the
interaction of the source resistance with parasitic capacitance
from the PCB traces.
Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
should be chosen so that the parasitic capacitance is as small as
possible.
Power Supplies
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect perfor-
mance. See the PSRR performance curves in Figure 23 and
Figure 24 for more information.
A 0.1 µF capacitor should be placed as close as possible to each
supply pin. As shown in Figure 61, a 10 µF tantalum capacitor
can be used farther away from the part. In most cases, it can be
shared by other precision integrated circuits.
AD8227
+VS
+IN
–IN
LOAD
RG
REF
0.1µF 10µF
0.1µF 10µF
–VS
VOUT
07759-061
Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground
References
The output voltage of the AD8227 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
AD8227
Rev. 0 | Page 21 of 24
INPUT BIAS CURRENT RETURN PATH The other AD8227 terminals should be kept within the supplies.
All terminals of the AD8227 are protected against ESD.
The input bias current of the AD8227 must have a return path to
ground. When the source, such as a thermocouple, cannot provide
a return current path, one should be created, as shown in Figure 62.
For applications where the AD8227 encounters voltages beyond
the allowed limits, external current limiting resistors and low
leakage diode clamps such as the BAV199L, the FJH1100s, or
the SP720 should be used.
THERMOCOUPLE
+VS
REF
–VS
AD8227
CAPACITIVELY COUPLED
+VS
REF
C
C
–VS
AD8227
TRANSFORMER
+VS
REF
–VS
AD8227
INCORRECT
CAPACITIVELY COUPLED
+VS
REF
C
R
C
R
–VS
AD8227
1
f
HIGH-PASS = 2πRC
THERMOCOUPLE
+VS
REF
–VS
10MΩ
AD8227
TRANSFORMER
+VS
REF
–VS
AD8227
CORRECT
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 63. The filter
limits the input signal bandwidth, according to the following
relationship:
07759-062
Figure 62. Creating an Input Bias Current Return Path
INPUT PROTECTION
The AD8227 has very robust inputs and typically does not need
additional input protection. Input voltages can be up to 40 V
from the opposite supply rail. For example, with a +5 V positive
supply and a −8 V negative supply, the part can safely withstand
voltages from −35 V to +32 V. Unlike some other instrumentation
amplifiers, the part can handle large differential input voltages
even when the part is in high gain. Figure 17 through Figure 20
show the behavior of the part under overvoltage conditions.
)2(π2
1
C
D
DIFF CCR
uencyFilterFreq +
=
C
CM RC
uencyFilterFreq π2
1
=
where CD ≥ 10 CC.
R
R
AD8227
+VS
+IN
–IN
0.1µF 10µF
10µF
0.1µF
REF
VOUT
–VS
RG
CD
10nF
CC
1nF
CC
1nF
4.02kΩ
4.02kΩ
07759-063
Figure 63. RFI Suppression
CD affects the differential signal and CC affects the common-
mode signal. Values of R and CC should be chosen to minimize
RFI. A mismatch between R × CC at the positive input and
R × CC at the negative input degrades the CMRR of the AD8227.
By using a value of CD one magnitude larger than CC, the effect
of the mismatch is reduced, and performance is improved.
AD8227
Rev. 0 | Page 22 of 24
APPLICATIONS INFORMATION
DIFFERENTIAL DRIVE
Figure 64 shows how to configure the AD8227 for differential
output.
+IN
–IN
REF
AD8227
V
BIAS
R
+
–
OP AMP
+OUT
–OUT
06407759-
R
RECOMMENDED OP AMPS: AD8515, AD8641, AD820.
RECOMMENDED R VALUES: 5kΩ to 20kΩ.
Figure 64. Differential Output Using an Op Amp
The differential output is set by the following equation:
VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−)
The common-mode output is set by the following equation:
VCM_OUT = (VOUT+ − VOUT−)/2 = VBIAS
The advantage of this circuit is that the dc differential accuracy
depends on the AD8227 and not on the op amp or the resistors.
This circuit takes advantage of the AD8227’s precise control of
its output voltage relative to the reference voltage. Op amp dc
performance and resistor matching affect the dc common-mode
output accuracy. However, because common-mode errors are
likely to be rejected by the next device in the signal chain, these
errors typically have little effect on overall system accuracy.
Tips for Best Differential Output Performance
For best ac performance, an op amp with at least 2 MHz gain
bandwidth and 1 V/µs slew rate is recommended. Good choices
for op amps are the AD8641, AD8515, or AD820.
Keep trace lengths from resistors to the inverting terminal of
the op amp as short as possible. Excessive capacitance at this
node can cause the circuit to be unstable. If capacitance cannot
be avoided, use lower value resistors.
PRECISION STRAIN GAGE
The low offset and high CMRR over frequency of the AD8227
make it an excellent choice for bridge measurements. The
bridge can be connected directly to the inputs of the amplifier
(see Figure 65).
5V
2.5V
10µF 0.1µF
AD8227
+IN
–IN
R
G
350Ω
350Ω350Ω
350Ω
+
–
07759-065
Figure 65. Precision Strain Gage
AD8227
Rev. 0 | Page 23 of 24
DRIVING AN ADC
Figure 66 shows several different methods for driving an ADC.
The ADC in the ADuC7026 microcontroller was chosen for
this example because it has an unbuffered charge sampling
architecture that is typical of most modern ADCs. This type of
architecture typically requires an RC buffer stage between the
ADC and the amplifier to work correctly.
Option 1 shows the minimum configuration required to drive
a charge sampling ADC. The capacitor provides charge to the
ADC sampling capacitor, and the resistor shields the AD8227
from the capacitance. To keep the AD8227 stable, the RC time
constant of the resistor and capacitor needs to stay above 5 µs.
This circuit is mainly useful for lower frequency signals.
Option 2 shows a circuit for driving higher frequency signals.
It uses a precision op amp (AD8616) with relatively high band-
width and output drive. This amplifier can drive a resistor and
capacitor with a much higher time constant and is, therefore,
suited for higher frequency applications.
Option 3 is useful for applications where the AD8227 needs to
run off a large voltage supply but drives a single-supply ADC.
In normal operation, the AD8227 output stays within the ADC
range, and the AD8616 simply buffers it. However, in a fault
condition, the output of the AD8227 may go outside the supply
range of both the AD8616 and the ADC. This is not an issue in
the circuit, because the 10 k resistor between the two amplifiers
limits the current into the AD8616 to a safe level.
AD8227
REF 100nF
100Ω
10Ω
ADC0
ADC1
3.3V
3.3V
OPTION 1: DRIVING LOW FREQUENCY SIGNALS
OPTION 2: DRIVING HIGH FREQUENCY SIGNALS
3.3V
10kΩ
10nF
ADC2
AGND
OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES
3.3V
AD8227
AD8616
ADuC7026
REF
3.3V
10Ω
10nF
AD8227
AD8616
REF
+15V
–15V
AV
DD
07759-066
Figure 66. Driving an ADC
AD8227
Rev. 0 | Page 24 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
OUTLINE DIMENSIONS
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.23
0.08
0.10
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0
.95
0
.85
0
.75
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-A A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 67. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 68. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8227ARMZ1
−40°C to +125°C 8-Lead MSOP RM-8 Y1S
AD8227ARMZ-RL1
−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1S
AD8227ARMZ-R71
−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1S
AD8227ARZ1
−40°C to +125°C 8-Lead SOIC_N R-8
AD8227ARZ-RL1
−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8227ARZ-R71
−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
AD8227BRMZ1
−40°C to +125°C 8-Lead MSOP RM-8 Y1U
AD8227BRMZ-RL1
−40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1U
AD8227BRMZ-R71
−40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1U
AD8227BRZ1
−40°C to +125°C 8-Lead SOIC_N R-8
AD8227BRZ-RL1
−40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8
AD8227BRZ-R71
−40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07759-0-5/09(0)
