HYB39S128400-800-160CT(L) - Infineon Technologies

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 1 7.01

The HYB 39S128400/800/160CT are four bank Synchronous DRAM’s organized as 4

banks ×8MBit x4, 4 banks ×4MBit x8 and 4 banks ×2Mbit x16 respectively. These synchronous

devices achieve high speed data transfer rates by employing a chip architecture that prefetches

multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using

the Infineon advanced 0.17 micron process technology.

The device is designed to comply with all industry standards set for synchronous DRAM products,

both electrically and mechanically. All of the control, address, data input and output circuits are

synchronized with the positive edge of an externally supplied clock.

Operating t he four memory banks in an inter leave fashion al lows random access operati on to occur

at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is

possible depending on burst length, CAS latency and speed grade of the device.

Auto Refr esh (CBR) and Self Refresh o peration are s upported. Thes e devices o perate with a singl e

3.3 V ±0.3 V power supply and are available in TSOPII packages.

• High Performance:

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• 0 to 70 °C operating temperature

• Four Banks controlled by BA0 & BA1

• Programmable CAS Latency: 2, 3

• Programmable Wrap Sequence: Sequential

or Interleave

• Programmable Burst Length: 1, 2, 4, 8

• Mul tiple Burst Read with Single Write

Operation

• Automati c and Controlled Precharge

Command

• Data M a sk for Read/Write Control (x4, x8)

• Data M a sk for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Power Down and Clock Suspend Mode

• 4096 R efresh Cycles / 64 ms

• Random Column Address every CLK

(1-N Rule)

• Single 3.3 V ±0.3 V Power Supply

• LVTTL Interface

• Plastic Packages:

P-TSOPII-54 400mil x 875 mil width

(x4, x8, x16)

• -7 for PC 133 2-2-2 applications

-7.5 for PC 133 3-3-3 applications

-8 for PC100 2-2-2 appl ications

-7 -7.5 -8 Units

fCK 143 133 125 MHz

tCK3 77.58ns

tAC3 5.4 5.4 6 ns

tCK2 7.5 10 10 ns

tAC2 5.4 6 6 ns

128-MBit Synchronous DRAM

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 2 7.01

Ordering Information

Type Function Code Package Description

HYB 39S128400CT-7 PC133-222-520 P-TSOP-54 (400mil) 143MHz 4B × 8M x4 SDRAM

HYB 39S128400CT-7.5 PC133-333-520 P- TSO P-54 (400mil) 133 M Hz 4B × 8M x4 SDRAM

HYB 39S128400CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 8M x4 SDRAM

HYB 39S128800CT-7 PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B × 4M x8 SDRAM

HYB 39S128800CT-7.5 PC133-333-520 P- TSO P-54 (400mil) 133 MHz 4B × 4M x8 SDRAM

HYB 39S128800CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 4M x8 SDRAM

HYB 39S128160CT-7 PC133-222-520 P-TSOP-54 (400mil) 143 MHz 4B × 2M x16 SDR AM

HYB 39S128160CT-7.5 PC133-333-520 P- TSO P-54 (400mil) 133 MHz 4B × 2M x16 SDRAM

HYB 39S128160CT-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 2M x16 SDR AM

HYB 39S128160CTL-8 PC100-222-620 P-TSOP-54 (400mil) 100 MHz 4B × 2M x16 SDRAM

Low Power (“L”) version

HYB 39S128160CTL-7.5 PC133-333-520 P- TSO P-54 (400mil) 133 MHz 4B × 2M x16 SDRAM

Low Power (“L”) version

Pin Definitions and Functions

CLK Clock Input DQ Data Input/Output

CKE Clock Enable DQM, LDQM,

UDQM Data Mask

CS Chip Select VDD Power (+ 3.3 V)

RAS Row Address Strobe VSS Ground

CAS Column Address Strobe VDDQ Power for DQ’s (+ 3.3 V)

WE Write Enable VSSQ Ground for DQ’s

A0 - A11 Address Inputs N.C. Not connected

BA0, BA1 Bank Select

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 3 7.01

Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs

SPP04121

VDD

DQ0

A10

VDD

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

CAS

RAS

BA0

BA1 BA1

BA0

RAS

CAS

N.C.

VDD

N.C.

VSSQ

DQ3

N.C.

VDDQ

DQ2

N.C.

VSSQ

DQ1

N.C.

VDDQ

VDD

A10

DQ0

VDD VDD

BA1

BA0

RAS

CAS

N.C.

VDD

N.C.

VSSQ

DQ1

N.C.

VDDQ

N.C.

VSSQ

DQ0

N.C.

VDDQ

VDD

A10

N.C. VSS

N.C.

VSS

VSSQ

N.C.

DQ3

VDDQ

N.C.

VSSQ

N.C.

DQ2

VDDQ

N.C.

VSS

N.C.

CLK

DQM

CKE

N.C.

A11

A9 A9

A11

N.C.

CKE

DQM

CLK

N.C.

VSS

N.C.

VDDQ

DQ4

N.C.

VSSQ

DQ5

N.C.

VDDQ

DQ6

N.C.

VSSQ

VSS

DQ7

VSS VSS

A11

N.C.

CKE

UDQM

CLK

N.C.

VSS

DQ8

VDDQ

DQ9

DQ10

VSSQ

DQ11

DQ12

VDDQ

DQ13

DQ14

VSSQ

VSS

DQ15

TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)

32 M x 4

16 M x 8

8 M x 16

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 4 7.01

Functi onal B lock Dia grams

Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)

Memory

Array

Bank 1

4096

x 2048

x 4 Bit

Memory

Array

Bank 2

4096

x 2048

x 4 Bit

Memory

Array

Bank 3

4096

x 2048

x 4 Bit

SPB04122

Column Address

Counter

Row

Decoder

Memory

Array

Bank 0

4096

x 2048

x 4 Bit

Column Decoder

Sense amplifier & I(O) Bus

Row

Decoder

Sense amplifier & I(O) Bus

Row

Decoder Row

Decoder

Column Decoder

Sense amplifier & I(O) Bus

Row Address

Buffer

Column Address

Buffer Refresh Counter

Sense amplifier & I(O) Bus

A0 - A11,

BA0, BA1

A0 - A9, A11, AP,

BA0, BA1

Column Addresses Row Addresses

Input Buffer Output Buffer

DQ0 - DQ3

Control Logic &

Timing Generator

CLK

CKE

RAS

CAS

DQM

Column Decoder

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 5 7.01

Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)

Memory

Array

Bank 1

4096

x 1024

x 8 Bit

Memory

Array

Bank 2

4096

x 1024

x 8 Bit

Memory

Array

Bank 3

4096

x 1024

x 8 Bit

SPB04123

Column Address

Counter

Row

Decoder

Memory

Array

Bank 0

4096

x 1024

x 8 Bit

Column Decoder

Sense amplifier & I(O) Bus

Row

Decoder

Sense amplifier & I(O) Bus

Row

Decoder Row

Decoder

Column Decoder

Sense amplifier & I(O) Bus

Row Address

Buffer

Column Address

Buffer Refresh Counter

Sense amplifier & I(O) Bus

A0 - A11,

BA0, BA1

A0 - A9, AP,

BA0, BA1

Column Addresses Row Addresses

Input Buffer Output Buffer

DQ0 - DQ7

Control Logic &

Timing Generator

CLK

CKE

RAS

CAS

DQM

Column Decoder

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 6 7.01

Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing)

Memory

Array

Bank 1

4096 x 512

x 16 Bit

Memory

Array

Bank 2

4096 x 512

x 16 Bit

Memory

Array

Bank 3

4096 x 512

x 16 Bit

SPB04124

Column Address

Counter

Row

Decoder

Memory

Array

Bank 0

4096 x 512

x 16 Bit

Column Decoder

Sense amplifier & I(O) Bus

Row

Decoder

Sense amplifier & I(O) Bus

Row

Decoder Row

Decoder

Column Decoder

Sense amplifier & I(O) Bus

Row Address

Buffer

Column Address

Buffer Refresh Counter

Sense amplifier & I(O) Bus

A0 - A11,

BA0, BA1

A0 - A8, AP,

BA0, BA1

Column Addresses Row Addresses

Input Buffer Output Buffer

DQ0 - DQ15

Control Logic &

Timing Generator

CLK

CKE

RAS

CAS

DQMU

DQML

Column Decoder

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 7 7.01

Signal Pin Description

Pin Type Signal Polarity Function

CLK Input Pulse Positive

Edge The system clock input. All of the SDRAM inputs are

sampled on the rising edge of the clock.

CKE Input Level Active

High Activates the CLK signal when high and deactivates the

CLK signal when low, thereby initiating either the Power

Down mode, Suspend mode, or the Self Refresh mode.

CS Input Pulse Active

Low CS enables the command decoder when low and disables

the command decoder when high. When the command

decoder is disabled, new com mands are ignored but

previous operations continue.

RAS

CAS

Input Pulse Active

Low When sampled at the positi ve rising edge of the clock,

CAS, RAS, and WE define the command to be executed by

the SDRAM.

A0 - A11 Input Level –During a Bank Activate command cycle, A0 - A11 define

the row address (RA0 - RA11) w hen sampled at the rising

clock edge.

During a Read or Write command cycle, A0-An define the

column address (CA0 - CAn) when sampled at the rising

clock edge.CAn depends upon the SDRAM organization:

32M x4 SDR AM CA0 - CA9, CA11

(Page Length = 2048 bi ts)

16M x8 SDR AM CA0 - CA9 (Page Length = 1024 bits)

8M x16 SDR AM CA0 = CA8 (Page Length = 512 bits)

In addition to the column address, A10(= AP) is used to

invoke the autoprecharge operation at the end of the burst

read or write cycle. If A10 is high, autoprecharge is

selected and BA0, BA1 defines the bank to be prec harged.

If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10 (= AP) is used in

conjunction with BA0 and BA1 to control which bank(s) to

precharge. If A10 is high, all four banks will be precharged

regardless of the state of BA0 and BA1. If A10 is low, then

BA0 and BA1 are used to define which bank to precharge.

BA0, BA1 Input Level –Bank Select Inputs. Selects which bank is to be active.

DQx Input

Output Level –Data Input/Output pins operate in the same m anner as on

conventional DRAMs.

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 8 7.01

DQM

LDQM

UDQM

Input Pulse Active

High The Data Input/Output mask places the DQ buffers in a

high impedance state when sampled high. In Read mode,

DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM

has a latency of zero and operates as a word mask by

allowing input data to be w ritten if it is low but blocks the

write operation if DQM is high.

One DQM input is present in x4 and x8 SDRAMs, LDQM

and UDQM controls the lower and upper bytes in x16

SDRAMs.

VDD

VSS

Supply –– Power and ground for the input buffers and the core logic.

VDDQ

VSSQ

Supply –– Isolated power supply and ground for the output buffers to

provide improved noise immunity.

Signal Pin Description (cont’d)

Pin Type Signal Polarity Function

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 9 7.01

Operation Definition

All of SDRAM operations are defined by states of control signals CS, RAS, CA S, WE, and DQM at

the positive edge of the clock. The following list shows the tr uth table for the operation comm ands.

Notes:

1. V = Valid, x = Don’t Care, L = Low Level, H = High Level.

2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock

before the commands are provided.

3. This is the state of the banks designated by BA0, BA1 signals.

4. Power Down Mode can not entry in the burst cycle. When this command is asserted in the burst

mode cycle the device is in clock suspend mode.

Operation De vice

State CKE

n-1 CKE

nDQM BA0

BA1 AP=

A10 Addr

A11,

A9-0

CS RAS CAS WE

Bank Active Idle3 HXXVVVLLHH

Bank Precharge Any H X X V L X L L H L

Precharge All Any H X X X H X L L H L

Write Active3HXXVLVLHLL

Write with Autoprecharge Active3HXXVHVLHLL

Read Active3HXXVLVLHLH

Read with Autop r echarge Active3HXXVHVLHLH

Mode Register Set Idle HXXVVVLLLL

No Operation Any H X X X X X L H H H

Burst Stop Active H X X X X X L H H L

Device Deselect Any HXXXXXHXXX

Auto Refresh Idle H H X X X X L L L H

Se lf R e fr es h E n tr y Idl e H L X X X X L L L H

Self Re fres h Exit Idle

(Self

Refr.) LHXXXXHXXX

LHHX

Power Down Entry

(Prech arge or active

standby)

Idle

Active4HLXXXXHXXX

LHHX

Power Down Exit Any

(Power

Down) LHXXXXHXXX

LHHL

Data Write/Output EnableActive HXLXXXX XXX

Data Write/Output DisableActive HXHXXXXXXX

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 10 7.01

Address Inputs for Mode Register Set Operation

SPD04125

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Operation Mode CAS Latency BT Burst Length

Address Bus (Ax)

Mode Register (Mx)

BA1 BA0 M11 M10 M9 M8 M7 Mode

0 0 0 0 0 0 0 Burst Read/

Burst Write

M3 Type

0 0 0 0 1 0 0 Burst Read/

Single Write

Operation Mode Burst Type

0 Sequential

1 Interleave

M5 M4 LatencyM6

CAS Latency

0 0 Reserved0

10 0 Reserved

200 1

1 310

1 0 40

11 0 Reserved

01 1

1 11

M1 M0 Length

Burst Length

Sequential

10 0 1

00 1

1 0 8

11 0 Reserved

01 1

1 11

Reserved

Interleave

00 0

Reserved

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 11 7.01

Power On and Initialization

The default power on state of the mode register is supplier specific and may be undefined. The

following power on and initialization sequence guarantees the device is preconditioned to each

user s speci fic needs. Like a conve ntional D RAM, t he Synchronous DRAM must be powered up and

initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up

simultaneously to the specified voltage when the input signals are held in the “NOP” state. The

power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK

signal must be started at the same time. After power on, an initial pause of 200 µs is required

foll owed by a pr echarge of al l banks us ing t he prechar ge command. To prevent data c ontention on

the DQ bus during power on, it i s required that the DQM and CKE pins be held high during the i nitial

pause period. Once all banks have been precharged, the Mode Register Set Command must be

issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also

required.These may be done before or after programming the Mode Register. Failure to follow these

steps may lead to unpredictable start-up modes.

Programming the Mode Register

The Mode registe r designates the operati on mode at the read or write cycle. This regis ter is divi ded

into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to

program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency

Field to set the access time at clock cycle and a Operation mode field to differentiate between

normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode.

After the initi al power up, the mode set operation must be done before any activate command. Any

content o f the mode register can be altered by re-exec uting the mode set command. All banks must

be in precharged state and CKE must be high at least one clock before the mode set operation. After

the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and

WE at the positive edge of the clock activate the mode set operation. Address input data at this

timing defines parameters to be set as shown in the previous table.

Read and Write Operation

When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle

starts. According to address data, a word line of the selected bank is activated and all of sense

amplifi ers associated to the wordline ar e set. A CAS cycle is triggered b y setting RAS high and CAS

low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either

a read (WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fas t access modes. In a single CAS cycle, serial data read or

write operations are allowed at up to a 143 MHz data rate. The numbers of serial data bits are the

burst length programmed at the mode set operation, i.e., one of 1, 2, 4, and 8. Col umn addresses

are s egmented by the burst len gth and serial data ac cesses are done within this boundar y. The first

column address to be ac cessed is supplied at the CAS timi ng and the s ubsequent addresses are

generated automati call y by the programmed burst l ength and i ts sequenc e. F or ex ample, i n a burs t

length of 8 with int erl eave sequence, if the fir st add ress is ‘2’, then the rest of the burst se quence is

3, 0, 1, 6, 7, 4, and 5.

Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column

address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the

refresh interval time limits the number of random column accesses. A new burst access can be

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 12 7.01

done even before the previous burst ends. The interrupt operation at every clock cycle is supported.

When the previous burst is interrupted, the remaining addresses are overridden by the new address

with the full burst length. An interrupt which accompanies an operation change from a read to a write

is possible by exploiting DQM to avoid bus contention.

When two or mo r e banks are activated sequentially, interleaved bank read or write operations are

possible. With the programmed burst length, alternate access and precharge operations on two or

more banks can realize fast serial data access modes among many different pages. Once two or

more banks are activated, column to column interleave operation can be performed between

different pages.

Refresh Mode

SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS

-before-RAS refresh of conv enti onal DRAMs. All of bank s must be prec harged befor e appl ying any

refresh mode. An on-chip address counter increments the word and the bank addresses and no

bank inform ation is required for both refresh modes.

The chip enters the Auto Refresh mode, w hen RAS and CAS are held low and CKE and WE are

held hi gh at a clock timing. T he mode restores word l ine after the refresh and no external pre charge

command i s nec es s ary . A mini mum tRC time is requir ed between two automatic refreshes in a burst

refresh mode. The same rule applies to any access command after the automatic refresh operation.

The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS,

CAS, and CKE are l ow and WE is hi gh at a clock timing. All of ex ternal contr ol signal s incl uding the

clock are disabl ed. Retur ning CKE to hi gh ena bles the c lock an d i nitiates th e r efresh e xit ope rati on.

After the exit command, at least one tRC delay is required prior to any access command.

Burst Length and Sequence

Burst

Length Starting

Address

(A 2 A1 A0)

Sequential Burst

Addressing

(decimal)

Interleave Burst

Addressing

(decimal)

2xx0

xx1 0, 1

1, 0 0, 1

1, 0

4x00

x01

x10

x11

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

8 000

001

010

011

100

101

110

111

0 1 2 3 4 5 6 7

1 2 3 4 5 6 7 0

2 3 4 5 6 7 0 1

3 4 5 6 7 0 1 2

4 5 6 7 0 1 2 3

5 6 7 0 1 2 3 4

6 7 0 1 2 3 4 5

7 0 1 2 3 4 5 6

0 1 2 3 4 5 6 7

1 0 3 2 5 4 7 6

2 3 0 1 6 7 4 5

3 2 1 0 7 6 5 4

4 5 6 7 0 1 2 3

5 4 7 6 1 0 3 2

6 7 4 5 2 3 0 1

7 6 5 4 3 2 1 0

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 13 7.01

DQM Function

DQM has two functions for data I/O read a nd write oper ations. Duri ng reads, when it turns to “high”

at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM

Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated,

the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).

Suspend Mode

During norm a l access mode, CKE is held high enabling the clock. When CKE is low, it freezes the

internal clock and extends data read and write operations. One clock delay is required for mode

entry and exit (Clock Suspend Latency tCSL).

Power Down

In order to redu ce standby power consumpti on, a power down mode is available. Al l banks must be

precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the

Power Down mode. Once the Power Down mode is ini tiate d by holding CKE l ow, all of the receiver

circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh

operations, therefore the device can’t remain in Power Down mode longer than the Refresh period

(tREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is

required for power down m ode entry and exit.

Auto Precharge

Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS

timing accepts one extra address, CA10, to determine whether the chip restores or not after the

operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function

is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function

is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR

(Write recovery time) after the last data in.

Precharge Command

There is also a separate precharge command available. When RAS and WE are low and CAS is

high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are

used to define banks as shown in the following list. The precharge command can be imposed one

clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS

latency = 3 and three clocks before the last data out for CAS latency = 4. Writes require a time delay

tWR from the last data out to apply the precharge command.

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 14 7.01

Burst Termination

Once a burst read or write operation has been initiated, there are several methods in which to

terminate the burst operation prematurely. These methods include using another Read or Write

Command to interrupt an existing burst operation, use a Precharge C ommand to interrupt a burst

cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst

operation but leave the bank open for future Read or Write Commands to the same page of the

activ e bank. When interrupti ng a bur st with another Read or Write Command c ar e must be tak en to

avoid DQ c ontention. The Burst Stop Command, however, has the fewest rest rict ions m aking it the

easiest method to use when terminating a burst operation before it has been comp leted. If a Burst

Stop command is issued during a burst write operation, then any residual data from the bur st write

cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is

registered will be written to the m emory.

Bank Selection by Address Bits

A10 BA0 BA1

000Bank 0

001Bank 1

010Bank 2

011Bank 3

1 x x all Banks

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 15 7.01

Electrical Characteristics

Absolute Maximum Ratings

Operating Temperature Range.......................................................................................0 to + 70 °C

Storage Temper ature Range.................................................................................. – 55 to + 150 °C

Input/Output Voltage......................................................................................... – 0.3 to VDD + 0.3 V

Power Supply Vol tage VDD/VDDQ.............................................................................. – 0.3 to + 4.6 V

Power Dissipation.......................................................................................................................1 W

Data out Current (short circuit) ............................................................................................... 50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Notes

1. All voltages are referenced to VSS.

2. VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to

–2.0 V for pulse w idth < 4.0 ns with 3.3 V. Pulse w idth measured at 50% points with amplitude

measured peak to DC reference.

Recommended Operation and DC Characteristics

TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V

Parameter Symbol Limit Values Unit Not es

min. max.

Input High Voltage VIH 2.0 VDD +0.3 V 1, 2

Input Low Voltage VIL –0.3 0.8 V 1, 2

Output High Voltage (IOUT =–4.0 mA) VOH 2.4 –V–

Output Low Voltage (IOUT =4.0mA) VOL –0.4 V –

Input Leakage Curr ent, any input

(0 V < VIN <VDDQ, all other inputs = 0 V) II(L) –55 µA–

Output Leakage Current

(DQ is disabled , 0 V < VOUT <VDD)IO(L) –55 µA–

Capacitance

TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz

Parameter Symbol Values Unit

min. max.

Input Capacitanc e (C LK) CI1 2.5 3.5 pF

Input Capacitanc e

(A0 - A11, BA0, BA1, RAS , CAS, WE, CS, CKE, DQM) CI2 2.5 3.8 pF

Input/Output Capacitance (DQ) CIO 4.0 6.0 pF

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 16 7.01

Notes

3. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 &

-7.5 and at 100 MHz for -8 parts. Input signals are changed once during tCK.

4. These parameters are measured with continuous data stream during read access and all DQ

toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded.

Operating Currents

TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V

(Recommended Operating Conditions unless otherwise noted)

Parameter & Test Condition S ymb. -7 -7.5 -8 Un it Note

max.

Operating current

tCK =tCK(MIN.)

All banks operated in random

access,

all banks operated in ping-pong

manner

–ICC1

170 160 150 mA 3,4

Precharge standby current

in Power Down Mode

CS = VIH (MIN.), CKE ≤VIL(MAX.)

tCK =min ICC2P 1.5 mA 3

Precharge standby current

in Non Power Down Mode

CS = VIH (MIN.), CKE ≥VIH(MIN.)

tCK =min ICC2N 45 40 35 mA 3

No operating current

tCK = min., CS = VIH (MIN.),

active state (max. 4 banks)

CKE ≥VIH(MIN.) ICC3N 50 50 45 mA 3

CKE ≤VIL(MAX.) ICC3P 10 mA 3

Burst Operating Current

tCK =min

Read command cycling

–ICC4 110 100 90 mA 3, 4

Auto Refresh Current

tCK = min, tr c = trcmin.

Auto Refresh command cycling

–ICC5 250 230 210 mA 3

Self Refresh Current

Self Refresh Mode

CKE = 0.2 V, tck=infinity

standard

version ICC6 1.5 mA

L-version 690 µA

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 17 7.01

AC Characteristics 1, 2

TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns

Paramet e r Symb. Limit Values Unit Note

-7 -7.5 -8

min. max. min. max. min. max.

Clock and Clock Enable

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2 tCK 7

7.5 –

–7.5

10 –

–8

10 –

–ns

–

Clock frequency

CAS Latency = 3

CAS Latency = 2 tCK –

–143

133 –

–133

100 –

–125

100 MHz

MHz

–

Access Time from Clock

CAS Latency = 3

CAS Latency = 2 tAC –

–5.4

5.4 –

–5.4

6–

–6

6ns

2, 3, 6

Clock High Pulse Width tCH 2.5 –2.5 –3–ns –

Clock Low Pulse Width tCL 2.5 –2.5 –3–ns –

Transition Time tT0.3 1.2 0.3 1.2 0.5 10 ns –

Se tup a nd Hold Ti mes

Input Setup Time tIS 1.5 –1.5 –2–ns 4

Input Hold Time tIH 0.8 –0.8 –1–ns 4

CKE Setup Time tCKS 1.5 –1.5 –2–ns 4

CKE Hold Time tCKH 0.8 –0.8 –1–ns 4

Mode Register Set-up Time tRSC 2–2–2–CLK –

Power Down Mode Entry

Time tSB 0707.508ns–

Common Paramet ers

Row to Column Delay Time tRCD 15 –20 –20 –ns 5

Row Precharge Time tRP 15 –20 –20 –ns 5

Row Active Time tRAS 42 100k 45 100k 48 100k ns 5

Row Cycle Time tRC 60 –67 –70 –ns 5

Activate(a) to Activate(b)

Command Period tRRD 14 –15 –16 –ns 5

CAS(a) to CAS(b) Command

Period tCCD 1–1–1–CLK –

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 18 7.01

Refresh Cycle

Refresh Period

(4096 cycles) tREF –64 –64 –64 ms –

Self Refresh Exit Time tSREX 1–1–1–CLK

Read Cycle

Data Out Hold Time tOH 3–3–3–ns 2, 5, 6

Data Out to Low Impedance

Time tLZ 0–0–0–ns –

Data Out to High Impedance

Time tHZ 373738ns–

DQM Data Out Disable

Latency tDQZ –2–2–2CLK–

Write Cycle

Write Recovery Time tWR 2–2–2–CLK 7

DQM Write Mask Latency tDQW 0–0–0–CLK –

AC Characteristics (cont’d)1, 2

TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns

Paramet e r Symb. Limit Values Unit Note

-7 -7.5 -8

min. max. min. max. min. max.

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 19 7.01

Notes

1. For proper power-up see the operation section of this data sheet.

2. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover

point. The transition time is measured between VIH and VIL. All AC measurements assume

tT= 1 ns with the AC outpu t load circuit shown in figure below. Specifi ed tAC and tOH param eters

are measured with a 50 pF only, without any resistive termination and with a input signal of 1V /

ns edge rate between 0.8 V and 2.0 V.

3. If clock rising time is longer than 1 ns, a time (tT/2 −0.5) ns has to be added to this parameter.

4. If tT is longer than 1 ns , a time (tT−1) ns has to be added to this parameter.

5. These parameter ac co unt for the number of clock cycles and depe nd on the operati ng frequency

of the clock, as follows:

the number of clock cycles = specified value of timing period (counted in fractions as a whole

number)

6. Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,

Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.

7. The write recovery time twr = 2 CLK cycles is a digital i nterlock on this device. Special devic es

with twr = 1 CLK for operations at less or equal 83 MHz will be available.

SPT03404

CLOCK 2.4 V

0.4 V

INPUT

HOLD

SETUP

OUTPUT 1.4 V

t t

1.4 V

50 pF

I/O

Measurement cond itions for

tAC and tOH

HYB 39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 20 7.01

Package Outlines

GPX09039

22.22

±0.131)

127

54 28

0.35

+0.1

-0.05

0.1

10.16

±0.13

±0.2

11.76

±0.1

0.5

Does not include plastic or metal protrusion of 0.15 max per side

54x

±0.05

0.15

-0.03

+0.06

15˚

±5˚

15˚

±5˚

6 max

2.5 max

Does not include plastic protrusion of 0.25 max per side

Does not include dambar protrusion of 0.13 max per side

Index Marking

0.8

20.8

26x 0.8 = 0.2

54x

Plastic Package, P-TSOPII-54

(400 mil, 0.8 mm lead pitch)

Thin Small Outline Package, SMD

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.Dimensions in mm

SMD = Surface Mounted Device

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 21

T iming Diagrams

1. Bank Activate Command Cycle

2. Burs t Read Operation

3. Read Interrupted by a Read

4. Read to Write Int erval

4.1 Read to Write Int erval

4.2 Minimum Read to Writ e Interval

4.3 Non-Minimum Re ad to Wri te Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 W ri te Interrupted by a Wr it e

6.2 W ri te Interr upted by Read

7. Burs t Wri te & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Pre charge

8. AC- Paramete rs

8.1 AC Paramet ers for a Write Timing

8.2 AC Parameters for a Read Timing

9. Mode Register Set

10. Power on Sequence and Auto Refresh (CBR)

11. Cl ock Suspension (using CKE)

11. 1 Clo ck Suspension During Bur st Read CAS Latency = 2

11. 2 Clo ck Suspension During Bur st Read CAS Latency = 3

11. 3 Clo ck Suspension During Bur st Wri te CAS Latency = 2

11. 4 Clo ck Suspension During Bur st Wri te CAS Latency = 3

12. Power Down Mode and Clock Suspend

13. Sel f Refresh ( Entr y and Exit )

14. Aut o Refresh ( CBR )

15. Random Column Read ( Page within sam e Bank)

15.1 CAS Lat ency = 2

15.2 CAS Lat ency = 3

16. Random Column Write ( Page wi thin sam e Bank)

16.1 CAS Lat ency = 2

16.2 CAS Lat ency = 3

17. Random Row Read ( Interleaving Banks) with Precharge

17.1 CAS Lat ency = 2

17.2 CAS Lat ency = 3

18. Random Row Write ( Inte rl eaving Banks) with Precharge

18.1 CAS Lat ency = 2

18.2 CAS Lat ency = 3

19. Precharge Termination of a Burst

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 22

1. Bank Activate Command Cycle

2. Burst Read Operation

"H" or "L"

(CAS latency = 3)

Bank B

Row Addr.

Activate

Bank B

Address

Command

CLK

NOPNOP

RCD

Col. Addr.

Bank B

with Auto

Precharge

Write B

SPT03784

Bank B

Row Addr.

Activate

Bank B

Row Addr.

Bank A

Activate

Bank A

NOP

RRD

SPT03712

CLK

Read A NOP

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command NOP NOP NOP NOP NOP NOP NOP

DOUT A3

CK2

latency = 2

t, DQ’s DOUT A1DOUT A0 DOUT A2

DOUT A2

CK3

latency = 3

t, DQ’s DOUT A0 DOUT A1 DOUT A3

(Burst Length = 4, CAS latency = 2, 3)

CAS

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 23

3. Read In terrupted by a Read

4. Read to Write Intrerval

4.1 Read to Write Interval

SPT03713

CLK

Read A

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DOUT A0 DOUT B0 DOUT B1 DOUT B2

NOP NOP NOP NOP NOP NOP NOP

latency = 2

, DQ’s

CK2

CK3

latency = 3

t, DQ’s

(Burst Length = 4, CAS latency = 2, 3)

CAS

Read B

DOUT B3

DOUT B1DOUT A0 DOUT B0 DOUT B3DOUT B2

Commands = 4 + 1 = 5 cycles

Minimum delay between the Read and Write

DOUT A0

DQ’s

(Burst Length = 4, CAS latency = 3)

DQMx

Command

CLK

NOP Read A

T0 T1

NOP NOP

T2 T3

the Write Command

Must be Hi-Z before

DIN B0 DIN B1

SPT03787

DIN B2

DQW

NOP

DQZ

NOP

T4 T5

Write B NOP

T6 T7

NOP

"H" or "L"

Write latency of DQMx

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 24

4 2. Minimum Read to Write Interval

4. 3. Non-Minimum Read to Write Interval

the Write Command

Must be Hi-Z before

Activate

CAS

CK2

latency = 2

t, DQ’s

(Burst Length = 4, CAS latency = 2)

CLK

DQM

Command NOP

T0 T1

Bank A

NOP

DQZ

T2 T3

DIN A0 DIN A1 DIN A2

SPT03939

DIN A3

1 Clk Interval

Read A Write A

T4 T5

NOP NOP

T6 T7

NOP

"H" or "L"

DQW

NOP

CAS

latency = 3

CK3

CAS

CK2

latency = 2

, DQ’s

, DQ’s DOUT A0

(Burst Length = 4, CAS latency = 2, 3)

CLK

DQM

Command NOP Read A

T0 T1

NOP NOP

T2 T3

the Write Command

Must be Hi-Z before

DOUT A0

DOUT A1

DIN B0

DIN B1

SPT03940

DIN B2

Read A

DQZ

NOP

T4 T5

Write B NOP

T6 T7

NOP

"H" or "L"

tDQW

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 25

5. Burst Write Operation

Extra data is ignored after

termination of a Burst.

DIN A3

are registered on the same clock edge.

The first data element and the Write

NOP

(Burst Length = 4, CAS latency = 2, 3)

Command

DQ’s

CLK

DIN A1

NOP

DIN A0

Write A

DIN A2

NOP

SPT03790

NOP NOP

NOP

don’t care

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 26

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by a Read

1 Clk Interval

SPT03791

CLK

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command NOP NOP NOP NOP NOP NOP

DQ’s

(Burst Length = 4, CAS latency = 2, 3)

NOP Write A

DIN A0 DIN B0 DIN B1 DIN B2 DIN B3

Write B

1 Clk Interval

NOP

DOUT B1

DOUT B0

Input data for the Write is ignored.

, DQ’s

latency = 3

CK3

CAS

don’t care

DIN A0

don’t care

(Burst Length = 4, CAS latency = 2, 3)

CLK

, DQ’s

Command

latency = 2

CK2

CAS

NOP

DIN A0

Write A

don’t care

Read B

T1 T2

DOUT B0

NOP NOP

T4T3

SPT03719

appears on the outputs to avoid data contention.

DOUT B2

Input data must be removed from the DQ’s

at least one clock cycle before the Read data

DOUT B1 DOUT B3

NOP

DOUT B3

NOP

DOUT B2

T6 T7

NOP

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 27

7. Burst Write and Read with Auto Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

SPT03909 2

CLK

Active

NOP

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command NOP NOP NOP NOP

DQ’s

Bank A

Begin Auto Precharge

Bank can be reactivated after trp

Wri te A

Auto Precharge

DIN A1DIN A0

CAS Latency = 2:

DQ’s

CAS Latency = 3:

Active

NOPCommand NOP NOP NOP NOP NOP NOP

Bank A Write A

Auto Precharge

NOP

Activate

(Burst Leng th = 2, CAS latency = 2, 3 )

Activate

SPT03721_2

CLK

with AP

NOP

T0 T1 T2 T3 T4 T5 T6 T7 T8

Command

DO UT A0 DOUT A1 DOUT A2 DOUT A3

NOP NOP NOP NOP NOP NOP NOP

latency = 2

DQ’s

DOUT A 3

latency = 3

DOUT A1DOUT A0 DOUT A2

(Bu rst Length = 4, CAS latency = 2, 3)

CAS

Read A

Bank can be reactivated after trp

Begin Auto Precharge

DQ’s

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 28

8. AC Parameters

8.1 AC Parameters for a Write Timing

A uto Precharge

Bank B

Command

Writ e wi t h

Activate

Writ e wi t h

Activate

Bank A

Command

Auto Precharge

Bank A

Command Command

Bank B

Addr.

DQM

Hi-Z

RCD

Ax2Ax1Ax0 Ax3

RAx

RBx

CAx

Command

SPT03910_2

Bx1Bx0

CBx

Precharge

Begin Auto

Bank A

CLK

CAS

RAS

CKE

CK2

CKS

T3T0 T2T1 T4 T5 T7T6 T18

B urst Length = 4, CAS Latency = 2

T13T9 T10 T12T11 T14 T15 T17T16 T19 T20 T22T21

RBx

RAx

Activate Write

Command

Bank AB ank A

RAy

B ank B

Precharge

B egin Auto

RBy

ActivatePrecharge

Command

Bank A Bank A

Command Activate

Bank B

Command

CKH

RAz

RAz RBy

RAy

Bx2 Bx3

WR RP

Ay2Ay1Ay0 Ay3

RRD

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 29

8.2 AC Parameters for a Read Timing

AC2

Hi-Z

Activate

Command

Bank A

Read

Bank A

Command

DQM

Addr.

RCD

RAx

CAx

RRD

Command

Bank B

Read w ith

Auto Precharge

Activate

B ank B

Command

Ax1Ax0 Bx0

Activate

SPT03911_2

Command

B ank A

Bx1

AC2

RAS

RBx

RAy

CAS

RAS

CKE

CKS

CK2

CLK

T0 T1 T2 T3 T4

Precharge

Bank B

Be gin A uto

CKH

B urst Length = 2, CA S Latency = 2

T6 T7 T8 T10T9 T11 T13T12

Precharge

B ank A

Command

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 30

9. Mode Register Set

Set Comm and

Mode Register

All Ba nks

Precharge

Command Any

Command

Addres s Key

T0 T1 T2 T8

RSC

T3 T5 T6 T7 T11T9 T10 T12 T13

SPT03912_2

T19T16T15T14 T17 T18

CAS Latency = 2

T20 T21 T22

Addr.

CAS

RAS

CKE

CLK

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 31

10. Power on Sequence and Auto Refresh (CBR)

Inputs must be

200stable for

DQM

Addr.

Command

All Banks

Precharge

Hi-Z

1st Auto Refresh

Command

SPT03913

Mode Register

Set Command

Address Key

8th Auto Refresh

Command

Any

Minimum of 8 Refresh Cycles are required

CAS

RAS

CKE

CLK

required

LevelHigh

T0 T2T1 T5T4 T7T6 T18

2 Clock min.

T13

T10T9 T12T11 T14 T15 T17T16 T20T19 T22T21

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 32

11. Clock Suspension ( Using CKE)

11.1 Clock Suspension During Burst Re ad CAS Latency = 2

Command

Bank A

DQM

Addr.

Read

Command

Bank A

Activate

Hi-Z

Suspend

1 Cycle

Clock

Ax0

CSL

Ax1

CAxRAx

RAx

SPT03914

Suspend

3 Cycles

Suspend

2 Cycles

Clock

Ax2

CSL

Clock

Ax3

CAS

RAS

CKE

CLK

CK2

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 2

T18T17 T19 T20 T21 T22

CSL

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 33

11.2 Clock Suspension Dur ing Burst Read CAS Latency = 3

CSL

DQM

Addr.

Bank A

Activate

Command

Hi-Z

Command

Bank A

Read

Ax0

RAx

CAx

Suspend

1 Cycle

Clock Suspend

2 Cycles

Clock

CSL

Ax1 Ax2

Clock

Suspend

3 Cycles

CSL

Ax3

SPT03915

CAS

RAS

CKE

CLK

CK3

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 3

T18T17 T19 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 34

11.3 Clock Suspension During Burst Write CAS Latency = 2

Bank A

DQM

Addr.

DAx0

Command

Write

Activate

Command

Bank A

Hi-Z

Clock Clock

1 Cycle

Suspend Suspend

2 Cycles

DAx1

CAxRAx

RAx

DAx3

Clock

Suspend

3 Cycles

DAx2

SPT03916

CAS

RAS

CKE

CLK

CK2

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 2

T18T17 T19 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 35

11.4 Clock Suspension During Burst Write CAS Latency = 3

Clock

Suspend

2 Cycles

Bank A

DQMx

Addr.

A8/AP

Activate

Command

Bank A

Hi-Z

Clock

1 Cycle

Suspend

Command

Write

DAx0 DAx1

RAx

CAx

Clock

Suspend

3 Cycles

DAx2 DAx3

SPT03917

CAS

RAS

CKE

CLK

CK3

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 3

T18T17 T19 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 36

12. Power Down Mod e and Clock Suspend

Clock SuspendClock Suspend

Mode Entry Mode Exit

Addr.

DQM

Standby

Active

Activate

Bank A

Command

Hi-Z

Read

Command

Bank A

RAx

CAx

Power Down Power Down

Mode ExitMode Entry

SPT03918

End

Clock Mask

Start

Ax0 Ax1 Ax2

Precharge

Command

Bank A

Ax3

Precharge

Standby Any

Command

CAS

RAS

CKE

CLK

CK2

T0 T1 T2

CKS

T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 2

CKS

T18

T17 T19 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 37

13 . Self Refresh (E ntry and Exit)

S elf Refresh Exit

Comm and issued

Addr.

DQM

Entry

Self Refresh

mus t be idle

A ll Banks

Hi-Z

SPT03919-2

Exit Com mand

Begin Self Refresh

SREX

Self Refresh

Command

Exit

Any

CAS

RAS

CKE

CLK

CKS

T0 T1 T2 T3 T4 T6T5 T16

CKS

T8 T9 T10 T11 T14T12 T13 T15 T18T17 T19 T20 T21 T22

minimum RAS cycle

time depends on CAS

Latency and trc

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 38

14. Auto Refresh (CBR)

(Minimum Interval)

Addr.

DQM

Auto Refresh

Command

All Banks

Precharge

Command

Hi-Z

SPT03920_2

RAx

CAx

CAS

RAS

CKE

CLK

CK2

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 4, CAS Latency = 2

T18T17 T19 T20 T21 T22

Command

Au to Re fre sh CommandCommand

Bank A

Activate

Bank A

Read

Ax2Ax0 Ax1 Ax3

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 39

15. Random Column Read (Page within same Bank)

15.1 CAS Latency = 2

Ay1

Addr.

DQM

Activate

Command

ZHi

Bank A

RAw

Command

Read

Command

Bank A

Read

Bank A

Aw0 Aw1

CAw CAx

Read

Bank A

Command

Aw3Aw2 Ax0 Ax1 Ay0

CAy

CAS

RAS

CKE

CLK

CK2

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

Precharge

Command

Bank A

Ay2 Ay3

Activate

Command

Bank A

RAz

SPT03921

Read

Bank A

Command

CAz

Burst Length = 4, CAS Latency = 2

T19T16T15T14 T17 T18 T20 T21 T22

Az3Az0 Az1 Az2

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 40

15.2 CAS Latency = 3

Ay3

CAw

Addr.

DQM

ZHi

Bank A

Activate

Command Read

Command

Bank A

RAw

Bank A

Command

Aw1Aw0

Read

Bank A

Command

Aw2 Aw3

CAx

Read

Ax1Ax0 Ay0

Precharge

Command

Bank A

Ay1 Ay2

CAy

CAS

RAS

CKE

CLK

CK3

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

Bank A

Read

Command

Activate

Command

Bank A

RAz

CAz

SPT03922

Burst Length = 4, CAS Latency = 3

T19T16T15T14 T17 T18 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 41

16. Random Column write (Page within same Bank)

16.1 CAS Latency = 2

DBy1

Addr.

DQM

Activate

Command

ZHi

Bank B

RBw

Command

Write

Command

Bank B

Write

Bank B

DBw0 DBw1

CBw CBx

Write

Bank B

Command

DBw3DBw2 DBx0 DBx1 DBy0

CBy

CAS

RAS

CKE

CLK

CK2

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

Precharge

Command

Bank B

DBy2 DBy3

Activate

Command

Bank B

RBz

SPT03923_2

Read

Bank B

Command

CBz

Burst Length = 4, CAS Latency = 2

T19T16T15T14 T17 T18 T20 T21 T22

DBz1DBz0 DBz2 DBz3

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 42

16.2. CAS Latency = 3

Command

Write

Bank B

CBz

DBw0

Addr.

DQM

Bank B

Activate

Command

ZHi

RBz

Command

Bank B

DBw3DBw1 DBw2

Write

Bank B

Command

DBx0 DBx1

CBx

Write

DBy1DBy0 DBy2

Precharge

Command

Bank B

DBy3

CBy

CAS

RAS

CKE

CLK

CK3

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

Command

Bank B

DBz0

Activate

Command

Bank B

Write

DBz1

RBz

CBz

SPT03924

Burst Length = 4, CAS Latency = 3

T19T16T15T14 T17 T18 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 43

17. Random Row Read (Interleaving Banks) with Precharge

17.1 CAS Latency = 2

Ax2

Addr.

DQM

Bank B

Activate

Command

Hi-Z

Command

Read

Bank B

RBx

RCD

CBx

Read

Activate

Bank A

Command

Bank B

Command

Bx2Bx0

AC2

Bx1

Bank A

Activate

Bx3 Bx4

RAx

Command

Precharge

Bank B

Bx6Bx5 Bx7 Ax0 Ax1

CAx RBy

RBy

CAS

RAS

CKE

CLK

High

CK2

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

SPT03925_2

Bank B

Command

Ax5Ax3 Ax4

Read

Ax6 Ax7

CBy

By1By0

Burst Length = 8, C AS Latency = 2

T19T16T15T14 T17 T18 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 44

17.2 CAS Latency = 3

Activate

Command

Bank A

Addr.

DQM

Read

Bank B

Command

Bank B

Activate

Hi-Z Bx1Bx0

CBxRBx

RCD

RBx

AC3

Activate

Command

Bank B

Bx6

Bank A

Command

Read

Bx4Bx3Bx2 Bx5

Bank B

Precharge

Command

Ax0Bx7 Ax2Ax1

RAx CAx

RAx

RBy

Precharge

Bank A

Command

Ax7

Read

Bank B

Command

Ax5Ax4Ax3 Ax6

SPT03926

By0

CBy

CAS

RAS

CKE

CLK

High

CK3

T0 T1 T2 T3 T4 T6T5 T16T8 T9 T10 T11 T14T12 T13 T15

Burst Length = 8, CAS Latency = 3

T18T17 T19 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 45

18. Rand om Row Write (Interleaving Banks) with Precharge

18.1 CAS Latency = 2

DBx4DAx1

Addr.

DQM

Activate

Command

Bank A

Hi-Z

Write

Command

Bank A

DAx0

RAx

RCD

CAx

CommandCommand

Bank B Bank A

Command

DAx4DAx2 DAx3

Bank B

Activate

DAx5 DAx6

RBx

Command

Precharge

Bank A

Write

DBx0DAx7 DBx1

Activate

DBx2 DBx3

CBx RAy

RAy

CLK

CKE

RAS

CAS

High

CK2

T1 T2 T8T4T3 T5 T6 T7 T11T9 T10 T12 T13

Command

Bank A

SPT03927_2

Command

Precharge

Bank B

DBx7DBx5 DBx6

Write

DAy0 DAy1

CAy

DAy4DAy3DAy2

T19

Burst Length = 8, CAS Latency = 2

T16T15T14 T17 T18 T20 T21 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEON Technologies 46

18.2 CAS Latency = 3

DAx4

Addr.

DQM

Command

Bank A

Activate

Command

Hi-Z

Write

DAx0 DAx1 DAx3DAx2

RAx

RCD

RAx

CAx

DBx4DBx0

Write

Command

Bank B

Activate

Command

DAx6DAx5 DAx7

Precharge

Command

Bank A

DBx2DBx1 DBx3

CBxRBx

RBx

Command

Bank A

Activate

Command Bank A

Write

DBx5 DBx6 DAy0DBx7

Precharge

Bank B

Command

SPT03928

DAy1 DAy2 DAy3

RAy

CAy

RAy

CAS

RAS

CKE

CLK

High

CK3

T0 T1 T4T3 T5 T6 T15T7 T8 T9 T10 T11 T12 T13 T14

Burst Length = 8, CAS Latency = 3

T19T17T16 T18 T21T20 T22

HYB39S128400/800/160CT(L)

128-MBit Synchronous DRAM

INFINEO N Technologi es 47

19. Precharge termination of a Burst

19.1 CAS Latency = 2

Command

Activate

Bank A

T14

Write Data is masked.

of a Write Burst.

Precharge Termination

Addr.

DQM

Command

Bank A

Activate

Hi Z

Bank A

Write

Command

DAx0 DAx1

RAx

CAx

Command

Bank A

Command

Precharge

Bank A

DAx3DAx2

Activate

RAy

Ay0

Command

Bank A

Read

Bank A

Precharge

Command

Ay1 Ay2

CAy

CAS

RAS

CKE

CLK

High

CK2

T1 T2 T4 T5 T7T6 T8 T10T9 T11 T13T12

Precharge Termination

of a Read Burst.

SPT03933

Bank A

Command

Precharge

Command

Bank A

Read

Az0 Az1

RAz CAz

RAz

Az2

Burst Length = 8 or Full Page, CAS Latency = 2

T20

T17T15 T16 T18 T19 T21 T22

INFINEON Technologies

Att e n tio n pl e ase !

As far as patents or other rights of third parties are concerned, liability is only

assumed for components, not for applications, processes and c ircuits implemented

within components or assemblies. This infomation describes the type of

components and shall not be considered as assured characteristics. Terms of

delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact INFINEON

Technologies Offices in Munich or the IN FINEON Technologies Sales Offices and

Representatives worldwide.

Due to technical requirements components may contain dangerous substances.

For information on the types in question please contact your nearest INFINEON

Technologies office or representative.

Packing

Please use the r ecycling operators known to you. We can help you - get in touch

with your nearest sales office. By agr eement we will take packing material back, if

it is sorted. You must bear the costs of transport. For packing material that is

returned to us unsorted or which we are not obliged to accept, we shall have to

invoice you for any costs incurred.

Components used in life-support devices or systems must be

expressly authorized for such purpose!

Ciritcal components1 of INFINEON Technologies, may only be used in life-support

devices or s yst ems2 with the ex press written app rov al of INFINEON Technol ogies.

1. A critical component is a component used in a life-support device or system

whose failure can reasonably be expected to cause the fai lure of that life-support

device or system, or to affect the safety or effectiveness of that device or system.

2. Life support devices or systems are intended (a) to be implanted i n the human

body, or (b) to support and/or maintain and sustain human life. If they fail, it is

reasonable to assume that the health of the user may be endangered.