XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 1 of 6
PRODUCT FEATURES
Supports Pentium series, M2 and K6 CPUs.
Supports Intel, VIA, SiS and Opti chipset
requirements.
Supports Sychronous DRAM designs
4 host (CPU/AGP) clocks & 8 SDRAM clocks.
Optional common or mixed supply mode :
(Vdd = Vddq3 = Vddq4 = Vddq2 = 3.3V)
(Vdd = Vddq3 = Vddq4 = 3.3V, Vddq2 = 2.5V)
< 250 pS skew on CPU buffers
< 250 pS skew on PCI buffers
Supports Single Pin Power Management.
48 Pin SSOP package for minimum board space
BLOCK DIAGRAM
REF
OSC
Xin
Xout
3
Buffers REF0,1,2
IOAPIC
Vddq2
PLL1
SEL [0:2]
4CPUCLK0~3
Vddq2
Buffer
Buffers
Buffers
8SDRAM0~7
Vddq3
dly Buffers
6PCICLK0~5
PLL2
PWR_DWN#
Buffer
Buffer
48MHZ
24MHZ
Buffer PCICLK_F
Vddq4
FREQUENCY TABLE
SEL2 SEL1 SEL0 CPU PCI
1 1 1 66.8* 33.4*
1 1 0 60* 30*
1 0 1 75* 37.5*
1 0 0 55 27.5
0 1 1 68.5 34.25
0 1 0 83.3 33.3
0 0 1 75 30
0 0 0 83.3 41.65
*Spread Spectrum - when SSON is at a logic high level
(center spread +/- 1.25%)
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
REF1
REF0
Vss
Xin
Xout
SSON
Vddq4
PCICLK_F
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
Vss
Vss
Vddq4
SEL0
SEL1
Vddq4
48MHZ
24MHZ
Vss Vdd
SDRAM6
Vddq3
SDRAM5
Vss
SDRAM4
SDRAM2
SDRAM1
SDRAM0
CPUCLK3
CPUCLK2
CPUCLK1
CPUCLK0
SDRAM3
Vddq3
Vss
Vddq2
Vss
PWR_DWN#
IOAPIC
Vddq2
REF2
Vdd
SEL2
SDRAM7
XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 2 of 6
PIN DESCRIPTION
Xin, Xout - These pins form an on-chip reference
oscillator when connected to an external parallel
resonant crystal (nom inally 14.318 MHz). Xin may also
be used as an input for an externally generated
reference signal.
SEL(0:2) - Standard f requency select inputs. T hey have
internal pull-ups.
CPUCLK(0:3) - Low skew (<250 pS) clock outputs for
host frequencies such as CPU, Chipset, Cache. Vddq2
is the supply voltage for these outputs.
SDRAM(0:7) - Synchronous DRAM DIMs clocks. They
are powered by Vddq3.
PCICLK(0:5) - Low skew (<250pS) clock outputs for
PCI frequencies. These buffers voltage level is
controlled by Vddq3.
PCICLK_F - A PCI cloc k output that does not stop until
it is in the power down mode. It is synchronous with
other PCI clocks.
SSON - Spread Spectrum On/Off switch. W hen SSON
= 0, Non-spread, When SSON = 1, spread is + 1.25%
of the specified frequency. See Frequency Table, pg. 1.
REF(0:2) - Buffered outputs of reference 14.3MHZ.
IOAPIC - Buffered output of 14.3MHZ for
multiprocessor support. It is powered by Vddq2.
48MHz - Frequency output for USB.
24MHz - Frequency output for super I/O.
PWR_DWN# - Power down pin stops the whole chip
including the VCOs and the PCICLK_F output pin. It has
an internal pull-up
Vss - Ground pins for the chip.
Vdd - Power supply pins for analog circuit and core
logic.
Vddq3 - Power supply pins for 3.3V IO pins.
Vddq2 - Power supply pins for 2.5V/3.3V IO pins.
Vddq4 = Power supply pins for 3.3V PCI pins.
POWER MANAGEMENT FUNCTIONS
The IMIXG552 clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are
stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered
down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry
should allow 3 mS for the VCOs to stabilize prior to assuming the pulse widths are correct.
XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 3 of 6
MAXIMUM RATINGS
Voltage Relative to VSS: -0.3V
Voltage Relative to VDD: 0.3V
Storage Temperature: 0ºC to + 125ºC
Operating Temperature: 0ºC to + 70ºC
Maximum Power Supply : 5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Units Conditions
Input Low Voltage VIL - - 0.8 Vdc -
Input High Voltage VIH 2.0 - - Vdc -
Input Low Current IIL -66 µA
Input High Current IIH 5 µA
Output Low Current IOL1 61 - - mA VOL1 = 1.6V (@ CPU, SDRAM, PCI,
IOAPIC and REF0 clocks)
Output High Current IOH1 61 - - mA VOH1 = 1.0V (@ CPU, SDRAM, PCI,
IOAPIC and REF0 clocks)
Output Low Current IOL2 42 - - mA VOL2 = 1.9V (@ 48Mhz, 24 Mhz, REF2
and REF1 clocks)
Output High Current IOH2 40 - - mA VOH2 = 1.0V (@ 48Mhz, 24 Mhz, REF2
and REF1 clocks)
Tri-State leakage Current Ioz - - 10 µA
Dynamic Supply Current Idd - 40 - mA CPU = 66.6 Mhz, No Load
Static Supply Current Idd - 200 - µA PWR_DWN# = Low
Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds
VDD = VDDq2 = VDDq3 = Vddq4 = 3.3V+5%, TA = 0ºC to +70ºC
Contact IMI for IBIS models.
XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 4 of 6
SWITCHING CHARACTERISTICS
Characteristic Symbol Min Typ Max Units Conditions
Output Rise (0.4V - 2.0V)
and Fall (2.0V-0.4V) time tTLH,
tTHL - - 1.6 ns 22 pf Load
CPU and PCI outputs
Output Duty Cycle - 45 50 55 % Measured at 1.5V
CPU/SDRAM to PCI Offset tOFF 1 - 4 ns 15 pf Load Measured at 1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM) tSKEW1 - - 250 ps 15 pf Load Measured at 1.5V
Skew (CPU-SDRAM) tSKEW2 - - 500 ps 15 pf Load Measured at 1.5V
∆Period Cycles, CPU ∆P- - +250 ps -
Jitter Absolute, CPU tjab - 500 ps -
Overshoot/Undershoot
Beyond Power Rails Vover - - 1.5 V 22 ohms @ source of 8 inch PCB run
to 15 pf load
Ring Back Exclusion VRBE 0.7 2.1 V note1
VDD = VDDq2 = VDDq3 = Vddq4 = 3.3V+5%, TA = 0ºC to +70ºC
note 1: Ring Back must not enter this range.
XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 5 of 6
PCB LAYOUT RECOMMENDATION
This is only a layout recommendation for best performance and lower EMI. The designer may choose a
differnent approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and
placed close to their VDD pins.
IMIXG552
C4
VCC
2
C13
VCC
1
FB1
FB2
C3
C6
C9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
15
16
17
19
20
21
22
23
24
18
30
29
28
27
26
25
31
C5
C12
C11
C10
C8
C7
Via to VDD Island
Via to GND plane
Via to VCC plane
10µF
10µF
XG552
Clock Generator for Pentium Based Designs W/2 DIMM and Spread
Spectrum Support
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. Rev.1.2 10/14/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Page 6 of 6
PACKAGE DRAWING AND DIMENSIONS
48 PIN SSOP OUTLINE DIMENSIONS
INCHES MILLIMETERS
SYMBOL MIN NOM MAX MIN NOM MAX
A 0.095 0.102 0.110 2.41 2.59 2.79
A10.008 0.012 0.016 0.20 0.31 0.41
A2 0.088 0.090 0.092 2.24 2.29 2.34
B 0.008 0.010 0.0135 0.203 0.254 0.343
C 0.005 - 0.010 0.127 - 0.254
D 0.620 0.625 0.630 15.75 15.88 16.00
E 0.292 0.296 0.299 7.42 7.52 7.59
e 0.025 BSC 0.635 B SC
H 0.400 0.406 0.410 10.16 10.31 10.41
a 0.10 0.013 0.016 0.25 0.33 0.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a0º5º8º 0º5º8º
X 0.085 0.093 0.100 2.16 2.36 2.54
ORDERING INFORMATION
Part Number Package Type Production Flow
IMIXG552AYB 48 PIN SSOP Commercial, 0ºC to +70ºC
Note: The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
XG552AYB
Date Code, Lot #
IMIXG552AYB Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
Revision
IMI Device Number
Be
A
A1
A2
E
H
a
L
C
D
