NCP3011, NCV3011 Synchronous PWM Controller The NCP3011 is a PWM device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.8 V. The NCP3011 provides integrated gate drivers and an internally set 400 kHz oscillator. The NCP3011 has an externally compensated transconductance error amplifier with an internally fixed soft-start. The NCP3011 incorporates output voltage monitoring with a Power Good pin to indicate that the system is in regulation. The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode) or outputs a 180 out-of-phase clock signal to drive another NCP3011 (Master Mode). Protection features include lossless current limit and short circuit protection, output overvoltage and undervoltage protection, and input undervoltage lockout. The NCP3011 is available in a 14-pin TSSOP package. http://onsemi.com 14 1 TSSOP-14 DT SUFFIX CASE 948G Features * * * * * * * * * * * * Input Voltage Range from 4.7 V to 28 V 400 kHz Operation 0.8 V $1.0% Reference Voltage Buffered External +1.25 V Reference Current Limit and Short Circuit Protection Power Good Enable/Disable Pin Input Undervoltage Lockout External Synchronization Output Overvoltage and Undervoltage Protection NCV Prefix for Automotive and Other Applications Requiring Site and Change Controls This is a Pb-Free Device PIN CONNECTIONS HSDR PG VSW Q2 LSDR VOUT RFB1 GND COMP NC LSDR GND (TOP VIEW) R ISET SYNC HSDR VSW Q1 LO VREF VCC BST BST EN CO FB Device Package Shipping NCV3011DTBR2G TSSOP-14 2500 / Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. C C1 Figure 1. Typical Application Circuit (c) Semiconductor Components Industries, LLC, 2011 ORDERING INFORMATION NCP3011DTBR2G TSSOP-14 2500 / Tape & Reel (Pb-Free) RFB2 RC June, 2011 - Rev. 3 3011= Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PG CBST VCC CC2 1 COMP FB VIN CREF 3011 ALYWG G EN NC SYNC * Set Top Box * Power Modules * ASIC / DSP Power Supply RREF 14 VREF Typical Applications CIN MARKING DIAGRAM 1 Publication Order Number: NCP3011/D NCP3011, NCV3011 VCC INTERNAL BIAS EN PG BST POR/STARTUP ENABLE/ POWER GOOD LOGIC VC THERMAL SD BOOST CLAMP SYNC CLK/ DMAX/ SOFT START OSCILLATOR VREF GATE DRIVE LOGIC RAMP 1.25 V REFERENCE 1.5 V LEVEL SHIFT HSDR VCC VSW CURRENT LIMIT SAMPLE & HOLD ISET + - COMP REF OTA VC LSDR PWM COMP FB + - + - OOV OUV Figure 2. NCP3011 Block Diagram http://onsemi.com 2 BST_CHRG GND NCP3011, NCV3011 PIN FUNCTION DESCRIPTION Pin Pin Name 1 VREF Description 2 EN The EN pin is the enable/disable input. A logic high on this pin enables the device. This pin has also an internal current source pull up. A 10 kW resistor should be connected in series with this pin if VEN is externally biased from a separate supply. 3 NC Not Connected 4 SYNC 5 PG 6 COMP 7 FB 8 GND Ground Pin 9 LSDR The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side N-FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR to GND. 10 NC 11 VSW The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense current in the high side MOSFET. 12 HSDR The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side N-FET. 13 BST The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the VSW pin. 14 VCC The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET. The VREF pin is the output for a 1.25 V reference (1 mA max). A 100 kW resistor in parallel with a 1 mF ceramic capacitor must be connected from this pin to GND to ensure external reference stability. The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode). Alternately, it outputs a 456 kHz clock signal with 180 of phase shift (Master Mode). Connect a 100 kW resistor from SYNC to GND to enable Master Mode. No resistor is required for Slave Mode. The Power Good pin is an open drain output that is low when the regulated output voltage is beyond the "Power Good" upper and lower thresholds. Otherwise, it is a high impedance pin. The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage mode control feedback loop. The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to compensate the voltage mode control feedback loop. Not Connected http://onsemi.com 3 NCP3011, NCV3011 ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted) Rating Symbol VMAX VMIN Unit BST 45 -0.3 V BST-VSW 13.2 -0.3 V COMP COMP 5.5 -0.3 V Enable EN 5.5 -0.3 V Feedback FB 5.5 -0.3 V High Side Drive Boost Pin Boost to VSW differential voltage High-Side Driver Output HSDR 40 -0.3 V Low-Side Driver Output LSDR 13.2 -0.3 V PG 5.5 -0.3 V SYNC 5.5 -0.3 V VCC 40 -0.3 V VREF 5.5 -0.3 V Switch Node Voltage VSW 40 -0.6 Maximum Average Current VCC, BST, HSDRV, LSDRV, VSW, GND REF EN SYNC PG Imax Power Good Synchronization Main Supply Voltage Input External Reference Operating Junction Temperature Range (Note 1) 130 7.1 2.5 11 4 V mA TJ -40 to +140 C TJ(MAX) +150 C Storage Temperature Range Tstg -55 to +150 C Thermal Characteristics (Note 2) TSSOP-14 Plastic Package Thermal Resistance Junction-to-Air RqJA 190 C/W RF 260 Peak C Maximum Junction Temperature Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb-Free (Note 3) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. PD + T J(max) * T A R qJA 2. When mounted on minimum recommended FR-4 or G-10 board 3. 60-180 seconds minimum above 237C. http://onsemi.com 4 NCP3011, NCV3011 ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Conditions Min - 4.7 Max Unit 28 V EN = 0 VCC = 12 V - 2.5 4.0 mA VCC Supply Current VFB = 0.75 V, Switching, VCC = 4.7 V - 5.8 8.0 mA VCC Supply Current VFB = 0.75 V, Switching, VCC = 28 V - 6.0 12 mA UVLO Rising Threshold VCC Rising Edge 3.8 4.3 4.7 V UVLO Falling Threshold VCC Falling Edge 3.6 4.0 4.3 V Input Voltage Range Typ SUPPLY CURRENT Quiescent Supply Current UNDER VOLTAGE LOCKOUT OSCILLATOR Oscillator Frequency Ramp-Amplitude Voltage TJ = +25C, 4.7 V v VCC v 28 V 350 400 450 kHz TJ = -40C to +125C, 4.7 V v VCC v 28 V 330 400 470 kHz Vpeak - Valley - 1.5 - V 0.44 0.7 0.96 V Ramp Valley Voltage PWM Minimum Duty Cycle - 7 - % Maximum Duty Cycle 80 83 - % VFB = VCOMP - 5.2 - ms IREF = 1 mA 1.14 1.25 1.35 V VREF Line Regulation VCC = 4.7 V - 28 V -1 - +1 % VREF Load Regulation IREF = 0 mA to 1.5 mA -2 -0.2 +2 % VREF = 0 V 4.5 5.7 7.0 mA Enable Threshold High - - 3.4 V Enable Threshold Low 1.0 - - V Enable Source Current 20 50 90 mA Soft Start Ramp Time EXTERNAL VOLTAGE REFERENCE VREF Voltage Short Circuit Output Current ENABLE POWER GOOD Power Good High Threshold VCC = 12 V 0.72 0.89 1.06 V Power Good Low Threshold VCC = 12 V 0.65 0.71 0.75 V VCC = 12 V, IPG = 4 mA 0.13 0.22 0.35 V - - 2.0 V - 5.0 - V - 90 - mV - 200 - - 1.6 - mA Master Threshold Current 5.0 14.4 25 mA Master Frequency 390 466 550 kHz Power Good Low Voltage SYNC SYNC Input High Threshold SYNC Output High 10 mA load SYNC Output Low Phase Delay (Note 4) SYNC Drive Current (Sourcing) 4. 5. 6. 7. Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature. http://onsemi.com 5 NCP3011, NCV3011 ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Conditions Min Typ Max Unit 0.9 1.33 1.9 mS - 70 - dB 45 45 70 70 100 100 mA mA ERROR AMPLIFIER (GM) Transconductance Open Loop dc Gain (Notes 4 and 6) Output Source Current Output Sink Current FB Input Bias Current - 0.5 500 nA TJ = 25 C 0.792 0.8 0.808 V -40C < TJ < +125C, 4.7 V < VIN < 28 V 0.788 0.8 0.812 V COMP High Voltage VFB = 0.75 V 4.0 4.4 5.0 V COMP Low Voltage VFB = 0.85 V - 60 - mV Feedback Voltage OUTPUT VOLTAGE FAULTS Feedback OOV Threshold 0.9 1.0 1.1 V Feedback OUV Threshold 0.55 0.59 0.65 V OVER CURRENT 7.0 14 18 mA RSET = 22.2 kW 140 240 360 mV HSDRV Pullup Resistance VCC = 8 V and VBST = 7.5 V VSW = GND 100 mA out of HSDR pin 4.0 10.5 20 W HSDRV Pulldown Resistance VCC = 8 V and VBST = 7.5 V VSW = GND 100 mA into HSDR pin 2.5 5.0 11.5 W LSDRV Pullup Resistance VCC = 8 V and VBST = 7.5 V VSW = GND 100 mA out of LSDR pin 3.0 8.9 16 W LSDRV Pulldown Resistance VCC = 8 V and VBST = 7.5 V VSW = GND 100 mA into LSDR pin 1.0 2.8 6.0 W HSDRV falling to LSDRV Rising Delay VCC and VBST = 8 V 50 85 110 ns LSDRV Falling to HSDRV Rising Delay VCC and VBST = 8 V 60 85 120 ns VIN = 12 V, VSW = GND, VCOMP = 1.3 V 5.5 7.5 9.6 V Thermal Shutdown (Notes 4 and 7) - 150 - C Hysteresis (Notes 4 and 7) - 15 - C ISET Source Current Current Limit Set Voltage (Note 5) GATE DRIVERS AND BOOST CLAMP Boost Clamp Voltage THERMAL SHUTDOWN 4. 5. 6. 7. Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature. http://onsemi.com 6 NCP3011, NCV3011 TYPICAL PERFORMANCE CHARACTERISTICS 3.35 95 9V 12 V 16 V 80 75 70 16 V 3.33 9V 3.32 Typical Application Circuit Figure 47 65 60 12 V 3.34 85 Vout (V) EFFICIENCY (%) 90 0 1 2 5 4 3 Typical Application Circuit Figure 47 3.31 6 0 1 2 Iout (A) 460 804 440 420 Vin = 12 V, 28 V fSW (kHz) VFB (mV) 802 Vin = 5 V Vin = 12 V, 28 V 400 Vin = 5 V 380 796 360 794 792 -40 -25 -10 5 20 35 50 65 80 340 -40 -25 -10 95 110 125 5 TEMPERATURE (C) 20 50 65 80 95 110 125 Figure 6. Switching Frequency vs. Input Voltage and Temperature 3.0 7.0 2.8 6.5 Vin = 28 V ICC, DISABLED (mA) 2.6 Vin = 28 V 6.0 5.5 Vin = 12 V 5.0 4.5 4.0 -40 -25 -10 35 TEMPERATURE (C) Figure 5. Feedback Reference Voltage vs. Input Voltage and Temperature ICC, SWITCHING (mA) 6 Figure 4. Load Regulation vs. Input Voltage 806 798 5 Iout (A) Figure 3. Efficiency vs. Output Current and Input Voltage 800 4 3 Vin = 5 V 5 20 35 50 2.4 2.2 Vin = 12 V Vin = 5 V 2.0 1.8 1.6 1.4 1.2 65 80 1.0 -40 -25 -10 95 110 125 TEMPERATURE (C) 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 7. Supply Current vs. Input Voltage and Temperature Figure 8. Supply Current (Disabled) vs. Input Voltage and Temperature http://onsemi.com 7 NCP3011, NCV3011 TYPICAL PERFORMANCE CHARACTERISTICS 1.39 4.4 1.375 Vin = 5 V 1.36 4.3 UVLO Rising Threshold 1.33 1.315 UVLO (V) gm (mS) 1.345 Vin = 12 V, 28 V 1.30 4.2 4.1 1.285 4.0 1.27 UVLO Falling Threshold 1.255 1.24 -40 -25 -10 5 20 35 50 65 80 3.9 -40 -25 -10 95 110 125 5 TEMPERATURE (C) 1100 VPG (mV) THRESHOLD VOLTAGE (mV) 80 95 110 125 300 PG_Upper, Vin = 5 - 28 V 900 800 PG_Lower, Vin = 5 - 28 V 700 275 250 Vin = 5, 12, 28 V 225 200 OUV, Vin = 5 - 28 V 600 175 500 -40 -25 -10 20 5 35 50 65 80 150 -40 -25 -10 95 110 125 5 TEMPERATURE (C) 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 11. Output Voltage Thresholds vs. Input Voltage and Temperature Figure 12. Power Good Output Low Voltage vs. Input Voltage and Temperature 3.5 70 Rising Threshold Vin = 12 V, 28 V 3.0 65 60 Vin = 5 V 2.75 55 2.5 IEN (mA) VEN (V) 65 IPG = 4 mA 325 1000 2.25 Falling Threshold 1.75 Vin = 12 V, 28 V Vin = 5 V 1.0 -40 -25 -10 Vin = 5, 12, 28 V 50 45 40 1.5 1.25 50 350 OOV, Vin = 5 - 28 V 2.0 35 Figure 10. Input Undervoltage Lockout vs. Temperature Figure 9. Transconductance vs. Input Voltage and Temperature 3.25 20 TEMPERATURE (C) 35 5 20 35 50 65 80 30 -40 -25 -10 95 110 125 TEMPERATURE (C) 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 13. Enable Thresold vs. Input Voltage and Temperature Figure 14. Enable Pullup Current vs. Input Voltage and Temperature http://onsemi.com 8 NCP3011, NCV3011 TYPICAL PERFORMANCE CHARACTERISTICS 1000 950 2.0 VALLEY VOLTAGE (mV) 1.8 VSYNC (V) Vin = 12 V, 28 V 1.6 Vin = 5 V 1.4 1.2 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 900 850 800 750 700 650 Vin = 5 - 28 V 600 550 500 450 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) Figure 16. Valley Voltage vs. Input Voltage and Temperature Figure 15. SYNC Threshold vs. Input Voltage and Temperature 1.0 1.26 0.8 1.255 1.245 VREFE_load-reg (%) VREFE (V) 1.25 0.6 Vin = 5 V Vin = 12 V, 28 V 1.24 0.4 0.2 Vin = 5 V 0 -0.2 -0.4 Vin = 12 V, 28 V -0.6 1.235 -0.8 1.23 -40 -25 -10 5 20 35 50 65 80 95 110 125 -1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) Figure 17. External Reference Voltage vs. Input Voltage and Temperature Figure 18. External Reference Voltage vs. Input Voltage and Temperature Input = 16 V, Output = 3.3 V, Load = 5 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = Power Good, C4 (Green) = Enable Input = 16 V, Output = 3.3 V, Load = 5 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = Power Good, C4 (Green) = Enable Figure 19. Soft-Start Waveforms Figure 20. Soft-Stop Waveforms http://onsemi.com 9 NCP3011, NCV3011 6.0 14.0 5.8 13.8 Vin = 5 V 5.6 ISET (mA) tSoft-Start (ms) TYPICAL PERFORMANCE CHARACTERISTICS Vin = 12 V, 28 V 5.4 5.2 13.6 Vin = 12 V, 28 V 13.4 Vin = 5 V 13.2 5.0 -40 -25 -10 5 20 35 50 65 80 13.0 -40 -25 -10 95 110 125 TEMPERATURE (C) 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Figure 21. Soft-Start Time vs. Input Voltage and Temperature Figure 22. Current Limit Set Current vs. Temperature Input = 9 V, Output = 3.3 V, Load = 0 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = HSDR Input = 9 V, Output = 3.3 V, Load = 5 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = HSDR Figure 24. CCM Switching Waveforms (Vin = 9 V) Figure 23. No Load Switching Waveforms (Vin = 9 V) Input = 16 V, Output = 3.3 V, Load = 0 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = HSDR Input = 16 V, Output = 3.3 V, Load = 5 A C1 (Blue) = VSW, C2 (Light Blue) = VOUT C3 (Magenta) = HSDR Figure 25. No Load Switching Waveforms (Vin = 16 V) Figure 26. CCM Switching Waveforms (Vin = 16 V) http://onsemi.com 10 NCP3011, NCV3011 DETAILED DESCRIPTION OVERVIEW threshold. The device remains in Standby if enable is not asserted following the 50 ms time period. The NCP3011 operates as a 400 kHz, voltage-mode, pulse-width-modulated, (PWM) synchronous buck converter. It drives high-side and low-side N-channel power MOSFETs. The NCP3011 incorporates an internal boost circuit consisting of a boost Clamp and boost diode to provide supply voltage for the high side MOSFET Gate driver. The NCP3011 also integrates several protection features including input undervoltage lockout (UVLO), output undervoltage (OUV), output overvoltage (OOV), adjustable high-side current limit (ISET and ILIM), and thermal shutdown (TSD). The NCP3011 includes a Power Good (PG) open drain output which flags out of regulation conditions. The operational transconductance amplifier (OTA) provides a high gain error signal which is compared to the internal ramp signal using the PWM comparator. This results in a voltage mode PWM feedback stage. The PWM signal is sent to the internal gate drivers to modulate MOSFET on and off times. The gate driver stage incorporates symmetrical fixed non-overlap time between the high-side and low-side MOSFET gate drives. The NCP3011 has a dual function Master/Slave SYNC pin In Slave mode, the NCP3011 synchronizes to an external clock signal. In Master mode, the NCP3011 can output a phase shifted clock signal to drive another master slave equipped power stage to provide a 180 switching relationship between the power stages. This can help to reduce the required input filter capacitance in multi-stage power converters. The external 1.25 V reference voltage (VREF) is provided for system level use. It remains active even when the NCP3011 is disabled. Enable/Disable The device has an enable pin (EN) with internal 50 mA pullup current. This gives the user the option of driving EN with a push-pull or open-drain/collector enable signal. When driving EN with an external logic supply a 10 kW series current limiting resistor must be placed in series with EN. See Figure 27. The maximum enable threshold is 3.4 V. If no external drive voltage is available, the internal pullup can be used to enable the device, and an open drain/collector input, such as a MOSFET or BJT can be used to disable the device. A capacitor connected between EN and ground can be used with the internal pullup current source to provide a fixed delay to turn-on and turn off. See Equation 1. V EN 10 kW DISABLE ENABLE EN Enable Logic - or- ENABLE DISABLE -or- ENABLE DISABLE Figure 27. Enable Circuits: Push-Pull, Open-Drain, or Open-Collector POR and UVLO The device contains an internal Power On Reset (POR) and input Undervoltage Lockout (UVLO) that inhibits the internal logic and the output stage from operating until VCC reaches their respective predefined voltage levels. The internal logic takes approximately 50 ms to check the SYNC pin and determine if the device is in Master mode or Slave mode once the voltage at VCC exceeds the rising UVLO C EN_DLY + I PU T EN_DLY V EN_TH CEN_DLY = Delay Capacitance (F) IPU = Pullup Current VEN_TH = Enable Input High Threshold Voltage TEN_DLY = Desired Delay Time http://onsemi.com 11 (eq. 1) NCP3011, NCV3011 Startup and Shutdown The soft-stop process begins once the EN pin voltage goes below the input low threshold. Soft-stop decreases the internal reference from 0.8 V - 0 V in 32 steps as with Soft-Start. Soft-Stop finishes with one "last" high side gate pulse at half the period of the prior pulse. This helps ensure positive inductor current following turn off at light loads, which prevents negative output voltage. Enable low during Soft-Start will result in Soft-Stop down counting from that step. Likewise, Enable high during Soft-Stop will result in Soft-Start up counting from that step. Once enable is asserted the device begins its startup process. Closed-loop soft-start begins after a 400 ms delay wherein the boost capacitor is charged, and the current limit threshold is set. During the 400 ms delay the OTA output is set to just below the valley voltage of the internal ramp. This is done to reduce delays and to ensure a consistent pre soft-start condition. The device increases the internal reference from 0 V to 0.8 V in 32 discrete steps while maintaining closed loop regulation at each step. Some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. See Figure 28. The total soft-start time is 5.12 ms. 0.8 V Output Voltage 25 mV Steps 32 Voltage Steps Internal Reference Voltage Internal Ramp OTA Output 0 .7V 0V Figure 28. Soft-Start Details http://onsemi.com 12 NCP3011, NCV3011 Master/Slave Synchronization (Slave Mode) or provide an external clock that is shifted by 180 from the high side switch (Master Mode). The typical application circuit for this is shown in Figure 29. The SYNC pin performs two functions. The first function is to identify if the device is a master or a slave. The second function is to either synchronize to an external clock VIN HSDR MASTER VIN SYNC 2 SYNC 1 HSDR SLAVE 60kW Figure 29. Master Slave Typical Application Upon initial power up, the device determines if it is a Master or Slave by applying 1.25 V to the SYNC pin and determining whether the current draw from the pin is greater than the Master Threshold Current (ISYNCTRIP). If ISYNCTRIP is exceeded then the device enters master mode. If the current is less than ISYNCTRIP the device enters slave mode. Once identified as a Master, the device switching frequency is increased by 15%. See Equation 2. R Master + 0-50% Duty Cycle Slave HSDRV Master Detection 0-50% Duty Cycle Hold Result Vref = 1.25 V SYNC1 Voltage Time > 40 ms Time > 40 ms Vref = 1.25 V SYNC 2 Voltage 40 ms Slave Pull Down Turn on ITRIP = 10 mA SYNC 1 Current SYNC 2 Current Indication of Master Indication of Slave ISYNC TRIP RMaster = Master Select Resistor (W) SYNCref = Sync Reference Voltage (V) ISYNCTRIP = Master Threshold Current (A) Master HSDRV Pulse Detect SYNC ref 0 mA Input Voltage Figure 30. Master Slave Typical Waveforms http://onsemi.com 13 (eq. 2) NCP3011, NCV3011 the ramp signal. The equation for calculating the remaining ramp height is shown below: The master slave identification begins when input voltage is applied prior to POR. Upon application of input voltage, the device waits for input pulses for a minimum of 40 ms as shown in Figure 30. During the pulse detection period if concurrent edges occur on the SYNC pin from an external source, the device enters slave mode and skips the master detection sequence. The device will remain in the detected state until power is cycled. V RAMP + VRAMP typ * Master Detect & Hold SYNC_out Figure 31. 400 kHz 570 kHz [ 0.70 V (eq. 3) The output voltage of the buck converter is monitored at the Feedback pin of the output power stage. Four comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figures 32 and 33. All comparator outputs are ignored during the soft-start sequence as soft-start is regulated by the OTA and false trips would be generated. Further, the Power Good pin is held low until the comparators are evaluated. After the soft-start period has ended, if the feedback is below the reference voltage of comparator 4 (0.6 < VFB), the output is considered "undervoltage," the device will initiate a restart, and the Power Good pin remains low with a 55 W pulldown resistance. If the voltage at the Feedback pin is between the reference voltages of comparator 4 and comparator 3 (0.60 < VFB < 0.72), then the output voltage is considered "power not good low" and the Power Good pin remains low. When the Feedback pin voltage rises between the reference voltages of comparator 3 and comparator 2 (0.72 < VFB < 0.88), then the output voltage is considered "Power Good" and the Power Good pin is released. If the voltage at the Feedback pin is between the reference voltages of comparator 2 and comparator 1 (0.88 < VFB < 1.00), the output voltage is considered "power not good high" and the power good pin is pulled low with a 55 W pulldown resistance. Finally, if the feedback voltage is greater than comparator 1 (1.0 < VFB), the output voltage is considered "overvoltage," the Power Good pin will remain low, and the device will latch off. To clear a latch fault, input voltage must be recycled. Graphical representation of the OOV, OUV, and Power Good pin functionality is shown in Figures 34 and 35. SYNC SYNC_in 1V* OOV, OUV, and Power Good Current Sensor 1.21 V F nom F SYNC GND External Synchronization The device can sync to frequencies that are 15% to 60% higher than the nominal switching frequency. If an external sync pulse is present at the SYNC pin prior to input voltage application to the device, then no additional external components are needed. If the external clock is not present following power on reset of the device, the voltage on the SYNC pin will determine whether the device is a master or a slave. If the external clock source is meant to start after device operation, its off state should be high or tristate. It is also important to note that the slope of the internal ramp is fixed and synchronizing to a faster clock which will truncate http://onsemi.com 14 NCP3011, NCV3011 Soft Start Complete V2 = Vref * 125% Comparator 1 V4 = Vref * 110% Comparator 2 V5 = Vref * 90% FB Power Good Restart LOGIC Comparator 3 Latch off V7= Vref * 75% Comparator 4 Vref = 0.8 V Figure 32. OOV, OUV, and Power Good Circuit Diagram Trip Level Tolerance 2% Hysteresis = 5 mV Trip Level Tolerance 2% Hysteresis = 5 mV OOVP & Power Good = 0 Voov = Vref * 125% Power Good = 0 Power Not good High Vtrip_pg = Vref * 110% Power Good = 1 Vref = 0.8 V Trip Level Tolerance 2% Hysteresis = 5 mV Trip Level Tolerance 2% Hysteresis = 5 mV Power Good = 1 Vtrip_pg = Vref * 90% Power Good = 0 Power Not Good Low Vouv = Vref * 75% OUVP & Power Good = 0 Figure 33. OOV, OUV, and Power Good Window Diagram http://onsemi.com 15 NCP3011, NCV3011 1.0 V (vref * 125 %) 0.88 V (vref * 110 %) 0.8 V ( vref * 100 %) 0.72 V (vref * 90%) 0.60 V (vref * 75%) FB Voltage Latch off Power Good Power Good Pin Reinitiate Softstart Softstart Complete Figure 34. Powerup Sequence and Overvoltage Latch 1.0 V (vref *125%) 0.88 V (vref *110%) 0.8 V (vref *100%) 0.72 V (vref *90%) 0.60 V (vref *75%) FB Voltage Latch off Power Good Power Good Reinitiate Softstart Softstart Complete Figure 35. Powerup Sequence and Undervoltage Soft-Start http://onsemi.com 16 NCP3011, NCV3011 CURRENT LIMIT AND CURRENT LIMIT SET ILimit block consists of a voltage comparator circuit which compares the differential voltage across the VCC Pin and the VSW Pin with a resistor settable voltage reference. The sense portion of the circuit is only active while the HS MOSFET is turned ON. Overview The NCP3011 uses the voltage drop across the High Side MOSFET during the on time to sense inductor current. The VIN VCC VSense Ilim Out HSDR Itrip Ref VSW Switch Cap CONTROL Iset 13 uA LSDR 6 Vset DAC / COUNTER RSet Itrip Ref-63 Steps, 6.51 mV/step Figure 36. Iset / ILimit Block Diagram Current Limit Set prior to Soft-Start, the DAC counter increments the reference on the ISET comparator until it crosses the VSET voltage and holds the DAC reference output to that count value. This voltage is translated to the ILimit comparator during the ISense portion of the switching cycle through the switch cap circuit. See Figure 36. Exceeding the maximum sense voltage results in no current limit. Steps 0 to 10 result in an effective current limit of 0 mV. The ILimit comparator reference is set during the startup sequence by forcing a typically 13 mA current through the low side gate drive resistor. The gate drive output will rise to a voltage level shown in the equation below: V set + I set * R set (eq. 4) Where ISET is 13 mA and RSET is the gate to source resistor on the low side MOSFET. This resistor is normally installed to prevent MOSFET leakage from causing unwanted turn on of the low side MOSFET. In this case, the resistor is also used to set the ILimit trip level reference through the ILimit DAC. The Iset process takes approximately 350 ms to complete prior to Soft-Start stepping. The scaled voltage level across the ISET resistor is converted to a 6 bit digital value and stored as the trip value. The binary ILimit value is scaled and converted to the analog ILimit reference voltage through a DAC counter. The DAC has 63 steps in 6.51 mV increments equating to a maximum sense voltage of 403 mV. During the Iset period Current Sense Cycle Figure 37 shows how the current is sampled as it relates to the switching cycle. Current level 1 in Figure 37 represents a condition that will not cause a fault. Current level 2 represents a condition that will cause a fault. The sense circuit is allowed to operate below the 3/4 point of a given switching cycle. A given switching cycle's 3/4 Ton time is defined by the prior cycle's Ton and is quantized in 10 ns steps. A fault occurs if the sensed MOSFET voltage exceeds the DAC reference within the 3/4 time window of the switching cycle. http://onsemi.com 17 NCP3011, NCV3011 Trip: Vsense > Itrip Ref at 3/4 Point No Trip: Vsense < Itrip Ref at 3/4 Point Itrip Ref Vsense 3/4 3/4 Current Level 1 Ton-1 Ton-2 Current Level 2 3/4 Point Determined by Prior Cycle 1/4 1/2 1/4 1/2 3/4 3/4 Ton-1 Ton Each switching cycle's Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle's limit sample time Figure 37. ILimit Trip Point Description Soft-Start Current limit Boost Clamp Functionality During soft-start the ISET value is doubled to allow for inrush current to charge the output capacitance. The DAC reference is set back to its normal value after soft-start has completed. The boost circuit requires an external capacitor connected between the BST and VSW pins to store charge for supplying the high and low-side gate driver voltage. This clamp circuit limits the driver voltage to typically 7.5 V when VIN > 9 V, otherwise this internal regulator is in dropout and typically VIN - 1.25 V. The boost circuit regulates the gate driver output voltage and acts as a switching diode. A simplified diagram of the boost circuit is shown in Figure 38. While the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the VSW is high and the linear regulator output transistor is reversed biased. VSW Ringing The ILimit block can lose accuracy if there is excessive VSW voltage ringing that extends beyond the 1/2 point of the high-side transistor on-time. Proper snubber design and keeping the ratio of ripple current and load current in the 10-30% range can help alleviate this as well. Current Limit A current limit trip results in completion of one switching cycle and subsequently half of another cycle Ton to account for negative inductor current that might have caused negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft-start time period wait passes before another soft-start cycle is attempted. VIN 8.9V Iave vs Trip Point The average load trip current versus RSET value is shown the equation below: I AveTRIP + I set R set R DS(on) * 1 V IN * V OUT 4 L Switch Sampling Circuit V OUT 1 V IN F SW BST VSW LSDR (eq. 5) Where: L = Inductance (H) ISET = 13 mA RSET = Gate to Source Resistance (W) RDS(on) = On Resistance of the HS MOSFET (W) VIN = Input Voltage (V) VOUT = Output Voltage (V) FSW = Switching Frequency (Hz) Figure 38. Boost Circuit http://onsemi.com 18 NCP3011, NCV3011 The boost ripple frequency is dependent on the output capacitance selected. The ripple voltage will not damage the device or $12 V gate rated MOSFETs. Conditions where maximum boost ripple voltage could damage the device or $12 V gate rated MOSFETs can be seen in Region 3 (Orange). Placing a boost capacitor that is no greater than 10X the input capacitance of the high side MOSFET on the boost pin limits the maximum boost voltage < 12 V. The typical drive waveforms for Regions 1, 2 and 3 (green, yellow, and orange) regions of Figure 39 are shown in Figure 40. Reduced sampling time occurs at high duty cycles where the low side MOSFET is off for the majority of the switching period. Reduced sampling time causes errors in the regulated voltage on the boost pin. High duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired DC boost voltage. Figure 39 outlines all operating regions. The recommended operating conditions are shown in Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor can be placed on the boost pin without causing damage to the device or MOSFETS. Larger boost ripple voltage occurring over several switching cycles is shown in Region 2 (Yellow). Boost Voltage Levels Normal Operation Increased Boost Ripple (Still in Specification) Increased Boost Ripple Capacitor Optimization Required 28 Region 3 26 24 In p u t V o lt a g e 22 22V 20 18 Region 2 Maxi mum Max Duty Duty Cycle Cycle Region 1 16 14 12 11.5V 10 8 71% 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Duty Cycle Figure 39. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor http://onsemi.com 19 NCP3011, NCV3011 VIN 7.5V VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Figure 40. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom) To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 41. http://onsemi.com 20 NCP3011, NCV3011 Boost Voltage 18 Voltage Ripple Maximum Allowable Voltage Maximum Boost Voltage 16 14 Boost Voltage (V) 12 10 8 6 4 2 0 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 Input Voltage (V) 20.5 22.5 24.5 26.5 (Clarity on Boost Max and Ripple Def) Figure 41. Boost Voltage at 80% Duty Cycle Inductor Selection D+ When selecting the inductor, it is important to know the input and output requirements. Some example conditions are listed below to assist in the process. V OUT ) V LSD V IN * V HSD ) V LSD 27.5% + Table 1. DESIGN PARAMETERS Design Parameter (VIN) 9 V to 18 V Nominal Input Voltage (VIN) 12 V (VOUT) 3.3 V Output Voltage Input ripple voltage (VINRIPPLE) 300 mV (VOUTRIPPLE) 50 mV Output current rating (IOUT) 8A Operating frequency (Fsw) 400 kHz D+ T ON T 1 T (* D + L+ + T 12 V DI (eq. 9) I OUT V OUT I OUT @ ra @ F SW @ (1 * D) 3.3 mH 3.3 V 8 A @ 23% @ 400 kHz (eq. 10) @ (1 * 27.5%) The relationship between ra and L for this design example is shown in Figure 42. (eq. 6) T OFF (eq. 8) The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. When using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, acceptable values of inductance for a design can be calculated using Equation 10. A buck converter produces input voltage (VIN) pulses that are LC filtered to produce a lower dc output voltage (VOUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty cycle (D). Duty cycle can also be calculated using VOUT, VIN, the low side switch voltage drop VLSD, and the High side switch voltage drop VHSD. F+ V IN 3.3 V ra + Output ripple voltage V OUT The ratio of ripple current to maximum output current simplifies the equations used for inductor selection. The formula for this is given in Equation 9. Example Value Input Voltage [D+ (eq. 7) http://onsemi.com 21 L, INDUCTANCE (mH) NCP3011, NCV3011 18 17 16 18 V 15 14 15 V 13 12 11 10 12 V 9 8 7 6 5 4 9V 3 2 1 0 10% 15% 20% 25% VIN, (V) I PP + Vout = 3.3 V 30% 35% 40% LP CU + I RMS 2 @ DCR +8A@ I PK + I OUT @ 1 ) 2 1 ) (0.23) 12 LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 16) (eq. 11) 2 Input Capacitor Selection ra 8.92 A + 8 A @ 1 ) 2 (0.23) 2 The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: (eq. 12) Iin RMS + I OUT @ D @ (1 * D) An inductor for this example would be around 3.3 mH and should support an rms current of 8.02 A and a peak current of 8.92 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 13. SlewRate LOUT + V IN * V OUT L OUT 2.6 (eq. 15) The core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: To keep within the bounds of the parts maximum rating, calculate the RMS current and peak current. 1 ) ra12 8.02 A (eq. 14) L OUT @ F SW Ipp is the peak to peak current of the inductor. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. The power dissipation of an inductor consists of both copper and core losses. The copper losses can be further categorized into dc losses and ac losses. A good first order approximation of the inductor losses can be made using the DC resistance as they usually contribute to 90% of the losses of the inductor shown below: Figure 42. Ripple Current Ratio vs. Inductance I RMS + I OUT @ V OUT(1 * D) (eq. 17) D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + ESR CIN @ I IN*RMS 2 (eq. 18) PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur. 12 V * 3.3 V A + ms 3.3 mH (eq. 13) Input Start-up Current This equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak-to-peak ripple current for the NCP3011 is given by the following equation: To calculate the input startup current, the following equation can be used. I INRUSH + C OUT @ V OUT t SS (eq. 19) Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. http://onsemi.com 22 NCP3011, NCV3011 Output Capacitor Selection In a typical converter design, the ESR of the output capacitor bank dominates the transient response. It should be noted that DVOUT-DISCHARGE and DVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. The ESR contribution from Equation 21 still applies in addition to the output capacitor charge which is approximated by the following equation: The important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: ra Co RMS + I O @ 12 2 DV OUT-CHG + (eq. 20) The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (ESL) and ESR. The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected. V ESR_C + I O @ ra @ ESR Co ) 1 8 @ F SW @ Co ESL @ I PP @ F SW V ESLOFF + D ESL @ I PP @ F SW (1 * D ) Power dissipation, package size, and the thermal environment drive MOSFET selection. To adequately select the correct MOSFETs, the design must first predict its power dissipation. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or high-side MOSFET will display both switching and conduction losses. The synchronous or low-side MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. Starting with the high-side or control MOSFET, the power dissipation can be approximated from: (eq. 21) (eq. 22) P D_CONTROL + P COND ) P SW_TOT (eq. 23) 2 P COND + I RMS_CONTROL @ R DS(on)_CONTROL (eq. 28) Using the ra term from Equation 9, IRMS becomes: I RMS_CONTROL + I OUT @ C OUT @ V IN * V OUT ra12 D@ 1) 2 P SW_TOT + P SW ) P DS ) P RR (eq. 24) (eq. 29) (eq. 30) The first term for total switching losses from Equation 30 includes the losses associated with turning the control MOSFET on and off and the corresponding overlap in drain voltage and current. P SW + P TON ) P TOFF 2 DV OUT-DISCHG + The second term from Equation 27 is the total switching loss and can be approximated from the following equations. A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is approximated by the following equation: I TRAN @ LOUT (eq. 27) The first term is the conduction loss of the high-side MOSFET while it is on. The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the effective series inductance (ESL)). DV OUT-ESR + DI TRAN @ ESR Co (eq. 26) C OUT @ V OUT Power MOSFET Selection The ESL of capacitors depends on the technology chosen but tends to range from 1 nH to 20 nH where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: V ESLON + I TRAN @ LOUT + 1 @ I OUT @ V IN @ f SW @ t ON ) t OFF 2 (eq. 25) http://onsemi.com 23 (eq. 31) NCP3011, NCV3011 where: t ON + Q GD I G1 + Q GD V BST * V THR HSPU ) R G IG1: output current from the high-side gate drive (HSDR) IG2: output current from the low-side gate drive (LSDR) SW: switching frequency of the converter. VBST: gate drive voltage for the high-side drive, typically 7.5 V. QGD: gate charge plateau region, commonly specified in the MOSFET datasheet VTH: gate-to-source voltage at the gate charge plateau region QOSS: MOSFET output gate charge specified in the data sheet QRR: reverse recovery charge of the low-side or synchronous MOSFET, specified in the datasheet RDS(on)_CONTROL: on resistance of the high-side, or control, MOSFET RDS(on)_SYNC: on resistance of the low-side, or synchronous, MOSFET NOLLH: dead time between the LSDR turning off and the HSDR turning on, typically 85 ns NOLHL: dead time between the HSDR turning off and the LSDR turning on, typically 75 ns (eq. 32) and: t OFF + Q GD I G2 + Q GD V BST * V THR HSPD ) R G (eq. 33) Next, the MOSFET output capacitance losses are caused by both the control and synchronous MOSFET but are dissipated only in the control MOSFET. P DS + 1 @ Q OSS @ V IN @ f SW 2 (eq. 34) Finally the loss due to the reverse recovery time of the body diode in the synchronous MOSFET is shown as follows: P RR + Q RR @ V IN @ f SW (eq. 35) The low-side or synchronous MOSFET turns on into zero volts so switching losses are negligible. Its power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non-overlap periods. P D_SYNC + P COND ) P BODY Once the MOSFET power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is: (eq. 36) Conduction loss in the low-side or synchronous MOSFET is described as follows: 2 P COND + I RMS_SYNC @ R DS(on)_SYNC (eq. 37) where: I RMS_SYNC + I OUT @ T J + T A ) P D @ R qJA ra 2 ( 1 * D) @ 1 ) 12 TJ: Junction Temperature TA: Ambient Temperature PD: Power Dissipation of the MOSFET under analysis RqJA: Thermal Resistance Junction-to-Ambient of the MOSFET's package (eq. 38) The body diode losses can be approximated as: P BODY + V FD @ I OUT @ f SW @ NOL LH ) NOL HL (eq. 39) As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Vth Figure 43. MOSFET Switching Characteristics http://onsemi.com 24 NCP3011, NCV3011 NOLHL NOLLH High-Side Logic Signal Low-Side Logic Signal td(on) tf RDSmax High-Side MOSFET RDS(on)min tr td(off) tr tf RDSmax Low-Side MOSFET RDS(on)min td(on) td(off) Figure 44. MOSFETs Timing Diagram response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows: Another consideration during MOSFET selection is their delay times. Turn-on and turn-off times must be short enough to prevent cross conduction. If not, there will be conduction from the input through both MOSFETs to ground. Therefore, the following conditions must be met. t d(ON)_CONTROL ) NOL LH u t d(OFF)_SYNC ) t f_SYNC f P0 + (eq. 40) and t (ON)_SYNC ) NOL HL u t d(OFF)_CONTROL ) t f _CONTROL 1 2 @ p @ L @ C OUT (eq. 41) Parasitic Equivalent Series Resistance (ESR) of the output filter capacitor introduces a high frequency zero to the filter network. Its value can be calculated by using the following equation: The MOSFET parameters, td(ON), tr, td(OFF) and tf are can be found in their appropriate datasheets for specific conditions. NOLLH and NOLHL are the dead times which were described earlier and are 85 ns and 75 ns, respectively. f Z0 + Feedback and Compensation The NCP3011 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient 1 2 @ p @ C OUT @ ESR (eq. 42) The main loop zero crossover frequency f0 can be chosen to be 1/10 - 1/5 of the switching frequency. Table 2 shows the three methods of compensation. Table 2. COMPENSATION TYPES Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic http://onsemi.com 25 NCP3011, NCV3011 Compensation Type II This compensation is suitable for electrolytic capacitors. Components of the Type II compensation (Figure 45) network can be specified by the following equations: f Z1 + 0.75 @ f P0 (eq. 47) f Z2 + f P0 (eq. 48) f P2 + f Z0 (eq. 49) fS f P3 + (eq. 50) 2 Method II is better suited for ceramic capacitors that typically have the lowest ESR available: Figure 45. Type II Compensation R C1 + 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 (eq. 44) C C2 + 1 p @ R C1 @ f S (eq. 45) R1 + V OUT * V ref V ref @ R2 sinq max 11 )* sin q max (eq. 51) f P2 + f 0 @ sin q max 11 *) sin q max (eq. 52) f Z1 + 0.5 @ f Z2 (eq. 53) f P3 + 0.5 @ f S (eq. 54) qmax is the desired maximum phase margin at the zero crossover frequency, 0. It should be 45 - 75. Convert degrees to radians by the formula: (eq. 43) C C1 + f Z2 + f 0 @ q max + q max degress @ 2 @ p : Units + radians 360 (eq. 55) The remaining calculations are the same for both methods. R C1 u u (eq. 46) VRAMP is the peak-to-peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional. Compensation Type III 1 2 @ p @ f Z1 @ R C1 (eq. 57) C C2 + 1 2 @ p @ f P3 @ R C1 (eq. 58) R FB1 + R1 + R2 + (eq. 56) C C1 + C FB1 + Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This requires a Type III compensation network as shown in Figure 46. There are two methods to select the zeros and poles of this compensation network. Method I is ideal for tantalum output capacitors, which have a higher ESR than ceramic: 2 gm 2 @ p @ f 0 @ L @ V RAMP @ C OUT V IN @ R C1 1 2p @ C FB1 @ f P2 (eq. 60) 1 * R FB1 2 @ p @ C FB1 @ f Z2 V ref V OUT * V ref (eq. 59) (eq. 61) @ R1 (eq. 62) If the equation in Equation 63 is not true, then a higher value of RC1 must be selected. R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2 Figure 46. Type III Compensation http://onsemi.com 26 u 1 (eq. 63) gm NCP3011, NCV3011 TYPICAL APPLICATION CIRCUIT 9-16 V C IN-1/2 CIN-3/4 CIN-5 C BST COMP RC C c1 NCP3011 VCC HSDR D1 RG Q1 RGS 3.3 uH 3.3 V VSW Q2 LSDR FB C c2 BST RFB1 C FB R ISET GND R FB3 R FB2 Figure 47. Typical Application, VIN = 9 - 16 V, VOUT = 3.3 V, IOUT = 6 A Reference Designator Value CIN-1 470 mF CIN-2 470 mF CIN-3 22 mF CIN-4 22 mF CIN-5 1 mF CC1 56 pF CC2 12 nF CFB 1.0 nF COUT1 470 mF COUT2 22 mF COUT3 22 mF CBST 0.1 mF RC 4.81 kW RG 0W RGS 1.0 kW RISET 22.1 kW RFB1 3.16 kW RFB2 1.0 kW RFB3 1.0 kW Q1 NTMS4816N Q2 NTMS4816N D1 BAT54 http://onsemi.com 27 C OUT -1 C OUT -2/3 NCP3011, NCV3011 PACKAGE DIMENSIONS TSSOP-14 CASE 948G-01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S S DETAIL E K A -V- EEE CCC CCC EEE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 28 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP3011/D