NCV3011DTBR2G - ON Semiconductor L.L.C.

June, 2011 − Rev. 3

1Publication Order Number:

NCP3011/D

NCP3011, NCV3011

Synchronous PWM Controller

The NCP3011 is a PWM device designed to operate from a wide

input range and is capable of producing an output voltage as low as

0.8 V. The NCP3011 provides integrated gate drivers and an internally

set 400 kHz oscillator. The NCP3011 has an externally compensated

transconductance error amplifier with an internally fixed soft−start.

The NCP3011 incorporates output voltage monitoring with a Power

Good pin to indicate that the system is in regulation. The dual function

SYNC pin synchronizes the device to a higher frequency (Slave

Mode) or outputs a 180° out−of−phase clock signal to drive another

NCP3011 (Master Mode). Protection features include lossless current

limit and short circuit protection, output overvoltage and undervoltage

protection, and input undervoltage lockout. The NCP3011 is available

in a 14−pin TSSOP package.

Features

•Input Voltage Range from 4.7 V to 28 V

•400 kHz Operation

•0.8 V $1.0% Reference Voltage

•Buffered External +1.25 V Reference

•Current Limit and Short Circuit Protection

•Power Good

•Enable/Disable Pin

•Input Undervoltage Lockout

•External Synchronization

•Output Overvoltage and Undervoltage Protection

•NCV Prefix for Automotive and Other Applications Requiring Site

and Change Controls

•This is a Pb−Free Device

Typical Applications

•Set Top Box

•Power Modules

•ASIC / DSP Power Supply

VIN

VCC BST

HSDR

VSW

LSDR

GND

COMP

VREF

SYNC

CBST

RISET

RFB1

CC2

CIN

CC1

RFB2

VOUT

RREF

CREF

Figure 1. Typical Application Circuit

TSSOP−14

DT SUFFIX

CASE 948G

MARKING DIAGRAM

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3011= Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

3011

ALYWG

VREF

SYNC

COMP

HSDR

VCC

BST

VSW

LSDR

GND

PIN CONNECTIONS

(TOP VIEW)

Device Package Shipping†

ORDERING INFORMATION

NCP3011DTBR2G TSSOP−14

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

(Note: Microdot may be in either location)

NCV3011DTBR2G TSSOP−14

(Pb−Free)

2500 / Tape & Reel

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GATE

DRIVE

LOGIC

CLK/

DMAX/

SOFT

START

OOV

BOOST

CLAMP

LEVEL

SHIFT

SAMPLE &

HOLD

HSDR

LSDR

GND

−

VCC

COMP

REF

RAMP

OSCILLATOR

BST

VSW

VCC

Figure 2. NCP3011 Block Diagram

SYNC

VREF

INTERNAL BIAS

ISET

1.5 V

BST_CHRG

ENABLE/

POWER GOOD

LOGIC THERMAL SD

POR/STARTUP

1.25 V

REFERENCE

OTA

PWM

COMP

OUV

CURRENT

LIMIT

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PIN FUNCTION DESCRIPTION

Pin Pin Name Description

1 VREF The VREF pin is the output for a 1.25 V reference (1 mA max). A 100 kW resistor in parallel with a 1 mF

ceramic capacitor must be connected from this pin to GND to ensure external reference stability.

2 EN The EN pin is the enable/disable input. A logic high on this pin enables the device. This pin has also an internal

current source pull up. A 10 kW resistor should be connected in series with this pin if VEN is externally biased

from a separate supply.

3 NC Not Connected

4 SYNC The dual function SYNC pin synchronizes the device to a higher frequency (Slave Mode). Alternately, it outputs

a 456 kHz clock signal with 180° of phase shift (Master Mode). Connect a 100 kW resistor from SYNC to GND

to enable Master Mode. No resistor is required for Slave Mode.

5 PG The Power Good pin is an open drain output that is low when the regulated output voltage is beyond the

“Power Good” upper and lower thresholds. Otherwise, it is a high impedance pin.

6 COMP The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive

terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage

mode control feedback loop.

7 FB The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to

compensate the voltage mode control feedback loop.

8 GND Ground Pin

9 LSDR The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side

N−FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR

to GND.

10 NC Not Connected

11 VSW The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense

current in the high side MOSFET.

12 HSDR The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side

N−FET.

13 BST The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the

VSW pin.

14 VCC The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current

in the high side MOSFET.

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ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted)

Rating Symbol VMAX VMIN Unit

High Side Drive Boost Pin BST 45 −0.3 V

Boost to VSW differential voltage BST−VSW 13.2 −0.3 V

COMP COMP 5.5 −0.3 V

Enable EN 5.5 −0.3 V

Feedback FB 5.5 −0.3 V

High−Side Driver Output HSDR 40 −0.3 V

Low−Side Driver Output LSDR 13.2 −0.3 V

Power Good PG 5.5 −0.3 V

Synchronization SYNC 5.5 −0.3 V

Main Supply Voltage Input VCC 40 −0.3 V

External Reference VREF 5.5 −0.3 V

Switch Node Voltage VSW 40 −0.6 V

Maximum Average Current

VCC, BST, HSDRV, LSDRV, VSW, GND

REF

SYNC

Imax 130

7.1

2.5

Operating Junction Temperature Range (Note 1) TJ−40 to +140 °C

Maximum Junction Temperature TJ(MAX) +150 °C

Storage Temperature Range Tstg −55 to +150 °C

Thermal Characteristics (Note 2)

TSSOP−14 Plastic Package

Thermal Resistance Junction−to−Air RqJA 190 °C/W

Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free

(Note 3)

RF260 Peak °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The maximum package power dissipation limit must not be exceeded.

PD+

TJ(max) *TA

RqJA

2. When mounted on minimum recommended FR−4 or G−10 board

3. 60−180 seconds minimum above 237°C.

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)

Characteristic Conditions Min Typ Max Unit

Input Voltage Range −4.7 28 V

SUPPLY CURRENT

Quiescent Supply Current EN = 0 VCC = 12 V −2.5 4.0 mA

VCC Supply Current VFB = 0.75 V, Switching, VCC = 4.7 V −5.8 8.0 mA

VCC Supply Current VFB = 0.75 V, Switching, VCC = 28 V −6.0 12 mA

UNDER VOLTAGE LOCKOUT

UVLO Rising Threshold VCC Rising Edge 3.8 4.3 4.7 V

UVLO Falling Threshold VCC Falling Edge 3.6 4.0 4.3 V

OSCILLATOR

Oscillator Frequency TJ = +25°C, 4.7 V v VCC v 28 V 350 400 450 kHz

TJ = −40°C to +125°C, 4.7 V v VCC v 28 V 330 400 470 kHz

Ramp−Amplitude Voltage Vpeak − Valley −1.5 −V

Ramp Valley Voltage 0.44 0.7 0.96 V

PWM

Minimum Duty Cycle −7−%

Maximum Duty Cycle 80 83 −%

Soft Start Ramp Time VFB = VCOMP −5.2 −ms

EXTERNAL VOLTAGE REFERENCE

VREF Voltage IREF = 1 mA 1.14 1.25 1.35 V

VREF Line Regulation VCC = 4.7 V − 28 V −1−+1 %

VREF Load Regulation IREF = 0 mA to 1.5 mA −2−0.2 +2 %

Short Circuit Output Current VREF = 0 V 4.5 5.7 7.0 mA

ENABLE

Enable Threshold High − − 3.4 V

Enable Threshold Low 1.0 − − V

Enable Source Current 20 50 90 mA

POWER GOOD

Power Good High Threshold VCC = 12 V 0.72 0.89 1.06 V

Power Good Low Threshold VCC = 12 V 0.65 0.71 0.75 V

Power Good Low Voltage VCC = 12 V, IPG = 4 mA 0.13 0.22 0.35 V

SYNC

SYNC Input High Threshold − − 2.0 V

SYNC Output High 10 mA load −5.0 −V

SYNC Output Low −90 −mV

Phase Delay (Note 4) −200 −°

SYNC Drive Current (Sourcing) −1.6 −mA

Master Threshold Current 5.0 14.4 25 mA

Master Frequency 390 466 550 kHz

4. Guaranteed by design.

5. The voltage sensed across the high side MOSFET during conduction.

6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW.

7. This is not a protection feature.

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)

Characteristic UnitMaxTypMinConditions

ERROR AMPLIFIER (GM)

Transconductance 0.9 1.33 1.9 mS

Open Loop dc Gain (Notes 4 and 6) −70 −dB

Output Source Current

Output Sink Current

100

FB Input Bias Current −0.5 500 nA

Feedback Voltage TJ = 25 C

−40°C < TJ < +125°C,

4.7 V < VIN < 28 V

0.792

0.788

0.8

0.808

0.812

COMP High Voltage VFB = 0.75 V 4.0 4.4 5.0 V

COMP Low Voltage VFB = 0.85 V −60 −mV

OUTPUT VOLTAGE FAULTS

Feedback OOV Threshold 0.9 1.0 1.1 V

Feedback OUV Threshold 0.55 0.59 0.65 V

OVER CURRENT

ISET Source Current 7.0 14 18 mA

Current Limit Set Voltage (Note 5) RSET = 22.2 kW140 240 360 mV

GATE DRIVERS AND BOOST CLAMP

HSDRV Pullup Resistance VCC = 8 V and VBST = 7.5 V

VSW = GND

100 mA out of HSDR pin

4.0 10.5 20 W

HSDRV Pulldown Resistance VCC = 8 V and VBST = 7.5 V

VSW = GND

100 mA into HSDR pin

2.5 5.0 11.5 W

LSDRV Pullup Resistance VCC = 8 V and VBST = 7.5 V

VSW = GND

100 mA out of LSDR pin

3.0 8.9 16 W

LSDRV Pulldown Resistance VCC = 8 V and VBST = 7.5 V

VSW = GND

100 mA into LSDR pin

1.0 2.8 6.0 W

HSDRV falling to LSDRV Rising

Delay

VCC and VBST = 8 V 50 85 110 ns

LSDRV Falling to HSDRV Rising

Delay

VCC and VBST = 8 V 60 85 120 ns

Boost Clamp Voltage VIN = 12 V, VSW = GND, VCOMP = 1.3 V 5.5 7.5 9.6 V

THERMAL SHUTDOWN

Thermal Shutdown (Notes 4 and 7) −150 −°C

Hysteresis (Notes 4 and 7) −15 −°C

4. Guaranteed by design.

5. The voltage sensed across the high side MOSFET during conduction.

6. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW.

7. This is not a protection feature.

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. Efficiency vs. Output Current and Input

Voltage

Figure 4. Load Regulation vs. Input Voltage

Figure 5. Feedback Reference Voltage vs. Input

Voltage and Temperature

Figure 6. Switching Frequency vs. Input Voltage

and Temperature

Iout (A)

63210

EFFICIENCY (%)

Iout (A)

63210

3.31

3.32

3.33

3.34

3.35

Vout (V)

TEMPERATURE (°C)

125110505−40

792

794

796

798

800

802

806

VFB (mV)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

TEMPERATURE (°C)

125110505−40

340

360

380

400

420

440

460

fSW (kHz)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

16 V

12 V

9 V

16 V

12 V

9 V

Vin = 5 V

Typical Application Circuit

Figure 47

Typical Application Circuit

Figure 47

Figure 7. Supply Current vs. Input Voltage and

Temperature

Figure 8. Supply Current (Disabled) vs. Input

Voltage and Temperature

TEMPERATURE (°C)

125110505−40

4.0

4.5

5.0

5.5

6.0

6.5

CC,

SWITCHING (

Vin = 28 V

−25 −10 20 35 65 80 95

7.0

Vin = 12 V

Vin = 5 V

804

TEMPERATURE (°C)

125110505−40

1.0

1.2

1.4

1.6

1.8

2.0

ICC, DISABLED (mA)

Vin = 28 V

−25 −10 20 35 65 80 95

2.2 Vin = 12 V

Vin = 5 V

2.4

2.6

2.8

3.0

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. Transconductance vs. Input Voltage and

Temperature

Figure 10. Input Undervoltage Lockout vs.

Temperature

Figure 11. Output Voltage Thresholds vs. Input

Voltage and Temperature

TEMPERATURE (°C)

125110505−40

1.24

1.255

1.27

1.285

1.30

1.315

1.33

gm (mS)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

1.345

1.36

1.375

1.39

TEMPERATURE (°C)

110505−40

3.9

4.0

4.1

4.2

4.3

4.4

UVLO (V)

UVLO Rising Threshold

−25 −10 20 35 65 80 95

TEMPERATURE (°C)

125110505−40

500

600

700

800

THRESHOLD VOLTAGE (mV)

−25 −10 20 35 65 80 95

900

1100

UVLO Falling Threshold

PG_Upper, Vin = 5 − 28 V

PG_Lower, Vin = 5 − 28 V

Figure 12. Power Good Output Low Voltage vs.

Input Voltage and Temperature

TEMPERATURE (°C)

110505−40

150

175

200

225

250

275

300

VPG (mV)

Vin = 5, 12, 28 V

−25 −10 20 35 65 80 95

IPG = 4 mA

Figure 13. Enable Thresold vs. Input Voltage and

Temperature

Figure 14. Enable Pullup Current vs. Input Voltage

and Temperature

1000 325

350

TEMPERATURE (°C)

125110505−40

1.0

1.25

1.5

1.75

2.0

2.25

2.5

VEN (V)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

2.75

3.0

3.25

3.5

Rising Threshold

Falling Threshold

Vin = 12 V, 28 V

Vin = 5 V

TEMPERATURE (°C)

125110505−40

IEN (mA)

Vin = 5, 12, 28 V

−25 −10 20 35 65 80 95

OOV, Vin = 5 − 28 V

OUV, Vin = 5 − 28 V

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 15. SYNC Threshold vs. Input Voltage and

Temperature

TEMPERATURE (°C)

125110505−40

1.0

1.2

1.4

1.6

1.8

2.0

VSYNC (V)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

Figure 16. Valley Voltage vs. Input Voltage and

Temperature

TEMPERATURE (°C)

125110505−40

400

450

500

550

600

650

700

VALLEY VOLTAGE (mV)

−25 −10 20 35 65 80 95

750

800

850

900

Vin = 5 − 28 V

950

1000

Input = 16 V, Output = 3.3 V, Load = 5 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = Power Good, C4 (Green) = Enable

Figure 17. External Reference Voltage vs. Input

Voltage and Temperature

TEMPERATURE (°C)

125110505−40

1.23

1.235

1.24

1.245

1.25

1.255

1.26

VREFE (V)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

Figure 18. External Reference Voltage vs. Input

Voltage and Temperature

Figure 19. Soft−Start Waveforms Figure 20. Soft−Stop Waveforms

TEMPERATURE (°C)

125110505−40

−1.0

−0.8

−0.6

−0.4

−0.2

0.2

VREFE_load−reg (%)

−25 −10 20 35 65 80 95

0.4

0.6

0.8

1.0

Vin = 5 V

Vin = 12 V, 28 V

Input = 16 V, Output = 3.3 V, Load = 5 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = Power Good, C4 (Green) = Enable

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 21. Soft−Start Time vs. Input Voltage and

Temperature Figure 22. Current Limit Set Current vs.

Temperature

Figure 23. No Load Switching Waveforms

(Vin = 9 V)

Figure 24. CCM Switching Waveforms

(Vin = 9 V)

Figure 25. No Load Switching Waveforms

(Vin = 16 V)

TEMPERATURE (°C)

125110505−40

5.0

5.2

5.4

5.6

5.8

6.0

tSoft−Start (ms)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

TEMPERATURE (°C)

125110505−40

13.0

13.2

13.4

13.6

13.8

14.0

ISET (mA)

Vin = 12 V, 28 V

−25 −10 20 35 65 80 95

Vin = 5 V

Input = 9 V, Output = 3.3 V, Load = 0 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = HSDR

Figure 26. CCM Switching Waveforms

(Vin = 16 V)

Input = 9 V, Output = 3.3 V, Load = 5 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = HSDR

Input = 16 V, Output = 3.3 V, Load = 0 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = HSDR

Input = 16 V, Output = 3.3 V, Load = 5 A

C1 (Blue) = VSW, C2 (Light Blue) = VOUT

C3 (Magenta) = HSDR

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DETAILED DESCRIPTION

OVERVIEW

The NCP3011 operates as a 400 kHz, voltage−mode,

pulse−width−modulated, (PWM) synchronous buck

converter. It drives high−side and low−side N−channel

power MOSFETs. The NCP3011 incorporates an internal

boost circuit consisting of a boost Clamp and boost diode to

provide supply voltage for the high side MOSFET Gate

driver. The NCP3011 also integrates several protection

features including input undervoltage lockout (UVLO),

output undervoltage (OUV), output overvoltage (OOV),

adjustable high−side current limit (ISET and ILIM), and

thermal shutdown (TSD). The NCP3011 includes a

Power Good (PG) open drain output which flags out of

regulation conditions.

The operational transconductance amplifier (OTA)

provides a high gain error signal which is compared to the

internal ramp signal using the PWM comparator. This

results in a voltage mode PWM feedback stage. The PWM

signal is sent to the internal gate drivers to modulate

MOSFET on and off times. The gate driver stage

incorporates symmetrical fixed non−overlap time between

the high−side and low−side MOSFET gate drives.

The NCP3011 has a dual function Master/Slave SYNC

pin In Slave mode, the NCP3011 synchronizes to an external

clock signal. In Master mode, the NCP3011 can output a

phase shifted clock signal to drive another master slave

equipped power stage to provide a 180° switching

relationship between the power stages. This can help to

reduce the required input filter capacitance in multi−stage

power converters.

The external 1.25 V reference voltage (VREF) is

provided for system level use. It remains active even when

the NCP3011 is disabled.

POR and UVLO

The device contains an internal Power On Reset (POR)

and input Undervoltage Lockout (UVLO) that inhibits the

internal logic and the output stage from operating until VCC

reaches their respective predefined voltage levels. The

internal logic takes approximately 50 ms to check the SYNC

pin and determine if the device is in Master mode or Slave

mode once the voltage at VCC exceeds the rising UVLO

threshold. The device remains in Standby if enable is not

asserted following the 50 ms time period.

Enable/Disable

The device has an enable pin (EN) with internal 50 mA

pullup current. This gives the user the option of driving EN

with a push−pull or open−drain/collector enable signal.

When driving EN with an external logic supply a 10 kW

series current limiting resistor must be placed in series with

EN. See Figure 27. The maximum enable threshold is 3.4 V.

If no external drive voltage is available, the internal pullup

can be used to enable the device, and an open drain/collector

input, such as a MOSFET or BJT can be used to disable the

device. A capacitor connected between EN and ground can

be used with the internal pullup current source to provide a

fixed delay to turn−on and turn off. See Equation 1.

DISABLE ENABLE EN

VEN

−or−

DISABLEENABLE

10 kWEnable

Logic

Figure 27. Enable Circuits: Push−Pull, Open−Drain,

or Open−Collector

CEN_DLY +

IPU TEN_DLY

VEN_TH

(eq. 1)

CEN_DLY = Delay Capacitance (F)

IPU = Pullup Current

VEN_TH = Enable Input High Threshold Voltage

TEN_DLY = Desired Delay Time

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Startup and Shutdown

Once enable is asserted the device begins its startup

process. Closed−loop soft−start begins after a 400 ms delay

wherein the boost capacitor is charged, and the current limit

threshold is set. During the 400 ms delay the OTA output is

set to just below the valley voltage of the internal ramp. This

is done to reduce delays and to ensure a consistent pre

soft−start condition. The device increases the internal

reference from 0 V to 0.8 V in 32 discrete steps while

maintaining closed loop regulation at each step. Some

overshoot may be evident at the start of each step depending

on the voltage loop phase margin and bandwidth. See

Figure 28. The total soft−start time is 5.12 ms.

The soft−stop process begins once the EN pin voltage

goes below the input low threshold. Soft−stop decreases the

internal reference from 0.8 V − 0 V in 32 steps as with

Soft−Start. Soft−Stop finishes with one “last” high side gate

pulse at half the period of the prior pulse. This helps ensure

positive inductor current following turn off at light loads,

which prevents negative output voltage.

Enable low during Soft−Start will result in Soft−Stop

down counting from that step. Likewise, Enable high during

Soft−Stop will result in Soft−Start up counting from that

step.

Figure 28. Soft−Start Details

Internal Reference Voltage

25 mV Steps

0.8 V

0 .7V

OTA Output

Internal Ramp

Output Voltage

32 Voltage Steps

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Master/Slave Synchronization

The SYNC pin performs two functions. The first function

is to identify if the device is a master or a slave. The second

function is to either synchronize to an external clock

(Slave Mode) or provide an external clock that is shifted by

180° from the high side switch (Master Mode). The typical

application circuit for this is shown in Figure 29.

SYNC 1

VIN

MASTER SYNC 2

VIN

SLAVE

60kW

HSDR HSDR

Figure 29. Master Slave Typical Application

Upon initial power up, the device determines if it is a

Master or Slave by applying 1.25 V to the SYNC pin and

determining whether the current draw from the pin is greater

than the Master Threshold Current (ISYNCTRIP). If

ISYNCTRIP is exceeded then the device enters master mode.

If the current is less than ISYNCTRIP the device enters slave

mode. Once identified as a Master, the device switching

frequency is increased by 15%. See Equation 2.

RMaster +

SYNCref

ISYNCTRIP

(eq. 2)

RMaster = Master Select Resistor (W)

SYNCref = Sync Reference Voltage (V)

ISYNCTRIP = Master Threshold Current (A)

Figure 30. Master Slave Typical Waveforms

Master

HSDRV

Slave

HSDRV

SYNC1

Voltage

SYNC 2

Voltage

SYNC 1

Current

SYNC 2

Current

Time > 40 ms

Vref = 1.25 V

ITRIP = 10 mA

0 mA

0−50%

Duty

Cycle

Indication

of Master

Indication

of Slave

Vref = 1.25 V

Pulse

Detect

Master

Detection

Time > 40 ms

Hold

Result

40 ms

0−50%

Duty

Cycle

Slave Pull

Down Turn on

Input

Voltage

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The master slave identification begins when input voltage

is applied prior to POR. Upon application of input voltage,

the device waits for input pulses for a minimum of 40 ms as

shown in Figure 30. During the pulse detection period if

concurrent edges occur on the SYNC pin from an external

source, the device enters slave mode and skips the master

detection sequence. The device will remain in the detected

state until power is cycled.

GND

SYNC

1.21 V

Master

Detect

Hold

Current

Sensor

Figure 31.

SYNC_in

SYNC_out

External Synchronization

The device can sync to frequencies that are 15% to 60%

higher than the nominal switching frequency. If an external

sync pulse is present at the SYNC pin prior to input voltage

application to the device, then no additional external

components are needed. If the external clock is not present

following power on reset of the device, the voltage on the

SYNC pin will determine whether the device is a master or

a slave. If the external clock source is meant to start after

device operation, its off state should be high or tristate. It is

also important to note that the slope of the internal ramp is

fixed and synchronizing to a faster clock which will truncate

the ramp signal. The equation for calculating the remaining

ramp height is shown below:

VRAMP +VRAMPtyp *Fnom

FSYNC

³1V*400 kHz

570 kHz [0.70 V

(eq. 3)

OOV, OUV, and Power Good

The output voltage of the buck converter is monitored at

the Feedback pin of the output power stage. Four

comparators are placed on the feedback node of the OTA to

monitor the operating window of the feedback voltage as

shown in Figures 32 and 33. All comparator outputs are

ignored during the soft−start sequence as soft−start is

regulated by the OTA and false trips would be generated.

Further, the Power Good pin is held low until the

comparators are evaluated. After the soft−start period has

ended, if the feedback is below the reference voltage of

comparator 4 (0.6 < VFB), the output is considered

“undervoltage,” the device will initiate a restart, and the

Power Good pin remains low with a 55 W pulldown

resistance. If the voltage at the Feedback pin is between the

reference voltages of comparator 4 and comparator 3 (0.60

< VFB < 0.72), then the output voltage is considered “power

not good low” and the Power Good pin remains low. When

the Feedback pin voltage rises between the reference

voltages of comparator 3 and comparator 2 (0.72 < VFB <

0.88), then the output voltage is considered “Power Good”

and the Power Good pin is released. If the voltage at the

Feedback pin is between the reference voltages of

comparator 2 and comparator 1 (0.88 < VFB < 1.00), the

output voltage is considered “power not good high” and the

power good pin is pulled low with a 55 W pulldown

resistance. Finally, if the feedback voltage is greater than

comparator 1 (1.0 < VFB), the output voltage is considered

“overvoltage,” the Power Good pin will remain low, and the

device will latch off. To clear a latch fault, input voltage must

be recycled. Graphical representation of the OOV, OUV, and

Power Good pin functionality is shown in Figures 34

and 35.

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Vref = 0.8 V

V7= Vref * 75%

V4 = Vref * 110%

V5 = Vref * 90%

V2 = Vref * 125%

Comparator 1

Comparator 2

Comparator 3

Comparator 4

LOGIC

Soft Start Complete

Power Good

Restart

Latch off

Figure 32. OOV, OUV, and Power Good Circuit Diagram

Power Good = 1

Power Good = 0

Vref = 0.8 V

Vtrip_pg = Vref * 110%

Voov = Vref * 125%

Vtrip_pg = Vref * 90%

Power Good = 0

OUVP & Power Good = 0

OOVP & Power Good = 0

Trip Level Tolerance 2%

Hysteresis = 5 mV

Trip Level Tolerance 2%

Hysteresis = 5 mV

Trip Level Tolerance 2%

Hysteresis = 5 mV

Trip Level Tolerance 2%

Hysteresis = 5 mV

Power Not good High

Power Not Good Low

Figure 33. OOV, OUV, and Power Good Window Diagram

Vouv = Vref * 75%

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0.8 V ( vref * 100 %)

0.72 V (vref * 90%)

0 .60 V (vref * 75 %)

0.88 V (vref * 110 %)

1.0 V ( vref * 125 %)

FB Voltage

Latch off

Power Good

Reinitiate Softstart

Softstart Complete

Power Good Pin

Figure 34. Powerup Sequence and Overvoltage Latch

0.8 V (vref *100%)

0.72 V (vref *90%)

0.60 V (vref*75%)

0.88 V (vref *110%)

1.0 V (vref *125%)

FB Voltage

Latch off

Power Good

Reinitiate Softstart

Softstart Complete

Power Good

Figure 35. Powerup Sequence and Undervoltage Soft−Start

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CURRENT LIMIT AND CURRENT LIMIT SET

Overview

The NCP3011 uses the voltage drop across the High Side

MOSFET during the on time to sense inductor current. The

ILimit block consists of a voltage comparator circuit which

compares the differential voltage across the VCC Pin and the

VSW Pin with a resistor settable voltage reference. The sense

portion of the circuit is only active while the HS MOSFET

is turned ON.

CONTROL

Vset

RSet

Iset

13 uA

Itrip Ref−63 Steps, 6.51 mV/step

DAC /

COUNTER

Ilim Out HSDR

LSDR

VSW

VIN

VCC

Itrip Ref

VSense

Switch

Cap

Figure 36. Iset / ILimit Block Diagram

Current Limit Set

The ILimit comparator reference is set during the startup

sequence by forcing a typically 13 mA current through the

low side gate drive resistor. The gate drive output will rise

to a voltage level shown in the equation below:

Vset +Iset *R

set (eq. 4)

Where ISET is 13 mA and RSET is the gate to source resistor

on the low side MOSFET.

This resistor is normally installed to prevent MOSFET

leakage from causing unwanted turn on of the low side

MOSFET. In this case, the resistor is also used to set the

ILimit trip level reference through the ILimit DAC. The Iset

process takes approximately 350 ms to complete prior to

Soft−Start stepping. The scaled voltage level across the ISET

resistor is converted to a 6 bit digital value and stored as the

trip value. The binary ILimit value is scaled and converted to

the analog ILimit reference voltage through a DAC counter.

The DAC has 63 steps in 6.51 mV increments equating to a

maximum sense voltage of 403 mV. During the Iset period

prior to Soft−Start, the DAC counter increments the

reference on the ISET comparator until it crosses the VSET

voltage and holds the DAC reference output to that count

value. This voltage is translated to the ILimit comparator

during the ISense portion of the switching cycle through the

switch cap circuit. See Figure 36. Exceeding the maximum

sense voltage results in no current limit. Steps 0 to 10 result

in an effective current limit of 0 mV.

Current Sense Cycle

Figure 37 shows how the current is sampled as it relates

to the switching cycle. Current level 1 in Figure 37

represents a condition that will not cause a fault. Current

level 2 represents a condition that will cause a fault. The

sense circuit is allowed to operate below the 3/4 point of a

given switching cycle. A given switching cycle’s 3/4 Ton

time is defined by the prior cycle’s Ton and is quantized in

10 ns steps. A fault occurs if the sensed MOSFET voltage

exceeds the DAC reference within the 3/4 time window of

the switching cycle.

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1/4 1/2

Ton−1

1/4

3/4

Ton

Ton−2

Ton−1

No Trip:

Vsense < Itrip Ref at 3/4 Point

Trip:

Vsense > Itrip Ref at 3/4 Point

3/4

3/4 Point Determined by

Prior Cycle

Vsense

1/2

Current Level 2

Current Level 1

Itrip Ref

Figure 37. ILimit Trip Point Description

Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time

value is held and used for the following cycle’s limit sample time

Soft−Start Current limit

During soft−start the ISET value is doubled to allow for

inrush current to charge the output capacitance. The DAC

reference is set back to its normal value after soft−start has

completed.

VSW Ringing

The ILimit block can lose accuracy if there is excessive

VSW voltage ringing that extends beyond the 1/2 point of the

high−side transistor on−time. Proper snubber design and

keeping the ratio of ripple current and load current in the

10−30% range can help alleviate this as well.

Current Limit

A current limit trip results in completion of one switching

cycle and subsequently half of another cycle Ton to account

for negative inductor current that might have caused

negative potentials on the output. Subsequently the power

MOSFETs are both turned off and a 4 soft−start time period

wait passes before another soft−start cycle is attempted.

Iave vs Trip Point

The average load trip current versus RSET value is shown

the equation below:

IAveTRIP +Iset Rset

RDS(on)

4ƪVIN *VOUT

VOUT

VIN

FSWƫ

(eq. 5)

Where:

L = Inductance (H)

ISET = 13 mA

RSET = Gate to Source Resistance (W)

RDS(on) = On Resistance of the HS MOSFET (W)

VIN = Input Voltage (V)

VOUT = Output Voltage (V)

FSW = Switching Frequency (Hz)

Boost Clamp Functionality

The boost circuit requires an external capacitor connected

between the BST and VSW pins to store charge for supplying

the high and low−side gate driver voltage. This clamp circuit

limits the driver voltage to typically 7.5 V when VIN > 9 V,

otherwise this internal regulator is in dropout and typically

VIN − 1.25 V.

The boost circuit regulates the gate driver output voltage

and acts as a switching diode. A simplified diagram of the

boost circuit is shown in Figure 38. While the switch node

is grounded, the sampling circuit samples the voltage at the

boost pin, and regulates the boost capacitor voltage. The

sampling circuit stores the boost voltage while the VSW is

high and the linear regulator output transistor is reversed

biased.

VIN

8.9 V

BST

VSW

LSDR

Figure 38. Boost Circuit

Switch

Sampling

Circuit

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Reduced sampling time occurs at high duty cycles where

the low side MOSFET is off for the majority of the switching

period. Reduced sampling time causes errors in the

regulated voltage on the boost pin. High duty cycle / input

voltage induced sampling errors can result in increased

boost ripple voltage or higher than desired DC boost voltage.

Figure 39 outlines all operating regions.

The recommended operating conditions are shown in

Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor

can be placed on the boost pin without causing damage to the

device or MOSFETS. Larger boost ripple voltage occurring

over several switching cycles is shown in Region 2 (Yellow).

The boost ripple frequency is dependent on the output

capacitance selected. The ripple voltage will not damage the

device or $12 V gate rated MOSFETs.

Conditions where maximum boost ripple voltage could

damage the device or $12 V gate rated MOSFETs can be

seen in Region 3 (Orange). Placing a boost capacitor that is

no greater than 10X the input capacitance of the high side

MOSFET on the boost pin limits the maximum boost

voltage < 12 V. The typical drive waveforms for Regions 1,

2 and 3 (green, yellow, and orange) regions of Figure 39 are

shown in Figure 40.

Region 1

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90

11 .5V

Region 2

22V

Region 3

Duty Cycle

Input Voltage

Normal Operation Increased Boost Ripple

(Still in Specification)

Increased Boost Ripple

Capacitor Optimization

Required

71%

Maxi

mum

Duty

Cycle

Boost Voltage Levels

Max

Duty

Cycle

Figure 39. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor

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Figure 40. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom)

VBOOST

VIN 7.5V

Normal

Maximum

VBOOST

VIN

Normal

Maximum

VBOOST

VIN

7.5V

To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications

for the driver supply voltage. See Figure 41.

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Boost Voltage

4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5

Input Voltage (V)

Boost Voltage (V)

(Clarity on Boost Max and Ripple Def)

Figure 41. Boost Voltage at 80% Duty Cycle

Voltage Ripple

Maximum Allowable Voltage

Maximum Boost Voltage

Inductor Selection

When selecting the inductor, it is important to know the

input and output requirements. Some example conditions

are listed below to assist in the process.

Table 1. DESIGN PARAMETERS

Design Parameter Example Value

Input Voltage (VIN)9 V to 18 V

Nominal Input Voltage (VIN)12 V

Output Voltage (VOUT)3.3 V

Input ripple voltage (VINRIPPLE)300 mV

Output ripple voltage (VOUTRIPPLE)50 mV

Output current rating (IOUT)8 A

Operating frequency (Fsw) 400 kHz

A buck converter produces input voltage (VIN) pulses that

are LC filtered to produce a lower dc output voltage (VOUT).

The output voltage can be changed by modifying the on time

relative to the switching period (T) or switching frequency.

The ratio of high side switch on time to the switching period

is called duty cycle (D). Duty cycle can also be calculated

using VOUT, VIN, the low side switch voltage drop VLSD,

and the High side switch voltage drop VHSD.

F+1

T(eq. 6)

D+

TON

T(*DǓ+

TOFF

T(eq. 7)

D+

VOUT )VLSD

VIN *VHSD )VLSD

[D+

VOUT

VIN (eq. 8)

³27.5% +3.3 V

12 V

The ratio of ripple current to maximum output current

simplifies the equations used for inductor selection. The

formula for this is given in Equation 9.

ra +DI

IOUT

(eq. 9)

The designer should employ a rule of thumb where the

percentage of ripple current in the inductor lies between

10% and 40%. When using ceramic output capacitors the

ripple current can be greater thus a user might select a higher

ripple current, but when using electrolytic capacitors a lower

ripple current will result in lower output ripple. Now,

acceptable values of inductance for a design can be

calculated using Equation 10.

L+

VOUT

IOUT @ra @FSW

@(1*D)³3.3 mH

(eq. 10)

+3.3 V

8A@23% @400 kHz @(1*27.5%)

The relationship between ra and L for this design example

is shown in Figure 42.

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10% 15% 20% 25% 30% 35% 40%

VIN, (V)

L, INDUCTANCE (mH)

18 V Vout = 3.3 V

15 V

12 V

9 V

Figure 42. Ripple Current Ratio vs. Inductance

To keep within the bounds of the parts maximum rating,

calculate the RMS current and peak current.

IRMS +IOUT @1)ra2

Ǹ³8.02 A

(eq. 11)

+8A@1)(0.23)2

(eq. 12)

IPK +IOUT @ǒ1)ra

2Ǔ³8.92 A +8A@ǒ1)(0.23)

2Ǔ

An inductor for this example would be around 3.3 mH and

should support an rms current of 8.02 A and a peak current

of 8.92 A.

The final selection of an output inductor has both

mechanical and electrical considerations. From a

mechanical perspective, smaller inductor values generally

correspond to smaller physical size. Since the inductor is

often one of the largest components in the regulation system,

a minimum inductor value is particularly important in

space−constrained applications. From an electrical

perspective, the maximum current slew rate through the

output inductor for a buck regulator is given by Equation 13.

SlewRateLOUT +

VIN *VOUT

LOUT

³2.6 A

(eq. 13)

+12 V *3.3 V

3.3 mH

This equation implies that larger inductor values limit the

regulator’s ability to slew current through the output

inductor in response to output load transients. Consequently,

output capacitors must supply the load current until the

inductor current reaches the output load current level. This

results in larger values of output capacitance to maintain

tight output voltage regulation. In contrast, smaller values of

inductance increase the regulator’s maximum achievable

slew rate and decrease the necessary capacitance, at the

expense of higher ripple current. The peak−to−peak ripple

current for the NCP3011 is given by the following equation:

IPP +

VOUT(1*D)

LOUT @FSW

(eq. 14)

Ipp is the peak to peak current of the inductor. From this

equation it is clear that the ripple current increases as LOUT

decreases, emphasizing the trade−off between dynamic

response and ripple current.

The power dissipation of an inductor consists of both

copper and core losses. The copper losses can be further

categorized into dc losses and ac losses. A good first order

approximation of the inductor losses can be made using the

DC resistance as they usually contribute to 90% of the losses

of the inductor shown below:

LPCU +IRMS 2@DCR (eq. 15)

The core losses and ac copper losses will depend on the

geometry of the selected core, core material, and wire used.

Most vendors will provide the appropriate information to

make accurate calculations of the power dissipation then the

total inductor losses can be capture buy the equation below:

LPtot +LPCU_DC )LPCU_AC )LPCore (eq. 16)

Input Capacitor Selection

The input capacitor has to sustain the ripple current

produced during the on time of the upper MOSFET, so it

must have a low ESR to minimize the losses. The RMS value

of this ripple is:

IinRMS +IOUT @D@(1*D)

Ǹ(eq. 17)

D is the duty cycle, IinRMS is the input RMS current, and

IOUT is the load current.

The equation reaches its maximum value with D = 0.5.

Loss in the input capacitors can be calculated with the

following equation:

PCIN +ESRCIN @ǒIIN*RMSǓ2(eq. 18)

PCIN is the power loss in the input capacitors and ESRCIN

is the effective series resistance of the input capacitance.

Due to large dI/dt through the input capacitors, electrolytic

or ceramics should be used. If a tantalum must be used, it

must by surge protected. Otherwise, capacitor failure could

occur.

Input Start−up Current

To calculate the input startup current, the following

equation can be used.

IINRUSH +

COUT @VOUT

tSS

(eq. 19)

Iinrush is the input current during startup, COUT is the total

output capacitance, VOUT is the desired output voltage, and

tSS is the soft start interval. If the inrush current is higher than

the steady state input current during max load, then the input

fuse should be rated accordingly, if one is used.

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Output Capacitor Selection

The important factors to consider when selecting an

output capacitor is dc voltage rating, ripple current rating,

output ripple voltage requirements, and transient response

requirements.

The output capacitor must be rated to handle the ripple

current at full load with proper derating. The RMS ratings

given in datasheets are generally for lower switching

frequency than used in switch mode power supplies but a

multiplier is usually given for higher frequency operation.

The RMS current for the output capacitor can be calculated

below:

CoRMS +IO@ra

Ǹ(eq. 20)

The maximum allowable output voltage ripple is a

combination of the ripple current selected, the output

capacitance selected, the equivalent series inductance (ESL)

and ESR.

The main component of the ripple voltage is usually due

to the ESR of the output capacitor and the capacitance

selected.

VESR_C +IO@ra @ǒESRCo )1

8@FSW @CoǓ(eq. 21)

The ESL of capacitors depends on the technology chosen

but tends to range from 1 nH to 20 nH where ceramic

capacitors have the lowest inductance and electrolytic

capacitors then to have the highest. The calculated

contributing voltage ripple from ESL is shown for the switch

on and switch off below:

VESLON +

ESL @IPP @FSW

(eq. 22)

VESLOFF +

ESL @IPP @FSW

(1*D)

(eq. 23)

The output capacitor is a basic component for the fast

response of the power supply. In fact, during load transient,

for the first few microseconds it supplies the current to the

load. The controller immediately recognizes the load

transient and sets the duty cycle to maximum, but the current

slope is limited by the inductor value.

During a load step transient the output voltage initially

drops due to the current variation inside the capacitor and the

ESR (neglecting the effect of the effective series inductance

(ESL)).

DVOUT−ESR +DITRAN @ESRCo (eq. 24)

A minimum capacitor value is required to sustain the

current during the load transient without discharging it. The

voltage drop due to output capacitor discharge is

approximated by the following equation:

DVOUT−DISCHG +ǒITRANǓ2@LOUT

COUT @ǒVIN *VOUTǓ(eq. 25)

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. It should be noted

that DVOUT−DISCHARGE and DVOUT−ESR are out of

phase with each other, and the larger of these two voltages

will determine the maximum deviation of the output voltage

(neglecting the effect of the ESL).

Conversely during a load release, the output voltage can

increase as the energy stored in the inductor dumps into the

output capacitor. The ESR contribution from Equation 21

still applies in addition to the output capacitor charge which

is approximated by the following equation:

DVOUT−CHG +ǒITRANǓ2@LOUT

COUT @VOUT

(eq. 26)

Power MOSFET Selection

Power dissipation, package size, and the thermal

environment drive MOSFET selection. To adequately select

the correct MOSFETs, the design must first predict its power

dissipation. Once the dissipation is known, the thermal

impedance can be calculated to prevent the specified

maximum junction temperatures from being exceeded at the

highest ambient temperature.

Power dissipation has two primary contributors:

conduction losses and switching losses. The control or

high−side MOSFET will display both switching and

conduction losses. The synchronous or low−side MOSFET

will exhibit only conduction losses because it switches into

nearly zero voltage. However, the body diode in the

synchronous MOSFET will suffer diode losses during the

non−overlap time of the gate drivers.

Starting with the high−side or control MOSFET, the

power dissipation can be approximated from:

PD_CONTROL +PCOND )PSW_TOT (eq. 27)

The first term is the conduction loss of the high−side

MOSFET while it is on.

PCOND +ǒIRMS_CONTROLǓ2

@RDS(on)_CONTROL (eq. 28)

Using the ra term from Equation 9, IRMS becomes:

(eq. 29)

IRMS_CONTROL +IOUT @D@ǒ1)ǒra2

12ǓǓ

The second term from Equation 27 is the total switching

loss and can be approximated from the following equations.

PSW_TOT +PSW )PDS )PRR (eq. 30)

The first term for total switching losses from Equation 30

includes the losses associated with turning the control

MOSFET on and off and the corresponding overlap in drain

voltage and current.

PSW +PTON )PTOFF

(eq. 31)

2@ǒIOUT @VIN @fSWǓ@ǒtON )tOFFǓ

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where:

tON +

QGD

IG1

QGD

ǒVBST *VTHǓńǒRHSPU )RGǓ(eq. 32)

and:

tOFF +

QGD

IG2

QGD

ǒVBST *VTHǓńǒRHSPD )RGǓ(eq. 33)

Next, the MOSFET output capacitance losses are caused

by both the control and synchronous MOSFET but are

dissipated only in the control MOSFET.

PDS +1

2@QOSS @VIN @fSW (eq. 34)

Finally the loss due to the reverse recovery time of the

body diode in the synchronous MOSFET is shown as

follows:

PRR +QRR @VIN @fSW (eq. 35)

The low−side or synchronous MOSFET turns on into zero

volts so switching losses are negligible. Its power

dissipation only consists of conduction loss due to RDS(on)

and body diode loss during the non−overlap periods.

PD_SYNC +PCOND )PBODY (eq. 36)

Conduction loss in the low−side or synchronous

MOSFET is described as follows:

PCOND +ǒIRMS_SYNCǓ2

@RDS(on)_SYNC (eq. 37)

where:

(eq. 38)

IRMS_SYNC +IOUT @(1*D)@ǒ1)ǒra2

12 ǓǓ

The body diode losses can be approximated as:

PBODY +VFD @IOUT @fSW @ǒNOLLH )NOLHLǓ(eq. 39)

Vth

Figure 43. MOSFET Switching Characteristics

IG1: output current from the high−side gate drive (HSDR)

IG2: output current from the low−side gate drive (LSDR)

ƒSW: switching frequency of the converter.

VBST: gate drive voltage for the high−side drive, typically

7.5 V.

QGD: gate charge plateau region, commonly specified in the

MOSFET datasheet

VTH: gate−to−source voltage at the gate charge plateau

region

QOSS: MOSFET output gate charge specified in the data

sheet

QRR: reverse recovery charge of the low−side or

synchronous MOSFET, specified in the datasheet

RDS(on)_CONTROL: on resistance of the high−side, or

control, MOSFET

RDS(on)_SYNC: on resistance of the low−side, or

synchronous, MOSFET

NOLLH: dead time between the LSDR turning off and the

HSDR turning on, typically 85 ns

NOLHL: dead time between the HSDR turning off and the

LSDR turning on, typically 75 ns

Once the MOSFET power dissipations are determined,

the designer can calculate the required thermal impedance

for each device to maintain a specified junction temperature

at the worst case ambient temperature. The formula for

calculating the junction temperature with the package in free

air is:

TJ+TA)PD@RqJA

TJ: Junction Temperature

TA: Ambient Temperature

PD: Power Dissipation of the MOSFET under analysis

RqJA: Thermal Resistance Junction−to−Ambient of the

MOSFET’s package

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered during testing should include

maximum ambient temperature, minimum airflow,

maximum input voltage, maximum loading, and component

variations (i.e. worst case MOSFET RDS(on)).

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Figure 44. MOSFETs Timing Diagram

High−Side

Logic Signal

Low−Side

Logic Signal

High−Side

MOSFET

Low−Side

MOSFET

RDSmax

RDS(on)min

RDSmax

RDS(on)min

NOLHL NOLLH

td(on)

trtd(off)

trtf

td(on) td(off)

Another consideration during MOSFET selection is their

delay times. Turn−on and turn−off times must be short

enough to prevent cross conduction. If not, there will be

conduction from the input through both MOSFETs to

ground. Therefore, the following conditions must be met.

td(ON)_CONTROL )NOLLH utd(OFF)_SYNC )tf_SYNC

(eq. 40)

t(ON)_SYNC )NOLHL utd(OFF)_CONTROL )tf_CONTROL

and

The MOSFET parameters, td(ON), tr, td(OFF) and tf are can

be found in their appropriate datasheets for specific

conditions. NOLLH and NOLHL are the dead times which

were described earlier and are 85 ns and 75 ns, respectively.

Feedback and Compensation

The NCP3011 is a voltage mode buck convertor with a

transconductance error amplifier compensated by an

external compensation network. Compensation is needed to

achieve accurate output voltage regulation and fast transient

response. The goal of the compensation circuit is to provide

a loop gain function with the highest crossing frequency and

adequate phase margin (minimally 45°). The transfer

function of the power stage (the output LC filter) is a double

pole system. The resonance frequency of this filter is

expressed as follows:

fP0 +1

2@p@L@COUT

Ǹ(eq. 41)

Parasitic Equivalent Series Resistance (ESR) of the

output filter capacitor introduces a high frequency zero to

the filter network. Its value can be calculated by using the

following equation:

fZ0 +1

2@p@COUT @ESR (eq. 42)

The main loop zero crossover frequency f0 can be chosen

to be 1/10 − 1/5 of the switching frequency. Table 2 shows

the three methods of compensation.

Table 2. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type

fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum

fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic

fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic

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Compensation Type II

This compensation is suitable for electrolytic capacitors.

Components of the Type II compensation (Figure 45)

network can be specified by the following equations:

Figure 45. Type II Compensation

RC1 +

2@p@f0@L@VRAMP @VOUT

ESR @VIN @Vref @gm (eq. 43)

CC1 +1

0.75 @2@p@fP0 @RC1

(eq. 44)

CC2 +1

p@RC1 @fS

(eq. 45)

R1 +

VOUT *Vref

Vref

@R2 (eq. 46)

VRAMP is the peak−to−peak voltage of the oscillator ramp

and gm is the transconductance error amplifier gain.

Capacitor CC2 is optional.

Compensation Type III

Tantalum and ceramics capacitors have lower ESR than

electrolytic, so the zero of the output LC filter goes to a

higher frequency above the zero crossover frequency. This

requires a Type III compensation network as shown in

Figure 46.

There are two methods to select the zeros and poles of this

compensation network. Method I is ideal for tantalum

output capacitors, which have a higher ESR than ceramic:

Figure 46. Type III Compensation

fZ1 +0.75 @fP0 (eq. 47)

fZ2 +fP0 (eq. 48)

fP2 +fZ0 (eq. 49)

fP3 +

2(eq. 50)

Method II is better suited for ceramic capacitors that

typically have the lowest ESR available:

fZ2 +f0@1*sinqmax

1)sin qmax

Ǹ(eq. 51)

fP2 +f0@1)sin qmax

1*sin qmax

Ǹ(eq. 52)

fZ1 +0.5 @fZ2 (eq. 53)

fP3 +0.5 @fS(eq. 54)

qmax is the desired maximum phase margin at the zero

crossover frequency, ƒ0. It should be 45° − 75°. Convert

degrees to radians by the formula:

qmax +qmaxdegress @ǒ2@p

360 Ǔ:Units+radians (eq. 55)

The remaining calculations are the same for both methods.

RC1 uu 2

gm (eq. 56)

CC1 +1

2@p@fZ1 @RC1

(eq. 57)

CC2 +1

2@p@fP3 @RC1

(eq. 58)

CFB1 +

2@p@f0@L@VRAMP @COUT

VIN @RC1

(eq. 59)

RFB1 +1

2p@CFB1 @fP2

(eq. 60)

(eq. 61)

R1 +1

2@p@CFB1 @fZ2

*RFB1

R2 +

Vref

VOUT *Vref

@R1 (eq. 62)

If the equation in Equation 63 is not true, then a higher value

of RC1 must be selected.

R1 @R2 @RFB1

R1 @RFB1 )R2 @RFB1 )R1 @R2 u1

gm (eq. 63)

NCP3011, NCV3011

http://onsemi.com

TYPICAL APPLICATION CIRCUIT

9−16 V

VCC BST

HSDR

VSW

LSDR

COMP

3.3

CBST

3.3 uH

RISET

RFB1

COUT −2/3

Cc1

Cc2

GND

RFB2

CIN−1/2

RGS

RFB3

CFB

CIN−3/4 CIN−5

COUT−1

NCP3011

Figure 47. Typical Application, VIN = 9 − 16 V, VOUT = 3.3 V, IOUT = 6 A

Reference Designator Value

CIN−1470 mF

CIN−2470 mF

CIN−322 mF

CIN−422 mF

CIN−51 mF

CC1 56 pF

CC2 12 nF

CFB 1.0 nF

COUT1 470 mF

COUT2 22 mF

COUT3 22 mF

CBST 0.1 mF

RC 4.81 kW

RG 0 W

RGS 1.0 kW

RISET 22.1 kW

RFB1 3.16 kW

RFB2 1.0 kW

RFB3 1.0 kW

Q1 NTMS4816N

Q2 NTMS4816N

D1 BAT54

NCP3011, NCV3011

http://onsemi.com

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL

IN EXCESS OF THE K DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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