Surface Mount Chip Capacitors LOW PROFILE Low Profile - 25/50V C0G Dielectric Size 0805 Rated voltage d.c. 25V Cap. range Code 0.47pF 0.56 0.68 0.82 1.0 1.2 1.5 1.8 2.2 2.7 3.3 3.9 4.7 5.6 6.8 8.2 10 12 15 18 22 27 33 39 47 56 68 82 100 120 150 180 220 270 330 390 470 560 680 820 1.0nF 1.2 1.5 1.8 2.2 2.7 3.3 3.9 4.7 5.6 6.8 8.2 10 12 15 18 22 27 33 39 47 56 68 82 100 120 150 180 220 0p47 0p56 0p68 0p82 1p0 1p2 1p5 1p8 2p2 2p7 3p3 3p9 4p7 5p6 6p8 8p2 100 120 150 180 220 270 330 390 470 560 680 820 101 121 151 181 221 271 331 391 471 561 681 821 102 122 152 182 222 272 332 392 472 562 682 822 103 123 153 183 223 273 333 393 473 563 683 823 104 124 154 184 224 X7R Dielectric 1206 50V 25V 1210 50V 25V 0805 50V 25V 1206 50V 25V 50V 1210 25V 50V Minimum and Maximum capacitance values available - Chip thickness (T) 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.50 0.50 0.60 0.65 0.45 0.50 0.60 0.65 0.45 0.50 0.60 0.65 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.50 0.60 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.50 0.60 0.65 0.45 0.50 0.60 0.60 0.65 Application Available in four maximum thicknesses of 0.45mm, 0.50mm, 0.60mm and 0.65mm. The 0.45mm type is ideal for use in smart cards and sensors, where an extremely low thickness is required. The 0.65mm Z5U capacitors are designed to be surface mounted beneath a plastic leaded chip carrier. This method minimises circuit inductance and allows higher packaging densities to be achieved. They are ideal for decoupling logic circuits and memories up to 1 megabyte. All types are available with either silver/palladium or nickel barrier terminations. 0.45 0.45 0.45 0.45 0.45 0.50 0.60 0.65 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.45 0.50 0.60 0.60 0.65 0.45 0.45 0.45 0.45 0.50 0.60 0.65 0.45 0.45 0.45 0.45 0.45 0.45 0.50 0.60 0.65 0.45 0.45 0.45 0.45 0.50 0.60 0.65 0.45 0.45 0.45 0.50 0.60 0.60 0.65 Ordering information Example: ........................ 0805 Type No/Size ref Termination J = Nickel Barrier F = Palladium/Silver Voltage d.c. 025 = 25V; 050 = 50V 24 Capacitance IEC Code (c) Copyright Syfer Technology Limited - 1998. J 025 0102 J C B A52 Suffix code A51 = 0.45mm; A52 = 0.50mm A53 = 0.60mm; A54 = 0.65mm Packaging B = Bulk; T = Taped Dielectric code C = C0G; X = X7R Tolerance Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND IEC Code Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Dimensions Size Length (L) mm inches Width (W) mm inches Thickness Tmax mm inches Termination Band L2, L3 mm inches min max 0603 1.6 0.2 0.063 0.008 0.8 0.2 0.031 0.008 0.8 0.031 0.1 0.004 0.4 0.015 0805 2.0 0.3 0.08 0.012 1.25 0.2 0.05 0.008 1.3 0.051 0.13 0.005 0.75 0.03 1206 3.2 0.3 0.126 0.012 1.6 0.2 0.063 0.008 1.6 0.063 0.25 0.01 0.75 0.03 1210 3.2 0.3 0.126 0.012 2.5 0.3 0.10 0.012 1.8 0.07 0.25 0.01 0.75 0.03 1808 4.5 0.35 0.18 0.014 2.0 0.3 0.08 0.012 2.0 0.08 0.25 0.01 1.0 0.04 1812 4.5 0.35 0.18 0.014 3.2 0.3 0.126 0.012 1.8 0.07 0.25 0.01 1.0 0.04 2220 5.7 0.4 0.225 0.016 5.0 0.4 0.197 0.016 1.8 0.07 0.25 0.01 1.0 0.04 2225 5.7 0.4 0.225 0.016 6.3 0.4 0.25 0.016 1.8 0.07 0.25 0.01 1.0 0.04 3640 9.2 0.5 0.36 0.02 10.16 0.5 0.40 0.02 2.0 0.08 0.5 0.02 1.5 0.06 5550 14.0 0.5 0.55 0.02 12.7 0.5 0.50 0.02 2.5 0.1 0.5 0.02 1.5 0.06 8060 20.3 0.5 0.80 0.02 15.24 0.5 0.60 0.02 2.5 0.1 0.5 0.02 1.5 0.06 L T L3 W L2 12 Notes: The above maximum thicknesses refer to standard ranges. Please refer to Capacitance Tables for any special thickness restrictions (c) Copyright Syfer Technology Limited - 1998. Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Tape and Reel packaging information Reel dimensions mm (inches) 0.5(0.02) Plastic carrier tape T 13(0.512) 1.5(.06) min 20.2(0.795)min Tape and reel packing of surface mounting chip capacitors for automatic placement are in accordance with IEC286 part 3 and RS481. Product identifying label A 60(2.36) min G Top tape 178mm or 330mm dia. reel 8 or 12mm nominal Embossment Symbol Peel force The peel force of the top sealing tape is between 0.2 and 1.0 Newton at 180. The breaking force of the carrier and sealing tape in the direction of unreeling is greater than 10 Newtons. Tape dimensions mm (inches) Description A Reel diameter G Reel inside width T Reel outside width 178mm reel 330mm reel 178(7) 2(0.079) 330(13) max 8.4(0.33) +1.5(0.059) -0 12.4(0.49) +1.5(0.059) -0 14.4(0.56) max 18.4(0.72) max Feed direction t1 D0 P0 Sealing tape P2 E F K0 t2 W B0 D1 P1 A0 Embossment Cavity centre lines Symbol 32 8mm tape Description 12mm tape A0 B0 K0 Width of cavity Length of cavity Depth of cavity W Width of tape F Distance between drive hole centres and cavity centres E Distance between drive hole centres and tape edge P1 Distance between cavity centres P2 Axial distance between drive hole centres and cavity centres 2(0.079)0.05(0.002) P0 Axial distance between drive hole centres 4(0.156)0.1(0.004) D0 Drive hole diameter D1 Diameter of cavity piercing 1(0.039) +0.1(0.004) -0 1.5(0.059) +0.1(0.004) -0 t1 Embossed tape thickness 0.3(0.012) 0.1(0.004) 0.4(0.016) 0.1(0.004) t2 Top tape thickness (c) Copyright Syfer Technology Limited - 1998. Dependent on chip size to minimize rotation 8(0.315) 0.2(0.008) 12(0.472) 0.2(0.008) 3.5(0.138) 0.05(0.002) 5.5(0.213)0.05(0.002) 1.75(0.069)0.1(0.004) 4(0.156) 0.1(0.004) 8(0.315) 0.1(0.004) 1.5(0.059) +0.1(0.004) -0 0.1(0.004) max Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Tape and Reel packaging information Leader and trailer END START 40 empty sealed embossments minimum length is quantity dependant TRAILER COMPONENTS 20 sealed embossments minimum LEADER 400mm min. Identification Missing components The number of missing components in the tape may not exceed 0.25% of the total quantity with not more than three consecutive components missing. This must be followed by at least six properly placed components. Each reel is labelled with the following information: manufacturer, chip size, capacitance, tolerance, rated voltage, dielectric type, batch number, date code and quantity of components. Outer Packaging Product identifying label T W Outer Carton Dimensions mm (inches) max. Reel size No. of reels L W T 178 (7.0) 1 185 (7.28) 185 (7.28) 25 (0.98) 178 (7.0) 4 190 (7.48) 195 (7.67) 75 (2.95) 330 (13.0) 1 335 (13.19) 335 (13.19) 25 (0.98) L Note: Labelling of Box and Reel with bar codes (Code 39) available by arrangement. 33 (c) Copyright Syfer Technology Limited - 1998. Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Bulk packaging information Bulk Packing - Tubs Chips are supplied in rigid re-sealable plastic tubs together with impact cushioning wadding and environmental control agents. Tubs are labelled with the details: chip size, capacitance, capacitance tolerance, rated voltage, dielectric type, batch number, date code and quantity of components. Product identifying label Caution label H Caution Label IMPORTANT KEEP SEALED UNTIL REQUIRED. REPLACE UNUSED PARTS AND RE-SEAL. DO NOT DISCARD PROTECTIVE MATERIALS D Dimensions mm (inches) H 60 (2.36) D 50 (1.97) Bulk Packaging-Cassette Knob 12 7) .4 (0 Slider Shutter 36 (1.42) Chips can be supplied in a cassette designed for attachment to a surface mount placement machine. The case is made from an anti-static transparent plastic material and can store chips in sizes up to 1206. Labelling is the same as for the bulk tubs. Capacity Chip Size Thickness Capacity 0603 0.8 mm 15,000 0805 0.6 mm 10,000 1206 0.6 mm 5,000 110 (4.33) 34 (c) Copyright Syfer Technology Limited - 1998. Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Application Notes Application Notes Notes intended to guide and assist our customers in using Multilayer Ceramic Capacitors in Surface Mount Technology are available from Syfer. The information concentrates on the handling, mounting, connection, cleaning, test and re-work requirements peculiar to MLC's for SMD technology, to ensure a good match between component capability and user expectation. Some extracts are given below. Handling Ceramics are dense, hard, brittle and abrasive materials. They are liable to suffer mechanical damage, in the form of chips or cracks, if improperly handled. Terminations will be abraded onto chip surfaces if loose chips are tumbled in bulk. Metallic tracks will be left on the chip surfaces which might pose a reliability hazard. Surface mount MLC's should never be handled with fingers; perspiration and skin oils can inhibit solderability and will aggravate cleaning. MLC's should never be handled with metallic instruments. Metal tweezers should never be used as these can chip the product and may leave abraded metal tracks on the product surface. Plastic or plastic coated metal type are readily available and recommended - these should be used with an absolute minimum of applied pressure. Counting or visual inspection of MLC's is best performed on a clean glass or hard plastic surface. If MLC's are dropped or subjected to rough handling, they should be visually inspected before use. Electrical inspection may also reveal gross damage via a change in Capacitance, an increase in Dissipation Factor or a decrease either in Insulation Resistance or Electric Strength. Transportation Where possible, any transportation should be carried out with the product in its unopened original packaging. If already opened, any environmental control agents supplied should be returned to packaging and the packaging re-sealed. Avoid paper and card as a primary means of handling, packing, transportation and storage of loose chip capacitors. Many grades have a Sulphur content which will adversely affect termination solderability. Loose chips should always be packed with Sulphur-free wadding to prevent impact or abrasion damage during transportation. Storage Incorrect storage of Surface Mount MLC's can lead to problems for the user. Rapid tarnishing of the terminations, with an associated degradation of solderability, will occur if the product comes into contact with industrial gases such as Sulphur Dioxide and Chlorine. Storage in free air, particularly moist air, can result in termination oxidation. Packaging should not be opened until the MLC's are required for use. If opened, the pack should be re-sealed as soon as is practicable. Alternatively, the contents could be kept in a sealed container with an environmental control agent. Long term storage conditions, ideally, should be temperature controlled between -5 and +40C and humidity controlled between 40 and 60% R.H. Taped product should be stored out of direct sunlight, which might promote a deterioration in tape or adhesive performance. (c) Copyright Syfer Technology Limited - 1998. Product, stored under the conditions recommended above, in its "as received" packaging, has a minimum shelf life of 2 years. Mechanical Considerations For Mounted Ceramic Chip Capacitors Due to its brittle nature, ceramic chip capacitors are more prone to excesses of mechanical stress than other components used in surface mounting. One of the most common causes of failure is directly attributable to bending of the printed circuit board after solder attachment. The excessive or sudden movement of the flexible circuit board stresses the inflexible ceramic block causing a crack to appear at the weakest point, usually the ceramic/termination interface. The crack may initially be quite small and not penetrate into the inner electrodes; however, subsequent handling and rapid changes in temperature will cause the crack to enlarge. This mode of failure is often invisible to normal inspection techniques as the resultant cracks usually lie under the capacitor terminations and if left, can lead to catastrophic failure. More importantly, mechanical cracks, unless they are severe will not be detected by normal electrical testing of the completed circuit, failure only occuring at some later stage after moisture ingression. The degree of mechanical stress generated on the printed circuit board is dependent upon several factors including the board material and thickness, the amount of solder and land pattern. The amount of solder applied is important, as an excessive amount reduces the chip's resistance to cracking. As to where board flexing occurs sufficiently to produce mechanical stress cracks, it is Syfer's experience that more than 90% are due to board depanelisation, a process where two or more circuit boards are separated after soldering is complete. Other manufacturing stages that should be reviewed include:1) 2) 3) 4) 5) Attaching rigid components such as connectors, relays, display panels, heat sinks etc. Fitting conventional leaded components. Special care must be exercised when rigid terminals, as found on large can electrolytic capacitors, are inserted. Storage of boards in such a manner which allows warping. Automatic test equipment, particularly the type employing " bed of nails" and support pillars. Positioning the circuit board in its enclosure especially where this is a "snap-fit". Further information regarding the mechanical stressing of ceramic multilayer chip capacitors is available on request from our sales office. 35 Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Application Notes Recommended Process Temperature - Time The various methods of attachment of chips onto substrates invariably involve thermal cycling and the components may be thermally sensitive. This is particularly true of MLC's. Any temperature steps employed must, in broad terms, be kept below 120C (248F) and steps of no more than 70C (158F) to 80C (176F) are preferred when MLC's, size 1812 and above, are used on the substrate. Ideally the pre-heat zone should elevate the substrate from room temperature to solder operations temperature - in practice, constraints are in place as a result of required process throughput, equipment capability and material properties. A recommended temperature - time profile for chip sizes up to and including 1210 is shown in Fig 1 below. The pre-heat temperature rise of the MLC's should be kept to around 2C (3.6F) per second and should be reduced below this when larger chip planforms are used. In practice, successful ranges tend to lie in the area 1.5 to 4C (2.7 to 7.2F) per second dependent upon substrate and components. Fig 1. Solder time should be minimised. The maximum permissible solder time that a surface mounted multilayer ceramic capacitor can be subjected to is dependent upon the termination material and the process temperature characteristics. For chip sizes 1812 and above, cooling to ambient should be allowed to occur naturally. Natural cooling allows a gradual relaxation of thermal mismatch stresses in the solder joints, very important for large chips. Draughts should be avoided. Forced air cooling can induce thermal breakage, and cleaning with cold fluids immediately after a soldering process may result in cracked chip MLC capacitors. Solder Time (see Fig 2) Solder melting time should be minimised. The maximum permissible solder time that a surface mounted multilayer ceramic capacitor can be subjected to is dependent upon the termination material and process temperature/time: Fig 2 shows Comparative Temperature/Time data for silver palladium and nickel barrier terminations to meet the "Solderability Test" as specified on Page 11 for both a static solder bath and a solder wave. These curves should not be exceeded in terms of the maximum exposure time: RECOMMENDED WAVE SOLDERING PROFILE FOR CHIP SIZES UP TO AND INCLUDING 1210 T (C) 300 Fig 2 solder time temperature curves Recommended maximum exposure time as a function of temperature. 250 second wave 200 first wave 150 300 100 290 forced cooling 50 0 0 50 100 TEMPERATURE C B Curve A Silver Palladium termination Curve B Nickel Barrier termination B 280 A 150 200 t (s) 250 The capacitors may be soldered twice in accordance with this method if desired. 270 Static Bath Solder Wave 260 A 250 240 Actual component temperatures may be verified at various points on the board, by the attachment of fine thermocouples with a bead diameter of no more than 0.25mm. This may be affected using a high melting point solder such as 10 Tin 88 Lead 2 Silver. The attachment points should be the upper surface of a component termination for Wave soldering (for re-flow methods, attachment should be made to the component footprint). Use of thru' holes for fixing thermocouples should be avoided. The introduction of a soak, at the end of the pre-heat, is useful, when larger components are used, as this allows temperature uniformity to be established across the substrate. Soldering a `cool' substrate may induce substrate warpage. The magnitude or direction of the warpage may change on cooling imposing damaging stresses upon the SMD components. 230 220 210 200 0 10 20 30 40 50 60 70 TIME (SECONDS) 80 90 100 110 Successive soldering cycles (including rework) are cumulative in terms of temperature and percentage of time in affecting the capacitor in terms of solderability and resistance to soldering heat. 36 (c) Copyright Syfer Technology Limited - 1998. Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com Surface Mount Chip Capacitors Application Notes Multilayer ceramic chip - with Nickel barrier termination Leaching Leaching is the term for the dissolution of silver into the solder during the soldering operation. This weakens the terminations leading to an increase in equivalent series resistance (esr), tan and open circuit faults as well as the possibility of the chip becoming detached from the substrate. Fired ceramic dielectric To prevent leaching, the following should be observed:1. Prework should be kept to a minimum. 2. An adequate preheat period is essential. 3. Solder temperature should be held at the lower end of the normal range. 4. Dwell time should be kept to a minimum. 5. Use ceramic chip capacitors with an "anti-leaching layer". We incorporate a "barrier layer" of Nickel in the end terminations to prevent leaching. Tin outer layer Intermediate nickel layer Metal electrodes Silver termination base Ordering information for Surface Mount Chip Capacitors Example: ........................ 0805 J 100 Type No/Size ref Termination F = Silver Palladium J = Nickel Barrier Special Terminations A = High Leach Resistant Silver Palladium Voltage d.c. 016 = 16 Volts 025 = 25 Volts 050 = 50 Volts 063 = 63 Volts 100 = 100 Volts 200 = 200 Volts 250 = 250 Volts 500 = 500 Volts 630 = 630 Volts 1K0 = 2K0 = 3K0 = 4K0 = 5K0 = 1KV 2KV 3KV 4KV 5KV Capacitance (pF) First digit - 0 Second digit - First significant figure of capacitance value Third digit - Second significant figure of capacitance value Fourth digit - Number of zeros following eg. 101 = 100pF for values below 10pF a P is inserted in the second position instead of a decimal point. eg. 2P2 = 2.2pF 0101 J C T Suffix code. The remaining alpha/numeric digits are used to denote variations from standard products to customer special requirements (electrical, packing, mechanical, environmental, coding etc.) Taped and reeled chips (see page 29 for quantities) T = 178mm (7" reel) R = 330mm (13" reel) B = Bulk pack - tubs C = Bulk pack - cassette Dielectric code Dielectric Class Classes Code CECC EIA MIL Ultra stable C 1B/CG COG(NPO) CG/(BP) Stable X 2R1 X7R General purpose Y Ultra High Frequency Q To special order Stable B 2X1 BX Stable R 2C1 BZ Y5V Capacitance tolerance code Ultra stable class Cr < 10pF Cr > 10pF Stable class 0.10 pF B 5% J 0.25 pF C 10% K 0.5 pF 1% D F 20% G.P. class M 2% G 20% M 5% J -20% + 80% Z 10% K 37 (c) Copyright Syfer Technology Limited - 1998. Syfer Technology Limited Old Stoke Road Arminghall Norwich, Norfolk NR14 8SQ ENGLAND Telephone +44 (0)1603 723300 Telephone (Sales) +44 (0)1603 723310 Fax +44 (0)1603 723301 Email sales@syfer.co.uk Website www.syfer.com