85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
1
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85411 is a low skew, high performance
1-to-2 Differential-to-LVDS Fanout Buffer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
CLK, nCLK pair can accept most standard differ-
ential input levels.The ICS85411 is characterized to oper-
ate from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85411
ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
FEATURES
•2 differential LVDS outputs
•1 differential CLK, nCLK clock input
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•Maximum output frequency: 650MHz
•Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
•Output skew: 20ps (maximum)
•Part-to-part skew: 250ps (maximum)
•Additive phase jitter, RMS: 0.05ps (typical)
•Propagation delay: 2.5 ns (maximum)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Lead-Free package available
•Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
ICS85411
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS™
ICS
VDD
CLK
nCLK
GND
8
7
6
5
Q0
nQ0
Q1
nQ1
CLK
nCLK
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
2
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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2,10Qn,0QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
4,31Qn,1QtuptuO.slevelecafr
etniSDVL.riaptuptuolaitnereffiD
5DNGrewoP.dnuorgylppusrewoP
6KLCntupnInwodlluP.tupnikcolclaitnereffidgnitrevnI
7KLCtupnIpulluP.tupnikcolclaitnereffidgnitrevni-noN
8V
DD
rewoP.nipylppusevitisoP
:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15KΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15KΩ
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
3
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
I
DD
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I
HI
tnerruChgiHtupnI KLCV
DD
V=
NI
V564.3=5Aµ
KLCnV
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCV
DD
V,V564.3=
NI
V0=051-Aµ
KLCnV
DD
V,V564.3=
NI
V0=5-Aµ
V
PP
egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
2,1ETON;egatloVtupnIedoMnommoC 5.0V
DD
58.0-V
VsadenifedsiegatlovedomnommoC:1ETON
HI
.
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
DD
.V3.0+
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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DO
egatloVtuptuOlaitnereffiD 002082063Vm
∆V
DO
egnahCedutingaMDOV 004Vm
V
SO
egatloVtesffO 521.152.1573.1V
∆V
SO
egnahCedutingaMSOV 552Vm
I
FFO
egakaeLffOrewoP 02-1±02+Aµ
I
DSO
tnerruCtiucriCtrohStuptuOlaitnereffiD 5.3-5-Am
I
SO
tnerruCtiucriCtrohStuptuO 5.3-5-Am
V
HO
egatloVhgiHtuptuO 43.16.1V
V
LO
egatloVwoLtuptuO 9.060.1V
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, θ
JA 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
4
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5% TA = 0°C TO 70°C
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cdoelcyCytuDtuptuO zHM005>7435%
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ETON
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segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssaden
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.stnio
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85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
5
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ADDITIVE PHASE JITTER
Input/Output Additive Phase Jitter
@ 200MHz (12KHz to 20MHz)
= 0.05ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M 500M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
6
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVDS
3.3V±5%
Power Supply
+-
Float GND
3.3V
PART-TO-PART SKEW
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
PROPAGATION DELAY OUTPUT RISE/FALL TIME
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
t
sk(o)
Qx
Qy
OUTPUT SKEW
t
PD
nQx
nQy
Q0, Q1
nQ0, nQ1
CLK
nCLK
t
sk(pp)
PART 1
PART 2
Qx
Qy
nQx
nQy
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Q0, Q1
nQ0, nQ1
DIFFERENTIAL OUTPUT VOLTAGE SETUP
➤
➤
➤
100
out
out
LVD S
DC Input VOD/∆ VOD
VDD
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
7
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER OFF LEAKAGE SETUP
OFFSET VOLTAGE SETUP
OUTPUT SHORT CIRCUIT CURRENT SETUP DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
out
out
LVD S
DC Input
➤
➤
➤
V
OS
/∆ V
OS
V
DD
out
out
LVDS
DC Input
➤
I
OSD
V
DD
out
LVDS
DC Input
➤
IOS
➤
IOSB
VDD
out
LVDS
➤
I
OFF
V
DD
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
8
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 2.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near the
receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate
the un-used outputs.
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
R1
100
3.3V
100 Ohm Differential Transmission Line
3.3V
+
-
LVDS
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
9
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A,
the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
10
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS85411 is: 636
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
11
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliM
NUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
12
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
MA11458SCIMA11458CIOSdael8ebutrep69C°07otC°0
TMA11458SCIMA11458lee
RdnaepaTnoCIOSdael80052C°07otC°0
FLMA11458SCIFLMA11458CIOS"eerFdaeL"dael8ebutrep69C°07otC°0
TFLMA11458SCIFLMA1
1458leeRdnaepaTnoCIOS"eerFdaeL"dael80052C°07otC°0
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
85411AM www.icst.com/products/hiperclocks.html REV. B JUNE 16, 2004
13
Integrated
Circuit
Systems, Inc.
ICS85411
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TEEHSYROTSIHNOISIVER
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tijtdedda-elbatscitsiretcarahCCA
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