T48C862M-R3-TNS - Atmel

Features

•Single Package Fully-integrated 4-bit Microcontroller with RF Transmitter

•Low Power Consumption in Sleep Mode (< 1 µA Typically)

•Flash Controller for Application Program Available

•Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)

•2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply

•-40°C to +125°C Operation Temperature

•SSO24 Package

•About Seven External Components

Description

The T48C862-R3 is a s ingle package dual-chip circuit. It combines a UHF ASK/FSK

transmit ter with a 4-bit microco ntroller. It supports hi ghly inte grated soluti ons in car

access and tire pressure monitoring applications, as well as manifold applications in

the industrial and consumer segment. It is available for the frequency range of

429 MHz to 439 MHz with data rates up to 32 kbaud.

For fu rther freque nc y ra nges s uc h a s 310 MHz to 3 30 MHz and 868 MHz to 928 MHz

separate data sheets are availabl e.

The device contains a flash microcontroller.

Figure 1. Application Diagram

Antenna

Micro-

controller

PLL-

Transmitter

T48C862

Keys

UHF ASK/FSK

Receiver Micro-

controller

Microcontroller

with UHF

ASK/FSK

Transmitter

T48C862-R3

Preliminary

Rev. 4554A–4BMCU–02/03

2T48C862-R3 4554A–4BMCU–02/03

Pin Configuration

Figure 2. Pinning SSO24

XTAL

GND

ENABLE

NRESET

BP63/T3I

BP20/NTE

BP23

BP41/T2I/VMI

BP42/T2O

BP43/SD/INT3

VSS

ANT1

ANT2

PA_ENABLE

CLK

BP60/T3O

OSC2

OSC1

BP50/INT6

BP52/INT1

BP53/INT1

BP40/SC/INT3

VDD

Pin Description: RF Part

Pin Symbol Function Configuration

1 XTAL Conne cti on for crystal

2 VS Supply voltage ESD protection circuitry (see Figure 8)

3 GND Ground ESD protection circuitry (see Figure 8)

4 ENABLE Enable input

XTAL

1.2k

1.5k

182 mA

ENABLE 200k

T48C862-R3

4554A–4BMCU–02/03

21 CLK Clock output signal for microcontroller

The cloc k outp ut frequenc y is set b y the

crystal to fXTAL/4.

22 PA_ENABLE Switches on power amplifier, used for

ASK modulation

ANT2

ANT1

Emitter of antenna output stage

Open collec tor antenna output

Pin Description: RF Part (Continued)

Pin Symbol Function Configuration

CLK

100

PA_ENABLE 50k Uref=1.1V

20 mA

ANT1

ANT2

Pin Description: Microcontroller Part

Name Type Function Alternate Function Pin No. Reset State

VDD – Supply voltage – 13 NA

VSS – Circuit ground – 12 NA

BP20 I/O Bi-directional I/O line of Port 2.0 NTE-test mode enable, see als o sect ion "Master Reset" 7 Input

BP40 I/O Bi-directional I/O line of Port 4.0 SC-se r ia l clock or INT3 external interrupt input 14 Input

BP41 I/O Bi-directional I/O line of Port 4.1 VMI voltage monitor input or T2I external clock input

Timer 2 9Input

BP42 I/O Bi-directional I/O line of Port 4.2 T2O Timer 2 output 10 Input

BP43 I/O Bi-directional I/O line of Por t 4.3 S D ser ial data I/O or INT3-external interrupt input 11 Input

BP50 I/O Bi-directional I/O line of Por t 5.0 INT 6 external interrupt input 17 Input

BP52 I/O Bi-directional I/O line of Por t 5.2 INT 1 external interrupt input 16 Input

BP53 I/O Bi-directional I/O line of Por t 5.3 INT 1 external interrupt input 15 Input

BP60 I/O Bi-directional I/O line of Port 6.0 T3O Timer 3 output 20 Input

BP63 I/O Bi-directional I/O line of Port 6.3 T3I Timer 3 input 6 Input

OSC1 I Oscillator input 4-MHz crystal input or 32-kHz crystal input or external

clock input or external trimming resistor input 18 Input

OSC2 O Oscillator output 4-MHz crystal output or 32-kHz crystal output or external

clock input 19 Input

NRESET I/O Bi -directio nal reset pin – 5 I/O

4T48C862-R3 4554A–4BMCU–02/03

UHF ASK/FSK Transmitter Block

Features

•Integrated PLL Loop Filter

•ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2

•High Output Power (8 dBm) with Low Supply Current (9.0 mA)

•Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-

drain Output of the Modulating Microcontroller

•Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

•Single Li-cell for Power Supply

•Supply Voltage 2.0 V to 4.0 V in the Temperature R ange of -40°C to +85°C/+125°C

•Single-ended Antenna Output with High Efficient Power Amplifier

•CLK Output for Clocking the Microcontroller

•One-chip Soluti on with Minim um Externa l Circuitry

•125°C Operation for Tire Pressure Systems

Description

The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to

32 kbaud. The transmitting frequency range is 310 MHz to 330 MHz. It can be used in both FSK and ASK systems.

T48C862-R3

4554A–4BMCU–02/03

Figure 3. Block Diagram

CLK

PA_ENABLE

ANT2

ANT1

ENABLE

GND

XTAL

VCO

PFD

XTO

PLL

Power up /

down

Voltage monitor

External input

UTCM

OSC1

OSC2

I/O bus

EEPROM RAM

4-bit CPU core

256 x 4 bit

Data directi on +

alternat e function Data direc tion +

interrupt control

Port 4 Port 5

Data direction +

alternate function

Port 6

Timer 3

Brown- out prot ect.

RESET

Clock management

Timer 1

watchdog timer

Timer 2

Serial i nterf ace

Port 1

Port 2

Data direction

T2O

T3O

T3I

BP10

BP13

BP20/NTE

BP21

BP22

BP23

oscillators Crystal

oscillators

4 K x 8 bit

VMI

with modulator

SSI

External

clock input

interval- and

8/12-bit timer

8-bit

timer / counter

with modulator

and dem odul ator

T2I

EEPROM

2 x 32 x 16 bit

BP40

INT3

SC T2I

BP41

VMI SD

BP43

INT3

BP42

T2O BP53

INT1

BP52

INT1

BP50

INT6

BP51

INT6

BP60

T3O BP63

T3I

VSS

VDD

NRESET

µC

T48C862

6T48C862-R3 4554A–4BMCU–02/03

General Description This fully-integrated PLL transmitter that allows particularly simple, low-cost RF minia-

ture transmitters to be assembled. The VCO is locked to 32 fXTAL, thus, a 9.8438 MHz

crystal is needed for a 315 MHz transmitter. All other PLL and VCO peripheral elements

are integrated.

The XTO i s a series resonanc e oscillator so that only one capacitor together with a

crystal connected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs maximum <1 ms until the PLL is

locked a nd the CLK ou tput is sta ble. A wait ti me of ³ 1 ms until the CLK is used for the

microcontroller and the PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly

indepen dent from the load imp edance. Th e deliver ed output pow er is control led via the

connected load impedance.

This output configuration enables a simple matching to any kind of antenna or to 50 W. A

high power efficiency of h=P

out/(IS,PA VS) of 40% for the power amplifier results when

an optimized load impedance of ZLoad = (255 + j192) W is used at 3 V supply voltage.

Functional

Description If ENABLE = L and PA_ ENABLE = L, the circuit is in s tandby mode consuming only a

very smal l amount o f curren t so that a li thium cel l used as po wer supply can work for

severa l years.

With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE

remains L, onl y th e PLL and the XTO ar e running and the CLK si gn al is del iv ered to the

microcontroller. The VCO locks to 32 times the XTO frequency.

With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power

amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off,

which is used to perform the ASK modulation.

ASK Transmission The PL L t ra ns mit ter bloc k is a ct ivated by ENA BL E = H. PA_E NAB LE m us t r em ain L for

t³1 ms , then the CLK signal can be taken to clock the microc ontroller and the output

power can be modulated by means of pin PA_ENABLE. After transmission,

PA_ENABLE is switched to L and the microcontroller switches back to internal clocking.

The PLL transmitter block is switched back to standby mode with ENABLE = L.

FSK Transmission The PL L t ra ns mit ter bloc k is a ct ivated by ENA BL E = H. PA_E NAB LE m us t r em ain L for

t³1 m s, then the CLK signal c an be taken to clock the microcontroller and the power

amplifi er is swi tched on wi th P A_ENA BLE = H. Th e ch ip is the n re ady f or FS K mo dula-

tion. The microcontroller starts to switch on and off the capacitor between the XTAL load

capacitor and GND with an open-drain output port, thus changing the reference

frequenc y of the PLL. If the switch is close d, t he output frequency is l ower than if the

switch is open. Afte r transm issi on PA_ ENABL E is swit ched to L and the mi cro controll er

switches back to internal clocking. The PLL transmitter block is switched back to

standby mode with ENABLE = L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when

the following tolerances are considered.

T48C862-R3

4554A–4BMCU–02/03

Figure 4. Tolerances of Frequency Modulation

Using C4=8.2pF ±5%, C

5= 10 pF ± 5%, a switch por t with CSwitch =3pF ±10%, stray

capacitances on each side of the crystal of CStray1 =C

Stray2 = 1 pF ±10%, a parallel

capacitance of the cryst al of C0= 3.2 pF ±10% and a crystal with CM= 13 fF ±10%, an

FSK deviation of ±21.5 kHz typical with worst case tolerances of ±16.25 kHz to

±28.0 1 kH z re su lt s .

CLK Output An output CLK signal is provided for a connected microcontroller, the delivered signal is

CMOS compatible if the load capacitance is lower than 10 pF.

Clock Pulse Take Over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s

M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on

the PLL transmitter block with ENABLE = H, and after 1 ms to assume the clock signal

of the transmission IC, so the message can be sent with crystal accuracy.

Output Matching and Power

Setting The ou tput power is set by the load impe dance o f the antenna. The maxi mum outp ut

power i s achieved wi th a load im pedance of ZLoad,opt = (255 + j192) W. T here mus t be a

low resistive path to VS to deliver the DC current.

The delivered current pulse of the power amplifier is 9 mA and the maximum output

power i s deliv ered to a resisti ve load of 400 W if the 1.0 pF outp ut capac itance of the

power amplifier is compensated by the load impedance.

An optimum load impedance of:

ZLoad =400W|| j/(2 ´p1.0 pF) = (255 + j192) W thus results for the maximum output

power of 8 dBm.

The loa d impe danc e i s def ine d as th e im ped anc e see n fr om the PL L tr ansmitter blo ck’s

ANT1, ANT2 i nto the matchin g networ k. Do n ot confu se this large signal l oad imp ed-

ance with a small signal input impedance delivered as input characteristic of RF

amplif iers an d measure d from the ap plicatio n into the IC i nstead of from the IC in to the

application for a power amplifier.

Less output power is achieved by lowering the real parallel par t of 400 W where the

parallel imaginary part should be kept constant.

Output power measur ement can be done with the circuit shown in Figure 5. Note that

the component values must be changed to compensate the individual board parasitics

until the PLL tr ansmitter block has the r ight load impedance Z Load,opt = (255 + j192) W.

Also the damping of the cable used to measure the output power must be calibrated.

XTAL CStray1

CMLMRS

CStray2

Crystal equivalent circuit CSwitch

8T48C862-R3 4554A–4BMCU–02/03

Figure 5. Output Power Measurement

Application Circuit For the supply-voltage blocking capacitor C3, a value of 68 nF/X7R is recommended

(see Figure 6 and Figure 7). C1 and C2 are used to match the loop antenna to the power

amplifier where C1 typically is 22 pF/NP0 and C2 is 10.8 pF/NP0 (18 pF + 27 pF in

series); fo r C2 two capacitors in series should be us ed to achieve a better tolerance

value and to have the possibility to realize the ZLoad,opt by using standard valued

capacitors.

C1 forms together with the pins of PLL transmitter block and the PCB board wires a

series resonanc e loop that s uppresses the 1st harmonic, thus, the position of C1 on th e

PCB is important. Normally the best suppression is achieved when C1 is pl ac ed as clo se

as possible to the pins ANT1 and ANT2.

The loop an tenna should not exc eed a width of 1.5 mm, o therwise the Q-factor of the

loop antenna is too high.

L1 (50 nH to 100 nH) can be printed on PCB. C4 should be selected so the XTO runs on

the load res onance frequency of the cr ystal. Normally, a value of 12 pF results for a

15 pF load-capacitance crystal.

ANT2

ANT1

Rin

Power

meter

C1 = 1n

L1 = 33n

C2 = 2.2p

ZLopt

Z = 50 W

50 W

T48C862-R3

4554A–4BMCU–02/03

Figure 6. ASK Application Circuit

CLK

PA_ENABLE

ANT2

ANT1

ENABLE

GND

XTAL

241

VCO

PFD

XTO

PLL

Power up/down

VS C1

Loop

Antenna

XTAL

BP20/NTE

VDD

BP42/T2O

VSS

OSC1

OSC2

BP60/T3O

BP50/INT6

BP63/T3I

BP23

NRESET

BP41/T2I/VMI

BP43/SD/

INT3

BP52/INT1

BP53/INT1

BP40/SC/INT3

10 T48C862-R3 4554A–4BMCU–02/03

Figure 7. FSK Application Circuit

CLK

PA_ENABLE

ANT2

ANT1

ENABLE

GND

XTAL

241

VCO

PFD

XTO

PLL

Power up/down

VS C1

Loop

Antenna

XTAL

BP20/NTE

VDD

BP42/T2O

VSS

OSC1

OSC2

BP60/T3O

BP50/INT6

BP63/T3I

BP23

NRESET

BP41/T2I/VMI

BP43/SD/

INT3

BP52/INT1

BP53/INT1

BP40/SC/INT3

T48C862-R3

4554A–4BMCU–02/03

Figure 8. ESD Protection Circuit

CLK PA_ENABLE ANT2

ANT1

XTAL ENABLE

GND

Absolute Maxim u m Ratings

Parameters Symbol Min. Max. Unit

Supply voltage VS5V

Power dissipation Ptot 100 mW

Junction temperature Tj150 °C

Storage temperature Tstg -55 +125 °C

Ambient tem per a ture Tamb -55 +125 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient RthJA 170 K/W

Electrical Characteristics

VS = 2.0 V to 4.0 V, Tamb = -40°C to +125°C, unless otherwise specified.

Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 7).

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Supply current Power down,

VENABLE < 0.25 V, -40°C to +85°C

VPA-ENABLE < 0.25 V, -85°C to +125°C

VPA-ENABLE < 0.25 V, 25°C

(100% correlation tested)

IS_Off <10

350

7nA

µA

Supply current Power up, PA off, VS= 3 V

VENABLE > 1.7 V, VPA-ENABLE <0.25V IS3.7 4.8 mA

Supply current Power up, VS= 3.0 V

VENABLE > 1.7 V, VPA-ENABLE >1.7V IS_Transmit 911.6mA

Output po wer VS= 3.0 V, Tamb =25°C

f = 315 MHz, ZLoad = (255 + j192) WPRef 6.0 8.0 10.5 dBm

12 T48C862-R3 4554A–4BMCU–02/03

Output p ower v ariatio n f or the full

temperature range Tamb = -40°C to +85°C

VS = 3.0 V

VS = 2.0 V DPRef

DPRef

-1.5

-4.0 dB

Output p ower v ariatio n f or the full

temperature range Tamb = -40°C to +125°C

VS = 3.0 V

VS = 2.0 V

POut = PRef + DPRef

DPRef

-2.0

-4.5 dB

Achievable output-power range Selectable by load impedance POut_typ 08.0dBm

Spurious emis sion fCLK = f0/128

Load capacitance at Pin CLK = 10 pF

fO ± 1´fCLK

fO ± 4 ´fCLK

other spurious are lower

-55

-52 dBc

dBc

Oscillator frequency XTO

(= phase comparator frequency) fXTO = f0/32

fXTAL = resonant frequency of the

XTAL, CM £ 10 fF, load capacitance

selected accordingly

Tamb = -40°C to +85°C

Tamb = -40°C to +125°C

fXTO

-30

-40 fXTAL +30

+40 ppm

ppm

PLL loop bandwidth 250 kHz

Phase noise of phase

comparator Ref e rred to fPC = fXT0,

25 kHz distance to carrier -116 -110 dBc/Hz

In loop phase noise PLL 25 kHz distance to carrier -86 -80 dBc/Hz

Phase noise VCO at 1 MHz

at 36 MHz -94

-125 -90

-121 dBc/Hz

dBc/Hz

Frequency range of VCO fVCO 310 330 MHz

Clock output frequency (CMOS

microcontroller compatible) f0/128 MHz

Voltage swing at Pin CLK CLoad £ 10 pF V0h

V0l

VS´0.8 VS´0.2 V

Series reson anc e R o f the crystal Rs 110 W

Capacitive load at Pin XT0 7pF

FSK modulation frequency rate Duty cycle of the modulation signal =

50% 032kHz

ASK modulation frequency rate Duty cycle of the modulation signal =

50% 032kHz

ENABLE input Low level input voltage

High level input voltage

Input current high

VIl

VIh

IIn

1.7 0.25

µA

PA_EN ABLE input Low level input voltage

High level input voltage

Input current high

VIl

VIh

IIn

1.7 0.25

µA

Electrical Characteristics (Continued)

VS = 2.0 V to 4.0 V, Tamb = -40°C to +125°C, unless otherwise specified.

Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 7).

Parameters Test Conditions Symbol Min. Typ. Max. Unit

T48C862-R3

4554A–4BMCU–02/03

Microcontr oller Bloc k

Features •4-Kbyte ROM, 256 x 4-bit RAM

•EEPROM Programmable Options

•Read Protection for the EEPROM Program Memory

•16 Bi-directional I/Os

•Up to Seven External/Internal Interrupt Sources

•Eight Hard ware and Softw are Interrup t Priorities

•Multifunction Timer/Counter

- IR Remote Control Carrier Generator

- Biphase-, Manchester- and Pulse-width Modulator and Demodulator

- Phase Contro l Function

•Programmable System Clock with Prescaler and Five Different Clock Sources

•Very Low Sleep Current (< 1 µA)

•2 × 512-bBit EEPROM Data Memory

•256 × 4-bit RAM Da ta Memory

•Synchronous Serial Interface (2-wire, 3-wire)

•Watchdog, POR and Brown-out Function

•Voltage Monitoring Inclusive Lo_BAT Detect

Description The microcontroller is designed with EEPROM cel ls so it can be programmed s everal

times. To offer full compatibility with each ROM version, the I/O configuration is stored

into a separate internal EEPROM block during programming. The configuration is down-

loaded to the I/Os with every power-on reset.

Introduction The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrol-

lers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit

programmable multifunction timer/counters, voltage supervisor, interval timer with

watchdog function and a soph isticat ed on-chip clock g eneration wi th integr ated RC-,

32-kHz and 4-MHz crystal oscillators.

Differences between T48C862-R3 and ATAR862 Microcontrollers

Program Memory The program memory of the devices is realized as an EEPROM. The memory size for

user prog rams is 4096 by tes. It is pro grammed as 258 ´ 16 bytes blocks of data. the

implement LOCK-bit function is user-selectable and protects the device from unautho-

rized read-out of the program memory.

Configuration Memory An addit ional ar ea of 32 b ytes of the EEPROM is use d to store informati on about th e

hardware configuration. All the options that are selectable for the ROM versions are

availab le to the user . This i nc ludes not o nly th e di fferen t por t op tio ns but a lso th e pos s i-

bilities to select different capacitors for OSC1 and OSC2, the option to enable or disable

the hardloc k for the watchdog, the option to select OSC2 instead of OSC1 as external

clock input and the option to enable the external clock monitor as a reset source.

Data Memory The microcontroller block contains an internal data EEPROM that is organized as two

pages of 32 ´16-bit. To be compatible with the ROM parts, the page used has to be

defined within the appl ication software by wr iting the 2-wire interfa ce (TWI) command

"09h" to the EE PROM. T his command ha s no effect for the microcont roller b lock, if it is

left inside the HEX-file for the ROM version. Also for compatibility reasons, the access to

the EEPROM is handled via the MCL (serial interface) as in the corresponding ROM

parts.

14 T48C862-R3 4554A–4BMCU–02/03

Reset Function During each reset (power-on or brown-out), the I/O configuration is deleted and

reloaded with the data from the configuration memory. T his leads to a slightly different

behavi or compar ed to the RO M versions . Both dev ices swi tch their I/ Os to input du ring

reset but the ROM part has the mask selected pull-up or pull-down resistors active while

the MTP has them removed until the download is finished.

Microcontroller

Architecture General

Description

The microcontroller consists of an advanced stack-based, 4-bit CPU core and on- chip

periph erals. The CPU is based on the Harvard architec ture with physically sep arated

program mem ory (ROM) and data memory (RAM). Three independent bu ses, the

instruction bus, the memory bus and the I/O bus, are used for parallel communication

between ROM, RAM and peripherals. This enhances program execution speed by

allowing both i nstr uctio n pref etching, and a simu ltaneou s co mmu nicat ion to the on -chip

peripheral circuitry . The extremely powerful in tegrated interrupt contr oller with associ-

ated eight prioritized interrupt levels supports fast and efficient processing of hardware

events. The microcont roller is designed for the high-level programming language

qFORTH . The core includes b oth an expressio n a nd a return stack. T his architect ure

enables high-level language programming without any loss of efficiency or code density.

Figure 9. Micr ocontr ol ler Core

Components of

Microcontroller Core The co re contai ns ROM, RA M, ALU, pr ogram cou nter, RA M addre ss registe rs, inst ruc-

tion decoder and interrupt controller. The following sections describe each functional

block in more detail.

Program Memory The program memory (EEPROM) is programmable with the customer application

program during the fabrication of the microcontroller. The EEPROM is addr essed by a

12-bit wide program counter, thus predefining a maximum program bank size of

4-Kbytes. The lowest user program memory address segment is taken up by a

512 bytes Zero page which contains predefined start addresses for interrupt service rou-

tines and special subroutines accessible with single byte instructions (SCALL).

Instruction

decoder

CCR

TOS

ALU

RAM

Program 256 x 4-bit

MARC4 CORE

Clock

Reset

Sleep

Memory bus

I/O bus

Instruction

bus

Reset

System

clo ck Interrupt

controller

On-chip peripheral modules

memory SP

T48C862-R3

4554A–4BMCU–02/03

The corr esponding memory map is shown in Figu re 4. Look-u p tables of cons tants can

also be held in ROM and are accessed via the microcontrollers’ built-in table instruction.

Figure 10. ROM Map of the Microcontroller Block

RAM The microcontroller block contains a 256 x 4-bit wide static random access memory

(RAM), which is used for the expression stack. The return stack and data memory are

used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM

address registers SP, RP, X and Y.

Expressi on Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All

arithmetic, I/O and memory r eference operations take their operands, and return their

results to the expression stack. The microcontroller performs the operations with the top

of stack items (TOS and TOS-1). The TOS register contains the top eleme nt of the

expression stack and works in the same way as an accumulator. This stack is also used

for passing parameters between subroutines and as a scratch pad area for temporary

storage of data.

Return Stack The 12 -b it wid e re tur n sta ck is ad dr essed by the r etu rn s tac k p oin ter ( RP ) . It i s us ed for

storing return ad dresse s of su broutines, interru pt routines and fo r keeping loop in dex

counts. The return stack can also be used as a temporary storage area.

The microcontroller instruction set supports the exchange of data between the top ele-

ments of the expression stack and the return stack. The two stacks within the RAM have

a user definable location and maximum depth.

EEPROM

(4 K x 8 bit)

Zero page

FFFh

7FFh

1FFh

000h

1F0h

1F8h

010h

018h

000h

008h

020h

1E8h

1E0h

SCALL addresses

140h

180h

040h

0C0h

008h $AUTOSLEEP

$RESET

INT0

INT1

INT2

INT3

INT4

INT5

INT6

INT7

1E0h

1C0h

100h

080h

page

000h

16 T48C862-R3 4554A–4BMCU–02/03

Figure 11. RAM Map

Registers The mi crocon trolle r has seve n p rogramm able regist ers a nd one condi tion c ode r egis ter

(seeFigure 12).

Pr ogram Counter (PC) The prog ram co unter i s a 12 -bit reg ister whi ch conta ins th e addr ess of the next in st ruc-

tion to be fetched from the EEPROM. Instructions currently being executed are decoded

in the instruction decoder to determine the internal micro-operations. For linear code (no

calls or branches), the pr ogram counte r is increm ented with ever y instructio n cycle. If a

branch-, call-, return-instruction or an interrupt is executed, the program counter is

loaded wit h a new address . The progr am counter is also used wit h the table instr uction

to fetch 8-bit wide EEPROM constants.

Figure 12. Prog rammi ng Mod e l

RAM

FCh

00h

Autosleep

FFh

03h

04h

TOS-1

Expression

stack

Return

stack

Global

variables

RAM address register:

07h

(256 x 4-bit)

Global

variables

4-bit

TOS

TOS-1

TOS-2

Expression stack

Return stack

011

12-bit

TOS

CCR

-- BI

Program counter

Return stack pointer

Expression stack pointer

RAM address register (X)

RAM address register (Y)

Top of stack register

Condition code register

Carry / borrow

Branch

Interrupt enabl e

Reserved

T48C862-R3

4554A–4BMCU–02/03

RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.

These registers allow access to any of the 256 RAM nibbles.

Expression Stack Pointer (SP) The st ack pointe r contains the ad dress of the next-to-top 4 -bit item (TOS-1) of the

expression stack. The pointer is automatically pre-incremented if a nibble is moved onto

the stack or post-decremented if a nibble is removed from the stack. Every post-decre-

ment operation moves the item (TOS-1) to the TOS register before the SP is

decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate

the start address of the expression stack area.

Return Stack Pointer (RP) The return stac k pointer points to the top element of the 12-bit wide r eturn stack. The

pointer automatically pre-increments if an element is moved onto the stack, or it post-

decrements if an element is removed from the stack. The return stack pointer incre-

ments and decrements in steps of 4. This means that every time a 12-bit element is

stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH

compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial-

ized via >RP FCh.

RAM Address Registers

(X and Y) The X and Y reg isters are used to add ress any 4-bit item in the RAM. A fetch ope ration

moves the addressed nibble onto the TOS. A store operation moves the TOS to the

addressed RAM location. By using either the pre-increment or post-decrement address-

ing mode arrays in the RAM can be compared, filled or moved.

Top of Stack (TOS) The top of stack register is the accumulator of the microcontroller block. All arith-

metic/lo gic, me mory refe rence and I /O ope rations use this r egister . The TO S register

receives data from the ALU, EEPROM, RAM or I/O bus.

Condition Code Regis ter

(CCR) The 4-bit wide condition code register contains the branc h, the carry and the interrupt

enabl e flag. The se bit s indicate the curr ent stat e of the CPU . The CCR flags are set or

reset by ALU operations. The instru ctions SET_BCF, TOG_BF, CCR! and DI allow

direct manipulation of the condition code register.

Carry/Borrow (C) The carr y /borr ow f lag in dica t es that the bor rowi ng o r car ry ing out of a ri thm eti c logi c unit

(ALU) occurred during the last arithmetic operation. During shift and rotate operations,

this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.

Branch (B) The branc h f lag co ntr ol s the condi tio nal progr a m br an ch ing . S hou ld the br anc h flag has

been set by a previous instruction, a condi tional branch will cause a jump. This flag is

affected by arithmetic, logic, shift, and rotate operations.

Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou-

tines wi th the exce ption of th e non-mas kable rese t. After a res et or while ex ecutin g the

DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will

not accept any further interrupt requests until the interrupt enable fl ag has been set

again by either executing an EI or SLEEP instruction.

18 T48C862-R3 4554A–4BMCU–02/03

ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top

two elements of the expression stack (TOS and TOS-1) and returns the result to the

TOS. The ALU operations affects the carry/borrow and branch flag in the condition code

Figure 13. ALU Zero-address Operations

I/O Bus The I/O ports and the reg is ters of the peri phe ral mod ules are I/O mappe d. Al l com mun i-

cation betw een the cor e a nd th e on -chip peri pheral s ta ke pl ace via th e I/O bu s and the

associated I/O control. With the microcontroller IN and OUT instructions, the I/O bus

allows a di r ect r ead or write acces s to o ne o f th e 16 pr im ar y I/O ad dr es se s. Mor e abo ut

the I/O ac cess to th e on-chip per ipherals is described in the sec tion “Perip heral Mod-

ules”. The I/O bus is internal and is not accessible by the customer on the final

microcontroller devi ce, but it is used as the interface for the mic rocontroller emulation

(see also the section “Emulation ”).

Instruction Set The microcontroller instruction set is optimized for the high level programming language

qFORTH. M any mi crocon troller instruc tions are qFOR TH word s. Th is enable s the c om-

piler to generate a fast and compact program code. The CPU has an instruction pipeline

allowing the contr oller to prefetch an instr uctio n from EEPR OM at the sam e time as the

present instr uction is being e xecuted. The micr ocontroller is a z ero-address machi ne,

the instructions contain only the operation to be performed and no source or destination

address fields. The operations are implicitly performed on the data placed on the stack.

There are one- and two-by te instructions which are exec uted within 1 to 4 machine

cycles. A microcontroller machine cycle is made up of two system clock

cycles (SYSCL). Most of the instructions are only one byte long and are executed in a

single mac hine cy cl e. For more info rmati on re fer to the “MARC 4 Pro gramm er ’s Guide” .

Interrupt Structure The microcontroller can handle interrupts with eight different priority levels. They can be

generated fr om the internal and external inter rupt sources or by a software interrupt

from the CPU itself. Each interrupt level has a hard-wired priority and an associated vec-

tor for the service routine in the EEPROM (see Table 1). The programmer can postpone

the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An inter-

rupt occurrence will still be registered, but the interrupt routine only started after the

I-flag is set. All interrupts can be masked, and the priority individually software config-

ured by programming the appropriate control register of the interrupting module (see

section “Peripheral Modules”).

TOS-1

CCR

RAM

TOS-2

TOS-3

TOS

ALU

TOS-4

T48C862-R3

4554A–4BMCU–02/03

Interrupt Processing For processing the eight interrupt levels, the microcontroller includes an interrupt con-

troller with two 8-bit wide interrupt pending and interrupt active registers. The interrupt

controller samples all interrupt requests during every non-I/O instruction cycle and

latches these in the inter rupt pendi ng regis ter. If no hi gher pri ority int errupt is present in

the interrupt active register, it signals the CPU to interrupt the current program execu-

tion. If the interrupt enable bit is set, the proces sor enters an i nter rupt acknowledge

cycle. During this cycle a short call (SCALL) instruction to the service routine is exe-

cuted an d the curren t PC is save d on the retu rn stack . An interru pt service ro utine is

completed with the RTI instruction. This instruction resets the corresponding bits in the

interrupt pen ding/a ctive r egister and f etches th e ret urn a ddress from the return st ack to

the progr am counter. Whe n the interru pt enable flag is reset (triggeri ng of interrupt r ou-

tines is di sabl ed), th e executi on of new inter rupt ser vice routi nes i s inhibi ted but n ot the

logging of the interrupt requests in the interrupt pending register. The execution of the

interrupt is dela yed until the inte rrupt enable fla g is set again . Note that interrupts are

only lost if an interrupt request occurs while the corresponding bit in the pending register

is still set (i.e., the interrupt service routine is not yet finished).

It should be noted that automatic stacking of the RBR is not carried out by the hardware

and so if ROM banking is us ed, the RBR must be stacked on the expression stack by

the applic ation program and restor ed before the RTI. After a master re set (power-on,

brown-out or watc hdog reset), the interrupt enab le flag and the interru pt pending and

interrupt active register are all reset.

Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt

service routine being activated. This is extremely short (taking between 3 to 5 machine

cycles depending on the state of the core).

Figure 14. Interrupt Handling

Priority level

INT5 active

INT7 active

INT2 pending

SWI0

INT2 active

INT0 pending INT0 active

INT2

RTI

INT5

INT3 active

INT3

RTI

INT7

Time

Main /

Autosleep

Main /

Autosleep

20 T48C862-R3 4554A–4BMCU–02/03

Table 1. Interrupt Priority

Table 2. Hardware Interrupts

Software Interrupts The programmer can generat e interrupts by using the software interrupt instruction

(SWI ), which is supporte d in qF ORTH by pre define d macros named SWI0... SWI7. Th e

software triggered interrupt operates exactly like any hardware trigger ed interrupt. The

SWI instruction takes the top two elements from the expression stack and writes the cor-

respon din g b its v ia the I/O bus to th e i nterr up t pe ndi ng re giste r. T heref or e, by us in g th e

SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for

later execution.

Hardware Interrupts In the microcontroller block, there ar e eleven hardware interrupt sourc es with seven

different levels. Each source can be masked individually by mask bits in the correspond-

ing control registers. An overview of the poss ible hardware configurations is shown in

Table 3.

Interrupt Priority RO M Add r ess Interrupt Opcode Functio n

INT0 Lowest 040h C8h (SCALL 040h) Software interrupt (SWI0)

INT1 | 080h D0h (SCALL 080h) External hardware int errupt, any ed ge at BP52 or

BP53

INT2 | 0C0h D8h (SCALL 0C0h) Timer 1 interrupt

INT3 | 100h E8h (SCALL 100h) SSI inte rrupt or external hardw are in terrupt at BP40

or BP43

INT4 | 140h E8h (SCALL 140h) Timer 2 interrupt

INT5 | 180h F0h (SCALL 180h) Timer 3 inte rrupt

INT6 | 1C0h F8h (SCALL 1C0h) External hardw are interrupt, at an y edg e at BP50 or

BP51

INT7 Highest 1E0h FCh (SCALL 1E0h) Voltage monitor (VM) interrupt

Interrupt

Interrupt Mask

Interrupt Sour ceRegister Bit

INT1 P5CR P52M1, P52M2

P53M1, P53M2 Any edge at BP52

any edge at BP53

INT2 T1M T1IM Timer 1

INT3 SISC SIM SSI buffer full/empty or BP40/BP43 interrupt

INT4 T2CM T2IM Timer 2 compare match/overflow

INT5 T3CM1

T3CM2

T3C

T3IM1

T3IM2

T3EIM

Timer 3 compare register 1 match

Timer 3 compare register 2 match

Timer 3 edge event occurs (T3I)

INT6 P5CR P50M1, P50M2

P51M1, P51M2 Any edge at BP50,

any edge at BP51

INT7 VCM VIM External/internal vol tag e mon itoring

T48C862-R3

4554A–4BMCU–02/03

Master Reset The master reset forces the CPU into a well-defined condition. It is unmaskable and is

activated independent of the current program state. It can be triggered by either initial

supply power-up, a short collapse of the power supply, brown-out detection circuitry,

watchdog time-out, or an external input clock supervisor stage (see Figure 15). A master

reset activ ati on will re se t the i nterr upt enab le fl ag, the in terr upt pe ndi ng regi s ter and the

interrup t active r egister. Durin g the power -on reset phase, the I/O bus c ontrol sign als

are se t to r eset m ode, th ereby, initia lizi ng al l on-c hip pe riphe rals. A ll b i-dire ction al ports

are set to input mode

Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an

additional internal strong pull-up transistor. This pin must not be pulled down to VSS dur-

ing reset by any external circuitry representing a resistor of less than 150 kW.

Releasi ng the res et res ults in a shor t call inst ruction (opc ode C1h) to the R OM addre ss

008h. This activa tes the initi alization routine $RESET which in turn has to initi alize all

necessary RAM variables, stack pointers and peripheral c onfiguration registers (see

Table 6).

Figure 15. Reset Configuration

Power -on Reset and

Brown-out Detection The micr oco ntrol le r bl ock has a fully in tegr ate d po wer- on res et an d br own -out de tec tio n

circuitry. For reset generation no external components are needed.

These circuits ensure that the core is held in the reset state until the minimum operating

supply voltage has been rea ched. A res et c ondition will also be generated should the

supply voltage drop momentar ily below the minimum operating level except when a

power-down mode is activated (the core is in SLEEP mode and the per ipheral clock is

stopped). In this power-down mode the brown-out detection is disabled.

Two values for the brown-out voltage threshold are programmable via the BOT-bit in the

SC-register.

Reset

timer

VDD

Power-on

reset

Internal

reset

res

CL=SYSCL/4

VDD

VSS

Brown-out

detection

VDD

VSS

Watch-

dog CWD

res

Ext. clock

supervisor ExIn

Pull-up

NRST

22 T48C862-R3 4554A–4BMCU–02/03

A power- on reset p ulse is g enerat ed by a V DD rise across the default BOT voltage level

(1.7 V). A brown-out reset pulse is generated when VDD fal ls bel ow the b rown- out v olt-

age t hreshold. Two val ues for t he brown -out volt age thr eshold ar e progra mmable vi a

the BOT-bit in the SC-register. When the controller runs in the upper supply voltage

range with a high system clock fr equency, the high threshold must be used. When it

runs with a l ower sy stem clo ck freq uency, the low thr esho ld and a wid er su pply vol tage

range may be chosen. For further deta ils, see the e lectrical speci fication an d the SC-

Figure 16. Brown-out Detection

Watchdog Reset The watchdog’s function can be enabled at the WDC-register and triggers a reset with

every watchdog counter overflow. To suppress the watchdog reset, the watchdog

counter must be regularly reset by reading the watchdog register address (CWD). The

CPU reacts in exactly the same manner as a reset stimulus from any of the above

sources.

External Clock Supervisor The exte rnal i nput clo ck su per vis or func ti on c an be enab led if the ex te rnal i npu t cl ock is

selected within the CM- and SC-registers of the clock module. The CPU reacts in

exactly the same manner as a reset stimulus from any of the above sources.

Voltage Monitor The voltage monitor consists of a comparator with internal voltage reference. It is used

to supervise the supply voltage or an external voltage at the VMI-pin. The c omparator

for the supply voltage has three internal programmable thresholds one lower threshold

(2.2 V), one middle threshold (2.6 V) and one higher threshold (3.0 V). For external volt-

ages at the VMI-pin, the comparator threshold is set to VBG = 1.3 V. The VMS-bit

indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this thresh-

old. An in terrupt can be gener ated wh en the V MS-bit is s et or reset t o detec t a risin g or

falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit

(VIM) is reset in the VMC-register.

VDD

CPU

Reset

BOT = '1'

2.0 V

1.7 V

CPU

Reset BOT = '0'

tdtd

td= 1.5 ms (typically)

BOT = 1, low brown-out voltage threshold 1.7 V (is reset value).

BOT = 0, high brown-out voltage threshold 2.0 V.

T48C862-R3

4554A–4BMCU–02/03

Figure 17. Voltage Monitor

Voltage Monitor

Control/Status Register Primary register address: "F"hex

VM2: Voltage monitor Mode bit 2

VM1: Voltage monitor Mode bit 1

VM0: Voltage monitor Mode bit 0

VIM Voltage Interrupt Mask bit

VIM = 0, voltage monitor interrupt is enabled

VIM = 1, voltage monitor interrupt is disabled

VMS Voltage Monitor Status bit

VMS = 0, the voltage at the comparator input is below VRef

VMS = 1, the voltage at the comparator input is above VRef

VDD

VM2

Volt age m onitor

VM1 VM0 VIM

VMS

- - res

OUT

BP41/

VMI

INT7

VMC :

VMST :

Bit 3Bit 2Bit 1Bit 0

VMC : Write VM2 VM1 VM0 VIM Reset value: 1111b

VMST: Read – – reserved VMS Reset value: xx11b

VM2 VM1 VM0 Function

1 1 1 Disable voltage monitor

110

External (VIM-input), internal refe renc e thresho ld (1.3 V), interrupt

with negative slope

101Not allowed

100

External (VMI-input), internal refe renc e thresho ld (1.3 V), interrupt

with positive slope

011

Internal (supply voltage), high threshold (3.0 V), interrupt with

nega tive slope

010

Internal (supply voltage), midd le threshold (2.6 V), interrupt with

nega tive slope

001

Internal (supply voltage), low threshold (2.2 V), interrupt wit h

nega tive slope

000Not allowed

24 T48C862-R3 4554A–4BMCU–02/03

Figure 18. Internal Supply Voltage Supervisor

Figure 19. External Input Voltage Supervisor

Clock Generation

Clock Module The T48C862-R3 contains a clock module with 4 different internal oscillator types: two

RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins

OSC1 a nd OSC2 are the interf ace to conn ect a crys tal either to the 4-MH z, or to the

32-kHz crystal oscillator. OSC1 can be used as input for external clocks or to connect an

external trimming resistor for the RC-oscillator 2. All necessary circuitry, except the crys-

tal and the trimming resistor, is integrated on-chip. One of these oscillator types or an

external input clock can be selected to generate the system clock (SYSCL).

In applications that do not r equire exact timing, it is possible to use the fully integrated

RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency

tolerance is better than ± 50%. The RC-oscillator 2 is a trimmable oscillator whereby the

oscillator frequency can be trimmed with an external resistor attached between OSC1

and VDD. In this configuration, the RC-oscillator 2 frequency can be maintained s table

with a tolerance of ± 15% over the full operating temperature and voltage range.

The clock module is programmable via software with the clock management register

(CM) and the sy stem configuration re gister (SC). The r equired oscilla tor configuration

can be selected with the OS1-bit and the OS 0-bit in the SC-register. A programmable

4-bit divider stage allows the adjustment of the system clock speed. A special feature of

the clock management is that an external oscillator may be used and s witched on and

off via a port pin for the power-down mode. Before the external clock is switched off, the

internal RC-osci llator 1 must be selected with the CCS- bit and then the S LEEP mode

may be activated. In this state an interrupt can wake up the controller with the RC-oscil-

lator, and the external oscillator can be activated and selected by software. A

synchronization stage avoids too short clock periods if the clock source or the clock

speed is changed. If an external input clock is selected, a supervisor circuit monitors the

externa l inpu t and gener ate s a har dwa re reset if the e xt er nal cl oc k s ou rce f ail s or drops

below 500 kHz for more than 1 ms.

VDD

Low threshold

Middle threshold

High threshold

VMS = 1

Low threshold

Middle threshold

High threshold VMS = 0

3.0 V

2.6 V

2.2 V

1.3 V

VMI

VMS = 1

VMS = 0

Positive slope

Negative slope

VMS = 1

VMS = 0

Interrupt negative slope

Interrupt positive slope

Internal reference level

T48C862-R3

4554A–4BMCU–02/03

Figure 20. Clock Module

Table 3. Clock Modes

The clock module generates two output clocks. One is the system clock (SYSCL) and

the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals

and the SUBCL can supply only the peripherals with clocks. The modes for clock

sources are programma ble with the OS1-bit and OS 0-bit in the SC-register and the

CCS-b it in the C M- reg i ste r.

Oscillator Circuits and

External Clock Input

Stage

The mic rocontrolle r block se ries co nsists of fou r differen t internal oscillators : two RC-

oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external

clock input stage.

RC-oscillator 1

Fully Inte grated For timing insensitive applications, it is possible to use the fully integrated RC

oscillator 1. It operates without any external components and saves additional costs.

The RC-oscillator 1 center frequency tolerance is better than ±50% over the full temper-

ature and voltage range. The basic center frequency of the RC-oscillator 1 is

fO»3.8 MHz. The RC oscillator 1 is selected by default after power-on reset.

Mode OS1 OS0 Clock Source for SYSCL Clock Source

for SUBCLCCS = 1 CCS = 0

1 1 1 RC-oscillator 1 (internal) External input clock Cin/16

2 0 1 RC-oscillator 1 (internal) RC-oscillator 2 with

external trimming

resistor Cin/16

3 1 0 RC-osc illator 1 (internal) 4-MHz oscillator Cin/16

4 0 0 RC-oscillator 1 (internal) 32-kHz oscillator 32 kHz

Ext. clock

ExI

ExOu

Stop

RC oscillator2 RCOut2

Stop

RTrim

4-MHz oscillator 4Out

Stop

Osci

Oscou

Osci

Oscou

32-kHz osc illa tor

32Out

Osci

Oscou

oscil lator 1

RCOut1

ControlStop

IN1

IN2

Cin /2 /2 /2 /2

Divide

Sleep

WDL

Osc-

Stop

NSTOP CCS CSS1 CSS0CM:

BOT - - - OS1 OS0

SUBCL

SYSCL

SC:

OSC1

OSC2

*Configurable

Cin/16

kHz

26 T48C862-R3 4554A–4BMCU–02/03

Figure 21. RC-oscillator 1

External Input Clock The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it

meets the speci fied duty cycle, rise and fa ll times and input level s. Additionally, the

exter nal cloc k st age co ntains a super visory circui t for the in put cloc k. The super visor

function is controlled via the OS1, OS0-bit in the SC-register and the CCS-bit in the CM-

the CM-register, the supervisory circuit generates a hardware reset.

Figure 22. External Input Clock

RC-oscillator 2 with External

Trimming Resistor The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator fre-

quency can be trimmed with an external resistor between OSC1 and VDD. In this

configuration, the RC-oscillator 2 frequency can be maintained stable with a tolerance of

±10% over the full operating temperature and a voltage range VDD from 2.5 V to 6.0 V.

For example:

An output frequ ency at the RC-osc illator 2 of 2 MHz c an be obtained by c onnecting a

resistor Rext = 360 kW (see Figure 23).

oscillator 1

RcOut1

Stop

Control

RcOut1

Osc-Stop

OS1 OS0 CCS Supervisor Reset Output (Res)

110 Enable

111 Disable

x 0 x Disable

Ext. input clock

ExOut

Stop

Ext.

Clock

RcOut1

Osc-Stop

ExIn

CCS

Res

OSC1

OSC2 Clock monitor

Ext.

Clock

T48C862-R3

4554A–4BMCU–02/03

Figure 23. RC-oscillator 2

4-MHz Oscillator The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator

connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscilla-

tor circuitry is integrated, except the actual crystal, resonator, C3 and C4.

Figure 24. 4-MHz Crystal Oscillator

Figure 25. Ceramic Resonator

32-kHz Oscillator So me app lica tions r equir e lon g-term time k eepin g o r low r esoluti on tim ing. In this case,

an on-chip, low power 32-kHz crystal oscillator can be used to generate both the

SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. The

32-kHz crystal oscillator can not be stopped while the power-down mode is in operation.

oscillator 2

RcOut2

Stop

RcOut2

Osc-Stop

RTrim

OSC1

OSC2

Rext

VDD

4-MHz

oscillator

4Out 4Out

OSC1

OSC2

*Oscin

Oscout

XTAL

4 MHz

Configurable

Stop Osc-Stop

4-MHz

oscillator

4Out

Stop

4Out

Osc-Stop

OSC1

OSC2

*Oscin

Oscout

Cer.

Res

Configurable

28 T48C862-R3 4554A–4BMCU–02/03

Figure 26. 32-kHz Crystal Oscillator

Clock Management The clock management register controls the system clock divider and synchronization

stage. Writing to this register triggers the synchronization cycle.

Clock Management Register

(CM) Auxiliary register address: "3"hex

32-kHz

oscillator

32Out 32Out

OSC1

OSC2

*Oscin

Oscout

XTAL

32 kHz

Configurable

Bit 3Bit 2Bit 1Bit 0

CM: NSTOP CCS CSS1 CSS0 Reset value: 1111b

NSTOP Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode

NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode

CCS Core Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL

CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal os cillator, an external

clock source or the internal RC-os cillator 2 with the external resistor at OSC1

generates SYSCL dependent on the setting of OS0 and OS1 in the system

configuration register

CSS1 Core Speed Select 1

CSS0 Core Speed Select 0

CSS1 CSS0 Divider Note

0016

118Reset value

104

012

T48C862-R3

4554A–4BMCU–02/03

System Configuration

Po wer-down Modes The sleep mode is a shut- down condition which is used to reduce the average system

power consumption in applications where the microcontroller is not fully utilized. In this

mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruc-

tion. This instruction sets the interrupt enable bit (I) in the condition code register to

enable al l interrup ts and stops the core. Durin g the sleep mo de the periphe ral modules

remain ac tive and are able to gene rate interrupt s. The microco ntroller exits the s leep

mode by carrying out any interrupt or a reset.

The sl eep mod e can onl y be kept whe n none of th e inter rupt pe nding or ac tive re gister

bits are set. The application of the $AUTOSLEEP routine ensures the correct function of

the sleep mode. For standar d applications use the $AUTOSLEE P routine to enter the

power-d own m ode . Us ing the SLE EP in str ucti on i ns tea d of th e $A UTO SLEE P fol lo win g

an I/O instruc tion requ ires to inser t 3 n on-I/O instr uction cyc les (f or exam ple N OP N OP

NOP) between the IN or OUT command and the SLEEP command.

The total power consumption is directly proportional to the active time of the microcon-

troller. For a rough estimation of the expected average system current consumption, the

following formula should be used:

Itotal (VDD,fsyscl) = ISleep + (IDD ´ tactive/ttotal)

IDD de pends on VDD and fsyscl

Bit 3Bit 2Bit 1Bit 0

SC: write BOT --- OS1 OS0 Reset value: 1x11b

BOT Brown-Out Threshold

BOT = 1, l ow brown-out voltage threshold (1.7 V)

BOT = 0, high brown-out voltage threshold (2.0 V)

OS1 Oscillator Select 1

OS0 Oscillator Select 0

Mode OS1 OS0 Input fo r SUBCL Selecte d Oscillators

111 C

in/16 RC-oscillator 1 and external input clock

201 C

in/16 RC-oscillator 1 and RC-oscillator 2

310 C

in/16 RC -osci llator 1 and 4-MH z crystal oscil lator

400 32 kHzRC-oscillator 1 and 32-kHz crystal

oscillator

Note: If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.

30 T48C862-R3 4554A–4BMCU–02/03

The microcontroller block has various power-down modes. Dur ing the sleep mode the

clock for the microcontroller block core is stopped. With the NSTOP-bit in the clock man-

agement register (CM), it is programmable if the clock for the on-c hi p peripherals is

active or stop ped du ring the slee p mode . If the clock for the co re and t he per ipher als is

stopped, the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it

is selected it runs continuously independent of the NSTOP-bit. If the oscillator is stopped

or the 32-kHz oscillator is selected, power consumption is extremely low.

Table 4. Power-down Modes

Peripheral Modules

Addressing Peripheral s Accessing the peripheral modules takes place via the I/O bus (see Figure 21). The IN or

OUT instructions allow direct addressing of up to 16 I/O modules. A dual register

addres sing sc heme has be en ado pted to enabl e direc t addr essing of the prim ary regis-

ter. To address the auxiliary r egister, the access must be switched with an auxiliary

swit chin g modu le. Th us, a si ngle IN (or O UT) to the module address will read (or write

into) th e module pri mary regis ter. Access ing the auxil iary registe r is perform ed with the

same instruction preceded by writing the module address into the auxiliary switching

module. Byte wide regist ers are accessed by multiple IN- (or OUT-) instructions. For

more complex peripheral modules, with a larger number of registers, extended address-

ing is used. In this case, a bank of up to 16 subport registers are indirectly addressed

with the subport address. The first OUT-instruction writes the subport address to the sub

address register, the second IN- or OUT-instruction reads data from or writes data to the

addressed subport.

Mode CPU

Core Osc-

Stop (1)

Brown-

out

Function

RC-oscillator 1

RC-oscillator 2

4-MHz

Oscillator 32-kHz

Oscillator

External

Input

Clock

Active RUN NO Active RUN RUN YES

Power-

down SLEEP NO Active RUN RUN YES

SLEEP SLEEP YES STOP STOP RUN STOP

Note: 1. Osc-Stop = SLEEP and NSTOP and WDL

T48C862-R3

4554A–4BMCU–02/03

Figure 27. Example of I/O Addressing

Module ASW Module M1 Module M2 Module M3

Auxiliary Switch

Module

Primary Reg.

(Address Pointer)

Subaddress Reg. Bank of

Primary Reg.

to other modules

Subport Fh

Subport Eh

Subport 1

Subport 0 Primary Reg.

Aux. Reg.

Primary Reg.

I/O bus

Example of

qFORTH

program code

Indirect Subport Access

(Subport Register Write)

1 Addr. (SPort) Addr. (M1) OUT

2 SPort _Data Addr. (M1) OUT

(Subport Register Read)

1 Addr. (SPort) Addr. (M1) OUT

2 Addr. (M1) IN

(Subport Register Write Byte)

1 Addr. (SPort) Addr. (M1) OUT

(Subport Register Read Byte)

1 Addr. (SPort) Addr. (M1) OUT

2 Addr. (M1) IN (hi)

2 Addr. (M1) IN (lo)

3 Prim._Data Addr. (M2) OUT

4 Addr. (M2) Addr. (ASW) OUT

Dual Register Access

(Primary Register Write)

(Auxiliary Registe r Write)

5 Aux._Data Addr. (M2) OUT

(Primary Register Read)

5 Addr. (M2) IN

(Auxiliary Register Read)

3 Addr. (M2) IN

(Auxiliary Registe r Write Byte)

4 Addr. (M2) Addr. (ASW) OUT

5 Aux._Data (lo) Addr. (M2) OUT

5 Aux._Data (hi) Addr. (M2) OUT

6 Prim._Data Addr.(M3) OUT

Single Register Access

(Primary Register Write)

6 Addr. (M3) IN

(Primary Register Read)

2 SPort _Data(lo) Addr. (M1) OUT

2 SPort _Data(hi) Addr. (M1) OUT

Addr.(ASW) = Auxiliary Switch Module address

Addr.(Mx) = Module Mx address

Addr.(SPort) = Subport address

Prim._Data = Data to be written into Primary Register

Aux._Data = Data to be written into Auxiliary Register

Prim._Data(lo )= Data to be written into Auxiliary Register (low nib ble)

Prim._Data(hi) = Data to be written in to Auxiliary Register (high nibble)

SPort_Data(lo) = Data to be written into SubPort (low nibble)

SPort_Data(hi) = Data to be written into SubPort (high nibble)

(lo) = SPort_Data (low nibble)

(hi) = SPort_Data (high nibble)

32 T48C862-R3 4554A–4BMCU–02/03

Table 5. Pe riph er al Add re sses

Port Address Name Write/

Read Reset Value Register Function Module

Type See

Page

1 P1D AT W/R 1xx1b Port 1 - data register/input data M3 22

2 P2DAT W/R 1111b Port 2 - data register/pin data M2 23

Aux iliary P2CR W 1111b Port 2 - control register 23

3 SC W 1x11b Sy st em conf iguration register M3 19

CWD R xxxxb Watchdog reset M3 29

Aux iliary CM W/R 1111b Clock management register M2 18

4 P4DAT W/R 1111b Port 4 - data register/pin data M2 27

Aux iliary P4CR W 1111 1111b Port 4 - control register (byte) 27

5 P5DAT W/R 1111b Port 5 - data register/pin data M2 25

Aux iliary P5CR W 1111 1111b Port 5 - control register (byte) 25

6 P6DAT W/R 1xx1b Port 6 - data register/pin data M2 28

Aux iliary P6CR W 1111b Port 6 - control register (byte) 28

7 T12SUB W – Data to Timer 1/2 subport M1 20

Subport address

0 T2C W 0000b Timer 2 control register M 1 39

1 T2M 1 W 1111b Timer 2 mode register 1 M1 40

2 T2M 2 W 1111b Timer 2 mode register 2 M1 41

3 T2CM W 0000b Timer 2 compare mode register M 1 42

4 T2CO1 W 1111b Timer 2 compare register 1 M1 42

5 T2CO2 W 1111 1111b Timer 2 compare register 2 (byte) M1 42

6– – – Reserved

7– – – Reserved

8 T1C1 W 1111b Timer 1 control register 1 M1 31

9 T1C2 W x111b Timer 1 control register 2 M1 32

A WDC W 1111b Watchdog control register M1 32

B-F Reserved

8 ASW W 1111b Auxiliary/switch register ASW 20

9 STB W xxxx xxxxb Serial transmit buffer (byt e) M2 65

SRB R xxxx xxxxb Serial receive buffer (byte) 65

Aux iliary SIC1 W 1111b Serial interface control register 1 63

A SISC W/R 1x11b Ser ial interface status/control register M2 65

Aux iliary SIC2 W 1111b Serial interface control register 2 64

B T3SUB W/R – Data to/from Timer 3 subport M1 20

Subport address

0 T3M W 1111b Timer 3 mode register M1 51

1 T3CS W 1111b Timer 3 clock select register M1 52

2 T3CM1 W 0000b Timer 3 compare mode register 1 M 1 53

3 T3CM2 W 0000b Timer 3 compare mode register 2 M 1 54

4 T3CO1 W 1111 1111b Timer 3 compare register 1 (byte) M1 54

4 T3CP R xxxx xxxxb Timer 3 capture register (byte) M1 55

5 T3CO2 W 1111 1111b Timer 3 compare register 2 (byte) M1 54

6 W 1111b Reserved

7-F – Reserved

C T3C W 0000b Timer 3 control register M3 52

T3ST R x000b Timer 3 status registe r M3 52

D, E – – Reserved

F VMC W 1111b Voltage monitor control register M3 12

VMST R xx11b Voltage monitor status register M3 12

T48C862-R3

4554A–4BMCU–02/03

Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1

and Port 6 hav e a data width of 2 bits (bit 0 and bit 3 ). All ports may be used for data

input or output. Al l ports are equippe d with Sch mitt trigg er input s and a varie ty of mask

option s for open- drain, open -sou rce, fu ll- complem entar y ou tputs, pull -up and p ull-do wn

transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address reg-

ister of the respective port address and the Port Control Register (PxCR), to the

corresponding auxiliary register.

There are five different directional ports available:

Port 1 2-bit wide bi-directional port with automatic full bus width direction switching.

Port 2 4-bit wide bitwise-programmable I/O port.

Port 5 4-bit wide bitwise-programmable bi-directional port with optional strong

pull-ups and programmable interrupt logic.

Port 4 4-bit wide bitwise-programmable bi-directional port also provides the I/O

interface to Timer 2, SSI, voltage monitor input and external interrupt input.

Port 6 2-bit wide bitwise-programmable bi-directional port also provides the I/O

interface to Timer 3 and external interrupt input.

Bi-directional Port 1 In Port 1 the data d irect ion reg ister i s not independ ently softwa re prog ramma ble, th e

directio n of the complete por t being s witched auto matically wh en an I/O instructio n

occur s (s ee Figu re 28 ). T he por t is s witc he d to ou tput mode v i a a n OU T i ns truc tion an d

to input via an IN instruction. The data written to a port will be stored into the output data

latches and appears immediately at the port pin following the OUT instruction. After

RESET all outpu t latches are set to "1" and the port is switche d to input mode. An IN

instruction reads the condition of the associated pins.

Note: Care must be taken when switching the bi-directional port from output to input. The

capacitive pin loading at this port in conjunction with the high resistance pull-ups may

cause the CPU to read the contents of the output data register rather than the exter nal

input state. To avoid th is, one o f the following programming techniques should be used:

Use two IN-instructions and DROP the first data nibble. The first IN switches the port

from output to input and the DROP removes the first invalid nibble. The second IN reads

the valid pin state.

Use an O UT-ins tructi on follo w ed by an IN-inst ruction . V ia the O U T-instructio n, th e ca pac -

itive load is charged or discharged depending on the optional pull-up/pull-down

confi gur ation . Wr ite a "1" for pin s wit h pul l-u p res ist ors a nd a " 0" for pi ns wi th pull- down

resistors.

34 T48C862-R3 4554A–4BMCU–02/03

Figure 28. Bi-directional Port 1

Bi-directional Port 2 As al l othe r bi- dire ctional por ts, t his port in clud es a bitwi se pro gram mable Contr ol R eg-

ister (P2CR), whi ch enables the individual programmi ng of each port bit as input or

output. It also opens up the possibility of reading the pin condition when in output mode.

This is a useful feature for self testing and for serial bus applications.

Port 2, howev er, has an increased d rive capability a nd an additional lo w resistance

pull-up/pull-down transistor mask option.

Care should be taken connecting external components to BP20/NTE. During any reset

phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up

transistor. This pin must not be pulled down (active or passive) to VSS during reset by

any ex ternal ci rcuitry repres enting a re sistor of less tha n 150 kW. This prevents th e cir-

cuit from unintended switching to test mode enable through the application circuitry at

pin BP20/NTE. Resistors less than 150 kW might lead to an undefined state of the inter-

nal test logic thus disabling the application firmware.

To avoid any conflict with the optional internal pull-down transistors, BP20 handles the

pull-down options in a different way than all other ports. BP20 is the only port that

switches off the pull-down transistors during reset.

Figure 29. Bi-directional Port 2

OUT

Reset

I/O Bus

Master rese t

P1DATy

(Data out)

(Direction)

BP1y

VDD

Switched

pull-up

*) Configurable

VDD

Static

pull-up

Static

pull-down

Switched

pull-down

Mast er reset

BP2y

Configurable

P2DATy

P2CRy

I/O Bus

Switched

pull-up *

Static

Pull-up

(Data out)

(Direction) *

VDD

Static

Pull-down

Switched

pull-down

VDD

T48C862-R3

4554A–4BMCU–02/03

Port 2 Data Register (P2DAT) Primary register address: "2"hex

* Bit 3 -> MSB, Bit 0 -> LSB

P ort 2 Control Register (P2CR) Auxiliary register address: "2"hex

Value: 1111b means all pins in input mode

Bi-directional Port 5 As al l othe r bi- dire ctional por ts, t his port in clud es a bitwi se pro gram mable Contr ol R eg-

ister (P5CR), which allows the individual programming of each port bit as input or

output. It also opens up the possibility of reading the pin condition when in output mode.

This is a useful feature for self testing and for serial bus applications.

The port pins can al so be used as ex ternal interrupt inputs (see Figure 30 and Figure

31). T he int errupts (INT1 and INT6) can be ma sked or indepen dently config ured to trig-

ger on either edge. The interrupt configuration and port direction is controlled by the Port

5 Control Register (P5CR). An additional low resistance pull-up/pull-down transistor

mask option provides an internal bus pull-up for serial bus applications.

The Port 5 Data Register (P 5DA T) is I/O mapped to the primary address register of

address "5"h and the Port 5 Control Register (P5CR) to the c orr esponding auxiliary

nibble and then the high nibble (see section "Addressing Peripherals").

Bit 3 * Bit 2 Bit 1 Bit 0

P2DAT3 P2DAT2 P2DAT1 P2DAT0 Reset value: 1111b

Bit 3Bit 2Bit 1Bit 0

P2CR3 P2CR2 P2CR1 P2CR0 Reset value: 1111b

Code

3 2 1 0 Function

x x x 1 BP20 in inpu t mode

x x x 0 BP20 in output mode

x x 1 x BP21 in input mode

x x 0 x BP21 in output mode

x 1 x x BP2 2 in input mode

x 0 x x BP22 in output mode

1 x x x BP23 in input mode

0 x x x BP23 in output mode

36 T48C862-R3 4554A–4BMCU–02/03

Figure 30. Bi-directional Port 5

Figure 31. Port 5 External Interrupts

Port 5 Data Register (P5DAT) Primary register address: "5"hex

Port 5 Control Register (P5CR)

Byte Write Auxiliary register address: "5"hex

Master reset

VDD

BP5y

Configurable

P5DATy

I/O Bus

IN enable

I/O Bus

Switched

pull-up

Switched

pull-down

*Static

pull-up

(Data out)

VDD

Static

Pull-down

VDD

Bidir. Port

Data in

IN_Enable

BP53

P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1

Decoder Decoder Decoder Decoder

Bidir. Port

Data in

IN_Enable

BP52

I/O-bus

Bidir. Port

Data in

IN_Enable

BP51

I/O-bus

Bidir. Port

Data in

IN_Enable

BP50

INT1 INT6

P5CR:

Bit 3Bit 2Bit 1Bit 0

P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b

Bit 3Bit 2Bit 1Bit 0

First write cycle P51M2 P51M1 P50M2 P50M1 Reset value: 1111b

Bit 7Bit 6Bit 5Bit 4

Second write cycle P53M2 P53M1 P52M2 P52M1 Reset value: 1111b

T48C862-R3

4554A–4BMCU–02/03

Table 6. P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code

Bi-directional Port 4 The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins

for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in

exactly the same way as bi- directional Port 2 (see F igure 32). Two a dditional multi-

plexes all ow data and po rt direc tion co ntrol to be pas sed over to other inte rnal modu les

(Timer 2, VM or SSI). The I/O-pins for SC and SD line have an additional mode to

generate an SSI-interrupt.

All four Por t 4 pins can be indi vidually switched by the P 4CR-regis ter. Figure 32 sh ows

the internal interfaces to bi-directional Port 4.

Figure 32. Bi-d irec ti ona l Por t 4 and Port 6

Auxiliary Address: "5"hex, First Write Cycle Second Write Cycle

Code

3 2 1 0 Function Code

3 2 1 0 Function

x x 1 1 BP50 in input mode – interrupt disabled x x 1 1 BP52 in input mode – interrupt disabled

x x 0 1 BP50 in input mode – rising edge interrupt x x 0 1 BP52 in input mode – rising edge interrupt

x x 1 0 BP50 in input mode – fall ing edge interrupt x x 1 0 BP52 in input mode – f a lli ng edg e inte rrupt

x x 0 0 BP50 in output mode – interrupt disabled x x 0 0 BP52 in output mode – interrupt disabled

1 1 x x BP51 in input mode – interrupt disabled 1 1 x x BP53 in input mode – interrupt disabled

0 1 x x BP51 in input mode – rising edge interrupt 0 1 x x BP53 in input mode – rising edge interrupt

1 0 x x BP51 in input mode – falling edge interrupt 1 0 x x BP53 in input mode – f a lli ng edg e inte rrupt

0 0 x x BP51 in output mode – interrupt disabled 0 0 x x BP53 in output mode – interrupt disabled

Master reset

VDD

BPxy

Configurable

PxDATy

I/O Bus

*Switched

pull-up

Switched

pull-down

PxCRy

SQD

PxMRy

POut

(Direction)

PDir

Intx

VDD

Static

pull-up

Static

pull-down

38 T48C862-R3 4554A–4BMCU–02/03

Port 4 Data Register (P4DAT) Primary register address: "4"hex

Port 4 Control Register (P4CR)

Byte Write Auxiliary register address: "4"hex

P4xM2, P4xM1 – Port 4x Interrupt mode/direction code

Bi-directional Port 6 The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins

for the Timer 3. As a normal port, it performs in exactly the same way as bi-directional

Port 6 (see Figure 32). Two additional multiplexes allow data and port direction control

to be passed over to other internal module (Timer 3). The I/O-pin for T3I line has an

addition al mod e to gener ate a Timer 3-in terr upt.

All two Port 6 pins can be individually switched by the P6CR register. Figure 32 shows

the internal interfaces to bi-directional Port 6.

Bit 3Bit 2Bit 1Bit 0

P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b

Bit 3Bit 2Bit 1Bit 0

First write cycle P41M2 P41M1 P40M2 P40M1 Reset value: 1111b

Bit 7Bit 6Bit 5Bit 4

Second write cycle P43M2 P43M1 P42M2 P42M1 Reset value: 1111b

Auxiliary Address: "4"hex, First Write

Cycle Second Write Cycle

Code

3 2 1 0 Function Code

3 2 1 0 Function

x x 1 1 BP40 in input mode x x 1 1 BP42 in input mode

x x 1 0 BP40 in output mode x x 1 0 BP42 in output mode

x x 0 1 BP40 enable alternate function

(SC for SSI) x x 0 x BP42 enable alternate function

(T2O for Timer 2)

x x 0 0 BP40 enable alternate function

(falling edge interrupt input for

INT3)

1 1 x x BP43 in input mode

1 1 x x BP41 in input mode 1 0 x x BP43 in output mode

1 0 x x BP41 in output mode 0 1 x x BP43 enable alternate function

(SD for SSI)

0 1 x x BP41 enable alternate function

(VMI for voltage monitor input) 0 0 x x BP43 enable alternate function

(falling edge interrupt input for

INT3)

0 0 x x BP41 enable alternate function

(T2I external clock input for

Timer 2)

––

T48C862-R3

4554A–4BMCU–02/03

Port 6 Data Register (P6DAT) Primary register address: "6"hex

P ort 6 Control Register (P6CR) Auxiliary register address: "6"hex

P6xM2, P6xM1 – Port 6x Interrupt mode/direction code

Universal Timer/Counter/

Communication Module

(UTCM)

The Universal T imer/counter/Communication Module (UTC M) consists of three timers

(Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI).

• Timer 1 is an interv al timer that can be used to generate periodical interrupts and as

prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

• Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).

• Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).

• The SSI operates as two wire serial interface or as shift register for modulation and

demodulation. The modulator and demodulator units work together with the timers

and shift the data bits into or out of the shift register.

There is a multitude of modes in which the timers and the serial interface can wo rk

together.

Bit 3Bit 2Bit 1Bit 0

P6DAT3 - - - - - - P6DAT0 Reset value: 1xx1b

Bit 3Bit 2Bit 1Bit 0

P63M2 P63M1 P60M2 P60M0 Reset value: 1111b

Auxiliary Address: "6"hex Write Cycle

Code

3 2 1 0 Function Code

3 2 1 0 Function

x x 1 1 BP60 in input mode 1 1 x x BP63 in input mode

x x 1 0 BP60 in output mode 1 0 x x BP63 in output mode

x x 0 x BP60 enable alternate port

functio n (T3O f or Tim er 3) 0 x x x BP63 enable alternate port

function (T3I for Timer 3)

40 T48C862-R3 4554A–4BMCU–02/03

Figure 33. UTCM Block Diagram

Timer 1 The Timer 1 is an int erva l tim er which c an be use d to gen er ate pe riod ic al interrupts and

as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL

or SYS CL. The t imer outp ut s ign al can be u sed as pres ca ler cloc k or as SUB CL a nd as

source for the Timer 1 interrupt. Because of other system requirements, the Timer 1 out-

put T1OUT i s synchronized with SYSCL. Therefore, in the power-down mod e SLEEP

(CPU co re -> slee p and OSC-S top -> ye s), the ou tput T1OU T is stopp ed (T1OU T = 0) .

Nevertheless, the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The

interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit

of the T1C2 register. The time interval for the timer output can be programmed via the

Timer 1 control register T1C1.

Demodu-

lator 3

8-bit Counter 3

Capture 3

Compare 3/1

Compare 3/2

Modu-

lator 3

MUX

Control

Watchdog

Interval / Prescaler

Timer 1

Timer 3

Modu-

lator 2

4-bit Counter 2/1

Compare 2/1

MUX

MUX DCG 8-bit Counter 2/2

Compare 2/2

Control

Timer 2

MUX 8-bit shift register

Receive buffer

Transmit buffer

Control

SSI SCL

INT4

INT5

INT2

NRST

INT3

POUT

TOG2

TOG3

T1OUT

SUBCL

SYSCL from clock module

T3O

T3I

T2I

T2O

I/O bus

T48C862-R3

4554A–4BMCU–02/03

This timer starts running automatically after any power-on reset! If the watchdog func-

tion is not activated, the timer can be restarted by writing into the T1C1 register with

T1RM = 1.

Timer 1 c an also be used as a watc hdog timer to prevent a s ystem from stall ing. The

watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It gen-

erates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter

must be re set before it ov erflows. The appl ication soft ware has to accom plish this by

reading the CWD register.

After po wer -on r es et t he wa tc hdog mu st be a cti va ted by so ftware in the $RESE T ini tia l-

ization routine. There are two watchdog modes, in one mode the watchdog can be

switched on and off by software, in the other mode the watchdog is active and locked.

This mode can only be stopped by carrying out a system reset.

The watchdog timer operation mode and the time interval for the watchdog reset can be

programmed via the watchdog control register (WDC).

Figure 34. Timer 1 Module

Figure 35. Timer 1 and Watchdog

Prescaler

14 bit

CL1 Watchdog

4 bit

MUX

WDCL

T1IM

T1BP

T1MUX

NRST

INT2

T1OUT

T1CS

SYSCL

SUBCL

Q5Q1 Q2 Q3 Q4

Q11

Q14

RES

Decoder

Watchdog

mode control

MUX for interval timer

Decoder MUX for watchdog t imer

T1RM T1C2 T1C1 T1C0

WDL WDR WDT1 WDT0

WDC RES

T1MUX

SUBCL

T1BP T1IM

T1IM=0

T1IM=1

INT2

T1OUT

T1C2

RESET

(NRST)

Watchdog

Divider / 8

Divider

RESET

T1C1

Write of the

T1C1 register

CL1

WDCL

Read of the

CWD re gister

42 T48C862-R3 4554A–4BMCU–02/03

Timer 1 Control Register 1

(T1C1) Address: "7"hex - Subaddress: "8"hex

* Bit 3 -> MSB, Bit 0 -> LSB

The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends

on this divider and the timer 1 input clock source. The timer input can be supplied by the

system clock, the 3-2kHz oscillator or via the clock management. If the clock manage-

ment ge nerates the SUBCL, the selected inpu t clock from the RC oscilla tor, 4-MHz

oscillator or an external clock is divided by 16.

Bit 3 * Bit 2 Bit 1 Bit 0

T1RM T1C2 T1C1 T1C0 Reset value: 1111b

T1RM Timer 1 Restart Mode T1 RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note: If WDL = 0, Timer 1 restart is impossible

T1C2 Timer 1 Control bit 2

T1C1 Timer 1 Control bit 1

T1C0 Timer 1 Control bit 0

T1C2 T1C1 T1C0 Divider Time Interval with

SUBCL Time Inter val with

SUBCL = 32 kHz Time Interval with

SYSCL = 2/1 MHz

0 0 0 2 SUBCL/2 61 µs 1 µs/2 µs

0 0 1 4 SUBCL/4 122 µs 2 µs/4 µs

0 1 0 8 SUBCL/8 244 µs 4 µs/8 µs

0 1 1 16 SUBCL/16 488 µs 8 µs/16 µs

1 0 0 32 SUBCL/32 0.977 ms 16 µs/32 µs

1 0 1 256 SUBCL/256 7.812 ms 128 µs/256 µs

1 1 0 2048 S UBC L/2048 62.5 ms 1024 µs/2048 µs

1 1 1 16384 SUBCL/16384 500 ms 8192 µs/16384 µs

T48C862-R3

4554A–4BMCU–02/03

Timer 1 Control Register 2

(T1C2) Address: "7"hex - Subaddress: "9"hex

* Bit 3 -> MSB, Bit 0 -> LSB

Watchdog Control Register

(WDC) Address: "7"hex - Subaddress: "A"hex

* Bit 3 -> MSB, Bit 0 -> LSB

Both these bits control the time interval for the watchdog reset.

Bit 3 * Bit 2 Bit 1 Bit 0

- - - T1BP T1CS T1IM Reset value: x111b

T1BP Timer 1 SUBCL ByPassed

T1BP = 1, TIOUT = T1MUX

T1BP = 0, T1OUT = SUBCL

T1CS Timer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see Figure 28)

T1CS = 0, CL1 = SYSCL (see Figure 28)

T1IM Timer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interrupt

T1IM = 0, enables Timer 1 interrupt

Bit 3 * Bit 2 Bit 1 Bit 0

WDL WDR WDT1 WDT0 Reset value: 1111b

WDL WatchDog Lock mode

WDL = 1, the w a tchdog ca n be enabled and disabled by using the WDR-bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no

effect. After the WDL-bit is cleared, the watchdog is active until a

system reset or po wer-on reset occurs.

WDR WatchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabled

WDR = 0, the watchdog is active/enabled

WDT1 WatchDog Time 1

WDT0 WatchDog Time 0

WDT1 WDT0 Divider Delay Time to Reset with

SUBCL = 32 kHz Dela y Time to Reset with

SYSCL = 2/1 MHz

0 0 512 15.625 ms 0.256 ms/0.512 ms

0 1 2048 62.5 ms 1.024 ms/2.048 ms

1 0 16384 0.5 s 8.2 ms/16.4 ms

1 1 131072 4 s 65.5 ms/131 ms

44 T48C862-R3 4554A–4BMCU–02/03

Timer 2 8-/12-bit Timer for:

• Interrupt, square-wave, pulse and duty cycle generation

• Baud-rate generation for the internal shift register

• Manchester and Biphase modulation together with the SSI

• Carrier frequency generation and modulation together with the SSI

Timer 2 can be used as an inter val time r for interru pt gener ation, as signal gen erato r or

as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and

an 8-bi t up counte r stage which both have com pare reg isters . The 4-bi t counter stages

of Timer 2 ar e casc ada ble as a 12- bi t timer or as an 8- b it timer with 4- bi t pres c ale r. Th e

timer can also be configured as an 8-bit timer and separate a 4-bit prescaler.

The Timer 2 input can be supplied via the system clock, the external input clock (T2I),

the Timer 1 output c lock, the Timer 3 outp ut clock or the s hift clock of the se rial inter-

face. The external input clock T2I is not synchronized with SYSCL. Therefore, it is

possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore, with that

input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep

and OSC -Stop - > yes) as well as in th e POWE R-DOWN (CPU cor e -> s leep and OSC-

Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit counter

stages of Timer 2 have an additional clock output (POUT).

Its output has a modulator stage that allows the generation of pulses as well as the gen-

eration and modulation of carrier frequencies. The Timer 2 output can modulate with the

shift register data output to generate Biphase- or Manchester code.

If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a

special task. The shift register can only handle bitstream lengths divisible by 8. For other

lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount

is shifted out.

If the tim er i s used for car rier f requenc y mod ulatio n, the 4-bit stage works togeth er with

an additional 2-bit duty cycle generator li ke a 6-bit prescaler to generate carrier fre-

quency and duty cycl e. The 8-bit counter is used to enable and disable the modulator

output for a programmable count of pulses.

For programming the time interval, the timer has a 4-bit and an 8-bit compare register.

For programming the timer function, it has four mode and control registers. The compar-

ator outpu t o f stage 2 is contr olled by a special c ompare mode regi ster (T2CM). Th is

which can be triggered by a compare match event or the counter overflow. This archi-

tecture enables the timer function for various modes.

The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit com pare register

(T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or

8-bit compare register and 4-bit compare register.

For 12-bit compare data value:m = x +1 0 £ x £ 4095

For 8-bit compare data value: n = y +1 0 £ y £ 255

For 4-bit compare data value:l = z +1 0 £ z £ 15

T48C862-R3

4554A–4BMCU–02/03

Figure 36. Timer 2

Timer 2 Modes

Mode 1: 12-bit Compare

Counter The 4 -bit st age and the 8-bi t stag e work to gethe r as a 12- bit co mpare count er. A co m-

pare match signal of the 4-bit and the 8-bit stage generates the signal for the counter

reset, tog gle fli p- fl op or in ter r upt. Th e co mpa re act ion is pro gram mab le v ia the c omp are

mode register ( T2CM). The 4-bit counter over flow (OVF1) supplies the clock output

(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.

Figure 37. 12-bit Compare Counter

Mode 2: 8-bit Compare

Counter with 4-bit

Programmable Prescaler

Figure 38. 8-bit Compare Counter

4-bit Counter 2/1

RES OVF1

Compare 2/1

T2CO1

CM1

POUT

SSI POUT

CL2/2 DCG

T2M1P4CR

8-bit Counter 2/2

RES OVF2

Compare 2/2

T2CO2T2CM

Control

TOG2

INT4 Biphase-,

Manchester-

modulator

OUTPUT

MOUT

M2 to

Modulat or 3

T2O

Timer 2

modulator

output-stage

T2M2

SO Control

SSI SSI

I/O-bus

T2C

CL2/1

T2I

SYSCL

T1OUT

TOG3

SCL

I/O-bus

DCGO

4-bit counter

4-bit com pare

RES

4-bit regi ster

CM1

POUT (CL2/1 /16)

8-bit counter

8-bit compare

8-bit re gi ster

OVF2

CM2

RES

T2RM T2OTM

Timer 2

output mode

and T2OTM-bit

T2IM T2CTM

TOG2

INT4

CL2/1 DCG

T2D1, 0

4-bit count er

4-bit com pare

RES

4-bit register

CM1

POUT

8-bit count er

8-bit compare

8-bit register

OVF2

CM2

RES

T2RM T2OTM

Timer 2

output mode

and T2OTM -bit

T2IM T2CTM

TOG2

INT4

CL2/1 DCG

T2D1, 0

DCGO

46 T48C862-R3 4554A–4BMCU–02/03

The 4-bit sta ge is used as programmable pr escaler for the 8 -bit counter s tage. In this

mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit

prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output

(CM1) supplies the clock output (POUT) with clocks.

Mode 3/4: 8-bit Compare

Counter and 4-bit

Programmable Prescaler

Figure 39. 4-/8-bit Compare Counter

In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit

prescale r and an 8- bit tim er with an 2-b it pr es caler o r as a d uty cyc le gen erato r. O nly i n

the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input

(T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating

of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for

the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to

generate the stop signal for modulator 2 and modulator 3.

Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the com-

pare match event toggles the output T2O. For high resolution duty cycle modulation 8

bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes

the DCG output is connected to T2O and switched on and off either by the toggle flipflop

output or the serial data line of the SSI. Modulator 2 also has 2 modes to output the con-

tent of the serial interface as Biphase or Manchester code.

The mo dulator outp ut stage ca n be configur ed by the output control b its in the T2M2

stopped e ither by car rying o ut a shif t regi ster st op (S IR = 1) or com pare match event of

stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler

has to be supplied with the internal shift clock (SCL).

4-bit count er

4-bit com pare

RES

4-bit register

8-bit counter

8-bit com pare

8-bit register

OVF2

CM2

RES

T2RM T2OTM

Timer 2

output mode

and T2OTM -bit

T2IM T2CTM

TOG2

INT4

CL2/2 DCG

T2D1, 0

DCGO

P41M2, 1P4CR

CM1 POUT

CL2/1

MUX

TOG3

T1OUT

SYSCL

SCL

T2CS1, 0

SYSCL

T2I

T48C862-R3

4554A–4BMCU–02/03

Figure 40. Timer 2 Modulator Ou tput Stage

Timer 2 Output Signals

Timer 2 Output Mode 1 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 41. Interrupt Timer/Square Wave Generator – the Output Toggles with Each

Edge Compare Match Event

Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 42. P ulse Generator – the Timer Output Togg les with the Timer Start if the

T2TS-bit Is Set

Toggle

RES/SET

Biphase/

Manchester

modulator

T2TOPT2OS2, 1, 0T2M2

T2O

S1 S2 S3

Modulator3

OMSK

SSI

CONTROL

TOG2

DCGO

4000123 40123 40123 01

Input

Counter 2

T2R

Counter 2

CMx

INT4

T2O

4000123 567 40123 56

Input

Counter 2

T2R

Counter 2

CMx

INT4

T2O Toggle

by start

T2O

4095/

255

48 T48C862-R3 4554A–4BMCU–02/03

Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 43. Pulse Generator – the Timer Toggles with Timer Overflow and Compare

Match

Timer 2 Output Mode 2 Duty Cycle Bur s t Generator 1: The DCG output signal (DCGO) is given to the output,

and gated by the output flip-flop (M2)

Figure 44. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output

Timer 2 Output Mode 3 Duty Cycle Bur s t Generator 2: The DCG output signal (DCGO) is given to the output,

and gated by the SSI internal data output (SO)

Figure 45. Carrier Frequency Burst Modulation with the SSI Data Output

4000123 567 40123 56

Input

Counter 2

T2R

Counter 2

CMx

OVF2

INT4

T2O

4095/

255

12012012345012012345678012345678910012345

DCGO

Counter 2

TOG2

T2O

Counter = com pare register (= 2)

1201201201201201201201201201201201201201

DCGO

Counter 2

TOG2

T2O

Counter = com pare register (=2)

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13

T48C862-R3

4554A–4BMCU–02/03

Timer 2 Output Mode 4 Biphase Modulator: Timer 2 Modulates the SSI Internal Data Output (SO) to Biphase

Code.

Figure 46. Biphase Modulation

Timer 2 Output Mode 5 Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to

Manchester code

Figure 47. Manchester Modulation

Timer 2 Output Mode 7 In this mo de the ti mer o verflow d efines the period an d the c ompare r egist er define s the

duty cy cl e. Du ring one per io d on ly the fir st c omp ar e ma tch oc cu rre nce is us ed to to ggl e

the timer output flip-flop, until the overflow all further compare match are ignored. This

avoids the situation that changing the compare register causes the occur rence of sev-

eral compare match during one period. The resolution at the pulse-width modulation

Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.

TOG2

T2O 0000

00110101

11 1 1

8-bit SR-Data

Bit 7 Bit 0

Data: 00110101

TOG2

T2O 000

00110101

11 1 1

8-bit SR-Data

Bit 7 Bit 0

Data: 00110101

50 T48C862-R3 4554A–4BMCU–02/03

PWM Mod e: Pulse-width modulation output on Timer 2 output pin (T2O)

Figure 48. PWM Modulation

Timer 2 Regi sters Timer 2 has 6 contr ol regi sters t o conf igure the tim er mode , the ti me in terval , the in put

clock and its output function. All registers are indirectly addressed using extended

addres sing as de scrib ed in s ection "Addre ssing Pe riph erals" . The a lternate fu nctio ns of

the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of

the Timer 2 modes require an input at T2 I/BP41 or an out put at T 2O/BP42.

Timer 2 Control Register (T2C) Address: "7"hex - Subaddress: "0"hex

0 0 50 255 1000 255 0 150 255 0 50 255 0 100

T2R

Input clock

Counter 2/2

OVF2

CM2

INT4

T2O

load the next

compare value T2CO2=150 load load

T1 T2 T3 T1 T2

TTT T T

Bit 3Bit 2Bit 1Bit 0

T2CS1 T2CS0 T2TS T2R Reset value: 0000b

T2CS1 Timer 2 Clock Select bit 1

T2CS0 Timer 2 Clock Select bit 0

T2CS1 T2CS0 Input Clock (CL 2/1) of Counter Stage 2/1

0 0 System clock (SYSCL)

0 1 Output signal of Timer 1 (T1OUT)

1 0 Internal shift clock of SSI (SCL)

1 1 Output signal of Timer 3 (TOG3)

T2TS Timer 2 Toggle w ith Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with

T2R

T2R Timer 2 Run

T2R = 0, Timer 2 stop and reset

T2R = 1, Timer 2 run

T48C862-R3

4554A–4BMCU–02/03

Timer 2 Mod e Register 1

(T2M1) Address: "7"hex - Subaddress: "1"hex

Duty Cycle Generator T he duty cy cle gen erator ge nerat es duty c ycles o f 25%, 33% o r 50%. The frequenc y at

the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler

setting. The DCG-stage can also be used as additional programmable prescaler for

Timer 2.

Bit 3Bit 2Bit 1Bit 0

T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b

T2D1 Timer 2 Duty cycl e bit 1

T2D0 Timer 2 Duty cycl e bit 0

T2D1 T2D0 Function of Duty Cycle Generator (DCG) Additional Divider Effect

1 1 Bypassed (DCGO0) /1

1 0 Duty cycle 1/1 (DC GO1) /2

0 1 Duty cycle 1/2 (DC GO2) /3

0 0 Duty cycle 1/3 (DC GO3) /4

T2MS1 Timer 2 Mode Select bit 1

T2MS0 Timer 2 Mode Select bit 0

Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes

1 1 1 4-bit counter overflow (OVF1) 12-bit compare counter; the

DCG has to be bypassed in

this mo de

2 1 0 4-bit compare output (CM1) 8-bit compare counter with

4-bit progr a mm able prescal er

and d u ty cycle generator

3 0 1 4-bit compare output (CM1) 8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler run,

the counter 2/1 starts after

writing mode 3

4 0 0 4-bit compare output (CM1) 8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler stop

and re sets

52 T48C862-R3 4554A–4BMCU–02/03

Figure 49. DCG Output Signals

Timer 2 Mod e Register 2

(T2M2) Address: "7"hex - Subaddress: "2"hex

If one of these output modes is used the T2O alternate function of Port 4 must also be

activated.

DCGIN

DCGO0

DCGO1

DCGO2

DCGO3

Bit 3Bit 2Bit 1Bit 0

T2TOP T2OS2 T2OS1 T2OS0 Reset value: 1111b

T2TOP Timer 2 Toggle Output Preset

This bit allows the programmer to preset the Timer 2 output T2O.

T2TOP = 0, resets the t oggle outputs with the write c ycle (M2 = 0)

T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)

Note: If T2R = 1, no output preset is possible

T2OS2 Timer 2 Output Select bit 2

T2OS1 Timer 2 Output Select bit 1

T2OS0 Timer 2 Output Select bit 0

Output Mode T2OS2 T2OS1 T2OS0 Clock Output (POUT)

1 1 1 1 Toggle mode: a Time r 2 compa re matc h

toggles the output flip-flop (M2) -> T2O

2 1 1 0 Duty cycle b urst genera tor 1: the DCG output

signal (DCG0) is given to the output and

gate d by the output flip-flop (M2)

3 1 0 1 Duty cycle b urst genera tor 2: the DCG output

signal (DCGO) is given to the outp ut and

gated by the SSI internal data output (SO)

4 1 0 0 Biphase modulator: Timer 2 modulates the

SSI internal data output (SO) to Biphase

code

5 0 1 1 Manchester modulator: Timer 2 modulates

the SSI internal data output (SO) to

Manchester code

6 0 1 0 SSI output: T2O is used directly as S SI

internal data output (SO)

7 0 0 1 PWM mode: an 8/12-bit PWM mode

8 0 0 0 Not allowed

T48C862-R3

4554A–4BMCU–02/03

Timer 2 Compare and

Compare Mode Registers Tim er 2 h as tw o separ ate com pare regis ters, T2 CO1 for t he 4-bi t sta ge an d T2CO 2 for

the 8-bit stage of Timer 2. The timer compares the contents of the compare register cur-

rent counter value and if it matches it generates an output signal. Dependent on the

timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop

as SSI clock or as a clock for the next counter stage.

In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit

compare value. In all other modes, the two compare registers work independently as a

4- and 8-bit compare register.

When assigned to the compare register a compare event will be suppressed.

Timer 2 Compare Mode

Reg i ster (T2C M) Address: "7"hex - Subaddress: "3"hex

Timer 2 COmpare Register 1

(T2CO1) Address: "7"hex - Subaddress: "4"hex

In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.

Bit 3Bit 2Bit 1Bit 0

T2OTM T2CTM T2RM T2IM Reset value: 0000b

T2OTM Timer 2 Overflow Toggle Mask bit

T2OTM = 0, disable ov erflow toggle

T2OTM = 1, enable ov erflow toggle, a counter overflow (OVF2) toggles output

flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow can

generate an interrupt except on the Timer 2 output mode 7.

T2CTM Timer 2 Compare Toggle Mask bit

T2CTM = 0, disabl e compare toggle

T2CTM = 1, enable compare t oggle, a match of the counter with the compare

when the T2CTM-bit is set, only a ma tch of the counter with the

compare register can generate an interrupt.

T2RM Timer 2 Reset Mask bit

T2RM = 0, disable counter reset

T2RM = 1, enable counter reset, a match of the counter with the compare register

resets the counter

T2IM Timer 2 Interrupt Mask bit

T2IM = 0, disable Timer 2 interrupt

T2IM = 1, enable Timer 2 interrupt

Timer 2 Output Mode T2OTM T2CTM Timer 2 Interrupt Source

1, 2, 3, 4, 5 and 6 0 x Compare match (CM2)

1, 2, 3, 4, 5 and 6 1 x Overflow (OVF2)

7 x 1 Compare match (CM2)

Write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b

54 T48C862-R3 4554A–4BMCU–02/03

Timer 2 COmpare Register 2

(T2CO2) Byte Write Address: "7"hex - Subaddress: "5"hex

Timer 3

Features •Two Compa r e Registe r s

•Capture Register

•Edge Sensitive Input with Zero Cross Detection Capability

•Trigger and Si ngle Action Modes

•Output Control Modes

•Automatically Modulation and Demodulation Modes

•FSK Modulat ion

•Pulse width Modulation (PWM)

•Manchester Demodulation Together with SSI

•Biphase Demodulation Together with SSI

•Pulse-width Demodulation Together with SSI

Figure 50. Time r 3

Fir st write c ycle Bit 3 Bit 2 Bit 1 Bit 0 Res et v alu e: 1111 b

Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b

8-bit comparator

Compare register 1

RES

Capture register

8-bit counter

Compare register 2

Control C31

C32

Control

T3SM1

NQ DT3RM1 T3IM1 T3TM1

TOG2 T3I

T3TM2T3IM2T3RM2T3SM2

NQ D

CL3

T3EIM

TOG3

INT5

CM31

CM32

: T3M1

: T3M2

T48C862-R3

4554A–4BMCU–02/03

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture reg-

ister. The timer can be used as event counter, timer and signal generator. Its output can

be pro grammed as modul ator and d emodulat or for the serial interface. The two com-

pare registers enable various modes of signal generation, modulation and

demodulation. The counter can be driven by internal and external clock sources. For

external clock sources, it has a programmable edge-sensitive input which can be used

as counter input, capture signal input or trigger input. This timer input is synchronized

with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-

Stop -> ye s) , th is ti mer i npu t is s topp ed too. Th e coun ter is readable via its c aptu re r eg-

ister while it is running. In capture mode, the counter value can be captured by a

programmable capture event from the Timer 3 input or Timer 2 output.

A special feature of this timer is the trigger- and single-action mode. In trigger mode, the

counter starts counting triggered by the external signal at its input. In single-action

mode, the counter counts only one time up to the programmed compare match event.

These m odes are very usef ul for modulation , demodulati on, signal gene ration, signal

measurement and phase controlling. For phase controlling, the timer input is protected

against negative voltages and has zero-cross detection capability.

Timer 3 has a modulator output stage and input functions for demodulation. As modula-

tor it work s together with Time r 2 or the serial interfac e. When the shift regis ter is use d

for modulation the data shifted out of the register is encoded bitwise. In all demodulation

modes, the decoded data bits are shifted automatically into the shift register.

Timer/Counter Modes Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via

the Timer 3 Mode Register T3M.

In all the se mod es , the co mpa re regi st er and the co mpa re -m ode regi ste r bel ong ing to i t

define the counter value for a compare match and the action of a compare match. A

match of the current counter value with the content of one compare register triggers a

counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare

mode regis ters T3M1 an d T3M2 con tain the mask bits for enabl ing or di sabling these

actions.

The c ounter can also b e enabled to exec ute singl e action s with o ne or bo th compar e

regis ters. If thi s mode is set the corr esp ondin g c ompare m atch event is gene rate d on ly

once after the counter start.

Most of the timer modes use their compare registers alternately. After the start has been

activated, the first com parison is carried out via the compare register 1, the sec ond is

carried out via the compare register 2, the third is carried out again via the compare reg-

ister 1 and so on. This makes it easy to generate signals with constant per iods and

variable duty cycle or to generate signals with variable pulse and space widths.

If single-action mode is set for one compare register, the comparison is always carried

out after the first cycle via the other compare register.

The co unter can be started an d stoppe d via the control reg ister T3 C. This regi ster als o

contro ls the init ial leve l of the output bef ore star t. T3C contain s the interr upt mask for a

T3I input interrupt.

Via the Timer 3 clock-select register, the internal or external clock source can be

selecte d. This registe r sele cts al so the act ive edge of the exter nal inp ut. An edge at the

extern al in put T3I can gener ate also an i nterrup t if the T3E IM-b it is se t and the Ti mer 3

is stopped (T3R = 0) in the T3C-register.

56 T48C862-R3 4554A–4BMCU–02/03

Figure 51. Counter 3 Stage

The status of the timer as well as the occurrence of a compare match or an edge detect

of the input signal is indicated by the status register T2ST. This allows identification of

the interrupt source because all these events share only one timer interrupt.

Timer 3 compares data values

The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value

can be ‘m’ for each of the Timer 3 compare registers.

The compare data value for the compare registers is: m = x +1 0 £ x £ 255

Timer 3 – Mode 1:

Timer/Counter The selected clock from an inter nal or external source increments the 8-bit counter. In

this mode , the tim er ca n be use d as even t counte r for ex ternal c locks a t T3I or as timer

for generati ng inte rrupts and pulses at T3O. T he co unter val ue can be r ead by th e soft-

ware via the capture register.

8-bit comparator

Compare register 1

RES

Capture register

8-bit counter

Compare register 2

Control C31

C32

Control

T3SM1

NQ DT3RM1 T3IM1 T3TM1

TOG2 T3I

T3TM2T3IM2T3RM2T3SM2

NQ D

CL3

T3EIM

TOG3

INT5

CM31

CM32

: T3M1

: T3M2

T48C862-R3

4554A–4BMCU–02/03

Figure 52. Counter Reset with Each Compare Match

Figure 53. Counter Reset with Compare Register 2 and Toggle with Start

Figure 54. Single Action of Compare Register 1

Timer 3 – Mode 2:

Timer/Counter, External

Trigger Restart and External

Capture (with T3I Input)

The cou nter is driven by an internal clock sourc e. After star ting with T3R, the first edge

from the ex ternal input T3I starts the counter. The following edges at T3I load the cur-

rent counter value into the ca pture register, r eset the counter a nd restart it. The ed ge

can be selected by the programmable edge decoder of the timer input stage. If single-

action mode is activated for one or both compare registers the trigger signal restarts the

single ac tio n.

0000123 51234 00123 12

T3R

Counter 3

CM31

INT5

T3O

CM32

4000123 567 40123 56

T3R

Counter 3

CM31

INT5

T3O

Toggle

by start

T3O

CL3

CM32

0012345678910012

Counter 3

CM31

CM32

T3O

01201201201201201201201201

Toggle by start

T3R

58 T48C862-R3 4554A–4BMCU–02/03

Figure 55. Ext ernal ly Trig gered Counter Reset an d Start C ombine d with Sing le-ac tion

Mode

Timer 3 – Mode 3:

Timer/Counter, Internal

Trigger Restart and Internal

Capture (with TOG2)

The counter is driven by an internal or external (T3I) clock source. The output toggle sig-

nal of Timer 2 resets the counter. The counter value before the reset is saved in the

capture register. If single-action mode is activated for one ore both compare registers,

the trigger signal restarts the single actions. This mode can be used for frequency mea-

surements or as event counter with time gate (see combination mode 10).

Figure 56. Event Counter with Time Gate

Timer 3 – Mode 4:

Timer/Counter The timer runs as timer/counter in mode 1, but its output T3O is used as output for the

Timer 2 output signal.

Timer 3 – Mode 5:

Timer/Counter, External

Trigger Restart and External

Capture (with T3I Input)

The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the

Timer 2 output signal.

Timer 3 Modulator/Demodulator Modes

Timer 3 – Mode 6:

Carrier Frequency Burs t

Modulation Controlled by

Timer 2 Output Toggle

Flip-Flop (M2)

The Time r 3 count er is driv en by an in ternal or external clock sou rce. Its co mpare- an d

compar e mode registe rs must be programmed to generate the carr ier freque ncy via the

output tog gle flip-flop. The output toggle flip-flop of Timer 2 is used to enab le or disable

the Tim er 3 output. Time r 2 can be driv en by the toggl e output sig nal of Timer 3 or any

other clock source (see combination mode 11).

Timer 3 – Mode 7:

Carrier Frequency Burs t

Modulation Controlled by SSI

Internal Output (SO)

The Time r 3 count er is driv en by an in ternal or external clock sou rce. Its co mpare- an d

compar e mode registe rs must be programmed to generate the carr ier freque ncy via the

output to ggle fli p- flo p. The ou tput ( SO) of the S SI is us ed to en abl e or dis able the Ti mer

3 output. The SSI should be supplied with the toggle signal of Timer 2 (see combination

mode 12).

00000000123456

Counter 3

T3EX

CM31

CM32

78910012XXX012345678910012XX

T3R

T3O

0012345678910

Counter 3

TOG2

T3CP-

11 0 1 2 401

T3I

T3R

Capture val ue = 0 Capture value = 11 Capture

value = 4

T48C862-R3

4554A–4BMCU–02/03

Timer 3 – Mode 8:

FSK Modulation with Shift

Reg ister Data (SO)

The two compar e registers are used for gen erating two di fferent time intervals. T he SSI

interna l data out put (SO) sel ects which compare regi ster is u se d for the output fre-

quency g ene ra tio n. A "0 " l ev el a t the SS I da ta ou tput enable s t he c om par e reg is ter 1. A

"1" level enables compare register 2. The compare- and compare-mode registers must

be pro gram med t o gen erate the two freq ue ncies via the o utput toggl e fli p-flop . Th e SS I

can be supplied with the toggle signal of T imer 2. The Timer 3 counter is driven by an

internal or external clock source. The Timer 2 counter is driven by the Counter 3 (TOG3)

(see also combination mode 13).

Figure 57. FSK Modulation

Timer 3 – Mode 9:

Pulse-width Modulation with

the Shift Register

The two compar e registers are used for gen erating two di fferent time intervals. T he SSI

internal data output (SO) selects which compare register is used for the output pulse

generation. In this mode both compare- and com pare-mode registers mu st be pro-

grammed for generating the two pulse widths. It is also useful to enable the single-action

mode for extreme duty cycles. Timer 2 is used as baudrate generator and for the trigger

restart of Timer 3. The SSI must be supplied with a toggle signal of Timer 2. The counter

is driven by an internal or external clock source (see combination mode 7).

Figure 58. Pulse-width Modulation

Timer 3 – Mode 10:

Manchester

Demodulation/Pulse-width

Demodulation

For Manche ste r dem odu la tion , the edge detec ti on sta ge must be pr ogr am me d to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage is used to generate the s hift clock for th e SSI. The com pare register 1 matc h

event defines the correct moment for shifting the state from the input T3I as the decoded

bit into shift register - after that the demodulator waits for the next edge to synchronize

the timer by a reset for the next bit. The compare register 2 can also be used to detect a

time-out error and handle it with an interrupt routine (see also combination mode 8).

01234012340123

Counter 3

CM31

CM32

40120120120120120120120123

T3R

T3O

01 0

000000000 0000

Counter 3

CM31

CM32

T3O

00000123456789101112131415012345

TOG2

678

9111210 1413 0 2 314150

00 1

SIR

SCO

T3R

60 T48C862-R3 4554A–4BMCU–02/03

Figure 59. Manchester Demodulation

Timer 3 – Mode 11:

Biphase Demodulation In the Biphase demodulation mode, the timer operates like in Manchester demodulation

mode. The difference is that the bits are decoded via a toggle flip-flop. This flip-flop sam-

ples the edge in the middle of the bitframe and the compare register 1 match event

shifts the toggle flip-flop output into shift register (see also combined mode 9).

Figure 60. Biphase Demodulation

1011100 110

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6

Synchronize Manchester demodulation mode

Timer 3

mode

T3EX

SR-DATA

T3I

CM31=SCI

100110

011 1 1

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6

Synchronize Biphase demodulation mode

Timer 3

mode

T3EX

Q1=SI

CM31=SCI

SR-DATA

0000

T3I

Reset

Counter 3

101010

T48C862-R3

4554A–4BMCU–02/03

Timer 3 – Mode 12:

Timer/Counter with External

Capture Mode (T3I)

The counter is driven by an internal clock source and an edge at the external input T3I

loads the counter value into the capture register. The edge can be selected with the pro-

grammable edge detector of the timer input stage. This mode can be used for signal and

pulse measurements.

Figure 61. External Capture Mode

Timer 3 Modulator for

Carrier Frequenc y Bur st

Modulation

If the output stage oper ates as puls e-width mod ulator for the shift regis ter, the output

can be stopped with stage 1 of Timer 2. For this task, the timer m ode 3 must be used

and the prescaler must be supplied by the internal shift clock of the shift register.

The modulator can be started with the start of the shift register (SIR = 0) and stopped

either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2.

For this task, the Timer 2 must be used in mode 3 and the prescaler stage must be sup-

plied by the internal shift clock of the shift register.

Figure 62. Modulator 3

Timer 3 Demodulator for

Biphase, Manchester and

Pulse-width-modulated

Signals

The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and

pulse-width-coded signals.

Figure 63. Timer 3 Demodulator 3

01234567891011

Counter 3

T3CP-

T3I

T3R

Capture value = X Capture value = 17 Capture

value = 35

0 121314 16 20171819 2221 23 27242526 2928 30 34313233 3635 37 41383940

Set Res

T3O

T3TOP

OMSK

TOG3

SSI/

Control

MUX

T3M

Timer 3 Mode T3O

6 MUX 1

7 MUX 2

9 MUX 3

other MUX 0

Demodulator 3

T3EX Res

CM31 Counter 3

Reset

Counter 3

Control

SCI

T3I

T3M

62 T48C862-R3 4554A–4BMCU–02/03

Timer 3 Regi sters

Timer 3 Mode Register (T3M) Address: "B"hex - Subaddress: "0"hex

Note: 1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All

other SSI modes are not allowed.

Bit 3Bit 2Bit 1Bit 0

T3M3 T3M2 T3M1 T3M0 Reset value: 1111b

T3M3 Timer 3 Mode select bit 3

T3M2 Timer 3 Mode select bit 2

T3M1 Timer 3 Mode select bit 1

T3M0 Timer 3 Mode select bit 0

Mode T3M3 T3M2 T3M1 T3M0 Timer 3 Modes

11111Timer/counter with a read access

21110Timer/counter, external capture and external

trigger restart mode (T3I)

31101Timer/counter, internal capture and internal

trigger restart mode (TOG2)

41100Timer/counter mode 1 without output

(T2O -> T3O)

51011Timer/counter mode 2 without output

(T2O -> T3O)

61010Burst modulation with Timer 2 (M2)

71001Burst modulation with shift register (SO)

81000FSK modulation with shift register (SO)

90111Pulse-width modulation with shift register (SO)

and Timer 2 (TOG2), internal trigger restart

(SCO) -> counter reset

100110Manchester demodulation/pulse-width

demodulation (1) (T2O -> T3O)

110101Biphase demodulation (T2O -> T3O)

120100Timer/counter with external capture mode (T3I)

130011Not allowed

140010Not allowed

150001Not allowed

160000Not allowed

T48C862-R3

4554A–4BMCU–02/03

Timer 3 Control Register 1

(T3C) Write Primary register address: "C"hex - Write

Timer 3 Status Register 1

(T3S T) Read Primary register address: "C"hex - Read

Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.

Timer 3 Clock Select Register

(T3CS) Address: "B"hex - Subaddress: "1"hex

Bit 3Bit 2Bit 1Bit 0

Write T3EIM T3TOP T3TS T3R Res e t value: 0000b

T3EIM Timer 3 Edge Interrupt Mask

T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)

T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)

T3TOP Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0"

T3TOP = 1, sets toggle output (M3) to "1"

Note: If T3R = 1, no output preset is possible

T3TS Timer 3 Toggle w ith Start T3TS = 0, Timer 3 ou tpu t is no t tog gle d during th e sta rt

T3TS = 1, Timer 3 output is toggled if started wit h T3R

T3R Timer 3 Run T3R = 0 , Timer 3 stop and reset

T3R = 1, Timer 3 run

Bit 3Bit 2Bit 1Bit 0

Read - - - T3ED T3C2 T3C1 Reset value: x000b

T3ED Timer 3 Edge Detect

This bit will be set by the edge-detect logic of Timer 3 input (T3I)

T3C2 Timer 3 Compare 2

This bit will be set when a match occurs between Counter 3 and T3CO2

T3C1 Timer 3 Compare 1

This bit will be set when a match occurs between Counter 3 and T3CO1

Bit 3 Bit 2 Bit 1 Bit 0

T3CS T3E1 T3E0 T3CS1 T3CS0 Reset value: 1111b

T3E1 Timer 3 Edge selec t bit 1 T3E1 T3E0 Timer 3 Input Edge Select (T3I)

T3E0 Timer 3 Edge selec t bit 01 1 - - -

1 0 Positive edge at T3I pi n

0 1 Neg a tive edge at T3I pin

0 0 Each edge at T3I pi n

64 T48C862-R3 4554A–4BMCU–02/03

Timer 3 Compare- and

Compare-mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of

Timer 3. The timer compares the content of the compare register with the current

counter value. If both match, it generates a signal. This signal can be used for the

counter res et, to gene ra te a ti me r in ter rupt, for to ggl in g th e o utp ut f li p-flo p, a s SS I c lock

or as clock for the next counter stage. For each compare register, a compare-mode reg-

ister exis ts. These regi sters contai n mask bits to enable or disable the generati on of an

interrupt, a counter reset, or an output toggling with the occurrence of a compare match

of the corresponding compare register. The mask bits for activating the single-action

mode can also be located in the compare mode registers. When assigned to the com-

pare register a compare event will be suppressed.

Timer 3 Compare-Mode

T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1

T3CS1 Timer 3 Clock Source sele ct bit 1 T3CS1 TCS0 Counter 3 Input Signal (CL3)

T3CS0 Timer 3 Clock Source sele ct bit 01 1 System clock (SYSCL)

1 0 Output signal of Timer 2 (POUT)

0 1 Output signal of Timer 1 (T1OUT)

0 0 External input signal fro m T3I e dge

detect

Bit 3Bit 2Bit 1Bit 0

T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b

T3SM1 Timer 3 Single action Mask bit 1

T3SM1 = 0, disables single-action compare mode

T3SM1 = 1, enables single-compare mode. A fter this bit is set, the compare

T3TM1 Timer 3 compare Toggle action Mask bit 1

T3TM1 = 0, disables compare toggle

T3TM 1 = 1, enab les compare toggle . A match of Co unter 3 with the compare

T3RM1 Timer 3 Reset Mask bit 1

T3RM1 = 0, disables counter reset

T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare

T3IM1 Timer 3 Interrupt Mask bit 1

T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.

T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.

T48C862-R3

4554A–4BMCU–02/03

Timer 3 Compare Mode

T3CM2 contains the mask bits for the match event of Counter 3 compare register 2

The compare registers and corresponding counter reset masks can be used to program

the counter time intervals and the toggle masks can be used to program output signal.

The si ngle- ac tion mask ca n also be u se d i n th is mo de. It s ta rts o per at ing aft er the ti mer

started with T3R.

Timer 3 COmpare Register 1

(T3CO1) Byte Write Address: "B"hex - Subaddress: "4"hex

Timer 3 COmpare Register 2

(T3CO2) Byte Write Address: "B"hex - Subaddress: "5"hex

Bit 3Bit 2Bit 1Bit 0

T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b

T3SM2 Timer 3 Single action Mask bit 2

T3SM2 = 0, disables single-action compare mode

T3SM2 = 1, enables single-compare mode. A fter this bit is set, the compare

T3TM2 Timer 3 compare Toggle action Mask bit 2

T3TM2 = 0, disables compare toggle

T3TM 2 = 1, enab les compare toggle . A match of Co unter 3 with the compare

T3RM2 Timer 3 Reset Mask bit 2

T3RM2 = 0, disables counter reset

T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare

T3IM2 Timer 3 Interrupt Mask bit 2

T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.

T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.

High Nibble

Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b

Low Nibble

First write cycle Bit 3 Bit 2 Bit15 Bit 0 Reset value: 1111b

High Nibble

Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b

Low Nibble

First write cycle Bit 3 Bit 2 Bit15 Bit 0 Reset value: 1111b

66 T48C862-R3 4554A–4BMCU–02/03

Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the

capture register. In modes 1 and 4, it is possible to read the current counter value

direct ly out of the c aptu re regis ter. In the cap tur e mod es 2, 3, 5 and 12, a capture event

like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter

value into the capture register. This counter value can be read from the capture register.

Timer 3 CaPture Register

(T3CP) Byte Read Address: "B"hex - Subaddress: "4"hex

Synchronous Serial Interface (SSI)

SSI Features: • With Timer 1:

– 2- and 3-wire NRZ

– 2-wire mode multi-chip link mode (MCL), additional internal 2-wire link for

multi-chip packaging solutions

• With Timer 2:

– B i phas e mod ula tio n

– Manchester modulation

– Pulse-width demodulation

– Burst modulation

• With Timer 3:

– Pulse-width modulation (PWM)

– FSK modulation

– B i phas e dem odu lation

– Manchester demodulation

– Pulse-width demodulation

– Pulse position Demodulation

High Nibble

First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb

Low Nibble

Second read cycle Bit 3 Bit 2 Bit15 Bit 0 Reset value: xxxxb

T48C862-R3

4554A–4BMCU–02/03

SSI Peripheral Configuration The synchr on ous seri al in terf ace (S S I) can be us ed eit her f or seria l com mun ic ation wi th

extern al devices such as EEPRO Ms, shift re gisters, di splay dr ivers, oth er microc ontrol-

lers, or as a means for generating and capturing on-chip serial streams of data. External

data communication takes place via the Port 4 (BP4),a multi-functional port which can

be software configured by writing the appropriate control word into the P4CR register.

The SSI can be configured in any of the following ways:

1. 2-wire external interface for bi-directional data communication with one data ter-

minal and one shift clock. The SSI uses the Port BP43 as a bi-directional serial

data line (SD) and BP40 as shift clock line (SC).

2. 3-wire external interface for simultaneous input and output of serial data, with a

serial input data terminal (SI), a serial output data terminal (SO) and a shift clock

(SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is

applied to BP43 (configured in P4CR as input!). Serial output data (SO) in this

case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2

output stage (T2M2 configured in mode 6).

3. Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is

capable of performing a variety of data modulation and demodulation functions

(see Timer Section). The modulating data is converted by the SSI into a continu-

ous serial stream of data which is in turn modulated in one of the timer functional

blocks. Serial demodulated data can be serially captured in the SSI and read by

the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI

can only be used as demodulator.

4. Multi-chip link (MCL) – the SSI can also be used as an interchip data interface f or

use in single package multi-chip modules or hybrids. For such applications, the

SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a

two-wire chip-to-chip link. The MCL can be activated by the MCL control bit.

Should these MCL pads be used by the SSI, the standard SD and SC pins are

not required and the corresponding Port 4 ports are available as conventional

data ports.

Figure 64. Block Diagram of the Synchronous Serial Interface

8-bit Shift Register

MSB LSB

Shift_CL

SIC1 SIC2 SISC

SC Control

STB SRB

Timer 2 / Timer 3

Output

INT3 SC

I/O-bus

SSI-Control

TOG2

POUT

T1OUT

SYSCL

SO SI

MCL_SC

MCL_SD

Transmit

Buffer Receive

Buffer

SCI

68 T48C862-R3 4554A–4BMCU–02/03

General SSI Operation The SSI i s c omprise d ess entia lly of an 8 -bit sh ift regist er wi th two a ssoci ated 8- bit b uff-

ers – the receiv e buffer (SRB) for capturing the inc oming serial data and a trans mit

buffer (S TB) for intermediate storage of data to be serially output. Both buf fers are

directly accessa ble by softwar e. Transfer ring the para llel buffer data in to and out of the

shift register is controlled automatically by the SSI control, so that both single byte trans-

fers or continuous bit streams can be supported.

The SSI can generate the shift clock (SC) either from one of several on-chip clock

sources or accept an external clock. The external shift clock is output on, or applied to

the Port BP40 . Selection of an external cl ock source is performed by the Serial Clock

Direction control bit ( SCD). In the combinational modes, the required clock is selected

by the corresponding timer mode.

The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a

9-bit Mu lti-Chip Link Mode (MCL), or 8- bit pseudo MCL protocol (w ithout ackn owledge-

bit).

External SSI clocking is not supported in these modes. The SSI should thus gener ate

and has full control over the shift clock so that it can always be regarded as an MCL bus

maste r devic e.

All dire ctional contr ol of the external data port used by the SSI is hand led automatic ally

and is dependent on the transmission direction set by the Serial Data Direction (SDD)

control bit. This control bit defines whether the SSI is currently operating in Transmit

(TX) mode or Receive (RX) mode.

Serial data is organi zed in 8-bi t telegram s wh ich are shift ed with t he mo st signi fica nt bit

first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the

telegram for handshaking purposes (see MCL protocol).

At the beginning of every telegram, the SSI control loads the transmit buffer into the shift

regist er and proceed s im mediate ly to shift data s erially out. A t the s ame ti me, in comin g

data is sh ifted into the shi ft register in put. This inco ming data is a utomatically loaded

into the receive buffer when the complete telegram has been received. Thus, data can

be simultan eou sl y re ce iv ed and tra nsm itted if required.

Before data can be transferred, the SSI must first be activated. This is performed by

means of the SS I reset control (SIR) bit. All further oper ation then depe nds on the data

directional mod e (TX/RX) and the present status of the SSI buffer registers sh own by

the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the

(empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX

mode). The control logic ensures that data shifting is temporarily halted at any time, if

the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will

then au tomatica lly be se t back to ‘1’ an d data shi fting re sumed as so on as the ap plica-

tion software loads the new data into the transmit register (in TX mode) or frees the shift

A further activity status (ACT) bit indicates the present status of the serial communica-

tion. The ACT bit remains high for the duration of the serial telegram or if MCL stop or

start conditions are currently being generated. Both the current SRDY and ACT status

can be read in the SSI st atus register. To deac tivate the SSI, the SIR bit must be s et

high.

T48C862-R3

4554A–4BMCU–02/03

8-bit Synchronous Mode Figure 65. 8-bit Synchronous Mode

In the 8 -bit sy nchronous mode, the SSI c an operat e as e ither a 2 - or 3-wire inte rface

(see SSI peripheral configuration). Th e serial data (SD) is receiv ed or transmitted in

NRZ format, sy nchroni zed to either the rising or fallin g edge of the sh ift clock (SC). The

choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be

noted that the transmission edge refers to the SC clock edge with which the SD

changes . To av oi d c lock s kew prob lem s, the i nc om ing se rial in put d ata i s sh ifte d i n with

the opposite edge.

When used together with one of the timer modulator or demodulator stages, the SSI

must be set in the 8-bit sync hron ous mode 1.

In RX mode, a s s oo n as the SSI is ac tiv at ed (SI R = 0 ), 8 shift clock s are ge ner ate d an d

the incoming serial data is shifted into the shift register. This first telegram is automati-

cally transferred into the receive buffer and the SRDY set to 0 indicating that the receive

buffer contains valid data. At the same time an interrupt (if enabled) is generated. The

SSI then c ontinues shi fting in the fo llowing 8-bi t telegram. If, du ring this tim e the first

telegram has been read by the controller, the second telegram will also be transferred in

the same way into the rec eive bu ffer and the SS I wil l contin ue cloc king in the n ext tel e-

gram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI

will stop, temporarily holding the second telegram in the shift register until a certain point

of time when the controller is able to service the receive buffer. In this way no data is lost

or overwritten.

Deactiv atin g the SSI (SI R = 1) in mid-te le gram wi ll i mmed iatel y st op th e sh ift c lock and

latch the present contents of the shift register into the receive buffer. This can be used

for clocking in a data telegram of less than 8 bits in length. Care should be taken to read

out the final co mplete 8 -bi t data tele gram o f a m ultip le wo rd m essage befo re d eactiv at-

ing the SSI (SIR = 1) and terminating the reception. After termination, the shift register

contents will over write the re ce iv e buffer.

DATA

SD/TO2

110 101

Bit 7 Bit 0

110 101

Bit 7 Bit 0

Data: 00110101

(Rising edge)

(Falling edge)

70 T48C862-R3 4554A–4BMCU–02/03

Figure 66. Example of 8-bit Synchronous Transmit Operation

Figure 67. Example of 8-bit Synchronous Receive Operation

9-bit Shift M ode (MCL) In the 9-bi t shift mod e, the SSI is abl e to handle th e MCL proto col (describ ed belo w). It

alway s operat es as an MCL master d evice, i .e., SC is a lways ge nerated a nd outpu t by

the SS I. Bo th th e MCL sta rt a nd sto p co nditi ons are a utomat icall y ge nera ted w henev er

the SSI is acti va ted or d eac tivated by the S IR-bit . In ac c ordanc e wit h th e MCL pr otocol ,

the output data is always changed in the clock low phase and shifted in on the high

phase.

7654321 0 765432107654321 0

msb lsb

tx data 1 tx data 2 tx data 3

msb lsb msb lsb

Write STB

(tx data 2) Write STB

(tx data 3)

Write STB

(tx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

43210 76543210

msb lsb

rx data 1 rx data 2 rx data 3

msb lsb msb lsb

Read SRB

(rx data 2) Read SRB

(rx data 3)

Read SRB

(rx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

765 43210765 7654

T48C862-R3

4554A–4BMCU–02/03

Befor e activating the SSI (SIR = 0) and comme ncing an M CL dialog, th e appropri ate

data direction for the first word must be set using the SDD control bit. The state of this

bit controls the direction of the data port (BP43 or MCL_SD). Once star ted, the 8 data

bits are, depending on the selected direction, either clocked into or out of the shift regis-

ter. During the 9t h clock pe riod, the port direct ion is automa tically switche d over so that

the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the

acknowledge bit received from the device is captured in the SSI Status Register (TACK)

where it can be read by the controller. In receive mode, the state of the acknowledge bit

to be returned to the device is predetermined by the SSI Status Register (RACK).

Changing the directional mode (T X/RX) should not be performed during the transfer of

an MC L tele gram. O ne s hould wait u ntil the en d of t he tel egram which can b e de tecte d

using the SSI interrupt (IFN =1) or by interrogating the ACT status.

Once star ted, a 9- bit teleg ram wi ll alway s run to c ompleti on and wi ll not be premat urely

terminated by the SIR bit. So, if the SIR-bit is set to ‘1’ in telegram, the SSI will complete

the current transfer and terminate the dialog with an MCL stop condition.

Figure 68. Example of MCL Transmit Dialog

7654321 76543210A

msb lsb

tx data 1 tx data 2

msb lsb

Write STB

(tx data 1)

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Write STB

(tx data 2)

SIR

SDD

Start Stop

72 T48C862-R3 4554A–4BMCU–02/03

Figure 69. Example of MCL Receive Dialog

8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the

acknowledge-bit which is never expected or transmitted.

7654321 76543210A

msb lsb

tx data 1 rx data 2

msb lsb

Write STB

(tx data 1)

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Read SRB

(rx data 2)

SIR

SDD

Start Stop

T48C862-R3

4554A–4BMCU–02/03

MCL Bus Protocol The MCL proto col const itutes a simple 2- wire bi-direc tional com municati on highway vi a

which de vice s can commu nica te cont rol a nd data i nformati on. Al though the M CL pro to-

col can sup port multi-maste r bus configurations, the S SI in MCL mode is intended for

use purely as a master controller on a single master bus system. So all reference to

multiple bus control and bus contention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit.

Normally the communication channel is opened with a so-called start condition, which

initializes all devices connected to the bus. This is then followed by a data telegram,

transmitted by the mas ter controller device. This telegram u sually contai ns an 8-bit

address code to activate a single slave device connected onto the MCL bus. Each slave

receiv es this address and compar es it with its ow n unique add ress. The addr essed

slave device, if read y to receiv e data, will respond by pulling the SD line low duri ng the

9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting

this affirmative a cknowledge then opens a connection to the req uired slave. Data can

then be passed back and forth by the master controller, each 8-bit telegram being

acknowledged by the respecti ve recipient. The communication is finally closed by the

master device and the slave device put back into standby by applying a stop condition

onto the bus.

Figure 70. MCL Bus Protocol 1

Bus not busy (1) Both data and clock lines remain HIGH.

Start data transfer (2) A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition

Stop data transfer (3) A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

Data valid (4) The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

(2)(1) (4) (4) (3) (1)

Start

condition Data

valid Data

change Data

valid Stop

condition

74 T48C862-R3 4554A–4BMCU–02/03

Figure 71. MCL Bus Protocol 2

SSI Interrupt The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,

transm it buffer emp ty or receiv e buffer full) , the end of SS I data teleg ram or on the fall-

ing edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed

by the I nterrupt Func tioN contro l bit ( IFN). The S SI in terrupt is u suall y used to sy nchro-

nize the software control of the SSI and inform the controller of the present SSI status.

The Port 4 interrup ts can be used to gether with the SSI or, if the SSI itself is not

requir ed, as add itiona l external interru pt sour ces. In ei ther case this inte rru pt is capabl e

of waking the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and

the Int errupt Func tion (IF N) whi le the Port 4 inter rupts are enab led by setting approp ri-

ate control bits in P4CR register.

Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodula-

tion pur poses, the 8-bit sy nchron ous mo de must be u sed. In this cas e, the un used Por t

4 pins can be used as conventional bi-directional ports.

The modulation and demodulation stages, if enabled, operate as soon as the SSI is acti-

vated (SIR = 0) and cease when deactivated (SIR = 1).

Due to the byte- orientated data control, the S SI (when running nor mally) generates

serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) func-

tion pe rmits; h owever, the gen eration of bit stre ams of a ny length . The OMS K signal is

derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable

number of unrequired trailing data bits during the shifting out of the final data word in the

bit stream. The number of non-masked data bits is defined by the value pre-pro-

grammed in th e pr esca ler c omp ar e regi ste r. To use outp ut maskin g, the modu la tor sto p

mode bit ( MSM) mus t be set to "0" be fore prog ramming the final data word in to the SS I

transmit b uffer. This in turn , enabl es shif t clocks to the p rescaler whe n this final wo rd is

shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and

all following data bits are blanked.

SD Start

1n89

1st Bit 8th Bit ACK Stop

T48C862-R3

4554A–4BMCU–02/03

Figure 72. SSI Output Masking Function

Serial In terface Registers

Serial Interface Control

Note: This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 o r 11

• In Transmit mode (SDD = 1) shifting starts only if the transmit buff er has been

loaded (SRDY = 1).

• Setting SIR-bit loads the contents of the shift register into the receive buffer

(synchronous 8-bit mode only).

• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1

generates a stop condition.

8-bit shift register

MSB LSB

Shift_CL

Control

Timer 2

Output

SSI-control

Com pare 2/1

4-bit counter 2/1

CL2/1

SCL

CM1 OMSK

TOG2

POUT

T1OUT

SYSCL /2

Bit 3Bit 2Bit 1Bit 0

SIR SCD SCS1 SCS0 Reset value: 1111b

SIR Serial Interface Reset

SIR = 1, SSI inactive

SIR = 0, SSI active

SCD Serial Clock Direction

SCD = 1, SC line us ed as output

SCD = 0, SC line used as input

SCS1 Serial Clock source Sele ct bit 1 SCS1 SCS0 Internal Clock for SSI

SCS0 Serial Clock source Sele ct bit 01 1 SYSCL/2

1 0 T1OUT/2

Note: with SCD = 0 the bits SCS1 0 1 POUT/2

and SCS0 are insignificant 0 0 TOG2/2

76 T48C862-R3 4554A–4BMCU–02/03

Serial Interface Control

Note: SDD controls port directional control and defines the reset function for the SRDY-flag

Bit 3Bit 2Bit 1Bit 0

MSM SM1 SM0 SDD Reset value: 1111b

MSM Modular Stop Mode

MSM = 1, modulator stop mode disabled (output masking off)

MSM = 0, modulator stop mode enabled (output masking on) - used in

modulation modes for generating bit streams which are not sub–multiples of 8

bits.

SM1 Serial Mode con trol bit 1

SM0 Serial Mode con trol bit 0

Mode SM1 SM0 SSI Mode

1 1 1 8-bit NRZ-Data changes with the rising edge of SC

2 1 0 8-bit NRZ-Data changes with th e falling edge of SC

3 0 1 9-bit two-wire MCL mode

4 0 0 8-bit two-wire MCL mode (no acknowledge)

SDD Serial Data Direction

SDD = 1, transmit mode – SD l ine us ed a s ou tpu t (tr ans m it data). S RDY is se t

b y a transmit buffer write access.

SDD = 0, receive mode – SD line used as input (receive data) . SRDY is set

by a receive b u ffer read access

T48C862-R3

4554A–4BMCU–02/03

Serial Interface Status and

Control Register (SISC) Primary register address: "A"hex

Serial Transmit Buffer (STB) –

Byte Write Primary register address: "9"hex

The STB is the tran sm it b uffe r of th e SS I. T he SS I t ransfers the tran sm it b uffe r int o the sh ift re gis-

ter and starts shifting with the most significant bit.

Serial Receive Buffer (SRB) –

Byte Read Primary register address: "9"hex

The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant

bit first) and loads content into the receive buffer when complete telegram has been received.

Bit 3Bit 2Bit 1Bit 0

Write MCL RACK SIM IFN Reset value: 1111b

Read - - - TACK ACT SRDY Reset value: xxxxb

MCL Multi-Chi p Link activation

MCL = 1,m u lti -ch ip lin k dis abled. This bit has to be set to "0" during

transactions to/ from the internal EEPR OM

MCL = 0, connects SC and SD additionally to the internal multi-chip link pads

RACK Receiv e ACKnowledge status/control bit for MCL mode

RACK = 0, transmit acknowledge in next receive telegram

RACK = 1, transmit no acknowledge in last receive telegram

TACK Transmit ACKnowledge status/control bit for MCL mode

TACK = 0, acknowledge received in last tr ansmit tele gram

TACK = 1, no acknowledge received in last transmit telegram

SIM Serial Interrupt Mask

SIM = 1, disable interrupts

SIM = 0, enable serial interrupt. An interrupt is generated.

IFN Interrupt FuNction

IFN = 1, the serial interrupt is generated at the end of telegram

IFN = 0, the serial interrupt is generated when the S RDY goes low (i.e., buffer

becomes empty/full in transmit/receive mode)

SRDY Serial interface buffer ReaDY status flag

SRDY = 1, in receive mode: receive buffer empty

in transm it mode: tran smit buf fer fu ll

SRDY = 0, in receive mode: receive buffer full

in tran sm it mo de: tr ans mit b uf fer empty

ACT Transmission ACTive status flag

ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditio n s

are currently in prog ress.

ACT = 0, transmis sion is inactive

Fir st write c ycle Bit 3 Bit 2 Bit 1 Bit 0 Res et v alu e: xxxx b

Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb

First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb

Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset valu e: xxxx b

78 T48C862-R3 4554A–4BMCU–02/03

Combination Modes The UTCM co nsis ts of two timer s (Timer 2 and Tim er 3) and a s erial i nterface. There is

a multitude of modes in which the timers and serial interface can work together.

The 8-bit wide serial interface operates as shift register for modulation and demodula-

tion. The modulator and demodulator units work together with the timers and shift the

data bits into or out of the shift register.

Combination Mode

Timer 2 and SSI

Figure 73. Combination Timer 2 and SSI

4-bit counter 2/1

RES OVF1

Compare 2/1

T2CO1

POUT

CL2/2 DCG

T2M1P4CR

8-bit counter 2/2

RES OVF2

Compare 2/2

T2CO2T2CM

Timer 2 - control TOG2

INT4 Biphase-,

Manchester-

modulator

Output

MOUT

T2O

Timer 2

modulator

output-stage

T2M2

SO Control

T2C

CL2/1

T2I

SYSCL

T1OUT

TOG3

SCL

I/O-bus

8-bit shift regist er

MSB LSB

Shift_CL

SIC1 SIC2 SISC

SCLI

Control

STB SRB

Output

INT3

I/O-bus

SSI-control

TOG2

POUT

T1OUT

SYSCL MCL_SC

MCL_SD

Transmit

buffer Receive

buffer

CM1

I/O-bus

POUT

SCL

DCGO

TOG2

T48C862-R3

4554A–4BMCU–02/03

Combination Mode 1:

Burst Modulation SSI mode 1: 8-bit NRZ and internal data SO output to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler

and DCG

Timer 2 output mode 3: Duty cycle burst generator

Figure 74. Carrier Frequency Burst Modulation with the SSI Internal Data Output

Combination Mode 2:

Biphase Modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler

Timer 2 output mode 4: The modulator 2 of Timer 2 modulates the SSI internal

data output to Biphase code

Figure 75. Biphase Modulation 1

1201201201201201201201201201201201201201

DCGO

Counter 2

TOG2

T2O

Counter = compare register (=2)

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13

TOG2

T2O 0000

00110101

1111

8-bit SR-data

Bit 7 Bit 0

Data: 00110101

80 T48C862-R3 4554A–4BMCU–02/03

Combination Mode 3:

Manchester Modulation 1 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler

Timer 2 output mode 5: The modulator 2 of Timer 2 modulates the SSI internal

data output to Manchester code

Figure 76. Manchester Modulation 1

Combination Mode 4:

Manchester Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 5: The modulator 2 of Timer 2 modulates the SSI data output

to Manchester code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for mod-

ulator 2. The SSI has a special mode to supply the prescaler with the shif t clock.

The c ontrol output signal (OMSK) of the SSI is used as st op signal for the modulator.

Figure 72 shows an example for a 12-bit Manchester telegram.

Figure 77. Manchester Modulation 2

TOG2

T2O 000

00110101

11 1 1

8-bit SR-data

Bit 7 Bit 0

Data: 00110101

0000000012340120Counter 2/1 = Compare Register 2/1 (= 4)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCLI

Buffer full

SIR

MSM

Timer 2

Mode 3

SCL

Counter 2/1

OMSK

T2O

T48C862-R3

4554A–4BMCU–02/03

Combination Mode 5:

Biphase Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 4: The modulator 2 of Timer 2 modulates the SSI data output

to Biphase code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for mod-

ulator 2. The SSI has a special mode to supply the prescaler via the shift clock.

The c ontrol output signal (OMSK) of the SSI is used as st op signal for the modulator.

Figure 73 shows an example for a 13-bit Biphase telegram.

Figure 78. Biphase Modulation 2

00000000123450Counter 2/1 = Compare Register 2/1 (= 5)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SCLI

Buffer full

SIR

MSM

Timer 2

Mode 3

SCL

Counter 2/1

OMSK

T2O

012

82 T48C862-R3 4554A–4BMCU–02/03

Combination Mode Timer 3 and SSI

Figure 79. Combination Timer 3 and SSI

Combination Mode 6:

FSK Modulation SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 8: FSK modulation with shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects which compare register is used for the output frequency generation. A "0"

level at the SSI da ta output en ables the compar e register 1 and a "1" le vel enable s the

compare register 2. The compare and compare mode registers must be programmed to

generate the two frequencies via the output toggle flip-lop. The SSI can be supplied with

the togg le signal of Timer 2 or any other clock sour ce. The T imer 3 c ounter is driven by

an internal or external clock source.

8-bit count er 3

RES

Compare 3/1

T3CO1

T3CP

T3CO2

Timer 3 - control

T3O

CL3

T3I

T3EX

SYSCL

T1OUT

POUT

I/O-bus

Compare 3/2

T3CM1 T3CM2

T3C T3ST

Modulator 3

Demodu-

lator 3

Control

TOG3

INT5

RES

CM31

T3I

T3EX

T3MT3CS

CP3

8-bit shift regist er

MSB LSB

Shift_CL

SIC1 SIC2 SISC

SCLI

Control

STB SRB

Output

INT3

I/O-bus

SSI-control

TOG2

POUT

T1OUT

SYSCL

MCL_SC

MCL_SD

Transmit buffer Receive buffer

T48C862-R3

4554A–4BMCU–02/03

Figure 80. FSK Modulation

Combination Mode 7:

Pulse-width Modulation

(PWM)

SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects wh ich c ompare re gister i s used fo r the o utput pul se gen eration. In this

mode, both compare and compare mode registers must be programmed to generate the

two pul se width. It is als o useful t o enable the sing le-action mode for extreme d uty

cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.

The SSI must be suppl ied with the toggle signa l of Tim er 2. The counte r is driv en by an

internal or external clock source.

Figure 81. Pulse-width Modulation

Combination Mode 8:

Manchester

Demodulation/Pulse-width

Demodulation

SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3

For Manche ste r dem odu la tion , the edge detec ti on sta ge must be pr ogr am me d to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage i s used to gene rate the shift cloc k for the SS I. A compar e regist er 1 match ev ent

defines the correct moment for shifting the state from the input T3I as the decoded bit

into shift regis ter. After that, the dem odulat or waits for the next ed ge to synch ronize the

timer by a reset for the ne xt bit. The compare r egister 2 can be u sed to de tect a tim e

error and handle it with an interrupt routine.

01234012340120

Counter 3

CM31

CM32

12012012012012012012012340

T3R

T3O

01 0

000000000 0000

Counter 3

CM31

CM32

T3O

00000123456789101112131415012345

TOG2

678

9111210 1413 0 2 314150

00 1

SIR

SCO

T3R

84 T48C862-R3 4554A–4BMCU–02/03

Before activating the demodulator mode the timer and the demodulator stage must be

synchron ized with t he bitstr eam. Th e Manc heste r co de tim ing con sists o f par ts wit h the

half bitlength and the complete bitlength. A synchronization routine must start the

demodulator after an interval with the complete bitlength.

The counter can be driven by any internal clock source. The output T3O can be used by

Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demod-

ulation. The input must programmed to detect the positive edge. The demodulator and

timer mus t be synchronized with the leading edge of the puls e. After that a counter

match with the co mpare regis ter 1 shifts the state at t he input T3I into the shif t register.

The next positive edge at the input restarts the timer.

Figure 82. Manchester Demodulation

Combination Mode 9:

Biphase Demodulation SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 11: Biphase demodulation with Timer 3

In the Biphase demodulation mode the timer works like in the Manchester demodulation

mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop

samples the edge in the middle of the bitfr ame and the compare re gister 1 ma tch eve nt

shifts the toggle flip-flop output into shift register. Before activating the demodulation the

timer and the demodulation stage must be synchronized with the bitstream. The

Biphas e code ti ming cons ists of par ts wit h the half bitlength an d the com plete bi tlengt h.

The synchronization routine must start the demodulator after an interval with the com-

plete bitlen gth.

The counter can be driven by any internal clock source and the output T3O can be used

by Timer 2 in this mode.

1011100 110

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Synchronize Manchester demodulation mode

Timer 3

mode

T3EX

SR-DATA

T3I

CM31=SCI

100110

Bit 0

T48C862-R3

4554A–4BMCU–02/03

Figure 83. Biphase Demodulation

Combination Mode Timer 2 and Timer 3

Figure 84. Combination Timer 3 and Timer 2

011 1 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Synchronize Biphase demodulation mode

Timer 3

mode

T3EX

Q1=SI

CM31=SCI

SR-DATA

0000

T3I

Reset

Counter 3

101010

Bit 0

8-bit counter 3

RES

Compare 3/1

T3CO1

T3CP

T3CO2

Timer 3 - control

T3O

CL3

T3I

T3EX

SYSCL

T1OUT

POUT

I/O-bus

Compare 3/2

T3CM1 T3CM2

T3C T3ST

Modulator 3

Demodu-

lator 3

Control SO

TOG3

INT5

RES

CM31

T3I

T3EX

TOG2

SCI

SSI

CP3

4-bit counter 2/1

RES OVF1

Compare 2/1

T2CO1

CM1

POUT

SSI

CL2/2 DCG

T2M1P4CR

8-bit counter 2/2

RES OVF2

Compare 2/2

T2CO2T2CM

TOG2

INT4 Biphase-,

Manchester-

modulator

OUTPUT

MOUT

T2O

Timer 2

modulator 2

output-stage

T2M2

Control

(RE, FE, SCO, OMSK)

SSI

T2C

CL2/1

TOG3

SYSCL

T1OUT

SCL

Timer 2 - control

T3CS T3M

POUT

DCGO

T2I

I/O-bus

86 T48C862-R3 4554A–4BMCU–02/03

Combination Mode 10:

Frequency Measurement or

Event Counter with Time Gate

Timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and

4-bit prescaler

Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the Timer 3

Timer 3 mode 3: Timer/Counter; internal trigger restart and internal capture

(with Timer 2 TOG2-signal)

The counter is driven by an external (T3I) clock source. The output signal (TOG2) of

Timer 2 resets the counter. The counter value before reset is saved in the capture regis-

ter. If s ingle-action mode is activ ated for on e or both comp are registers, the trigger

signal restarts also the single actions. This mode can be used for fr equency measure-

ments or as event counter with time gate.

Figure 85. Frequency Measurement

Figure 86. Event Counter with Time Gate

Combination Mode 11:

Burst Modulation 1 Timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and

4-bit prescaler

Timer 2 output mode 1/6: Timer 2 compare match toggles the output flip-flop (M2)

to the Timer 3

Timer 3 mode 6: Carrier frequency burst modulation controlled by Timer 2

output (M2)

The Timer 3 counter is driven by an internal or external clock source. Its compare and

compar e mode registers m ust be program med to generate t he carrier frequen cy with

the output toggle flip-flop. The output toggle flip-flop (M2) of Timer 2 is used to enable

and disable the Timer 3 output. The Timer 2 can be driven by the toggle output signal of

Timer 3 (TOG3) or any other clock source.

0012345678910

ounter 3

TOG2

T3CP-

T3I

T3R

Capture val ue = 0 Capt ure value = 17 Capt. value = 18

11121314151617 1234567891011121314151617180 012345

0012345678910

Counter 3

TOG2

T3CP-

11 0 1 2 401

T3I

T3R

Capture val ue = 0 Capture value = 11 Cap. val. = 4

T48C862-R3

4554A–4BMCU–02/03

Figure 87. Burst Modulation 1

0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101

30 1 2 3 3 0 1 32

CL3

Counter 3

CM1

CM2

TOG3

Counter 2/ 2

TOG2

T3O

88 T48C862-R3 4554A–4BMCU–02/03

Combination Mode Timer 2, Timer 3 and SSI

Figure 88. Combination Timer 2, Timer 3 and SSI

8-bit Counter 3

RES

Compare 3/1

T3CO1

T3CP

T3CO2

Timer 3 - control

T3O

CL3

T3I

T3EX

SYSCL

T1OUT

POUT

I/O-bus

Compare 3/2

T3CM1 T3CM2

T3C T3ST

Modulator 3

Demodu-

lator 3

Control SO

TOG3

INT5

RES

CM31

T3I

T3EX

TOG2

SCI

SSI

CP3

4-bit Counter 2/1

RES OVF1

Compare 2/1

T2CO1

CM1

POUT

CL2/2 DCG

T2M1P4CR

8-bit Counter 2/2

RES OVF2

Compare 2/2

T2CO2

T2CM

TOG2

INT4 Biphase-,

Manchester-

modulator

OUTPUT

MOUT

T2O

Timer 2

modulator 2

output-stage

T2M2

Control

(RE, FE,

SCO, OMSK)

T2C

CL2/1

TOG3

SYSCL

T1OUT

SCL

Timer 2 - control

T3CS T3M

POUT

DCGO

T2I

I/O-bus

8-bit shift register

MSB LSB

Shift_CL

SIC1 SIC2 SISC

SCLI

Control

STB SRB

Output

INT3

I/O-bus

SSI-control

TOG2

POUT

T1OUT

SYSCL MCL_SC

MCL_SD

Transmit buffer Recei ve buffer

SCL

T48C862-R3

4554A–4BMCU–02/03

Combination Mode 12:

Burst Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3

Timer 2 output mode 2: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the SSI

Timer 3 mode 7: Carrier frequency burst modulation controlled by the internal

output (SO) of SSI

The Time r 3 count er is driv en by an in ternal or external clock sou rce. Its co mpare- an d

compar e mode registers m ust be program med to generate t he carrier frequen cy with

the output toggle flip-flop (M3). The internal data output (SO) of the SSI is used to

enable and disable the Timer 3 output. The SSI can be supplied with the toggle signal of

Timer 2.

Figure 89. Burst Modulation 2

Combination Mode 13:

FSK Modulation SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3

Timer 2 output mode 3: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6: Timer 2 4-bit compare match signal (POUT) to the SSI

Timer 3 mode 8: FSK modulation with shift register data output (SO)

The two compare re gisters are used to generat e two di fferent time intervals. The SSI

data ou tpu t se le cts wh ic h com par e r e gist er i s used for the outp ut f re que ncy genera tio n.

A "0" level at the SSI data output enables the compare register 1 and a "1" level enables

the compare register 2. The compare- and compare mode registers must be pro-

grammed to generate the two frequencies via the output toggle flip-flop. The SSI can be

supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter

is driven by an internal or external clock source.

0101234501012345010123450101 50101 50101 50101 50101 50101 50101 50101 50101 50101

30 1 2 3 3 0 1 32

CL3

Counter 3

CM31

CM32

TOG3

Counter 2/ 2

TOG2

T3O

90 T48C862-R3 4554A–4BMCU–02/03

Figure 90. FSK Modulation

Data EEPROM The int ernal da ta EEPR OM offe rs 2 pag es of 51 2 bits ea ch. Bo th pages are orga nized

as 32 ´ 16-b it words. The pr ogram ming volta ge as well as the write cy cle timin g is gen-

erated on ch ip. To be compati ble with the ROM pa rts, two restric tions have to be taken

into account:

• To use the same EEPROM page as with the ROM parts the application software has

to write the MCL-command “09h” to the EEPROM. This command has no effect for

the microcontroller if it is left inside the HEX-file for the ROM version.

• Data handling for read and write is performed using the serial interface MCL.

The page s elect is performe d by either writing “01h” (page 1) or “09h” (page 0) to the

EEPROM.

Figure 91. Data EEPROM

01234012340123

Counter 3

CM31

CM32

40120120120120120120120123

T3R

T3O

01 0

16-bit read/write buffer

Address

control

8-bit data register

EEPROM

2 x 32 x 16

HV-generatorTiming control

Mode

control

I/O

control

SCL

VDD

VSS

SDA

Page 1

Page 0

--> Write "01h"

--> Write "09h"

T48C862-R3

4554A–4BMCU–02/03

Serial In terface The EEPROM us es a t wo- wire seri al in terf ace (T WI) to the micr ocont roll er for rea d and

write accesses to the data. It is considered to be a slave in all these applications. That

means, the controller has to be the master that initiates the data tr ansfer and provides

the clock for transmit and receive operations.

The seri al inter face is con tr olled by th e mic rocontr olle r whi ch ge nerate s the ser ial c lock

and controls the access via the SCL-line and S DA-line. SCL is use d to clock the data

into and out of the device. SDA is a bi-directional line that is used to transfer data into

and out of the device. The following protocol is used for the data transfers.

Serial Protocol • Data states on the SDA-line changing only while SCL is low.

• Changes on the SD A-line while SCL is high are interpreted as START or STOP

condition.

• A START condition is defined as high to low transition on the SDA-line while the

SCL-line is high.

• A ST OP condition is defined as low to high transition on the SDA-line while the SCL-

line is high.

• Each data transfer must be initialized with a STAR T condition and terminated with a

STO P condition. The STAR T condition wakes the device from standby mode and the

STOP condition returns the device to standby mode.

• A receiving device generates an acknowledge (A) after the reception of each byte.

This requires an additional clock pulse, generated by the master. If the reception

was successful the receiving master or slave device pulls down the SD A-line during

that clock cycle. If an acknowledge is not detected (N) by the interface in transmit

mode, it will terminate further data transmissions and go into receive mode. A

master device must finish its read operation by a non-acknowledge and then send a

stop condition to bring the device into a known state.

Figure 92. MCL Protocol

• Before the START condition and after the STOP condition the device is in standb y

mode and the SDA line is switched as input with pull-up resistor.

• The control byte that follows the START condition determines the following

operation. It consists of the 5-bit row address, 2 mode control bits and the

READ/NWRITE bit that is used to control the direction of the following transfer . A "0"

defines a write access and a "1" a read access.

Start

condition Data

valid Data

change Data/

acknowledge

valid

Stop

condition

SCL

SDA

Stand

by Stand-

92 T48C862-R3 4554A–4BMCU–02/03

Control Byte Format

EEPROM The EEPROM has a size of 2 ´ 512 bits and is organized as 32 x 16-bit matrix each. To

read and write data to and from the EEPROM the serial interface must be used. The

interfac e s up por ts one and two b yte wr ite ac ce ss es and one to n-byte read accesses to

the EEPROM.

EEPROM – Operating Modes The operating mode s of the EE PROM ar e defined via the control b yte. The control by te

contains the row address, the mode control bits and the read/not-write bit that is used to

control the direction o f the followi ng transfer. A "0" defi nes a write access and a "1" a

read access. The five address bits select one of the 32 rows of the EEPROM memory to

be accessed. For all accesses the c omplete 16-bi t word of the selected row is loaded

into a buffer. The buffer must be read or overwritten via the serial interface. The two

mode control bits C1 and C2 define in which order the ac cesses to the buffer are per-

formed: High byte – low byte or low byte – high byte. The EEPROM also supports

autoincrement and autodecrement read operations. After sending the start address with

the corresponding mode, consecutive memory cells can be read row by row without

transmission of the row addresses.

Two spec ial contro l bytes e nable the complete i nitializat ion of E EPROM with " 0" or

with "1".

Write Operations The EEPROM permits 8-bi t and 16-bit write operati ons. A write acces s starts with the

START cond ition follo wed by a write co ntrol byte and on e or two data bytes from the

master. It is completed via the STOP condition from the master after the acknowledge

cycle.

The programming cycle consists of an erase cycle (write "zeros") and the write cycle

(write "ones"). Both cycles together take about 10 ms.

Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the

EEPROM will not acknowledge until the writ e cycle is fini shed. This can be us ed to

detect the end of the write cycle. The master must perform acknowledge poll ing by

sending a start condition followed by the control byte. If the device is still busy with the

write cycle, it will not return an acknowledge and the master has to generate a stop con-

dition or per form further ackno wledge polling sequenc es. If the cycle is complete, it

returns an acknowledge and the master can proceed with the next read or write cycle.

Write One Data Byte

Write Two Data Bytes

Write Contro l Byte Only

EEPROM Address Mode

Control Bits Read/

NWrite

StartA4A3A2A1A0C1C0R/NWAckn

Start Control b yt e Ackn Data byte Ackn Data b y te Ackn Stop

Start Control byte A Data byte 1 A Stop

Start Control byte A Data byte 1 A Data byte 2 A Stop

Start Control byte A Stop

T48C862-R3

4554A–4BMCU–02/03

Write Contro l Bytes

A -> acknowledge; HB: high byte; LB: low byte; R: row address

Read Operations The EEPROM all ows byt e-, w ord- and cu rren t addre ss rea d opera tio ns. The rea d oper-

ations are initiated in the same way as write operations. Every read access is initiated by

sending the START condition followed by the control byte which contai ns the address

and the read mode. When the device has received a read command, it returns an

acknowledge, loads the addressed word into the read/write buffer and sends the

selecte d data by te to the m aster. The m aster has to a cknowled ge the r eceived byt e if it

wants to proceed the read operation. If two bytes are read out from the buffer the device

increments respectively decrements the word address automatically and loads the

buffer wi th t he nex t word . The re ad mode b its de termines if th e l ow or hig h byte is r ead

first fr om the bu ffer an d if the wo rd address is incr emente d or dec remente d for the next

read access. If the memory address limit is reached, the data word address will roll over

and the sequential read will continue. The master can terminate the read operation after

every byte by not responding with an acknowledge (N) and by issuing a stop condition.

Read One Da ta Byte

Read Two Data Bytes

Read n Data Bytes

Read Control Bytes

MSB LSB

Write low byte firs t A4 A3 A2 A1 A0 C1 C0 R/NW

Row address 0 1 0

Byte order LB(R) HB(R)

MSB LSB

Write high byte first A4 A3 A2 A1 A0 C1 C0 R/NW

Row address 1 0 0

Byte order HB(R) LB(R)

Start Control byte A Data byte 1 N Stop

Start Control byte A Data byte 1 A Data byte 2 N Stop

Start Control byte A Data byte 1 A Data byte 2 A - - - Data byte n N Stop

MSB LSB

Read low byte first,

address increment A4 A3 A2 A1 A0 C1 C0 R/NW

Row address 0 1 1

Byte order LB(R) HB(R) LB(R+1) HB(R+1) - - - LB(R+ n) HB(R+n)

MSB LSB

94 T48C862-R3 4554A–4BMCU–02/03

A -> acknowledge, N -> no acknowledge; HB: high byte; LB: low byte, R: row address

Initialization the Serial

Inte rface to the EEPROM To prevent unexpect ed behavior of he EEPROM and its interface it is good pr actice to

use an initialization sequence after any reset of the circuit. This is performed by writing:

to the serial interface. If the EEPROM acknowledges this sequence it is in a defined

state. Maybe it is necessary to perform this sequence twice.

Read high byte first,

address decrement A4 A3 A2 A1 A0 C1 C0 R/NW

Row address 1 0 1

Byte order HB(R) LB(R) HB(R-1) LB(R-1) - - - H B(R-n) LB(R-n)

Start "FFh" A Stop

T48C862-R3

4554A–4BMCU–02/03

Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at any condition above those indicated in the operational section of this

specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability.

All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the

build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are

connected to an appropriate logic voltage level (e.g., VDD).

Absolute Maxim u m Ratings

Voltages are given relative to VSS

Parameters Symbol Value Unit

Supply voltage VDD -0.3 to + 6.5 V

Input voltage (on any pin) VIN VSS -0.3 £ VIN £ VDD +0.3 V

Output short circuit duration tshort Indefinite s

Oper ating temperature range Tamb -40 to +125 °C

Storage temperature range Tstg -40 to +150 °C

Soldering temperature (t £ 10 s) Tsld 260 °C

Thermal Resistance

Parameter Symbol Value Unit

Thermal resistance (SSO20) RthJA 140 K/W

DC Operating Characteristics

VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified.

P a rameters Test Conditions Sym bol Min. Typ. Max. Unit

Power Supply 2.0 4.0 V

Operating voltage at VDD VDD VPOR V

Active current

CPU active fSYSCL = 1 MHz

VDD = 1.8 V

VDD = 3.0 V IDD 0.3

0.4 0.4 mA

Power down current

(CPU sleep,

RC oscillator active,

4-MHz quartz oscillator active)

fSYSCL = 1 MHz

VDD = 1.8 V

VDD = 3.0 V IPD 40

70 150 µA

µA

Sleep current

(CPU sleep,

32-kHz quartz oscillator active

4-MHz quartz osci llator inactive)

VDD = 1.8 V

VDD = 3.0 V

VDD = 3.0 V at 85°C

ISleep 0.4

0.6 4.3

1.5

µA

Sleep current

(CPU sleep,

32-kHz quartz oscillator inactive

4-MHz quartz osci llator inactive)

VDD = 3.0 V

VDD = 3.0 V at 85°CISleep 0.3 3.5

1.0 µA

µA

Pin capacitance Any pin to VSS CL710pF

96 T48C862-R3 4554A–4BMCU–02/03

Note: The Pin BP 20/NTE has a static pull-up resistor during the reset-phase of the microcontroller

Power-on Reset Threshold Voltage

POR threshold voltage BOT = 1 VPOR 1.54 1.7 1.88 V

POR threshold voltage BOT = 0 VPOR 1.83 2.0 2.20 V

POR hysteresis VPOR 50 mV

Voltage Monitor Threshold Voltage

VM high threshold voltage VDD > VM, VMS = 1 VMThh 3.0 3.35 V

VM high threshold voltage VDD < VM, VMS = 0 VMThh 2.77 3.0 V

VM middle threshold voltage VDD > VM, VMS = 1 VMThm 2.6 2.9 V

VM middle threshold voltage VDD < VM, VMS = 0 VMThm 2.4 2.6 V

VM low threshold voltage VDD > VM, VMS = 1 VMThl 2.2 2.44 V

VM low threshold voltage VDD < VM, VMS = 0 VMThl 2.0 2.2 V

External Input Voltage

VMI VDD = 3 V, VMS = 1 VVMI 1.3 1.44 V

VMI VDD = 3 V, VMS = 0 VVMI 1.18 1.3 V

All Bi-direc tiona l Ports

Input voltage LOW VDD = 2.0 to 4.0 V VIL VSS 0.2 ´

VDD

Input voltage HIGH VDD = 2.0 to 4.0 V VIH 0.8 ´

VDD

VDD V

Input LOW current

(switched pull-up) VDD = 2.0 V,

VDD = 3.0 V, VIL= VSS

IIL -3

-10 -8

-20 -14

-40 µA

µA

Input HIGH current

(switched pull-down) VDD = 2.0 V,

VDD = 3.0 V, VIH = VDD

IIH 3

10 6

20 14

40 µA

µA

Input LOW current

(static pul l-up ) VDD = 2.0 V

VDD = 3.0 V, VIL= VSS

IIL -30

-80 -50

-160 -98

-320 µA

µA

Input LOW current

(static pul l-down) VDD = 2.0 V

VDD = 3.0 V, VIH= VDD

IIH 20

80 50

160 100

320 µA

µA

Input leakage current VIL = VSS IIL 100 nA

Input leakage current VIH = VDD IIH 100 nA

Output LOW current VOL = 0.2 ´VDD

VDD = 2.0 V

VDD = 3.0 V IOL 0.9

31.8

53.6

8mA

Output HI GH current VOH = 0.8 ´VDD

VDD = 2.0 V

VDD = 3.0 V IOH -0.8

-3 -1.7

-5 -3.4

-8 mA

DC Operating Characteristics (Continued)

VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified.

P a rameters Test Conditions Sym bol Min. Typ. Max. Unit

T48C862-R3

4554A–4BMCU–02/03

AC Characteristics

Suppl y vo ltage VDD = 2.0 to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Operation Cycle Time

System clock cycle VDD = 2.0 to 4.0 V

Tamb = -40 to 85°CtSYSCL 500 2000 ns

VDD = 2.4 to 4.0 V

Tamb = -40 to 85°CtSYSCL 250 2000 ns

Timer 2 input Timing Pin T2I

Timer 2 input clock fT2I 5MHz

Timer 2 input LOW time Rise/fall tim e < 10 ns tT2IL 100 ns

Timer 2 input HIGH time Rise/fall time < 10 ns tT2IH 100 ns

Timer 3 Input Timing Pin T3I

Timer 3 input clock fT3I SYSCL/2 MHz

Timer 3 input LOW time Rise/fall tim e < 10 ns tT3IL 2t

SYSCL ns

Timer 3 input HIGH time Rise/fall time < 10 ns tT3IH 2t

SYSCL ns

Interrupt Request Input Timing

Interrupt request LOW time Rise/fall time < 10 ns tIRL 100 ns

Interrupt request HIGH time Rise/fall time < 10 ns tIRH 100 ns

External System Clock

EXSCL at OSC1, ECM = EN Rise/fall time < 10 ns fEXSCL 0.5 4 MHz

EXSCL at OSC1, ECM = DI Rise/fall time < 10 ns fEXSCL 0.02 4 MHz

Input HIGH time Rise/fall time < 10 ns tIH 0.1 ms

Reset Timing

Pow er-on reset time VDD > VPOR tPOR 1.5 5 ms

RC Oscill ator 1

Frequency fRcOut1 3.8 MHz

Stability VDD = 2.0 to 4.0 V

Tamb = -40 to +125°CDf/f ±50 %

RC Oscill ator 2 – External Resistor

Frequency Rext = 180 kWfRcOut2 4MHz

Stability VDD = 2.0 to 4.0 V

Tamb = -40 to +125°CDf/f ±15 %

Stabili zation time tS10 ms

4-MHz Crystal Oscillator (Operating Range VDD = 2.2 V to 4.0 V)

Frequency fX4MHz

Start-up time tSQ 5ms

Stability Df/f -10 10 ppm

Integrated input/output capacitances

(configurable) CIN/COUT progr a mm able CIN

COUT

0, 2, 5, 7, 10 or 12

0, 2, 5, 7, 10 or 12 pF

98 T48C862-R3 4554A–4BMCU–02/03

Crystal

Characteristics Figure 93. Crystal Equivalent Circuit

32-kHz C rystal Oscillator (Operating Range VDD = 2.0 V to 4.0 V)

Frequency fX32.768 kHz

Start-up time tSQ 0.5 s

Stability Df/f -10 10 ppm

Integrated input/output capacitances

(configurable) CIN/COUT progr a mm able CIN

COUT

0, 2, 5, 7, 10 or 12

0, 2, 5, 7, 10 or 12 pF

External 32-kHz Crystal Parameters

Crystal frequency fX32.768 kHz

Serial resistance RS 30 50 kW

Static capacitance C01.5 pF

Dynamic capacitance C1 3 fF

External 4-MHz Crystal Parameters

Crystal frequency fX4.0 MHz

Serial resistance RS 40 150 W

Static capacitance C01.4 3 pF

Dynamic capacitance C1 3 fF

EEPROM

Oper ating cur rent during er as e/w rite

cycle IWR 600 1300 mA

Endura nc e Era se-/ w rite cycles

Tamb = 125°CED

500,000

10,000 1,000,000

20,000 Cycles

Cycles

Data erase/write cycle time For 16-bit access tDEW 913ms

Data retention time Tamb = 125°CtDR

tDR

100

1years

years

Pow er-up to read operation tPUR 0.2 ms

Power-up to write operation tPUW 0.2 ms

Program EEPROM Erase-/write cycles, Tamb = 0 to 40°Cn

EW 100 1,000 Cycles

Serial Interface

SCL clock frequency fSC_MCL 100 500 kHz

AC Characteristics (Continued)

Suppl y vo ltage VDD = 2.0 to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.

Parameters Test Conditions Symbol Min. Typ. Max. Unit

LC1 RS

OSCIN OSCOUT

Equivalent

circuit

SCLIN SCLOUT

T48C862-R3

4554A–4BMCU–02/03

File: _____________________ . HEX CRC: ____________________ . HEX

Approval Date: _________________ Signature: _________________________

Ordering Information

Please select the option settings from the list below and insert ROM CRC.

Output Input Output Input

Port 1 Port 5

BP10 [ ] CMOS [ ] Switched pull-up BP50 [ ] CMOS [ ] Switched pull-up

[ ] Open drain [N] [ ] Switched pull-down [ ] O pen drain [N] [ ] Switched pull-down

[ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up

[]Static pull-down []Static pull-down

BP13 [ ] CMOS [ ] Switched pull-up BP51 [ ] CMOS [ ] Switched pull-up

[ ] Open drain [N] [ ] Switched pull-down [ ] O pen drain [N] [ ] Switched pull-down

[ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up

[]Static pull-down []Static pull-down

Port 2 BP52 [ ] CMOS [ ] Switched pull-up

BP20 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down

[ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up

[ ] O pen drain [P] [ ] Static pull-up [ ] Static pull-down

BP53 [ ] CMOS [ ] Switched pull-up

BP21 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down

[ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up

[ ] O pen drain [P] [ ] Static pull-up [ ] Static pull-down

[ ] Static pull-down Port 6

BP22 [ ] CMOS [ ] Switched pull-up BP60 [ ] CMOS [ ] Switched pull-up

[ ] Open drain [N] [ ] Switched pull-down [ ] O pen drain [N] [ ] Switched pull-down

[ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up

[]Static pull-down []Static pull-down

BP23 [ ] CMOS [ ] Switched pull-up BP63 [ ] CMOS [ ] Switched pull-up

[ ] Open drain [N] [ ] Switched pull-down [ ] O pen drain [N] [ ] Switched pull-down

[ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up

[]Static pull-down []Static pull-down

Port 4 BP40 [ ] CMOS [ ] Switched pull-up OSC1

[ ] Open drain [N] [ ] Switched pull-down [ ] No integrated capacitance

[ ] Open drain [P] [ ] Static pull-up [ ] I nternal capacitance (0 to 20 pF) [ _____pF]

[ ] Static pull-down OSC2

BP41 [ ] CMOS [ ] Switched pull-up [ ] No integrated capacitance

[ ] Open drain [N] [ ] Switched pull-down [ ] Internal capacit ance (0 to 20 pF) [ _____pF]

[ ] Open drain [P] [ ] Static pull-up

[ ] Static pull-down Clock Used

BP42 [ ] CMOS [ ] Switched pull-up [ ] External resistor

[ ] Open drain [N] [ ] Switched pull-down [ ] External clock

[ ] O pen drain [P] [ ] Static pull-up [ ] 32-kHz cr ystal

[]Static pull-down []4-MHz crystal

BP43 [ ] CMOS [ ] Switched pull-up

[ ] Open drain [N] [ ] Switched pull-down ECM (External Clock Monitor)

[ ] Open drain [P] [ ] Static pull-up [ ] E nable

[ ] Static pull-down [ ] Disable

100 T48C862-R3 4554A–4BMCU–02/03

Package Information

Extended Type Number Package Remarks

T48C862M-R3-TNQ SSO24 429 MHz to 439 MHz

technical drawings

according to DIN

specifications

Packag e SS O24

Dimensions in mm 8.05

7.80

0.15

0.05

0.25

0.65 7.15

1.30

5.7

5.3

4.5

4.3

6.6

6.3

0.15

24 13

112

101

T48C862-R3

4554A–4BMCU–02/03

Table of Contents Features ................................................................................................. 1

Description ............................................................................................ 1

Pin Configuration .................................................................................. 2

Pin Description: RF Part ......................................................................2

Pin Description: Microcontroller Part ................................................. 3

UHF ASK/FSK Transmitter Block ........................................................ 4

Features ................................................................................................. 4

Description ............................................................................................ 4

General Description .............................................................................. 6

Functional Description ......................................................................... 6

ASK Transmission ................................................................................................6

FSK Transmission ................................................................................................6

CLK Output ...........................................................................................................7

Clock Pulse Take Over ...................................................................................7

Output Matching and Power Setting ...............................................................7

Application Circuit .................................................................................................8

Absolute Maximum Ratings ............................................................... 11

Thermal Resis tance ........ .... ..... ................... .... ..... ..... .......................... 11

Electrical Characteristics ...................................................................11

Microcontroller Block ......................................................................... 13

Features ............................................................................................... 13

Description .......................................................................................... 13

Introduction ......................................................................................... 13

Differences between T48C862-R3 and ATAR862 Microcontrollers ...................13

Program Memory ..........................................................................................13

Configuration Memory ...................................................................................13

Data Memory ................................................................................................13

Reset Function ......................... ....... ...... .................... ...... .................... ...... ....1 4

Microcontroller Architecture General Description .......................... 14

102 T48C862-R3 4554A–4BMCU–02/03

Components of Microcontroller Core ...............................................14

Program Memory ................................................................................................14

RAM ....................................................................................................................15

Expression Stack ..........................................................................................15

Return Stack .................................................................................................15

Registers .. ...... ....... ...... ................... ....... ...... .................... ...... ....... ................... ....16

Program Counter (PC) ..................................................................................16

RAM Address Registers ................................................................................17

Expression Stack Pointer (SP) ......................................................................17

Return Stack Pointer (RP) ............................................................................17

RAM Address Registers (X and Y) ...............................................................17

Top of Stack (TOS) ............ ...... .................... ...... ....... ................... ....... ..........17

Condition Code Register (CCR) ....................................................................17

Carry/Borrow (C) ... ....... ................... ...... ....... ................... ....... ...... ....... ..........17

Branch (B) .....................................................................................................17

Interrupt Enable (I) ........................................................................................17

ALU .....................................................................................................................18

I/O Bus ................................................................................................................18

Instruction Set .....................................................................................................18

Interrupt Structure ...............................................................................................18

Interrupt Processing ......................................................................................19

Interrupt Latency ...........................................................................................19

Software Interrupts .............................................................................................20

Hardware Interrupts ............................................................................................20

Master Reset .......................................................................................21

Power-on Reset and Brown-out Detection .........................................................21

Watchdog Reset ...........................................................................................22

External Clock Supervisor .. ...... .................... ...... .................... ...... ....... ..........22

Voltage Monitor ...................................................................................22

Voltage Monitor Control/Status Register .......................................................23

Clock Generation ................................................................................ 24

Clock Module ......................................................................................................24

Oscillator Circuits and External Clock Input Stage .............................................25

RC-oscillator 1 Fully Integrated .....................................................................25

External Input Clock ..... ...... ...... ....... ................... ....... ...... .................... ...... ....2 6

RC-oscillator 2 with External Trimming Resistor ...........................................26

4-MHz Oscillator ...........................................................................................27

32-kHz Oscillator ...........................................................................................27

Clock Management .............................................................................................28

Clock Management Register (CM) ................................................................28

System Configuration Register (SC) .............................................................29

Power-down Modes ............................................................................ 29

103

T48C862-R3

4554A–4BMCU–02/03

Peripheral Modules ............................................................................. 30

Addressing Peripherals .......................................................................................30

Bi-directional Port s ......... .... ..... ..... ...................................................... 33

Bi-directional Port 1 ............................................................................................33

Bi-directional Port 2 ............................................................................................34

Port 2 Data Register (P2DAT) ......................................................................35

Port 2 Control Register (P2CR) ....................................................................35

Bi-directional Port 5 ............................................................................................35

Port 5 Data Register (P5DAT) ......................................................................36

Port 5 Control Register (P5CR) Byte Write ...................................................36

Bi-directional Port 4 ............................................................................................37

Port 4 Data Register (P4DAT) ......................................................................38

Port 4 Control Register (P4CR) Byte Write ...................................................38

Bi-directional Port 6 ............................................................................................38

Port 6 Data Register (P6DAT) ......................................................................39

Port 6 Control Register (P6CR) ....................................................................39

Universal Timer/Counter/ Communication Module (UTCM) ...............................39

Timer 1 ................................................................................................................40

Timer 1 Control Register 1 (T1C1) ................................................................42

Timer 1 Control Register 2 (T1C2) ................................................................43

Watchdog Control Register (WDC) ...............................................................43

Timer 2 ................................................................................................................44

Timer 2 Modes ....................................................................................................45

Mode 1: 12-bit Compare Counter .................................................................45

Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler ...........45

Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler .........46

Timer 2 Output Modes ........................................................................................46

Timer 2 Output Signals .......................................................................................47

Timer 2 Output Mode 1 .................................................................................47

Timer 2 Output Mode 2 .................................................................................48

Timer 2 Output Mode 3 .................................................................................48

Timer 2 Output Mode 4 .................................................................................49

Timer 2 Output Mode 5 .................................................................................49

Timer 2 Output Mode 7 .................................................................................49

Timer 2 Registers ...............................................................................................50

Timer 2 Control Register (T2C) .....................................................................50

Timer 2 Mode Register 1 (T2M1) ..................................................................51

Duty Cycle Generator ...................................................................................51

Timer 2 Mode Register 2 (T2M2) ..................................................................52

Timer 2 Compare and Compare Mode Registers .........................................53

Timer 2 Compare Mode Register (T2CM) ....................................................53

Timer 2 COmpare Register 1 (T2CO1) .........................................................53

Timer 2 COmpare Register 2 (T2CO2) Byte Write .......................................54

Timer 3 .................................................................................................54

104 T48C862-R3 4554A–4BMCU–02/03

Features ....................... .................................................................................54

Timer/Counter Modes .........................................................................................55

Timer 3 – Mode 1: Timer/Counter .................................................................56

Time r 3 – Mode 2: Timer/Counter, External Trigger Restart and External

Capture (with T3I Input) .....................................................57

Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal

Capture (with TOG2) .........................................................58

Timer 3 – Mode 4: Timer/Counter .................................................................58

Time r 3 – Mode 5: Timer/Counter, External Trigger Restart and External

Capture (with T3I Input) .....................................................58

Timer 3 Modulator/Demodulator Modes .............................................................58

Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by

Timer 2 Output Toggle Flip-Flop (M2) ...............................58

Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by

SSI Internal Output (SO) ...................................................58

Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO) ...............59

Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register ...............59

Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation .59

Timer 3 – Mode 11: Biphase Demodulation ..................................................60

Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I) .........61

Timer 3 Modulator for Carrier Frequency Burst Modulation ...............................61

Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated

Signals .....................................................................................................61

Timer 3 Registers ...............................................................................................62

Timer 3 Mode Register (T3M) .......................................................................62

Timer 3 Control Register 1 (T3C) Write ........................................................63

Timer 3 Status Register 1 (T3ST) Read .......................................................63

Timer 3 Clock Select Register (T3CS) ..........................................................63

Timer 3 Compare- and Compare-mode Register .........................................64

Timer 3 Compare-Mode Register 1 (T3CM1) ...............................................64

Timer 3 Compare Mode Register 2 (T3CM2) ...............................................65

Timer 3 COmpare Register 1 (T3CO1) Byte Write .......................................65

Timer 3 COmpare Register 2 (T3CO2) Byte Write .......................................65

Timer 3 Capture Register ...................................................................................66

Timer 3 CaPture Register (T3CP) Byte Read ...............................................66

Synchronous Serial Interface (SSI) ....................................................................66

SSI Features: ................................................................................................66

SSI Peripheral Configuration ........................................................................66

General SSI Operation ..................................................................................67

8-bit Synchronous Mode ...............................................................................68

9-bit Shift Mode (MCL) ..................................................................................70

8-bit Pseudo MCL Mode .... ...... .................... ...... .................... ...... .................71

MCL Bus Protocol .........................................................................................72

SSI Interrupt ..................................................................................................73

Modulation and Demodulation ......................................................................73

Serial Interface Registers ...................................................................................74

Serial Interface Control Register 1 (SIC1) ....................................................74

105

T48C862-R3

4554A–4BMCU–02/03

Serial Interface Control Register 2 (SIC2) ....................................................75

Serial Interface Status and Control Register (SISC) .....................................76

Serial Transmit Buffer (STB) – Byte Write ....................................................76

Serial Receive Buffer (SRB) – Byte Read .....................................................76

Combination Modes ........... ........................ ........................................77

Combination Mode Timer 2 and SSI ...................................................................77

Combination Mod e 1: Burst Modulati on ....... ...... ....... ................... ....... ..........78

Combination Mode 2: Biphase Modulation 1 ................................................78

Combination Mode 3: Manchester Modulation 1 ..........................................79

Combination Mode 4: Manchester Modulation 2 ..........................................79

Combination Mode 5: Biphase Modulation 2 ................................................80

Combination Mode Timer 3 and SSI ...................................................................81

Combination Mod e 6: FSK Modulation ........ ...... ....... ...... .................... ...... ....81

Combination Mode 7: Pulse-width Modulation (PWM) .................................82

Combinati on Mod e 8: Manch es ter Demodu lat ion /Pu ls e-wi dth

Demodulation ...............................................................82

Combination Mod e 9: Bipha se Demodul ati on .... ....... ................... ....... ..........83

Combination Mode Timer 2 and Timer 3 ............................................................84

Combination Mode 10: Frequency Measurement or Event Counter with

Time Gate ....................................................................85

Combination Mode 11: Burst Modulation 1 ...................................................85

Combination Mode Timer 2, Timer 3 and SSI ....................................................87

Combination Mode 12: Burst Modulation 2 ...................................................88

Combination Mode 13: FSK Modulation .......................................................88

Data EEPROM ....................................................................................................89

Serial Interface ....................................................................................................90

Serial Protocol ...............................................................................................90

Control Byte Format ......................................................................................91

EEPROM ............................................................................................................91

EEPROM – Operating Modes .......................................................................91

Write Operations ...........................................................................................91

Acknowledge Polling .....................................................................................91

Write One Data Byte .....................................................................................91

Write Two Data Bytes ...................................................................................91

Write Control Byte Only ................................................................................91

Write Control Bytes .......................................................................................92

Read Operations ...........................................................................................92

Read One Data Byte .....................................................................................92

Read Two Data Bytes ...................................................................................92

Read n Data Bytes ................... .................... ...... .................... ...... ....... ..........92

Read Control Bytes .......................................................................................92

Initialization the Serial Interface to the EEPROM ...............................................93

Absolute Maximum Ratings ............................................................... 94

106 T48C862-R3 4554A–4BMCU–02/03

Thermal Resis tance ........ .... ..... ................... .... ..... ..... .......................... 94

DC Operating Characteristics ............................................................ 94

AC Characteristics ..............................................................................96

Crystal Charac te ris ti cs .......................... ..... .... ....................................97

Ordering Information .......................................................................... 98

Package Information .......................................................................... 99

Table of Contents ............................................................................. 100

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