DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 DS90CR286A/DS90CR286AQ/DS90CR216A +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link - 66 MHz Check for Samples: DS90CR216A, DS90CR286A FEATURES DESCRIPTION * * * The DS90CR286A receiver converts the four LVDS data streams (Up to 1.848 Gbps throughput or 231 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data. Also available is the DS90CR216A that converts the three LVDS data streams (Up to 1.386 Gbps throughput or 173 Megabytes/sec bandwidth) back into parallel 21 bits of CMOS/TTL data. Both Receivers' outputs are Rising edge strobe. 1 2 * * * * * * * * 20 to 66 MHz Shift Clock Support 50% Duty Cycle on Receiver Output Clock Best-in-Class Set & Hold Times on RxOUTPUTs Rx Power Consumption <270 mW (typ) @66MHz Worst Case Rx Power-down Mode <200W (max) ESD Rating >7 kV (HBM), >700V (EIAJ) PLL Requires No External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-Lead or 48-Lead TSSOP Package Operating Temperature: -40C to +85C Automotive Q grade available - AEC-Q100 Grade 3 Qualified Both devices are offered in TSSOP packages. The DS90CR286A / DS90CR216A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. BLOCK DIAGRAM Figure 1. DS90CR286A See Package Number DGG-56 (TSSOP) Figure 2. DS90CR216A See Package Number DGG-48 (TSSOP) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated DS90CR216A, DS90CR286A SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 www.ti.com Absolute Maximum Ratings (1) (2) -0.3V to +4V Supply Voltage (VCC) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) Junction Temperature +150C Storage Temperature -65C to +150C Lead Temperature (Soldering, 4 sec) Maximum Package Power Dissipation Capacity @ 25C +260C DGG0056A (TSSOP) Package DS90CR286AMTD DGG0048A (TSSOP) Package DS90CR216AMTD 1.89 W DS90CR286AMTD 12.4 mW/C above +25C DS90CR216AMTD 15 mW/C above +25C Package Derating (HBM, 1.5 k, 100 pF) ESD Rating (1) (2) 1.61 W > 7 kV (EIAJ, 0, 200 pF) > 700V If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. "Electrical Characteristics" specify conditions for device operation. Recommended Operating Conditions Min Nom Max Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) -40 +25 +85 C 2.4 V 100 mVPP Receiver Input Range 0 Supply Noise Voltage (VCC) Units Electrical Characteristics (1) (2) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS (For PowerDown Pin) VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage IIN Input Current ICL = -18 mA -0.79 -1.5 V V IN = 0.4V, 2.5V or VCC +1.8 +10 A V IN = GND -10 2.7 A 0 CMOS/TTL DC SPECIFICATIONS VOH High Level Output Voltage IOH = -0.4 mA VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V IOS Output Short Circuit Current VOUT = 0V -60 -120 mA +100 mV 3.3 V LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold I IN (1) (2) 2 Input Current V CM = +1.2V -100 mV V IN = +2.4V, VCC = 3.6V 10 A V IN = 0V, VCC = 3.6V 10 A Typical values are given for VCC = 3.3V and TA = +25C. Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and V OD). Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 Electrical Characteristics(1)(2) (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT ICCRW CL = 8 pF, Worst Case Pattern, DS90CR286A (Figure 3 Figure 4), TA=-10C to +70C f = 33 MHz 49 65 mA f = 37.5 MHz 53 70 mA f = 66 MHz 81 105 mA CL = 8 pF, Worst Case Pattern, DS90CR286A (Figure 3 Figure 4), TA=-40C to +85C f = 40 MHz 53 70 mA Receiver Supply Current Worst Case f = 66 MHz 81 105 mA CL = 8 pF, Worst Case Pattern, DS90CR216A (Figure 3 Figure 4), TA=-10C to +70C f = 33 MHz 49 55 mA Receiver Supply Current Worst Case f = 37.5 MHz 53 60 mA f = 66 MHz 78 90 mA f = 40 MHz 53 60 mA Receiver Supply Current Worst Case CL = 8 pF, Worst Case Pattern, DS90CR216A (Figure 3 Figure 4), TA=-40C to +85C f = 66 MHz 78 90 mA Receiver Supply Current Power Down Power Down = Low Receiver Outputs Stay Low during Power Down Mode 10 55 A Receiver Supply Current Worst Case ICCRW ICCRW ICCRW ICCRZ Receiver Switching Characteristics (1) Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units CLHT Symbol CMOS/TTL Low-to-High Transition Time (Figure 4) 2 5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 4) 1.8 5 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 11, Figure 12) 1.0 1.4 2.15 ns RSPos1 Receiver Input Strobe Position for Bit 1 4.5 5.0 5.8 ns RSPos2 Receiver Input Strobe Position for Bit 2 8.1 8.5 9.15 ns RSPos3 Receiver Input Strobe Position for Bit 3 11.6 11.9 12.6 ns RSPos4 Receiver Input Strobe Position for Bit 4 15.1 15.6 16.3 ns RSPos5 Receiver Input Strobe Position for Bit 5 18.8 19.2 19.9 ns RSPos6 Receiver Input Strobe Position for Bit 6 22.5 22.9 23.6 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 11, Figure 12) 0.7 1.1 1.4 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns RSKM Parameter RxIN Skew Margin (2) (Figure 13) RCOP RxCLK OUT Period (Figure 5) RCOH RxCLK OUT High Time (Figure 5) RCOL Min f = 40 MHz f = 66 MHz f = 40 MHz 490 f = 66 MHz 400 ps ps 15 T 10.0 12.2 ns RxCLK OUT Low Time (Figure 5) 10.0 11.0 ns RSRC RxOUT Setup to RxCLK OUT (Figure 5) 6.5 11.6 ns RHRC RxOUT Hold to RxCLK OUT (Figure 5) 6.0 11.6 ns (1) (2) f = 40 MHz 50 ns Typical values are given for VCC = 3.3V and TA = +25C. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps). Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A Submit Documentation Feedback 3 DS90CR216A, DS90CR286A SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 www.ti.com Receiver Switching Characteristics(1) (continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter f = 66 MHz Min Typ Max Units RCOH RxCLK OUT High Time (Figure 5) 5.0 7.6 ns RCOL RxCLK OUT Low Time (Figure 5) 5.0 6.3 ns RSRC RxOUT Setup to RxCLK OUT (Figure 5) 4.5 7.3 ns RHRC RxOUT Hold to RxCLK OUT (Figure 5) 4.0 6.3 ns 3.5 5.0 (3) RCCD RxCLK IN to RxCLK OUT Delay @ 25C, VCC = 3.3V 7.5 ns RPLLS Receiver Phase Lock Loop Set (Figure 7) 10 ms RPDD Receiver Power Down Delay (Figure 10) 1 s (3) (Figure 6) Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. AC Timing Diagrams Figure 3. "Worst Case" Test Pattern Figure 4. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times Figure 5. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times 4 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 Figure 6. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay Figure 7. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time Figure 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A Submit Documentation Feedback 5 DS90CR216A, DS90CR286A SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 www.ti.com Figure 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A Figure 10. DS90CR286A/DS90CR216A (Receiver) Power Down Delay 6 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 Figure 11. DS90CR286A (Receiver) LVDS Input Strobe Position Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A Submit Documentation Feedback 7 DS90CR216A, DS90CR286A SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 www.ti.com Figure 12. DS90CR216A (Receiver) LVDS Input Strobe Position 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 C--Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos--Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2) Cable Skew--typically 10 ps-40 ps per foot, media dependent (1) Cycle-to-cycle jitter (2) ISI dependent is is less on than interconnect TBD ps length; at may 66 MHz. be zero. Figure 13. Receiver LVDS Input Skew Margin DS90CR286A PIN DESCRIPTIONS -- DGG0056A Package -- 28-Bit Channel Link Receiver Pin Name I/O No. Description RxIN+ I 4 Positive LVDS differentiaI data inputs. RxIN- I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN- I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. V CC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V CC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. DS90CR216A PIN DESCRIPTIONS -- DGG0048A Package -- 21-Bit Channel Link Receiver Pin Name I/O No. RxIN+ I 3 Positive LVDS differentiaI data inputs. (1) RxIN- I 3 Negative LVDS differential data inputs. (1) RxOUT O 21 TTL level data outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN- I 1 Negative LVDS differential clock input. RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe. PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low. V CC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL V CC I 1 Power supply for PLL. (1) Description These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last valid state. A floating/terminated clock input will result in a LOW clock output. Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A Submit Documentation Feedback 9 DS90CR216A, DS90CR286A SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 www.ti.com DS90CR216A PIN DESCRIPTIONS -- DGG0048A Package -- 21-Bit Channel Link Receiver (continued) I/O No. PLL GND Pin Name I 2 Ground pin for PLL. Description LVDS V CC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. Pin Diagram for TSSOP Packages Figure 14. DS90CR286AMTD Figure 15. DS90CR216AMTD 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A DS90CR216A, DS90CR286A www.ti.com SNLS043F - MAY 2000 - REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision E (February 2013) to Revision F * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: DS90CR216A DS90CR286A Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) DS90CR216AMTD NRND TSSOP DGG 48 38 TBD Call TI Call TI -40 to 85 DS90CR216AMTD >B DS90CR216AMTD/NOPB ACTIVE TSSOP DGG 48 38 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR216AMTD >B DS90CR216AMTDX/NOPB ACTIVE TSSOP DGG 48 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR216AMTD >B DS90CR286AMTD NRND TSSOP DGG 56 34 TBD Call TI Call TI -40 to 85 DS90CR286AMTD >B DS90CR286AMTD/NOPB ACTIVE TSSOP DGG 56 34 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR286AMTD >B DS90CR286AMTDX/NOPB ACTIVE TSSOP DGG 56 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR286AMTD >B DS90CR286AQMT/NOPB ACTIVE TSSOP DGG 56 34 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR286AQ MT DS90CR286AQMTX/NOPB ACTIVE TSSOP DGG 56 1000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR286AQ MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF DS90CR286A, DS90CR286A-Q1 : * Catalog: DS90CR286A * Automotive: DS90CR286A-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90CR216AMTDX/NOP B TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 DS90CR286AMTDX/NOP B TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 DS90CR286AQMTX/NOP B TSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90CR216AMTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 DS90CR286AMTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0 DS90CR286AQMTX/NOP B TSSOP DGG 56 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. 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