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MB88155
Spread Spectrum Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-08298 Rev. *B Revised January 4, 2018
MB88155 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can
be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. For modulation, the
MB88155 supports both center-spreading and down-spreading. It has a non-modulated clock output pin (REFOUT) as well as a
modulated clock output pin (CKOUT) .
Features
■Input frequency : 12.5 MHz to 50 MHz (Multiplied by 1)
12.5 MHz to 20 MHz (Multiplied by 4)
■Output frequency : CKOUT 12.5 MHz to 80 MHz
REFOUT The same as input frequency (not multiplied)
■Modulation rate : 0.5, 1.0 (center spread) , 1.0, 2.0 (Down spread)
■Equipped with oscillation circuit : range of oscillation 12.5 MHz to 40 MHz (Fundamental oscillation)
40 MHz to 48 MHz (3rd overtone)
■Modulation clock output Duty : 40 to 60
■Modulation clock cycle cycle jitter : MB88155-1xx 12.5 MHz to 20 MHz less than 150 ps
MB88155-1xx 20 MHz to 50 MHz less than 100 ps
MB88155-400 less than 200 ps
■Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load)
■Power supply voltage : 3.3 V 0.3 V
■Operating temperature : 40 °C to 85 °C
■Package : 8-pin plastic TSSOP
Document Number: 002-08298 Rev. *B Page 2 of 27
MB88155
Contents
Product Lineup ...................................................................... 3
Pin Assignment .....................................................................3
Pin Description ...................................................................... 4
I/O Circuit Type ......................................................................5
Handling Devices ...................................................................7
Preventing Latch-up ......................................................... 7
Handling Unused Pins ...................................................... 7
The Attention when the External Clock is Used ............... 7
Power Supply Pins ........................................................... 7
Oscillation Circuit .............................................................. 7
Block Diagram .......................................................................8
Pin Setting ..............................................................................9
Absolute Maximum Ratings ...............................................11
Recommended Operating Conditions ...............................12
Electrical Characteristics .................................................... 13
Output Clock Duty Cycle (tDCC, tDCR = tb/ta) ................ 15
Input Frequency (fin = 1/tin) ...................... .. .............. ... ..... 15
Output Slew Rate (SRC, SRR) ........................................... 15
Cycle-Cycle Jitter (tJC = |tn - tn + 1| ) .............................. . 16
Modulation Waveform ......................................................... 17
Lock-Up Time ............. .............. .............. .............. ... ............. 18
Oscillation Circuit ................................................................ 20
Interconnection Circuit Example ....................................... 21
Spectrum Example Characteristics ................................... 22
Ordering Information ........................................................... 23
Package Dimensions ........................................................... 24
Document History .................... .............. .............. .............. .. 26
Sales, Solutions, and Legal Information ........................... 27
Document Number: 002-08298 Rev. *B Page 3 of 27
MB88155
1. Product Lineup
The MB88155 is available in different models : 2 models different in multiplier (× 1 and × 4) , 2 in modulation type (center-spreading
and down-spreading) , 2 in input frequency range at a multiplier of 1 (12.5 MHz to 25 MHz and 25 MHz to 50 MHz) , and 1 in input
frequency range at a multiplier of 4 (12.5 MHz to 20 MHz) .
The MB88155 is also available in two versions : modulation-on/off selectable version (with ENS pin) and power-down function built-
in version (with XPD pin) .
Line-up of MB88155
2. Pin Assignment
MB88155-M T F
Input frequency range,
With/without ENS/XPD →Multiplied
by 1 0 : 12.5 MHz to 25.0 MHz, With ENS, Without XPD
1 : 25.0 MHz to 50.0 MHz, With ENS, Without XPD
2 : 12.5 MHz to 25.0 MHz, Without ENS, With XPD
3 : 25.0 MHz to 50.0 MHz, Without ENS, With XPD
Multiplied
by 4 0 : 12.5 MHz to 20.0 MHz, With ENS, Without XPD
Spread type →0 : Down spread, 1 : Center spread
Multiplication rate setting →1 : Multiplied by 1, 4 : Multiplied by 4
Product Input Frequency Multiplication
Rate Output
Frequency Modulation
Type Modulation
Enable pin Power
Down Pin
MB88155-100 12.5 MHz to 25 MHz
Multiplied by 1
The same as
input frequency
Down
spread
Yes No
MB88155-102 12.5 MHz to 25 MHz No Yes
MB88155-103 25 MHz to 50 MHz
MB88155-110 12.5 MHz to 25 MHz
Center
spread
Yes No
MB88155-111 25 MHz to 50 MHz
MB88155-112 12.5 MHz to 25 MHz No Yes
MB88155-400 12.5 MHz to 20 MHz Multiplied by 4 50 MHz to
80 MHz
Down
spread
Yes No
1
2
3
4
8
7
6
5
XIN
XOUT
ENS
SEL
V
DD
CKOUT
V
SS
REFOUT
1
2
3
4
8
7
6
5
XIN
XOUT
XPD
SEL
V
DD
CKOUT
V
SS
REFOUT
MB88155
-xx0
-xx1
MB88155
-xx2
-xx3
STA008
Document Number: 002-08298 Rev. *B Page 4 of 27
MB88155
3. Pin Description
Pin Name I/O Pin No. Description
XIN I 1 Connection pin of resonator/clock input pin
XOUT O 2 Connection pin of resonator
ENS/XPD I 3 Modulation enable pin/power down pin
SEL I 4 Modulation rate setting pin
Down spread, SEL “L” : Modulation rate 1.0
Down spread, SEL “H” : Modulation rate 2.0
Down spread, SEL “L” : Modulation rate 0.5
Down spread, SEL “H” : Modulation rate 1.0
REFOUT O 5 Non-modulated clock output pin
This pin becomes to“L” at power-down.
VSS 6GND Pin
CKOUT O 7 Modulated clock output pin
This pin becomes to“L” at power-down.
VDD 8 Power supply voltage pin
Document Number: 002-08298 Rev. *B Page 5 of 27
MB88155
4. I/O Circuit Type
(Continued)
Pin Circuit Type Remarks
SEL,
XPD
CMOS hysteresis input
ENS CMOS hysteresis input with pull-up
resistor of 50 k (Typ)
REFOUT ■CMOS output
■IOL 3 mA
■“L” output at power-down
50 kΩ
Document Number: 002-08298 Rev. *B Page 6 of 27
MB88155
(Continued)
Note : For XIN pin and XOUT pin, refer to “Oscillation Circuit”.
Pin Circuit Type Remarks
CKOUT
■CMOS output
■IOL 4 mA
■“L” output at power-down
Document Number: 002-08298 Rev. *B Page 7 of 27
MB88155
5. Handling Devices
5.1 Preventing Latch-up
A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or
(b) a voltage higher than the rating is applied between VDD and VSS. The latch-up, if it occurs, significantly increases the power supply
current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating.
5.2 Handling Unused Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor.
Unused output pin should be opened.
5.3 The Attention when the External Clock is Used
Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock.
Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin.
5.4 Power Supply Pins
Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source.
We recommend connecting electrolytic capacitor (about 10 F) and the ceramic capacitor (about 0.01 F) in parallel between VSS
and VDD near the device, as a bypass capacitor.
5.5 Oscillation Circuit
Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN
or XOUT pin and the resonator do not intersect other wiring.
Design the printed circuit board that surrounds the XIN and XOUT pins with ground.
Document Number: 002-08298 Rev. *B Page 8 of 27
MB88155
6. Block Diagram
VDD
CKOUT
REFOUT
VSS
Rf = 1 MΩ
XOUT
XIN
ENS/XPD
SEL
Modulation rate
setting
Reference
clock
PLL block Clock output
Phase
compare V/I
conversion
Loop filter
Reference
clock
Modulation logic
Modulation
clock
output
Modulation rate
setting/
Modulation
enable setting
Modulation enable/
power down setting
MB88155 PLL block
A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing
EMI.
Reference clock output
Power down signal
Charge
pump
Document Number: 002-08298 Rev. *B Page 9 of 27
MB88155
7. Pin Setting
The modulation clock requires stabilization wait time after the PIN setting is changed. For the modulation clock stabilization wait time,
assure the maximum value for “Lock-up time” in the AC Characteristics list in “ Electrical Characteristics”.
ENS Modulation Enable Setting
Note : Spectrum does not diffuse when “L” is set to ENS pin.
MB88155-xx2, xx3 do not have ENS pin.
XPD Power Down
Note : When setting “L” to XPD pin, it becomes power down mode (low power consumption mode) .
Both CKOUT and REFOUT of output pins are fixed to “L” output during power down.
MB88155-xx0, xx1 do not have XPD pin.
SEL Modulation Rate Setting
Note : The modulation rate can be changed at the level of the pin.
ENS Modulation
L No modulation MB88155-xx0, xx1
H Modulation
XPD Status
L Power down status MB88155-xx2, xx3
H Operating status
SEL Frequency
L 0.5MB88155-x1x
1.0MB88155-x0x
H 1.0MB88155-x1x
2.0MB88155-x0x
Document Number: 002-08298 Rev. *B Page 10 of 27
MB88155
■ Center Spread
Spectrum is spread (modulated) by centering on the non-spread frequency.
■ Down Spread
Spectrum is spread (modulated) below the non-spread frequency.
−1.0% +1.0%
Radiation level
Frequency
Non-spread frequency
Example of center spread at modulation rate 1.0
Modulation width 2.0
−2.0%
Non-spread frequency
Frequency
Radiation level
Example of down spread at modulation rate 2.0
Modulation width 2.0
Document Number: 002-08298 Rev. *B Page 11 of 27
MB88155
8. Absolute Maximum Ratings
* : The parameter is based on VSS 0.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit
Min Max
Power supply voltage* VDD 0.5 4.0 V
Input voltage* VIVSS 0.5 VDD 0.5 V
Output voltage* VOVSS 0.5 VDD 0.5 V
Storage temperature TST 55 125 °C
Operation junction
temperature
TJ 40 125 °C
Output current IO 14 14 mA
Overshoot VIOVER VDD 1.0 (tOVER 50 ns) V
Undershoot VIUNDER VSS 1.0 (tUNDER 50 ns) V
VDD
VSS
Input pin
Overshoot/Undershoot
tUNDER 50 ns
VIOVER VDD 1.0 V
tOVER 50 ns VIUNDER VSS 1.0 V
Document Number: 002-08298 Rev. *B Page 12 of 27
MB88155
9. Recommended Operating Conditions
(VSS 0.0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their Cypress representatives
beforehand.
Parameter Symbol Pin Conditions Value Unit
Min Typ Max
Power supply voltage VDD VDD 3.0 3.3 3.6 V
“H” level input voltage VIH XIN, SEL,
ENS, XPD
VDD × 0.8 VDD 0.3 V
“L” level input voltage VIL XIN, SEL,
ENS, XPD
VSS VDD × 0.2 V
Input clock
duty cycle
tDCI XIN 12.5 MHz to 50 MHz 40 50 60
Operating temperature Ta  40 85 °C
XIN
ta
tb
1.5 V
Input clock duty cycle (tDCI tb/ta)
Document Number: 002-08298 Rev. *B Page 13 of 27
MB88155
10. Electrical Characteristics
■ DC Characteristics
(Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V)
Parameter Symbol Pin Conditions Value Unit
Min Typ Max
Power supply current ICC VDD
24 MHz output
No load capacitance
5.0 7.0 mA
At power-down 10 A
Output voltage
VOHC CKOUT “H” level output
IOH 4 mA
VDD 0.5 VDD V
VOHR REFOUT “H” level output
IOH 3 mA
VOLC CKOUT “L” level output
IOL 4 mA
VSS 0.4 V
VOLR REFOUT “L” level output
IOL 3 mA
Output impedance ZOC CKOUT 12.5 MHz to 80 MHz 45 
ZOR REFOUT 12.5 MHz to 50 MHz 70
Input capacitance CIN XIN, SEL,
ENS/XPD
Ta 25 C
VDD VI 0.0 V
f 1 MHz
16 pF
Input pull-up resistor RPU ENS VIL 0.0 V 25 50 200 k
Load capacitance CL
REFOUT 12.5 MHz to 50 MHz 15 pF
CKOUT 12.5 MHz to 50 MHz 15
50 MHz to 80 MHz  7
Document Number: 002-08298 Rev. *B Page 14 of 27
MB88155
■ AC Characteristics
(Ta 40 °C to 85 °C, VDD 3.3 V 0.3 V, VSS 0.0 V)
*1 : Duty of the REFOUT output is guaranteed only for the following A and B because it depends on tDCI of input
clock duty.
A. Resonator input : When resonator is connected with XIN pin and XOUT pin, and oscillates normally.
B. External clock input : The input level is Full-swing (VSS VDD).
*2 : The modulation clock requires stabilization wait time after the IC is turned on or released from power-down
mode, or after SEL (modulation factor) or ENS (modulation enable) setting is changed. For the modulation clock
stabilization wait time, assure the maximum value for the lock-up time.
Parameter Symbol Pin Conditions Value Unit
Min Typ Max
Oscillation
frequency fxXIN,
XOUT
Fundamental oscillation 12.5 40 MHz
3rd overtone 40 48
Input frequency fin XIN
MB88155 1x0, 1x2 12.5 25 MHz
MB88155 1x1, 1x3 25 50
MB88155 400 12.5 20
Output frequency fOUT
REFOUT
MB88155 1x0, 1x2 12.5 25 MHz
MB88155 1x1, 1x3 25 50
MB88155 400 12.5 20
CKOUT
MB88155 1x0, 1x2 12.5 25
MB88155 1x1, 1x3 25 50
MB88155 400 50 80
Output slew rate
SRc CKOUT Load capacitance 15 pF,
0.4 V to 2.4 V
0.4 4.0 V/ns
SRRREFOUT Load capacitance 15 pF,
0.4 V to 2.4 V
0.3 2.0
Output clock
duty cycle
tDCC CKOUT 1.5 V reference level 40 60
tDCR REFOUT 1.5 V reference level tDCI 10*1tDCI 10*1
Modulation
frequency fMOD CKOUT Input frequency at 24 MHz 32.4 kHz
Lock-up time*2tLK CKOUT 25ms
Cycle-cycle jitter tJC CKOUT
MB88155 1xx
Input frequency
12.5 MHz to 20 MHz,
No load capacitance,
Ta 25 °C, VDD 3.3 V,
Standard deviation
150 ps
MB88155 1xx
Input frequency
20 MHz to 50 MHz,
No load capacitance,
Ta 25 °C, VDD 3.3 V,
Standard deviation
100 ps
MB88155 400
No load capacitance,
Ta 25 °C, VDD 3.3 V, Stan-
dard deviation
200 ps
Document Number: 002-08298 Rev. *B Page 15 of 27
MB88155
11. Output Clock Duty Cycle (tDCC, tDCR tb/ta)
12. Input Frequency (fin 1/tin)
13. Output Slew Rate (SRC, SRR)
CKOUT,
REFOUT
1.5 V
t
a
t
b
0.8 VDD
tin
XIN
2.4 V
0.4 V
tf
t
r
CKOUT,
REFOUT
Note : SRC (2.4 0.4) /tr, SRC (2.4 0.4) /tf
SRR (2.4 0.4) /tr, SRR (2.4 0.4) /tf
Document Number: 002-08298 Rev. *B Page 16 of 27
MB88155
14. Cycle-Cycle Jitter (tJC |tn tn 1| )
tn+1tn
CKOUT
Note : Cycle-cycle jitter indicates the difference between a certain cycle and the immediately
succeeding (or preceding) cycle.
Document Number: 002-08298 Rev. *B Page 17 of 27
MB88155
15. Modulation Waveform
fMOD (Typ) = 32.4 kHz (fin = 24 MHz)
− 1.0 %
+ 1.0 %
− 1.0 %
− 0.5 %
fMOD (Typ) = 32.4 kHz (fin = 24 MHz)
■ Modulation rate 1.0, example of center spread
■ Modulation rate 1.0, example of down spread
CKOUT output
frequency
CKOUT output
frequency
Frequency at
modulation off
Frequency at
modulation off
Time
Time
Document Number: 002-08298 Rev. *B Page 18 of 27
MB88155
16. Lock-Up Time
If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT
pin is (the stabilization wait time of input clock to XIN pin) (the lock-up time “tLK”). For the input clock stabilization time, check the
characteristics of the resonator or oscillator used.
If the XPD pin is used for power-down control, the set clock signal is output from the CKOUT pin at most the lock-up
time “tLK” after the XPD pin goes “H” level. (Continued)
3.0 V
VDD
XIN
XPD VIH
VIH
CKOUT
SEL
ENS
External clock
stabilization waiting time
tLK (Lock-up time)
V
IH
V
IH
3.0 V
V
DD
XIN
XPD
CKOUT
SEL
ENS
External clock
stabilization waiting time
tLK (Lock-up time)
Document Number: 002-08298 Rev. *B Page 19 of 27
MB88155
(Continued)
If the ENS pin is used for modulation enable control during normal operation, the set clock signal is output from the CKOUT pin at
most the lock-up time “tLK” after the level at the ENS pin is determined.
Note : The wait time for the clock signal output from the CKOUT pin to become stable is required after the IC is released from power-
down mode by the XPD pin or after another pin’s setting is changed. During the period until the output clock signal becomes
stable, neither of the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter characteristic cannot
be guaranteed. It is therefore advisable to take action, such as cancelling a device reset at the stage after the lock-up time
has passed.
VIL
VIH
XIN
ENS
CKOUT
tLK (Lock-up time) tLK (Lock-up time)
Document Number: 002-08298 Rev. *B Page 20 of 27
MB88155
17. Oscillation Circuit
The following schematic on the left-hand side shows a sample connection of a general resonator. The oscillation circuit contains a
feedback resistor (1 M) . The values of capacitors (C1 and C2) must be adjusted to the optimum constant of the resonator used.
The following schematic on the right-hand side shows a sample connection of a 3rd overtone resonator. The values of capacitors (C1,
C2, and C3) and inductor (L1) must be adjusted to the optimum constant of the resonator used.
The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most
suitable value.
To use an external clock signal (without using the resonator) , input the clock signal to the XIN pin with the XOUT pin connected to
nothing.
C1
Rf (1 MΩ)
C2C1
L1
Rf (1 MΩ)
C2
C3
XIN pin XOUT pin XIN pin XOUT pin
LSI internal
LSI external
Fundamental resonator 3rd overtone resonator
■ When using the resonator
OPEN
Rf (1 MΩ)
■ When using the external clock
Note : Note that the jitter characteristic of the input clock signal may affect the cycle-cycle jitter characteristic.
LSI internal
LSI external
XOUT pin
External clock
XIN pin
Document Number: 002-08298 Rev. *B Page 21 of 27
MB88155
18. Interconnection Circuit Example
1
2
3
4
8
7
6
5
MB88155
C1C2
C4C3
R1
R2
C1, C2 : Oscillation stabilization capacitance (refer to “ Oscillation Circuit”)
C3 : Capacitor of 10 F or higher
C4 : Capacitor of about 0.01 F (connect a capacitor of good high frequency property
(ex. laminated ceramic capacitor) to close to this device)
R1, R2 : Impedance matching resistor for board pattern
Document Number: 002-08298 Rev. *B Page 22 of 27
MB88155
19. Spectrum Example Characteristics
The condition of the examples of the characteristic is shown as follows : Input frequency 16 MHz (Output frequency 64 MHz :
Using MB88155 (Multiplied by 4) )
Power-supply voltage 3.3 V, None load capacity. Modulation rate 1.0 (center spread).
Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW 1 kHz (ATT use for 6 dB) .
CH B Spectrum 10 dB /REF 0 dBm
Avg
4
RBW# 1 kH
Z
VBW 1 kH
Z
ATT 6 dB
CENTER 64 MH
Z
SWP 8.005 s
SPAN 12.8 MH
Z
No modulation
5.64 dBm
1.0 modulation
26.93 dBm
Document Number: 002-08298 Rev. *B Page 23 of 27
MB88155
20. Ordering Information
Part Number Input
Frequency Multiplica-
tion Rate Output
Frequency Modulation
Type Modulation
Enable
Pin
Power
Down
Pin Package Remarks
MB88155PFT-G-
100-JN-EFE1
12.5 MHz to
25 MHz
Multiplied
by 1
The same
as input fre-
quency
Down
spread
Yes No
8-pin plastic
TSSOP
(STA008)
Emboss
taping
(EF type)
MB88155PFT-G-
102-JN-EFE1
12.5 MHz to
25 MHz No Yes
MB88155PFT-G-
103-JN-EFE1
25 MHz to 50
MHz
MB88155PFT-G-
110-JN-EFE1
12.5 MHz to
25 MHz The same
as input fre-
quency
Center
spread
Yes No
MB88155PFT-G-
111-JN-EFE1
25 MHz to 50
MHz
MB88155PFT-G-
112-JN-EFE1
12.5 MHz to
25 MHz No Yes
MB88155PFT-G-
400-JN-EFE1
12.5 MHz to
20 MHz
Multiplied
by 4
50 MHz to
80 MHz
Down
spread Yes No
MB88155PFT-G-
100-JN-ERE1
12.5 MHz to
25 MHz
Multiplied
by 1
The same
as input fre-
quency
Down
spread
Yes No
8-pin plastic
TSSOP
(STA008)
Emboss
taping
(ER type)
MB88155PFT-G-
103-
JN-
ERE1
25 MHz to
50 MHz No Yes
MB88155PFT-G-
110-
JN-
ERE1
12.5 MHz to
25 MHz
Center
spread
Yes No
MB88155PFT-G-
111-
JN-
ERE1
25 MHz to
50 MHz
MB88155PFT-G-
112-
JN-
ERE1
12.5 MHz to
25 MHz No Yes
MB88155PFT-G-
400-
JN-
ERE1
12.5 MHz to
20 MHz
Multiplied
by 4
50 MHz to
80 MHz
Down
spread Yes No
Document Number: 002-08298 Rev. *B Page 24 of 27
MB88155
21. Package Dimensions
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7+('$0%$50$<127%(/2&$7('217+(/2:(55$',862)7+()227
7+,6&+$0)(5)($785(,6237,21$//),7,612735(6(177+(1$3,1
,'(17,),(50867%(/2&$7(':,7+,17+(,1'(;$5($,1',&$7('
$,6'(),1('$67+(9(57,&$/',67$1&()5207+(6($7,1*3/$1(72
7+(/2:(6732,17217+(3$&.$*(%2'<(;&/8',1*7+(/,'$1'25
7+(50$/(1+$1&(0(1721&$9,7<'2:13$&.$*(&21),*85$7,216
127(6
11. JEDEC SPECIFICATION NO. REF : N/A
L1
L
c
NOM.MIN.
E
0°
D
A
1A
SYMBOL
MAX.
8°
ș
E1
b
e
DIMENSION
L20.25 BSC
1.20
0.05 0.15
3.10 BSC
6.40 BSC
4.40 BSC
0.047 0.207
0.12 0.22 0.32
0.50 0.60 0.70
1.00 REF
0.65 BSC
D
4
5
E1 E
0.20 CA-B D
A
A1
10
DETAIL A
e0.10 C
SEATING
PLANE
b0.10 CA-B D8
SIDE VIEW
TOP VIEW
b
SECTION A-A'
c
L1
L
GAUGE
PLANE
DETAIL A
L2
șA
A'
0.10 H D
;
0.10 H D
㻭㻰
㻯
4
5
INDEX AREA
;
㻮
BOTTOM VIEW
002-15912 Rev. **
Document Number: 002-08298 Rev. *B Page 26 of 27
MB88155
Document History
Spansion Publication Number: DS04-291 19-2Ea
Document Title: MB88155 Spread Spectrum Clock Generator
Document Number: 002-08298
Revision ECN Orig. of
Change Submission
Date Description of Change
** – TAOA 11/09/2006 Initial Release
*A 5568597 TAOA 12/29/2016 Updated to Cypress Template
*B 5998865 TAOA 01/04/2018
Deleated EOL part number: MB88155-101/113/402/410/412
Updated Package Dimensions: Updated to Cypress format
Changed the package name from FPT-8P-M07 to STA008
Document Number: 002-08298 Rev. *B Revised January 4, 2018 Page 27 of 27
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