MX26LV160ABMC-55G - Macronix International

P/N:PM1123 REV. 1.1, NOV. 18, 2004

MX26LV160AT/AB

16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE

3V ONLY BOOT SECTOR HIGH SPEED eLiteFlashTM MEMORY

- Provides a hardware method of detecting program or

erase operation completion

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

- Temporary sector unprotect allows code changes in

previously locked sectors

• CFI (Common Flash Interface) compliant

- Flash device parameters stored on the device and

provide the host system to access

• 2K minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Package type:

- 44-pin SOP

- 48-pin TSOP

- 48-ball CSP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

• 20 years data retention

FEATURES

• Extended single - supply voltage range 3.0V to 3.6V

• 2,097,152 x 8 / 1,048,576 x 16 switchable

• Single power supply operation

- 3.0V only operation for read, erase and program

operation

• Fast access time: 55/70ns

• Low power consumption

- 30mA maximum active current

- 30uA typical standby current

• Command register architecture

- Byte/word Programming (55us/70us typical)

- Sector Erase (Sector structure 16K-Bytex1,

8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)

• Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with

erase verify capability

- Automatically program and verify data at specified

address

• Status Reply

- Data# polling & Toggle bit for detection of program

and erase operation completion

• Ready/Busy# pin (RY/BY#)

GENERAL DESCRIPTION

The MX26L V160AT/AB is a 16-mega bit high speed Flash

memo ry o rganized as 2M b ytes o f 8 bits o r 1M w o rds o f

16 bits. MXIC's high speed Flash memories offer the

most cost-effective and reliable read/wr ite non-volatile

rando m access memory . The MX26LV160AT/AB is pack-

aged in 44-pin SOP, 48-pin TSOP, and 48-ball CSP. It is

designed to be repro grammed and er ased in system or

in standard EPROM pro grammers.

The standard MX26LV160AT/AB o ffers access time as

fast as 55ns, allowing o peratio n of high-speed micro pro-

cessors without wait states. To eliminate bus conten-

tion, the MX26LV160AT/AB has separate chip enable

(CE#) and o utput enable (OE#) co ntrols.

MXIC's high speed Flash memories augment EPROM

functionality with in-circuit electrical erasure and program-

ming. The MX26LV160AT/AB uses a co mmand register

to manage this functionality. The command register al-

lows for 100% TTL lev el control inputs and fixed pow er

supply levels during erase and pro gramming, while main-

taining maximum EPR OM compatibility.

MXIC high speed Flash technology reliably stores

memory contents even after 2K erase and program

cycles. The MXIC cell is designed to optimize the erase

and pro gramming mechanisms . In additio n, the co mbi-

natio n of advanced tunnel o xide processing and low in-

ternal electr ic fields for erase and program operations

pro duces reliable cycling. The MX26LV160AT/AB uses

a 3.0V~3.6V VCC supply to perfo rm the High Reliability

Erase and auto Pro gram/Erase algo rithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pin from -1V to VCC + 1V.

Macronix NBitTM Memory Family

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

PIN CONFIGURATIONS PIN DESCRIPTION

SYMBOL PIN NAME

A0~A19 Address Input

Q0~Q14 Data Input/Output

Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)

CE# Chip Enable Input

WE# Write Enable Input

BYTE# Word/Byte Selection input

RESET# Hardware Reset Pin

OE# Output Enable Input

R Y/BY# Ready/Busy Output

VCC P ower Supply Pin (3.0V~3.6V)

GND Ground Pin

44 SOP

48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down

ABCDEFGH

6 A13 A12 A14 A15 A16 BYTE# Q15/A-1 GND

5 A9 A8 A10 A11 Q7 Q14 Q13 Q6

4 WE# RESET# NC A19 Q5 Q12 Vcc Q4

3 RY/BY# NC A18 NC Q2 Q10 Q11 Q3

2 A7 A17 A6 A5 Q0 Q8 Q9 Q1

1A3A4A2A1A0CE#OE#GND

A15

A14

A13

A12

A11

A10

A19

WE#

RESET#

RY/BY#

A18

A17

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

OE#

GND

CE#

MX26LV160AT/AB

48 TSOP (Standard Type) (12mm x 20mm)

RESET#

A18

A17

CE#

GND

OE#

Q10

Q11

WE#

A19

A10

A11

A12

A13

A14

A15

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

MX26LV160AT/AB

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

BLOCK STRUCTURE

TABLE 1: MX26LV160AT SECTOR ARCHITECTURE

Sector Sector Size Address range Sector Address

Byte Mode W ord Mode Byte Mode(x8) W ord Mode(x16) A19 A18 A 17 A16 A15 A 14 A13 A12

SA0 64Kbytes 32Kwords 000000-00FFFF 00000-07FFF 00000XXX

SA1 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XXX

SA2 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XXX

SA3 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XXX

SA4 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XXX

SA5 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XXX

SA6 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XXX

SA7 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XXX

SA8 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XXX

SA9 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XXX

SA10 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XXX

SA11 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XXX

SA12 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XXX

SA13 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XXX

SA14 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XXX

SA15 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XXX

SA16 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XXX

SA17 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XXX

SA18 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XXX

SA19 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XXX

SA20 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XXX

SA21 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XXX

SA22 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XXX

SA23 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XXX

SA24 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XXX

SA25 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XXX

SA26 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XXX

SA27 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XXX

SA28 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XXX

SA29 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XXX

SA30 64Kbytes 32Kwords 1E0000-1EFFFF F0000-F7FFF 11110XXX

SA31 32Kbytes 16Kwords 1F0000-1F7FFF F8000-FBFFF 111110XX

SA32 8Kbytes 4Kwords 1F8000-1F9FFF FC000-FCFFF 1111110 0

SA33 8Kbytes 4Kwords 1FA000-1FBFFF FD000-FDFFF 1111110 1

SA34 16Kbytes 8Kwords 1FC000-1FFFFF FE000-FFFFF 1111111X

No te: Byte mo de: address range A19:A-1, wo rd mode:address range A19:A0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

TABLE 2: MX26LV160AB SECTOR ARCHITECTURE

Sector Sector Size Address range Sector Address

Byte Mode W ord Mode Byte Mode (x8) W ord Mode (x16) A19 A 18 A 17 A16 A15 A14 A 13 A12

SA0 16Kbytes 8Kwords 000000-003FFF 00000-01FFF 0000000 X

SA1 8Kbytes 4Kwords 004000-005FFF 02000-02FFF 0000001 0

SA2 8Kbytes 4Kwords 006000-007FFF 03000-03FFF 0000001 1

SA3 32Kbytes 16Kwords 008000-00FFFF 04000-07FFF 000001XX

SA4 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XXX

SA5 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XXX

SA6 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XXX

SA7 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XXX

SA8 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XXX

SA9 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XXX

SA10 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XXX

SA11 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XXX

SA12 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XXX

SA13 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XXX

SA14 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XXX

SA15 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XXX

SA16 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XXX

SA17 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XXX

SA18 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XXX

SA19 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XXX

SA20 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XXX

SA21 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XXX

SA22 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XXX

SA23 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XXX

SA24 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XXX

SA25 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XXX

SA26 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XXX

SA27 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XXX

SA28 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XXX

SA29 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XXX

SA30 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XXX

SA31 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XXX

SA32 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XXX

SA33 64Kbytes 32Kwords 1E0000-1EFFFF F0000-FFFFF 11110XXX

SA34 64Kbytes 32Kwords 1F0000-1FFFFF F8000-FFFFF 11111XXX

No te: Byte mo de:address range A19:A-1, wo rd mode:address range A19:A0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTA GE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER

Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-A19

CE#

OE#

WE#

RESET#

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AUTOMATIC PROGRAMMING

The MX26LV160AT/AB is wo rd/byte programmable us-

ing the Automatic Programming algorithm. The Auto-

matic Programming algorithm makes the e xternal sys-

tem do no t need to have time o ut sequence nor to verify

the data pro grammed.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's A uto matic Pro g ramming algo rithm requires the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(program data and address). The device auto matically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to DATA# polling and a status bit

toggling between consecutive read cycles, provide feed-

back to the user as to the status of the programming

operation. Refer to write operatio n status, table 7, for more

inf o rmatio n on these status bits.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

The Auto matic Erase algo rithm automatically pro grams

the entire arra y prio r to electrical erase. The timing and

verification of electrical erase are controlled internally

within the device.

AUTOMATIC SECTOR ERASE

The MX26L V160AT/AB is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. The Automatic Sector

Erase algorithm automatically programs the specified

secto r(s) prio r to electrical erase. The timing and v erifi-

catio n of electrical erase are co ntro lled internally within

the device. An erase operation can erase one sector,

multiple sectors, or the entire device .

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard micro processor write timings. The device will auto-

matically pre-pro g ram and verify the entire arra y. Then

the device automatically times the erase pulse width,

pro vides the erase verificatio n, and counts the number o f

sequences. A status bit toggling between consecutive

read cycles pro vides f eedback to the user as to the sta-

tus o f the erasing o peration.

machine which controls the erase and programming cir-

cuitry . During write cycles, the co mmand register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first.

MXIC's high speed Flash technology combines years of

EPROM experience to produce the highest levels of

quality, reliability, and cost effectiveness. The

MX26LV160AT/AB electrically erases all bits simulta-

neo usly using Fowler-No rdheim tunneling. The bytes are

pro grammed by using the EPROM pro gramming mecha-

nism o f ho t electro n injectio n.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. After the state machine

has co mpleted its task, it will allo w the co mmand regis-

ter to respond to its full co mmand set.

AUTOMATIC SELECT

The auto select mode provides manufacturer and de-

vice identificatio n, protectio n verification, thro ugh identi-

fier codes output o n Q7~Q0. This mode is mainly adapted

for programming equipment on the device to be pro-

grammed with its pro gramming algo rithm. When pro gram-

ming by high v oltage metho d, auto matic select mode re-

quires VID (11V to 12V) on address pin A9 and other

address pin A6, A1 and A0 as referring to Table 3. In

addition, to access the automatic select codes in-sys-

tem, the host can issue the automatic select command

thro ugh the co mmand register witho ut requiring VID , as

shown in table 4.

To verify whether o r not secto r being protected, the sec-

tor address must appear on the appropriate highest order

address bit (see T able 1 and T able 2). The rest of address

bits, as shown in Table 3, are do n't care. Once all neces-

sary bits have been set as required, the programming

equipment may read the co rrespo nding identifier code o n

Q7~Q0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

A19 A11 A9 A8 A6 A5 A1 A0

Description Mode CE# OE# WE# | | | | Q15~Q0

A12 A10 A7 A2

Manufacturer Code L L H X X VID X L X L L C2H

Read Device ID W ord L L H X X V ID X L X L H 22C4H

Silico n (To p Bo ot Blo ck) Byte L L H X X VID X L X L H XXC4H

ID Device ID W or d L L H X X VID X L X L H 2249H

(Bo tto m Bo o t Blo ck) Byte L L H X X VID X L X L H XX49H

XX01H

Secto r Protection V erification L L H SA X VID X L X H L (protected)

XX00H

(unprotected)

TABLE 3. MX26LV160AT/AB AUTO SELECT MODE OPERATION

NO TE:SA=Secto r Address , X=Do n't Care , L=Lo gic Low, H=Lo gic High

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset 1 XXXH F0H

Read 1 RA RD

Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI

Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI

Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H

Verify x02H XX01H

Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H

x04H 01H

Program Word 4 555H AAH 2AAH 55H 555H A0H PA PD

Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD

Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H

CFI Query Word 1 555H 98

Byte AAAH 98

TABLE 4. MX26LV160AT/AB COMMAND DEFINITIONS

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 22DA/DA(Top), and 225B/5B(Bottom) for device code.

X = X can be VIL or VIH

RA=Address of memor y location to be read.

RD=Data to be read at location RA.

2. PA = Address of memor y location to be programmed.

PD = Data to be programmed at location PA.

SA = Address of the sector.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A19=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).

Write Sequence may be initiated with A11~A19 in either state.

4. F or Secto r Protect Verify operation : If read o ut data is 01H, it means the sector has been pro tected. If read out data is 00H, it

means the sector is still not being protected.

5. Any number of CFI data read cycles are per mitted.

in the improper sequence will reset the device to the

read mo de. Table 5 defines the v alid register co mmand

sequences.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ADDRESS Q8~Q15

DESCRIPTION CE# OE# WE# RE- A19 A11 A 9 A8 A 6 A 5 A 1 A 0 Q0~Q7 BYTE BYTE

SET# A12 A10 A7 A2 =VIH =VIL

Read L L H H AIN Dout Dout Q8~Q14

=High Z

Q15=A-1

Write L H L H AIN DIN(3) DIN

Reset X X X L X High Z High Z High Z

Output Disable L H H H X High Z High Z High Z

Standby Vcc±X X Vcc± X High Z High Z High Z

0.3V 0.3V

Secto r Pro tect L H L VID SA X X X L X H L DI N X X

Chip Unprotect L H L VID X XXXHXHL DIN X X

Secto r Protection L L H H SA X VID X L X H L CODE(5) X X

V erify

TABLE 5. MX26LV160AT/AB BUS OPERATION

NOTES:

1. Manuf acturer and device co des may also be accessed via a co mmand register write sequence. Ref er to Table 4.

2. VID is the Silico n-ID-Read high v oltage, 11V to 12V.

3. Refer to Table 5 fo r valid Data-In during a write operatio n.

4. X can be VIL or VIH.

5 . Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

6. A19~A12=Secto r address fo r secto r pro tect.

7. The secto r protect and chip unpro tect functions may also be implemented via pro gramming equipment.

COMMAND DEFINITIONS

De vice o perations are selected by writing specific address and data sequences into the co mmand register . Writing

incorrect address and data values or writing them in the improper sequence will reset the device to the read mode.

Table 5 defines the v alid register command sequences.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates arra y data to the o utput pins . WE# should re-

main at VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

micro processo r read cycles that assert valid address o n

the device address inputs produce valid data on the de-

vice data outputs. The de vice remains enab led f or read

access until the command register contents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase secto rs of memo ry

, the system must driv e WE# and CE# to VIL, and OE#

to VIH.

The "Wo rd/b yte Pro gram Co mmand Sequence" sectio n

has details on programming data to the device.

An erase operation can erase one sector, multiple sec-

tors , or the entire device. Table indicates the address

space that each sector occupies. A "sector address"

consists of the address bits required to uniquely select a

sector. The "Writing specific address and data commands

or sequences into the command register initiates device

operations. Table 1 defines the valid register command

sequences. Writing incorrect address and data values o r

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip.

After the system writes the autoselect command se-

quence, the device enters the autoselect mo de. The sys-

tem can then read autoselect codes from the internal

Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Autoselect Command

Sequence section for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

STANDBY MODE

When using both pins of CE# and RESET#, the device

enter CMOS Standby with bo th pins held at VCC ± 0.3V.

If CE# and RESET# are held at VIH, but not within the

range o f VCC ± 0.3V, the device will still be in the standby

mo de, but the standby current will be larger. During Auto

Algo rithm o peration, Vcc active current (Icc2) is required

even CE# = "H" until the operation is completed. The

device can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

fro m the devices are disabled. This will cause the o utput

pins to be in a high impedance state.

RESET# OPERATION

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RESET#

pin is driven low for at least a period of tRP, the device

immediately terminates any operation in progress, tri-

states all output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse. The de-

vice also resets the internal state machine to reading

array data. The o peration that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

The RESET# pin ma y be tied to system reset circuitry.

A system reset would that also reset the high speed

Flash, enabling the system to read the boot-up firmware

from the high speed Flash.

If RESET# is asserted during a program o r erase o pera-

tio n, the RY/BY# pin remains a "0" (busy) until the inter-

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

nal reset o peratio n is complete, which requires a time o f

tREAD Y (during Embedded Algorithms). The system can

thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asser ted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms). The sys-

tem can read data tRH after the RESET# pin returns to

VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 21 f or the timing diagram.

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID READ COMMAND

High speed Flash memories are intended for use in ap-

plications where the local CPU alters memory contents.

As such, manufacturer and device codes must be ac-

cessible while the device resides in the target system.

PROM programmers typically access signature codes

by raising A9 to a high voltage (VID). However, multi-

plexing high voltage onto address lines is not generally

desired system design practice.

The MX26LV160AT/AB contains a Silicon-ID-Read op-

eration to supple traditio nal PROM programming meth-

odology. The operation is initiated by writing the read

silico n ID command sequence into the co mmand regis-

ter.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlo c k" write cycles. These are f o llo wed by writing the

"set-up" co mmand 80H. Two more "unlo ck" write cycles

are then followed by the chip erase command 10H or

secto r erase co mmand 30H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory fo r an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1" (see Table 7), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE# o r CE# pulse, whichever happens first in the

command sequence and terminates when the data on

Q7 is "1" at which time the device returns to the Read

mode, or the data on Q6 stops toggling for two consecu-

tive read cycles at which time the device returns to the

Read mode.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

READING ARRAY DATA

The device is automatically set to reading array data

after device power-up. No commands are required to re-

trieve data. The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algo rithm.

The system must issue the reset command to re-en-

able the de vice fo r reading array data if Q5 go es high, or

while in the "read silicon-ID" and "sector protect v erify"

mo de . See the "Reset Co mmand" sectio n, ne xt.

Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code Word VIL VIL 00H 1 1 0 0 0 0 1 0 00C2H

Byte VIL VIL X 1 1 0 0 0 0 1 0 C2H

Device co de W o r d VIH VIL 2 2H 1 1 0 0 0 1 0 0 22C4H

for MX26LV160A T Byte VIH VIL X 1 1 0 0 0 1 0 0 C4H

Device co de W o r d VIH VIL 2 2H 0 1 0 0 1 0 0 1 2249H

fo r MX26LV160AB Byte VIH VIL X 0 1 0 0 1 0 0 1 49H

Sector Protection W o rd X VIH X 0 0 0 0 0 0 0 1 01H (Protected)

Ver ification Byte X VIH X 0 0 0 0 0 0 0 0 00H (Unprotected)

TABLE 6. SILICON ID CODE

RESET COMMAND

Writing the reset co mmand to the de vice resets the de-

vice to reading array data. Address bits are don't care for

this co mmand.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, howev er, the device igno res

reset co mmands until the o peratio n is co mplete.

The reset command may be written between the se-

quence cycles in a pro gram co mmand sequence befo re

programming begins. This resets the device to reading

array data Once pro gramming begins, however, the de-

vice igno res reset commands until the o peration is co m-

plete.

The reset command may be written between the se-

quence cycles in an SILICON ID READ command se-

quence. Once in the SILICON ID READ mo de, the reset

co mmand must be written to return to reading array data.

If Q5 go es high during a program o r erase operatio n, writ-

ing the reset command retur ns the device to read-ing

array data.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Sector Erase Set-up command and Au-

tomatic Sector Erase command. Upon executing the

Automatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is no t required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when either the data on Q7 is "1" at which time the de-

vice returns to the Read mode, or the data on Q6 stops

toggling for two consecutive read cycles at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The secto r address is latched on the falling edge o f WE#

or CE#, whichever happens later, while the command

(data) is latched on the rising edge of WE# or CE#,

whichever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE# or CE#, whichever happens later. Each succes-

sive sector load cycle started by the falling edge o f WE#

or CE#, whichever happens later must begin within 50us

fro m the rising edge of the preceding WE# or CE#, which-

ever happens first. Otherwise, the loading period ends

and internal auto secto r erase cycle starts. (Monito r Q3

to determine if the sector erase timer window is still open,

see section Q3, Sector Erase Timer.) Any co mmand other

than Sector Erase (30H) during the time-out period re-

sets the de vice to read mode.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device pro grams o ne byte o f data fo r each pro gram

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlo ck write cycles,

fo llowed by the pro gram set-up co mmand. The pro gram

address and data are written next, which in turn initiate

the Embedded Pro gram algo rithm. The system is not re-

quired to provide further co ntrols o r timings . The de vice

automatically generates the program pulses and verifies

the pro grammed cell margin. Table 1 shows the address

and data requirements f or the word/byte program com-

mand sequence.

When the Embedded Program algo rithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status o f the pro gram o peratio n by using Q7, Q6, o r R Y/

BY#. See "Write Operation Status" for info rmation on these

status bits.

Any co mmands written to the device during the Embed-

ded Program Algo rithm are ignored. Note that a hardware

reset immediately terminates the programming o peration.

The word/byte Pro gram command sequence sho uld be

reinitiated once the device has reset to reading array

data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the op-

eration and set Q5 to "1", or cause the Data# Polling

algorithm to indicate the o peration was successful. How-

ever, a succeeding read will show that the data is still

"0". Only erase o perations can co nvert a "0" to a "1".

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/

BY#. T able 7 and the following subsections describe the

functio ns of these bits. Q7, RY/BY#, and Q6 each o ffer a

metho d fo r determining whether a program o r erase o p-

eration is complete or in progress. These three bits are

discussed first.

Q7: Data# Polling

The Data# Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted. Data# Po lling is valid after the rising edge o f the

final WE# pulse in the program or erase command se-

quence.

During the Auto matic Pro gram algo rithm, the device o ut-

puts o n Q7 the complement of the datum programmed to

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Q7. When the A utomatic Pro gram algo rithm is complete,

the device outputs the datum programmed to Q7. The

system must pro vide the pro gr am address to read valid

status info rmation o n Q7.

During the Auto matic Erase algo rithm, Data# Polling pro-

duces a "0" o n Q7. When the Auto matic Erase algo rithm

is co mplete, Data# P o lling pro duces a "1" o n Q7. This is

analogous to the complement/true datum out-put de-

scribed for the Automatic Pro gr am algorithm: the er ase

function changes all the bits in a sector to "1" prior to

this, the device outputs the "complement," or "0". The

system must provide an address within any of the sec-

to rs selected fo r erasure to read v alid status info rmation

o n Q7.

After an erase co mmand sequence is written, if all sec-

to rs selected fo r erasing are pro tected, Data# Po lling on

Q7 is active for approximately 100 us, then the device

returns to reading arra y data. If no t all selected sectors

are pro tected, the Auto matic Erase algo rithm erases the

unprotected sector s, and ignores the selected sector s

that are pro tected.

When the system detects Q7 has changed from the

co mplement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE#) is asserted low.

RY/BY# : Ready/Busy

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algo rithm

is in progress or complete. The RY/BY# status is valid

after the rising edge o f the final WE# o r CE#, whichever

happens first, in the command sequence. Since RY/BY#

is an o pen-drain output, several RY/BY# pins can be tied

to gether in parallel with a pull-up resisto r to VCC.

If the o utput is low (Busy), the device is activ ely erasing

o r programming. If the output is high (Ready), the de vice

is ready to read arra y data, or is in the standby mode.

Table 7 shows the outputs for RY/BY# during write op-

eration.

Q6:Toggle BIT I

To ggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete. T oggle

Bit I may be read at any address, and is valid after the

rising edge of the final WE# o r CE#, whichever happens

first, in the co mmand sequence (prio r to the pro gr am o r

erase o peratio n), and during the sector time-out.

During an Auto matic Program o r Erase algo rithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

co ntrol the read cycles. When the operatio n is co mplete,

Q6 sto ps to ggling.

When the device is actively erasing (that is, the Auto-

matic Erase algo rithm is in progress), Q6 to ggling. How-

e v er, the system must also use Q2 to determine which

sectors are erasing. Alter natively, the system can use

Q7.

Q6 sto ps toggling once the Auto matic Program algo rithm

is complete.

Table 7 sho ws the o utputs f o r To ggle Bit I o n Q6.

Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates

whether a par ticular sector is actively erasing (that is,

the A uto matic Erase algo rithm is in pro cess). To ggle Bit

II is valid after the rising edge of the final WE# or CE#,

whiche ver happens first, in the co mmand sequence.

Q2 to ggles when the system reads at addresses within

tho se sectors that hav e been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish when the sector is

actively erasing or is in Erase Suspend. Q6, by com-

parison, indicates when the device is actively erasing

but cannot distinguish which sectors are selected fo r era-

sure. Thus, bo th status bits are required fo r secto rs and

mode inf ormatio n. Refer to Table 7 to compare outputs

f o r Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whene v er the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a to ggle bit is toggling. Typically, the

system would no te and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

first. If the to ggle bit is no t toggling, the device has co m-

pleted the pro gram o r erase o peration. The system can

read arra y data o n Q7-Q0 on the fo llowing read cycle.

How ever, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section o n Q5). If it is, the system sho uld then

determine again whether the toggle bit is to ggling, since

the to ggle bit may have sto pped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully co mpleted the program o r erase opera-

tio n. If it is still to ggling, the device did not co mplete the

operation successfully, and the system must wr ite the

reset co mmand to return to reading array data.

The remaining scenario is that system initially determines

that the to ggle bit is toggling and Q5 has no t go ne high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively ,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gor ithm when it returns to deter mine the status of the

operation.

Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse co unt). Under these

co nditions Q5 will produce a "1". This time-out co ndition

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

the o nly operating functio ns of the device under this co n-

dition.

If this time-out co ndition o ccurs during secto r er ase op-

eratio n, it specifies that a particular secto r is bad and it

may no t be reused. Howe ver , other sectors are still func-

tio nal and ma y be used f o r the pro g ram o r erase o per a-

tion. The device must be reset to use other sectors.

Write the Reset co mmand sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If this time-out condition occurs during the chip erase

o peration, it specifies that the entire chip is bad o r co m-

binatio n o f sectors are bad.

If this time-o ut condition occurs during the word/byte pro-

gramming operation, it specifies that the entire sector

containing that byte is bad and this sector may not be

reused, (o ther secto rs are still functio nal and can be re-

used).

The time-out condition will not appear if a user tr ies to

program a non blank location without erasing. Please note

that this is no t a device failure co ndition since the device

was inco rrectly used.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

TABLE 7. WRITE OPERATION STATUS

Note:

1. Q7 and Q2 require a valid address when reading status inf ormation. Refer to the appropriate subsection fo r further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5 : Exceeded Timing Limits" fo r more info rmatio n.

Status Q7 Q6 Q5 Q3 Q2 RY/BY#

(Note1) (Note2)

In Progress Word/Byte Program in Auto Program Algorithm Q7# Toggle 0 N/A No 0

Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Exceeded Word/Byte Program in Auto Program Algorithm Q7# Toggle 1 N/A No 0

Time Toggle

Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND .

POWER-UP SEQUENCE

The MX26L V160AT/AB powers up in the Read only mode.

In addition, the memor y contents may only be altered

after successful co mpletion o f the predefined command

sequences.

TEMPORARY SECTOR UNPROTECT

This feature allows tempo rary unprotection of previo usly

pro tected secto r to change data in-system. The Tempo-

rary Sector Unprotect mode is activated by setting the

RESET# pin to VID (11.5V-12.5V). Dur ing this mode,

formerly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET# pin. All the previo usly protected sectors are pro-

tected again.

SECTOR PROTECTION

The MX29LV160A T/AB features hardware sector pro tec-

tion. This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and OE# (suggest VID = 12V). Program-

ming o f the protectio n circuitry begins on the falling edge

of the WE# pulse and is terminated on the rising edge.

Please refer to secto r pro tect algo rithm and wavefo rm.

To verify programming o f the pro tection circuitry , the pro-

gramming equipment must force VID on address pin A9

( with CE# and OE# at VIL and WE# at VIH). When

A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"

code at device output Q0 for a pro tected sector . Other-

wise the device will produce 00H fo r the unprotected sec-

to r. In this mode, the addresses, except fo r A1, are do n't

care. Address locations with A1 = VIL are reserved to

read manuf acturer and device co des. (Read Silico n ID)

It is also po ssible to determine if the secto r is pro tected

in the system by writing a Read Silicon ID command.

P erfo rming a read operatio n with A1=VIH, it will produce

a logical "1" at Q0 for the pro tected sector .

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-o ut is co mplete. Data# P o lling

and T o ggle Bit are valid after the initial secto r erase co m-

mand sequence.

If Data# Polling or the Toggle Bit indicates the device

has been written with a valid erase command, Q3 may

be used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operatio n is completed as indicated by Data# P olling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase co mmands. To insure the co m-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

DATA PROTECTION

The MX26LV160AT/AB is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transitio n. During power up the device auto matically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down tran-

sition or system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH o r WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

The system must write the reset command to exit the

"Silico n-ID Read Command" code.

CHIP UNPROTECT

The MX29LV160AT/AB also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in the

code. It is recommended to protect all sectors before

activating chip unprotect mode.

To activate this mode, the programming equipment must

force VID on control pin OE# and address pin A9. The

CE# pins must be set at VIL. Pins A6 must be set to VIH.

Refer to chip unprotect algorithm and waveform for the

chip unprotect algorithm. The unprotection mechanism

begins on the falling edge of the WE# pulse and is

terminated on the rising edge.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ABSOLUTE MAXIMUM RATINGS

Storage T emperature

Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC

Vo ltage with Respect to Gro und

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC v oltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During vo ltage transitio ns, input o r I/O pins may o ver-

sho ot to VCC +2.0 V f or perio ds up to 20 ns .

2. Minimum DC input vo ltage o n pins A9, OE#, and RE-

SET# is -0.5 V. During voltage transitions, A9, OE#,

and RESET# may overshoot VSS to -2.0 V for peri-

o ds o f up to 20 ns. Maximum DC input vo ltage on pin

A9 is +12 V which may o versho ot to 13.5V fo r periods

up to 20 ns.

3. No mo re than one o utput may be sho rted to gro und at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

OPERATING RATINGS

Commercial (C) Devices

Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C

VCC Supply Voltages

VCC for full voltage range. . . . . . . . . . . +3.0 V to 3.6 V

Operating ranges define tho se limits between which the

functio nality o f the de vice is guaranteed.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

CAPACITANCE TA = 25oC, f = 1.0 MHz

SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS

CIN1 Input Capacitance 8 pF VIN = 0V

CIN2 Control Pin Capacitance 1 2 pF VIN = 0V

COUT Output Capacitance 12 p F V OUT = 0V

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maxim um v alue, read operation canno t be guar anteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

MX26LV160AT/AB

Symbol PARAMETER MIN. TYP MAX. UNIT CONDITIONS

ILI Input Leakage Current ± 1± 3 uA VIN = VSS to VCC

ILIT A9 Input Leakage Current 3 5 200 uA VCC=VCC max;

A9=12V

ILO Output Leakage Current ± 1 u A V OUT = VSS to VCC,

VCC=VCC max

ICC1 VCC Active Read Current 20 3 0 mA CE#=VIL, @5MHz

8 14 mA OE#=VIH @1MHz

ICC2 VCC Active write Current 2 6 3 0 mA CE#=VIL, OE#=VIH

ICC3 VCC Standby Current 3 0 10 0 uA CE#; RESET#=VCC ± 0.3V

ICC4 VCC Standby Current 3 0 100 uA RESET#=VSS ± 0.3V

During Reset

VIL Input Low V o ltage (No te 1) -0.5 0.8 V

VIH Input High V o ltage 0.7xVCC VCC+0.3 V

VID Vo ltage f or Automatic Select 11 12 V VCC=3.3V

and T emporary Sector Unprotect

V OL Output Low V oltage 0.45 V IOL = 4.0mA,

VCC= VCC min

V OH1 Output High V oltage (TTL) 0.85xVCC IOH = -2mA,

VCC=VCC min

V OH2 Output High V o ltage VCC-0.4 IOH = -100uA, VCC min

(CMOS)

TABLE 8. DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 3.0V~3.6V

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

26LV160AT/AB-55 26LV160AT/AB-70

SYMBOLPARAMETER MIN. MAX. MIN. MAX. UNIT CONDITIONS

tRC Read Cycle Time (Note 1) 5 5 7 0 ns

tACC Address to Output Delay 5 5 7 0 ns CE#=OE#=VIL

tCE CE# to Output Delay 5 5 7 0 ns OE#=VIL

tOE OE# to Output Delay 2 5 30 ns CE#=VIL

tDF OE# High to Output Flo at (Note1) 0 2 5 0 2 5 ns CE#=VIL

tOEH Output Read 0 0 ns

Enable To ggle and 10 10 ns

Hold Time Data# Polling

tO H Address to Output ho ld 0 0 ns CE#=OE#=VIL

NOTE:

1. Not 100% tested.

2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

•Input pulse levels: 0V/3.0V.

•Input rise and fall times is equal to or less than 5ns.

•Output load: 1 TTL gate + 100pF (Including scope and

jig), for 26LV160AT/AB-70. 1 TTL gate + 30pF (Includ-

ing scope and jig) for 26LV160AT/AB-55.

•Reference levels for measuring timing: 1.5V.

AC CHARACTERISTICS TA = 0 oC to 70oC, VCC = 3.0V~3.6V

TABLE 9. READ OPERATIONS

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

TEST POINTS

3.0V

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

OUTPUT

INPUT

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

2.7K ohm +3.3V

CL= 100pF Including jig capacitance for MX26LV160T/B-70

(30pF for MX26LV160T/B-55)

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 1. READ TIMING WAVEFORMS

Addresses

CE#

OE#

tACC

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

HIGH Z HIGH Z

D ATA V alid

tOE

tOEH tDF

tCE

tACC

tRC

Outputs

RESET#

tOH

ADD V alid

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AC CHARACTERISTICS TA = 0 oC to 70oC, VCC = 3.0V~3.6V

TABLE 10. Erase/Program Operations

26LV160AT/AB-55 26LV160AT/AB-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT

tWC Write Cycle Time (Note 1) 5 5 7 0 ns

tAS Address Setup Time 0 0 ns

tAH Address Hold Time 4 5 45 ns

tDS Data Setup Time 3 5 3 5 ns

tDH Data Hold Time 0 0 ns

tOES Output Enable Setup Time 0 0 ns

tGHWL Read Recovery Time Before Write 0 0 ns

(OE# High to WE# Low)

tCS CE# Setup Time 0 0 ns

tCH CE# Hold Time 0 0 ns

tWP Write Pulse Width 3 5 3 5 ns

tWPH Write Pulse Width High 3 0 3 0 ns

tWHWH1 Programming Operation (Note 2) 55/70(TYP.) 55/70(TYP.) us

(Byte/Word program time)

tWHWH2 Sector Erase Operation (Note 2) 2.4(TYP.) 2.4(TYP.) sec

tVCS VCC Setup Time (Note 1) 5 0 5 0 us

tRB Recovery Time from RY/BY# 0 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay 9 0 9 0 ns

tWPP1 Write pulse width for sector 100ns 10us(typ.) 100ns 10us(typ.)

protect (A9, OE# Control)

tWPP2 Write pulse width for sector 100ns 12ms(typ.) 100ns 12ms(typ.)

unprotect (A9, OE# Control)

tVLHT Voltage transition time 4 4 us

tOESP OE# setup time to WE# active 4 4 us

tBAL Sector Address Load Time 50 50 us

NOTES:

1. Not 100% tested.

2. See the "Erase and Programming Performance" sectio n for mo re inf ormation.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

26LV160AT/AB-55 26LV160AT/AB-70

SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT

t WC Write Cycle Time (Note 1) 5 5 7 0 ns

tAS Address Setup Time 0 0 ns

tAH Address Hold Time 4 5 4 5 ns

tDS Data Setup Time 3 5 3 5 ns

tDH Data Ho ld Time 0 0 ns

tOES Output Enable Setup Time 0 0 ns

tGHEL Read Reco very Time Befo re Write 0 0 ns

tWS WE# Setup Time 0 0 ns

tWH WE# Hold Time 0 0 ns

tCP CE# Pulse Width 3 5 35 ns

tCPH CE# Pulse Width High 3 0 3 0 ns

tWHWH1 Programming Byte 55(Typ.) 55(Typ.) us

Operation(note2) Word 70(Typ.) 70(Typ.) us

tWHWH2 Sector Erase Operation (note2) 2.4(Typ.) 2.4(Typ.) sec

NOTE:

1. Not 100% tested.

2. See the "Erase and Programming Performance" sectio n for mo re inf ormation.

AC CHARACTERISTICS TA = 0 oC to 70oC, VCC = 3.0V~3.6V

TABLE 11. Alternate CE# Controlled Erase/Program Operations

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 2. COMMAND WRITE TIMING WAVEFORM

Addresses

CE#

OE#

WE#

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tWPH

tWP

tOES

tAS

VCC 3V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

AUTOMATIC PROGRAMMING TIMING WAVEFORM

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Ver ify in fast algorithm

and additional verification by external control are not re-

quired because these operations are executed automati-

cally by internal control circuit. Programming comple-

tion can be verified by DATA# polling and toggle bit check-

ing after auto matic programming starts. Device outputs

DATA# during programming and DATA# after pro gram-

ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#

polling, timing waveform)

tWC

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

PA PA

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS tDH

tWHWH1

Read Status Data (last two cycle)Program Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Verify Word Ok ?

YES

Auto Program Completed

Data Poll

from system

Increment

Address

Last Address ?

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM

tWC

tWH

tGHEL

tWHWH1 or 2

tCP

Address

WE#

OE#

CE#

Data DQ7

Data# Polling

DOUT

RESET#

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

tAH

tAS

PA for program

SA for sector erase

555 for chip erase

tRH

tDH

tDS

tWS

A0 for program

55 for erase

tCPH

tBUSY

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

All data in chip are erased. External erase verification is

not required because data is verified automatically by

internal control circuit. Erasure completion can be veri-

fied by D ATA# polling and toggle bit checking after auto-

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle

bit, D ATA# po lling, timing wa vef o rm)

FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM

AUTOMATIC CHIP ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh 555h

10h In

Progress Complete

VA VA

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

tAS

tAH

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

NO Data=FFh ?

Write Data 10H Address 555H

Write Data 55H Address 2AAH

Data Pall from System

Auto Chip Erase Completed

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A19 are erased. Exter nal

erase verify is not required because data are verified

auto matically by internal contro l circuit. Erasure co mple-

tio n can be verified by DATA# polling and to ggle bit check-

ing after automatic erase starts. Device outputs 0 dur-

ing erasure and 1 after erasure on Q7. (Q6 is f or to ggle

bit; see to ggle bit, DATA# po lling, timing wav efo rm)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tWC

Address

OE#

CE#

55h

2AAh Sector

Address 1

Sector

Address 0

30h In

Progress Complete

VA VA

30h

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Sector

Address n

tAS

tAH

tBAL

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

30h

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Data Poll from System

Auto Sector Erase Completed

Last Sector

to Erase

YES

Data=FFh

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 10. IN-SYSTEM SECT OR PR O TECT/CHIP UNPROTECT TIMING W AVEFORM (RESET# Con-

trol)

Sector Protect =150us

chip Unprotect =15ms

1us

VID

VIH

Data

SA, A6

A1, A0

CE#

WE#

OE#

Valid* Valid*

Status

Valid*

Sector Protect or Sector Unprotect

40h60h60h

Verify

RESET#

Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 11. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)

No tes: tVLHT (V o ltage transitio n time)=4us min.

tOESP (OE# setup time to WE# active)=4us min.

tOE

Data

OE#

WE#

12V

CE#

tOESP

tWPP 1

tVLHT

Verify

01H F0H

A19-A12 Sector Address

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 12. SECTOR PROTECTION ALGORITHM (A9, OE# Control)

START

Set Up Sector Addr

PLSCNT=1

Sector Protection

Complete

Data=01H?

Yes

OE#=VID, A9=VID, CE#=VIL

A6=VIL

Activate WE# Pulse

Time Out 150us

Set WE#=VIH, CE#=OE#=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1, A6=0, A0=0

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=32?

Yes

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 13. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID

START

PLSCNT=1

First Write

Cycle=60H

Yes

RESET#=VID

Wait 1us

Set up sector address

Write 60H to sector address

with A6=0, A1=1, A0=0

Verify sector protect :

write 90H with A6=0,

A1=1, A0=0

Wait 150us

Increment PLSCNT

Read from sector address

Remove VID from RESET#

Temporary Sector

Unprotect Mode

Reset PLSCNT=1

Data=01H

Yes

PLSCNT=25?

Protect another

sector?

Write reset command

Sector protect complete

Device failed

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 14. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID

START

PLSCNT=1

First Write

Cycle=60H ?

Yes

RESET#=VID

Wait 1us

Set up first sector address

Chip unprotect :

write 60H with

A6=1, A1=1, A0=0

Verify chip unprotect

write 90H to sector address

with A6=0, A1=1, A0=0

Wait 50ms

Increment PLSCNT

Read from sector address

with A6=0, A1=1, A0=0

Remove VID from RESET#

Temporary Sector

Unprotect Mode

Set up next sector address

All sector

protected?

Yes

Data=00H

Yes

No Protect all sectors

PLSCNT=1000?

Last sector

verified?

Write reset command

Chip unprotect complete

Device failed

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 15. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)

tOE

Data

OE#

WE#

12V

Vcc 3V

12V

Vcc 3V

CE#

tOESP

tWPP 2

tVLHT

Verify

00H

Sector Address

A19-A12

F0H

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 16. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

START

Protect All Sectors

PLSCNT=1

Chip Unprotect

Complete

Data=00H?

Yes

Set OE#=A9=VID, CE#=VIL,

A6=1, A1=1, A0=0

Activate WE# Pulse

Time Out 50ms

Set OE#=CE#=VIL, A9=VID,

A1=1, A0=0, A6=0

Set Up First Sector Addr

All sectors have

been verified?

Remove VID from A9

Write Reset Command

Device Failed

PLSCNT=1000?

Increment

PLSCNT

Read Data from Device

Yes

Increment

Sector Addr

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 17. DATA# POLLING ALGORITHM

Read Q7~Q0

Add.=VA(1)

Read Q7~Q0

Add.=VA

Start

Q7 = Data ?

Q5 = 1 ?

Q7 = Data ?

FAIL Pass

(2)

Yes

NOTE : 1.VA=Valid address for programming

2.Q7 should be re-checked even Q5="1" because Q7 may change

simultaneously with Q5.

WRITE OPERATION STATUS

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 18. TOGGLE BIT ALGORITHM

Read Q7-Q0

Q5= 1?

Read Q7~Q0 Twice

Program/Erase Operation

Not Complete,Write

Reset Command

Program/Erase

operation Complete

Toggle bit Q6=

Toggle?

Toggle Bit Q6 =

Toggle ? NO

(Note 1)

(Note 1,2)

YES

Note:1.Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 change to "1".

Start

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 19. Data# Polling Timings (During Automatic Algorithms)

RY/BY#

NOTES:

1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

2. CE# must be toggled when DATA# polling.

tDF

tCE

tACC

tRC

tCH

tOE

tOEH

tOH

tBUSY

Address

CE#

OE#

WE#

Q0-Q6

Status Data Status Data

Complement Complement Valid DataTrue

VAVAVA

High Z

Valid DataTrue

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 20. Toggle Bit Timings (During Automatic Algorithms)

NOTES:

1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

2. CE# must be toggled when toggle bit toggling.

tDF

tCE

tACC

tRC

tCH

tOE

tOEH

tBUSY

High Z

tOH

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

Valid Status

(first raed)

Valid Status

(second read) (stops toggling)

Valid Data

VA VA

Valid Data

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 21. RESET# TIMING WAVEFORM

TABLE 12. AC CHARACTERISTICS

Parameter Std Description T est Setup All Speed Options Unit

tREAD Y1 RESET# PIN Low (During Automatic Algorithms) MAX 2 0 us

to Read o r Write (See No te)

tREADY2 RESET# PIN Low (NOT During Auto matic MAX 500 ns

Algo rithms) to Read o r Write (See No te)

tRP RESET# Pulse Width (During Auto matic Algo rithms) MIN 5 00 ns

tRH RESET# High Time Befo re Read (See Note) MIN 5 0 ns

tRB R Y/BY# Recov ery Time (to CE#, OE# go lo w) MI N 0 n s

Note: Not 100% tested

tRH

tRB

tReady1

tRP

tReady2

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

RESET#

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from b yte

mode to word mode)

AC CHARACTERISTICS

TABLE 13. WORD/BYTE CONFIGURATION (BYTE#)

Parameter Description Speed Options Unit

JEDEC Std -55 -70

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 2 5 25 ns

tFHQV BYTE# Switching High to Output Active M i n 55 70 ns

tFHQV

tELFH

DOUT

(Q0-Q7) DOUT

(Q0-Q14)

VA DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 23. BYTE# TIMING WA VEFORM FOR READ OPERATIONS (BYTE# switching from wor d

mode to byte mode)

FIGURE 24. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS

tFLQZ

tELFH

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

tAS tAH

The falling edge of the last WE# signal

CE#

WE#

BYTE#

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Table 14. TEMPORARY SECTOR UNPROTECT

Parameter Std. Description T est Setup All Speed Options Unit

tVIDR VID Rise and F all Time (See No te) Min 50 0 ns

tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us

Note:

No t 100% tested

Figure 25. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

RESET#

CE#

WE#

RY/BY#

tVIDR tVIDR

Program or Erase Command Sequence

12V

0 or Vcc 0 or Vcc

tRSP

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Figure 26. TEMPORARY SECTOR UNPROTECT ALGORITHM

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Operation Completed

2. All previously protected sectors are protected again.

Note : 1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

FIGURE 27. ID CODE READ TIMING WAVEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H/00C2H C4H/49H (Byte)

22C4H/2249H (Word)

VID

VIH

VIL

ADD

A2-A8

A10-A19

CE#

OE#

WE#

ADD

DATA OUT

DATA

Q0-Q15

VCC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX26LV160AT/AB is capable of operating in the CFI

mode. This mode all the host system to deter mine the

manufacturer of the device such as operating param-

eters and co nfigur atio n. Two commands are required in

CFI mo de. Query co mmand o f CFI mo de is placed first,

then the Reset command exits CFI mode. These are

described in Table 15.

The single cycle Query co mmand is valid o nly when the

device is in the Read mode, Standby mode, and Auto-

matic Select mo de; ho wev er , it is igno red o therwise .

The Reset command exits from the CFI mode to the

Read mo de, o r Auto matic Select mode. The command is

v alid only when the device is in the CFI mode.

Table 15-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query-unique ASCII string "QRY" 2 0 1 0 0051

22 11 0052

24 12 0059

Primary vendor command set and control interface ID code 2 6 1 3 0002

28 14 0000

Address for primary algorithm extended query table 2A 1 5 0040

2C 16 0000

Alternate vendor command set and control interface ID code (none) 2E 1 7 0000

30 18 0000

Address for secondary algorithm extended query table (none) 32 1 9 0000

34 1A 0000

Table 15-2. CFI Mode: System Interface Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

VCC supply, minimum (3.0V) 3 6 1B 0030

VCC supply, maximum (3.6V) 3 8 1 C 0036

VPP supply, minimum (none) 3A 1 D 0000

VPP supply, maximum (none) 3 C 1E 0000

Typical timeout for single word/byte write (2N us) 3E 1F 0004

Typical timeout for Minimum size buffer write (2N us) (not supported) 4 0 2 0 0000

Typical timeout for individual sector erase (2N ms) 4 2 2 1 000A

Typical timeout for full chip erase (2N ms) 4 4 22 0000

Maximum timeout for single word/byte write times (2N X Typ) 4 6 23 0005

Maximum timeout for buffer write times (2N X Typ) 48 2 4 0000

Maximum timeout for individual sector erase times (2N X Typ) 4 A 25 0004

Maximum timeout for full chip erase times (not supported) 4C 2 6 0000

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

Table 15-3. CFI Mode: Device Geometry Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Device size (2N bytes) 4E 27 0015

Flash device interface code (x8/x16 async.) 50 2 8 0002

52 29 0000

Maximum number of bytes in multi-byte write (not supported) 5 4 2A 0000

56 2B 0000

Number of erase sector regions 5 8 2C 0004

Erase sector region 1 information (refer to the CFI publication 100) 5A 2 D 0000

5C 2E 0000

5E 2F 0040

60 30 0000

Erase sector region 2 information 6 2 31 0001

64 32 0000

66 33 0020

68 34 0000

Erase sector region 3 information 6A 35 0000

6C 36 0000

6E 37 0080

70 38 0000

Erase sector region 4 information 7 2 39 001E

74 3A 0000

76 3B 0000

78 3C 0001

Table 15-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

(All values in these tables are in hexadecimal)

Description Address Address Data

(Byte Mode) (Word Mode)

Query-unique ASCII string "PRI" 8 0 4 0 0050

82 41 0052

84 42 0049

Major version number, ASCII 8 6 43 0031

Minor version number, ASCII 8 8 44 0030

Address sensitive unlock (0=required, 1= not required) 8A 45 0000

Erase suspend (0=not supported) 8C 46 0000

Sector protect (0=not supported) 8E 47 0000

Temporary sector unprotect (0=not supported) 90 48 0000

Sector protect/chip unprotect scheme (0=not supported) 92 49 0004

Simultaneous R/W operation (0=not supported) 94 4A 0000

Burst mode type (0=not supported) 9 6 4B 0000

Page mode type (0=not supported) 98 4C 0000

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

LIMITS

PARAMETER MIN. TYP. (2) MAX. (3) UNITS

Sector Erase Time 2. 4 1 5 sec

Chip Erase Time 8 0 320 sec

Byte Programming Time 5 5 220 us

Word Programming Time 7 0 280 us

Chip Programming Time (Word/Byte Mode) 7 0 140 sec

Erase/Program Cycles 2K (6) Cycles

TABLE 17. LATCH-UP CHARACTERISTICS

TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1)

Note:

1. Not 100% tested.

2. Typical pro gram and er ase times assume the fo llo wing co nditio ns : 25°C , 3.3V VCC . Pro g ramming spec. assume

that all bits are pro grammed to checkerbo ard pattern.

3. Maximum values are measured at VCC=3.0V, worst case temperature. Maximum values are up to including 2K

program/erase cycles.

4. System-level overhead is the time required to execute the command sequences for the all program command.

5. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits

are programmed to 00H befo re erasure)

6. Min. erase/program cycles is under : 3.3V VCC, 25°C, checkerbo ard pattern conditio ns, and without baking pro cess.

MIN. MAX.

Input Voltage with respect to GND on ACC, OE#, RESET#, A9 -1.0V 12V

Input Voltage with respect to GND on all power pins, Address pins, CE# and WE# -1.0V VCC + 1.0V

Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V

Current -100mA +100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

ORDERING INFORMATION

P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

MX26LV160ATMC-55 5 5 3 0 1 0 0 44 Pin SOP

MX26LV160ATMC-70 7 0 3 0 1 0 0 44 Pin SOP

MX26LV160ABMC-55 5 5 30 1 0 0 44 Pin SOP

MX26LV160ABMC-70 7 0 30 1 0 0 44 Pin SOP

MX26LV160ATTC-55 55 3 0 10 0 48 Pin TSOP

(Normal Type)

MX26LV160ABTC-55 5 5 30 1 00 48 Pin TSOP

(Normal Type)

MX26LV160ATTC-70 70 3 0 10 0 48 Pin TSOP

(Normal Type)

MX26LV160ABTC-70 7 0 30 1 00 48 Pin TSOP

(Normal Type)

MX26LV160ATXBC-55 55 30 1 00 48 Ball CSP

(Ball size:0.3mm)

MX26LV160ABXBC-55 5 5 3 0 1 00 48 Ball CSP

(Ball size:0.3mm)

MX26LV160ATXBC-70 70 30 1 00 48 Ball CSP

(Ball size:0.3mm)

MX26LV160ABXBC-70 7 0 3 0 1 00 48 Ball CSP

(Ball size:0.3mm)

MX26LV160ATXEC-55 55 30 1 00 48 Ball CSP

(Ball size:0.4mm)

MX26LV160ABXEC-55 5 5 3 0 1 00 48 Ball CSP

(Ball size:0.4mm)

MX26LV160ATXEC-70 70 30 1 00 48 Ball CSP

(Ball size:0.4mm)

MX26LV160ABXEC-70 7 0 3 0 1 00 48 Ball CSP

(Ball size:0.4mm)

MX26LV160ATMC-55G 5 5 30 1 0 0 44 Pin SOP Pb-free

MX26LV160ATMC-70G 7 0 30 1 0 0 44 Pin SOP Pb-free

MX26LV160ABMC-55G 5 5 30 100 44 Pin SOP Pb-free

MX26LV160ABMC-70G 7 0 30 100 44 Pin SOP Pb-free

MX26LV160ATTC-55G 5 5 30 10 0 48 Pin TSOP Pb-free

(Normal Type)

MX26LV160ABTC-55G 5 5 30 10 0 48 Pin TSOP Pb-free

(Normal Type)

MX26LV160ATTC-70G 7 0 30 10 0 48 Pin TSOP Pb-free

(Normal Type)

MX26LV160ABTC-70G 7 0 30 10 0 48 Pin TSOP Pb-free

(Normal Type)

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

P ART NO. ACCESS OPERA TING STANDBY PACKA GE Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

MX26LV160ATXBC-55G 55 30 10 0 48 Ball CSP Pb-free

(Ball size:0.3mm)

MX26LV160ABXBC-55G 55 30 100 48 Ball CSP Pb-free

(Ball size:0.3mm)

MX26LV160ATXBC-70G 70 30 10 0 48 Ball CSP Pb-free

(Ball size:0.3mm)

MX26LV160ABXBC-70G 70 30 100 48 Ball CSP Pb-free

(Ball size:0.3mm)

MX26LV160ATXEC-55G 55 30 10 0 48 Ball CSP Pb-free

(Ball size:0.4mm)

MX26LV160ABXEC-55G 55 30 100 48 Ball CSP Pb-free

(Ball size:0.4mm)

MX26LV160ATXEC-70G 70 30 10 0 48 Ball CSP Pb-free

(Ball size:0.4mm)

MX26LV160ABXEC-70G 70 30 100 48 Ball CSP Pb-free

(Ball size:0.4mm)

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

PACKAGE INFORMATION

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

48-Ball CSP (for MX26LV160ATXBC/ATXBI/ABXBC/ABXBI)

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

48-Ball CSP (for MX26LV160ATXEC/ATXEI/ABXEC/ABXEI)

P/N:PM1123

MX26LV160AT/AB

REV. 1.1, NOV. 18, 2004

REVISION HISTORY

Revision No. Description Page Date

1.0 1. Removed "Preliminary" P1 NOV/15/2004

2. To added 44-SOP package information All

3. To modified cycling time from 10K to 2K P1 , 53

1. 1 1. To corrected protect/unprotect information in CFI table P5 2 NOV/18/2004

MX26LV160AT/AB

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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.