M3062BFCVGP - Renesas Technology / Hitachi Semiconductor

M16C/62 Group (M16C/62P, M16C/62PT)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0210Z

Rev.2.10

Nov. 07, 2003

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1. Overview

The M16C/62 group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high-per-

formance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin,

100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated

instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca-

pable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and

DMAC which combined with fast instruction processing capability, makes it suitable for control of various

OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.

1.1 Applications

Audio, cameras, office/communications/portable/industrial equipment, automobile, etc

Specifications written in this manual are believed to be accurate, but are

not guaranteed to be entirely free of error. Specifications in this manual

may be changed for functional or performance improvements. Please make

sure your manual is the latest edition.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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1.2 Performance Outline

Table 1.1 to table 1.3 list performance outline of M16C/62 group (M16C/62P, M16C/62PT).

Table 1.1 Performance outline of M16C/62 group (M16C/62P) (128-pin version)

Item Performance

M16C/62P

Number of basic instructions 91 instructions

Shortest instruction execution time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation mode Single-chip, memory expansion and microprocessor mode

Memory space 1 Mbyte (Available to 4M bytes by memory space

expansion function)

Memory capacity See table 1.4 and 1.5 Product List

Port Input/Output : 113 pins, Input : 1 pin

Multifunction timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART,

I2C bus (1), IEBus (2)

2 channels

Clock synchronous

A-D converter 10-bit A-D converter: 1 circuit, 26 channels

D-A converter 8 bits x 2 channels

DMAC 2 channels

CRC calculation circuit CCITT-CRC

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock generating circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

Ring oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation stop detection function Stop detection of main clock oscillation, re-oscillation detection

function

Voltage detection circuit Available (option (4))

Supply voltage VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)

Power consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)

1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)

0.7 µA (VCC1=VCC2=3V, stop mode)

Program/erase supply voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V

Program and erase endurance 100 times (all area)

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) (3)

Operating ambient temperature –20 to 85oC

–40 to 85oC (3)

Package 128-pin plastic mold QFP

CPU

Peripheral

function

Electric

characteris-

tics

Flash memory

Version

NOTES:

1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.

4. All options are on request basis.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Table 1.2 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (100-pin version)

Item Performance

M16C/62P M16C/62PT(Note 4)

Number of basic instructions 91 instructions

Shortest instruction execution time

41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)

41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation mode

Single-chip, memory expansion and

Single-chip mode

microprocessor mode

Memory space 1 Mbyte (Available to 4 Mbytes by 1M byte

memory space expansion function)

Memory capacity See table 1.4 to 1.7 Product List

Port Input/Output : 87 pins, Input : 1pin

Multifunction timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit

Serial I/O 3 channels

Clock synchronous, UART,

I2C bus (1), IEBus (2)

2 channels

Clock synchronous

A-D converter 10-bit A-D converter: 1 circuit, 26 channels

D-A converter 8 bits x 2 channels

DMAC 2 channels

CRC calculation circuit CCITT-CRC

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock generating circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

Ring oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation stop detection function

Stop detection of main clock oscillation, re-oscillation detection function

Voltage detection circuit Available (option (5)) Absent

Supply voltage

VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1

VCC1=VCC2=4.0V to 5.5 V

(f(BCLK)=24MHz) (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, V

CC2

=2.7V to VCC1

(f(BCLK)=10MHz)

Power consumption

14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=VCC2=5V,

1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)

f(XCIN)=32kHz, wait mode) 0.8 µA (VCC1=VCC2=5V, stop mode)

0.7 µA (VCC1=VCC2=3V, stop mode)

Program/erase supply voltage

3.3 ± 0.3 V or 5.0 ± 0.5 V

5.0 ± 0.5 V

Program and erase endurance

100 times (all area)

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) (3)

Operating ambient temperature –20 to 85oC T version : –40 to 85oC

–40 to 85oC (3) V version : –40 to 125oC

Package 100-pin plastic mold QFP, LQFP

CPU

Peripheral

function

Electric

characteris-

tics

Flash memory

Version

NOTES:

1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.

4. Use the high reliability version on VCC1 = VCC2.

5. All options are on request basis.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Table 1.3 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (80-pin version)

Item Performance

M16C/62P M16C/62PT

Number of basic instructions 91 instructions

Shortest instruction execution time

41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation mode Single-chip mode

Memory space 1M byte

Memory capacity See table 1.4 to 1.7 Product List

Port Input/Output : 70 pins, Input : 1pin

Multifunction timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer)

Timer B : 16 bits x 6 channels (Timer B1 is internal timer)

Serial I/O 2 channels

Clock synchronous, UART,

I2C bus(1), IEBus(2)

1 channel

Clock synchronous,

I2C bus(1), IEBus(2)

2 channels

Clock synchronous (1 channel is only for transmission)

A-D converter 10-bit A-D converter: 1 circuit, 26 channels

D-A converter 8 bits x 2 channels

DMAC 2 channels

CRC calculation circuit CCITT-CRC

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources,

Priority level: 7 levels

Clock generating circuit 4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

Ring oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation stop detection function

Stop detection of main clock oscillation, re-oscillation detection function

Voltage detection circuit Available (option (4)) Absent

Supply voltage

VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, (f(BCLK)=10MHz)

Power consumption

14 mA (VCC1=5V, f(BCLK)=24MHz)

8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=5V,

1.8 µA (VCC1=3V,

f(XCIN)=32kHz, wait mode)

f(XCIN)=32kHz, wait mode) 0.8 µA (VCC1=5V, stop mode)

0.7 µA (VCC1=3V, stop mode)

Program/erase supply voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V

Program and erase endurance

100 times (all area)

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) (3)

Operating ambient temperature –20 to 85oC T version : –40 to 85oC

–40 to 85oC(option) V version : –40 to 125oC

Package 80-pin plastic mold QFP

CPU

Peripheral

function

Electric

characteris-

tics

Flash

memory

Version

NOTES :

1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule.

4. All options are on request basis.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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1.3 Block Diagram

Figure 1.1 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 128-pin and 100-pin version,

figure 1.2 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 80-pin version.

Figure 1.1 M16C/62 Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram

AAAAA

A

AAA

A

AAAAA

Output (timer A): 5

Input (timer B): 6

Internal peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

D-A converter

(8 bits X 2 channels)

Memory

ROM (1)

RAM (2)

A-D converter

(10 bits

X

8 channels

Expandable up to 26 channels)

UART or

clock synchronous serial I/O

(8 bits

X

3 channels)

System clock

generation circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

Ring oscillator

M16C/60 series16-bit CPU core

Port P0

8

Port P1

8

Port P2

8 8 8 8

Port P6

8

R0LR0H

R1H R1L

R2

R3

A0

A1

FB

SB

ISP

USP

INTB

CRC arithmetic circuit (CCITT )

(Polynomial : X16+X12+X5+1)

Multiplier

788

Port P10

Port P9

Port P8_5

Port P8

Port P7

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. Ports P11 to P14 exist only in 128-pin version.

4. Use M16C/62PT on VCC1= VCC2.

Port P5

Port P4Port P3

Clock synchronous serial I/O

(8 bits

X

2 channels)

PC

FLG

Timer (16-bit)

Three-phase motor

control circuit

8 8 82

Port P11 Port P12

Port P14 Port P13

(3)

(4)

(4)

(4)

(4)

(4)

(3) (3) (3)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Figure 1.2 M16C/62 Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram

Timer (16-bit)

Output (timer A): 5

Input (timer B): 6

Internal peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

D-A converter

(8 bits X 2 channels)

A-D converter

(10 bits

X

8 channels

Expandable up to 26 channels)

UART or

clock synchronous serial I/O (2 channels)

UART (1 channel)

System clock

generation circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

Ring oscillator

M16C/60 series16-bit CPU core

Port P0

8

Port P2

8

Port P3

8

Port P4

4

Port P5

8

Port P6

8

CRC arithmetic circuit (CCITT )

(Polynomial : X16+X12+X5+1)

Memory

4778

Port P10

Port P9

Port P8

Port P7 Port P8_5

ROM (1)

RAM (2)

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).

4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.

Clock synchronous serial I/O

(8 bits

X

2 channels)

R0LR0H

R1H R1L

R2

R3

SB

FLG

USP

ISP

INTB

PC

Multiplier

Three-phase motor

control circuit

A0

A1

FB

(4)

(3)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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1.4 Product List

Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages,

table 1.8 lists the product code of flash memory version and external ROM version for M16C/62P. Fig-

ure 1.4 shows the marking diagram of flash memory version and external ROM version for M16C/62P.

Please specify the mark of the mask ROM version at the time of ROM order.

Please ask separately marking of the flash memory version of M16C/62PT.

4K bytes

64K bytes

M30622M8P-XXXFP

4K bytes

48K bytes

M30622M6P-XXXFP 100P6Q-A

M30622M8P-XXXGP

M30622M6P-XXXGP

RAM capacity

ROM capacity Package type RemarksType No. As of Nov. 2003

100P6S-A

MASK ROM version

(D): Under development

(P): Under planning

100P6Q-A

100P6S-A

(D)

5K bytes

96K bytes

M30622MAP-XXXFP

M30622MAP-XXXGP 100P6Q-A

100P6S-A

80P6S-A

M30623M6P-XXXGP

M30623M8P-XXXGP 80P6S-A

M30623MAP-XXXGP 80P6S-A

12K bytes

192K bytes

M30622MEP-XXXFP

10K bytes

128K bytes

M30620MCP-XXXFP

M30622MEP-XXXGP

M30620MCP-XXXGP 100P6Q-A

100P6S-A

100P6Q-A

100P6S-A

M30623MEP-XXXGP 128P6Q-A

M30624MGP-XXXFP 100P6S-A

20K bytes

M30624MGP-XXXGP 100P6Q-A

M30625MGP-XXXGP 128P6Q-A

M30622MGP-XXXFP 100P6S-A

12K bytes

256K bytes

M30622MGP-XXXGP 100P6Q-A

128P6Q-A

M30623MGP-XXXGP

M30626MWP-XXXFP 100P6S-A

31K bytes

M30626MWP-XXXGP 100P6Q-A

128P6Q-A

M30627MWP-XXXGP

M30624MWP-XXXFP 100P6S-A

100P6Q-A

24K bytes

320K bytes

M30624MWP-XXXGP

128P6Q-A

M30625MWP-XXXGP

M30622MWP-XXXFP 100P6S-A

16K bytes

M30622MWP-XXXGP 100P6Q-A

M30626MHP-XXXFP 100P6S-A

31K bytes

M30626MHP-XXXGP 100P6Q-A

128P6Q-A

M30623MWP-XXXGP

128P6Q-A

M30627MHP-XXXGP

100P6S-A

M30624MHP-XXXFP 100P6Q-A

24K bytes

384K bytes

M30624MHP-XXXGP

128P6Q-A

M30625MHP-XXXGP

M30622MHP-XXXFP 100P6S-A

16K bytes

M30622MHP-XXXGP 100P6Q-A

128P6Q-A

M30623MHP-XXXGP

(D)

M30621MCP-XXXGP 80P6S-A

(D)

Table 1.4 Product List (1) (M16C/62P)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Table 1.5 Product List (2) (M16C/62P)

M30625FGPGP

ROM capacity

ROM capacity Package type RemarksType No. As of Nov. 2003

128P6Q-A Flash memory version

(D): Under development

(P): Under planning

100P6S-A

4K bytes

64K+4K bytes

M30622F8PFP

M30622F8PGP 100P6Q-A

10K bytes128K+4K bytes

M30620FCPFP 100P6S-A

100P6Q-A

M30620FCPGP

20K bytes

256K+4K bytes

M30624FGPGP

100P6S-A

M30624FGPFP

M30626FHPFP

128P6Q-A

100P6S-A

100P6Q-A31K bytes384K+4K bytes

M30626FHPGP

M30627FHPGP

100P6Q-A

M30623F8PGP 80P6S-A

80P6S-A

M30621FCPGP (D)

M30626FJPFP 100P6Q-A

100P6S-A

31K bytes512K+4K bytes

M30626FJPGP (P)

(P)

External ROM version

10K bytes

M30620SPFP 100P6S-A(D)

M30620SPGP 100P6Q-A(D)

4K bytes

M30622SPFP 100P6S-A(D)

M30622SPGP 100P6Q-A(D)

M30627FJPGP 128P6Q-A(P)

MASK ROM version

M30627MJP-XXXGP

M30626MJP-XXXFP

100P6Q-A

100P6S-A

31K bytes

512K bytes

M30626MJP-XXXGP 128P6Q-A

(P)

(D)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Table 1.6 Product List (3) (T version (M16C/62PT))

100P6S-A

4K bytes64K bytes

M3062CM8T-XXXFP

M3062CM8T-XXXGP 100P6Q-A

100P6S-A

5K bytes96K bytes

M3062CMAT-XXXFP

M3062CMAT-XXXGP 100P6Q-A

100P6S-A

10K bytes128K bytes

M3062AMCT-XXXFP

M3062AMCT-XXXGP 100P6Q-A

M3062EMAT-XXXGP 80P6S-A

M3062EM8T-XXXGP 80P6S-A

M3062BMCT-XXXGP 80P6S-A

MASK ROM

version

100P6S-A

M3062AFCTFP

M3062AFCTGP 100P6Q-A

100P6S-A

31K bytes384K+4K bytes

M3062JFHTFP

M3062JFHTGP 100P6Q-A

10K bytes

128K+4K bytes

M3062BFCTGP 80P6S-A Flash memory

version

T Version

(High reliability

85 °C Version)

RAM capacity

ROM capacity Package type RemarksType No.

As of Nov. 2003

(D): Under development

(P): Under planning

(P)

(D)

(P)

(D)

(P)

(D)

(P)

(D)

M3062CM6T-XXXGP

M3062EM6T-XXXGP

M3062CM6T-XXXFP (D)

(D)

(P)

100P6S-A

4K bytes48K bytes 100P6Q-A

80P6S-A

M3062CF8TGP 100P6Q-A4K bytes64K bytes(D)

Table 1.7 Product List (4) (V version (M16C/62PT))

RAM capacityROM capacity Package type RemarksType No. As of Nov. 2003

100P6S-A

M3062CM8V-XXXFP

4K bytes64K bytes

M3062CM8V-XXXGP 100P6Q-A

100P6S-A

M3062CMAV-XXXFP

5K bytes96K bytes

M3062CMAV-XXXGP 100P6Q-A

100P6S-A

M3062AMCV-XXXFP

10K bytes128K bytes

M3062AMCV-XXXGP 100P6Q-A

M3062EMAV-XXXGP 80P6S-A

M3062EM8V-XXXGP 80P6S-A

M3062BMCV-XXXGP 80P6S-A

MASK ROM

version

100P6S-A

M3062AFCVFP

M3062AFCVGP 100P6Q-A10K bytes128K+4K bytes

M3062BFCVGP 80P6S-A Flash memory

version

(P)

(D)

100P6S-A

M3062JFHVFP

M3062JFHVGP 100P6Q-A

31K bytes384K+4K bytes

(P)

(D): Under development

(P): Under planning

100P6S-A

M3062CM6V-XXXFP

4K bytes48K bytes

M3062CM6V-XXXGP 100P6Q-A

M3062EM6V-XXXGP 80P6S-A

(P)

V Version

(High reliability

125 °C Version)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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Figure 1.3 Type No., Memory Size, and Package

Package type:

FP : Package 100P6S-A

GP : Package 80P6Q-A, 100P6Q-A, 128P6Q-A

ROM No.

Omitted for flash memory version and

external ROM version

Memory type:

M: Mask ROM version

F: Flash memory version

S: External ROM version

Type No. M 3 0 6 2 6 M H P – X X X F P

M16C/62 Group

M16C Family

Shows RAM capacity, pin count, etc

Numeric : M16C/62P

Alphabet : M16C/62PT

ROM capacity:

6: 48K bytes

8: 64K bytes

A: 96K bytes

C: 128K bytes

E: 192K bytes

G: 256K bytes

W: 320K bytes

H: 384K bytes

J: 512K bytes

Classification

P : M16C/62P

T : T version (M16C/62PT)

V : V version (M16C/62PT)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

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product

code Package

Internal ROM

(user ROM area without block 1)

Program and

erase endurance Temperature

range

Internal ROM

(block A, block 1) Operating ambient

temperature

Temperature

range

Lead-free

Lead-included

D3

D5

D7

D9

U3

U5

U7

U9

100

1,000

100

1,000

0°C to 60°C

100

10,000

100

10,000

0°C to 60°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

Lead-free

D3

D5

U3

U5

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

Lead-included

Flash

memory

version

External

ROM

version

Program and

erase endurance

Table 1.8 Product Code of Flash Memory version and External ROM version for M16C/62P

M16C

M30626FHPFP

BD5

XXXXXXX

Type No. (See Figure 1.3 Type No., Memory Size, and Package)

Chip version and product code.

B : Shows chip version.

Henceforth, whenever it changes a version, it continues with B, C, and D.

D5 : Shows Product code. (See table 1.8 Product Code.)

Data code seven digits

The product without marking of chip version of the flash memory version and the ROM external version

corresponds to the chip version “A”.

Figure 1.4

Marking Diagram of Flash Memory version and External ROM version for M16C/62P (Top View)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 12

1.5 Pin Configuration

Figures 1.5 to 1.8 show the pin configurations (top view).

Package: 128P6Q-A

Figure 1.5 Pin Configuration (Top View)

PIN CONFIGURATION (top view)

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

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101102

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P0_0/AN0_0/D0

P0_1/AN0_1/D1

P0_2/AN0_2/D2

P0_3/AN0_3/D3

P0_4/AN0_4/D4

P0_5/AN0_5/D5

P0_6/AN0_6/D6

P0_7/AN0_7/D7

P1_0/D8

P1_1/D9

P1_2/D10

AVSS

VCC1

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE

P7_4/TA2OUT/W

P7_6/TA3OUT

P5_6/ALE

P7_7/TA3IN

P5_5/HOLD

P5_4/HLDA

P5_3/BCLK

P5_2/RD

P5_7/RDY/CLKOUT

P4_7/CS3

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CLK4

P9_6/ANEX1/SOUT4

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P8_0/TA4OUT/U

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P8_2/INT0

P8_3/INT1

P8_5/NMI

P4_5/CS1

P4_6/CS2

P4_4/CS0

P5_0/WRL/WR

P5_1/WRH/BHE

P9_0/TB0IN/CLK3

P7_2/CLK2/TA1OUT/V

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P7_0/TXD2/SDA2/TA0OUT

(1)

P8_4/INT2/ZP

P8_1/TA4IN/U

P7_3/CTS2/RTS2/TA1IN/V

P7_5/TA2IN/W

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

VREF

AVCC

P9_7/ADTRG/SIN4

P14_1

P14_0

P13_7

P13_6

P13_5

P13_4

P1_3/D11

P1_4/D12

P2_0/AN2_0/A0(/D0/-)

P2_1/AN2_1/A1(/D1/D0)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

P3_0/A8(/-/D7)

P3_1/A9

P3_2/A10

P3_3/A11

P3_4/A12

P3_5/A13

P3_6/A14

P3_7/A15

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

VCC2

VSS

P1_5/D13/INT3

P1_6/D14/INT4

P1_7/D15/INT5

P12_4

P12_3

P11_3

P11_2

P11_1

P11_0

VCC1

VSS

P13_0

P13_1

P13_2

P13_3

P12_5

P12_6

P12_7

P11_4

P11_5

P11_6

P11_7

P12_2

P12_1

P12_0

M16C/62 Group (M16C/62P)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 13

Figure 1.6 Pin Configuration (Top View)

Package: 100P6S-A

PIN CONFIGURATION (top view)

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50

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97

98

99

100

P0_0/AN0_0/D0

P0_1/AN0_1/D1

P0_2/AN0_2/D2

P0_3/AN0_3/D3

P0_4/AN0_4/D4

P0_5/AN0_5/D5

P0_6/AN0_6/D6

P0_7/AN0_7/D7

P1_0/D8

P1_1/D9

P1_2/D10

P1_3/D11

P1_4/D12

VREF

AVSS

VCC1

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE P2_0/AN2_0/A0(/D0/-)

P2_1/AN2_1/A1(/D1/D0)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

P3_0/A8(/-/D7)

P3_1/A9

P3_2/A10

P3_3/A11

P3_4/A12

P3_5/A13

P3_6/A14

P3_7/A15

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

P7_4/TA2OUT/W

P7_6/TA3OUT

P5_6/ALE

P7_7/TA3IN

P5_5/HOLD

P5_4/HLDA

P5_3/BCLK

P5_2/RD

VCC2

VSS

P5_7/RDY/CLKOUT

P4_5/CS1

P4_6/CS2

P4_7/CS3

AVCC

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CLK4

P9_6/ANEX1/SOUT4

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P8_0/TA4OUT/U

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P7_2/CLK2/TA1OUT/V

P8_2/INT0

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P8_3/INT1

P8_5/NMI

P9_7/ADTRG/SIN4

P4_4/CS0

P5_0/WRL/WR

P5_1/WRH/BHE

P9_0/TB0IN/CLK3

P7_0/TXD2/SDA2/TA0OUT

(1)

P8_4/INT2/ZP

P8_1/TA4IN/U

P7_3/CTS2/RTS2/TA1IN/V

P7_5/TA2IN/W

P1_5/D13/INT3

P1_6/D14/INT4

P1_7/D15/INT5

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

M16C/62 Group

(

M16C/62P, M16C/62PT

)

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 14

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100

P0_0/AN0_0/D0

P0_1/AN0_1/D1

P0_2/AN0_2/D2

P0_3/AN0_3/D3

P0_4/AN0_4/D4

P0_5/AN0_5/D5

P0_6/AN0_6/D6

P0_7/AN0_7/D7

P1_0/D8

P1_1/D9

P1_2/D10

P1_3/D11

P1_4/D12

VREF

AVSS

VCC1

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE P2_0/AN2_0/A0(/D0/-)

P2_1/AN2_1/A1(/D1/D0)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

P3_0/A8(/-/D7)

P3_1/A9

P3_2/A10

P3_3/A11

P3_4/A12

P3_5/A13

P3_6/A14

P3_7/A15

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

P7_4/TA2OUT/W

P7_6/TA3OUT

P5_6/ALE

P7_7/TA3IN

P5_5/HOLD

P5_4/HLDA

P5_3/BCLK

P5_2/RD

VCC2

VSS

P5_7/RDY/CLKOUT

P4_5/CS1

P4_6/CS2

P4_7/CS3

AVCC

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CLK4

P9_6/ANEX1/SOUT4

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P8_0/TA4OUT/U

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P8_2/INT0

P8_3/INT1

P8_5/NMI

P9_7/ADTRG/SIN4

P4_4/CS0

P5_0/WRL/WR

P5_1/WRH/BHE

P9_0/TB0IN/CLK3

P8_4/INT2/ZP

P7_2/CLK2/TA1OUT/V

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P7_0/TXD2/SDA2/TA0OUT

(1)

P7_5/TA2IN/W

P7_3/CTS2/RTS2/TA1IN/V

P1_5/D13/INT3

P1_6/D14/INT4

P1_7/D15/INT5

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P8_1/TA4IN/U

Figure 1.7 Pin Configuration (Top View)

Package: 100P6Q-A

PIN CONFIGURATION (top view)

M16C/62 Group

(

M16C/62P, M16C/62PT

)

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 15

Figure 1.8 Pin Configuration (Top View)

Package: 80P6S-A

PIN CONFIGURATION (top view)

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56

P4_2

P4_3

P5_6

P5_5

P5_4

P5_3

P5_2

P5_7/CLKOUT

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P5_0

P5_1

P7_0/TXD2/SDA2/TA0OUT

(1)

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

P4_0

P4_1

VCC1

XIN

XOUT

VSS

RESET

CNVSS(BYTE)

P8_7/XCIN

P8_6/XCOUT

P7_6/TA3OUT

P7_7/TA3IN

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CLK4

P8_2/INT0

P8_3/INT1

P8_1/TA4IN

P8_4/INT2/ZP

P8_0/TA4OUT

P8_5/NMI

P0_0/AN0_0

P0_1/AN0_1

P0_2/AN0_2

P0_3/AN0_3

P0_4/AN0_4

P0_5/AN0_5

P0_6/AN0_6

P0_7/AN0_7

VREF

AVSS

AVCC

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P10_4/AN4/KI0

P10_5/AN5/KI1

P10_6/AN6/KI2

P10_7/AN7/KI3

P9_6/ANEX1/SOUT4

P9_0/TB0IN/CLK3

P2_0/AN2_0

P2_1/AN2_1

P2_2/AN2_2

P2_4/AN2_4

P2_5/AN2_5

P2_6/AN2_6

P2_7/AN2_7

P2_3/AN2_3

P9_7/ADTRG/SIN4

P9_2/TB2IN/SOUT3

M16C/62 Group

(

M16C/62P, M16C/62PT

)

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 16

1.6 Pin Description

Table 1.9 Pin Description (100-pin and 128-pin Version) (1)

Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the V

SS

pin. The VCC

apply condition is that VCC1 ≥ VCC2.

(2)

Applies the power supply for the A-D converter. Connect the AVCC pin to

VCC1. Connect the AVSS pin to VSS.

The microcomputer is in a reset state when applying "L" to the this pin.

Switches processor mode. Connect this pin to VSS to when after a reset to start

up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor

mode.

Switches the data bus in external memory space. The data bus is 16 bits long

when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it

to either one. Connect this pin to V

SS

when an single-chip mode.

Inputs and outputs data (D0 to D7) when these pins are set as the separate bus.

Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the

separate bus.

Output address bits (A0 to A19).

Input and output data (D0 to D7) and output address bits (A0 to A7) by time-

sharing when external 8-bit data bus are set as the multiplexed bus.

Input and output data (D0 to D7) and output address bits (A8 to A15) by time-

sharing when external 16-bit data bus are set as the multiplexed bus.

________ ________ ________ ________

Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an

external space.

________ _________ ______ ________ _____ ________ _________ _______ ______

Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR

can be switched by program.

________ _________ _____

• WRL, WRH and RD are selected

________

The WRL signal becomes "L" by writing data to an even address in an external

memory space.

_________

The WRH signal becomes "L" by writing data to an odd address in an external

memory space.

_____

The RD pin

signal becomes "L" by reading

data in an external memory space.

______ ________ _____

• WR, BHE and RD are selected

______

The WR signal becomes "L" by writing data in an external memory space.

_____

The RD

signal becomes "L" by

reading data in an external memory space.

________

The BHE signal becomes "L" by accessing an odd address.

______ ________ _____

Select WR, BHE and RD for an external 8-bit data bus.

ALE is a signal to latch the address.

__________

While the HOLD pin is held "L", the microcomputer is placed in a hold state.

_________

In a hold state, HLDA outputs a "L" signal.

________

While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait

state.

VCC1, VCC2

VSS

AVCC

AVSS

____________

RESET

CNVSS

BYTE

D0 to D7

D8 to D15

A0 to A19

A0/D0 to

A7/D7

A1/D0 to

A8/D7

______ ______

CS0 to CS3

________ ______

WRL/WR

_________ ________

WRH/BHE

_____

RD

ALE

__________

HOLD

__________

HLDA

________

RDY

Power supply input

Analog power

supply input

Reset input

CNVSS

External data bus

width select input

Bus control pins

(4)

I

I/O

O

I/O

O

I

O

I

-

VCC1

VCC2

Power

Signal name Pin name I/O type Description

supply

I : Input O : Output I/O : Input and output

Power supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be inter-

faced using the different voltage as VCC1.

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. In M16C/62PT, apply 2.7 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 ≥ VCC2.

3. When use VCC1 ≥ VCC2, contacts due to some points or restrictions to be checked.

4. This pin function is not in M16C/62PT.

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 17

1. Overview

Table 1.10 Pin Description (100-pin and 128-pin Version) (2)

XIN

XOUT

XCIN

XCOUT

BCLK

CLKOUT

________ ________

INT0 to INT5

_______

NMI

_____ ______

KI0 to KI3

TA0OUT to

TA4OUT

TA0IN to

TA4IN

ZP

TB0IN to

TB5IN

__ __

U, U, V, V,

__

W, W

__________ ________

CTS0 to CTS2

________ ________

RTS0 to RTS2

CLK0 to CLK4

RXD0 to RXD2

SIN3, SIN4

TXD0 to

TXD2

SOUT3, SOUT4

CLKS1

SDA0 to SDA2

SCL0 to SCL2

Main clock input

Main clock output

Sub clock input

Sub clock output

BCLK output

(2)

Clock output

______

INT interrupt input

_______

NMI interrupt input

Key input interrupt

input

Timer A

Timer B

Three-phase motor

control output

Serial I/O

I

2

C mode

VCC1

VCC2

VCC1

I

O

I

O

I

I/O

I

O

I

O

I/O

I

O

I/O

I/O pins for the main clock generation circuit. Connect a ceramic resonator or

crystal oscillator between XIN and XOUT

(3)

. To use the external clock, input the

clock from XIN and leave XOUT open.

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between

XCIN and XCOUT

(3)

. To use the external clock, input the clock from XCIN and

leave XCOUT open.

Outputs the BCLK signal.

The clock of the same cycle as fC, f8, or f32 is outputted.

______

Input pins for the INT interrupt

_______

Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8

register.

Input pins for the key input interrupt

These are timer A0 to timer A4 I/O pins. (except the output of TAOUT for the N-

channel open drain output.)

These are timer A0 to timer A4 input pins.

Input pin for the Z-phase.

These are timer B0 to timer B5 input pins.

These are Three-phase motor control output pins.

These are send control input pins.

These are receive control output pins.

These are transfer clock I/O pins.

These are serial data input pins.

These are serial data output pins. (except TXD2 for the N-channel open drain

output.)

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

These are serial data I/O pins. (except SDA2 for the N-channel open drain

output.)

These are transfer clock I/O pins. (except SCL2 for the N-channel open drain

output.)

I : Input O : Output I/O : Input and output

NOTES:

1. When use VCC1 ≥ VCC2, contacts due to some points or restrictions to be checked.

2. This pin function is not in M16C/62PT.

3. Ask the oscillator maker the oscillation characteristic.

Power

Signal name Pin name I/O type Description

supply

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 18

Table 1.11 Pin Description (100-pin and 128-pin Version) (3)

VREF

AN0 to AN7,

AN0_0 to AN0_7,

AN2_0 to AN2_7

___________

ADTRG

ANEX0

ANEX1

DA0, DA1

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_0 to P4_7,

P5_0 to P5_7,

P12_0 to

P12_7

(2)

,

P13_0 to

P13_7

(2)

P6_0 to P6_7,

P7_0 to P7_7,

P9_0 to P9_7,

P10_0 to P10_7,

P11_0 to

P11_7

(2)

P8_0 to P8_4,

P8_6, P8_7,

P14_0, P14_1

(2)

P8_5

Reference voltage

input

A-D converter

D-A converter

I/O port

Input port

VCC1

VCC2

VCC1

Applies the reference voltage for the A-D converter and D-A converter.

Analog input pins for the A-D converter

This is an A-D trigger input pin.

This is the extended analog input pin for the A-D converter, and is the output

in external op-amp connection mode.

This is the extended analog input pin for the A-D converter.

This is the Input pin for the D-A converter.

8-bit I/O ports in CMOS, having a direction register to select an input or output.

Each pin is set as an input port or output port. An input port can be set for a

pull-up or for no pull-up in 4-bit unit by program.

8-bit I/O ports having equivalent functions to P0.

(except P7_0 and P7_1 for the N-channel open drain output.)

I/O ports having equivalent functions to P0.

_______

Input pin for the NMI interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

I

I/O

I

O

I/O

I

I : Input O : Output I/O : Input and output

NOTES:

1. When use VCC1 ≥ VCC2, contacts due to some points or restrictions to be checked.

2. Ports P11 to P14 are provided in the 128-pin version only.

Power

Signal name Pin name I/O type Description

supply

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 19

1. Overview

Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin.

(2)

Applies the power supply for the A-D converter. Connect the AVCC pin to

VCC1. Connect the AVSS pin to VSS.

The microcomputer is in a reset state when applying "L" to the this pin.

Switches processor mode. Connect this pin to V

SS

to when after a reset to

start up in single-chip mode. Connect this pin to V

CC1

to start up in micropro-

cessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing

is performed within the microcomputer.

I/O pins for the main clock generation circuit. Connect a ceramic resonator or

crystal oscillator between XIN and XOUT

(3)

. To use the external clock, input

the clock from XIN and leave XOUT open.

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between

XCIN and XCOUT

(3)

. To use the external clock, input the clock from XCIN

and leave XCOUT open.

The clock of the same cycle as fC, f8, or f32 is outputted.

______

Input pins for the INT interrupt

_______

Input pin for the NMI interrupt.

Input pins for the key input interrupt

These are timer A0, timer A3 and Timer A4 I/O pins. (except the output of

TAOUT for the N-channel open drain output.)

These are timer A0, timer A3 and Timer A4 input pins.

Input pin for the Z-phase.

These are timer B0, timer B2 to timer B5 input pins.

These are send control input pins.

These are receive control output pins.

These are transfer clock I/O pins.

These are serial data input pins.

These are serial data output pins. (except TXD2 for the N-channel open drain

output.)

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

These are serial data I/O pins. (except SDA2 for the N-channel open drain

output.)

These are transfer clock I/O pins. (except SCL2 for the N-channel open drain

output.)

VCC1,

VSS

AVCC,

AVSS

____________

RESET

CNVSS

(BYTE)

XIN

XOUT

XCIN

XCOUT

CLKOUT

________ ________

INT0 to INT2

_______

NMI

______ ______

KI0 to KI3

TA0OUT,

TA3OUT,

TA4OUT

TA0IN,

TA3IN,

TA4IN

ZP

TB0IN,

TB2IN to TB5IN

_________ _________

CTS0, CTS2

_________ _________

RTS0, RTS2

CLK0, CLK1,

CLK3, CLK4

RXD0 to RXD2

SIN4

TXD0 to TXD4

SOUT3, SOUT4

CLKS1

SDA0 to SDA2

SCL0 to SCL2

Power supply input

Analog power

supply input

Reset input

CNVSS

Main clock input

Main clock output

Sub clock input

Sub clock output

Clock output

______

INT interrupt input

_______

NMI interrupt input

Key input interrupt

input

Timer A

Timer B

Serial I/O

I

2

C mode

I

O

I

O

I

I/O

I

O

I/O

I

O

I/O

-

VCC1

VCC2

VCC1

Power

Signal name Pin name I/O type Description

supply

I : Input O : Output I/O : Input and output

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.

3. Ask the oscillator maker the oscillation characteristic.

Table 1.12 Pin Description (80-pin Version) (1)

1. Overview

M16C/62 Group (M16C/62P, M16C/62PT)

48fo3002,70.voN01.2.veR

page 20

Table 1.13 Pin Description (80-pin Version) (2)

VREF

AN0 to AN7,

AN0_0 to AN0_7,

AN2_0 to AN2_7

___________

ADTRG

ANEX0

ANEX1

DA0, DA1

P0_0 to P0_7,

P2_0 to P2_7,

P3_0 to P3_7,

P5_0 to P5_7,

P6_0 to P6_7,

P10_0 to P10_7

P8_0 to P8_4,

P8_6, P8_7,

P9_0,

P9_2 to P9_7

P4_0 to P4_3,

P7_0, P7_1,

P7_6, P7_7

P8_5

Reference voltage

input

A-D converter

D-A converter

I/O port

Input port

VCC1

Applies the reference voltage for the A-D converter and D-A converter.

Analog input pins for the A-D converter

This is an A-D trigger input pin.

This is the extended analog input pin for the A-D converter, and is the output

in external op-amp connection mode.

This is the extended analog input pin for the A-D converter.

This is the Input pin for the D-A converter

8-bit I/O ports in CMOS, having a direction register to select an input or

output.

Each pin is set as an input port or output port. An input port can be set for a

pull-up or for no pull-up in 4-bit unit by program.

I/O ports having equivalent functions to P0.

(except P7_0 and P7_1 for the N-channel open drain output.)

_______

Input pin for the NMI interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

I

I/O

I

O

I/O

I

I : Input O : Output I/O : Input and output

NOTES:

1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

Set the direction bits in these ports to “1” (input mode), and set the output data to “0” (“L”) using the program.

Power

Signal name Pin name I/O type Description

supply

M16C/62 Group (M16C/62P, M16C/62PT)

page 21

2. Central Processing Unit (CPU)

48fo3002,70.voN01.2.veR

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-

bit data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address

register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as

A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Data registers

(1)

Address registers

(1)

Frame base registers

(1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

NOTES:

1. These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)

b15 b8 b7 b0

R3

INTBH

USP

ISP

SB

AA

A

AAAAAAA

AA

A

AA

CDZSBOIU

IPL

R0L(R0's low bits)

R1H(R1's high bits)R1L(R1's low bits)

R2

b31

R3

R2

A1

A0

FB

b19

INTBL

b15 b0

PC

b19 b0

b15 b0

FLG

b15 b0

b7 b8

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

M16C/62 Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU)

48fo3002,70.voN01.2.veR

page 22

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to

“1”

when an arithmetic operation resulted in a negative value; otherwise, it is

“0”

.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I

flag is cleared to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.

The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for

software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from

level 0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write "0". When read, its content is indeterminate.

M16C/62 Group (M16C/62P, M16C/62PT)

page 23

3. Memory

48fo3002,70.voN01.2.veR

3. Memory

Figure 3.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from

address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a

64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is

mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the

start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example,

a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data,

the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are

located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot

be used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by

the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.

In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be

used by users. Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expan-

sion and microprocessor modes cannot be used.

Figure 3.1 Memory Map

00000h

XXXXXh

AAAAAA

A

AAAA

A

AAAA

A

AAAA

A

AAAA

A

AAAAAA

External area

Internal ROM

(program area)

SFR

Internal RAM

Reserved area (1)

Reserved area (2)

FFFDCh

NOTES:

1. During memory expansion and microprocessor modes, can not be used.

2. In memory expansion mode, can not be used.

3. As for the flash memory version, 4-Kbyte space (block A) exists.

4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”

and the PM13 bit in the PM1 register is “1”.

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

Reset

Special page

vector table

DBC

NMI

4K bytes 013FFh

02BFFh

017FFh

Address XXXXXh

033FFh

10K bytes

5K bytes

12K bytes

Size Address YYYYYhSize

F0000h

E8000h

F4000h

96K bytes

48K bytes

64K bytes Reserved area

External area

00400h

10000h

27000h

28000h

80000h

YYYYYh

FFFFFh

E0000h

256K bytes

128K bytes

192K bytes D0000h

320K bytes

C0000h

384K bytes

B0000h

A0000h

512K bytes 80000h

063FFh

053FFh

07FFFh

24K bytes

20K bytes

31K bytes

Internal RAM Internal ROM

(3)

043FFh16K bytes

FFE00h

FFFFFh

Internal ROM

(data area)

(3)

0FFFFh

0F000h

M16C/62 Group (M16C/62P, M16C/62PT) 4. SFR

48fo3002,70.voN01.2.veR

page 24

DMA0 control register DM0CON 00000X00b

DMA0 transfer counter TCR0 XXh

XXh

DMA1 control register DM1CON 00000X00b

DMA1 source pointer SAR1 XXh

XXh

DMA1 transfer counter TCR1 XXh

XXh

DMA1 destination pointer DAR1 XXh

XXh

Watchdog timer start register WDTS XXh

Watchdog timer control register WDC 00XXXXXXb

(4)

Processor mode register 0

(2)

PM0

00000000b(CNVSS pin is “L”)

00000011b(CNVSS pin is “H”)

Chip select control register

(6)

CSR 00000001b

System clock control register 0 CM0 01001000b

System clock control register 1 CM1 00100000b

Address match interrupt enable register AIER XXXXXX00b

Protect register PRCR XX000000b

Processor mode register 1 PM1 00001000b

DMA0 destination pointer DAR0 XXh

XXh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.

3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.

4. The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage

at the V

CC1

pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enabl

e

5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

6. This register cannot be used by M16C/62PT.

X : Nothing is mapped to this bit

Data bank register

(6)

DBR 00h

Oscillation stop detection register

(3)

CM2 0000X000b

Chip select expansion control register

(6)

CSE 00h

PLL control register 0 PLC0 0001X010b

Processor mode register 2 PM2 XXX00000b

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

Address

Register Symbol After reset

Address match interrupt register 0 RMAD0 00h

00h

X0h

Address match interrupt register 1 RMAD1 00h

00h

X0h

DMA0 source pointer SAR0 XXh

XXh

Voltage detection register 1

(5, 6)

VCR1 00001000b

Voltage detection register 2

(5, 6)

VCR2 00h

Voltage down detection interrupt register

(6)

D4INT 00h

4. SFR

M16C/62 Group (M16C/62P, M16C/62PT)

page 25

4. SFR

48fo3002,70.voN01.2.veR

Timer A1 interrupt control register TA1IC XXXXX000b

UART0 transmit interrupt control register S0TIC XXXXX000b

Timer A0 interrupt control register TA0IC XXXXX000b

Timer A2 interrupt control register TA2IC XXXXX000b

UART0 receive interrupt control register S0RIC XXXXX000b

UART1 transmit interrupt control register S1TIC XXXXX000b

UART1 receive interrupt control register S1RIC XXXXX000b

DMA1 interrupt control register DM1IC XXXXX000b

DMA0 interrupt control register DM0IC XXXXX000b

Key input interrupt control register KUPIC XXXXX000b

A-D conversion interrupt control register ADIC XXXXX000b

UART2 Bus collision detection interrupt control register BCNIC XXXXX000b

UART2 transmit interrupt control register S2TIC XXXXX000b

UART2 receive interrupt control register S2RIC XXXXX000b

INT1 interrupt control register INT1IC XX00X000b

Timer B0 interrupt control register TB0IC XXXXX000b

Timer B2 interrupt control register TB2IC XXXXX000b

Timer A3 interrupt control register TA3IC XXXXX000b

INT2 interrupt control register INT2IC XX00X000b

INT0 interrupt control register INT0IC XX00X000b

Timer B1 interrupt control register TB1IC XXXXX000b

Timer A4 interrupt control register TA4IC XXXXX000b

INT3 interrupt control register INT3IC XX00X000b

Timer B5 interrupt control register TB5IC XXXXX000b

Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register TB4IC, U1BCNIC

XXXXX000b

Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register TB3IC, U0BCNIC

XXXXX000b

SI/O4 interrupt control register (S4IC), INT5 interrupt control register S4IC

,

INT5IC XX00X000b

SI/O3 interrupt control register, INT4 interrupt control register S3IC

,

INT4IC XX00X000b

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

Address

Register Symbol After reset

M16C/62 Group (M16C/62P, M16C/62PT) 4. SFR

48fo3002,70.voN01.2.veR

page 26

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

to

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

00C0h

to

02AFh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

to

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

X : Nothing is mapped to this bit

Peripheral clock select register PCLKR 00000011b

Flash memory control register 0

(2)

FMR0 XX000001b

Flash memory control register 1

(2)

FMR1 0X00XX0Xb

Address match interrupt register 2 RMAD2 00h

00h

X0h

Address match interrupt register 3 RMAD3 00h

00h

X0h

Address match interrupt enable register 2 AIER2 XXXXXX00b

Address

Register Symbol After reset

Flash identification register

(2)

FIDR XXXXXX00b

M16C/62 Group (M16C/62P, M16C/62PT)

page 27

4. SFR

48fo3002,70.voN01.2.veR

Address

Register Symbol After reset

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

Timer A1-1 register TA11 XXh

XXh

Timer A2-1 register TA21 XXh

XXh

Dead time timer DTT XXh

Timer B2 interrupt occurrence frequency set counter ICTB2 XXh

Three-phase PWM control register 0 INVC0 00h

Three-phase PWM control register 1 INVC1 00h

Three-phase output buffer register 0 IDB0 00h

Three-phase output buffer register 1 IDB1 00h

Timer B3 register TB3 XXh

XXh

Timer B4 register TB4 XXh

XXh

Timer B5 register TB5 XXh

XXh

Timer B3, 4, 5 count start flag TBSR 000XXXXXb

Timer B3 mode register TB3MR 00XX0000b

Timer B4 mode register TB4MR 00XX0000b

Timer B5 mode register TB5MR 00XX0000b

Interrupt cause select register IFSR 00h

SI/O3 transmit/receive register S3TRR XXh

SI/O4 transmit/receive register S4TRR XXh

SI/O3 control register S3C 01000000b

SI/O3 bit rate generator S3BRG XXh

SI/O4 bit rate generator S4BRG XXh

SI/O4 control register S4C 01000000b

UART2 special mode register U2SMR X0000000b

UART2 receive buffer register U2RB XXh

XXh

UART2 transmit buffer register U2TB XXh

XXh

UART2 transmit/receive control register 0 U2C0 00001000b

UART2 transmit/receive mode register U2MR 00h

UART2 transmit/receive control register 1 U2C1 00000010b

UART2 bit rate generator U2BRG XXh

Timer A4-1 register TA41 XXh

XXh

UART2 special mode register 2 U2SMR2 X0000000b

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

UART2 special mode register 3 U2SMR3 000X0X0Xb

Interrupt cause select register 2 IFSR2A 00XXXXXXb

UART0 special mode register 2 U0SMR2 X0000000b

UART0 special mode register U0SMR X0000000b

UART0 special mode register 3 U0SMR3 000X0X0Xb

UART0 special mode register 4 U0SMR4 00h

UART1 special mode register 2 U1SMR2 X0000000b

UART1 special mode register U1SMR X0000000b

UART1 special mode register 3 U1SMR3 000X0X0Xb

UART1 special mode register 4 U1SMR4 00h

UART2 special mode register 4 U2SMR4 00h

M16C/62 Group (M16C/62P, M16C/62PT) 4. SFR

48fo3002,70.voN01.2.veR

page 28

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

Timer A0 register TA0 XXh

XXh

Timer A1 register TA1 XXh

XXh

Timer A2 register TA2 XXh

XXh

Timer B0 register TB0 XXh

XXh

Timer B1 register TB1 XXh

XXh

Timer B2 register TB2 XXh

XXh

Count start flag TABSR 00h

One-shot start flag ONSF 00h

Timer A0 mode register TA0MR 00h

Timer A1 mode register TA1MR 00h

Timer A2 mode register TA2MR 00h

Timer B0 mode register TB0MR 00XX0000b

Timer B1 mode register TB1MR 00XX0000b

Timer B2 mode register TB2MR 00XX0000b

Up-down flag UDF 00h

(2)

Timer A3 register TA3 XXh

XXh

Timer A4 register TA4 XXh

XXh

Timer A3 mode register TA3MR 00h

Timer A4 mode register TA4MR 00h

Trigger select register TRGSR 00h

Clock prescaler reset flag CPSRF 0XXXXXXXb

UART0 transmit/receive mode register

U0MR 00h

UART0 transmit buffer register U0TB XXh

XXh

UART0 receive buffer register U0RB XXh

XXh

UART1 transmit/receive mode register

U1MR 00h

UART1 transmit buffer register U1TB XXh

XXh

UART1 receive buffer register U1RB XXh

XXh

UART0 bit rate generator U0BRG XXh

UART0 transmit/receive control register 0

U0C0 00001000b

UART0 transmit/receive control register 1

U0C1 00000010b

UART1 bit rate generator U1BRG XXh

UART1 transmit/receive control register 0

U1C0 00001000b

UART1 transmit/receive control register 1

U1C1 00000010b

DMA1 request cause select register DM1SL 00h

DMA0 request cause select register DM0SL 00h

CRC data register CRCD XXh

XXh

CRC input register CRCIN XXh

UART transmit/receive control register 2

UCON X0000000b

NOTES :

1.The blank areas are reserved and cannot be accessed by users.

2. Bits 7 to 5 in the Up-down flag are “

0” by reset. However, The values in these bits when read are indeterminate.

X : Nothing is mapped to this bit

Timer B2 special mode register TB2SC XXXXXX00b

Address

Register Symbol After reset

M16C/62 Group (M16C/62P, M16C/62PT)

page 29

4. SFR

48fo3002,70.voN01.2.veR

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. At hardware reset 1 or hardware reset 2, the register is as follows:

• “00000000b” where “L” is inputted to the CNV

SS

• “00000010b” where “H” is inputted to the CNV

SS

At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:

• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode)

• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or

“11b” (microprocessor mode)

X : Nothing is mapped to this bit

A-D register 7 AD7 XXh

XXh

A-D register 0 AD0 XXh

XXh

A-D register 1 AD1 XXh

XXh

A-D register 2 AD2 XXh

XXh

A-D register 3 AD3 XXh

XXh

A-D register 4 AD4 XXh

XXh

A-D register 5 AD5 XXh

XXh

A-D register 6 AD6 XXh

XXh

A-D control register 0 ADCON0 00000XXXb

D-A register 0 DA0 00h

D-A register 1 DA1 00h

D-A control register DACON 00h

A-D control register 2 ADCON2 00h

A-D control register 1 ADCON1 00h

Port P0 register P0 XXh

Port P0 direction register PD0 00h

Port P1 register P1 XXh

Port P1 direction register PD1 00h

Port P2 register P2 XXh

Port P2 direction register PD2 00h

Port P3 register P3 XXh

Port P3 direction register PD3 00h

Port P4 register P4 XXh

Port P4 direction register PD4 00h

Port P5 register P5 XXh

Port P5 direction register PD5 00h

Port P6 register P6 XXh

Port P6 direction register PD6 00h

Port P7 register P7 XXh

Port P7 direction register PD7 00h

Port P8 register P8 XXh

Port P8 direction register PD8 00X00000b

Port P9 register P9 XXh

Port P9 direction register PD9 00h

Port P10 register P10 XXh

Port P10 direction register PD10 00h

Pull-up control register 0 PUR0 00h

Pull-up control register 1 PUR1

00000000b

00000010b

Pull-up control register 2 PUR2 00h

Port control register PCR 00h

Port P14 control register PC14 XX00XXXXb

Pull-up control register 3 PUR3 00h

Port P11 register P11 XXh

Port P12 register P12 XXh

Port P13 register P13 XXh

Port P11 direction register PD11 00h

Port P12 direction register PD12 00h

Port P13 direction register PD13 00h

Register Symbol After reset

Address

(2)

M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P)

48fo3002,70.voN01.2.veR

page 30

Table 5.1 Absolute Maximum Ratings

O

p

e

r

a

t

i

n

g

a

m

b

i

e

n

t

e

m

p

e

r

a

t

u

r

e

P

a

r

a

m

e

t

e

rUnit

V

R

E

F

,

X

I

N

I

n

p

u

t

v

o

l

t

a

g

e

A

n

a

l

o

g

s

u

p

l

y

v

o

l

t

a

g

e

Supply voltage

O

u

t

p

u

t

v

o

l

t

a

g

e

X

O

U

T

V

O

-0.3 to V

CC1

+0.3

(1)

-

0

.

3

t

o

V

C

1

+

0

.

3

(

1

)

P

d

Power dissipation

S

t

o

r

a

g

e

t

e

m

p

e

r

a

t

u

r

e

R

a

t

e

d

v

a

l

u

e

V

C

o

n

d

i

t

i

o

n

V

I

A

V

C

V

C

1

,

V

C

2

T

s

t

g

T

o

p

r

S

y

m

b

o

l

mW

P

3

_

0

t

o

P

3

_

7

,

P

4

_

0

t

o

P

4

_

7

,

P

5

_

0

t

o

P

5

_

7

,

P

6

_

0

t

o

P

6

_

7

,

P

7

_

2

t

o

P

7

_

7

,

P

8

_

0

t

o

P

8

_

7

,

P

6

_

0

t

o

P

6

_

7

,

P

7

_

2

t

o

P

7

_

7

,

P

8

_

0

t

o

P

8

_

4

,

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

9

_

0

t

o

P

9

_

7

,

P

1

0

_

0

t

o

P

1

0

_

7

,

P

8

_

6

,

P

8

_

7

,

P

9

_

0

t

o

P

9

_

7

,

P

1

0

_

0

t

o

P

1

0

_

7

,

P

7

_

0

,

P

7

_

1

P

7

_

0

,

P

7

_

1

-

0

.

3

t

o

6

.

5

V

R

E

S

E

T

,

C

N

V

S

,

B

Y

T

E

,

V

CC1

=AV

CC

V

CC1

=AV

CC

-

0

.

3

t

o

6

.

5

P

1

_

0

t

o

P

1

_

7

,

P

1

4

_

0

,

P

1

4

_

1

,

S

u

p

l

y

v

o

l

t

a

g

e -

0

.

3

t

o

V

C

1

+

0

.

1V

V

C

2

V

CC2

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7-

0

.

3

t

o

V

C

2

+

0

.

3

(

1

)

V

P11_0 to P11_7, P 14_0, P14_1,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P12_0 to P12_7, P 13_0 to P13_7

-0.3 to V

CC2

+0.3

(1)

V

-

0

.

3

t

o

6

.

5

-

6

5

t

o

1

5

0

300

-

2

0

t

o

8

5

/

-

4

0

t

o

8

5

-

0

.

3

t

o

6

.

5

°C

NOTES:

1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

-40 °C < T

opr

≤ 85 °C

W

h

e

n

t

h

e

m

i

c

r

o

c

o

m

p

u

t

e

r

i

s

o

p

e

r

a

t

i

n

g

F

l

a

s

h

p

r

o

g

r

a

m

e

r

a

s

e0

t

o

6

0

5. Electrical Characteristics

5.1 Electrical Characteristics (M16C/62P)

M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P)

48fo3002,70.voN01.2.veR

page 31

2

.

75

.

5

T

y

p

.M

a

x

.UnitP

a

r

a

m

e

t

e

r

VC

C

1,

VC

C

25.0S

u

p

l

y

v

o

l

t

a

g

e

(

VC

C

1≥V

C

2)

S

y

m

b

o

lMin. S

t

a

n

d

a

r

d

A

n

a

l

o

g

s

u

p

l

y

v

o

l

t

a

g

e VC

C

1A

V

c

c V

V0

0A

n

a

l

o

g

s

u

p

l

y

v

o

l

t

a

g

e

S

u

p

l

y

v

o

l

t

a

g

e

VI

H

IOH (avg) H

I

G

H

a

v

e

r

a

g

e

o

u

t

p

u

t

c

u

r

e

n

t

mA

V

s

A

V

s

s0

.

8

VC

C

2

V

VC

C

2

0

.

2

VC

C

2

0.2VCC1

0

L

O

W

i

n

p

u

t

v

o

l

t

a

g

e

0.16VCC2

IOH (peak) HIGH peak output

current

H

I

G

H

i

n

p

u

t

v

o

l

t

a

g

e

-5.0

-10.0

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P

8

_

0

t

o

P

8

_

4

,

P

8

_

6

,

P

8

_

7

,

P

9

_

0

t

o

P

9

_

7

,

P

1

0

_

0

t

o

P

1

0

_

7

,

P

3

_

1

t

o

P

3

_

7

,

P

4

_

0

t

o

P

4

_

7

,

P

5

_

0

t

o

P

5

_

7

,

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7

V

0

.

8

VC

C

2

0

.

5

VC

C

2

VC

C

2

VC

C

2

(

d

a

t

a

i

n

p

u

t

d

u

r

i

n

g

m

e

m

o

r

y

e

x

p

a

n

s

i

o

n

a

n

d

m

i

c

r

o

p

r

o

c

e

s

o

r

m

o

d

e

s

)

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

3

_

0

(

d

u

r

i

n

g

s

i

n

g

l

e

-

c

h

i

p

m

o

d

e

)

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

3

_

0

L

O

W

p

e

a

k

o

u

t

p

u

t

c

u

r

e

n

t1

0

.

0

5.0

m

A

LOW average

output current

IO

L

(

p

e

a

k

)

mAIOL (avg)

V

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

3

_

0

t

o

P

3

_

7

,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

3

_

0

t

o

P

3

_

7

,

P

4

_

0

t

o

P

4

_

7

,

P

5

_

0

t

o

P

5

_

7

,

P

6

_

0

t

o

P

6

_

7

,

P

7

_

0

t

o

P

7

_

7

,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P

8

_

0

t

o

P

8

_

4

,

P

8

_

6

,

P

8

_

7

,

P

9

_

0

t

o

P

9

_

7

,

P

1

0

_

0

t

o

P

1

0

_

7

,

P

7

_

0

,

P

7

_

1

0

.

8

VC

C

16

.

5V

VI

L

P

1

_

0

t

o

P

1

_

7

,

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7

,

P

1

4

_

0

,

P

1

4

_

1

P

1

_

0

t

o

P

1

_

7

,

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7

,

P

1

4

_

0

,

P

1

4

_

1

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

P

1

_

0

t

o

P

1

_

7

,

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7

,

P

1

4

_

0

,

P

1

4

_

1

NOTES:

1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.

2. SVCC indicates the minimum time gradient until VCC1 reaches 2.7V.

3. The mean output current is the mean value within 100ms.

4. The total IOL (peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL (peak) for

ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be

-40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for ports P6, P7, and

P8_0 to P8_4 must be -40mA max. The total IOH (peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be -40mA max.

5. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

0

.

8

VC

C

1VVCC1

P

6

_

0

t

o

P

6

_

7

,

P

7

_

2

t

o

P

7

_

7

,

P

8

_

0

t

o

P

8

_

7

,

P

9

_

0

t

o

P

9

_

7

,

P

1

0

_

0

t

o

P

1

0

_

7

,

X

I

N

,

R

E

S

E

T

,

C

N

V

S

,

B

Y

T

E

P

1

_

0

t

o

P

1

_

7

,

P

1

4

_

0

,

P

1

4

_

1

,

P

3

_

1

t

o

P

3

_

7

,

P

4

_

0

t

o

P

4

_

7

,

P

5

_

0

t

o

P

5

_

7

,

P

1

2

_

0

t

o

P

1

2

_

7

,

P

1

3

_

0

t

o

P

1

3

_

7

P

0

_

0

t

o

P

0

_

7

,

P

1

_

0

t

o

P

1

_

7

,

P

2

_

0

t

o

P

2

_

7

,

P

3

_

0

(

d

u

r

i

n

g

s

i

n

g

l

e

-

c

h

i

p

m

o

d

e

)

V0.2VCC20

(data input during memory expansion and microprocessor modes)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

XIN, RESET, CNVSS, BYTE

P

1

_

0

t

o

P

1

_

7

,

P

1

4

_

0

,

P

1

4

_

1

,

f(

r

i

p

l

e

)

(

2

)

P

o

w

e

r

s

u

p

l

y

r

i

p

l

e

a

l

o

w

a

b

l

e

f

r

e

q

u

e

n

c

y

P

o

w

e

r

s

u

p

l

y

r

i

p

l

e

a

l

o

w

a

b

l

e

a

m

p

l

i

t

u

d

e

v

o

l

t

a

g

e

VP

-

P

(

r

i

p

l

e

)

(

2

)

(VCC1=5V)

(VCC1=3V)

P

o

w

e

r

s

u

p

l

y

r

i

p

l

e

r

i

s

i

n

g

/

f

a

l

i

n

g

r

a

d

i

e

n

t

VC

C

(

|

∆

V

/

∆

T

|

)

(

2

)

(VCC1=5V)

(VCC1=3V)

P

o

w

e

r

s

u

p

l

y

r

i

s

i

n

g

r

a

d

i

e

n

t

S

VC

C

(

2

)

1

0

0.5

0.

3

0.

3

0.

3

0

.

0

5

M

H

z

V

/

m

s

V

/

m

s

V

/

m

s

Table 5.2

Recommended Operating Conditions (1)

(1)

Vp-p(ripple)

f(ripple)

SVCC

t

V

VCC1

0V

M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P)

48fo3002,70.voN01.2.veR

page 32

Table 5.3

Recommended Operating Conditions (2)

(1)

Main clock input oscillation frequency

16.0

0.0

f(XIN) operating maximum

frequency

[MHz]

V

CC1

[V] (main clock: no division) 5.53.0

10.0

2.7

AAAAAA

20 x V

CC1

-44MHz

PLL clock oscillation frequency

24.0

0.0

f(PLL) operating maximum

frequency

[MHz]

V

CC1

[V] (PLL clock oscillation) 5.5

10.0

2.7

AAAAAA

3.0

46.67 x V

CC1

-116MHz

T

y

p

.Max.U

n

i

tP

a

r

a

m

e

t

e

r

S

y

m

b

o

lMin. S

t

a

n

d

a

r

d

NO

T

E

S:

1

.

R

e

f

e

r

e

n

c

e

d

t

o

VC

C

1

=

VC

C

2

=

2

.

7

t

o

5

.

5

V

a

t

To

p

r

=

-

2

0

t

o

8

5

°

C

/

-

4

0

t

o

8

5

°

C

u

n

l

e

s

o

t

h

e

r

w

i

s

e

s

p

e

c

i

f

i

e

d

.

2

.

R

e

l

a

t

i

o

n

s

h

i

p

b

e

t

w

e

n

m

a

i

n

c

l

o

c

k

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y

,

P

L

c

l

o

c

k

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y

a

n

d

s

u

p

l

y

v

o

l

t

a

g

e

.

f (

X

I

N

)M

a

i

n

c

l

o

c

k

i

n

p

u

t

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y

(

2

)2

0

X

VC

C

1-

4

VC

C

1=

3

.

0

t

o

5

.

5

V

VC

C

1=

2

.

7

t

o

3

.

0

V0

0MHz

MHz

1

6

f (

X

C

I

N

)S

u

b

-

c

l

o

c

k

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y kHz503

2

.

7

6

8

f (

R

i

n

g

)R

i

n

g

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

yMHz1

f (

P

L

)P

L

c

l

o

c

k

o

s

c

i

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y

(

2

)4

6

.

6

7

X

VC

C

1-

1

6

VC

C

1=

3

.

0

t

o

5

.

5

V

VC

C

1=

2

.

7

t

o

3

.

0

V

1

0

1

0

MHz

2

4

f (BCL K) CPU operation clock 0MHz

24

tS

U(

P

L

)P

L

f

r

e

q

u

e

n

c

y

s

y

n

t

h

e

s

i

z

e

r

s

t

a

b

i

l

i

z

a

t

i

o

n

w

a

i

t

i

m

eVC

C

1=

5

.

0

V

VC

C

1=

3

.

0

V50

20 ms

ms

0

.

52

M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P)

48fo3002,70.voN01.2.veR

page 33

Table 5.4 A-D Conversion Characteristics (1)

Standard

Min. T

y

p

.M

a

x

.

–

I

N

L

R

e

s

o

l

u

t

i

o

n

I

n

t

e

g

r

a

l

n

o

n

-

l

i

n

e

a

r

i

t

y

e

r

o

r

BitsV

R

E

F

=

V

C

1

0

S

y

m

b

o

lP

a

r

a

m

e

t

e

rM

e

a

s

u

r

i

n

g

c

o

n

d

i

t

i

o

nUnit

<