M16C/62 Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0210Z Rev.2.10 Nov. 07, 2003 1. Overview The M16C/62 group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 Applications Audio, cameras, office/communications/portable/industrial equipment, automobile, etc Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.2.10 Nov. 07, 2003 page 1 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 1.2 Performance Outline Table 1.1 to table 1.3 list performance outline of M16C/62 group (M16C/62P, M16C/62PT). Table 1.1 Performance outline of M16C/62 group (M16C/62P) (128-pin version) Item CPU Performance M16C/62P Number of basic instructions Shortest instruction execution time Operation mode Memory space Peripheral function Memory capacity Port Multifunction timer Serial I/O A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Oscillation stop detection function Electric characteristics Flash memory Version Voltage detection circuit Supply voltage Power consumption Program/erase supply voltage Program and erase endurance Operating ambient temperature Package 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Single-chip, memory expansion and microprocessor mode 1 Mbyte (Available to 4M bytes by memory space expansion function) See table 1.4 and 1.5 Product List Input/Output : 113 pins, Input : 1 pin Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels Three phase motor control circuit 3 channels Clock synchronous, UART, I2C bus (1), IEBus (2) 2 channels Clock synchronous 10-bit A-D converter: 1 circuit, 26 channels 8 bits x 2 channels 2 channels CCITT-CRC 15 bits x 1 channel (with prescaler) Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), Ring oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Stop detection of main clock oscillation, re-oscillation detection function Available (option (4)) VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz) VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8 A (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7 A (VCC1=VCC2=3V, stop mode) 3.3 0.3 V or 5.0 0.5 V 100 times (all area) or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) -20 to 85oC -40 to 85oC (3) 128-pin plastic mold QFP NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule. 4. All options are on request basis. Rev.2.10 Nov. 07, 2003 page 2 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.2 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (100-pin version) Item Performance M16C/62P M16C/62PT(Note 4) Number of basic instructions 91 instructions Shortest instruction execution time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operation mode Single-chip, memory expansion and Single-chip mode microprocessor mode Memory space 1 Mbyte (Available to 4 Mbytes by 1M byte memory space expansion function) Memory capacity See table 1.4 to 1.7 Product List Port Input/Output : 87 pins, Input : 1pin Peripheral Multifunction timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels function Three phase motor control circuit Serial I/O 3 channels Clock synchronous, UART, I2C bus (1), IEBus (2) 2 channels Clock synchronous A-D converter 10-bit A-D converter: 1 circuit, 26 channels D-A converter 8 bits x 2 channels DMAC 2 channels CRC calculation circuit CCITT-CRC Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Clock generating circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), Ring oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation stop detection function Stop detection of main clock oscillation, re-oscillation detection function Voltage detection circuit Available (option (5)) Absent VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 VCC1=VCC2=4.0V to 5.5 V Supply voltage Electric (f(BCLK)=24MHz) (f(BCLK)=24MHz) characterisVCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 tics (f(BCLK)=10MHz) Power consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 A (VCC1=VCC2=5V, 1.8 A (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) f(XCIN)=32kHz, wait mode) 0.8 A (VCC1=VCC2=5V, stop mode) 0.7 A (VCC1=VCC2=3V, stop mode) 3.3 0.3 V or 5.0 0.5 V 5.0 0.5 V Flash memory Program/erase supply voltage Program and erase endurance 100 times (all area) Version or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) Operating ambient temperature -20 to 85oC T version : -40 to 85oC o (3) -40 to 85 C V version : -40 to 125oC Package 100-pin plastic mold QFP, LQFP CPU NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule. 4. Use the high reliability version on VCC1 = VCC2. 5. All options are on request basis. Rev.2.10 Nov. 07, 2003 page 3 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.3 Performance outline of M16C/62 group (M16C/62P, M16C/62PT) (80-pin version) Item Performance M16C/62P M16C/62PT CPU Number of basic instructions 91 instructions Shortest instruction execution time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Operation mode Single-chip mode Memory space 1M byte Memory capacity See table 1.4 to 1.7 Product List Peripheral Port Input/Output : 70 pins, Input : 1pin function Multifunction timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer) Timer B : 16 bits x 6 channels (Timer B1 is internal timer) Serial I/O 2 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 1 channel Clock synchronous, I2C bus(1), IEBus(2) 2 channels Clock synchronous (1 channel is only for transmission) A-D converter 10-bit A-D converter: 1 circuit, 26 channels D-A converter 8 bits x 2 channels DMAC 2 channels CRC calculation circuit CCITT-CRC Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock generating circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), Ring oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation stop detection function Stop detection of main clock oscillation, re-oscillation detection function Voltage detection circuit Available (option (4)) Absent Electric VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz) Supply voltage characterisVCC1=2.7 to 5.5V, (f(BCLK)=10MHz) tics Power consumption 14 mA (VCC1=5V, f(BCLK)=24MHz) 14 mA (VCC1=5V, f(BCLK)=24MHz) 8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0 A (VCC1=5V, 1.8 A (VCC1=3V, f(XCIN)=32kHz, wait mode) f(XCIN)=32kHz, wait mode) 0.8 A (VCC1=5V, stop mode) 0.7 A (VCC1=3V, stop mode) Flash Program/erase supply voltage 3.3 0.3 V or 5.0 0.5 V 5.0 0.5 V memory Program and erase endurance 100 times (all area) Version or 1,000 times (user ROM area without block 1) / 10,000 times (block A, block 1) (3) Operating ambient temperature -20 to 85oC T version : -40 to 85oC o -40 to 85 C(option) V version : -40 to 125oC Package 80-pin plastic mold QFP NOTES : 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Oct., 2003. Please inquire about a release schedule. 4. All options are on request basis. Rev.2.10 Nov. 07, 2003 page 4 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 1.3 Block Diagram Figure 1.1 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 128-pin and 100-pin version, figure 1.2 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 80-pin version. 8 8 Port P0 8 Port P1 8 Port P3 Port P2 8 Port P4 Port P5 Timer (16-bit) Expandable up to 26 channels) Output (timer A): 5 Input (timer B): 6 UART or clock synchronous serial I/O (8 bits X 3 channels) Clock synchronous serial I/O (8 bits X 2 channels) M16C/60 series16-bit CPU core R2 R3 DMAC ISP INTB D-A converter PC FLG 8 <VCC2 ports>(4) Port P14 Port P12 (3) Port P13 (3) (3) 2 8 8 <VCC1 ports>(4) (3) AAAAA AAAAA AAAAA Multiplier (8 bits X 2 channels) Port P11 RAM (2) Port P10 A0 A1 FB (2 channels) ROM (1) USP 8 (15 bits) SB R0L R1L Port P9 R0H R1H Watchdog timer Memory Port P8_5 CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) <VCC1 ports>(4) XIN-XOUT XCIN-XCOUT PLL frequency synthesizer Ring oscillator 7 System clock generation circuit A-D converter (10 bits X 8 channels 8 <VCC1 ports>(4) Internal peripheral functions Three-phase motor control circuit Port P6 Port P8 ports>(4) 8 Port P7 <VCC2 8 8 NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1= VCC2. Figure 1.1 M16C/62 Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram Rev.2.10 Nov. 07, 2003 page 5 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 8 8 Port P0 Port P2 8 Port P3 4 8 Port P4 Port P5 8 Port P6 XIN-XOUT XCIN-XCOUT PLL frequency synthesizer Ring oscillator UART or clock synchronous serial I/O (2 channels) UART (1 channel) (3) Clock synchronous serial I/O Watchdog timer M16C/60 series16-bit CPU core R0H R1H R0L R1L DMAC (2 channels) (8 bits X 2 channels) ISP INTB ROM (1) RAM (2) PC FLG Multiplier 8 Port P10 A0 A1 FB D-A converter SB USP 7 R2 R3 Memory Port P9 (15 bits) (4) (8 bits X 2 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) Port P8_5 Three-phase motor control circuit Expandable up to 26 channels) 7 Output (timer A): 5 Input (timer B): 6 System clock generation circuit A-D converter (10 bits X 8 channels Port P8 Timer (16-bit) 4 Internal peripheral functions Port P7 (4) NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. To use a UART2, set the CRD bit in the U2C0 register to "1" (CTS/RTS function disabled). 4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to "1" (output mode), and set the output data to "0" ("L") using the program. Figure 1.2 M16C/62 Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram Rev.2.10 Nov. 07, 2003 page 6 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 1.4 Product List Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table 1.8 lists the product code of flash memory version and external ROM version for M16C/62P. Figure 1.4 shows the marking diagram of flash memory version and external ROM version for M16C/62P. Please specify the mark of the mask ROM version at the time of ROM order. Please ask separately marking of the flash memory version of M16C/62PT. Table 1.4 Product List (1) (M16C/62P) Type No. ROM capacity As of Nov. 2003 RAM capacity Package type M30622M6P-XXXFP (D) M30622M6P-XXXGP M30623M6P-XXXGP (D) 48K bytes (D) M30622M8P-XXXFP (D) 100P6S-A M30622M8P-XXXGP (D) 64K bytes (D) 100P6Q-A M30623M8P-XXXGP 100P6S-A 4K bytes 100P6Q-A 80P6S-A 4K bytes 80P6S-A 100P6S-A M30622MAP-XXXFP 96K bytes M30622MAP-XXXGP M30623MAP-XXXGP Remarks 5K bytes 100P6Q-A 80P6S-A (D) 100P6S-A M30620MCP-XXXFP M30620MCP-XXXGP 128K bytes 10K bytes 100P6Q-A M30621MCP-XXXGP (D) 80P6S-A M30622MEP-XXXFP (D) 100P6S-A M30622MEP-XXXGP M30623MEP-XXXGP (D) 192K bytes (D) M30622MGP-XXXFP (D) M30622MGP-XXXGP (D) M30623MGP-XXXGP (D) 12K bytes 100P6Q-A 128P6Q-A 100P6S-A 12K bytes 100P6Q-A 128P6Q-A 256K bytes M30624MGP-XXXFP 100P6S-A M30624MGP-XXXGP 100P6Q-A 20K bytes M30625MGP-XXXGP 128P6Q-A M30622MWP-XXXFP (D) M30622MWP-XXXGP (D) M30623MWP-XXXGP (D) 100P6S-A 16K bytes 128P6Q-A M30624MWP-XXXFP M30624MWP-XXXGP 100P6Q-A 100P6S-A 320K bytes 24K bytes 100P6Q-A M30625MWP-XXXGP 128P6Q-A M30626MWP-XXXFP 100P6S-A M30626MWP-XXXGP 31K bytes M30627MWP-XXXGP 128P6Q-A M30622MHP-XXXFP 100P6S-A M30622MHP-XXXGP 16K bytes M30623MHP-XXXGP 100P6S-A 384K bytes 24K bytes M30625MHP-XXXGP 100P6Q-A 128P6Q-A 100P6S-A M30626MHP-XXXFP 31K bytes M30626MHP-XXXGP 100P6Q-A 128P6Q-A M30627MHP-XXXGP (D): Under development (P): Under planning Rev.2.10 Nov. 07, 2003 page 7 100P6Q-A 128P6Q-A M30624MHP-XXXFP M30624MHP-XXXGP 100P6Q-A of 84 MASK ROM version 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.5 Product List (2) (M16C/62P) Type No. ROM capacity M30626MJP-XXXFP (P) M30626MJP-XXXGP (P) 512K bytes M30627MJP-XXXGP (P) As of Nov. 2003 ROM capacity 100P6S-A 31K bytes MASK ROM version 100P6S-A 64K+4K bytes 4K bytes (D) 100P6Q-A 80P6S-A M30620FCPFP 100P6S-A 128K+4K bytes M30620FCPGP M30621FCPGP 100P6Q-A 128P6Q-A M30622F8PFP M30622F8PGP M30623F8PGP Package type Remarks 10K bytes 100P6Q-A 80P6S-A (D) 100P6S-A M30624FGPFP 256K+4K bytes M30624FGPGP 20K bytes 100P6Q-A Flash memory version 128P6Q-A M30625FGPGP 100P6S-A M30626FHPFP 384K+4K bytes M30626FHPGP 31K bytes 100P6Q-A 128P6Q-A M30627FHPGP M30626FJPFP (P) M30626FJPGP (P) 512K+4K bytes M30627FJPGP (P) M30622SPFP (D) M30622SPGP (D) M30620SPFP (D) M30620SPGP (D): Under development (P): Under planning (D) Rev.2.10 Nov. 07, 2003 page 8 100P6S-A 31K bytes 100P6Q-A 128P6Q-A 100P6S-A 4K bytes 10K bytes 100P6Q-A 100P6S-A 100P6Q-A of 84 External ROM version 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.6 Product List (3) (T version (M16C/62PT)) Type No. ROM capacity RAM capacity As of Nov. 2003 Package type M3062CM6T-XXXFP (D) M3062CM6T-XXXGP (D) 48K bytes M3062EM6T-XXXGP (P) 80P6S-A M3062CM8T-XXXFP (D) 100P6S-A M3062CM8T-XXXGP (D) 64K bytes M3062EM8T-XXXGP (P) 80P6S-A M3062CMAT-XXXFP (D) 100P6S-A M3062CMAT-XXXGP (D) 96K bytes M3062EMAT-XXXGP (P) 80P6S-A M3062AMCT-XXXFP (D) 100P6S-A M3062AMCT-XXXGP (D) 128K bytes M3062BMCT-XXXGP (P) M3062CF8TGP (D) 64K bytes M3062AFCTFP (D) 100P6S-A M3062AFCTGP (D) 128K+4K bytes 10K bytes 100P6Q-A M3062BFCTGP (P) M3062JFHTFP (D) 80P6S-A 100P6S-A M3062JFHTGP (D) Remarks 100P6S-A 4K bytes 4K bytes 5K bytes 10K bytes 100P6Q-A 100P6Q-A MASK ROM version 100P6Q-A T Version (High reliability 85 C Version) 100P6Q-A 80P6S-A 4K bytes 384K+4K bytes 31K bytes 100P6Q-A Flash memory version 100P6Q-A (D): Under development (P): Under planning Table 1.7 Product List (4) (V version (M16C/62PT)) Type No. ROM capacity RAM capacity As of Nov. 2003 Package type M3062CM6V-XXXFP (P) M3062CM6V-XXXGP (P) 48K bytes M3062EM6V-XXXGP (P) 80P6S-A M3062CM8V-XXXFP (P) 100P6S-A M3062CM8V-XXXGP (P) 64K bytes M3062EM8V-XXXGP (P) 80P6S-A M3062CMAV-XXXFP (P) 100P6S-A M3062CMAV-XXXGP (P) 96K bytes M3062EMAV-XXXGP (P) 80P6S-A M3062AMCV-XXXFP (D) 100P6S-A M3062AMCV-XXXGP (D) 128K bytes M3062BMCV-XXXGP (P) 80P6S-A M3062AFCVFP (D) 100P6S-A M3062AFCVGP (D) 128K+4K bytes M3062BFCVGP (P) M3062JFHVFP (P) M3062JFHVGP (P) 100P6S-A 4K bytes 4K bytes 5K bytes 10K bytes 10K bytes 100P6Q-A 100P6Q-A 100P6Q-A 384K+4K bytes of 84 31K bytes MASK ROM version 100P6Q-A 100P6Q-A 80P6S-A (D): Under development (P): Under planning Rev.2.10 Nov. 07, 2003 page 9 Remarks 100P6S-A 100P6Q-A Flash memory version V Version (High reliability 125 C Version) 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Type No. M3062 6 MH P- XXX FP Package type: FP : Package GP : Package 100P6S-A 80P6Q-A, 100P6Q-A, 128P6Q-A ROM No. Omitted for flash memory version and external ROM version Classification P : M16C/62P T : T version (M16C/62PT) V : V version (M16C/62PT) ROM capacity: 6: 48K bytes 8: 64K bytes A: 96K bytes C: 128K bytes E: 192K bytes G: 256K bytes W: 320K bytes H: 384K bytes J: 512K bytes Memory type: M: Mask ROM version F: Flash memory version S: External ROM version Shows RAM capacity, pin count, etc Numeric : M16C/62P Alphabet : M16C/62PT M16C/62 Group M16C Family Figure 1.3 Type No., Memory Size, and Package Rev.2.10 Nov. 07, 2003 page 10 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.8 Product Code of Flash Memory version and External ROM version for M16C/62P Internal ROM (user ROM area without block 1) product code Package Program and erase endurance Internal ROM (block A, block 1) Temperature Program and range erase endurance D7 Flash memory version 100 1,000 10,000 0C to 60C U3 U7 D3 D5 100 100 1,000 10,000 Lead-free U9 External ROM version 100 Lead-included D9 U5 Operating ambient temperature -40C to 85C D3 D5 Temperature range 0C to 60C -40C to 85C -40C to 85C -20C to 85C -20C to 85C 0C to 60C -40C to 85C -20C to 85C -40C to 85C -40C to 85C -20C to 85C -20C to 85C -40C to 85C Lead-included -20C to 85C -40C to 85C U3 U5 -20C to 85C Lead-free -20C to 85C M1 6 C M3 0 6 2 6 FHPF P B D5 XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package) Chip version and product code. B : Shows chip version. Henceforth, whenever it changes a version, it continues with B, C, and D. D5 : Shows Product code. (See table 1.8 Product Code.) Data code seven digits The product without marking of chip version of the flash memory version and the ROM external version corresponds to the chip version "A". Figure 1.4 Marking Diagram of Flash Memory version and External ROM version for M16C/62P (Top View) Rev.2.10 Nov. 07, 2003 page 11 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 1.5 Pin Configuration Figures 1.5 to 1.8 show the pin configurations (top view). P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 PIN CONFIGURATION (top view) 102 101 100 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 64 63 62 61 60 59 58 57 56 55 54 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 M16C/62 Group (M16C/62P) 128 2 3 4 5 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P12_5 P12_6 P12_7 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P13_0 P13_1 P13_2 P13_3 P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P13_4 P13_5 P13_6 P13_7 P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 VSS 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 P14_1 P14_0 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT(1) P6_7/TXD1/SDA1 VCC1 P6_6/RXD1/SCL1 1 NOTES: 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 1. P7_0 and P7_1 are N channel open-drain output pins. Package: 128P6Q-A Figure 1.5 Pin Configuration (Top View) Rev.2.10 Nov. 07, 2003 page 12 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 M16C/62 Group (M16C/62P, M16C/62PT) 100 P9_6/ANEX1/SOUT4 1 2 3 4 5 6 7 8 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN(1) P7_0/TXD2/SDA2/TA0OUT(1) P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 Package: 100P6S-A NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. Figure 1.6 Pin Configuration (Top View) Rev.2.10 Nov. 07, 2003 page 13 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 PIN CONFIGURATION (top view) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 M16C/62 Group (M16C/62P, M16C/62PT) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 100 26 2 3 4 5 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. Figure 1.7 Pin Configuration (Top View) Rev.2.10 Nov. 07, 2003 page 14 of 84 P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT 1 RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 Package: 100P6Q-A 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) P4_2 P3_7 P4_0 P4_1 P3_5 P3_6 P3_4 P3_0 P3_1 P3_2 P3_3 P2_4/AN2_4 P2_5/AN2_5 P2_6/AN2_6 P2_7/AN2_7 P2_2/AN2_2 P2_3/AN2_3 P0_7/AN0_7 P2_0/AN2_0 P2_1/AN2_1 PIN CONFIGURATION (top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 61 40 P4_3 62 39 63 38 64 37 65 36 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC 66 35 67 34 68 33 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_6/TA3OUT 32 69 M16C/62 Group (M16C/62P, M16C/62PT) 70 71 72 31 30 29 73 28 74 27 75 26 76 25 77 24 78 23 P9_7/ADTRG/SIN4 79 22 P9_6/ANEX1/SOUT4 80 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. Figure 1.8 Pin Configuration (Top View) Rev.2.10 Nov. 07, 2003 page 15 of 84 P7_7/TA3IN 9 10 11 12 13 14 15 16 17 18 19 20 P8_0/TA4OUT 8 P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN 7 XIN VCC1 P8_5/NMI 6 VSS 5 RESET XOUT 4 P9_0/TB0IN/CLK3 CNVSS(BYTE) P8_7/XCIN 3 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 2 P8_6/XCOUT 21 1 Package: 80P6S-A 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) 1.6 Pin Description Table 1.9 Pin Description (100-pin and 128-pin Version) (1) Signal name Pin name I/O type Power supply Description Power supply input VCC1, VCC2 VSS I - Analog power supply input AVCC AVSS I VCC1 Applies the power supply for the A-D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. Reset input CNVSS RESET CNVSS I I VCC1 VCC1 The microcomputer is in a reset state when applying "L" to the this pin. Switches processor mode. Connect this pin to VSS to when after a reset to start Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 VCC2.(2) ____________ up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. External data bus width select input Bus control pins(4) BYTE I VCC1 Switches the data bus in external memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. D0 to D7 I/O VCC2 D8 to D15 I/O VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. A0 to A19 A0/D0 to O I/O VCC2 VCC2 Output address bits (A0 to A19). Input and output data (D0 to D7) and output address bits (A0 to A7) by time- A7/D7 A1/D0 to I/O VCC2 sharing when external 8-bit data bus are set as the multiplexed bus. Input and output data (D0 to D7) and output address bits (A8 to A15) by time- VCC2 sharing when external 16-bit data bus are set as the multiplexed bus. ________ ________ ________ ________ Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an A8/D7 ______ ______ CS0 to CS3 O external space. ________ ______ WRL/WR WRH/BHE O VCC2 _________ ________ _____ ________ _________ ________ _________ RD ______ ________ _____ ________ _________ _______ ______ Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program. _____ * WRL, WRH and RD are selected ________ The WRL signal becomes "L" by writing data to an even address in an external memory space. _________ The WRH signal becomes "L" by writing data to an odd address in an external memory space. _____ The RD pin signal becomes "L" by reading data in an external memory space. ______ ________ _____ * WR, BHE and RD are selected ______ The WR signal becomes "L" by writing data in an external memory space. _____ The RD signal becomes "L" by reading data in an external memory space. ________ The BHE signal becomes "L" by accessing an odd address. ______ ________ ALE O VCC2 I O VCC2 VCC2 While the HOLD pin is held "L", the microcomputer is placed in a hold state. _________ In a hold state, HLDA outputs a "L" signal. I VCC2 While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state. __________ HOLD HLDA __________ __________ ________ RDY I : Input O : Output _____ Select WR, BHE and RD for an external 8-bit data bus. ALE is a signal to latch the address. ________ I/O : Input and output Power supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be interfaced using the different voltage as VCC1. NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 2.7 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 VCC2. 3. When use VCC1 VCC2, contacts due to some points or restrictions to be checked. 4. This pin function is not in M16C/62PT. Rev.2.10 Nov. 07, 2003 page 16 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.10 Pin Description (100-pin and 128-pin Version) (2) Signal name I O Power supply VCC1 VCC1 XCIN I VCC1 XCOUT O VCC1 Pin name I/O type Main clock input Main clock output XIN XOUT Sub clock input Sub clock output BCLK output (2) Clock output BCLK CLKOUT ______ ________ I VCC1 Input pins for the key input interrupt I/O VCC1 TA4OUT TA0IN to These are timer A0 to timer A4 I/O pins. (except the output of TAOUT for the Nchannel open drain output.) I VCC1 These are timer A0 to timer A4 input pins. TA4IN ZP I VCC1 I VCC1 Input pin for the Z-phase. These are timer B0 to timer B5 input pins. O VCC1 These are Three-phase motor control output pins. CTS0 to CTS2 ________ ________ RTS0 to RTS2 I O VCC1 VCC1 These are send control input pins. CLK0 to CLK4 RXD0 to RXD2 I/O I VCC1 VCC1 SIN3, SIN4 TXD0 to I O VCC1 VCC1 TXD2 SOUT3, SOUT4 O VCC1 CLKS1 SDA0 to SDA2 O I/O VCC1 VCC1 SCL0 to SCL2 I/O VCC1 TB0IN to TB5IN __________ O : Output The clock of the same cycle as fC, f8, or f32 is outputted. ______ Input pins for the INT interrupt _______ Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. ______ TA0OUT to __ I : Input leave XCOUT open. Outputs the BCLK signal. VCC1 VCC1 ________ __ Three-phase motor U, U, V, V, __ control output W, W I2C mode I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and I I _____ Serial I/O crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open. VCC2 VCC2 Key input interrupt KI0 to KI3 Timer B I/O pins for the main clock generation circuit. Connect a ceramic resonator or O O INT interrupt input INT0 to INT5 _______ _______ NMI interrupt input NMI input Timer A Description ________ These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data input pins. These are serial data output pins. (except TXD2 for the N-channel open drain output.) These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (except SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (except SCL2 for the N-channel open drain output.) I/O : Input and output NOTES: 1. When use VCC1 VCC2, contacts due to some points or restrictions to be checked. 2. This pin function is not in M16C/62PT. 3. Ask the oscillator maker the oscillation characteristic. Rev.2.10 Nov. 07, 2003 page 17 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.11 Pin Description (100-pin and 128-pin Version) (3) Signal name Pin name Reference voltage VREF input A-D converter AN0 to AN7, AN0_0 to AN0_7, I/O port Description Applies the reference voltage for the A-D converter and D-A converter. I VCC1 Analog input pins for the A-D converter I VCC1 This is an A-D trigger input pin. ANEX0 I/O VCC1 This is the extended analog input pin for the A-D converter, and is the output in external op-amp connection mode. ANEX1 DA0, DA1 I O VCC1 VCC1 This is the extended analog input pin for the A-D converter. This is the Input pin for the D-A converter. P0_0 to P0_7, P1_0 to P1_7, I/O VCC2 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a AN2_0 to AN2_7 ___________ ADTRG D-A converter I/O type Power supply VCC1 I P2_0 to P2_7, P3_0 to P3_7, pull-up or for no pull-up in 4-bit unit by program. P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7 (2), P13_0 to P13_7 (2) P6_0 to P6_7, P7_0 to P7_7, I/O VCC1 8-bit I/O ports having equivalent functions to P0. (except P7_0 and P7_1 for the N-channel open drain output.) I/O VCC1 I/O ports having equivalent functions to P0. I VCC1 Input pin for the NMI interrupt. P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7 (2) P8_0 to P8_4, P8_6, P8_7, P14_0, P14_1(2) _______ Input port P8_5 Pin states can be read by the P8_5 bit in the P8 register. I : Input O : Output I/O : Input and output NOTES: 1. When use VCC1 VCC2, contacts due to some points or restrictions to be checked. 2. Ports P11 to P14 are provided in the 128-pin version only. Rev.2.10 Nov. 07, 2003 page 18 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.12 Pin Description (80-pin Version) (1) Signal name Pin name I/O type Power supply Description Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (2) Power supply input VCC1, I - Analog power VSS AVCC, I VCC1 Applies the power supply for the A-D converter. Connect the AVCC pin to supply input Reset input AVSS ____________ RESET I VCC1 VCC1. Connect the AVSS pin to VSS. The microcomputer is in a reset state when applying "L" to the this pin. CNVSS CNVSS (BYTE) I VCC1 Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing is performed within the microcomputer. Main clock input Main clock output XIN XOUT I O VCC1 VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input Sub clock input XCIN I VCC1 the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between Sub clock output XCOUT O VCC1 XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. ______ Clock output INT interrupt input ________ CLKOUT ________ INT0 to INT2 O I VCC2 VCC1 The clock of the same cycle as fC, f8, or f32 is outputted. ______ Input pins for the INT interrupt _______ _______ I I VCC1 VCC1 Input pin for the NMI interrupt. Input pins for the key input interrupt I/O VCC1 These are timer A0, timer A3 and Timer A4 I/O pins. (except the output of _______ NMI interrupt input NMI ______ ______ Key input interrupt KI0 to KI3 input Timer A TA0OUT, TA3OUT, TA4OUT TA0IN, TAOUT for the N-channel open drain output.) I VCC1 These are timer A0, timer A3 and Timer A4 input pins. Timer B ZP TB0IN, I I VCC1 VCC1 Input pin for the Z-phase. These are timer B0, timer B2 to timer B5 input pins. Serial I/O TB2IN to TB5IN _________ _________ CTS0, CTS2 I VCC1 These are send control input pins. O I/O VCC1 VCC1 These are receive control output pins. These are transfer clock I/O pins. CLK3, CLK4 RXD0 to RXD2 I VCC1 These are serial data input pins. SIN4 TXD0 to TXD4 I O VCC1 VCC1 These are serial data input pins. These are serial data output pins. (except TXD2 for the N-channel open drain SOUT3, SOUT4 O VCC1 output.) These are serial data output pins. CLKS1 SDA0 to SDA2 O I/O VCC1 VCC1 This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (except SDA2 for the N-channel open drain VCC1 output.) These are transfer clock I/O pins. (except SCL2 for the N-channel open drain TA3IN, TA4IN _________ _________ RTS0, RTS2 CLK0, CLK1, I2C mode SCL0 to SCL2 I/O output.) I : Input O : Output I/O : Input and output NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin. 3. Ask the oscillator maker the oscillation characteristic. Rev.2.10 Nov. 07, 2003 page 19 of 84 1. Overview M16C/62 Group (M16C/62P, M16C/62PT) Table 1.13 Pin Description (80-pin Version) (2) Reference voltage VREF I Power supply VCC1 input A-D converter I VCC1 Analog input pins for the A-D converter I I/O VCC1 VCC1 This is an A-D trigger input pin. I VCC1 O I/O VCC1 VCC1 This is the extended analog input pin for the A-D converter. This is the Input pin for the D-A converter Signal name Pin name AN0 to AN7, I/O type Description Applies the reference voltage for the A-D converter and D-A converter. AN0_0 to AN0_7, AN2_0 to AN2_7 ___________ ADTRG ANEX0 ANEX1 D-A converter I/O port DA0, DA1 P0_0 to P0_7, P2_0 to P2_7, P3_0 to P3_7, 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. P5_0 to P5_7, P6_0 to P6_7, P10_0 to P10_7 P8_0 to P8_4, This is the extended analog input pin for the A-D converter, and is the output in external op-amp connection mode. I/O VCC1 I/O ports having equivalent functions to P0. I/O VCC1 I/O ports having equivalent functions to P0. (except P7_0 and P7_1 for the N-channel open drain output.) I VCC1 Input pin for the NMI interrupt. P8_6, P8_7, P9_0, P9_2 to P9_7 P4_0 to P4_3, P7_0, P7_1, P7_6, P7_7 _______ Input port P8_5 Pin states can be read by the P8_5 bit in the P8 register. I : Input O : Output I/O : Input and output NOTES: 1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to "1" (input mode), and set the output data to "0" ("L") using the program. Rev.2.10 Nov. 07, 2003 page 20 of 84 2. Central Processing Unit (CPU) M16C/62 Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R0H(R0's high bits) R0L(R0's low bits) R3 R1H(R1's high bits)R1L(R1's low bits) R2 Data registers (1) R3 A0 Address registers (1) A1 FB b19 b15 Frame base registers (1) b0 INTBH INTBL Interrupt table register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC Program counter b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG AA AAAAAAA AA A AA AA A AA AA AA AA AAAAAAAAAAAAAAAA AAAAA b15 b8 IPL b7 U I Flag register b0 O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area NOTES: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0. 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev.2.10 Nov. 07, 2003 page 21 of 84 M16C/62 Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate. Rev.2.10 Nov. 07, 2003 page 22 of 84 3. Memory M16C/62 Group (M16C/62P, M16C/62PT) 3. Memory Figure 3.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and microprocessor modes cannot be used. 00000h SFR 00400h Internal RAM XXXXXh Reserved area (1) FFE00h 0F000h AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Internal ROM (data area) (3) 0FFFFh Special page vector table 10000h Internal RAM Size Address XXXXXh Internal ROM Size (3) Address YYYYYh 4K bytes 013FFh 48K bytes F4000h 5K bytes 017FFh 64K bytes F0000h 10K bytes 02BFFh 96K bytes E8000h 12K bytes 033FFh 128K bytes E0000h 16K bytes 043FFh 192K bytes D0000h 20K bytes 053FFh 256K bytes C0000h 24K bytes 063FFh 320K bytes B0000h 31K bytes 07FFFh 384K bytes A0000h 512K bytes 80000h External area 27000h Reserved area Reserved area (2) YYYYYh Internal ROM (program area) FFFFFh Rev.2.10 Nov. 07, 2003 page 23 of 84 Undefined instruction Overflow External area 80000h NOTES: 1. During memory expansion and microprocessor modes, can not be used. 2. In memory expansion mode, can not be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is "1" and the PM13 bit in the PM1 register is "1". Figure 3.1 Memory Map FFFDCh 28000h FFFFFh BRK instruction Address match Single step Watchdog timer DBC NMI Reset 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) 4. SFR Register Address Symbol After reset 0000h 0001h 0002h 0003h 0004h Processor mode register 0 (2) PM0 0005h Processor mode register 1 System clock control register 0 System clock control register 1 Chip select control register (6) Address match interrupt enable register Protect register Data bank register (6) Oscillation stop detection register (3) PM1 CM0 CM1 CSR AIER PRCR DBR CM2 00001000b 01001000b 00100000b 00000001b XXXXXX00b XX000000b 00h 0000X000b Watchdog timer start register Watchdog timer control register Address match interrupt register 0 WDTS WDC RMAD0 XXh 00XXXXXXb (4) 00h 00h X0h Address match interrupt register 1 RMAD1 00h 00h X0h Voltage detection register 1 (5, 6) Voltage detection register 2 (5, 6) Chip select expansion control register (6) PLL control register 0 VCR1 VCR2 CSE PLC0 00001000b 00h 00h 0001X010b Processor mode register 2 Voltage down detection interrupt register (6) DMA0 source pointer PM2 D4INT SAR0 XXX00000b 00h XXh XXh XXh DMA0 destination pointer DAR0 XXh XXh XXh DMA0 transfer counter TCR0 XXh XXh DMA0 control register DM0CON 00000X00b DMA1 source pointer SAR1 XXh XXh XXh DMA1 destination pointer DAR1 XXh XXh XXh DMA1 transfer counter TCR1 XXh XXh DMA1 control register DM1CON 00000X00b 00000000b(CNVSS pin is "L") 00000011b(CNVSS pin is "H") 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh NOTES : 1. The blank areas are reserved and cannot be accessed by users. 2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. 3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. 4. The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1" (RAM retention limit detection circuit enable 5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 6. This register cannot be used by M16C/62PT. X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 24 of 84 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) Register Address Symbol After reset INT3IC TB5IC XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b 0040h 0041h 0042h 0043h 0045h INT3 interrupt control register Timer B5 interrupt control register 0046h Timer B4 interrupt control register, UART1 BUS collision detection interrupt control register 0047h Timer B3 interrupt control register, UART0 BUS collision detection interrupt control register TB3IC, U0BCNIC 0048h SI/O4 interrupt control register (S4IC), INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC 0044h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh NOTES : 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 25 of 84 TB4IC, U1BCNIC 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) Register Address Symbol After reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h Flash identification register (2) Flash memory control register 1 (2) FIDR FMR1 XXXXXX00b 0X00XX0Xb Flash memory control register 0 (2) Address match interrupt register 2 FMR0 RMAD2 01BBh Address match interrupt enable register 2 01BCh Address match interrupt register 3 AIER2 RMAD3 XX000001b 00h 00h X0h XXXXXX00b 00h 00h X0h Peripheral clock select register PCLKR 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BDh 01BEh 01BFh 00C0h to 02AFh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh NOTES : 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 26 of 84 00000011b 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) Address 0340h Register Symbol After reset Timer B3, 4, 5 count start flag TBSR 000XXXXXb Timer A1-1 register TA11 Timer A2-1 register TA21 Timer A4-1 register TA41 Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter INVC0 INVC1 IDB0 IDB1 DTT ICTB2 XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h XXh XXh Timer B3 register TB3 Timer B4 register TB4 Timer B5 register TB5 Timer B3 mode register Timer B4 mode register Timer B5 mode register Interrupt cause select register 2 Interrupt cause select register SI/O3 transmit/receive register TB3MR TB4MR TB5MR IFSR2A IFSR S3TRR 00XX0000b 00XX0000b 00XX0000b 00XXXXXXb 00h XXh SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register S3C S3BRG S4TRR 01000000b XXh XXh SI/O4 control register SI/O4 bit rate generator S4C S4BRG 01000000b XXh UART0 special mode register 4 UART0 special mode register 3 UART0 special mode register 2 UART0 special mode register UART1 special mode register 4 UART1 special mode register 3 UART1 special mode register 2 UART1 special mode register UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register U2C0 U2C1 U2RB 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h XXh XXh XXh XXh XXh XXh 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh NOTES : 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 27 of 84 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Register Symbol TABSR CPSRF ONSF TRGSR UDF After reset 00h 0XXXXXXXb 00h 00h 00h (2) Timer A0 register TA0 Timer A1 register TA1 Timer A2 register TA2 Timer A3 register TA3 Timer A4 register TA4 Timer B0 register TB0 Timer B1 register TB1 Timer B2 register TB2 Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX0000b 00XX0000b 00XX0000b XXXXXX00b 03A0h UART0 transmit/receive mode register 03A1h UART0 bit rate generator UART0 transmit buffer register U0MR U0BRG U0TB Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03ADh UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 03AEh UART1 receive buffer register U1C0 U1C1 U1RB UART transmit/receive control register 2 UCON 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh X0000000b DMA0 request cause select register DM0SL 00h DMA1 request cause select register DM1SL 00h CRC data register CRCD CRC input register CRCIN XXh XXh XXh 03A2h 03A3h 03A4h 03A5h UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 03A6h UART0 receive buffer register U0C0 U0C1 U0RB 03A7h 03A8h UART1 transmit/receive mode register 03A9h UART1 bit rate generator UART1 transmit buffer register 03AAh U1MR U1BRG U1TB 03ABh 03ACh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh NOTES : 1.The blank areas are reserved and cannot be accessed by users. 2. Bits 7 to 5 in the Up-down flag are "0" by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 28 of 84 4. SFR M16C/62 Group (M16C/62P, M16C/62PT) Address 03C0h Register A-D register 0 Symbol AD0 A-D register 1 AD1 A-D register 2 AD2 A-D register 3 AD3 A-D register 4 AD4 A-D register 5 AD5 A-D register 6 AD6 A-D register 7 AD7 A-D control register 2 ADCON2 00h A-D control register 0 A-D control register 1 D-A register 0 ADCON0 ADCON1 DA0 00000XXXb 00h 00h D-A register 1 DA1 00h D-A control register DACON 00h Port P14 control register Pull-up control register 3 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register Port P12 register Port P13 register Port P12 direction register Port P13 direction register Pull-up control register 0 Pull-up control register 1 PC14 PUR3 P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 PUR0 PUR1 XX00XXXXb 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh XXh 00h 00h XXh XXh 00h 00h 00h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh After reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 00000000b 00000010b 03FEh 03FFh Pull-up control register 2 Port control register PUR2 PCR 00h 00h NOTES : 1. The blank areas are reserved and cannot be accessed by users. 2. At hardware reset 1 or hardware reset 2, the register is as follows: * "00000000b" where "L" is inputted to the CNVSS pin * "00000010b" where "H" is inputted to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: * "00000000b" where the PM01 to PM00 bits in the PM0 register are "00b" (single-chip mode) * "00000010b" where the PM01 to PM00 bits in the PM0 register are "01b" (memory expansion mode) or "11b" (microprocessor mode) X : Nothing is mapped to this bit Rev.2.10 Nov. 07, 2003 page 29 of 84 (2) M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) 5. Electrical Characteristics 5.1 Electrical Characteristics (M16C/62P) Table 5.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit VCC1, VCC2 Supply voltage VCC1=AVCC -0.3 to 6.5 V VCC2 Supply voltage VCC2 -0.3 to VCC1+0.1 V AVCC Analog supply voltage VCC1=AVCC -0.3 to 6.5 V RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN -0.3 to VCC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 -0.3 to VCC2+0.3 (1) V -0.3 to 6.5 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XOUT -0.3 to VCC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 -0.3 to VCC2+0.3 (1) V Input voltage VI P7_0, P7_1 Output voltage VO P7_0, P7_1 Pd Power dissipation Topr Operating ambient temperature -40 C < Topr 85 C When the microcomputer is operating Flash program erase Tstg Storage temperature -0.3 to 6.5 V 300 mW -20 to 85 / -40 to 85 C 0 to 6 0 -65 to 150 NOTES: 1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 30 of 84 C 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.2 Recommended Operating Conditions (1) (1) Parameter Symbol VCC1, VCC2 Supply voltage(VCC1VCC2) AVcc Analog supply voltage f(ripple)(2) VP-P(ripple)(2) Power supply ripple allowable frequency Min. 2.7 Standard Typ. Max. 5.0 5.5 V 10 MHz (VCC1=5V) (VCC1=3V) 0.5 0.3 V V (VCC1=5V) (VCC1=3V) 0.3 0.3 V/ms V/ms VCC1 Power supply ripple allowable amplitude voltage VCC(|V / T|) Power supply ripple rising / falling gradient (2) Unit V V/ms SVCC(2) Power supply rising gradient Vss Supply voltage 0 V AVss Analog supply voltage HIGH input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0 0.05 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor modes) VIH P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE P7_0 , P7_1 LOW input voltage VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) 0.8VCC2 VCC2 V V 0.8VCC2 VCC2 V 0.5VCC2 VCC2 V 0.8VCC1 VCC1 V 0.8VCC1 6.5 V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 0 0.2VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0 0.2VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor modes) 0 0.16VCC2 V 0 0.2VCC1 V -10.0 mA -5.0 mA 10.0 mA 5.0 mA P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE HIGH peak output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, current P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, HIGH average P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, output current P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, LOW peak output P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, current P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, LOW average P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, output current P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2. SVCC indicates the minimum time gradient until VCC1 reaches 2.7V. f(ripple) V SVCC Vp-p(ripple) VCC1 0V t 3. The mean output current is the mean value within 100ms. 4. The total IOL (peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be -40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for ports P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH (peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be -40mA max. 5. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 31 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.3 Recommended Operating Conditions (2) (1) Symbol Parameter f (XIN) Main clock input oscillation frequency f (XCIN) f (Ring) Ring oscillation frequency (2) Min. VCC1=3.0 to 5.5V VCC1=2.7 to 3.0V Standard Typ. Max. 0 0 Sub-clock oscillation frequency 32.768 0.5 f (PLL) PLL clock oscillation frequency (2) f (BCLK) CPU operation clock tSU(PLL) PLL frequency synthesizer stabilization wait time 1 10.0 0.0 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA 2.7 3.0 VCC1[V] (main clock: no division) Rev.2.10 Nov. 07, 2003 page 32 of 84 5.5 MHz MHz 24 VCC1=2.7 to 3.0V 10 46.67 X VCC1116 24 MHz 20 ms ms VCC1=5.0V VCC1=3.0V f(PLL) operating maximum frequency [MHz] f(XIN) operating maximum frequency [MHz] 16.0 MHz MHz kHz 10 50 NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2. Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage. 20 x VCC1-44MHz Unit VCC1=3.0 to 5.5V 0 Main clock input oscillation frequency 16 20 X VCC1-44 50 2 AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA PLL clock oscillation frequency 46.67 x VCC1-116MHz 24.0 10.0 0.0 2.7 3.0 VCC1[V] (PLL clock oscillation) 5.5 MHz 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.4 A-D Conversion Characteristics (1) Symbol - Parameter Resolution Integral nonlinearity error INL Measuring condition Bits 3 LSB External operation amp connection mode AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0, ANEX1 input 7 LSB 5 LSB External operation amp connection mode VREF =VCC1=3.3V 7 LSB 10 bit VREF= VCC1= 5V 10 bit VREF= VCC1= 3.3V AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0, ANEX1 input 2 LSB AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0, ANEX1 input 3 LSB External operation amp connection mode 7 LSB AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0, ANEX1 input 5 LSB External operation amp connection mode 7 LSB 2 LSB 1 3 3 40 k LSB LSB LSB k VREF =VCC1=3.3V 8 bit - DNL - - RLADDER tCONV Tolerance level impedance Differential non-linearity error Offset error Gain error Ladder resistance Conversion time(10bit), Sample & hold function available tCONV Conversion time(8bit), Sample & hold function available tSAMP VREF Sampling time Reference voltage VI A Analog input voltage Unit 10 VREF= VCC1= 5V 8 bit Absolute accuracy Standard Typ. Max. VREF =VCC1 VREF= VCC1= 3.3V - Min. 3 VREF =VCC1 VREF =VCC1=5V, oAD=12MHz 10 2.75 VREF =VCC1=5V, oAD=12MHz 2.33 s s 0.25 2.0 VCC1 s V 0 VREF V NOTES: 1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. 3. AD operation clock frequency (oAD frequency) must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and oAD frequency into 10 MHz or less. 4. A case without sample & hold function turn oAD frequency into 250 kHz or more in addition to a limit of Note 3. A case with sample & hold function turn oAD frequency into 1MHz or more in addition to a limit of Note 3. Table 5.5 D-A Conversion Characteristics (1) Symbol - - tsu RO IVREF Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Standard Min. Typ. Max. 4 (Note 2) 10 Unit 8 1.0 3 20 Bits % s k 1.5 mA NOTES: 1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2. This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "00h". The A-D converter's ladder resistance is not included. Also, when D-A register contents are not "00h", the current IVREF always flows even though Vref may have been set to be unconnected by the A-D control register. Rev.2.10 Nov. 07, 2003 page 33 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.6 Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3, U5) Standard Symbol Parameter Unit Min. Typ. Max. cycle - Program and erase endurance (3) - Word program time (VCC1=5.0V, Topr=25C) 25 200 s - Lock bit program time 25 200 s - Block erase time (VCC1=5.0V, Topr=25 C) 4K bytes block 0.3 4 s 8K bytes block 0.3 4 s 32K bytes block 0.5 4 s 64K bytes block 0.8 4 s tPS - Erase all unlocked blocks time 100 (2) Flash memory circuit stabilization wait time Data hold time (5) 4Xn s 15 s 10 year Table 5.7 Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (D7, D9, U7, U7) (Block A and Block 1 (7)) Standard Symbol Parameter Min. Typ. Max. Unit - Program and erase endurance (3, 8, 9) - Word program time (VCC1=5.0V, Topr=25C) 25 s - Lock bit program time 25 s - Block erase time (VCC1=5.0V, Topr=25 C) 0.3 s tPS - 10,000 (4) 4K bytes block cycle Flash memory circuit stabilization wait time 15 10 Data hold time (5) s year NOTES : 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 C unless otherwise specified. 2. n denotes the number of block erases. 3. Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times. For example, if a 4K bytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Topr = -40 to 85 C (D3, D7, U3, U7) / -20 to 85 C (D5, D9, U5, U9). 6. Referenced to VCC1 = 2.7 to 5.5V at Topr = -20 to 85 C (D9, U9) / -40 to 85 C (D7, U7) unless otherwise specified. 7. Table 5.7 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.6. 8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary. Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the total number of times erasure is used. 9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command at least three times until erase error disappears. 10. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 5.8 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60oC) Flash program, erase voltage VCC1 = 3.3 V 0.3 V or 5.0 V 0.5 V Rev.2.10 Nov. 07, 2003 page 34 of 84 Flash read operation voltage VCC1=2.7 to 5.5 V 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.9 Low Voltage Detection Circuit Electrical Characteristics (1) Symbol Measuring condition Parameter Min. Standard Typ. Max. Unit Vdet4 Voltage down detection voltage (1) 3 .3 3 .8 4.4 V Vdet3 Reset level detection voltage (1, 2) 2 .2 2 .8 3.6 V Vdet3s Low voltage reset retention voltage Vdet3r Low voltage reset release voltage 2 .2 2 .9 4.0 V Vdet2 RAM retention limit detection voltage (1) 1.4 2 .0 2.7 V VCC1=0.8 to 5.5V (3) V 0 .8 NOTES: 1. Vdet4 > Vdet3 > Vdet2. 2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the operation at f(BCLK) 10MHz is guaranteed. 3. Vdet3r > Vdet3 is not guaranteed. Table 5.10 Power Supply Circuit Timing Characteristics Symbol Measuring condition Parameter td(P-R) Time for internal power supply stabilization during powering-on td(R-S) STOP release time td(W-S) Low power dissipation mode wait mode release time td(M-L) Time for internal power supply stabilization when main clock oscillation starts td(S-R) Hardware reset 2 release wait time td(E-A) Low voltage detection circuit operation start time Standard Typ. VCC1=2.7 to 5.5V VCC1=Vdet3r to 5.5V VCC1=2.7 to 5.5V Vdet3r VCC1 td(S-R) Interrupt for stop mode release CPU clock td(R-S) of 84 Max. 2 NOTES: 1. When VCC1 = 5V. Rev.2.10 Nov. 07, 2003 page 35 Min. 6 (1) Unit ms 150 s 150 s 50 s 20 ms 20 s 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Table 5.11 Electrical Characteristics (1) Symbol VOH VOH HIGH output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, voltage P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 HIGH output voltage XOUT HIGH output voltage VOL VOL XCOUT LOW output voltage Hysteresis VT+-VT- XCOUT Max. VCC1 VCC2 IOH=-200A VCC1-0.3 VCC1 IOH=-200A (2) VCC2-0.3 VCC2 HIGHPOWER IOH=-1mA VCC1-2.0 VCC1 LOWPOWER IOH=-0.5mA VCC1-2.0 HIGHPOWER With no load applied 2 .5 LOWPOWER With no load applied 1 .6 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 LOW output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 XOUT Standard Typ. VCC2-2.0 LOW output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, voltage P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 LOW output voltage IOH=-5mA Min. VCC1-2.0 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 HIGH output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, voltage P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 VOH VOL Measuring condition Parameter Unit V IOH=-5mA (2) V VCC1 V V IOL=5mA 2.0 IOL=5mA (2) 2.0 IOL=200A 0.45 V V IOL=200A 0.45 (2) HIGHPOWER IOL=1mA 2.0 LOWPOWER IOL=0.5mA 2.0 HIGHPOWER With no load applied 0 LOWPOWER With no load applied 0 HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 TO SDA2, CLK0 to CLK4,TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3, SIN4 V V 0 .2 1.0 V 0.2 2.5 V 0.2 0.8 V VT+-VT- Hysteresis VT+-VT- Hysteresis XIN HIGH input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=5V 5.0 A P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=0V -5.0 A IIH LOW input current IIL RPULLUP Pull-up resistance RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, VI=0V P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 RfXIN Feedback resistance XIN RfXCIN Feedback resistance XCIN VRAM RAM retention voltage 30 50 1.5 15 At stop mode 2 .0 NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=24MHz unless otherwise specified. 2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on the VCC2 port side. 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 36 of 84 170 k M M V 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Table 5.12 Electrical Characteristics (2) (1) Symbol Measuring condition Parameter In single-chip mode, the output pins are open and other pins are VSS Standard Typ. Max. Unit Mask ROM f(BCLK)=24MHz, No division, PLL operation No division, Ring oscillation Flash memory f(BCLK)=24MHz, No division, PLL operation Flash memory Program f(BCLK)=10MHz, VCC1=5.0V 15 mA Flash memory Erase f(BCLK)=10MHz, VCC1=5.0V 25 mA Mask ROM f(XCIN)=32kHz, Low power dissipation mode, ROM (3) 25 A 25 A 420 A Ring oscillation, Wait mode 50 A f(BCLK)=32kHz, Wait mode (2), 7.5 A 2.0 A No division, Ring oscillation ICC Min. Power supply current (VCC1=4.0 to 5.5V) Flash memory Mask ROM Flash memory f(BCLK)=32kHz, Low power dissipation mode, RAM (3) f(BCLK)=32kHz Low power dissipation mode, Flash memory (3) 14 20 1 18 mA mA 27 1 .8 mA mA Oscillation capacity High f(BCLK)=32kHz, Wait mode (2), Oscillation capacity Low Stop mode, Topr=25C 0.8 3.0 A Idet4 Voltage down detection dissipation current 0.7 4 A Idet3 Reset area detection dissipation current (4) 1.2 8 A Idet2 RAM retention limit detection dissipation current (4) 1.1 6 A (4) NOTES: 1. Referenced to VCC1=VCC2= 4.2 to 5.5V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=24MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists. 4. Idet is dissipation current when the following bit is set to "1" (detection circuit enabled). Idet4: VC27 bit of VCR2 register Idet3: VC26 bit of VCR2 register Idet2: VC25 bit of VCR2 register Rev.2.10 Nov. 07, 2003 page 37 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.13 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. Unit ns 62.5 25 25 15 15 ns ns ns ns Table 5.14 Memory Expansion Mode and Microprocessor Mode Symbol Parameter tac1(RD-DB) Data input access time (for setting with no wait) tac2(RD-DB) Data input access time (for setting with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) Standard Min. Max. (Note 1) (Note 2) (Note 3) 40 Unit ns ns ns 40 ns ns ns 0 ns 0 ns 0 ns 30 NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 45 [ns] 2. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 45 f(BCLK) [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 45 f(BCLK) [ns] Rev.2.10 Nov. 07, 2003 page 38 of 84 n is "2" for 2-wait setting, "3" for 3-wait setting. 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.15 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 5.16 Timer A Input (Gating Input in Timer Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.17 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter Standard Max. Min. Unit TAiIN input cycle time 200 ns TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 ns ns Table 5.18 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Max. Min. 100 100 Unit ns ns Table 5.19 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) Symbol Parameter tc(UP) TAiOUT input cycle time tw(UPH) TAiOUT input HIGH pulse width tw(UPL) TAiOUT input LOW pulse width tsu(UP-TIN) TAiOUT input setup time TAiOUT input hold time th(TIN-UP) Standard Min. Max. 2000 1000 Unit ns 1000 400 ns ns ns 400 ns Table 5.20 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time Rev.2.10 Nov. 07, 2003 page 39 of 84 Standard Max. Min. 800 200 200 Unit ns ns ns 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.21 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 100 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 40 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) 40 200 ns ns tc(TB) TBiIN input cycle time (counted on both edges) tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 80 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 80 ns Table 5.22 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 200 200 ns ns Table 5.23 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) TBiIN input HIGH pulse width 200 ns tw(TBL) TBiIN input LOW pulse width 200 ns Table 5.24 A-D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 5.25 Serial I/O Symbol Parameter Standard Min. Max. Unit tc(CK) CLKi input cycle time 200 ns tw(CKH) CLKi input HIGH pulse width 100 ns tw(CKL) CLKi input LOW pulse width 100 td(C-Q) TXDi output delay time th(C-Q) TXDi hold time tsu(D-C) RXDi input setup time RXDi input hold time th(C-D) ns 80 ns 0 30 ns 90 ns ns _______ Table 5.26 External Interrupt INTi Input Symbol Parameter Standard Min. Max. Unit tw(INH) INTi input HIGH pulse width 250 ns tw(INL) INTi input LOW pulse width 250 ns Rev.2.10 Nov. 07, 2003 page 40 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.27 Memory Expansion and Microprocessor Modes (for setting with no wait) td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Measuring condition Parameter Symbol Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(3) Data output delay time (refers to WR) Standard Min. Max. 25 4 0 (Note 2) 25 4 See Figure 5.1 Data output hold time (refers to WR)(3) HLDA output delay time 15 -4 25 0 25 0 40 4 (Note 1) (Note 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 40 [ns] f(BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. P0 P1 P2 P3 30pF P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Figure 5.1 Ports P0 to P14 Measurement Circuit Rev.2.10 Nov. 07, 2003 page 41 of 84 R DBi C 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.28 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Measuring condition Parameter Symbol Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(3) Data output delay time (refers to WR) Standard Min. Max. 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 0 (Note 2) 25 4 15 See Figure 5.1 Data output hold time (refers to WR)(3) HLDA output delay time Unit -4 25 0 25 0 40 4 (Note 1) (Note 2) 40 NOTES: 1. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 40 f(BCLK) [ns] n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n=1, f(BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. Rev.2.10 Nov. 07, 2003 page 42 of 84 R DBi C 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.29 Memory Expansion and Microprocessor Modes (for 2- to p 3-waitysetting, external area access and multiplex bus selection) th(BCLK-AD) th(RD-AD) Address output hold time (refers to BCLK) Address output hold time (refers to RD) 4 (Note 1) ns ns th(WR-AD) Address output hold time (refers to WR) (Note 1) ns td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) Chip select output delay time Chip select output hold time (refers to BCLK) Chip select output hold time (refers to RD) Chip select output hold time (refers to WR) RD signal output delay time RD signal output hold time td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) th(BCLK-DB) td(DB-WR) Data output hold time (refers to BCLK) Data output delay time (refers to WR) 25 4 (Note 1) (Note 1) 25 0 25 0 40 See Figure 5.1 4 (Note 2) ns ns ns ns ns ns ns ns ns ns ns th(WR-DB) Data output hold time (refers to WR) td(BCLK-HLDA) HLDA output delay time td(BCLK-ALE) ALE signal output delay time (refers to BCLK) th(BCLK-ALE) ALE signal output hold time (refers to BCLK) td(AD-ALE) ALE signal output delay time (refers to Address) (Note 1) -4 (Note 3) ns ns ns th(ALE-AD) td(AD-RD) ALE signal output hold time (refers to Adderss) RD signal output delay from the end of Adress (Note 4) 0 ns ns td(AD-WR) tdZ(RD-AD) WR signal output delay from the end of Adress Address output floating start time 0 40 15 8 NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -10 [ns] 2. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 -40 f(BCLK) [ns] n is "2" for 2-wait setting, "3" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -25 [ns] 4. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) -15 Rev.2.10 Nov. 07, 2003 page 43 of 84 [ns] ns ns ns ns 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V XIN input tf tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input th(TIN-UP) (When count on falling edge is selected) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 5.2 Timing Diagram (1) Rev.2.10 Nov. 07, 2003 page 44 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) RXDi tw(INL) INTi input tw(INH) Figure 5.3 Timing Diagram (2) Rev.2.10 Nov. 07, 2003 page 45 of 84 th(C-D) 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) Memory Expansion Mode, Microprocessor Mode VCC1 = VCC2 = 5V (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) th(BCLK-HOLD) HOLD input HLDA output td(BCLK-HLDA) td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) Hi-Z NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. Measuring conditions : * VCC1=VCC2=5V * Input timing voltage : Determined with VIL=1.0V, VIH=4.0V * Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 5.4 Timing Diagram (3) Rev.2.10 Nov. 07, 2003 page 46 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 X tcyc-45)ns.max Hi-Z DBi tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(WR-AD) -4ns.min (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) tcyc= f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.5 Timing Diagram (4) Rev.2.10 Nov. 07, 2003 page 47 th(WR-DB) (0.5 X tcyc-40)ns.min (0.5 X tcyc-10)ns.min 1 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 25ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD tac2(RD-DB) (1.5 X tcyc-45)ns.max Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns.min 40ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 25ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) -4ns.min 25ns.max (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) tcyc= (0.5 X tcyc-40)ns.min 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.6 Timing Diagram (5) Rev.2.10 Nov. 07, 2003 page 48 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5 X tcyc-45)ns.max DBi Hi-Z tSU(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min CSi 4ns.min ADi BHE td(BCLK-ALE) th(WR-AD) (0.5 X tcyc-10)ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max DBi Hi-Z td(DB-WR) (1.5 X tcyc-40)ns.min tcyc= th(BCLK-DB) 4ns.min 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.7 Timing Diagram (6) Rev.2.10 Nov. 07, 2003 page 49 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-AD) td(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (3.5 X tcyc-45)ns.max DBi Hi-Z tsu(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min CSi 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(WR-AD) (0.5 X tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) (2.5 X tcyc-40)ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.8 Timing Diagram (7) Rev.2.10 Nov. 07, 2003 page 50 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection) Read timing BCLK td(BCLK-CS) th(RD-CS) (0.5 X tcyc-10)ns.min tcyc 25ns.max th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5 X tcyc-25)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DBi Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) tsu(DB-RD) (1.5 X tcyc-45)ns.max 40ns.min th(RD-DB) 0ns.min td(AD-RD) 0ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min 25ns.max ADi BHE td(BCLK-ALE) th(BCLK-ALE) 25ns.max th(RD-AD) (0.5 X tcyc-10)ns.min -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 25ns.max RD Write timing BCLK td(BCLK-CS) tcyc th(BCLK-CS) th(WR-CS) 25ns.max 4ns.min (0.5 X tcyc-10)ns.min CSi th(BCLK-DB) td(BCLK-DB) 4ns.min 40ns.max ADi /DBi Address Data output td(DB-WR) td(AD-ALE) (1.5 X tcyc-40)ns.min (0.5 X tcyc-25)ns.min Address th(WR-DB) (0.5 X tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) td(AD-WR) -4ns.min 0ns.min 25ns.max th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max WR,WRL, WRH tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.9 Timing Diagram (8) Rev.2.10 Nov. 07, 2003 page 51 of 84 th(BCLK-WR) 0ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 X tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 4ns.min 25ns.max CSi td(AD-ALE) (0.5 X tcyc-25)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DBi Address td(BCLK-AD) td(AD-RD) 25ns.max ADi BHE Data input tdZ(RD-AD) 8ns.max th(RD-DB) tac3(RD-DB) (2.5 X tcyc-45)ns.max 0ns.min tsu(DB-RD) 0ns.min th(BCLK-AD) 40ns.min 4ns.min (no multiplex) td(BCLK-ALE) 25ns.max th(RD-AD) th(BCLK-ALE) (0.5 X tcyc-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 25ns.max RD Write timing tcyc BCLK AAAA th(WR-CS) (0.5 X tcyc-10)ns.min td(BCLK-CS) 25ns.max CSi th(BCLK-DB) td(BCLK-DB) 40ns.max ADi /DBi Address th(BCLK-CS) 4ns.min 4ns.min Data output td(AD-ALE) td(DB-WR) (0.5 X tcyc-25)ns.min (2.5 X tcyc-40)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 25ns.max 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) td(BCLK-WR) 25ns.max WR, WRL WRH tcyc= (0.5 X tcyc-10)ns.min 0ns.min ALE 1 f(BCLK) Measuring conditions * VCC1=VCC2=5V * Input timing voltage : VIL=0.8V, VIH=2.0V * Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.10 Timing Diagram (9) Rev.2.10 Nov. 07, 2003 page 52 of 84 th(BCLK-WR) 0ns.min M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62P) VCC1 = VCC2 = 3V Table 5.30 Electrical Characteristics (1) Symbol VOH Parameter HIGH output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, voltage P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 VOH HIGH output voltage XOUT HIGH output voltage XCOUT VOL VOL VT+-VT- Hysteresis VT+-VT- Hysteresis HIGH input current II H LOW input current II L RPULLUP Pull-up resistance IOH=-1mA VCC1-0.5 VCC1 IOH=-1mA (2) VCC2-0.5 VCC2 IOH=-0.1mA VCC1-0.5 VCC1 LOWPOWER IOH=-50A VCC1-0.5 VCC1 HIGHPOWER With no load applied With no load applied 2 .5 1.6 0 .5 IOL=1mA (2) 0 .5 IOL=0.1mA 0 .5 HIGHPOWER XCOUT V HIGHPOWER IOL=50A With no load applied 0 LOWPOWER With no load applied 0 LOWPOWER HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3, SIN4 0 .2 VI=3V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=0V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VI=0V Feedback resistance XIN Feedback resistance XCIN VRAM RAM retention voltage (0.7) 0 .2 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE RfXCIN 0 .5 0 .2 RESET XIN RfXIN 50 100 3.0 25 At stop mode 2 .0 NOTES: 1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified. 2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13. 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 53 of 84 V V IOL=1mA XOUT Unit V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 LOW output voltage VT+-VT- Standard Max. Typ. P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 LOW output voltage Hysteresis Min. HIGHPOWER LOWPOWER LOW output voltage Measuring condition V V 0 .8 V 1 .8 V 0 .8 V 4 .0 A -4 . 0 A 500 k M M V 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Table 5.31 Electrical Characteristics (2) (1) Symbol Measuring condition Parameter In single-chip mode, the output pins are open and other pins are VSS Mask ROM Flash memory Min. Standard Typ. f(BCLK)=10MHz, No division 8 No division, Ring oscillation 1 f(BCLK)=10MHz, No division 8 No division, Ring oscillation ICC Max. 11 Unit mA mA 13 mA 1 .8 mA Flash memory Program f(BCLK)=10MHz, Vcc1=3.0V 12 mA Flash memory Erase f(BCLK)=10MHz, Vcc1=3.0V 22 mA Mask ROM f(XCIN)=32kHz, Low power dissipation mode, ROM (3) 25 A 25 A 420 A Ring oscillation, Wait mode 45 A f(BCLK)=32kHz, Wait mode (2), 6.0 A 1.8 A Power supply current (VCC1=2.7 to 3.6V) Flash memory Mask ROM Flash memory f(BCLK)=32kHz, Low power dissipation mode, RAM (3) f(BCLK)=32kHz, Low power dissipation mode, Flash memory (3) Oscillation capacity High f(BCLK)=32kHz, Wait mode (2), Oscillation capacity Low Stop mode, Topr=25C 0 .7 3.0 A 0.6 4 A Reset level detection dissipation current (4) 0.4 2 A RAM retention limit detection dissipation current (4) 0 .9 4 A Idet4 Voltage down detection dissipation current Idet3 Idet2 (4) NOTES: 1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists. 4. Idet is dissipation current when the following bit is set to "1" (detection circuit enabled). Idet4: VC27 bit of VCR2 register Idet3: VC26 bit of VCR2 register Idet2: VC25 bit of VCR2 register Rev.2.10 Nov. 07, 2003 page 54 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.32 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. Unit ns 100 40 40 18 18 ns ns ns ns Table 5.33 Memory Expansion and Microprocessor Modes Symbol Parameter tac1(RD-DB) Data input access time (for setting with no wait) tac2(RD-DB) Data input access time (for setting with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) Standard Min. Max. (Note 1) (Note 2) (Note 3) 50 Unit ns ns ns 50 ns ns ns 0 ns 0 ns 0 ns 40 NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 60 [ns] 2. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 60 f(BCLK) [ns] n is "2" for 1-wait setting, "3" for 2-wait setting and "4" for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 60 f(BCLK) Rev.2.10 Nov. 07, 2003 page 55 [ns] of 84 n is "2" for 2-wait setting, "3" for 3-wait setting. 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.34 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Max. Min. 150 60 Unit ns ns ns 60 Table 5.35 Timer A Input (Gating Input in Timer Mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 600 300 300 Unit ns ns ns Table 5.36 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter Standard Max. Min. Unit tc(TA) TAiIN input cycle time 300 ns tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width 150 150 ns ns Table 5.37 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 150 150 Unit ns ns Table 5.38 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) tc(UP) TAiOUT input cycle time Standard Min. Max. 3000 tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input HIGH pulse width 1500 TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 1500 600 Symbol Parameter 600 Unit ns ns ns ns ns Table 5.39 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol Parameter tc(TA) TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time Rev.2.10 Nov. 07, 2003 page 56 of 84 Standard Min. Max. 2 500 500 Unit s ns ns 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.40 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time (counted on one edge) 150 ns tw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 ns tw(TBL) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) 60 300 ns tc(TB) tw(TBH) TBiIN input HIGH pulse width (counted on both edges) 120 ns tw(TBL) TBiIN input LOW pulse width (counted on both edges) 120 ns ns Table 5.41 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 600 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 300 300 ns ns Table 5.42 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 600 tw(TBH) TBiIN input HIGH pulse width 300 ns 300 ns tw(TBL) TBiIN input LOW pulse width ns Table 5.43 A-D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 5.44 Serial I/O Symbol Parameter Standard Min. Max. Unit tc(CK) CLKi input cycle time 300 ns tw(CKH) CLKi input HIGH pulse width 150 ns tw(CKL) CLKi input LOW pulse width 150 td(C-Q) TXDi output delay time th(C-Q) TXDi hold time tsu(D-C) RXDi input setup time RXDi input hold time th(C-D) ns 160 ns 0 50 ns 90 ns ns _______ Table 5.45 External Interrupt INTi Input Symbol Parameter tw(INH) INTi input HIGH pulse width tw(INL) INTi input LOW pulse width Rev.2.10 Nov. 07, 2003 page 57 of 84 Standard Min. 380 380 Max. Unit ns ns 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.46 Memory Expansion, Microprocessor Modes (for setting with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Measuring condition Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(3) Data output delay time (refers to WR) Standard Min. Max. 30 4 0 (Note 2) 30 4 25 See Figure 5.11 Data output hold time (refers to WR)(3) HLDA output delay time -4 30 0 30 0 40 4 (Note 1) (Note 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 40 [ns] f(BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 0.5 X 109 f(BCLK) - 10 [ns] 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. P0 P1 P2 P3 30pF P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 Figure 5.11 Ports P0 to P14 Measurement Circuit Rev.2.10 Nov. 07, 2003 page 58 of 84 R DBi C 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC unless otherwise specified) Table 5.47 Memory expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Measuring condition Parameter Address output delay time Address output hold time (refers to BCLK) Address output hold time (refers to RD) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK)(3) Data output delay time (refers to WR) Standard Min. Max. 30 4 0 (Note 2) 30 4 25 See Figure 5.11 Data output hold time (refers to WR)(3) HLDA output delay time -4 30 0 30 0 40 4 (Note 1) (Note 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Calculated according to the BCLK frequency as follows: (n-0.5) X 109 - 40 f(BCLK) [ns] n is "1" for 1-wait setting, "2" for 2-wait setting and "3" for 3-wait setting. When n=1, f(BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 0.5 X 109 - 10 f(BCLK) [ns] 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = -CR X ln (1 - VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1k, hold time of output "L" level is t = - 30pF X 1k X ln (1 - 0.2VCC2 / VCC2) = 6.7ns. Rev.2.10 Nov. 07, 2003 page 59 of 84 R DBi C 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = - 20 to 85oC / - 40 to 85oC, unless otherwise specified) Table 5.48 Memory expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Measuring condition Parameter Symbol td(BCLK-AD) th(BCLK-AD) Address output delay time Address output hold time (refers to BCLK) th(RD-AD) Address output hold time (refers to RD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) Address output hold time (refers to WR) Chip select output delay time Chip select output hold time (refers to BCLK) Chip select output hold time (refers to RD) th(WR-CS) Chip select output hold time (refers to WR) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (refers to BCLK) Data output hold time (refers to BCLK) Data output delay time (refers to WR) 50 4 50 4 (Note 1) (Note 1) See Figure 5.11 RD signal output delay from the end of Address WR signal output delay from the end of Address Address output floating start time -10 40 0 40 0 50 4 (Note 2) (Note 1) 40 25 -4 (Note 3) (Note 4) 0 0 8 [ns] 2. Calculated according to the BCLK frequency as follows: (n-0.5) X 10 9 f(BCLK) -50 n is "2" for 2-wait setting, "3" for 3-wait setting. [ns] 3. Calculated according to the BCLK frequency as follows: 0.5 X 10 9 f(BCLK) -40 [ns] 4. Calculated according to the BCLK frequency as follows: 0.5 X 10 9 f(BCLK) -15 Rev.2.10 Nov. 07, 2003 page 60 [ns] of 84 ns ns ns ns ns ns ns NOTES: 1. Calculated according to the BCLK frequency as follows: 0.5 X 10 9 f(BCLK) Unit ns (Note 1) (Note 1) th(WR-DB) Data output hold time (refers to WR) td(BCLK-HLDA) HLDA output delay time td(BCLK-ALE) ALE signal output delay time (refers to BCLK) th(BCLK-ALE) ALE signal output hold time (refers to BCLK) td(AD-ALE) ALE signal output delay time (refers to Address) th(ALE-AD) ALE signal output hold time (refers to Adderss) td(AD-RD) td(AD-WR) tdZ(RD-AD) Standard Min. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V XIN input tf tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 5.12 Timing Diagram (1) Rev.2.10 Nov. 07, 2003 page 61 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) RXDi tw(INL) INTi input Figure 5.13 Timing Diagram (2) Rev.2.10 Nov. 07, 2003 page 62 of 84 tw(INH) th(C-D) 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY-BCLK) th(BCLK-RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD-BCLK) th(BCLK-HOLD) HOLD input HLDA output td(BCLK-HLDA) td(BCLK-HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) Hi-Z NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. Measuring conditions : * VCC1=VCC2=3V * Input timing voltage : Determined with VIL=0.6V, VIH=2.4V * Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 5.14 Timing Diagram (3) Rev.2.10 Nov. 07, 2003 page 63 of 84 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE th(BCLK-ALE) td(BCLK-ALE) -4ns.min 30ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 X tcyc-60)ns.max Hi-Z DBi tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) 30ns.max th(WR-AD) (0.5 X tcyc-10)ns.min -4ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 4ns.min 40ns.max Hi-Z DBi td(DB-WR) 1 (0.5 X tcyc-40)ns.min tcyc= f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.15 Timing Diagram (4) Rev.2.10 Nov. 07, 2003 page 64 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) th(BCLK-ALE) 0ns.min -4ns.min 30ns.max ALE td(BCLK-RD) th(BCLK-RD) 0ns.min 30ns.max RD tac2(RD-DB) (1.5 X tcyc-60)ns.max Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns.min 50ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 4ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) th(WR-AD) (0.5 X tcyc-10)ns.min -4ns.min 30ns.max ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z DBi td(DB-WR) (0.5 X tcyc-40)ns.min tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.16 Timing Diagram (5) Rev.2.10 Nov. 07, 2003 page 65 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) 4ns.min td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(RD-AD) th(BCLK-ALE) -4ns.min 0ns.min ALE th(BCLK-RD) 0ns.min td(BCLK-RD) 30ns.max RD tac2(RD-DB) (2.5 X tcyc-60)ns.max DBi Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min CSi 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(WR-AD) (0.5 X tcyc-10)ns.min th(BCLK-ALE) -4ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max DBi Hi-Z td(DB-WR) (1.5 X tcyc-40)ns.min tcyc= th(BCLK-DB) 4ns.min 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.17 Timing Diagram (6) Rev.2.10 Nov. 07, 2003 page 66 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access) Read timing tcyc BCLK th(BCLK-CS) 4ns.min td(BCLK-CS) 30ns.max CSi th(BCLK-AD) td(BCLK-AD) 30ns.max 4ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 30ns.max -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 30ns.max 0ns.min RD tac2(RD-DB) (3.5 X tcyc-60)ns.max DBi Hi-Z tsu(DB-RD) th(RD-DB) 50ns.min 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min td(BCLK-AD) th(BCLK-AD) 4ns.min CSi 30ns.max ADi BHE td(BCLK-ALE) 30ns.max th(WR-AD) th(BCLK-ALE) (0.5 X tcyc-10)ns.min -4ns.min ALE th(BCLK-WR) 0ns.min td(BCLK-WR) 30ns.max WR, WRL WRH DBi td(BCLK-DB) th(BCLK-DB) 40ns.max 4ns.min Hi-Z td(DB-WR) (2.5 X tcyc-40)ns.min 1 tcyc= f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.18 Timing Diagram (7) Rev.2.10 Nov. 07, 2003 page 67 of 84 th(WR-DB) (0.5 X tcyc-10)ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection) Read timing BCLK td(BCLK-CS) th(BCLK-CS) th(RD-CS) (0.5 X tcyc-10)ns.min tcyc 40ns.max 4ns.min CSi td(AD-ALE) (0.5 X tcyc-40)ns.min th(ALE-AD) (0.5 X tcyc-15)ns.min ADi /DBi Address 8ns.max Address Data input tdZ(RD-AD) tac3(RD-DB) (1.5 X tcyc-60)ns.max tSU(DB-RD) th(RD-DB) 0ns.min 50ns.min td(AD-RD) th(BCLK-AD) 0ns.min td(BCLK-AD) 4ns.min 40ns.max ADi BHE td(BCLK-ALE) th(BCLK-ALE) 40ns.max th(RD-AD) (0.5 X tcyc-10)ns.min -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 40ns.max 0ns.min RD Write timing BCLK tcyc td(BCLK-CS) th(BCLK-CS) th(WR-CS) 40ns.max 4ns.min (0.5 X tcyc-10)ns.min CSi th(BCLK-DB) td(BCLK-DB) 4ns.min 50ns.max ADi /DBi Address Data output td(DB-WR) td(AD-ALE) (1.5 X tcyc-50)ns.min (0.5 X tcyc-40)ns.min Address th(WR-DB) (0.5 X tcyc-10)ns.min td(BCLK-AD) th(BCLK-AD) 40ns.max ADi BHE td(BCLK-ALE) 40ns.max 4ns.min th(BCLK-ALE) td(AD-WR) -4ns.min 0ns.min th(WR-AD) (0.5 X tcyc-10)ns.min ALE td(BCLK-WR) 40ns.max WR,WRL, WRH tcyc= 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.19 Timing Diagram (8) Rev.2.10 Nov. 07, 2003 page 68 of 84 th(BCLK-WR) 0ns.min 5. Electrical Characteristics (M16C/62P) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 3V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) Read timing tcyc BCLK th(RD-CS) (0.5 X tcyc-10)ns.min td(BCLK-CS) th(BCLK-CS) 6ns.min 40ns.max CSi td(AD-ALE) th(ALE-AD) (0.5 X tcyc-15)ns.min (0.5 X tcyc-40)ns.min ADi /DBi Address td(BCLK-AD) 40ns.max ADi BHE Data input tdZ(RD-AD) td(AD-RD) 8ns.max th(RD-DB) tac3(RD-DB) (2.5 X tcyc-60)ns.max 0ns.min tsu(DB-RD) 0ns.min th(BCLK-AD) 50ns.min 4ns.min (No multiplex) td(BCLK-ALE) 40ns.max th(RD-AD) th(BCLK-ALE) (0.5 X tcyc-10)ns.min -4ns.min ALE th(BCLK-RD) td(BCLK-RD) 0ns.min 40ns.max RD Write timing tcyc BCLK th(WR-CS) td(BCLK-CS) (0.5 X tcyc-10)ns.min 40ns.max th(BCLK-CS) 4ns.min CSi th(BCLK-DB) td(BCLK-DB) 50ns.max ADi /DBi Address 4ns.min Data output td(AD-ALE) td(DB-WR) (0.5 X tcyc-40)ns.min (2.5 X tcyc-50)ns.min th(WR-DB) (0.5 X tcyc-10)ns.min td(BCLK-AD) 40ns.max th(BCLK-AD) 4ns.min ADi BHE (No multiplex) td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) td(BCLK-WR) WR, WRL WRH tcyc= (0.5 X tcyc-10)ns.min 0ns.min ALE 40ns.max 1 f(BCLK) Measuring conditions * VCC1=VCC2=3V * Input timing voltage : VIL=0.6V, VIH=2.4V * Output timing voltage : VOL=1.5V, VOH=1.5V Figure 5.20 Timing Diagram (9) Rev.2.10 Nov. 07, 2003 page 69 of 84 th(BCLK-WR) 0ns.min M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62PT) 5.2 Electrical Characteristics (M16C/62PT) Table 5.49 Absolute Maximum Ratings Condition Rated value VCC1, VCC2 Symbol Supply voltage Parameter VCC1=AVCC -0.3 to 6.5 V VCC2 Supply voltage VCC2 -0.3 to VCC1+0.1 V AVCC Analog supply voltage VCC1=AVCC Input voltage VI -0.3 to 6.5 V RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN -0.3 to VCC1+0.3 (1) V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 -0.3 to VCC2+0.3 (1) V -0.3 to 6.5 V -0.3 to VCC1+0.3 (1) V -0.3 to VCC2+0.3 (1) V -0.3 to 6.5 V P7_0, P7_1 Output voltage Unit P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11 0 to P11_7, P14_0, P14_1, XOUT VO P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P7_0, P7_1 Pd Topr Power dissipation Operating ambient temperature When the microcomputer is operating Flash program erase Tstg Storage temperature -40 C < Topr 85 C 300 -40 C < Topr 125 C 200 -40 to 85 / -40 to 125 (2) C 0 to 60 -65 to 150 NOTES : 1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. 2. T version = -40 to 85 C, V version = -40 to 125 C. Rev.2.10 Nov. 07, 2003 page 70 of 84 mW C 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.50 Recommended Operating Conditions (1) Parameter Symbol Min. VCC1, VCC2 Supply voltage(VCC1=VCC2) AVcc Analog supply voltage Vss Supply voltage AVss 4.0 VIH 5.0 VCC1 0 5.5 Unit V V V 0 Analog supply voltage HIGH input voltage Standard Typ. Max. V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 0.8VCC2 VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0.8VCC2 VCC2 V P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, 0.8VCC1 VCC1 V XIN, RESET, CNVSS, BYTE 0.8VCC1 6.5 V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 0 0.2VCC2 V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0 0.2VCC2 V P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, 0 0.2VCC1 V P7_0 , P7_1 LOW input voltage VIL XIN, RESET, CNVSS, BYTE IOH (peak) HIGH peak output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 -10.0 mA IOH (avg) HIGH average output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 -5.0 mA 10.0 mA 5.0 mA 16 MHz IOL (peak) LOW peak output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 IOL (avg) LOW average output current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 f (XIN) Main clock input oscillation frequency f (XCIN) Sub-clock oscillation frequency f (Ring) Ring oscillation frequency f (PLL) PLL clock oscillation frequency (4) f (BCLK) CPU operation clock tSU(PLL) PLL frequency synthesizer stabilization wait time VCC1=4.0 to 5.5V 0 0.5 VCC1=4.0 to 5.5V VCC1=5.0V 32.768 50 kHz 1 2 MHz 10 24 MHz 0 24 MHz 20 ms NOTES: 1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = -40 to 85 C / -40 to 125 C unless otherwise specified. T version = -40 to 85 C, V version = -40 to 125 C. 2. The mean output current is the mean value within 100ms. 3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be -40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be -40mA max. As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS. 4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 71 of 84 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.51 A-D Conversion Characteristics (1) Symbol - Parameter Resolution Integral nonlinearity error INL Absolute accuracy Standard Unit Min. Typ. Max. VREF =VCC1 VREF= VCC1= 5V 10 bit 8 bit - Measuring condition 10 bit 10 Bits AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0, ANEX1 input 3 LSB External operation amp connection mode 7 LSB 2 LSB 3 LSB 7 LSB 2 LSB 1 3 3 40 k LSB LSB LSB k VREF =VCC1=3.3V VREF= AN0 to AN7 input VCC1= AN0_0 to AN0_7 input AN2_0 to AN2_7 input 5V ANEX0, ANEX1 input External operation amp connection mode 8 bit - DNL - - RLADDER tCONV Tolerance level impedance Differential non-linearity error Offset error Gain error Ladder resistance Conversion time(10bit), Sample & hold function available tCONV Conversion time(8bit), Sample & hold function available tSAMP VREF Sampling time Reference voltage VI A Analog input voltage VREF =VCC1=3.3V 3 VREF =VCC1 VREF =VCC1=5V, oAD=12MHz 10 2.75 VREF =VCC1=5V, oAD=12MHz 2.33 s 0.25 2.0 VCC1 s V 0 VREF V s NOTES: 1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = -40 to 85 C / -40 to 125 C unless otherwise specified. T version = -40 to 85 C, V version = -40 to 125 C. 2. AD operation clock frequency (oAD frequency) must be 12 MHz or less. 3. A case without sample & hold function turn oAD frequency into 250 kHz or more in addition to a limit of Note 2. A case with sample & hold function turn oAD frequency into 1MHz or more in addition to a limit of Note 2. Table 5.52 D-A Conversion Characteristics (1) Symbol Parameter - - Resolution Absolute accuracy Setup time Output resistance Reference power supply input current tsu RO IVREF Measuring condition Standard Min. Typ. Max. 4 (Note 2) 10 Unit 8 1.0 3 20 Bits % s k 1.5 mA NOTES : 1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = -40 to 85 C / -40 to 125 C unless otherwise specified. T version=-40 to 85 C, V version=-40 to 125 C 2. This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "00h". The A-D converter's ladder resistance is not included. Also, when D-A register contents are not "00h", the current IVREF always flows even though Vref may have been set to be unconnected by the A-D control register. Rev.2.10 Nov. 07, 2003 page 72 of 84 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.53 Flash Memory Version Electrical Characteristics (1) for 100 cycle products Symbol Parameter Min. Standard Typ. Max. Unit cycle - Program and erase endurance (3) - Word program time (VCC1=5.0V, Topr=25C) 25 200 s - Lock bit program time 25 200 s - Block erase time (VCC1=5.0V, Topr=25 C) 4K bytes block 0.3 4 s - Erase all unlocked blocks time tPS - 100 8K bytes block 0.3 4 s 32K bytes block 0.5 4 s 64K bytes block 0.8 4 s (2) Flash memory circuit stabilization wait time 4Xn s 15 s 10 Data hold time (5) year Table 5.54 Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (Block A and Block 1 (7)) Symbol Parameter Min. Standard Typ. Max. Unit - Program and erase endurance (3, 8, 9) - Word program time (VCC1=5.0V, Topr=25C) 25 s - Lock bit program time 25 s - Block erase time (VCC1=5.0V, Topr=25 C) 0.3 s tPS - 10,000 (4) 4K bytes block Flash memory circuit stabilization wait time Data hold time 15 10 (5) cycle s year NOTES : 1. Referenced to VCC1=4.5 to 5.5V at Topr = 0 to 60 C unless otherwise specified. 2. n denotes the number of block erases. 3. Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times. For example, if a 4K bytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Topr = -40 to 85 C (T version) / -40 to 125 C (V version). 6. Referenced to VCC1 = 4.0 to 5.5V at Topr = -40 to 85 C (T version) / -40 to 125 C (V version) unless otherwise specified. 7. Table 5.55 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.54. 8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary. Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the total number of times erasure is used. 9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command at least three times until erase error disappears. 10. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 5.55 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60oC) Flash program, erase voltage VCC1=5.0 0.5 V Rev.2.10 Nov. 07, 2003 page 73 Flash read operation voltage VCC1=4.0 to 5.5 V of 84 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) Table 5.56 Power Supply Circuit Timing Characteristics Symbol Parameter td(P-R) Time for internal power supply stabilization during powering-on td(R-S) STOP release time td(W-S) Low power dissipation mode wait mode release time td(M-L) Time for internal power supply stabilization when main clock oscillation starts Measuring condition Standard Typ. Max. 2 VCC1=4.0 to 5.5V Interrupt for stop mode release CPU clock td(R-S) Rev.2.10 Nov. 07, 2003 page 74 of 84 Min. Unit ms 150 s 150 s 50 s M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62PT) VCC1 = VCC2 = 5V Table 5.57 Electrical Characteristics (1) Symbol VOH VOH Parameter HIGH output voltage HIGH output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 HIGH output voltage HIGH output voltage XCOUT VOL VOL IOH=-5mA (2) VCC2-2.0 VCC2 IOH=-200A VCC1-0.3 VCC1 IOH=-200A (2) VCC2-0.3 VCC2 HIGHPOWER IOH=-1mA VCC1-2.0 VCC1 LOWPOWER IOH=-0.5mA VCC1-2.0 VCC1 HIGHPOWER With no load applied With no load applied P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 LOW output voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 LOW output voltage Hysteresis VT+-VT- XOUT XCOUT Max. VCC1 LOW output voltage LOW output voltage Standard Typ. VCC1-2.0 LOWPOWER VOL Min. IOH=-5mA XOUT VOH Measuring condition Unit V V 2.5 1.6 V V IOL=5mA 2 .0 IOL=5mA (2) 2 .0 IOL=200A 0.45 V V IOL=200A 0.45 (2) HIGHPOWER IOL=1mA LOWPOWER IOL=0.5mA HIGHPOWER With no load applied 0 LOWPOWER With no load applied 0 2 .0 2 .0 V V HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL0 to SCL2, SDA0 TO SDA2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SIN3, SIN4 0.2 1 .0 V VT+-VT- Hysteresis RESET 0.2 2.5 V VT+-VT- Hysteresis XIN 0.2 0 .8 V HIGH input current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=5V 5 .0 A P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=0V -5.0 A P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VI=0V II H LOW input current II L RPULLUP Pull-up resistance RfXIN Feedback resistance XIN RfXCIN Feedback resistance XCIN VRAM RAM retention voltage 30 50 1.5 15 At stop mode 2 .0 NOTES: 1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS=0V at Topr = -40 to 85 C / -40 to 125 C, f(BCLK)=24MHz unless otherwise specified. T version is -40 = 85 C, V version = -40 to 125 C. 2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.10 Nov. 07, 2003 page 75 of 84 170 k M M V 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Table 5.58 Electrical Characteristics (2) (1) Symbol In single-chip mode, the output pins are open and other pins are VSS ICC Measuring condition Parameter Mask ROM f(BCLK)=24MHz, No division, PLL operation No division, Ring oscillation Flash memory f(BCLK)=24MHz, No division, PLL operation Min. Standard Typ. 14 Max. 20 1 18 Unit mA mA 27 mA No division, Ring oscillation 1 .8 mA Flash memory Program f(BCLK)=10MHz, VCC1=5.0V 15 mA Flash memory Erase f(BCLK)=10MHz, VCC1=5.0V 25 mA Mask ROM f(XCIN)=32kHz, Low power dissipation mode, ROM (3) 25 A f(BCLK)=32kHz, Low power dissipation mode, RAM (3) 25 A f(BCLK)=32kHz Low power dissipation mode, Flash memory (3) 420 A 50 A 7 .5 A 2 .0 A Power supply current (VCC1=4.0 to 5.5V) Flash memory Ring oscillation, Wait mode f(BCLK)=32kHz, Wait mode (2), Mask ROM Flash memory Oscillation capacity High f(BCLK)=32kHz, Wait mode (2), Oscillation capacity Low Stop mode, Topr=25C 0 .8 3 .0 A Idet4 Voltage down detection dissipation current (4) 0.7 4 A Idet3 Reset area detection dissipation current (4) 1.2 8 A Idet2 RAM retention limit detection dissipation current (4) 1 .1 6 A NOTES: 1. Referenced to VCC1=VCC2= 4.0 to 5.5V, VSS=0V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=24MHz unless otherwise specified. T version = -40 to 85 C, V version = -40 to 125 C 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists. 4. Idet is dissipation current when the following bit is set to "1" (detection circuit enabled). Idet4: VC27 bit of VCR2 register Idet3: VC26 bit of VCR2 register Idet2: VC25 bit of VCR2 register Rev.2.10 Nov. 07, 2003 page 76 of 84 M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 40 to 85oC (T version) / - 40 to 125oC (V version) unless otherwise specified) Table 5.59 External Clock Input (XIN input) Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Rev.2.10 Nov. 07, 2003 page 77 of 84 Standard Min. Max. Unit ns 62.5 25 25 15 15 ns ns ns ns 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 40 to 85oC (T version) / - 40 to 125oC (V version) unless otherwise specified) Table 5.60 Timer A Input (Counter Input in Event Counter Mode) Symbol tc(TA) Parameter TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 100 40 40 Unit ns ns ns Table 5.61 Timer A Input (Gating Input in Timer Mode) Symbol tc(TA) Parameter TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 5.62 Timer A Input (External Trigger Input in One-shot Timer Mode) Symbol Parameter tc(TA) tw(TAH) TAiIN input cycle time TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Max. Min. Unit 200 ns 100 100 ns ns Table 5.63 Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Max. Min. 100 100 Unit ns ns Table 5.64 Timer A Input (Counter Increment/decrement Input in Event Counter Mode) TAiOUT input HIGH pulse width Standard Min. Max. 2000 1000 TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 1000 400 400 Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Parameter TAiOUT input cycle time Unit ns ns ns ns ns Table 5.65 Timer A Input (Two-phase Pulse Input in Event Counter Mode) Symbol tc(TA) Parameter TAiIN input cycle time tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time Rev.2.10 Nov. 07, 2003 page 78 of 84 Standard Max. Min. 800 200 200 Unit ns ns ns M16C/62 Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics (M16C/62PT) VCC1 = VCC2 = 5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 40 to 85oC (T version) / - 40 to 125oC (V version) unless otherwise specified) Table 5.66 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter tc(TB) TBiIN input cycle time (counted on one edge) tw(TBH) tw(TBL) tc(TB) TBiIN input cycle time (counted on both edges) tw(TBH) tw(TBL) Standard Min. Max. Unit 100 ns TBiIN input HIGH pulse width (counted on one edge) 40 ns TBiIN input LOW pulse width (counted on one edge) 40 200 ns TBiIN input HIGH pulse width (counted on both edges) 80 ns TBiIN input LOW pulse width (counted on both edges) 80 ns ns Table 5.67 Timer B Input (Pulse Period Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 200 200 ns ns Table 5.68 Timer B Input (Pulse Width Measurement Mode) Symbol Parameter Standard Min. Max. Unit tc(TB) TBiIN input cycle time 400 tw(TBH) TBiIN input HIGH pulse width 200 ns 200 ns tw(TBL) TBiIN input LOW pulse width ns Table 5.69 A-D Trigger Input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 5.70 Serial I/O Symbol Parameter Standard Min. Max. Unit tc(CK) CLKi input cycle time 200 ns tw(CKH) CLKi input HIGH pulse width 100 ns tw(CKL) CLKi input LOW pulse width 100 ns td(C-Q) TXDi output delay time th(C-Q) TXDi hold time tsu(D-C) RXDi input setup time RXDi input hold time th(C-D) 80 ns 0 30 ns 90 ns ns _______ Table 5.71 External Interrupt INTi Input Symbol Parameter tw(INH) INTi input HIGH pulse width tw(INL) INTi input LOW pulse width Rev.2.10 Nov. 07, 2003 page 79 of 84 Standard Min. 250 250 Max. Unit ns ns 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = - 40 to 85oC (T version) / - 40 to 125oC (V version) unless otherwise specified) P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Figure 5.21 Ports P0 to P10 Measurement Circuit Rev.2.10 Nov. 07, 2003 page 80 of 84 30pF 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V XIN input tf tw(H) tr tw(L) tc tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input th(TIN-UP) (When count on falling edge is selected) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode tc(TA) TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 5.22 Timing Diagram (1) Rev.2.10 Nov. 07, 2003 page 81 of 84 5. Electrical Characteristics (M16C/62PT) M16C/62 Group (M16C/62P, M16C/62PT) VCC1 = VCC2 = 5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) RXDi tw(INL) INTi input tw(INH) Figure 5.23 Timing Diagram (2) Rev.2.10 Nov. 07, 2003 page 82 of 84 th(C-D) Package Dimensions M16C/62 Group (M16C/62P, M16C/62PT) Package Dimensions MMP 80P6S-A EIAJ Package Code QFP80-P-1414-0.65 Plastic 80pin 1414mm body QFP Weight(g) 1.11 Lead Material Alloy 42 MD e JEDEC Code HD 61 b2 80 ME D 1 60 I2 Symbol HE E Recommended Mount Pad 41 20 21 A 40 c F A2 L1 b e x M A1 y b2 I2 MD ME L Detail F 100P6S-A MMP EIAJ Package Code QFP100-P-1420-0.65 A A1 A2 b c D E e HD HE L L1 x y Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 - 0.65 - 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 - - - - 0.13 - - 0.1 - 0 10 - - 0.35 1.3 - - 14.6 - - - - 14.6 Plastic 100pin 1420mm body QFP Weight(g) 1.58 Lead Material Alloy 42 MD e JEDEC Code - 81 1 b2 100 ME HD D 80 I2 Recommended Mount Pad E 30 HE Symbol 51 50 A L1 c A2 31 A A1 A2 b c D E e HD HE L L1 x y b x y Rev.2.10 Nov. 07, 2003 page 83 of 84 M A1 F e L Detail F b2 I2 MD ME Dimension in Millimeters Min Nom Max 3.05 - - 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - - - 0.13 0.1 - - 0 10 - 0.35 - - 1.3 - - 14.6 - - 20.6 - - Package Dimensions M16C/62 Group (M16C/62P, M16C/62PT) MMP Plastic 100pin 1414mm body LQFP Weight(g) 0.63 JEDEC Code - Lead Material Cu Alloy MD b2 HD ME EIAJ Package Code LQFP100-P-1414-0.50 e 100P6Q-A D 76 100 l2 Recommended Mount Pad 75 1 A A1 A2 b c D E e HD HE L L1 Lp HE E Symbol 51 25 26 50 A L1 F A3 y M L Detail F x y c x A1 b A3 A2 e b2 I2 MD ME Lp MMP EIAJ Package Code LQFP128-P-1420-0.50 Plastic 128pin 1420mm body LQFP Weight(g) - JEDEC Code - Lead Material Cu Alloy MD e 128P6Q-A Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 - 0.5 - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 0.9 - - 14.4 - - - - 14.4 b2 D 128 ME HD 103 1 102 l2 Recommended Mount Pad Symbol E HE A A1 A2 b c D E e HD HE L L1 Lp 65 38 39 64 L1 A y b Rev.2.10 Nov. 07, 2003 page 84 x of 84 M L Detail F Lp A3 x y c A1 A2 e A3 F b2 I2 MD ME Dimension in Millimeters Min Nom Max 1.7 1.4 1.5 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 13.9 14.0 14.1 19.9 20.0 20.1 0.5 - - 15.8 16.0 16.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - - 1.0 - 14.4 - - 20.4 - - REVISION HISTORY Rev. M16C/62 Group (M16C/62P, M16C/62PT) Data Sheet Date Description Summary Page 1.10 May/28/Y03 (Continued) 2 4-5 14-19 22 23 24 30 31 30-31 32 30-32 36-39 40-41 42 47 48 47-48 49 47-49 53-56 57-58 2.00 Oct./29/Y03 2-4 6 7-9 11 12-15 17,19 18,20 30 31-32 33 34,74 36 38,55 41 41-43, 58-60 44 Table 1.1.1 is partly revised. Table 1.1.2 and 1.1.3 is partly revised. SFR is partly revised. "Note 1" is partly revised. Table 1.5.3 is partly revised. Table 1.5.5 is partly revised. Table 1.5.6 is added. Table 1.5.9 is partly revised. Notes 1 and 2 in Table 1.5.26 is partly revised. Notes 1 in Table 1.5.27 is partly revised. Note 3 is added to "Data output hold time (refers to BCLK)" in Table 1.5.26 and 1.5.27. Note 4 is added to "th(ALE-AD)" in Table 1.5.28. Switching Characteristics is partly revised. th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised. th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to 1.5.10 is partly revised. Note 2 is added to Table 1.5.29. Notes 1 and 2 in Table 1.5.45 is partly revised. Notes 1 in Table 1.5.46 is partly revised. Note 3 is added to "Data output hold time (refers to BCLK)" in Table 1.5.45 and 1.5.46. Note 4 is added to "th(ALE-AD)" in Table 1.5.47. Switching Characteristics is partly revised. th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised. th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to 1.5.20 is partly revised. Since high reliability version is added, a group name is revised. M16C/62 Group (M16C/62P) AE M16C/62 Group (M16C/62P, M16C/62PT) Table 1.1 to 1.3 are revised. Note 3 is partly revised. Figure 1.2 Note5 is deleted. Table 1.4 to 1.7 Product List is partly revised. Table 1.8 and Figure 1.4 are added. Figure 1.5 to 1.9 ZP is added. Table 1.10 and 1.12 ZP is added to timer A. Table 1.11 and 1.13 VCC1 is added to VREF. Table 5.1 is revised. Table 5.2 and 5.3 are revised. Table 5.4 A-D Conversion Characteristics is revised. Table 5.5 D-A Conversion Characteristics revised. Table 5.6 to 5.7 and table 5.54 to 5.55 are revised. Table 5.11 is revised. Table 5.14 and 5.33 HLDA output deley time is deleted. Figure 5.1 is partly revised. Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added. Figure 5.2 Timing Diagram (1) A-1 XIN input is added. REVISION HISTORY Rev. Date 2.10 Nov./07/Y03 Page 47-48 49-50 52 53 58 61 64-65 66-67 69 70-85 8-9 23 71 72 M16C/62 Group (M16C/62P, M16C/62PT) Data Sheet Description Summary Figure 5.5 to 5.6 Read timing DB --> DBi Figure 5.7 to 5.8 Write timing DB --> DBi Figure 5.10 DB --> DBi Table 5.30 is revised. Figure 5.11 is partly revised. Figure 5.12 Timing Diagram (1) XIN input is added. Figure 5.15 to 5.16 Read timing DB --> DBi Figure 5.17 to 5.18 Write timing DB --> DBi Figure 5.20 DB --> DBi Electrical Characteristics (M16C/62PT) is added. Table 1.5 to 1.7 Product List is partly revised. Note 1 is deleted. Table 3.1 is revised. Table 5.50 is revised. Table 5.51 is deleted. A-2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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