D a t a S h e e t , D S 2 , Ma y 2 0 0 1 TE3-CHATT Channelized T3 Termination with D S 3 F r a m e r , M 1 3 M u lt i p l e x e r , T 1 / E1 Fra m er s a n d 2 5 6 Ch a n n e l H DL C / PP P c o n tr o l le r PEB 3456 E Version 2.1 Datacom N e v e r s t o p t h i n k i n g . Edition 05.2001 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 5/21/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a t a S h e e t , D S 2 , Ma y 2 0 0 1 TE3-CHATT Channelized T3 Termination with D S 3 F r a m e r , M 1 3 M u lt i p l e x e r , T 1 / E1 Fra m er s a n d 2 5 6 Ch a n n e l H DL C / PP P c o n tr o l le r PEB 3456 E Version 2.1 Datacom N e v e r s t o p t h i n k i n g . PEB 3456 E Revision History: 05.2001 Previous Version: Preliminary Data Sheet 11.1999 Major changes to document since last version Page DS2 Description 27 Pin Diagram Added 162 Corrected Part Number from 0076 to 0077. 208 Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER register as their bit postitions were not correct in the preliminary data sheet. 209 Swap the postions of TBRTC with TBFTC in Table 8-7, as their column positions were not correct in the preliminary data sheet 213 Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD 243 Fixed typo in IQMASK, replaced ROFD with RFOD 256 Added note to clarify configuration of FDL links 28 and 29. 263 Added special programming note for reseting D3CLKCS register 268 Added text to clarify function of TXBIT in D3TCOM 268 Reset value of D3TCOM Register was incorrectly documented. 268 Note added to recommend seting register D3TCOM to 0070 after reset, for normal operation. 284 Note added to explain that reset value of D3RSTAT will be different after some time. 302 Note added to explain that reset value of D2RSTAT will be different after some time 389 Update voltage min/max information for Table 9-1 Absolute Maximum Ratings 391 Update timing Information for Table 9-4 DC Characteristics (PCI Interface Pins) 392 Update timing Information for Table 9-5 PCI Clock Characteristics 393 Update timing Information for Table 9-6 PCI Interface Signal Characteristics 396 Update timing Information for Table 9-8 Intel Bus Interface Timing 397 Intel Bus Interface Timing Diagram modified. The setup and hold times for "LD to LRDY" was not a valid timing parameter. Instead, the setup and hold parameters for "LD to LRD" were specified. Data Sheet 4 05.2001 PEB 3456 E Revision History: 05.2001 Previous Version: Preliminary Data Sheet 11.1999 Major changes to document since last version Page DS2 Description 399 Update timing Information for Table 9-9 Intel Bus Interface Timing (Master Mode) 399 Timing parameter (setup time) 67a was changed from "LD to LDRY" to "LD to LRD", because it was not a valid timing parameter. 399 Timing parameter (hold time) 67b was changed from "LD to LDRY" to "LD to LRD", because it was not a valid timing parameter. 401 Update timing Information for Table 9-10 Motorola Bus Interface Timing 404 Update timing Information for Table 9-11 Motorola Bus Interface Timing (Master Mode) 407 Update timing Information for Table 9-13 DS3 Transmit Cycle Timing For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com Data Sheet 5 05.2001 PEB 3456 E Preface The Channelized T3 Termination with DS3 Framer, M13 Multiplexer, T1/E1 Framers and 256 Channel HDLC/PPP controller is a Multichannel Protocol Controller for a wide area of telecommunication and data communication applications. Organization of this Document This Data Sheet is divided into ten chapters and is organized as follows: * Chapter 1 TE3-CHATT Overview Gives a general description of the product and its family, lists the key features, and presents some typical applications . * Chapter 2 Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3 General Overview This chapter provides short descriptions of all the internal functional blocks. * Chapter 4 Functional Description Gives a detailed description of all functions * Chapter 5 Interface Description This chapter provides functional diagrams of all interfaces. * Chapter 6 Channel Programming / Reprogramming Concept This chapter provides a detailed description of the channel programming concept. * Chapter 7 Reset and Initialization procedure Gives examples of the initialzation procedure and operation. * Chapter 8 Register Description Gives a detailed description of all on-chip registers. * Chapter 9 Electrical Characteristics Data Sheet 6 05.2001 PEB 3456 E Gives a detailed description of all electrical DC and AC characteristics, and provides timing diagrams for all interfaces. * Chapter 10 Package Outline. Shows the mechanical values of the device package. Data Sheet 7 05.2001 PEB 3456 E Data Sheet 8 05.2001 PEB 3456 E Table of Contents Page 1 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.2 1.3 TE3-CHATT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Alignment T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signaling Controller T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Alignment E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signaling Controller E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23 24 24 24 24 24 25 25 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply, Reserved Pins and No-connect Pins . . . . . . . . . . . . . . . . . 27 27 28 29 35 36 39 44 45 3 3.1 3.2 3.3 3.4 General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 47 48 48 49 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Port Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time slot Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channelized Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unchannelized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Descriptor Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Management Unit Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Management Unit Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmission Bit/Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 54 54 56 56 56 58 59 59 60 64 66 69 71 72 Data Sheet 9 05.2001 PEB 3456 E Table of Contents 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.6 4.6.1 4.6.2 4.6.2.1 4.6.2.2 4.6.2.3 4.6.2.4 4.6.3 4.6.3.1 4.6.3.2 4.6.4 4.6.4.1 4.6.4.2 4.6.4.3 4.6.4.4 4.6.4.5 4.6.4.6 4.7 4.7.1 4.7.1.1 4.7.1.2 4.7.1.3 4.7.2 4.7.2.1 4.7.2.2 4.7.2.3 4.7.2.4 4.7.2.5 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.3.4 4.8 Page Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Internal Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Internal Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Bit Synchronous PPP with HDLC Framing Structure . . . . . . . . . . . . . . 77 Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 T1 Framer and FDL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4-Frame Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Multiframe Synchronization Procedure of the Receiver . . . . . . . . . . . 81 CRC-6 Generation / Check according to ITU-T G.706 . . . . . . . . . . . 81 Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . 82 Facility Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 85 Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . 86 Common Features for SF and ESF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 AIS (Blue Alarm) Generation/Detection . . . . . . . . . . . . . . . . . . . . . . . 87 Loss of Signal (Red Alarm) Detection . . . . . . . . . . . . . . . . . . . . . . . . 87 In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . . 88 Pulse Density Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Error Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . . 89 E1 Framing and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Doubleframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 90 A-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 CRC-4 Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 93 CRC-4 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 A-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 E-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Common Features for E1 Doubleframe and CRC-4 Multiframe . . . . . . 98 Error Performance Monitoring and Alarm Handling . . . . . . . . . . . . . . 98 Loss of Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . 100 Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . 100 Signaling Controller Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Data Sheet 10 05.2001 PEB 3456 E Table of Contents 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.9 4.9.1 4.9.1.1 4.9.1.2 4.9.1.3 4.9.1.4 4.9.2 4.9.2.1 4.9.2.2 4.9.2.3 4.9.2.4 4.9.2.5 4.10 4.10.1 4.10.1.1 4.10.1.2 4.10.1.3 4.10.1.4 4.10.1.5 4.10.1.6 4.10.2 4.10.2.1 4.10.2.2 4.10.2.3 4.10.2.4 4.10.2.5 4.10.2.6 4.10.2.7 4.10.2.8 4.10.2.9 4.10.3 4.11 4.12 4.13 4.13.1 4.13.1.1 4.13.1.2 Page HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signalling Controller FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer Two interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . . System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 11 101 103 103 104 105 108 108 109 110 110 110 111 111 111 112 112 112 112 113 114 114 114 114 115 115 116 117 117 117 118 118 118 118 119 119 120 120 121 122 123 125 127 05.2001 PEB 3456 E 4.13.1.3 4.13.1.4 4.13.1.5 4.13.2 4.13.2.1 4.13.2.2 4.13.2.3 4.13.2.4 4.13.2.5 Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layer One Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Framer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Facility Data Link Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3, DS2 and Test Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . Mailbox Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 130 135 137 138 139 141 143 146 5 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.2 5.2.3 5.3 5.3.1 5.3.1.1 5.3.1.2 5.3.2 5.3.2.1 5.3.2.2 5.4 5.5 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface (ROM Load Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accesses to a SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 147 148 149 150 150 151 152 153 153 153 156 156 156 158 161 6 6.1 6.2 6.3 Channel Programming / Reprogramming Concept . . . . . . . . . . . . . . Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 164 164 166 7 7.1 7.2 Reset and Initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Chip Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Register Set (Direct Access) . . . . . . . . . . . . . . . . . PCI Slave Register Set (Direct Access) . . . . . . . . . . . . . . . . . . . . . . . . PCI and Local Bus Register Set (Direct Access) . . . . . . . . . . . . . . . . . Transmit T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . Receive T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . . Facility Data Link Registers (Indirect Access) . . . . . . . . . . . . . . . . . . . Data Sheet 12 171 171 171 173 175 180 181 182 05.2001 PEB 3456 E 8.2 8.2.1 8.2.2 8.2.2.1 8.2.2.2 8.2.2.3 8.2.2.4 8.2.3 8.2.3.1 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.1.3 8.3.1.4 8.3.2 8.3.2.1 8.3.2.2 8.3.2.3 8.3.2.4 8.3.2.5 8.4 8.4.1 8.4.1.1 8.4.1.2 8.4.1.3 8.4.1.4 8.4.1.5 8.4.1.6 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.2.5 8.4.2.6 8.4.2.7 8.4.2.8 8.4.2.9 8.4.3 8.5 8.5.1 8.5.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Slave Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3, DS2 and Test Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . . . . . . . . Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Port Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 13 183 183 198 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 215 05.2001 PEB 3456 E 8.5.3 8.6 8.7 8.8 8.8.1 8.8.2 8.8.3 8.9 8.9.1 8.9.1.1 8.9.1.2 8.9.1.3 8.9.2 8.9.2.1 8.9.2.2 8.9.3 8.9.4 8.9.5 8.9.6 Test Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . M13 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . M13 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Framer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 215 215 215 215 215 215 215 215 215 215 215 247 263 293 308 326 336 360 9 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.3.1 9.4.3.2 9.4.3.3 9.4.3.4 9.4.4 9.4.4.1 9.4.4.2 9.4.4.3 9.4.4.4 9.4.4.5 9.4.5 9.4.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . Intel Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . tCYC is the clock period of the PCI clock.Serial Interface Timing . . . . DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 389 389 389 391 392 394 395 395 397 400 402 406 406 410 412 413 415 418 419 10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 11 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Data Sheet 14 05.2001 PEB 3456 E List of Figures Page Figure 1-1 TE3-CHATT Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 1-2 System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 2-1 TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 3-1 TE3-CHATT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 4-1 Port configuration in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 4-2 Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 4-3 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 4-4 Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 4-5 Time slot Assignment in Channelized Modes . . . . . . . . . . . . . . . . . . . 58 Figure 4-6 Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 4-7 Receive Buffer Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 4-8 Transmit Buffer Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 4-9 HDLC Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure. . . . . . . . . . . . . . 77 Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithms . . . . . . . . . . . . . . . 95 Figure 4-12 Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . 107 Figure 4-13 Interrupt Driven Transmit Sequence Example . . . . . . . . . . . . . . . . . . 108 Figure 4-14 Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 4-15 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 4-16 Mailbox Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 4-17 Layer Two Interrupts (Channel, command, port and system interrupts . . . 124 Figure 4-18 Interrupt Queue Structure in System Memory . . . . . . . . . . . . . . . . . . 125 Figure 4-19 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . . 137 Figure 5-1 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 5-2 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 5-3 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 5-4 SPI Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 5-5 Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 5-6 Intel Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 5-7 Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 5-8 Motorola Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 5-9 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Figure 5-10 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 161 Figure 8-1 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-2 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 215 Figure 8-3 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-4 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-5 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-6 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Data Sheet 15 05.2001 PEB 3456 E List of Figures Page Figure 8-7 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-8 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-9 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-10 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-11 T1/E1 Test Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-12 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-13 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-14 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . . 215 Figure 8-15 Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-16 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-17 Port configuration in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-18 Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-19 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-20 Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-21 TE3-CHATT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-22 TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-23 System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-24 TE3-CHATT Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-25 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-26 DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-27 DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 8-28 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Figure 9-1 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 391 Figure 9-2 PCI Clock Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Figure 9-3 PCI Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . 392 Figure 9-4 PCI Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . 393 Figure 9-5 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Figure 9-6 Intel Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . 395 Figure 9-7 Intel Write Cycle Timing (Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . 395 Figure 9-8 Intel Read Cycle Timing (Master Mode, LRDY controlled) . . . . . . . . 397 Figure 9-9 Intel Write Cycle Timing (Master Mode, LRDY controlled). . . . . . . . . 397 Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled) . . . . . 398 Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled) . . . . . 398 Figure 9-12 Intel Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 Figure 9-13 Motorola Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . 400 Figure 9-14 Motorola Write Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . 400 Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled). . . 402 Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled). . . 402 Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled). . 403 Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled) . . 403 Figure 9-19 Motorola Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Data Sheet 16 05.2001 PEB 3456 E Figure 9-20 Figure 9-21 Figure 9-22 Figure 9-23 Figure 9-24 Figure 9-25 Figure 9-26 Figure 9-27 Figure 9-28 Figure 9-29 Figure 9-30 Figure 9-31 Figure 9-32 Figure 9-33 Figure 9-34 Figure 9-35 Figure 9-36 Data Sheet Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 406 407 407 408 410 410 411 412 412 413 414 415 416 416 417 418 419 05.2001 PEB 3456 E Data Sheet 18 05.2001 PEB 3456 E List of Tables Page Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14 Table 4-15 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Receive Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Transmit Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Example for little/big Endian with BNO = 3 . . . . . . . . . . . . . . . . . . . . . 72 Example for little big Endian with BNO = 7 . . . . . . . . . . . . . . . . . . . . . 72 4-Frame Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ESF Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SF Multiframe Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Allocation of Bits 1 to 8 of Time slot 0 . . . . . . . . . . . . . . . . . . . . . . . . . 90 CRC-4 Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Summary of Alarm Detection and Alarm Release . . . . . . . . . . . . . . . . 98 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Interrupt Vector Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Correspondence between PCI memory space and chip select . . . . . 152 C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode) . . . . 155 C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode) . . . 155 C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode) 158 C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode) . . 158 Table 6-1 Channel Specification Registers and Channel Commands . . . . . . . . 163 Table 8-1 PCI Configuration Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 8-2 PCI Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 8-3 PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . 175 Table 8-4 Transmit T1/E1 Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 8-5 Receive T1/E1 Framer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 8-6 Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 8-7 Threshold Codings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 8-8 DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-9 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-10 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-11 DS3 Transmit Stuff Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-12 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-13 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-14 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-15 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-16 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-17 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-18 Test T1/E1 Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-19 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 8-20 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Data Sheet 19 05.2001 PEB 3456 E Table 8-21 Table 8-22 Table 8-23 Table 8-24 Table 8-25 Table 8-26 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 9-5 Table 9-6 Table 9-7 Table 9-8 Table 9-9 Table 9-10 Table 9-11 Table 9-12 Table 9-13 Table 9-14 Table 9-15 Table 9-16 Table 9-17 Table 9-18 Table 9-19 Table 9-20 Table 9-21 Table 9-22 Table 9-23 Table 9-24 Table 9-25 Table 9-26 Table 9-27 Data Sheet M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signalling Controller Transmit Commands . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Non-PCI Interface Pins) . . . . . . . . . . . . . . . . . . . DC Characteristics (PCI Interface Pins). . . . . . . . . . . . . . . . . . . . . . . PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing (Master Mode). . . . . . . . . . . . . . . . . . Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Transmit Stuff Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Test T1/E1 Receive Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 215 215 215 215 215 374 389 389 390 391 392 393 394 396 399 401 404 406 407 408 409 410 411 412 412 413 414 415 416 416 417 418 419 05.2001 PEB 3456 E Data Sheet 21 05.2001 PEB 3456 E TE3-CHATT Overview 1 TE3-CHATT Overview The TE3-CHATT is a highly integrated protocol controller that implements HDLC, PPP and transparent (TMA) protocol processing for 256 channels as well as frame alignment for up to 28 T1 signals or 21 E1 signals. An integrated M13 multiplexer together with a DS3 framer concentrates the data links for direct connection to a DS3 line interface unit. Optionally the device supports unchannelized DS3 applications. An internal bit error rate tester can be attached to different test points and provides flexible PRBS and fixed pattern tests. An on-chip data management unit is optimized to transfer data packets via a PCI interface by minimizing the bus load. Note: The TE3-CHATT does not contain DS3 Line Interface Units. 1.1 General Features * Protocol processing on a channelized or unchannelized DS3 link for frame relay or router applications * Direct connection to DS3 line interface unit or DS3 to STS-1 mapper * Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum of 28 links, for HDLC, PPP or transparent mode (TMA) processing * Concatenation of any, not necessarily consecutive, time slots to logical channels on each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels * Provides 32kB data buffer in transmit direction and 12kB data buffer in receive direction * Integrates 28T1/21E1 framers (frame alignment function) and 28T1/21E1 signalling controllers * Integrates a DS2/DS3 multiplexer and framer * Remote loopbacks selectable for either DS3 signal, DS2 signal or T1/E1 signal/ payload * System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM interface. PCI bus interface can be operated in the range of 33 MHz to 66 MHz * Integrates a local microprocessor master and slave interface (demultiplexed 16 bit address and data bus in Intel mode or Motorola mode) which allows access to the local bus via the PCI bus or which can communicate with a PCI host processor through an on-chip mailbox * For debugging purposes optional access to the framer and signalling controller functions via the PCI interface * JTAG boundary scan according to IEEE1149.1 (5 pins). * 0.25 m, 2.5V core technology * I/Os are 3.3V tolerant and have 3.3V driving capability * Package P-BGA 388 (35mm x 35mm; pitch 1.27mm) Data Sheet 22 05.2001 PEB 3456 E TE3-CHATT Overview * * * * Full scan path and BIST of on-chip RAMs for production test Performance: 45Mbit/s (DS3) throughput per direction Estimated power consumption: 2W Also available as device with extended temperature range -40..+85C 1.1.1 M12 Multiplexer and DS2 Framer * Multiplexing/Demultiplexing of four asynchronous DS1 bit streams into/from M13 asynchronous format * Multiplexing/Demultiplexing of 3 E1 signals into/from ITU G.747 compliant DS2 signal. * DS2 line loopback detection/generation * Framing according to ANSI T1.107, T1.107a or ITU-T G.747 * Insertion and extraction of X-bit * Insertion and Extraction of alarms (remote alarm, AIS) * Detection of AIS in presence of BER 10-3 * Alarm and performance monitoring (framing bit errors, parity errors) * Reframe time below 7ms (TR-TSY-000009) for DS2 format and below 1 ms for ITU G.747 format * Bit Stuffing/Destuffing in M12 multiplex format or C-bit parity format 1.1.2 M23 Multiplexer and DS3 Framer * Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format according to ANSI T1.107, ANSI T1.107a * Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to ANSI T1.107, ITU-T G.704 * DS3 framing according to ANSI T1.107, T1.107a, ITU-T G.704 * Support of unipolar and B3ZS encoded signals * Provides access to the DS3 overhead bits and the DS3 stuffing bits via a serial clock and data interface (overhead interface) * Insertion and Extraction of alarms according to ANSI T1.404 (remote alarm, AIS, far end receive failure) * Supports HDLC (Path Maintenance Data Link) and bit oriented message mode (Far End Alarm and Control Channel) in C-bit parity mode. An integrated signalling controller provides 2x32 byte deep FIFO's for each direction of both channels * Detection of AIS and idle signal in presence of BER 10-3 * Detection of excessive zeroes and LOS * Alarm and performance monitoring with 16-bit counters for line code violations, excessive zeroes, parity error (P-bit), framing errors (F-bit errors with or without M-bit errors, far end block error (FEBE-bit) and CP-bit errors. * Automatic insertion of severely errored frame and AIS defect indication Data Sheet 23 05.2001 PEB 3456 E TE3-CHATT Overview 1.1.3 * * * * * * * * Frame Alignment T1 Features Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704 Supports T1 frame alignment for F4, SF (F12) and ESF (F24) mode Error checking via CRC-6 procedures according to ITU-T G.706 Performance monitor: 16 bit counter for CRC, framing errors, loss of frame alignment, loss of signal AIS Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm) Detection of LOS (Red Alarm) Pseudo-random bit sequence generator and monitor for one logical channel according to ITU-T O.151 Programmable in-band loop code detection/generation according to TR 62411 1.1.4 Signaling Controller T1 Features * FDL-channel protocol for ESF format according to ANSI T1.403 specification or according to AT&T TR54016 * Supports HDLC mode with address recognition * Supports BOM mode * FIFO Buffers (64 bytes deep) for efficient transfer of data packets 1.1.5 Frame Alignment E1 Features * Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 * Programmable formats: Doubleframe, CRC-4 Multiframe Selectable conditions for recover / loss of frame alignment * CRC-4 to Non-CRC-4 Interworking of ITU-T G.706 Annex B * Error checking via CRC-4 procedures according to ITU-T G.706 * Performance monitor: 16 bit counter for CRC-, framing errors, error monitoring via Ebit and Sa6 bit * Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, ...) * Pseudo-random bit sequence (PRBS) generator and monitor for one logical channel * Programmable in-band loop code detection / generation according to TR 62411 1.1.6 * * * * Signaling Controller E1 Features HDLC controller with address recognition and programmable preamble Time slot 0 Sa8-4 HDLC handling via FIFOs HDLC access to any Sa-bit combination FIFO Buffers (64 byte deep) for efficient transfer of data packets 1.1.7 Bit Error Rate Tester * User specified PRBS/Fixed Pattern with programmable length of 1 to 32 bits * Optional Bit Inversion Data Sheet 24 05.2001 PEB 3456 E TE3-CHATT Overview * * * * Two error insertion modes: Single or programmable bit rates Optional zero suppression 32-bit counters for errors and received bits Programmable bit intervals for receive measurements 1.2 Logic Symbol Serial Interface Overhead Bits DS3 Status Signals RD44P RD44N RC44 TD44P TD44N TC44 TC44O CTCLK CTFS TOVHCK TOVHD TOVHDEN TOVHSYN TSBDCK TSBD ROVHCK ROVHD ROVHSYN RSBD RSBDCK RLOS RLOF RAIS RRED * RSPO TRCLK TRD TTCLK TTD AD[31:0] C/BE[3:0] PCI FRAME TRDY IRDY STOP DEVSEL IDSEL PAR LA(12:0) LD(15:0) TE3-CHATT PEB 3456 E REQ GNT CLK RST LBHE/LSIZE0 LRDY/LDTACK LRD/LDS LWR/LRDWR LHOLD/LBR LHLDA/LBG LBGACK PERR SERR INTA Local Bus LCLK LMODE LINT SPCLK SPCS SPI SPO SPLOAD TDI TDO TMS TCK TRST SCAN LCS0 LCS1 LCS2 V DD3 V DD25 V SS SPITM Test and Reference Signals JTAG Figure 1-1 1.3 TE3-CHATT Logic Symbol General System Integration The TE3-CHATT provides the HDLC/PPP protocol handling, T1/E1 framing and signalling functions, an integrated M13 multiplexer and a DS3 framer. The line interface of the TE3-CHATT directly connects to a DS3 line interface unit. Protocol data is Data Sheet 25 05.2001 PEB 3456 E TE3-CHATT Overview transferred to the packet RAM via the PCI bus and handled (e.g. for layer3 protocol handling) by the line card processor. An external processor provides control of the integrated T1/E1 framer, M13 multiplexer, DS3 framer and the signalling channels. A mailbox allows the transfer of information between both CPUs. * Linecard Processor Local CPU Packet RAM TE3-CHATT DS3 LIU Back plane Conne ction Route r Back plane Figure 1-2 Data Sheet PCI Bus T3 Linecard System Integration of the TE3-CHATT 26 05.2001 PEB 3456 E Pin Description 2 Pin Description 2.1 Pin Diagram (Top view) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF VSS LD(3) NC22 LD(5) VDD25 LD(11) LD(13) LA(1) VSS LA(4) LA(8) VDD25 LA(10) LA(11) VDD25 AD(0) AD(5) VSS AD(6) AD(9) AD(12) VDD25 PAR STOP NC24 VSS AE LD(2) VDD25 LD(4) NC23 NC20 LD(8) VSS LD(12) LA(0) VDD25 LA(5) VSS LA(9) LA(12) VSS AD(2) VDD25 C/ BE(0) AD(10) VSS AD(14) SERR DEVSE L NC25 VDD25 NC28 AD VSS LD(1) VSS NC17 NC18 VDD3 LD(7) LD(9) VDD3 LD(14) LD(2) LA(6) VDD3 LBHE/ LSIZE0 AD(1) AD(4) AD(8) VDD3 AD(13) C/ BE(1) VDD3 TRDY NC27 VSS NC29 AD(17) AC LINT LCS2 LRD/ LDS VDD3 NC16 NC19 NC21 LD(6) LD(10) VDD3 LD(15) LA(3) LA(7) INTA AD(3) AD(7) VDD3 AD(11) AD(15) PERR IRDY NC26 VDD3 NC31 AD(16) AD(21) AB VDD25 LHLDA/ LBG LWR/ LRD WR LD(0) NC30 FRAM E AD(20) VDD25 AA RES36 LHOLD /LBR VDD3 LRDY C/ BE(2) VDD3 AD(23) IDSEL Y VDD25 VSS LCLK LCS0 AD(18) AD(19) VSS VDD25 W RES38 RES37 LMOD E LCS1 AD(22) VDD3 AD(25) AD(26) V VSS RES43 VDD3 LBGAC K AD24 C/ BE(3) AD(27) VSS U RES44 VDD25 RES40 VDD3 VDD3 AD(28) VDD25 AD(29) T RES48 RES46 RES41 RES39 VSS VSS VSS VSS VSS VSS AD(30) AD(31) REQ GNT R VDD25 VSS RES45 RES42 VSS VSS VSS VSS VSS VSS CLK RST VSS VDD25 P RES50 RES49 RES47 VDD3 VSS VSS VSS VSS VSS VSS SPLOA D VDD3 SPI SPO N TTCLK RES51 VDD3 RES52 VSS VSS VSS VSS VSS VSS SPCLK SPCS RES35 RES34 M VDD25 VSS TRD RES55 VSS VSS VSS VSS VSS VSS RES33 RES32 VSS VDD25 L RES53 RES56 VDD3 RES58 VSS VSS VSS VSS VSS VSS RES29 RES28 RES30 RES31 K RES54 VDD25 RES60 VDD3 RES14 RES15 VDD25 RES16 J VSS RES59 VDD3 RES63 RES11 VDD3 RES13 VSS H RES57 RES61 RES64 VDD3 RES27 RES9 RES10 RES12 G VDD25 VSS RES66 RES68 RES23 RES25 VSS VDD25 F RES62 RES65 VDD3 TMS RES20 VDD3 RES24 RES26 E VDD25 RES69 SCAN NC12 NC0 RES7 RES22 VDD25 D RES67 VSS TDO VDD3 NC15 VDD25 RES71 RLOF RES75 VDD3 RES82 RES83 TC44O RD44/ RD44P C RES70 TCK VSS NC14 VDD25 VDD3 RES74 RAIS VDD3 RES79 TD44N RSPO/ TRCLK TC44 VDD3 VSS RC44 RES85 VSS RES87 VDD25 ROVH CK VDD25 RD44N RES86 VDD25 CTFS RSBD VSS B TRST VDD25 NC13 VSS RES72 RLOS VSS RES76 RES78 VDD25 TD44/ TD44P A VSS VSS TDI RES73 VDD25 RRED RES77 RES80 VSS RES81 RES84 Figure 2-1 Data Sheet CTCLK RSBCK VDD3 TTD RES88 ROVH SYN TSBCK TOVHE N RES90 RES93 RES3 VDD3 NC7 RES8 RES21 ROVH D TOVH D RES89 VDD3 RES2 RES6 VSS NC3 NC1 TOVH CK VSS RES92 RES1 RES5 NC6 VDD25 NC2 TOVHS YNC TSBD RES91 VDD25 RES4 NC4 NC5 VSS TE3-CHATT Pin Configuration 27 05.2001 PEB 3456 E Pin Description 2.2 Pin Definition and functions Signal Type Definitions: The following signal type definitions are partly taken from the PCI Specification Rev. 2. 1: I Input is a standard input- only signal. O Totem Pole Output is a standard active driver. t/s, I/O Tri-State or I/O is a bidirectional, tri-state input/output pin. s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a s/t/s signal any sooner than one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. o/d Open Drain allows multiple devices to share a line as a wire-OR. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. Signal Name Conventions: NCn No-connect Pin n Such pins are not bonded with the silicon. Although any potential at these pins will not impact the device it is recommended to leave them unconnected. No-connect pins might be used for additional functionality in later versions of the device. Leaving them unconnected will guarantee hardware compatibility to later device versions. Reserved Reserved pins are for vendor specific use only and should be connected as recommended to guarantee normal operation. Note: The signal type definition specifies the functional usage of a pin. This does not reflect necessarily the implementation of a pin, e.g. a pin defined of signal type `Input' may be implemented with a bidirectional pad. Data Sheet 28 05.2001 PEB 3456 E Pin Description 2.3 PCI Bus Interface * Pin No. Symbol T3, T4, U1, U3, AD(31:0) V2, W1, W2, V4, AA2, W4, AC1, AB2, Y3, Y4, AD1, AC2, AC8, AE6, AD8, AF6, AC9, AE8, AF7, AD10, AC11, AF8, AF10, AD11, AC12, AE11, AD12, AF11 Data Sheet Input (I) Output (O) Function t/s Address/Data Bus A bus transaction consists of an address phase followed by one or more data phases. When the TE3-CHATT is the bus master, AD(31:0) are outputs in the address phase of a transaction. During the data phases, AD(31:0) remain outputs for write transactions, and become inputs for read transactions. When the TE3-CHATT is bus slave, AD(31:0) are inputs in the address phase of a transaction. During the data phases, AD(31:0) remain inputs for write transactions, and become outputs for read transactions. AD(31:0) are tri-state when the TE3CHATT is not involved in the current transaction. AD(31:0) are updated and sampled on the rising edge of CLK. 29 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function V3, AA4, AD7, AE9 C/BE(3:0) t/s Command/Byte Enable During the address phase of a transaction, C/BE(3:0) define the bus command. During the data phase, C/ BE(3:0) are used as byte enable lines. The byte enable lines are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE(0) applies to byte 0 (LSB) and C/BE(3) applies to byte 3 (MSB). When the TE3-CHATT is bus master, C/ BE(3:0) are outputs. When the TE3-CHATT is bus slave, C/ BE(3:0) are inputs. C/BE(3:0) are tri-stated when the TE3CHATT is not involved in the current transaction. C/BE(3:0) are updated and sampled on the rising edge of CLK. AF4 PAR t/s Parity PAR is even parity across AD(31:0) and C/BE(3:0). PAR is stable and valid one clock after the address phase. PAR has the same timing as AD(31:0) but delayed by one clock. When the TE3-CHATT is Master, PAR is output during address phase and write data phases and input during read data phase. When the TE3-CHATT is Slave, PAR is output during read data phase and input during write data phase. PAR is tri-stated when the TE3-CHATT is not involved in the current transaction. Parity errors detected by the device are indicated on PERR output. PAR is updated and sampled on the rising edge of CLK. Data Sheet 30 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function AB3 FRAME s/t/s Frame FRAME indicates the beginning and end of an access. FRAME is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is deasserted, the transaction is in the final phase. When the TE3-CHATT is bus master, FRAME is an output. When the TE3CHATT is bus slave, FRAME is an input. FRAME is tri-stated when the TE3CHATT is not involved in the current transaction. FRAME is updated and sampled on the rising edge of CLK. AC6 IRDY s/t/s Initiator Ready IRDY indicates the bus master's ability to complete the current data phase of the transaction. It is used in conjunction with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled asserted. During a write, IRDY indicates that valid data is present on AD(31:0). During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. When the TE3-CHATT is bus master, IRDY is an output. When the TE3-CHATT is bus slave, IRDY is an input. IRDY is tristated, when the TE3-CHATT is not involved in the current transaction. IRDY is updated and sampled on the rising edge of CLK. Data Sheet 31 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function AD5 TRDY s/t/s Target Ready TRDY indicates a slave's ability to complete the current data phase of the transaction. During a read, TRDY indicates that valid data is present on AD(31:0). During a write, it indicates the target is prepared to accept data. When the TE3-CHATT is Master, TRDY is an input. When the TE3-CHATT is Slave, TRDY is an output. TRDY is tri-stated, when the TE3-CHATT is not involved in the current transaction. TRDY is updated and sampled on the rising edge of CLK. AF3 STOP s/t/s Stop STOP is used by a slave to request the current master to stop the current bus transaction. When the TE3-CHATT is bus master, STOP is an input. When the TE3-CHATT is bus slave, STOP is an output. STOP is tri-stated, when the TE3-CHATT is not involved in the current transaction. STOP is updated and sampled on the rising edge of CLK. AA1 IDSEL I Initialization Device Select When the TE3-CHATT is slave in a transaction, where IDSEL is active in the address phase and C/BE(3:0) indicates an configuration read or write, the TE3CHATT assumes a read or write to a configuration register. In response, the TE3-CHATT asserts DEVSEL during the subsequent CLK cycle. IDSEL is sampled on the rising edge of CLK. Data Sheet 32 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function AE4 DEVSEL s/t/s Device Select When activated by a slave, it indicates to the current bus master that the slave has decoded its address as the target of the current transaction. If no bus slave activates DEVSEL within six bus CLK cycles, the master should abort the transaction. When the TE3-CHATT is bus master, DEVSEL is input. If DEVSEL is not activated within six clock cycles after an address is output on AD(31:0), the TE3CHATT aborts the transaction. When the TE3-CHATT is bus slave, DEVSEL is output. DEVSEL is tri-stated, when the TE3-CHATT is not involved in the current transaction. AC7 PERR s/t/s Parity Error When activated, indicates a parity error over the AD(31:0) and C/BE(3:0) signals (compared to the PAR input). It has a delay of two CLK cycles with respect to AD and C/BE(3:0) (i.e., it is valid for the cycle immediately following the corresponding PAR cycle). PERR is asserted relative to the rising edge of CLK. AE5 SERR o/d System Error The TE3-CHATT asserts this signal to indicate an address parity error and report a fatal system error. SERR is an open drain output activated on the rising edge of CLK. T2 REQ t/s Request Used by the TE3-CHATT to request control of the PCI bus. It is tri-state during reset. REQ is activated on the rising edge of CLK. Data Sheet 33 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function T1 GNT I Grant This signal is asserted by the arbiter to grant control of the PCI to the TE3CHATT in response to a bus request via REQ. After GNT is asserted, the TE3CHATT will begin a bus transaction only after the current bus Master has deasserted the FRAME signal. GNT is sampled on the rising edge of CLK. R4 CLK I Clock Provides timing for all PCI transactions. Most PCI signals are sampled or output relative to the rising edge of CLK. The PCI clock is used as internal system clock. The maximum CLK frequency is 66 MHz. R3 RST I Reset An active RST signal brings all PCI registers, sequencers and signals into a consistent state. All PCI output signals are driven to high impedance. AC13 INTA o/d Interrupt Request When an interrupt status is active and unmasked, the TE3-CHATT activates this open-drain output. Data Sheet 34 05.2001 PEB 3456 E Pin Description 2.4 SPI Interface * Pin No. Symbol P2 SPI I SPI Serial Input SPI is a data input pin, where data coming from an external EEPROM is shifted in. SPI is sampled on the rising edge of SPCLK. A pull-up resistor is recommended if the SPI interface is not used. P1 SPO O SPI Serial Output SPO is a push/pull serial data output pin. Opcodes, byte addresses and data is updated on the falling edge of SPCLK. It is tri-state during reset. N4 SPCLK O SPI Clock Signal SPCLK controls the serial bus timing of the SPI bus. SPCLK is derived from the PCI bus clock with a frequency of 1/78 of the PCI bus clock. It is tri-state during reset. N3 SPCS O SPI Chip Select SPCS is used to select an external EEPROM. It is tri-state during reset. P4 SPLOAD I Enable SPI Load Functionality Connecting SPLOAD to VDD3 enables the SPI bus after reset. In this case parts of the PCI configuration space can be configured via an external EEPROM. Data Sheet Input (I) Function Output (O) 35 05.2001 PEB 3456 E Pin Description 2.5 Local Microprocessor Interface * Pin No. Symbol Input (I) Output (O) Function W24 LMODE I Local Bus Mode By connecting this pin to either VSS or VDD3 the bus interface can be adapted to either Intel or Motorola environment. LMODE = VSS selects Intel bus mode. LMODE = VDD3 selects Motorola bus mode. Y24 LCLK O Local Clock Reference output clock derived from the PCI clock. AE13, AF13, AF14, AE14, AF16, AC14, AD15, AE16, AF17, AC15, AD16, AF19, AE18 LA(12:0) I/O Address bus These input address lines select one of the internal registers for read or write access. Note: Only LA(7:0) are evaluated during read/write accesses to the TE3-CHATT. In local bus master mode the address lines are output. If local bus master functionality is disabled these pins are input only. AC16, AD17, AF20, AE19, AF21, AC18, AD19, AE21, AD20, AC19, AF23, AE24, AF25, AE26, AD25, AB23 LD(15:0) I/O Data Bus Bidirectional tri-state data lines. Y23 LCS0 Data Sheet I Chip Select This active low signal selects the TE3CHATT as bus slave for read/write operations. 36 05.2001 PEB 3456 E Pin Description Pin No. AC24 AB24 AA23 Symbol Input (I) Output (O) Function LRD I/O or LDS I/O Read (Intel Bus Mode) This active low signal selects a read transaction. Data strobe (Motorola Bus Mode) This active low signal indicates that valid data has to be placed on the data bus (read cycle) or that valid data has been placed on the data bus (write cycle). LWR I/O or LRDWR I/O LRDY I/O Write Enable (Intel Bus Mode) This active low signal selects a write cycle. Read Write Signal (Motorola Bus Mode) This input signal distinguishes write from read operations. Ready (Intel bus mode) This signal indicates that the current bus cycle is complete. The TE3-CHATT asserts LRDY during a read cycle if valid output data has been placed on the data bus. In write direction LRDY will be asserted when input data has been latched. In local bus master mode TE3-CHATT evaluates LRDY to finish a transaction. Data Transfer Acknowledge (Motorola bus mode) This active low input indicates that a data transfer may be performed. During a read cycle data becomes valid at the falling edge of DTACK. The data is latched internally and the bus cycle is terminated. During a write cycle the falling edge of DTACK marks the latching of data and the bus cycle is terminated. or DTACK Data Sheet I/O 37 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Output (O) Function I/od Interrupt Request This line indicates general interrupt requests of the layer one functions or the mailbox. The interrupt sources can be masked via registers. In local bus master mode the TE3-CHATT can monitor external interrupts indicated via LINT. AC26 LINT AC25, W23 LCS2, LCS1 O Chip Select 2, 1 These signals select external peripherals when TE3-CHATT is the local bus master. As long as the local bus master functionality is disabled these outputs are set to tri-state. AD13 LBHE O Byte High Enable (Intel Bus Mode) In local bus master mode this signal indicates a data transfer on the upper byte of the data bus LD(15:8). This signal has no function in slave mode. When local bus master functionality is disabled this output is tri-state. Byte Access (Motorola Bus Mode) In local bus master mode this signal indicates byte transfers. This signal has no function when the TE3CHATT is local bus slave. When local bus master functionality is disabled this output is tri-state. or AA25 LSIZE0 O LHOLD O Bus Request (Intel Bus Mode) This pin indicates a requests to become local bus master. When local bus master functionality is disabled this output is tri-state. Bus Request (Motorola Bus Mode) LBR indicates a request to become local bus master. When local bus master functionality is disabled this output is set to tri-state. or LBR Data Sheet O 38 05.2001 PEB 3456 E Pin Description Pin No. AB25 Symbol LHLDA Input (I) Output (O) Function I Hold (Intel Bus Mode) LHLDA indicates that the external processor has released control of the local bus. Bus Grant (Motorola Bus Mode) LBG indicates that the TE3-CHATT may access the local bus. or V23 2.6 LBG I LBGACK O Bus Grant Acknowledge (Motorola Bus Mode) LBGACK is driven low when the TE3CHATT has become bus master. When local bus master functionality is disabled this output is tri-state. Serial Interface * Pin No. Symbol D12 CTCLK I Common Transmit Clock CTCLK is the external transmit clock for the T1 or E1 tributaries configured in external timing mode. A11 CTFS I Common Transmit Frame Synchronization CTFS is used to synchronize the T1/E1 transmit lines, which are clocked with CTCLK in external timing mode. If not used CTFS should be connected to VSS. Data Sheet Input (I) Function Output (O) 39 05.2001 PEB 3456 E Pin Description Pin No. Symbol C15 RSPO Input (I) Function Output (O) O Regenerated Sync Pulse RSPO supports debugging of the on-chip T1/E1 framing function. If the T1/E1 framer achieved synchronization, the internal synchronization pulse of one selected T1/E1 framer can be monitored on RSPO. Test Receive Clock In serial test mode the receive clock of one selected T1/E1 interface is directly feed to this output. or TRCLK O M24 TRD O Test Receive Data In serial test mode the incoming data stream of one T1/E1 tributary is directly feed to this output. Test receive data is updated on the falling edge of the TRCLK. N26 TTCLK I Test Transmit Clock In serial test mode this clock provides the clock reference for the tributary provided via TTD. C12 TTD I Test Transmit Data In serial test mode the data stream provided via TTD replaces the E1/T1 data stream of the selected tributary. TTD is sampled on the rising edge of the TTCLK. C14 TC44 I DS3 Transmit Clock Input This clock provides a reference clock for the DS3 interface. The frequency of this clock is nominally 44.736 MHz. D14 TC44O O DS3 Transmit Clock Output This output is a buffered version of the selected transmit clock which can be set to RC44 or TC44. Data Sheet 40 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Function Output (O) B16 TD44 D3TCFG.UTD is used to select the operating mode for this pin. DS3 Transmit Data In Single rail mode, this unipolar serial data output represents the DS3 signal. TD44 is updated on the falling or rising edge of TC44. DS3 Transmit Positive Pulse In dual-rail mode this pin represents the positive pulse of the B3ZS encoded DS3 signal. TD44P is updated on the falling edge or rising edge of TC44O. O or TD44P O C16 TD44N O DS3 Transmit Negative Pulse In dual-rail mode this pin represents the negative pulse of the B3ZS encoded DS3 signal. TD44N is updated on the falling or rising edge of TC44O. B14 RC44 I DS3 Receive Clock Input The frequency of this clock is nominally 44.736 MHz. D3RCFG.URD is used to select the operating mode for this pin. DS3 Receive Data This unipolar serial data input represents the DS3 signal. RD44 is sampled on the falling or rising edge of RC44. DS3 Receive Positive Pulse In dual-rail mode this pin represents the positive pulse of the B3ZS encoded DS3 signal. RD44P is sampled on the falling or rising edge of RC44. D13 RD44 I or A14 Data Sheet RD44P I RD44N I DS3 Receive Negative Pulse In dual-rail mode this pin represents the negative pulse of the B3ZS encoded DS3 signal. RD44 is sampled on the falling or rising edge of RC44. 41 05.2001 PEB 3456 E Pin Description Pin No. Symbol A21 RRED O Received RED This signal is asserted whenever the DS3 receive framer is in RED alarm state. B21 RLOS O Received LOS This signal is asserted whenever the received DS3 bit stream contained at least 175 consecutive `0's. D19 RLOF O Receive LOF This signal is asserted whenever the DS3 receive framer is in 'Loss of frame' state. C19 RAIS O Received AIS This signal is asserted whenever the DS3 receive framer is in AIS state. B8 TOVHCK O Transmit Overhead Bit Clock This signal provides the bit clock for the DS3 overhead bits of the outgoing DS3 frame. TOVHCK is nominally a 526 kHz clock. C8 TOVHD I Transmit Overhead Data The overhead bits of the outgoing DS3 frame can be provided via TOVHD. Transmit overhead data is sampled on the rising edge of TOVHCK and those bits which are enabled by TOVHEN are inserted in the overhead bit positions of the DS3 frame. D8 TOVHEN I Enable Transmit Overhead Data The asserted TOVHEN signal marks the bits to be inserted in the DS3 frame. TOVHEN is sampled together with TOVHD on the rising edge of TOVHD. Data Sheet Input (I) Function Output (O) 42 05.2001 PEB 3456 E Pin Description Pin No. Symbol A8 TOVHSYN I/O Transmit Overhead Synchronization TOVHSYN provides the means to align TOVHD to the first M-frame of the DS3 signal. If operated in output mode TOVHSYN it is asserted when the X-bit of the 1st subframe of the DS3 overhead bits has to be inserted via TOVHD. TOVHSYN is updated on the rising edge of TOVHCK. If operated in input mode TOVHSYN must be asserted together with the X-bit of the 1st subframe of the DS3 signal which is input on TOVHD. TOVHSYN is sampled on the rising edge of TOVHCK. D9 TSBCK O Transmit Stuff Bit Clock This signal provides the bit clock for DS3 stuff bit data. Transmit stuff bit data is sampled on the rising edge of TSBCK. A7 TSBD I Transmit Stuff Bit Data Data provided via TSBD is optionally inserted in the stuffed bit positions of the DS3 signal. TSBD is sampled on the rising edge of TSBD. This function is available in M13 asynchronous format only. B9 ROVHCK O Receive Overhead Bit Clock This signal provides the bit clock for the received DS3 overhead bits. ROVHCK is nominally a 526 kHz clock. C9 ROVHD O Receive Overhead Data ROVHD contains the extracted overhead bits of the DS3 frame. It is updated on the rising edge of ROVHCK. C10 ROVHSYN O Receive Overhead Synchronization ROVHSYN is asserted while the X-bit of the 1st subframe of the DS3 overhead bits is provided via ROVHD. It is sampled on the rising edge of ROVHCK. Data Sheet Input (I) Function Output (O) 43 05.2001 PEB 3456 E Pin Description Pin No. Symbol D11 RSBCK O Receive Stuff Bit Clock This signal provides the bit clock for DS3 stuff bit data. Transmit stuff bit data is sampled on the rising edge of TSBCK. A10 RSBD O Receive Stuff Bit Data ROVHD provides data which was inserted in the stuffed bit positions of the DS3 signal. RSBD is updated on the rising edge of RSBD. This function is available in M13 asynchronous format only. 2.7 Input (I) Function Output (O) Test Interface * Pin No. Symbol C25 TCK I JTAG Test Clock This pin is connected with an internal pullup resistor. F23 TMS I JTAG Test Mode Select This pin is connected with an internal pullup resistor. A24 TDI I JTAG Test Data Input This pin is connected with an internal pullup resistor. D24 TDO O JTAG Test Data Output B26 TRST I JTAG Test Reset This pin is connected with an internal pulldown resistor. E24 SCAN I Full Scan Path Test When connected to VDD3 the TE3-CHATT works in a vendor specific test mode. It is recommended to connect this pin to VSS. Data Sheet Input (I) Function Output (O) 44 05.2001 PEB 3456 E Pin Description 2.8 Power Supply, Reserved Pins and No-connect Pins * Pin No. Symbol Input (I) Function Output (O) AF1, AE7, AF9, AE12, VSS AE15, AF18, AE20, AF26, AD3, AD24, AD26, Y2, Y25, V1, V26, R2, T12, T11, R12, R11, T14, T13, R14, R13, T16, T15, R16, R15, R25, P12, P11, N12, N11, P14, P13, N14, N13, P16, P15, N16, N15, M2, M12, M11, L12, L11, M14, M13, L14, L13, M16, M15, L16, L15, M25, J1, J26, G2, G25, C3, C24, D25, A1, B7, A9, B12, B15, A18, B20, A26, B23, A25 I Ground 0V All pins must have the same level. AE2, AF5, AE10, AF12, VDD25 AF15, AE17, AF22, AE25, AB1, AB26, Y1, Y26, U2, U25, R1, R26, M1, M26, K2, K25, G1, G26, E1, E26, B2, A5, B10, A12, A15, B17, A22, B25, C22, D21 I Supply Voltage 2.5V 0.25V All pins must have the same level. AC4, AD6, AD9, AC10, VDD3 AD14, AD18, AC17, AD21, AC23, AA3, AA24, W3, U4, V24, U23, P3, P23, N24, L24, J3, K23, J24, H23, F3, F24, D4, C6, D10, C13, D17, C18, C21, D23 I Supply Voltage 3.3V 0.3V All pins must have the same level. Data Sheet 45 05.2001 PEB 3456 E Pin Description Pin No. Symbol Input (I) Function Output (O) B5, C5, D5, A4, B4, C4, RES1..16, E3, D2, H3, H2, J4, H1, RES20..93 J2, K4, K3, K1, F4, D1, E2, G4, F2, G3, F1, H4, L3, L4, L2, L1, M3, M4, N1, N2, AA26, W25, W26, T23, U24, T24, R23, V25, U26, R24, T25, P24, T26, P25, P26, N25, N23, L26, K26, M23, L25, H26, L23, J25, K24, H25, F26, J23, H24, F25, G24, D26, G23, E25, C26, D20, B22, A23, C20, D18, B19, A20, B18, C17, A19, A17, D16, D15, A16, B13, A13, B11, C11, C7, D7, A6, B6, D6 Reserved Pins 1..16, 20..93 E4, C1, B1, C2, A3, A2, NC0..7 B3, D3, E23, B24, C23, NC12..31 D22, AC22, AD23, AD22, AC21, AE22, AC20, AF24, AE23, AF2, AE3, AC5, AD4, AE1, AD2, AB4, AC3 No-connect Pins 0..7, 12..31 Data Sheet A pull-up resistor to VDD3 is recommended. It is recommended connect these pins. 46 not to 05.2001 PEB 3456 E General Overview 3 General Overview 3.1 Functional Overview TE3-CHATT The TE3-CHATT is a highly integrated WAN protocol controller that performs HDLC, PPP and transparent (TMA) protocol processing on 256 full duplex serial channels for a channelized or unchannelized DS3 link. The device provides the framing functions for 28 T1 links or 21 E1 links. Signalling controller functions for DS3, T1 and E1 mode are integrated as well. The following operating modes are provided (assuming a PCI clock frequency of 33 MHz or more): * 28 times T1 signals operating at 1.544 MBit/s mapped into M13 asynchronous format or C-bit parity format * 21 times E1 signals operating at 2.048 MBit/s mapped into ITU-T G.747 compliant signal. * Full payload rate DS3 signal in C-bit parity format The serial interface operates in unipolar or dual-rail mode and connects directly to available DS3 LIUs. Each T1 or E1 tributary can be operated in external timing mode, where the tributary is clocked with the common transmit clock CTCLK, or in looped timing mode, where data of the selected tributaries is sent synchronous to the incoming receive clock. A variety of loop modes is provided to support remote as well as inloop testing of the device. Remote loops are provided on DS3-, DS2-, DS1- or payload level. Two bus interfaces, a PCI Rev. 2.1 compliant bus interface and a 16 bit Intel/Motorola style bus interface, connect the device to system environment. Device configuration and channel operation is provided through the PCI bus interface, whereas the 16 bit bus interface provides access to the framing functions and the signalling controller. The TE3CHATT supports PCI PnP capability by loading the subsystem ID and the subsystem vendor ID via a SPITM interface into the PCI configuration space. Data Sheet 47 05.2001 PEB 3456 E General Overview 3.2 Block Diagram * TC44 Clock References TD44N TD44P TC44O RD44N RD44P RC44 DS3 interface unipolar or B3ZS encoded Overhead Access DS3 framer M13 Multiplexer 1 BERT 2 28 CTCLK T1/E1 Interface/Unchannelized Interface TestPort synchronization JTAG interface Data management unit PCI Interface Local Bus Interface PCI Figure 3-1 3.3 Message FIFO Interrupt FIFO Initiator bus SPITM Interface Interrupt bus II Configuration bus I Internal Buffer Facility data link Mailbox/ Bridge SPITM Interrupt controller Protocol handler Configuration bus I Framer Interrupt bus I JTAG Loop buffer local uP interface TE3-CHATT Block Diagram Internal Interface The device consists of several macro functions as shown in Figure 3-1. The internal modules are connected by busses/signals according to Infineons on-chip bus. The main busses are: * The initiator bus, on which the DMA requests of the data management units and the interrupt controller are arbitrated and funneled into the PCI interface. Data Sheet 48 05.2001 PEB 3456 E General Overview * The configuration busses, which serve as the standard programming interface to access the chip internal registers and functions either via PCI bus or via the local bus interface. * The interrupt busses, which collect all interrupt information and forward them to the corresponding interrupt handler. The chip's core functions are all operated with the PCI clock. Transfers between clocking regions (serial clocks and system clock) are implemented only in the serial interface. 3.4 Block Description The following section gives a brief overview to the function of each block. For a detailed description of each function refer to "Functional Description" on Page 53. T1/E1 Interface/Unchannelized Interface The T1/E1 interface consists of the subfunctions receive and transmit. This block provides the function of serial/parallel and parallel/serial conversion for up to 28 incoming and up to 28 outgoing tributaries of the DS3 signal. Serial data is transferred between the internal clocking system, which is derived from the PCI clock, and the various line clocks. This provides a unique clocking scheme on the internal interfaces. The aggregate bandwidth of all enabled tributaries can be up to 45 Mbit/s in each direction. Time slot assigner The time slot assigner exchanges data with the serial interface on a 8 bit parallel bus, thus funneling all data of up to 28 interfaces. The time slot assigner provides freely programmable mapping of any time slot or any combination of time slots to 256 logical channels. A programmable mask can be provided to allow subchanneling of the available time slots which allows channel data rates starting at 8kbit/s. At the protocol machine interface the time slot assigner and the protocol machine exchanges channel oriented data (8 bit) together with the time slots masks. Protocol handler Two protocol machines, one for receive direction and one for transmit direction, provide protocol handling for up to 256 logical channels and a maximum serial aggregate data rate of up to 45 Mbit/s per direction. The protocol machines implement four modes, which can be programmed independently for each logical channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and Transparent Mode A, including frame synchronous TMA. Data Sheet 49 05.2001 PEB 3456 E General Overview Internal buffer The internal buffers provides channelwise buffering of raw (unformatted/deformatted) data for 256 logical channels. Channel specific thresholds can be programmed independently in transmit and receive direction. In order to avoid transmit underrun conditions each transmit channel has two control parameters for smoothing the filling/ emptying process (transmit forward threshold, transmit refill threshold). In receive direction each channel has a receive burst threshold. To avoid unnecessary waste of bus bandwidth, e.g. in case of transmission errors, the receive buffer provides the capability to discard frames which are smaller than a programmable threshold. Data management units The data management units provide direct data transfer between the system memory and the internal buffers. Each channel has an associated linked list of descriptors, which is located in system memory and handled by the data management units. This linked list is the interface between the system processor and the TE3-CHATT for exchange of data packets. The descriptors and the data packets can be stored arbitrarily in 32 bit address space of system memory, thus allowing full scatter/gather assembly of packets. In order to optimize PCI bus utilization, each descriptor is read in one burst and held on-chip afterwards. Interrupt controller Two interrupt controllers manage internal interrupts. Interrupts from the mailbox, the framing engines and the signalling controller are passed in the form of interrupt vectors to an internal interrupt FIFO which can be read from the local bus. All system, port and channel related interrupt information is passed to the main interrupt controller which is connected to the PCI system. A programmable DMA with nine channels stores these interrupts in the form of interrupt vectors in different interrupt queues in system memory. PCI interface The PCI interface unit combines all DMA requests from the internal data management unit and the interrupt controller and translates them into PCI Rev. 2.1 compliant bus accesses. The PCI interface optionally includes the function of loading the subsystem vendor ID and the subsystem ID from an external SPI compliant EEPROM. Mailbox, internal bridge and global registers The mailbox is used to exchange data between the PCI attached microprocessor and the local bus microprocessor and provides a doorbell function between the two interfaces. Controlled by an arbiter an internal bridge connects the configuration bus I and the configuration bus II. It is therefore possible to access the "layer one" registers from the Data Sheet 50 05.2001 PEB 3456 E General Overview PCI interface directly. Thus the device could also be operated without a local microprocessor connected to it, e.g. for debugging purposes. It is NOT possible to access the configuration bus I and therefore the 'HDLC' registers or the PCI bridge from the local bus. Local bus interface The local bus interface provides access between the local microprocessor and the onchip configuration bus II, in order to access the registers of the on-chip M13 multiplexer, DS2/DS3 framer, T1/E1 framer, the registers of the signalling controller and the mailbox. The local bus interface provides a switchable Intel-style or Motorola-style processor interface. M23 multiplexer/demultiplexer and DS3 framer In channelized operating modes the M23 multiplexer/demultiplexer maps/demaps seven DS2 signals into/from M13 asynchronous format or C-bit parity format. In unchannelized mode one logical input stream is mapped into the information bits of the DS3 stream according to ANSI T1.107. The DS3 framer performs frame and multiframe alignment in receive direction and inserts the frame and multiframe alignment bits. Performance monitors provide for counting of framing bit errors, parity errors, CP-bit errors, far end block errors, excessive zeroes or line code violations. The framer detects loopback requests and allows insertion of loopback requests under microprocessor control. M12 multiplexer/demultiplexer and DS2 framer The M12 multiplexer/demultiplexer operates in two modes. It maps either 28 T1 signals or 21 E1 signals into/from seven ANSI T1.107 or ITU-T G.747 compliant DS2 signals. It performs inversion of the second and fourth DS1 signal. The DS2 framer performs frame and multiframe alignment in receive direction and vice versa inserts the framing bits according to ANSI T1.107 or ITU-T G.704. It detects loopback requests or enables insertion of loopback requests under microprocessor control. T1/E1 framer Synchronization is achieved with the on-chip framing function. T1/E1 mode is supported for up to 28 ports. Once the framer achieved synchronization for a line, that is the frame alignment information in the incoming bit stream has been identified correctly, it informs the port interface and the facility data link about the frame position. In transmit direction the framing bits are inserted according to T1 F4 format, T1 SF (F12) format, T1 ESF (F24) format, E1 doubleframe format or E1 CRC-4 multiframe format. Performance monitors provide for counting framing errors, CRC errors, block errors, E-bit errors or PRBS bit errors. The framer detects loopback requests and allows insertion of loopback requests or pseudo-random bit sequences under microprocessor control. Data Sheet 51 05.2001 PEB 3456 E General Overview Facility data link, Signaling controller The facility data link exchanges the `F-bits' of the T1 links or the Sa-bits of time slot zero of the E1 links with the framer block and it provides the function of HDLC formatting or BOM mode in receive and transmit direction. The signalling controller also provides access to the DS3 signalling bits (Far End Alarm and Control Channel, Path Maintenance Data Link Channel). Message FIFO For intermediate buffering of data link messages two FIFOs are integrated, one for transmit and one for receive direction. Each FIFO provides two pages of 32 bytes buffer per line and direction. JTAG Boundary Scan logic according to IEEE 1149.1. Data Sheet 52 05.2001 PEB 3456 E Functional Description 4 Functional Description 4.1 Port Handler The port handler is the interface between the serial ports and the chip internal protocol and framing functions. It converts incoming serial data into parallel data for further internal processing and in the outgoing direction it converts parallel data into a serial bit stream. The TE3-CHATT provides one port for operation at DS3 signal speeds. It provides unipolar data transmission or B3ZS encoded data transmission. The system interface consists of one receive clock input and either one receive data input in unipolar mode or two receive data inputs in dual-rail mode, one for the positive pulse and one for the negative pulse. In transmit direction the system interface is build of one transmit clock input and one or two transmit data outputs. CTCLK 28 1 RD44P RD44N M12 multiplexer stage + DS2 framer RC44 DS3 looped timing mode TD44N DS3 framer TD44P M23 multiplexer stage TC44O T1/E1 Transmit Path tributary looped timing mode 7 1 TC44 external timing mode * T1/E1 Receive Path Overhead Access Figure 4-1 Data Sheet Port configuration in M13 mode 53 05.2001 PEB 3456 E Functional Description 4.1.1 Local Port Loop Local port loops are provided on DS3, DS2 and DS1 level on a per port/tributary basis. In the local loop the outgoing bit stream of a port/tributary is mirrored to the receive data path. This allows to prepare data in system memory, which is processed by the TE3CHATT in transmit direction, mirrored to the respective receiver and stored in system memory again. In order to ensure that the local port loop works even without incoming receive clock, each receiver looped uses the corresponding transmit clock. * RC44 RD44P RD44N TC44O TD44P TD44N DS3 Receive Framer M23 Demux DS2 Receive Framer DS2 Demux T1/E1 Receive Framer DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer DS2 Multiplexer T1/E1 Transmit Framer DS3 Receive Framer M23 Demux DS2 Receive Framer DS2 Demux T1/E1 Receive Framer DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer DS2 Multiplexer T1/E1 Transmit Framer Protocol Data Protocol Data TC44 RC44 RD44P RD44N TC44O TD44P TD44N Protocol Data Protocol Data TC44 Figure 4-2 4.1.2 Local Port Loops in M13 mode Remote Line Loops The TE3-CHATT supports remote line loops in different stages of the M13 data path. In DS3 line loopback mode the incoming DS3 signal is mirrored and placed on the DS3 signal output. While operating in DS3 line loopback mode, the incoming receive clock RCLK is used to update outgoing transmit data. In DS2 line loopback mode one arbitrarily selectable DS2 signals is looped in the M12 stage of the TE3-CHATT. The T1/ E1 line loopback mode mirrors one or more incoming lines. Transmit data coming from the transmit data path is replaced with the mirrored data stream. Data Sheet 54 05.2001 PEB 3456 E Functional Description * RC44 RD44P RD44N DS3 Receive Framer M23 Demux DS2 Receive Framer M12 Demux T1/E1 Receive Framer DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer M12 Multiplexer T1/E1 Transmit Framer DS3 Receive Framer M23 Demux DS2 Receive Framer DS2 Demux T1/E1 Receive Framer DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer DS2 Multiplexer T1/E1 Transmit Framer DS3 Receive Framer M23 Demux DS2 Receive Framer DS2 Demux T1/E1 Receive Framer DS3 Transmit Framer M23 Multiplexer DS2 Transmit Framer DS2 Multiplexer T1/E1 Transmit Framer TC44O TD44P TD44N TC44 RC44 RD44P RD44N TC44O TD44P TD44N TC44 RC44 RD44P RD44N TC44O TD44P TD44N Protocol Data Protocol Data Protocol Data Protocol Data Protocol Data Protocol Data TC44 Figure 4-3 Remote Line Loops The T1/E1 line loopback mode mirrors one or more incoming lines. Transmit data coming from the transmit data path is replaced with the mirrored data stream. While T1/ E1 line loop is closed the transmit framer and the protocol machines are disabled. Data Sheet 55 05.2001 PEB 3456 E Functional Description 4.1.3 Test Breakout The test breakout function provides the capability to multiplex one of the incoming 28 receive tributaries to the outgoing test receive port, where an external T1/E1 analyzer can be easily connected to. A selectable incoming tributary signal can be mapped to the test receive port where RCLK(x) is mapped to TRCLK and RD(x) to TRD. TRD is updated on the falling edge of TRCLK. In the opposite direction one of the 28 transmit tributaries can be replaced with the incoming test transmit data input TTD and the test transmit clock input TTCLK. TTD is sampled on the rising edge of TTCLK. RD44N TC44 TC44O TD44P TD44N Figure 4-4 DS2 Receive Framer + M12 Demux DS3 Transmit Framer + M23 Multiplexer DS2 Transmit Framer + M12 Multiplexer RCLK(27) RD(27) RCLK(0) RD(0) TCLK(27) TD(27) TCLK(0) TD(0) TTCLK TTD To/From time slot assigner, T1/E1Framer RC44 RD44P DS3 Receive Framer + M23 Demux TRD TRCLK * Test Breakout 4.2 Time slot Handler 4.2.1 Channelized Modes The time slot handler assigns any combination of time slots of ports configured in T1 or E1 mode to logical channels. The assigned time slots are connected internally and the bit stream of one logical channel is mapped continuously over the selected time slots. Data Sheet 56 05.2001 PEB 3456 E Functional Description Since the receiver and the transmitter operate independently of each other, the assignment of time slots to logical channels can be done separately in receive and transmit direction. Any time slot can be assigned to any channel and any sequence of time slots can be assigned to one channel. In normal operation each time slot consists of eight bits and all bits are used for data transmission. An available mask function provides the capability to mask selected bits, which in turn are disabled for data transmission. This provides the possibility to operate time slots with less than 64 kBit/s throughput. So, instead of mapping the bit stream of one logical channel over all bits of the assigned time slots, the bit stream is mapped continuously over all unmasked bits of the time slots belonging to that channel. Masked bits are transmitted as `1'. In receive direction masked data bits are discardedFigure 4-5 shows a simple assignment process. In this case one port is configured in E1 mode and time slots two and three are assigned to logical channel 5. The bit mask of time slot two is set to FEH, which disables bit zero of that time slot, and the bit mask of the third time slot is set to FDH, which disables bit one. Data Sheet 57 05.2001 PEB 3456 E Functional Description * Time Frame 1 0 1 2 7 0 1 0 1 Frame 2 3 29 30 31 0 1 2 Timeslot 2 6 2 3 4 1 1 3 29 30 31 Timeslot 3 5 6 7 0 1 1 1 1 0 Timeslot Mask 1 2 1 3 4 5 6 7 1 1 0 1 Timeslot Mask 1 1 1 1 Example configuration: Port three in mode E1. Timeslot 2 and 3 are assigned to channel 5. Bit 0 of timeslot 2 and bit 1 of timeslot 3 are masked. Programming sequence: 1. Port mode configuration Register Data 31 0 PMIAR PMR 3H Select port 3 E1 mode 8H 2. Timeslot assignment TSAIA TSAD 3H 5H TSAIA TSAD Figure 4-5 4.2.2 2H 11111110 3H 5H 3H 11111101 Select port 3, timeslot 2 Set channel 5, mask Select port 3, timeslot 3 Set channel 5, mask Time slot Assignment in Channelized Modes Unchannelized Mode In unchannelized mode the complete incoming and outgoing serial bit stream belongs to one logical DS3 channel. To operate the link in unchannelized mode tributary zero (port zero) has to be programmed for unchannelized operation and all `time slots', that is time slot 0 to 23 must be assigned to one channel. Additionally the M13 multiplexer must be switched into unchannelized DS3 mode. The function of bit masks, which is available for the T1/E1 tributaries, is not available in unchannelized mode. Data Sheet 58 05.2001 PEB 3456 E Functional Description 4.3 Data Management Unit Each packet or part of a packet is referenced by a descriptor. The descriptors form a link list, thus connecting all packets together. Packet data as well as descriptors are located in system memory. Both the TE3-CHATT and the system CPU operate on these data structures. Each logical channel has its dedicated linked list of descriptors, one for receive direction and one for transmit direction. This type of data structure allows channel specific memory organization which can be specified by the system processor. It provides an optimized way to transfer data packets between the system processor and the TE3CHATT. The TE3-CHATT has a flexible DMA controller to transfer data either from the internal receive buffer to the shared memory (receive direction) or from the shared memory to the internal transmit buffer (transmit direction). Each DMA works on one linked list. Each linked list located in system memory is associated with one of the 256 transmit channels or one of 256 receive channels. The address generator of the DMA controller supports full link list handling. Descriptors are stored independently from the data buffers, thus allowing full scatter/gather assembly and disassembly of data packets. 4.3.1 Descriptor Concept A descriptor is used to build a linked list, where each member of the linked list points to a data section. A descriptor consists of four DWORDS1). The first three DWORDS, containing link and packet information, are provided by the system CPU and the last DWORD contains status information, which is written when the TE3-CHATT has finished operation on a descriptor. The data section itself can be of any size up to the maximum size of 65535 bytes per descriptor and is defined in the first DWORD of a descriptor. Each logical data packet can be split into one or multiple parts, where each part is referenced by one descriptor, and all parts are referenced by a linked list of descriptors. The descriptor containing the last part of a data packet is marked with a frame end bit. The descriptor following the marked descriptor therefore contains the beginning of the next data packet (Figure 4-6). The last descriptor in a linked list is marked with a hold indication. For ease of programming the transmit descriptor and the receive descriptor are structured the same way, thus allowing to link a receive descriptor directly into the linked list of the transmit queues with minimum descriptor processing. 1) Data Sheet 59 05.2001 PEB 3456 E Functional Description * Linked list in system memory in little endian mode Data on serial link 7EH Flag 00H 01H 00 0 0 0CH 02H Next Descriptor Pointer 03H Data Pointer 01 00000 04H 0CH 03H 02H 01H 00H 05H 07H 06H 05H 04H 06H 0BH 0A H 09H 08H 07H 08H 09H 00 0 1 10H 0A H Next Descriptor Pointer 0BH Data Pointer 11 00000 Payload 0CH 09H 0FH 0EH 0DH 0CH 0DH 13H 12H 11H 10H 0EH 14H 0FH 10H 11H 01 0 2 08H 12H Next Descriptor Pointer 13H Data Pointer 01 00000 14H 08H CRC CRC 7EH Figure 4-6 CRC Flag Descriptor Structure Although the data management unit works 32-bit oriented, it is possible to begin a transmit data section at an uneven address. The two least significant bits of the transmit data pointer determine the beginning of the data section and the number of bytes in the first DWORD of the data section, respectively. In receive direction the address of the data sections must be DWORD aligned. 4.3.2 Receive Descriptor Each receive descriptor is initialized by the host CPU and stored in system memory as part of a linked list. The TE3-CHATT reads a descriptor, when requested to do so from the host by a receive command or after branching from one receive descriptor to the next receive descriptor. Each receive descriptor contains four DWORDs, where the first three DWORDs contain link and packet information and the last DWORD contains status information. Once the descriptor is processed the status information will be written back to system memory by the TE3-CHATT (Receive status update). When the TE3-CHATT Data Sheet 60 05.2001 PEB 3456 E Functional Description branches to a new descriptor it reads the link and packet information entirely and stores it in its on-chip channel database. Table 4-1 Receive Descriptor Structure DWORD ADDR. 31 00H 0 30 29 HOLD RHI 28 27 26 25 24 23 22 OFFSET(2:0) 0 0 0 0 04H 21 20 19 18 17 16 DescriptorID(5:0) NextReceiveDescriptorPointer(31:2) 08H ReceiveDataPointer(31:2) 0CH FE C 0 0 0 0 0 0 0 0 0 DWORD ADDR. 15 14 13 12 11 10 9 8 7 6 5 MFL RFOD CRC ILEN RAB 4 3 2 1 0 NO(15:0) 00H 04H NextReceiveDescriptorPointer(31:2) 0 0 08H ReceiveDataPointer(31:2) 0 0 0CH HOLD BNO(15:0) Hold indication HOLD indicates that a descriptor is the last element of a linked list containing valid information. 0 Next descriptor is available in the shared memory. After checking the HOLD bit the data management unit branches to the next receive descriptor. 1 This descriptor is the last one that is available for a channel. This means that the data section where this descriptor points to is the last data section which is available for data storage. After processing of descriptor has finished, the data management unit repolls the descriptor one time to check if HOLD has already been cleared. If HOLD is still set the corresponding receive channel is deactivated as long as the system CPU does not request a new activation via a 'Receive Hold Reset' command or forces the TE3-CHATT to branch to a new linked list via a 'Receive Abort/Branch' command. Note: When repolling a descriptor the TE3-CHATT checks the HOLD bit and the bit field NextReceiveDescriptorPointer. All other information are NOT updated in the internal channel database. Data Sheet 61 05.2001 PEB 3456 E Functional Description RHI Receive Host Initiated Interrupt This bit indicates that the TE3-CHATT shall generate a 'Receive Host Initiated' interrupt vector after it has finished processing the descriptor. OFFSET 0 Data management unit does not generate an interrupt vector after it has processed the receive descriptor. 1 Data management unit generates an interrupt vector, as soon as all data bytes are transferred into the current data section and the status information is updated. Offset of unused data section. This bit field allows to reserve memory space in increments of DWORDs for an additional header. If the marked descriptor is the first one of a new packet the data management unit will write data at the address ReceiveDataPointer+4xOFFSET. Note: Offset x 4 must be smaller than NO. Note: This option is not available in transparent mode. DescriptorID This bit field is read by the data management unit and written back in the corresponding interrupt status of a channel interrupt vector which is generated by the data management unit. This value provides a link between the descriptor and the corresponding interrupt vector. NO Byte Number This bit field defines the size of the receive data section allocated by the host. The maximum buffer length is 65535 bytes and it has to be a multiple of 4 bytes. Data bytes are stored in the receive data section according to the selected mode (little endian or big endian). Note: Please note that the device handles the status (CRC, flag and frame status) of frame based protocols (HDLC, PPP) internally in the same way as payload data. Therefore byte number should include four bytes more than the maximum length of incoming frames. Nevertheless, the frame status will be deleted from the end of the data stream and be attached as a status word to the receive descriptor. The frame status will not be written to the data section. Data Sheet 62 05.2001 PEB 3456 E Functional Description NextReceiveDescriptorPointer This pointer contains the start address of the next valid receive descriptor. After completion of the current receive descriptor the data management unit branches to the next receive descriptor to continue data reception. System CPU can force the TE3-CHATT to branch to the beginning of a new linked list via the command 'Receive Abort/Branch'. In this case the receive descriptor address provided via register CSPEC_FRDA is used as the next receive descriptor pointer to be branched to. ReceiveDataPointer This pointer contains the start address of the receive data section. The start address must be DWORD aligned. FE Frame End It indicates that the current receive data section (addressed by ReceiveDataPointer) contains the end of a frame. This bit is set by the data management unit after transferring the last data of a frame from the internal receive buffer into the receive data section which is located in the shared memory. Moreover the bit field BNO and the status bits are updated, the complete (C) bit is set and a 'Frame End' interrupt vector is generated. C Complete This bit indicates that *filling the data section has completed (with or without errors), *processing of this descriptor was aborted by a 'Receive Abort/Branch' command, *or the end of frame (PPP, HDLC) was stored in the receive data section. The complete bit releases the descriptor. BNO Byte Number of Received Data The data management unit writes the number of data bytes stored in the current data section into bit field BNO. Data Sheet 63 05.2001 PEB 3456 E Functional Description When the TE3-CHATT completes a data section, which included the end of a frame (C bit and FE bit are set), or when the TE3-CHATT branches to a new linked list due to a 'Receive Abort/Branch' command the status information bits RAB, ILEN, CRC, RFOD and MFL are updated as part of the receive status update. In the abort scenario, the C bit will always be set. Bit FE will be set only, if the particular channel operates in HDLC or PPP mode. RAB Receive Abort This bit is set when *the incoming serial data stream contained an abort sequence, or *an incoming frame was aborted by the command 'Receive Abort/ Branch', or *when a channel is switched off while a frame is being received. ILEN Illegal length This bit is set, when the length of the incoming data packet was not a multiple of eight bits. CRC CRC Error This bit is set, when the checksum of an incoming data packet was different to the internally calculated checksum. RFOD Receive Frame Overflow This bit is set, when a receive buffer overflow occurred during data reception. MFL Maximum Frame Length This bit is set, when the length of the incoming data packet exceeded the value programmed in CONF1.MFL. 4.3.3 Data Management Unit Receive The data management unit receive transfers data for each of the 256 logical receive channels from the internal receive buffer to the data sections of the corresponding channel. To fulfill the task it has to be initialized for operation, which is described in "Channel Programming / Reprogramming Concept" on Page 163. Relevant part of the channel information for the data management unit is the address pointer to the first receive descriptor, the channel interrupt queue and the channel interrupt mask. The first receive descriptor of a channel is fetched from system memory and stored in the chip internal channel database the first time the receive buffer requests a data transfer for the channel. The descriptor contains a pointer to the data section, the size of the provided data section and a pointer to the next receive descriptor. The data transfer is requested as soon as a programmed receive buffer threshold is reached. This threshold is programmed during channel setup on a per channel basis. Task of the data management unit is to calculate the maximum number of bytes that can Data Sheet 64 05.2001 PEB 3456 E Functional Description be stored in the receive data section and to compare this with the length of the requested data transfer. In case that the requested transfer length from the receive buffer fits into the provided data section the data management unit transfers the data block to system memory in one single burst. If the requested transfer length exceeds the available space of the data section the transfer is divided into two or more parts. Data packets are written to the data section until the given data section is filled or the end of a packet is reached. If the data section in the shared memory is completely filled with data, the data management unit updates the status word of the receive descriptor by setting the complete (C) bit and the number of bytes (BNO), which are stored in the data section. In this case the number of bytes written to the data section equals the size of the data section. If the data packet, which is written to system memory, contains the remaining part of a completely received packet, the data management unit updates the status word of the receive descriptor by setting the complete bit together with the frame end (FE) bit. The BNO field is updated on the actual value of bytes written to the data section. If enabled, the data management unit generates a `Frame End' channel interrupt vector. With the next receive buffer request the data management unit branches to the next receive descriptor, which was referenced in the next descriptor field of the current processed descriptor. To keep track of the linked list the data management unit provides the possibility to issue a `Receive Host Initiated' interrupt vector, which is generated after the status word was updated. To enable this interrupt vector the bit RHI must be set in a descriptor. Descriptor hold operation Processing of the descriptor list is controlled by the HOLD bit, which is located in the first DWORD of each receive descriptor. The HOLD bit indicates that the marked descriptor is the last descriptor containing a valid data buffer. The data management unit will not branch to a next descriptor until the hold condition is removed or a `Receive Abort' command forces the TE3-CHATT to branch to the beginning of a new linked list. Since the HOLD bit marks the last descriptor in a linked list, it may prevent that further received data packets can be written to system memory. When a given data section is filled, and does not contain the end of a frame (frame based protocols) and the requested transfer length could not be satisfied, the data management unit polls the HOLD bit of the current receive descriptor once more. If the HOLD bit is removed, it branches to the next descriptor. When the HOLD bit is still '1', an internal poll bit is set and the data management unit does not branch to the next descriptor. Additionally a 'Hold Caused Receive Abort' interrupt vector is generated. The status of the descriptor in the shared memory is aborted (RAB bit set) and the complete bit and the frame end bit are set in the receive descriptor. The rest of the frame will be discarded. As long as the HOLD bit remains set further data of the same channel is Data Sheet 65 05.2001 PEB 3456 E Functional Description discarded and for each discarded frame a 'Silent Discard' interrupt vector with the bits HRAB and RAB set is generated. If the current data section was filled and does contain the end of frame a 'Frame End' interrupt vector is generated and the descriptor is updated on the FE bit and the C bit. Therefore the status of this receive descriptor is error free. With the next request of the receive buffer, the data management unit repolls the HOLD bit of the current receive descriptor. If the hold bit is removed, it branches to the next descriptor. If the HOLD bit is still '1', an internal poll bit is set. As long as the HOLD bit remains set, further data of the same channel is discarded and for each discarded frame a 'Silent Discard' interrupt vector with bits HRAB and RAB set is generated. When the receive buffer request matches exactly the remaining size of the data section and the data block does not contain the end of a packet, it is stored completely in the data section. The descriptor is updated immediately (C bit set). With the next receive buffer request, the data management unit repolls the HOLD bit of the current receive descriptor. If the HOLD bit is removed, it branches to the next descriptor. If the HOLD Bit is still '1', an internal poll bit is set. Additionally a 'Hold Caused Receive Abort' interrupt vector is generated and the rest of the frame is discarded. As long as the HOLD bit remains set further data of the same channel is discarded and for each discarded frame a 'Silent Discard' interrupt vector is generated. The system CPU can remove the hold condition, when the next receive descriptor is available in shared memory. Therefore the CPU has to execute a `Receive Hold Reset' command, which will reactivate the channel. When the receive buffer requests a new data transfer, the data management unit will repoll the last receive descriptor. If the HOLD bit was removed, the data management unit branches to the next receive descriptor pointed to by bit field NextReceiveDescriptor. Note: In protocol modes HDLC and PPP data from receive buffer is discarded until the end of a received frame is reached. As soon as the beginning of a new frame is received, the data management unit starts to fill the data section. Note: In transparent mode data transferred from receive buffer is written immediately to the data section of the next receive descriptor. If the CPU issues a 'Receive Hold Reset' command and does not remove the HOLD bit (erroneous programming), no action will take place. 4.3.4 Transmit Descriptor The transmit descriptor in shared memory is initialized by the host CPU and is read afterwards by the TE3-CHATT. The address pointer to the first transmit descriptor is stored in the on-chip channel database, when requested to do so by the host CPU via the 'Transmit Init' command. The first three DWORDs of a transmit descriptor are read when the transmit buffer requests a data transfer for this channel and then they are stored in the on-chip memory. Also they are read when branching from one transmit Data Sheet 66 05.2001 PEB 3456 E Functional Description descriptor to the next transmit descriptor. Therefore all information in the next descriptor must be valid when the data management unit branches to a descriptor. The last DWORD of a transmit descriptor optionally is written by the TE3-CHATT when processing of a descriptor has finished. Table 4-2 DWORD ADDR. 00H Transmit Descriptor Structure 31 30 29 28 27 FE HOLD THI CEN 0 04H 26 25 24 23 22 0 0 0 0 0 21 20 19 18 17 16 DescriptorID(5:0) NextTransmitDescriptorPointer(31:2) 08H TransmitDataPointer(31:0) 0CH 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWORD ADDR. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 NO(15:0) 00H 04H NextTransmitDescriptorPointer(31:2) 08H 0CH FE TransmitDataPointer(31:0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Frame end It indicates that the current transmit data section (addressed by transmit data pointer) contains the end of a frame. After the last byte is read from system memory this bit is passed to the transmit buffer and to the protocol machine. The bit FE informs the transmit buffer to move a stored frame to the protocol machine even if the programmed transmit forward threshold is not reached (see "Internal Transmit Buffer" on Page 74). The protocol machine is informed to append the checksum (HDLC, PPP) and then to send the interframe time-fill. Providing a transmit descriptor with FE = '0' and HOLD = '1' is an error. HOLD Hold indication It indicates that this descriptor is the last valid element of a linked list. Data Sheet 0 Next descriptor is available in the shared memory. The data management unit branches to the next descriptor as soon as processing of the current descriptor has finished. 1 The current descriptor is the last descriptor containing valid data in the data section. As soon as the data management unit has transferred the data contained in the data section to the internal buffer, it tries one more time to read the descriptor. In case that 67 05.2001 PEB 3456 E Functional Description the hold indication is still set, it stores further requests of the receive buffer in its channel database. The channel can be reactivated by issuing a 'Transmit Hold Reset' command or by providing a new linked list via the 'Transmit Abort/Branch' command, in which case not served requests are processed. Note: When repolling a descriptor the TE3-CHATT checks the HOLD bit and the bit field NextTransmitDescriptorPointer. All other information are NOT updated in the internal channel database. NO Byte Number The byte number defines the number of bytes stored in the data section to be transmitted. Thus the maximum length of data buffer is 65535 bytes. In order to provide dummy transmit descriptors NO = 0 is allowed in conjunction with the FE bit set. In this case (NO = 0) a 'Transmit Host Initiated' interrupt vector and/or the C-bit will be generated/set when the data management unit recognizes this condition. It is an error to set NO = 0 without FE bit set. THI Transmit Host Initiated Interrupt This bit indicates that the TE3-CHATT shall generate a 'Transmit Host Initiated' interrupt vector after it has finished operating on the descriptor. DescriptorID 0 Data management unit does not generate an interrupt vector after it has processed the transmit descriptor. 1 Data management unit generates an interrupt vector, as soon as all data bytes are transferred to the internal transmit buffer and the status information is updated. This bit field is read by the data management unit and written back in the corresponding interrupt status of a channel interrupt vector which is generated by data management unit. This value provides a link between the descriptor and the corresponding interrupt vector. NextTransmitDescriptorPointer This pointer contains the start address of the next transmit descriptor. It has to be DWORD aligned. After sending the indicated number of data bytes, the data management unit branches to the next transmit descriptor. The transmit descriptor is read entirely at the beginning of transmission and stored in on-chip memory. Therefore all informations in the descriptor must be valid. System CPU can force the TE3-CHATT to branch to the beginning of a new linked list via the command 'Transmit Abort/Branch'. In this case the transmit descriptor address provided via register CSPEC_FTDA is used as the next transmit descriptor pointer to be branched to. Data Sheet 68 05.2001 PEB 3456 E Functional Description TransmitDataPointer This 32-bit pointer contains the start address of the transmit data section. Although the data management unit works DWORD oriented, it is possible to begin transmit data section at byte addresses. CEN Complete Enable This bit is set by the CPU if the complete bit mechanism is desired: C 0 The data management unit will NOT update the transmit descriptor with the C bit. In this mode the use of the THI interrupt is recommended. 1 The data management unit will set the C bit. Complete This bit is set by the data management unit, when the bit CEN of a descriptor is set and when it *completed reading a data section normally, or *it was aborted by a 'Transmit Off' command or by a 'Transmit Abort/ Branch' command. The complete bit releases the descriptor. 4.3.5 Data Management Unit Transmit The data management unit transmit provides the interface between system memory on one side and the internal transmit buffer on the other side. The data management unit handles requests of the transmit buffer, controls the address and burst length calculation, initiates data transfers from system memory to the transmit buffer and handles the linked lists on a per channel basis. For initialization the CPU programs the first transmit descriptor address, the interrupt mask, the interrupt queue and starts the channel with the 'Transmit Init' command. For detailed description of channel commands refer to "Channel Commands" on Page 164.The data management unit then fetches the given information and stores them in its on-chip channel database. The first transmit descriptor is fetched from system memory and stored in the chip internal channel database the first time the transmit buffer requests data for a channel. It contains a pointer to the data buffer, the length of the data section as well as a pointer to the next transmit descriptor. After the first descriptor is stored internally a 'Transmit Command Complete' interrupt vector is generated. Data transfers are requested as long as the number of empty locations is below a programmable refill threshold. The number of empty locations is reported from the transmit buffer to the data management unit. Task of the data management unit is to calculate the number of bytes that can be loaded from the data section based on the NO Data Sheet 69 05.2001 PEB 3456 E Functional Description field of the transmit descriptor and to compare this with the number of bytes requested by the transmit buffer. Depending on the bit field NO in the transmit descriptor several read accesses must be performed by the data management unit. It stops serving the request as soon as the requested amount of data was transferred to the transmit buffer, when a Frame End bit (FE) in the processed transmit descriptor is set or when the channel was aborted using a `Transmit Abort' command. Serving the request can also be suspended, when the programmed transmit burst length (CONF3.TPBL) is reached. All these events may result in open transmit buffer locations, but the data management unit stores this information as open requests in the channel database and processes these requests continuously. The data management unit alternately serves requests issued by the transmit buffer or open requests stored in its internal channel database. If there are open requests for a channel, data transmission will be initiated. The procedure is the same as described above. It stops, if the requested amount of data is served or when the FE bit field is set. If a transmit descriptor has its FE bit set and all data of the data section is moved to the transmit buffer, the data management unit serves requests of further channels or looks for open requests in its database. Therefore open requests from other channels are served faster and possible underruns can be avoided. The next transmit descriptor will be retrieved with the next data transfer of the channel. When the data management unit completed reading a data section associated with a transmit descriptor, it updates the complete (C) bit in the status word of the transmit descriptor if the complete enable (CEN) bit is set. Additionally a 'Transmit Host Initiated' interrupt vector is generated if the THI bit is set in the transmit descriptor. Afterwards the data management unit the TE3-CHATT branches to the next transmit descriptor. Descriptor hold operation The data transfer is controlled by the HOLD bit, which is located in the first DWORD of a transmit descriptor. The HOLD bit indicates that the marked descriptor is the last descriptor in a linked list. The data management unit will not branch to the next descriptor until the hold condition is removed or a 'Transmit Abort' command forces the TE3CHATT to branch to a new linked list. If the HOLD bit and the frame end bit are set together in a descriptor, the data management unit transfers all data of the belonging data section to the transmit buffer and optionally sets the C-bit in the current transmit descriptor. When a new data transfer is requested (either from the transmit buffer or an open request) the data management unit repolls the descriptor. If the HOLD bit is removed, it will branch to the next transmit descriptor. If the HOLD bit is still set, that channel is suspended for further operation. Following requests from the transmit buffer will not be served, but the number of requested data is stored in the open request registers. Data Sheet 70 05.2001 PEB 3456 E Functional Description If the HOLD bit is detected in a descriptor and the frame end bit is not set, the data management unit will transfer all data of the belonging data section to the transmit buffer. Afterwards it generates a 'Hold Caused Transmit Abort' interrupt vector in order to inform the host CPU about the erroneous descriptor structure. In PPP and HDLC mode the abort status is propagated to the transmit buffer and the protocol machine, so that a abort sequence is sent on the serial side. In TMA mode the data management unit generates a 'Hold Caused Transmit Abort' interrupt vector every time it recognizes the HOLD bit. Then it reads the transmit descriptor once more. If the HOLD bit is removed it branches to the next transmit descriptor and proceeds with normal operation. Otherwise, when the HOLD bit is still set, the channel is suspended for further operation and an internal poll bit is set. Following requests from the transmit buffer will not be served, but the number of requested data is stored in the open request register. The host CPU can remove the hold condition, when the next transmit descriptor is available in system memory. Therefore the CPU has to execute a 'Transmit Hold Reset' command, which will reactive the channel. When the transmit buffer requests a new data transfer or when open request are stored in the on-chip database the data management unit repolls the transmit descriptor and checks the HOLD bit again. If the HOLD bit is removed it branches to next transmit descriptor. If the CPU issues a 'Transmit Hold Reset' command and does not remove the HOLD bit (erroneous programming), no action will take place. Nevertheless, the CPU always has to issue a 'Transmit Hold Reset' command when it removes the HOLD bit in a descriptor, no matter the data management unit has already seen the HOLD bit or not. 4.3.6 Byte Swapping The TE3-CHATT operates per default as a little endian device. To support integration into big endian environments, the data management unit provides an internal byte swapping mechanism, which can be enabled via bit CONF1.LBE. The big endian swapping applies only to the data section pointed to by the receive and transmit descriptors in the shared memory. Note: Byte swapping only effects the organization of packet data in system memory. All internal registers, as well as the descriptors, address pointers or interrupt vectors are handled with little endian byte ordering. Data Sheet 71 05.2001 PEB 3456 E Functional Description Table 4-3 Example for little/big Endian with BNO = 3 BNO 3 Table 4-4 Little Endian - 4.3.7 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 - Example for little big Endian with BNO = 7 BNO 7 Byte 2 Big Endian Little Endian Big Endian Byte3 Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 Byte3 - Byte 6 Byte 5 Byte 4 Byte 4 Byte 5 Byte 6 - Transmission Bit/Byte Ordering Data is transmitted beginning with byte zero in increasing order. Vice versa data received is stored starting with byte zero. The position of byte zero depends on the selected endian mode. Each byte itself consists of eight bits starting with bit zero (LSB) up to bit seven (MSB). Data on the serial line is transmitted starting with the LSB. The first bit received is stored in bit zero. 4.4 Buffer Management 4.4.1 Internal Receive Buffer The internal receive buffer provides buffering of frame data and status between the protocol handler and the receive data management units. Internal buffers are essential to avoid data loss due to the PCI bus latency, especially in the presence of multiple devices on the same PCI bus, and to enable a minimized bus utilization through burst accesses. The incoming data from the protocol handler is stored in a receive central buffer shared by all the 256 channels. The buffer is written by the protocol handler every time a complete DWORD is ready or the last byte of a frame has been received. Each channel has an individual programmable threshold code, which determines after how many DWORDs a data transfer into the shared memory is generated. The threshold therefore defines the maximum burst length for a particular channel in receive direction. A data transfer is also requested as soon as a frame end has been reached. Programming the burst length to be greater than 1 DWORD avoids too frequent accesses to the PCI bus, thereby optimizing use of this resource. For real time channels with lowest possible latency (example: constant bit rate) a value of one DWORD can be selected for the burst length. Data Sheet 72 05.2001 PEB 3456 E Functional Description The total size of the internal receive buffer is 12 kByte. If all the 256 channels are active, the average burst threshold should be programmed with 8 DWORDs, so that 4 DWORDs are available on the average to compensate for PCI latency and avoid data loss. However if less than 256 channels are active or if only 64 KBit/s channels are used, the burst threshold may be programmed to a higher value. In other words, the sum of all channel thresholds shall not exceed the maximum receive buffer locations. In order to prevent an overload condition from one particular channel (e.g. receiving only small or invalid frames), the receive buffer provides the capability to delete frames which are smaller or equal than a programmable threshold. All frames that have been dropped will be counted and an interrupt vector will be generated as soon as a programmable threshold has been reached. The actual value of the counter can be read in the small frame dropped counter register. Data Sheet 73 05.2001 PEB 3456 E Functional Description * protocol machine protocol machine receive buffer receive buffer 2nd burst receive burst threshold receive burst threshold receive burst threshold minimum frame length frame data management unit data management unit Example A: Normal operation Figure 4-7 delete minimum frame length 1st burst frame Example B: Drop of small frames Receive Buffer Thresholds For performance monitoring the receive buffer provides the capability to monitor the receive buffer utilization and to generate interrupts when certain fill thresholds have been reached. 4.4.2 Internal Transmit Buffer The internal transmit buffer with a total size of 32 kByte stores protocol data before it is processed by the protocol machine. The transmit buffer is essential to ensure that enough data is available during transmission, since PCI latency and usage of multiple Data Sheet 74 05.2001 PEB 3456 E Functional Description channels limit access to system memory for a particular channel. A programmable transmit buffer size and two programmable threshold are configurable by the host CPU for each channel. Note: The sum of both thresholds must be smaller than the transmit buffer size of a particular channel. * protocol machine transmit buffer transmit refill threshold request new data as long as num ber of empty locations is above transmit refill threshold programmable number of buff er locat ions per channel transmit forward threshold frame wa i t wi t h d a t a t r a n s mission until buffer level reaches transmit forward threshold data management unit Figure 4-8 Transmit Buffer Thresholds The threshold values have the following effect: * Data belonging to one channel stored in the internal transmit buffer will only be transferred to the protocol machine when the transmit forward threshold is reached or if a complete frame is stored inside the transmit buffer. This mechanism avoids data underrun conditions. Data Sheet 75 05.2001 PEB 3456 E Functional Description * As long as the amount of data stored in the transmit buffer is below the transmit refill threshold the data management unit will keep filling the buffer by initiating PCI burst transfers. Note: Since there is a delay between the time the transmit buffer requests data from the data management unit and the time the data management unit serves the request, the actual number of empty locations may be higher than the transmit refill threshold. To determine the maximum PCI burst length an additional parameter is available which limits these requests up to a maximum of 64 DWORDs. 4.5 Protocol Description The protocol machines provide protocol handling for up to 256 channels. The protocol machines implement 4 modes, which can be programmed independently for each channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and transparent mode A. The configuration of each logical channel is programmed via the PCI bus and will be stored inside the protocol machines. Furthermore the current state for the protocol processing (CRC check, 1 bit count,...) is also stored inside the protocol machines. Each protocol machine (receive, transmit) handles a maximum of 256 channels and a maximum aggregate bit rate of up to 45 Mbit/s. 4.5.1 HDLC Mode * Flag Address Control Information CRC Flag 0111 1110 8 bits 8 bits <=0 Bits 16/32 bits 0111 1110 Figure 4-9 HDLC Frame Format The frame begin and frame end synchronization is performed with the flag character 7EH. Shared opening and closing flag is supported in receive direction and can be programmed in the channel configuration register for transmit direction. Shared `0' bit between two flags is only supported in receive direction. Interframe time-fill can be programmed to either flag 7EH or FFH indicating idle. In receive operation, prior to Frame check sum (FCS) computation, any `0' bit that directly follows five contiguous `1' bits is discarded. When closing flag is recognized, a CRC check, octet boundary check, MFL (maximum frame length) check, a short frame check and an additional small frame check are performed. Short frames have less than 4 octets if CRC16 is used or less than 6 octets if CRC32 is used. An aborted frame is recognized if 7 or more `1's are received. In transmit operation after the CRC computation a `0' bit is inserted after every sequence of five contiguous `1' bits. When frame end is indicated in the belonging transmit descriptor the calculated CRC is transmitted and a flag is generated. If an underrun Data Sheet 76 05.2001 PEB 3456 E Functional Description occurs in the internal transmit buffer (because of PCI latency e.g.) an abort sequence with 7 `1's is transmitted and an underrun interrupt is generated. The abort sequence is also generated if the host CPU resets or aborts a channel during the transmission of a frame. An invert option is provided to invert all the data output or data input between serial line and protocol machines or vice versa. The following CRC modes are supported: * 16 bit CRC * 32 bit CRC 1+x5+x12+x16 1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32 Optionally CRC transfer and check can be disabled. 4.5.2 Bit Synchronous PPP with HDLC Framing Structure * Flag Address Control Protocol 0111 1110 1111 1111 0000 0011 8/16 bits Information Padding FCS Flag 16/32 bits 0111 1110 Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure Same as HDLC. The handling of the abort sequence differs from that in HDLC mode. If 7EH is programmed as interframe time fill character, the abort sequence consists of 7 "1"s. If FFH is programmed as interframe time fill character, the abort sequence consists of 15 "1"s. The same programmable parameters as in HDLC mode apply to bit synchronous PPP. 4.5.3 Octet Synchronous PPP This mode uses a frame structure similar to the bit synchronous PPP mode. The frame begin and end synchronization is performed with the flag character (7EH). Use of a shared opening and closing flag is supported if programmed in the channel configuration register. Use of a shared '0' bit between two flags is not supported. A 16 or 32 bit CRC is computed over all service data read from the transmit buffer and appended to the end of the frame. The octet synchronous PPP mode uses octet stuffing instead of `0' bit stuffing in order to replace control characters used by intervening hardware equipment. This allows transparent transmission and also recognition and removal of spurious characters inserted by such equipment. A 32 bit per channel asynchronous control character map (ACCM) specifies characters in the range 00H-1FH to be stuffed/destuffed in service data and FCS field. In addition, the DEL control character (7FH ) and any of 4 ACCM extension characters stored in a programmable 32 bit register can be selected for character stuffing/destuffing. When a Data Sheet 77 05.2001 PEB 3456 E Functional Description character specified to be mapped is found in service data or the FCS field, it is replaced by a 2 octet sequence consisting of 7DH (Control Escape) followed by the character EXORed with 20H (e.g. 13H is mapped to 7DH 33H). In addition to the per channel specification of characters to be mapped, the control escape sequence 7DH and 7EH in the service data stream are always mapped. Opening and closing flags are not affected. The abort sequence consists of the control escape character followed by a flag character 7EH (not stuffed). Between two frames, the interframe time fill character is always 7EH. If in the transmit direction a data underrun occurs during transmission of a frame and the frame has not finished, an abort sequence is automatically sent (escape character followed by a flag) and an underrun interrupt vector will generated. If the transmit buffer indicates an empty condition for a channel between two frames (idle or interframe fill), the protocol machine will continue to send interframe time fill characters. Also an abort sequence will be generated if a channel is reset or an abort command is issued during transmission of a frame. The following CRC modes are supported: * 16 bit CRC * 32 bit CRC 1+x5+x12+x16 1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32 CRC computation/check or removing can be disabled. 4.5.4 Transparent Mode When programmed in transparent mode, the protocol machine performs fully transparent data transmission/reception without HDLC framing, i.e. without * Flag insertion/removing * CRC generation/CRC check * Bit stuffing/destuffing (0 bit insertion/removal). An option `Transparent Mode Pack' is provided to support subchanneling. If subchanneling is used (logical channels of less than 64 kbit/s), masked bits in the protocol data are set high and each bit in shared memory maps directly to enabled (not masked) bits on the serial line. Otherwise they contain protocol data, that is each byte in shared memory maps directly to a time slot. A programmable transparent flag can be programmed which will be inserted between payload data or is removed during reception of a payload data. An invert option is provided to invert the outgoing or incoming data stream. 4.6 T1 Framer and FDL Function The T1 framer includes frame alignment, CRC-6 check/generation, facility data link (FDL) support and bit error rate test. Three modes can be programmed for each T1 link: F4, ESF (F24), SF (F12). Data Sheet 78 05.2001 PEB 3456 E Functional Description 4.6.1 4-Frame Multiframe The allocation of the FT bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in Table 4-5. The FS bit may be used for signaling. Remote alarm (yellow alarm) is indicated by setting bit(2) to `0' in each channel. Table 4-5 4-Frame Multiframe Structure. Frame Number FT 1 2 3 4 1 - 0 - FS Service bit Service bit Synchronization Procedure For multiframe synchronization, the terminal framing bits (FT bits) are observed. The synchronous state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is forced to lock onto the next available candidate (RCMDR.FRS). Data Sheet 79 05.2001 PEB 3456 E Functional Description 4.6.2 ESF Mode The ESF multiframe consists of 24 consecutive frames. The first bit of each frame (F bit) is used as frame alignment, data link channel and CRC-6 channel (see Table 4-6). Table 4-6 ESF Multiframe Structure F bits Frame number Superframe bit number Framing Pattern Sequence (FPS) Data link (DL) Cyclic redundancy check (CRC-6) 1 0 - m - 2 193 - - c1 3 386 - m - 4 579 0 - - 5 772 - m - 6 965 - - c2 7 1158 - m - 8 1351 0 - - 9 1544 - m - 10 1737 - - c3 11 1930 - m - 12 2123 1 - - 13 2316 - m - 14 2509 - - c4 15 2702 - m - 16 2895 0 - - 17 3088 - m - 18 3281 - - c5 19 3474 - m - 20 3667 1 - - 21 3860 - m - 22 4053 - - c6 Data Sheet 80 05.2001 PEB 3456 E Functional Description 23 4246 - m - 24 4439 1 - - Frame 1 is transmitted first. Bit 1 (most significant bit) of each frame is transmitted first. 4.6.2.1 Multiframe Synchronization Procedure of the Receiver The F-bit of every fourth frame forms the pattern 001011. This multiframe alignment allows to identify where each particular frame is located within the multiframe in order to extract the cyclic redundancy check code (CRC-6) and the data link information. In the synchronous state two errors within 4 or 5 framing bits, two or more erroneous framing bits within one ESF multiframe or 4 consecutive errored multiframes will lead to the asynchronous state. There are two multiframe synchronization modes selectable via RFMR.SSP: 0 In the synchronous state, the setting of RCMDR.FRS resets the synchronizer and initiates a new frame search. The synchronous state will be reached again, if there is only one definite framing candidate. In the case of repeated apparent simulated candidates, the synchronizer remains in the asynchronous state. In asynchronous state, setting bit RCMDR.FRS induces the synchronizer to lock onto the next available framing candidate if there is one. At the same time the internal framing pattern memory will be cleared and other possible framing candidates are lost. 1 In the synchronous state, the setting of RCMR.FRS resets the synchronizer and initiates a new frame search. Synchronization is achieved if there is only one definite framing candidate AND the CRC-6 checksum is received without an error. If the CRC-6 check failed on the assumed framing pattern the TE3CHATT will stay in the asynchronous state, searching for an alternate framing pattern. In case no alternate framing pattern can be found, setting bit RCMDR.FRS starts a totally new multiframe search. At the same time the internal framing pattern memory will be cleared and other possible framing candidates are lost. 4.6.2.2 CRC-6 Generation / Check according to ITU-T G.706 Generation In calculating the CRC-6 bits, the F-bits are replaced by binary 1s. All information in the other bit positions will be identical to the information in the corresponding multiframe bit positions. The CRC-6 bit sequence c1, c2, c3, c4, c5, c5 and c6 calculated on multiframe N is transmitted in multiframe N+1. This CRC polynomial is defined as the remainder after Data Sheet 81 05.2001 PEB 3456 E Functional Description multiplication by x6 and then division (modulo 2) by the generator polynomial x6+x+1 of the polynomial corresponding to multiframe N. The first check bit c1 is the most significant bit of the remainder; the last check bit c6 is the least significant bit of the remainder. Check At the receiver, the received multiframe, with each F-bit having first been replaced by a binary 1, is acted upon by the multiplication/division process described above. The resulting remainder is compared on a bit-by-bit basis, with the CRC-6 check bits contained in the subsequently received multiframe. In synchronous state a received CRC-6 error may generate an interrupt status and will increment a CRC-6 counter. 4.6.2.3 Remote Alarm (Yellow Alarm) Generation / Detection Generation If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote Alarm is also sent unconditionally when TCMDR.XRA='1'. ESF RA is sent by repeating the pattern `1111 1111 0000 0000' in the Data Link (DL). Detection Remote Alarm (yellow alarm) is detected and flagged with bit FRS.RRA when the pattern '1111 1111 0000 0000' is received in the DL bits if RFMR.SRAF=0. If RFMR.SRAF=1, yellow alarm is detected when every bit2 of each time slot is 0. If RFMR.RRAM is set, Remote Alarm can be detected even in the presence of BER 1/1000. FRS.RRA will be reset automatically when the alarm condition is no longer detected. 4.6.2.4 Facility Data Link The Facility Data Link (FDL) contains bit oriented messages (priority or command/ response) or HDLC-based message oriented signals that are processed by a HDLC machine. Each T1 port has its dedicated FDL controller. In HDLC mode CRC16 is supported. Additionally one or two byte address comparison is supported. Note: CAS - BR (Channel Associated Signalling - bit robbing) is not supported. The protocol machines support access to 56 kBit/s or 64 kBit/s data channels with their bit masking function. If CCS (Common Channel Signalling) is used, the corresponding channel (usually time slot 24) is handled as a standard data time slot by the HDLC/PPP machine and the data is transferred via the PCI bus. Data Sheet 82 05.2001 PEB 3456 E Functional Description In transmit and receive direction 64 byte deep FIFOs divided into two pages of 32 bytes are provided for the intermediate storage of data between the HDLC machine and the CPU interface. Receive Signaling Controller Each of the signaling controllers may be programmed to operate in various signaling modes. The TE3-CHATT will perform the following signaling and data link methods on the DL-Channel of the ESF format: * HDLC/SDLC Access In case of common channel signaling the signaling procedure HDLC/SDLC will be supported. The signaling controller of the TE3-CHATT performs the flag detection, CRC checking, address comparison and zero bit-removing. Depending on the selected address mode, the TE3-CHATT may perform a 1 or 2 byte address recognition. If a 2-byte address field is selected, the high address byte is compared with two individually programmable values in register RAH. Buffering of receive data is done in the RFIFO. Refer also to Chapter 4.8.1. * Transparent Access In signaling controller transparent mode, fully transparent data reception without HDLC framing is performed, i.e. without flag recognition, CRC checking or bit-stuffing. This allows the user specific protocol variations. * Bit Oriented Messages in ESF-DL Channel The TE3-CHATT supports the DL-channel protocol for ESF format according to ANSI T1.403 specification or according to AT&T TR54016. The Bit Oriented Message (BOM) receiver may be switched on/off separately. If the TE3-CHATT is used for HDLC formats only, the BOM receiver has to be switched off. If BOM-receiver has been switched on, an automatic switching between HDLC and BOM mode is enabled. If eight or more consecutive ones are detected, the BOM mode is entered. Upon detection of a flag in the data stream, the TE3-CHATT switches back to HDLC-mode. In BOM-mode, the following byte format is assumed (the left most bit is received first). 111111110xxxxxx0 The TE3-CHATT uses the FFH byte for synchronization, the next byte is stored in RFIFO (first bit received: LSB) if it starts and ends with a `0'. Bytes starting or ending with a `1' are not stored. If there are no 8 consecutive one's detected within 32 bits and the TE3-CHATT is currently in the BOM mode, an interrupt is generated. However, byte sampling is not stopped. Transmit Signaling Controller Similar to the receive signaling controller the same signaling method is provided. The TE3-CHATT will perform the following signaling and data link methods on the DLchannel of the ESF format: Data Sheet 83 05.2001 PEB 3456 E Functional Description * HDLC access The transmit signaling controller of the TE3-CHATT performs the FLAG generation, CRC generation, zero bit-stuffing and programmable IDLE code generation. Buffering of transmit data is done in the 2x32 byte deep transmit FIFO. The signaling information will be internally multiplexed with the data applied to the outgoing ports. * Transparent/BOM mode In signaling controller transparent mode, fully transparent data transmission without HDLC framing is performed. Optionally the TE3-CHATT supports the continuous transmission of the XFF.XFIFO contents with a maximum of 32 bytes. Operating in HDLC or BOM mode "flags" or "idle" may be transmitted as interframe timefill. Data Sheet 84 05.2001 PEB 3456 E Functional Description 4.6.3 SF Mode The SF multiframe consists of 12 consecutive frames. The first bit of each frame (F-bit) the TE3-CHATTis used as frame alignment (see following table). Table 4-7 SF Multiframe Structure F-bits Frame number Superframe bit Terminal Framing (Ft) Signaling Framing (Fs) number 1 0 1 - 2 193 - 0 3 386 0 - 4 579 - 0 5 772 1 - 6 965 - 1 7 1158 0 - 8 1351 - 1 9 1544 1 - 10 1737 - 1 11 1930 0 - 12 2123 - 0 The Fs-bits are used to get a higher synchronization probability but no CAS - BR (Channel Associated Signalling - bit robbing) is supported. Only frame alignment is provided in this mode. 4.6.3.1 Synchronization Procedure of the Receiver In the synchronous state terminal framing (Ft-bits) and multiframing (Fs-bits) are observed, independently. Further reaction on framing errors depends on the selected synchronization/resynchronization procedure (via bit RFMR0.SSP): 0 Terminal frame and multiframe synchronization are combined. Two errors within 4/5/6 Ft-bits or two errors within 4/5/6 in Fs-bits (via bits RFMR.SSC) will lead to the asynchronous state for terminal framing and multiframing. Additionally to the bit FRS.LFA, loss of multiframe alignment is reported via bit FRS.LMFA. The resynchronization procedure starts with synchronizing upon the terminal framing. If the pulseframing has been regained, the search for Data Sheet 85 05.2001 PEB 3456 E Functional Description multiframe alignment is initiated. Multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. 1 Terminal frame and multiframe synchronization are separated. Two errors within 4/5/6 terminal framing bits will lead to the same reaction as described above for the 'combined' mode. Two errors within 4/5/6 multiframing bits will lead to the asynchronous state only for the multiframing. Loss of multiframe alignment is reported via bit FRS.LMFA. The state of terminal framing is not influenced. Now, the resynchronization procedure includes only the search for multiframe alignment. Multiframe synchronization has been regained after two consecutive correct multiframe patterns have been received. 4.6.3.2 Remote Alarm (Yellow Alarm) Generation / Detection There are two possibilities of remote alarm (yellow alarm) indication: * Bit 2 = '0' in each time slot of the frame, selected with bit R/TFMR.SRAF = 0 * The last bit of the multiframe alignment signal (bit 1 of frame 12) changes from '0' to `1', selected with bit R/TFMR.SRAF = 1. Generation If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote Alarm is also sent unconditionally when TCMDR.XRA = 1. Detection Remote alarm (yellow alarm) is detected and flagged with bit FRS.RRA which will be reset automatically when the alarm condition is no longer detected. Data Sheet 86 05.2001 PEB 3456 E Functional Description 4.6.4 Common Features for SF and ESF 4.6.4.1 AIS (Blue Alarm) Generation/Detection Generation The alarm indication signal is an all one unframed signal and will be transmitted if enabled via bit TCMDR.XAIS. Detection The detection of AIS is done, if 2 or less '0's are detected in a multiframe. This condition is flagged by bit FRS.AIS. AIS detection can also only be enabled in asynchronous state by bit RFMR0.AIS3. In this case AIS is indicated if three or less zeros within a time interval of 12 frames (in SF mode), or if five or less zeros within a time interval of 24 frames (ESF mode) are detected in the received bit stream. 4.6.4.2 Loss of Signal (Red Alarm) Detection The TE3-CHATT can be programmed to satisfy the different definitions for detecting Loss of Signal (LOS) alarms in ITU-T G.775 and AT&T TR54016. Loss of signal is indicated by a flag in the receive framer's status register (FRS.LOS). In addition, a 'Loss of Signal Status' interrupt vector is generated, if not masked. LOS detection and recovery conditions are set by a flag RFMR.LOSR and the two parameters PCD and PCR. Detection 'Loss of Signal' alarm will be generated, if the incoming data stream has no pulses (no '1') for a certain number N of consecutive bits. 'No pulse' in the receive interface means a logical zero octet on receive data inputs. The number N can be set via register PCD and is calculated as 8*(PCD+1). Recovery The recovery procedure starts after detecting a logical '1' in the received bit stream. The value via register PCR defines the number of pulses, which must occur during the time interval 8*(PCD+1), to clear the LOS alarm. Additionally, if selected via RFMR.LOSR, any pulse density violation resets the measurement interval. I.e. in addition to the basic pulse density required for recovery, a density of at least N `1's in every N+1 octets (0 < N < 24) is required during 8*(PCD+1) bit intervals. Data Sheet 87 05.2001 PEB 3456 E Functional Description 4.6.4.3 In-Band Loop Generation and Detection The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate (00001) and down/deactuate (001) pattern according to ANSI T1.403 even in the presence of bit error rates as high as 1/100. Replacing the transmit data with the in-band loop codes is done by TCMDR.XLD / XLU for actuate or deactuate loop code. The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate and down/deactuate pattern. The loop up and down pattern is individual programmable in the Loop Code Register from 5 to 8 bits in length. Status and interrupt-status bits will inform the user whether Loop Actuate- or Deactuate code was detected, but the CPU must activate the loop-back. 4.6.4.4 Pulse Density Detection The framer examines the receive data stream of each port on the pulse density requirement defined by ANSI T1. 403. More than 15 consecutive zeros or less than N ones in each and every time window of 8(N+1) data bits, where N=23 will be detected. Violations of these rules are indicated by setting the status bit FRS.PDEN. Moreover the PDEN bit in the interrupt vector will be set. 4.6.4.5 Error Performance Monitoring The TE3-CHATT supports the error performance monitoring by detecting following alarms in the received data. * * * * * Framing errors CRC errors Loss of frame alignment Loss of signal Alarm indication signal Loss of frame alignment, Loss of signal and AIS are indicated with interrupt status bits. With a programmable interrupt mask (register IMR) all these error events could generate an Errored Second interrupt (ES) if enabled. Additionally a one Second interrupt could be generated to indicate that the ES interrupt has to be read. If the ES interrupt is set the enabled alarm status bits or the error counters have to be examined. The following counters are implemented in the T1 framer: * Framing Error Counter: This counter will be incremented when incorrect FT and FS bits in SF mode or incorrect FPS bits in ESF format are received. Framing errors will not be counted during asynchronous state. * CRC Error Counter (Only ESF mode): The counter will be incremented when a multiframe has been received with a CRC error. CRC errors will not be counted during asynchronous state. Data Sheet 88 05.2001 PEB 3456 E Functional Description * Errored block counter: This counter will be incremented, if a multiframe has been received with framing errors or CRC errors (ESF only). Clearing and updating of the counters is done according to bit RFMR1.ECM. If this bit is reset, the error counter is permanently updated. Reading of actual error counter status is always possible. The error counters are reset by reading the corresponding status register. If RFMR1.ECM is set, every second the error counter will be latched and then automatically reset. The latched error counter state should be read within the next second. 4.6.4.6 Pseudo-random Bit Sequence Generator and Monitor A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151 can be activated for one particular logical channel. The PRBS pattern type can be selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots which should be used for PRBS can be defined in R/TPTSL register. Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1 with length up to 32 bit to be defined in R/TPRBSC.FPL. The PRBS monitor searches synchronization on the inverted and non-inverted PRBS pattern. The current synchronization status is reported in status and interrupt status registers. Each PRBS bit error will increment an error counter. An additional counter will accumulate the total number of received bits. Synchronization will be reached within 400 ms with a probability of 99.9% and a BER of 1/10. 4.7 E1 Framing and Signaling The operating mode of the TE3-CHATT is selected by programming the carrier data rate and characteristics, multiframe structure, and signaling scheme. The TE3-CHATT implements the standard framing structures for E1 or PCM 30 (CEPT, 2048 Kbit/s) carriers. The internal HDLC controller supports signaling procedures like signaling frame synchronization/synthesis and signaling alarm detection in all framing formats. Summary of E1- Framing Modes: * Doubleframe format according to ITU-T G. 704. * Multiframe format according to ITU-T G. 704 CRC-4 processing according to ITU-T G. 706. * Multiframe format with CRC-4 to non CRC-4 interworking according to ITU-T G. 706. After reset, the TE3-CHATT is switched into doubleframe format automatically. Switching between the framing formats is done via bit T/RFMR.FM Data Sheet 89 05.2001 PEB 3456 E Functional Description 4.7.1 Doubleframe Format The framing structure is defined by the contents of time-slot 0 (refer to Table 4-8). Table 4-8 Alternate Frames Allocation of Bits 1 to 8 of Time slot 0 Bit Number 1 Frame Containing the Frame Alignment Signal Si 1) Frame not Containing the Frame Alignment Signal 3 4 5 6 7 8 0 0 1 1 0 1 1 Sa5 Sa6 Sa7 Sa8 Frame Alignment Signal Si 1) 2 1 2) A 3) Sa4 4) 1) Si-bits: Reserved for international use. They are fixed to `1'. 2) Fixed to `1'. Used for synchronization. 3) Remote alarm indication: In undisturbed operation `0'; in alarm condition `1'. 4) Sa-bits: Reserved for national use. If not used, they should be fixed at `1'. Access to received information via registers RSAW1-3. Transmission via registers XSAW1-XSAW3. HDLC signalling in bits Sa4 - Sa8 is selectable. 4.7.1.1 Synchronization Procedure of the Receiver Synchronization status is reported via bit FRS.LFA. Framing errors are counted by the Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4 consecutive incorrect FAS words or 3 or 4 consecutive incorrect service words (bit 2 = 0 in time-slot 0 of every other frame not containing the frame alignment word), the selection is done via bit RFMR.SSC. Additionally, the service word condition can be disabled. When the framer lost its synchronization an status bit FRS.LFA is generated. In asynchronous state, counting of framing errors will be stopped. The resynchronization procedure starts automatically after reaching the asynchronous state. Additionally, it may be invoked user controlled via bit RCMDR.FRS (Force Resynchronization: the FAS word detection is interrupted. In connection with the above conditions this will lead to asynchronous state. After that, resynchronization starts automatically). Data Sheet 90 05.2001 PEB 3456 E Functional Description Synchronous state is established after detecting: * a correct FAS word in frame n, * the presence of the correct service word (bit 2 = 1) in frame n + 1, * a correct FAS word in frame n + 2. If the service word in frame n + 1 or the FAS word in frame n + 2 or both are not found searching for the next FAS word will be start in frame n + 2 just after the previous frame alignment signal. Reaching the asynchronous state causes the removal of FSR.LFA and additionally an interrupt vector with LFA bit reset (if not masked). Undisturbed operation starts with the beginning of the next doubleframe. 4.7.1.2 A-bit Access If the TE3-CHATT detects a remote alarm indication in the received data stream the interrupt status bit FRS.RRA will be set. By setting TFMR.AXRA the TE3-CHATT automatically transmits the remote alarm bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment FRS.LFA = 1. If the receiver is in synchronous state FRS.LFA = 0 the remote alarm bit will be reset. 4.7.1.3 Sa-bit Access The TE3-CHATT allows access to the Sa-bits via registers RSAW1-3 and XSAW1-3. Data Sheet 91 05.2001 PEB 3456 E Functional Description 4.7.2 CRC-4 Multiframe The multiframe structure shown in Table 4-9 is enabled by setting TFMR.FM for the transmitter and RFMR.FM for the receiver. Multiframe : 2 submultiframes = 2 x 8 frames Frame alignment: refer to Chapter 4.7.1 Doubleframe Format Multiframe alignment: bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern `001011' CRC bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14 CRC block size : 2048 bit (length of a submultiframe) CRC procedure: CRC-4, according to ITU-T G.704, G.706 Table 4-9 CRC-4 Multiframe Structure SubFrame Multiframe Number Multiframe Bits 1 to 8 of the Frame 1 2 3 4 5 6 7 8 I 0 1 2 3 4 5 6 7 C1 0 C2 0 C3 1 C4 0 0 1 0 1 0 1 0 1 0 A 0 A 0 A 0 A 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa5 1 Sa5 1 Sa5 1 Sa5 0 Sa61 0 Sa62 0 Sa63 0 Sa64 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa8 1 Sa8 1 Sa8 1 Sa8 II 8 9 10 11 12 13 14 15 C1 1 C2 1 C3 E C4 E 0 1 0 1 0 1 0 1 0 A 0 A 0 A 0 A 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa5 1 Sa5 1 Sa5 1 Sa5 0 Sa61 0 Sa62 0 Sa63 0 Sa64 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa8 1 Sa8 1 Sa8 1 Sa8 E Spare bits for international use. E bits are replaced by XSP.XS13 and XSP.XS15 or automatic transmission for submultiframe error indication. Sa Spare bits for national use. Sa-bit access via registers RSAW1-3 and XSAW1-3 is provided. HDLC-signaling in bits Sa4 - Sa8 is selectable. C1 ... C4 Cyclic redundancy check bits. A Remote alarm indication. Automatic transmission of the A-bit is selectable. Data Sheet 92 05.2001 PEB 3456 E Functional Description The CRC procedure is automatically invoked when the multiframe structure is enabled. CRC errors in the received data stream are counted by the 16 bit CRC Error Counter CEC (one error per submultiframe, maximum). Additionally a CRC error interrupt vector with CRC set can be generated if enabled. 4.7.2.1 Synchronization Procedure of the Receiver Multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged at status bits FRS.LFA and FRS.LMFA). Either edge of these bits will cause an LFA interrupt. The multiframe resynchronization procedure starts when Doubleframe alignment has been regained which is indicated by a FAS interrupt vector. For Doubleframe synchronization refer to Chapter 4.7.1. It may also be invoked by the user by setting bit RFMR.FRS for complete doubleframe and multiframe resynchronization. The CRC checking mechanism will be enabled after the first correct multiframe pattern has been found. However, CRC errors will not be counted in asynchronous state. The multiframe synchronous state is established after detecting two correct multiframe alignment signals at an interval of n x 2 ms (n = 1, 2, 3 ...). The loss of multiframe alignment flag FRS.LMFA will be reset. Additionally a multiframe alignment status interrupt MFAS is generated on the falling edge of bit FRS.LMFA. Automatic Force Resynchronization In addition, a search for Doubleframe alignment is automatically initiated if two multiframe pattern with a distance of n x 2 ms have not been found within a time interval of 8 ms after doubleframe alignment has been regained. The new search for frame alignment will be started just after the previous frame alignment signal. CRC-4 Interworking Mode CRC-4 interworking is implemented according to ITU-T G.706 Appendix B. For operational description refer to Figure 4-11. 4.7.2.2 CRC-4 Performance Monitoring In the synchronous state checking of multiframe pattern is disabled. However, with bit RFMR.ALMF an automatic multiframe resynchronization mode can be activated. If 915 out of 1000 errored CRC submultiframes are found then a false frame alignment will be assumed and a search for double- and multiframe pattern is initiated. The new search for frame alignment will be started just after the previous basic frame alignment signal. The internal CRC-4 resynchronization counter will be reset when the multiframe synchronization has been regained. Data Sheet 93 05.2001 PEB 3456 E Functional Description 4.7.2.3 A-Bit Access If the TE3-CHATT detects a remote alarm indication (bit 2 in TS0 not containing the FAS word) in the received data stream a RAS interrupt will be generated. With the deactivation of the remote alarm the remote alarm status interrupt with RAS='0' is generated. By setting TFMR.AXRA the TE3-CHATT automatically transmits the remote alarm bit = '1' in the outgoing data stream if the receiver detects a loss of frame alignment (FRS.LFA = '1'). If the receiver is in synchronous state (FRS.LFA = '0') the remote alarm bit will be reset in the outgoing data stream. Data Sheet 94 05.2001 PEB 3456 E Functional Description * Out of primary BFA: Inhibit incoming CRC-4 performance monitoring Reset all timers Set FRS.LFA/LMFA/NMF = 110B. No Primary BFA search ? Yes In primary BFA: Start 400 ms timer Enable primary BFA (loss checking procedure) Reset internal frame alignment status (FRS.LFA = 0) CRC-4 MFA search Start 8 ms timer Yes No Parallel BFA search good ? No Yes Can CRC-4 MFA be found in 8 ms ? No 400 ms timer elapsed ? Yes Assume CRC-4 to CRC-4 interworking Confirm primary BFA associated with CRC-4 MFA Adjust primary BFA if necessary Reset internal multiframe alignment status (FRS.LMFA = 0) Assume CRC-4 to non CRC-4 interworking Confirm primary BFA Set internal 400 ms timer expiration status bit (FRS.T400 = 1) Start CRC-4 performance monitoring Yes CRC-4 error count > 914 or LFA No Continue CRC-4 performance monitoring Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithms Data Sheet 95 05.2001 PEB 3456 E Functional Description 4.7.2.4 Sa-bit Access Due to signaling procedures using the five Sa-bits (Sa4 ... Sa8) of every other frame of the CRC-4 multiframe structure, two possibilities of access via the microprocessor are implemented. * The standard procedure, allows reading/writing the Sa-bit registers RSAW1 to RSAW3 and XSAW1 through XSAW3. Registers RSAW1-3 contains the service word information of the previously received CRC-4 multiframe or 8 doubleframes (bit slots 4-8 of every service word). These registers will be updated on every multiframe. Optionally TE3-CHATT provides the possibility to check the received Sa-data with the Sa-data received earlier. An interrupt vector is generated on Sa-data change in order to reduce microprocessor bus load. With the transmit multiframe begin the contents of this registers XSAW1-3 will be copied into shadow registers. The contents will subsequently sent out in the service words of the next outgoing CRC-4 multiframe (or doubleframes). The TXSA interrupt request that these registers should be serviced. If requests for new information will be ignored, current contents will be repeated. * The extended access via the receive and transmit FIFOs of the signaling controller. In this mode it is possible to transmit / receive a HDLC frame or a transparent bit stream in any combination of the Sa-bits. Sa-bit Detection according to ETS 300233 Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit combinations. The TE3-CHATT can be programmed to detect any bit combination on one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The corresponding status in register RSAW4 will be set. Register RSAW4 is from type "Clear on Read". With any change of state of the selected Sa-bit combinations a 'SSM Data Valid' interrupt vector will be generated. During the basic frame asynchronous state updating of register RSAW4 and interrupt vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit combinations can be done either synchronous or asynchronous to the submultiframe. In synchronous detection mode updating of register RSAW4 is done in the multiframe synch. state. In asynchronous detection mode updating is independent to the multiframe synchronous state. Sa-bit Error Indication Counters The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit sequence 0001B and 0011B or two user programmable values defined in register VCRC in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors are reported from the TE via Sa6. Incrementing is only possible in the multiframe synchronous state. Data Sheet 96 05.2001 PEB 3456 E Functional Description The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit sequence 0010B and 0011B or two user programmable values defined in register VCRC in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors detected at T-reference points are reported via Sa6. Incrementing is only possible in the multiframe synchronous state. 4.7.2.5 E-Bit Access Due to signalling procedures, the E-bits of frame 13 and frame 15 of the CRC-4 multiframe can be used to indicate received errored submultiframes: no CRC error : E = '1' CRC error : E = '0' Standard Procedure E-bits of the service word are replaced by values of bit XSP.XS13 and XSP.XS15. Automatic Procedure Values programmed in register Status information of received submultiframes is automatically inserted in E-bit position of the outgoing CRC-4 Multiframe without any further interventions of the microprocessor. In the double- and multiframe asynchronous state the E-bits are set to zero. In the multiframe synchronous state the E-bits are processed according to ITU-T G.704. Submultiframe Error Indication Counter The Error Bit Counter counts zeros in E-bit position of frame 13 and 15 of every received CRC-4 multiframe. This counter option gives information about the outgoing transmit line if the E-bits are used by the remote end for submultiframe error indication. Incrementing is only possible in the multiframe synchronous state. Data Sheet 97 05.2001 PEB 3456 E Functional Description 4.7.3 Common Features for E1 Doubleframe and CRC-4 Multiframe 4.7.3.1 Error Performance Monitoring and Alarm Handling Alarm detection and generation Alarm Indication Signal: Detection and recovery is flagged by bit FRS.AIS and the 'Alarm Indication Signal Status' interrupt vector. Transmission is enabled via bit TFMR.XAIS. Loss of Signal: Detection and recovery is flagged via bit FRS.LOS and a 'Loss of Signal Status' interrupt vector. Remote Alarm Indication: Detection and release is flagged by bit FRS.RRA and a 'Remote Alarm Status' interrupt vector. Transmission is enabled via bit TCMDR.XRA. Table 4-10 Summary of Alarm Detection and Alarm Release Alarm Detection Condition Clear Condition Loss of Signal (LOS) PCD Register No transitions (log. zero octets) in a programmable time interval of 16 - 512 consecutive pulse periods. PCR Register Programmable amount of ones (1-63) in a progr. time interval of 16 - 512 consecutive pulse periods. The pulse density is fulfilled and no more than 15 or 99 contiguous zeros during the recovery interval are detected. Alarm Indication Signal (AIS) FMR0.ALM = 0: FMR0.ALM = 0: less than 3 zeros in more than 2 zeros in 250 s and 250 s and loss of frame frame alignment found alignment declared FMR0.ALM = 1: FMR0.ALM = 1: more than 2 zeros in each of two less than 3 zeros in each of consecutive double frame periods two consecutive double frame periods Remote Alarm (RRA) bit 3 = 1 in time-slot 0 not set conditions no longer detected. containing the FAS word Data Sheet 98 05.2001 PEB 3456 E Functional Description Automatic remote alarm access If the receiver has lost its synchronization a remote alarm could be sent if enabled via TFMR.AXRA to the distant end. The remote alarm bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (FRS.LFA bit is set). In synchronous state the remote alarm bit will be removed. Error Counter The TE3-CHATT framer offers four error counters, each of them has a length of 16 bit. They record framing bit errors, CRC-4 bit errors. Updating the buffer is done in two modes: - one second boundary - clear on read In the one second mode an internal one second timer will update these buffers and reset the counter to accumulating the error events. The error counter can not overflow. Error events occurring during reset will not be lost. Status: Errored Second TE3-CHATT supports the error performance monitoring by detecting alarms or error events in the received data. Loss of frame alignment, including alarm indication signal and loss of signal, as well as CRC errors could generate an Errored Second interrupt if enabled. Second Timer An one-second timer interrupt could be internally generated to indicate that the enabled alarm status bits or the error counters have to be checked. 4.7.3.2 Loss of Signal Detection The TE3-CHATT can be programmed to satisfy the different definitions for detecting Loss of Signal (LOS) alarms in ITU-T G.775 and ETS 300233. Loss of signal is indicated by a flag in the receive framer's status register (FRS.LOS). In addition, a 'Loss of Signal Status' interrupt vector is generated, if not masked. Detection 'Loss of Signal' alarm will be generated, if the incoming data stream has no pulses (no '1') for a certain number N of consecutive pulse periods. 'No pulse' in the receive interface means a logical zero on receive data inputs. The number N can be set via register PCD and is calculated as 8*(PCD+1). Data Sheet 99 05.2001 PEB 3456 E Functional Description Recovery The recovery procedure starts after detecting a logical '1' in the received bit stream. The value via register PCR defines the number of pulses, which must occur during the time interval 8*(PCD+1), to clear the LOS alarm. 4.7.3.3 In-Band Loop Generation and Detection The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate (00001) and down/deactuate (001) pattern according to ANSI T1.403 with bit error rates as high as 1/100. Replacing the transmit data with the in-band loop codes is done by TCMDR.XLD / XLU for actuate or deactuate loop code. The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate and down/deactuate pattern. The loop up and down pattern is individual programmable in the Loop Code Register from 5 to 8 bits in length. Status and interrupt-status bits will inform the user whether Loop Up - or Loop Down code was detected, but the CPU must activate the loop-back. 4.7.3.4 Pseudo-random Bit Sequence Generator and Monitor A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151 can be activated for one particular logical channel. The PRBS pattern type can be selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots which should be used for PRBS can be defined in R/TPTSL register. Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1 with length up to 32 bit to be defined in R/TPRBSC.FPL. The PRBS monitor searches synchronization on the inverted and non-inverted PRBS pattern. The current synchronization status is reported in status and interrupt status registers. Each PRBS bit error will increment an error counter. An additional counter will accumulate the total number of received bits. Synchronization will be reached within 400 ms with a probability of 99.9% and a BER of 1/10. Data Sheet 100 05.2001 PEB 3456 E Functional Description Alarm Simulation Alarm simulation does not affect the normal operation of the device, i.e. all channels remain available for transmission. However, possible `real' alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. The alarm simulation is initiated by setting different code words in bit field FMR0.SIM. The following alarms are simulated: * * * * * * * * Loss of Signal Alarm Indication Signal (AIS) Auxiliary pattern Loss of pulse frame Remote alarm indication Framing error counter CRC-4 error counter E-Bit error counter Some of the above indications are only simulated if the TE3-CHATT is configured in a mode where the alarm is applicable (e.g. no CRC-4 error simulation when doubleframe format is enabled). Setting a code word in bit field FMR0.SIM initiates alarm simulation. Error counting and indication will occurs while this bit is set. After it is reset all simulated error conditions disappear. 4.8 Signaling Controller Protocol Modes The signalling controller provides access to the data link and Sa bits of the T1/E1 signals and provides access to the far end alarm and control channel (FEAC) and the C-bit parity path maintenance data link channel. It operates in HDLC, BOM or automatic modes. 4.8.1 HDLC Mode In HDLC mode the transmit signaling controller of the TE3-CHATT performs the FLAG generation, CRC generation, zero bit-stuffing and programmable IDLE code generation. Buffering of transmit data is done in the 2x32 byte deep transmit FIFO. The signaling information will be internally multiplexed with the data applied to the outgoing ports and is inserted in or extracted from the DL-Bits in T1 ESF mode or the Sa-bits in E1 modes. Any sequence of Sa-bits can be specified for protocol insertion. Shared Flags The closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. The Shared Flag feature is enabled by setting XCR1.SF. Data Sheet 101 05.2001 PEB 3456 E Functional Description CRC check As an option in HDLC mode the internal handling of received and transmitted CRC checksum can be influenced via control bits RCR1.XCRC and XCR1.DISCRC. * Receive Direction The received CRC checksum is always assumed to be in the last two bytes of a frame, immediately preceding a closing flag. If RCR1.XCRC is set, the received CRC checksum will be written to RFIFO where it precedes the frame status byte. The received CRC checksum is additionally checked for correctness. * Transmit Direction If XCR1.DISCRC is set, the CRC checksum is not generated internally. The checksum has to be provided via the transmit FIFO (XFF.XFIFO) as the last two bytes. The transmitted frame will only be closed automatically with a (closing) flag. The TE3-CHATT does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not. Address comparison An optional address comparison feature forwards all frames which match a programmable address to the receive FIFO. Frames not matching the address are discarded. If a 2-byte address field is selected, the high address byte is compared with two individually programmable values defined in register RAH. Similarly, two values can be programmed in register RAL for the low address byte. A valid address is recognized when the high byte and the low byte of the address field correspond to one of the compare values. Thus, the TE3-CHATT can be called (addressed) with 4 different address combinations. In case of a 1-byte address, RAL will be used as compare registers. The HDLC control field, data in the I-field and an additional status byte are temporarily stored in the receive FIFO. Preamble Transmission If enabled, a programmable 8-bit pattern XCR1.PBYTE is transmitted with a selectable number of repetitions after interframe time-fill transmission is stopped and a new frame is ready to be sent out. Zero Bit Insertion is disabled during preamble transmission. To guarantee correct function the programmed preamble value should be different from Receive Address Byte values. Data Sheet 102 05.2001 PEB 3456 E Functional Description 4.8.2 Transparent Mode In transparent mode, fully transparent data transmission/reception without HDLC framing is performed, i.e. without FLAG generation/recognition, CRC generation/check, or bit-stuffing. This feature can be profitably used e.g for: * Specific protocol variations * Test purposes Data transmission is always performed out of the transmit FIFO (XFF.XFIFO). In transparent mode receive data is shifted into the receive FIFO without protocol processing. If the transparent mode is selected, the TE3-CHATT supports the continuous transmission of the contents of the transmit FIFO. After having written 1 to 32 bytes to transmit FIFO, the command HND via the CMDR register forces the TE3-CHATT to repeatedly transmit the data stored in transmit FIFO to the remote end. The cyclic transmission continues until a reset command (HND. SRES) is issued or with resetting CMDR.XREP, after which continuous `1'-s are transmitted. 4.8.3 BOM Mode The signalling controller supports the DL channel protocol for ESF format according to ANSI T1.403 or according to AT&T TR54016. The Bit Oriented Message (BOM) receiver can be switched on or off separately. If the signalling controller is used for HDLC formats only, the BOM receiver has to be switched off (RCR1.BRAC = '0'). If HDLC and BOM receiver are switched on, an automatic switching between HDLC and BOM mode is done, which depends on the received bit sequence ( 01111110B or 11111111B). If eight or more consecutive ones are detected, the BOM mode is entered automatically. Upon detection of a flag in the data stream, the FDL-Macro switches back to HDLC-mode. Once in BOM mode, if eight consecutive ones are not detected in 32 bits, a BOM header error will be declared. Transmission of BOM data is done via the transparent mode of the signalling controller. BOM Regular Mode The following byte format is assumed (the left most bit is received first): 111111110xxxxxx0B The signalling controller uses the FFH byte for synchronization, the next byte is stored in the receive FIFO (first bit received: LSB) if it starts and ends with a `0'. Bytes starting or ending with a `1' are not stored. If there are no 8 consecutive one's detected within 32 bits and the FDL-Macro is currently in the BOM mode, an 'Incorrect Synchronization Format' interrupt vector is generated. However, byte sampling is not stopped. Data Sheet 103 05.2001 PEB 3456 E Functional Description After detecting an HDLC flag, byte sampling is stopped, the receive status byte marking a BOM frame is stored in the receive FIFO and a 'Receive Message End' interrupt vector is generated. Byte sampling may be stopped by deactivating the BOM receiver (RCR1.BRAC). In this case the receive status byte marking a BOM frame is added, a 'Receive Message End' interrupt vector is generated and HDLC mode is entered. BOM Filter Mode In BOM filter mode the received BOM data is validated and then filtered. If same valid BOM pattern is received for 7 out of 10 patterns, then BOM data is written to the receive FIFO along with the status byte indicating that filtered BOM data was received. Filtered BOM mode will be exited if one of the following conditions occurs: * 4 valid BOM patterns are consecutively received but none of these equals the BOM data received earlier. * 4 times idle pattern is received. * A HDLC flag is received. 4.8.4 Sa-bit Access The TE3-CHATT supports the Sa-bit signaling of time-slot 0 of the T1/E1 signals in several ways. The access via registers RSAW and XSAW, capable of storing the information for a complete multiframe, and the most effective one is the access via the receive/transmit FIFOS of the integrated signaling controller. The extended Sa-bit access gives the opportunity to transmit/receive a transparent bit stream as well as HDLC frames where the signaling controller automatically processes the HDLC protocol. Data written to the transmit FIFO will subsequently be transmitted in the selected Sa-bit positions. Any combination of Sa-bits can be selected. After the data have been completely sent out an "all ones" or flags will be transmitted. The continuous transmission of a transparent bit stream, which is stored in the XFF.XFIFO, can be enabled. The access to and from the FIFOs is supported by status and interrupts. Sa-Bit Detection according to ETS 300233 Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit combinations. The TE3-CHATT can be programmed to detect any bit combination on one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The corresponding status in register RSAW4 will be set. Register RSAW4 is from type "Clear on Read". With any change of state of the selected Sa-bit combinations a 'SSM Data Valid' interrupt vector will be generated. Data Sheet 104 05.2001 PEB 3456 E Functional Description During the basic frame asynchronous state updating of register RSAW4 and interrupt vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit combinations can be done either synchronous or asynchronous to the submultiframe. In synchronous detection mode updating of register RSAW4 is done in the multiframe synch. state. In asynchronous detection mode updating is independent to the multiframe synchronous state. Sa-bit Error Indication Counters The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit sequence 0001B or 0011B or user programmable values in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors are reported from the TE via Sa6. Incrementing is only possible in the multiframe synchronous state. The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit sequence 0010B or 0011B or user programmable values in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors detected at Treference points are reported via Sa6. Incrementing is only possible in the multiframe synchronous state. 4.8.5 Signalling Controller FIFO Operations Access to the FIFO's of the signalling controllers is handled via registers RFF and XFF. FIFO status and commands are exchanged using the port status registers PSR and the handshake register HND. Additional facility data link interrupt vectors inform system software about protocol and FIFO status. Receive FIFO In receive direction there are different interrupt indications associated with the reception of data: * A 'Receive Pool Full' (RPF) interrupt vector is indicating that a data block can be read from the receive FIFO and the received message is not yet complete. It is generated, when the amount of data bytes has reached the programmed threshold. * A 'Receive Message End' (RME) interrupt vector is indicating that the reception of one message is completed. After this interrupt system software has to read the PSR register in order to get the number of bytes stored in the receive FIFO. This number includes the status byte which is written into the receive FIFO as the last byte after the received frame. The status byte includes information about the CRC result, valid frame indication, abort sequence or data overflow. The format of the status byte is shown in the table below: 7 6 5 SMODE(1:0) BRFO Data Sheet 4 0 STAT(4:0) 105 05.2001 PEB 3456 E Functional Description SMODE BRFO STAT Receiver Status Mode This bit indicates the type of data received. 10B HDLC data 01B BOM data BOM Receive FIFO Overflow 0 No overflow 1 Receive FIFO overflow Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. HDLC mode BOM MODE 00000B Valid HDLC Frame BOM Filtered data declared 00001B Receive Data Overflow BOM data available 00010B Receive Abort BOM End 00011B Not Octet BOM filtered data undeclared 00100B CRC Error BOM header error (ISF, incorrect synchronization format) 00101B Channel Off After the received data has been read from the FIFO, the receive FIFO can be released by the CPU by issuing a 'Receive Message Complete' (HND.RMC) command. The CPU has to process a 'Receive Pool Full' interrupt vector and issue the 'Receive Message Complete' command before the second page of the FIFO becomes full. Otherwise a 'Receive Data Overflow' condition will occur. This time is dependent on the threshold programmed (smaller threshold results in shorter time). Data Sheet 106 05.2001 PEB 3456 E Functional Description * Receive frame (79 bytes) FDL channel 32 bytes 32 bytes 15 bytes Local Bus Interface RD 32 bytes RPF RD 32 bytes RMC RPF RD RD RD RBC 15 bytes status RMC RMC RME Figure 4-12 Interrupt Driven Reception Sequence Example Transmit FIFO In the transmit direction after checking the transmit FIFO status by polling the transmit FIFO write enable bit (PSR.XFW) or after a 'Transmit Pool Ready' (XPR) interrupt vector, up to 32 bytes may be written to the transmit FIFO (bit field XFF.XFIFO) by the CPU. Transmission of a frame can be started by issuing a 'Transmit Transparent Frame' (XTF) or 'Transmit HDLC Frame' (XHF) command via register HND. If the transmit command does not include a 'Transmit Message End' indication (HND.XME), the signalling controller will repeatedly request for the next data block by means of a XPR interrupt vector as soon as the transmit FIFO becomes free. This process will be repeated until the local CPU writes the last bytes to the transmit FIFO. The end of message is then indicated per HND.XME command, after which frame transmission is finished correctly by appending the CRC and closing flag sequence. Consecutive frames may share a flag (enabled via bit XCR1.SF) or may be transmitted as back-to-back frames, if service of transmit FIFO is quick enough. In case that no more data is available in the transmit FIFO prior to the arrival of HND.XME, the transmission of the frame is terminated with an abort sequence and the CPU is notified via a 'Transmit Data Underrun' interrupt vector (XDU). The frame may also be aborted per software by setting the XAB bit in the handshake register HND. Data Sheet 107 05.2001 PEB 3456 E Functional Description * Transmit frame (79 bytes) 32 bytes FDL channel 32 bytes 15 bytes Local Bus Interface WR 32 bytes WR 32 bytes XTF XPR WR 15 bytes XTF XPR XTF+XME XPR ALLS Figure 4-13 Interrupt Driven Transmit Sequence Example Note: Transmit FIFO is 16 bit wide. In the given example writing 32 bytes requires 16 write accesses. Writing 15 byte requires 8 accesses. 4.9 M12 Multiplexer/Demultiplexer and DS2 framer The M12 multiplexer and the DS2 framer can be operated in two modes: * M12 multiplex format according to ANSI T1.107 * ITU-T G.747 format 4.9.1 M12 multiplex format The framing structure of the M12 signal is shown in Table 4-11. A DS2 multiframe consists of four subframes. Each subframe combines 6 blocks with 49 bits each. The first bit of each block contains an overhead (OH) bit and 48 information bits. The 48 information bits are divided into four time slots of 12 bits each. The first time slot is Data Sheet 108 05.2001 PEB 3456 E Functional Description assigned to the 1st tributary DS1 signal, the second time slot is assigned to the 2nd tributary DS1 signal and so forth. Table 4-11 M12 multiplex format Subframe Block 1 through 6 of a subframe 1 DS2Multiframe 2 3 4 5 6 1 0M [48] C11 [48] F0 [48] C12 [48] C13 [48] F1 [48] 2 1M [48] C21 [48] F0 [48] C22 [48] C23 [48] F1 [48] 3 1M [48] C31 [48] F0 [48] C32 [48] C33 [48] F1 [48] 4 X F0 [48] C42 [48] C43 [48] F1 [48] [48] C41 [48] F0, F1 F0 and F1 form the frame alignment pattern. Each DS2 frame consists of eight F-bits, two per subframe in block 3 and 6. F0 and F1 form the pattern '01'. This pattern is repeated in every subframe. X This bit is the forth bit of the multiframe alignment signal and can be set to either '0' or '1'. It is accessible via an internal register. M0, M1,MX M0 and M1 and MX form the multiframe alignment signal. Each subframe consists of four M-bits and they are located in bit 0 of each subframe. The multiframe alignment signal is '011-'. C11..C43 The C-bits control the bit stuffing procedure of the multipexed DS1 signals. [48] These bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12 bit and each time slot is assigned to one of four participating DS1 signals. 4.9.1.1 Synchronization Procedure The integrated DS2 framer searches for the frame alignment pattern '01' and the multiframe alignment pattern in each of the seven DS2 frames which are contained in a DS3 signal. Frame alignment is declared, when the DS2 framer has found the basic frame alignment pattern (F-bit) and the multiframe alignment pattern (M-bit). Loss of frame is declared, when 2 out of 4 or 3 out of 5 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. Data Sheet 109 05.2001 PEB 3456 E Functional Description 4.9.1.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts four DS1 signals out of each DS2 signal. If two out of three bits of Ci1, Ci2, Ci3 are set to '1' the first information bit in the ith subframe and the 6th block which is assigned to the ith DS1 signal is discarded. The demultiplexer performs inversion of the 2nd and 4th tributary DS1 signal. Multiplexer The multiplexer combines four DS1 signals to form a DS2 signal. Stuffing bits are inserted and the Ci1-, Ci2-, Ci3-bits, which are assigned to the ith DS1 signal, are set to '1' in case that not enough data is available. The 2nd and 4th DS1 signal are automatically inverted in transmit direction. 4.9.1.3 Loopback Control Detection Loopback requests encoded in the C-bits of the DS2 signal are flagged when they are repeated for at least five DS2 multiframes. Loops must be initiated by an external microprocessor. Generation A loopback request, which is transmitted in lieu of the C-bits, can be placed in each DS2 signal. 4.9.1.4 Alarm Indication Signal Detection AIS is declared, when the AIS condition (the received DS2 data stream contains an all `1' signal with less then 3/9 zeros within 3156 bits while the DS2 framer is out of frame) is present within a time interval that is determined by register D2RAP. Generation The alarm indication signal is an all '1' unframed signal and will be transmitted if enabled. Data Sheet 110 05.2001 PEB 3456 E Functional Description 4.9.2 ITU-T G.747 format The multiplexing frame structure is shown in Table 4-12. Table 4-12 ITU-T G.747 format Set I Content Frame Alignment Signal 111010000 Bits from tributaries II 1 Parity Bit 2 3 Bits from tributaries III Justification control bits Cj1 Bits from tributaries IV Justification control bits Cj2 Bits from tributaries V 4 to 168 1 to 3 4 to 168 1 to 3 4 to 168 Justification control bits Cj3 1 to 3 Bits from tributaries available for justification 4 to 6 Bits from tributaries 4.9.2.1 1 to 9 10 to 168 Alarm indication to the remote multiplex equipment Reserved ITU-T G.747 Frame Bit 7 to 168 Synchronization Procedure The integrated framer searches for the frame alignment pattern '111010000' in each of the seven frames which are contained in a DS3 signal. Frame alignment is declared, when the framer has found three consecutive correct frame alignment signals. If the frame alignment signal has been received incorrectly in one of the following frames after the receiver found the first correct frame alignment signal a new search is started. Loss of frame is declared, when four consecutive frame alignment signals have been received incorrectly. 4.9.2.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts three E1 signals from each 6.312 MHz signal. If two out of three bits of Cj1, Cj2, Cj3 are set to '1' the available justification bit of the jth E1 signal is discarded. Data Sheet 111 05.2001 PEB 3456 E Functional Description Multiplexer The multiplexer combines three E1 signals to form a DS2 signal. Stuffing bits are inserted and the Cj1-, Cj2-, Cj3-bits, which are assigned to the jth E1 signal, are set to '1' in case that not enough data is available. 4.9.2.3 Parity Bit Detection The receiver optionally calculates the parity of all tributary bits and compares this value with the received parity bit. Differences are counted in the parity error counter. Generation The parity bit is automatically calculated according to ITU-T G.747 or programmable to a fixed value under microprocessor control. 4.9.2.4 Remote Alarm Indication Detection Remote alarm is reported when bit 1 of set II changes and when the change persists for at least three multiframes. Generation Remote alarm is transmitted in bit 2 of "set II" and can be inserted under microprocessor control. 4.9.2.5 Alarm Indication Signal Detection AIS is declared, when the AIS condition (the received DS2 data stream contains an all `1' signal with less then 5/9 zeros within two consecutive multiframes while the DS2 framer is out of frame) is present within a time interval that is determined by register D2RAP. Generation The alarm indication signal is an all '1' unframed signal and will be transmitted if enabled. 4.10 M23 multiplexer and DS3 framer The M23 multiplexer and the DS3 framer can be operated in three modes: Data Sheet 112 05.2001 PEB 3456 E Functional Description * M23 multiplex format * C-bit parity format with modified M23 multiplex operation * C-bit parity format with non-M23 multiplex operation (Full payload rate format) 4.10.1 M23 multiplex format The framing structure of the M23 multiplex signal is shown in Table 4-13. Each DS3 multiframe consists of 7 subframes and each subframe of eight blocks. One block consists of 85 bits, where the first bit is the overhead (OH) bit and the remaining 84 bits are the information bits. The 84 information bits are divided into seven time slots of 12 bits each. The first time slot is assigned to the 1st tributary DS2 signal, the second time slot is assigned to the 2nd tributary DS2 signal and so forth. Table 4-13 Subframe DS3Multiframe M23 multiplex format Block 1 through 8 of a subframe 1 2 3 4 5 6 7 8 1 X [84] F1 [84] C11 [84] F0 [84] C12 [84] F0 [84] C13 [84] F1 [84] 2 X [84] F1 [84] C21 [84] F0 [84] C22 [84] F0 [84] C23 [84] F1 [84] 3 P [84] F1 [84] C31 [84] F0 [84] C32 [84] F0 [84] C33 [84] F1 [84] 4 P [84] F1 [84] C41 [84] F0 [84] C42 [84] F0 [84] C43 [84] F1 [84] 5 M0 [84] F1 [84] C51 [84] F0 [84] C52 [84] F0 [84] C53 [84] F1 [84] 6 M1 [84] F1 [84] C61 [84] F0 [84] C62 [84] F0 [84] C63 [84] F1 [84] 7 M0 [84] F1 [84] C71 [84] F0 [84] C72 [84] F0 [84] C73 [84] F1 [84] F0, F1 F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern '1001'. This pattern is repeated in every subframe. M0, M M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first block in subframe 5,6 and 7. The multiframe alignment signal is '010'. C11..C73 The C-bits control the bit stuffing procedure of the multipexed DS2 signals. P The P-bits contain parity information and are calculated as even parity on all information bits of the previous DS3 frame. Both P-bits are identical. X The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be identical and may not change more than once every second. Data Sheet 113 05.2001 PEB 3456 E Functional Description [84] These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating DS2 signals. 4.10.1.1 Synchronization Procedure The integrated DS3 framer searches for the frame alignment pattern '1001' and when found for the multiframe alignment pattern in each of the seven DS3 subframes. When the multiframe alignment pattern is found in three consecutive DS3 frames while frame alignment is still valid frame alignment is declared. The P-bits and the X-bits are ignored during synchronization. Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. 4.10.1.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. If two or three bits out of Ci1, Ci2, Ci3 are set to '1' the first bit following the F1 bit in the ith subframe which is assigned to the ith DS2 signal is discarded. Multiplexer The multiplexer combines seven DS2 signals to form a DS3 signal. If not sufficient data is available for a DS2 signal, it automatically inserts a stuffing bit and sets the bits Ci1, Ci2, Ci3 assigned to the ith DS2 signal to '1'. 4.10.1.3 X-bit The TE3-CHATT provides access to the X-bit of each tributary via an internal registers. Data written to the X-bit register is copied to an internal shadow register which is then locked for one second after each write access. 4.10.1.4 Alarm Indication Signal, Idle Signal Detection Alarm indication signal or Idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one multiframe. The alarm indication signal can be selected as: * Unframed all '1's Data Sheet 114 05.2001 PEB 3456 E Functional Description * Framed '1010' sequence, starting with a binary '1' after each OH-bit. C-bits are set to `0'. X-bit can be checked as `1' or X-bit check can be disabled. The idle signal is a * Framed '1100' sequence, starting with a binary '11' after each OH-bit. C-bits are set to `0' in M-subframe 3. X-bit can be checked as `1' or X-bit check can be disabled. Generation The alarm indication signal or idle signal will be generated according to the selected signal format. X-bit needs to be set seperately to `1'. 4.10.1.5 Loss of Signal Detection Loss of signal is declared, when the incoming data stream contains more than 1022 consecutive '0's. Recovery Loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.10.1.6 Performance Monitor The following conditions are counted: * * * * * * Line code violations Excessive zeroes P-bit errors, CP-bit errors Framing bit errors Multiframe bit errors Far end block errors Data Sheet 115 05.2001 PEB 3456 E Functional Description 4.10.2 C-bit parity format The framing structure of the C-bit parity format is shown in Table 4-13. The assignment of the information bits [84] is identical to the M23 multiplex format, but the function of the C-bits is redefined for path maintenance and data link channels. Table 4-14 Subframe DS3Multiframe C-bit parity format Block 1 through 8 of a subframe 1 2 3 4 5 6 7 8 1 X [84] F1 [84] AIC [84] F0 [84] Nr [84] F0 [84] FEAC [84] F1 [84] 2 X [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] 3 P [84] F1 [84] CP [84] F0 [84] CP [84] F0 [84] CP [84] F1 [84] 4 P [84] F1 [84] FEBE [84] F0 [84] FEBE [84] F0 [84] FEBE [84] F1 [84] 5 M0 [84] F1 [84] DLt [84] F0 [84] DLt [84] F0 [84] DLt [84] F1 [84] 6 M1 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] 7 M0 [84] F1 [84] DL [84] F0 [84] DL [84] F0 [84] DL [84] F1 [84] F0, F1 F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern '1001'. This pattern is repeated in every subframe. M0, M M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first block in subframe 5,6 and 7. The multiframe alignment signal is '010'. Nr Reserved. Set to '1' in transmit direction. AIC Application Identification Channel. DLt The terminal-to-terminal path maintenance data link uses the HDLC protocol. Access to the DLt bits is possible via the DS3 transmit and receive FIFO. DL Reserved. Set to '1' in transmit direction. FEAC The alarm or status information of a far end terminal is sent back over the far end and control channel. This bit also contains DS3 or DS1 line loopback requests. Messages are sent in bit oriented mode. Message codes can be accessed via an internal register. FEBE The far end block error bits indicate a CP-bit parity error or a framing error. They are used to Data Sheet 116 05.2001 PEB 3456 E Functional Description monitor the performance of a DS3 signal. Upon detection of either error in the incoming data stream the FEBE-bits are set automatically to '000' in the outgoing direction. Received far end block errors are counted. CP The CP-bits are used to carry path parity information and are set to the same value as the P-bits. In receive direction the CP-bits are checked against the calculated parity and differences are counted. P The P-bits contain parity information and are automatically calculated as even parity on all information bits of the previous DS3 frame. X The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be identical and may not change more than once every second. Access to the X-bits is possible via a register. [84] These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with 12 bits each and they are assigned to one of the seven participating DS2 signals. 4.10.2.1 Synchronization Procedure The integrated DS3 framer searches for the frame alignment pattern '1001' and when found for the multiframe alignment pattern in each of the seven DS3 subframes. Frame alignment is declared when the multiframe alignment pattern is found in three consecutive DS3 frames. The P-bits and the X-bits are ignored during synchronization. Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or when one or more incorrect M-bits are found in 3 out of 4 subframes. 4.10.2.2 Multiplexer/Demultiplexer Demultiplexer The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. Since the DS3 signal is always stuffed the stuffing bit assigned to each DS2 signal is discarded. Multiplexer The multiplexer combines seven DS2 signals to form a DS3 signal and automatically inserts a stuffing bit for each DS2 signal. 4.10.2.3 X-bit The TE3-CHATT provides access to the X-bits via internal registers. Data Sheet 117 05.2001 PEB 3456 E Functional Description 4.10.2.4 Far End Alarm and Control Channel The far end alarm and control channel is accessible via the signalling controller in BOM mode. 4.10.2.5 Path Maintenance Data Link Channel The path maintenance data link channel is accessible via the signalling controller in HDLC mode. 4.10.2.6 Loopback Control Detection Loopback requests are encoded in the messages of the far end alarm and control channel. The microprocessor has access to the messages as described in Chapter 4.10.2.4. Generation A loopback request can be initiated via the far end alarm and control channel. 4.10.2.7 Alarm Indication Signal, Idle Signal Detection Alarm indication signal or Idle signal is declared, when the selected signal format was received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one multiframe. The alarm indication signal can be selected as: * Unframed all '1's * Framed '1010' sequence, starting with a binary '1' after each OH-bit. C-bits are set to `0'. X-bit can be checked as `1' or X-bit check can be disabled. The idle signal is a * Framed '1100' sequence, starting with a binary '11' after each OH-bit. C-bits are set to `0' in M-subframe 3. X-bit can be checked as `1' or X-bit check can be disabled. Generation The alarm indication signal or idle signal will be generated according to the selected signal format. X-bit needs to be set seperately to `1'. Data Sheet 118 05.2001 PEB 3456 E Functional Description 4.10.2.8 Loss of Signal Detection Loss of signal is declared, when the incoming data stream contains more than 1022 consecutive '0's. Recovery Loss of signal is removed, when two or more ones are detected in the incoming data stream. 4.10.2.9 Performance Monitor The following conditions are counted: * * * * * * Line code violations Excessive zeroes P-bit errors, CP-bit errors Framing bit errors Multiframe bit errors Far end block errors Data Sheet 119 05.2001 PEB 3456 E Functional Description 4.10.3 Full Payload Rate Format In full payload rate format the DS3 multiframe structure can be selected according to the M13 multiplex structure or the C-bit parity structure. In either case the data blocks [84] carry one continuous data stream which is provided via the tributary interface one. Multiplexing/Demultiplexing of the data block [84] does NOT apply. 4.11 Test Unit The test unit of the TE3-CHATT incorporates a test pattern generator and a test pattern synchronizer which can be attached to different test points as shown in Figure 4-14. Controlled by a small set of registers it can generate and synchronize to polynomial pseudorandom test patterns or repetitive fixed length test patterns. Test patterns can be generated in the following modes: * * * * Framed DS3 Unframed DS2 Framed DS2 Unframed DS1/E1 * DS3 Framer M12 To T1/E1 Framer DS2 Framer DS2 Framer M23 (De)multiplexer M12 DS2 Framer 0 6 Test Port Select 0 6 Test Port Select 0 27 Test Port Select Test Mode Select Test Unit Figure 4-14 Test Unit Access Points In pseudorandom test mode the receiver tries to achieve synchronization to a test pattern which satisfies the programmed receiver polynomial. In fixed pattern mode it synchronizes to a repetitive pattern with a programmable length. An all '1' pattern or an all '0' pattern, which satisfies this condition, is flagged. Measurement intervals as well as receiver synchronization can be controlled by the user. When a test is finished an interrupt is generated and the bit count and the bit error count are readable. Data Sheet 120 05.2001 PEB 3456 E Functional Description * + Feedback in Pseudorandon pattern mode only 0 N X 1 X-1 X N-2 N-1 + Bit error insertion Pattern length Feedback Tap Figure 4-15 Pattern Generator Bit Error Insertion The test unit provides the optional capability to insert bit errors in the range of 10-7 (1 error in 10.000.000 bits) up to 10-1 bit errors (1 error in 10 bits). 4.12 Mailbox The TE3-CHATT contains a mailbox to allow communication between two intelligent peripherals connected to the PCI bus and the local microprocessor bus. The mailbox is organized in two pages of eight registers. The first page is used to store information from the PCI side and to read the information from the local microprocessor side. The second page is used for the opposite direction, from the local microprocessor side to the PCI side. Each page consists of one status register and seven data registers. The mailbox provides a `doorbell' capability. In this case an interrupt vector can be generated to inform the addressed intelligent peripheral that new information has been stored in the mailbox. This interrupt vector will be generated on write accesses to the status register of the selected page. As an example, consider when the PCI host system wants to transfer data to an intelligent peripheral. First it loads data into the mailbox data registers MBP2E1 through MBP2E7, and then writes a status information to the mailbox status register MBP2E0. This last action causes an interrupt vector to be written to the interrupt FIFO which is connected to the local bus. The presence of an interrupt vector results in assertion of pin LINT. The intelligent peripheral recognizes the interrupt pin asserted and reads the interrupt vector out of the interrupt FIFO (which results in deassertion of pin LINT), and then reads data from the mailbox data registers. Data Sheet 121 05.2001 PEB 3456 E Functional Description * Interrupt Vector INTA MBE2P0 read only MBE2P1..MBE2P7 PCI Interface read only Interrupt Controller Local Bus Configuration Bus II MBP2E1..MBP2E7 Mailbox registers Local Bus --> PCI Interrupt Controller PCI Side Interrupt Vector MBP2E0 Local Bus Interface LINT Configuration Bus I Mailbox registers PCI --> Local Bus Figure 4-16 Mailbox Structure Alternately, consider when an intelligent peripheral connected to the local bus wants to transfer data to the PCI host system. First it loads data into the mailbox data registers MBE2P1 through MBE2P7 and then it writes status information to the mailbox status register MBE2P0. This causes a system interrupt vector to be written to the PCI host system, indicating that valid data is contained in the mailbox data registers. This interrupt vector will be written to the interrupt queue specified in CONF1.SYSQ and together with this the pin INTA will be asserted. The processor sees the interrupt pin asserted, reads the register GISTA in order to determine the interrupt queue, and then writes a `1' to the interrupt status acknowledge register GIACK to clear the interrupt. Next, it reads the interrupt vector which contains a copy of the mailbox status register and then reads the mailbox data registers. 4.13 Interrupt Controller Since the TE3-CHATT is divided into the basic functions mailbox, layer one functions (T1/E1 framer, facility data link, M13 multiplexer and DS2/DS3 framer) and layer two protocol functions (HDLC, PPP, TMA), the same partitioning is used for the interrupt handling. All layer two interrupts (channel, port, system and command interrupts) are handled via an internal interrupt controller which forwards those interrupts to external interrupt queues. This interrupt controller is connected to the PCI interrupt pin INTA. Data Sheet 122 05.2001 PEB 3456 E Functional Description Mailbox interrupts and layer one interrupts are handled via an internal interrupt FIFO which is connected to the local bus interrupt pin LINT (normal operation). Additionally the interrupts stored in the internal interrupt FIFO can be notified via the PCI interrupt pin INTA. The TE3-CHATT also provides the capability to bridge the local bus interrupt LINT to the PCI bus. 4.13.1 Layer Two interrupts All channel interrupts, port interrupts and system interrupts are written in form of interrupt vectors to interrupt queues. Each interrupt vector has an interrupt source. An interrupt source is either a channel, the port handler or certain device functions (system interrupts). After reset no interrupt vector is generated since port and system interrupts are masked and channels are in their idle state. Each interrupt source forwards its interrupt vector to the interrupt controller, together with the information in which interrupt queue the vector should be forwarded. The interrupt controller moves the interrupt vector to the selected interrupt queue. Channel interrupts can optionally be forwarded to a dedicated high priority interrupt queue (interrupt queue seven). A programmable interrupt queue high priority mask determines channel interrupts, which shall be forwarded into the high priority interrupt queue instead of queueing them in the selected interrupt queue. This function is available for each interrupt queue and allows to queue important interrupt conditions in the high priority queue. Data Sheet 123 05.2001 PEB 3456 E Functional Description * Int. vector setup: CSPEC_IVMASK, CSPEC_BUFFER Int. vector setup: CONF1, CONF2 Int. vector setup: PMR, CONF2 Channel, Command interrupts System interrupts 256 Port interrupts 1 IV 1 Interrupt bus Interrupt status: GISTA, GMASK Interrupt queue setup: IQIA, IQBA, IQL, IQMASK from layer one interrupt FIFO Interrupt controller LINT 2 PCI interface INTA 4 PCI bus 5 FFFFFFFFH 3 Microprocessor System memory Interrupt queue IQBA 1. Interrupt source forwards interrupt vector to interrupt controller. 2. Interrupt controller moves interrupt vector to interrupt queue. 3. Interrupt controller asserts INTA (if enabled). 4. Microprocessor reads status register GISTA. 5. Microprocessor reads interrupt queue. 00000000H Figure 4-17 Layer Two Interrupts (Channel, command, port and system interrupts As soon as the interrupt controller has written an interrupt vector to one of the nine interrupt queues the PCI interrupt pin INTA is asserted. The global interrupt status register indicates in which interrupt queue the interrupt vector can be found. Each of the Data Sheet 124 05.2001 PEB 3456 E Functional Description nine interrupt queues can be masked. In this case the interrupt pin INTA is not asserted, but the interrupt vector is still written into the assigned interrupt queue. An interrupt queues is a reserved memory locations in system memory. The TE3-CHATT supports up to eight interrupt queues which are organized in form of ring buffers with a programmable start address and a programmable size per interrupt queue. Additionally there is one fixed sized command interrupt queue where command interrupts are stored. The size of this queue is two times 256 DWORDs (Figure 4-18). * Channel 255: Transmit Command IV ring buffer Interrupt Vector IQL*16 Channel 0: Transmit Command IV Channel 255: Receive Command IV Interrupt Vector 3 IQBA+4H Interrupt Vector 2 IQBA+4H Channel 1: Receive Command IV IQBA Interrupt Vector 1 IQBA Channel 0: Receive Command IV Channel, Port and System Interrupt Queue Command Interrupt Queue Note: IV = Interrupt Vector Figure 4-18 Interrupt Queue Structure in System Memory 4.13.1.1 General Interrupt Vector Structure Each interrupt vector is 32 bit wide and contains several subfields, which indicate the interrupt group and depend on the interrupt group the interrupt information. Bit 31 of the interrupt vector is generally set to '1' by the TE3-CHATT and allows the system CPU to clear the bit in order to mark processed interrupts. Table 4-15 Interrupt Vector Structure 31 30 29 1 TYPE(1:0) 28 27 STYPE(1:0) 26 24 23 QUEUE(2:0) 16 INT(23:0) 15 0 INT(23:0) Data Sheet 125 05.2001 PEB 3456 E Functional Description TYPE Interrupt type The interrupt vectors are divided into four basic groups, where TYPE determines the interrupt group. A further classification of interrupts is done with the subtype indication. STYPE 00B Command interrupts 01B Channel interrupts 10B Port interrupts 11B System interrupts Interrupt subtype A specific interrupt type is divided into several subtypes. In general STYPE(1) indicates the data path (transmit, receive) generating the interrupt. QUEUE Interrupt queue The interrupt vectors are written into 9 external interrupt queues located in the shared memory. Corresponding to these 9 queues are 9 interrupt queue start addresses and 8 interrupt queue length registers, since the interrupt queue 8 has a fixed length of 2 x 256). INT Interrupt Information INT itself contains the interrupt information. The meaning of INT is dependent on TYPE and STYPE indication. Data Sheet 126 05.2001 PEB 3456 E Functional Description 4.13.1.2 System Interrupts * 31 30 1 29 11B 28 27 00B 26 24 QUEUE(2:0) 20 0 0 0 15 MB 19 18 17 16 RBF RBEWRAEW PB 0 INFO(15:0) MB Mailbox The 'Mailbox' interrupt vector is generated, in case that the local microprocessor has written data to the mailbox status register MBE2P0. The bit field INFO contains a copy of MBE2P0. RBAF Receive Buffer Access Failed The 'Receive Buffer Access Failed' interrupt vector is generated, when the protocol machine discarded packets due to permanent inaccessibility of the receive buffer. This interrupt is issued as soon as the programmable threshold stored in register RBAFT is reached. The actual value of discarded packets is stored in register RBAFC. RBEW Receive Buffer Queue Early Warning The 'Receive Buffer Queue Early Warning' interrupt vector is generated, when the receive buffer data threshold has been exceeded (RBTH.RBTH). This interrupt can be masked via bit CONF1.RBIM. RAEW Receive Buffer Action Queue Early Warning The 'Receive Buffer Action Queue Early Warning' interrupt vector is generated, when the receive data action queue threshold (RBTH.RBAQTH) has been exceeded. The receive buffer action queue stores all requests of the receive buffer to forward data packets to system memory. This interrupt vector can be masked via bit CONF1.RBIM. PB PCI Access Error The 'PCI Access Error' interrupt vector is generated, when system software tries to read/write internal registers with accesses that do not enable all byte lanes, e.g. the access is not a full 32 bit access. The bit field INFO contains the register address which was tried to access. INFO Data Sheet Contains additional interrupt information data according to the bit, which is set: See specific interrupt for details. 127 05.2001 PEB 3456 E Functional Description 4.13.1.3 Port Interrupts Port interrupt vectors indicate the synchronous or asynchronous state of a port. Immediately after enabling both, the port and the port interrupts, port interrupts are generated indicating the synchronous or asynchronous state of a port. After this initial interrupt vector generation, further interrupts are written only when the state of a port changes from synchronous state to asynchronous state or vice versa. Port interrupts are enabled by resetting the corresponding mask bit in register PMR. Transmit interrupts * 31 30 1 29 28 27 10B 10B 26 24 QUEUE(2:0) 17 0 0 15 0 0 PORT 0 0 0 0 0 0 0 0 0 0 5 4 0 0 0 16 SYN ASYN 0 PORT(4:0) Port Number This bit field identifies the port for which the information in the interrupt vector is valid. SYN Synchronization achieved Port has changed from asynchronous state to synchronous state. This interrupt is available for ports configured in T1 or E1 mode. In unchannelized mode there is no synchronous state. A transmit port changes to the synchronous state, if common transmit frame synchronization is enabled and the number of bits between two synchronization pulses is equal to the number of frame bits of the selected mode or is equal to a multiple of that number. The first CTFS pulse after a port is enabled causes the transmitter to change to the synchronous state. In case the common transmit frame synchronization is disabled, i.e. the looped timing bit or the CTFS disable bit of a port is set in PMR, the initial asynchronous state will not be left. ASYN Asynchronous State The transmitter generates an 'Asynchronous State' interrupt vector if a port has changed from synchronous to asynchronous state. This interrupt is available for ports configured in T1, E1 mode. In Data Sheet 128 05.2001 PEB 3456 E Functional Description unchannelized mode there is no asynchronous state. In general a port is in asynchronous state when a port is disabled. A transmit port changes to the asynchronous mode if the number of bits between two synchronization pulses is not equal to a multiple of the number of frame bits of the selected mode Receive Interrupts * 31 30 1 29 28 27 00B 10B 26 24 QUEUE(2:0) 17 0 0 0 15 0 0 0 0 SYN ASYN 4 0 PORT 0 0 0 0 0 0 0 0 0 16 0 PORT(4:0) Port Number This bit field identifies the port for which the information in the interrupt vector is valid. SYN Synchronization achieved Port has changed from asynchronous state to synchronous state. This interrupt is available for ports configured in T1, E1 mode. In unchannelized mode there is no synchronous state. A receive port changes to the synchronous state, if the number of bits between two synchronization pulses generated by the port related framer is exactly equal to the number of frame bits of the selected mode. The first framer pulse after a port is enabled causes the receive port to change to the synchronous state. ASYN Asynchronous state Port has changed from synchronous to asynchronous state. This interrupt is available for ports configured in T1 or E1 mode. In unchannelized mode there is no asynchronous state. In general a port is in asynchronous state when a port is disabled. A receive port changes to the asynchronous state if the number of bits between two framer synchronization pulses is not equal to the number of frame bits of the selected mode. The synchronization pulses are generated internally by the T1/E1 framer. Data Sheet 129 05.2001 PEB 3456 E Functional Description 4.13.1.4 Channel Interrupts Channel interrupt are divided into two subtypes: * Receive Interrupt I and Transmit Interrupt I * Receive Interrupt II and Transmit Interrupt II Subtype I contains interrupts which indicate the general status of a channel. These interrupts are not linked to a descriptor. Subtype II contains interrupts which indicate a channel or packet status that is linked to a descriptor. Each interrupt vector contains a descriptor ID which can be used for tracking purposes. Receive Interrupt I * 31 30 1 15 29 28 00B 01B 14 ROFP SF ROFP 27 26 24 QUEUE(2:0) 13 12 11 IFFL IFID SFD 0 0 0 0 0 7 0 0 0 0 0 0 0 CHAN(7:0) Receive Buffer Overflow The 'Receive Buffer Overflow' interrupt vector is generated, when one or more whole frames or short frames or changes of interframe time-fill (HLDC, PPP) or data in general (TMA) has been discarded due to the inaccessibility of the internal receive buffer. SF Short Frame Detected The 'Short Frame Detected' interrupt vector is generated, when the receiver detected a frame which length matches the condition defined in CONF1.SFL. IFFL Interframe Time-fill Flag The 'Interframe Time-fill Flag' interrupt vector is generated, when the receiver detected a interframe time-fill change from FFH to 7EH. IFID Interframe Time-fill Idle The 'Interframe Time-fill Idle' interrupt vector is generated, when the receiver detected a interframe time-fill change from 7EH to FFH. Data Sheet 130 05.2001 PEB 3456 E Functional Description SFD Small Frames Dropped The 'Small Frames Dropped' interrupt vector is generated, when the receiver discarded N small frames. The length of small frames is defined in CONF3.MINFL and the threshold value N is defined in register SFDT. CHAN Channel Number This bit field identifies the channel for which the information in the interrupt vector is valid. Transmit Interrupt I * 31 30 1 29 28 10B 01B 15 14 UR FE UR 27 26 24 QUEUE(2:0) 16 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 CHAN(7:0) Underrun The 'Underrun' interrupt vector is generated, when the transmit buffer was not able to provide data to the protocol machine transmit. If this happens during transmission of a HDLC or PPP packet, the transmitter will end the already started data packet with an abort sequence. FE Frame End The 'Frame End' interrupt vector is generated, when one complete data packet has been transmitted via serial side. CHAN Channel Number This bit field identifies the channel for which the information in the interrupt vector is valid. Data Sheet 131 05.2001 PEB 3456 E Functional Description Receive Interrupt II * 31 30 1 29 28 01B 15 14 RHI RAB CHAN 27 26 01B 13 12 24 QUEUE(2:0) 11 10 9 8 23 22 0 0 21 16 DESID(5:0) 7 FE HRAB MFL RFOD CRC ILEN 0 CHAN(7:0) Channel Number This bit field identifies the channel for which the information in the interrupt vector is valid. RHI (Receive) Host Initiated Interrupt The '(Receive) Host Initiated' interrupt vector will be issued, if bit RHI is set in a receive descriptor and processing of this descriptor has finished. After receiving this interrupt vector, system software can release the descriptor, e.g. put the descriptor into a free pool. RAB Receive Abort The 'Receive Abort' interrupt vector is generated, when an incoming data packet is aborted (more than 6 `1' in case of HDLC or more than 15 `1' in case of PPP) or if the receiver got a receive abort command from the system CPU. FE Frame End The 'Frame End' interrupt Vector is generated, when one complete frame has been received completely and has been stored in system memory. HRAB Hold Caused Receive Abort The 'Hold Caused Receive Abort' interrupt vector is generated, when the receiver discarded the first data packet after it has found a HOLD bit in a receive descriptor. RAB, HRAB Silent Discard The 'Silent Discard' interrupt vector (bit RAB and HRAB set together) occurs, if two or more frames have been discarded by the receiver due to continuous inaccessibility of receive descriptor. This occurs, if receive descriptor has HOLD bit set and receiver gets further data packets. The interrupt vector will be generated for each packet discarded. Data Sheet 132 05.2001 PEB 3456 E Functional Description MFL Maximum Frame Length Exceeded The 'Maximum Frame Length Exceeded' interrupt vector is generated, when the length of a received data packet exceeded the frame length defined in CONF1.MFL. RFOD Receive Frame Overflow DMA The 'Receive Frame Overflow DMA' interrupt indicates that protocol handler was unable to transfer data to the receive buffer. As soon as receive buffer can store data again, this interrupt is generated. CRC CRC Error The 'CRC Error' interrupt vector is generated, when the internally calculated CRC and the CRC of a received packet did not match. ILEN Invalid Length The 'Invalid Length' interrupt vector is generated, when the bit length of received frame was not divisible by 8. Transmit Interrupt II * 31 30 1 29 28 14 THI TAB DESID 26 11B 01B 15 27 24 QUEUE(2:0) 0 12 0 HTAB 21 0 16 DESID(5:0) 7 0 0 0 0 0 CHAN(7:0) Descriptor ID This bit field is a copy of the descriptor ID of the transmit descriptor which is currently in use. It can be used for tracking purposes. THI (Transmit) Host Initiated Interrupt The '(Transmit) Host Initiated' interrupt vector is generated, if bit THI is set in a transmit descriptor and processing of this descriptor has finished. After receiving this interrupt vector, system software can release the descriptor, e.g. put the descriptor into a free pool. TAB Transmit Abort The 'Transmit Abort' interrupt vector is generated, either when the 'Transmit Abort/Branch' command was given and therefore one frame could not be transmitted completely or when NO and FE were set to 0 in a transmit descriptor and previous frame was incompletely specified. Data Sheet 133 05.2001 PEB 3456 E Functional Description HTAB Hold Caused Transmit Abort The 'Hold Caused Transmit Abort' interrupt vector is generated, when data management unit retrieved a transmit descriptor where HOLD was set and FE equals 0. The interrupt will be generated after the data section was transferred completely. After transmission of frame based protocols (HDLC, PPP) protocol machine appends abort sequence due to incomplete packet. CHAN Channel Number This bit field identifies the channel for which the information in the interrupt vector is valid. Data Sheet 134 05.2001 PEB 3456 E Functional Description 4.13.1.5 Command Interrupts Command interrupts are written to the command interrupt queue (interrupt queue eight). Transmit Interrupts * 31 30 1 27 0010B 0 0 0 0 15 0 0 0 0 0 0 17 16 TCF TCC 7 0 TCF 0 0 0 0 0 0 0 CHAN(7:0) Transmit Command Failed The 'Transmit Command Failed' interrupt vector is issued, if the command 'Transmit Init' given via register CSPEC_CMD.XCMD could not be finished. This happens, when *system software tried to allocate more buffer locations for a channel than were available. *system software specified thresholds (transmit forward threshold, transmit refill threshold), which were greater than the specified transmit buffer size. Note:The sum of both thresholds must be smaller than the transmit buffer size of a particular channel. Erroneous programming does NOT result in the 'Transmit Command Failed' interrupt vector. TCC Transmit Command Complete The 'Transmit Command Complete' interrupt vector is issued after successful completion of commands 'Transmit Init' and 'Transmit Off', which can be issued via register CSPEC_CMD.XCMD. CHAN Channel Number This bit field contains the channel number of the affected channel. Data Sheet 135 05.2001 PEB 3456 E Functional Description Receive Interrupts * 31 30 1 27 0000B 16 0 0 0 0 15 0 0 0 0 0 0 0 RCC 7 0 RCC 0 0 0 0 0 0 0 CHAN(7:0) Receive Command Complete The 'Receive Command Complete' interrupt vector is issued after successful completion of commands 'Receive Init' and 'Receive Off', which can be issued via register CSPEC_CMD.RCMD. CHAN Channel Number This bit field contains the channel number of the affected channel. Data Sheet 136 05.2001 PEB 3456 E Functional Description 4.13.2 Layer One Interrupts All layer one related interrupts, that is interrupts issued by either the T1/E1 framer, the M13 multiplexer and DS2/DS3 framer, the facility data link or the PCI to Local Bus mailbox, are stored in an internal interrupt FIFO which is located inside the TE3-CHATT and can be read from either the local microprocessor or (for test purposes) via the chip internal bridge from the host processor located on the PCI bus. The T1/E1 framer, the facility data link, the M13 multiplexer and DS2/DS3 framer, and the mailbox forward their specific interrupts to the internal interrupt FIFO. The interrupt FIFO triggers the LINT pin which indicates that there is at least one interrupt vector available. The interrupt FIFO then can be read from either PCI side or local bus side. The interrupt vector contains a coding for the interrupt reason and a last indication when there is no further interrupt vector stored in the internal interrupt FIFO. The interrupts of the internal layer one interrupt FIFO or the local bus interrupt LINT can also be reported via pin INTA. * Int. ve ctor s e tup: MSK Int. ve ctor s e tup: IMR Facility data link Int. ve ctor s e tup: [] M13 Test unit Framer Int. ve ctor s e tup: FCONF.MID Mailbox IV Interrupt bus II 1 optional interrupt notification on INTA Interrupt FIFO Inte r r upt Contr ol: INTCTRL Inte r r upt s tatus : INTFIFO EBU LINT TE3-CHATT 3 Local uP interface 2 1. Interrupt source forwards interrupt vector to interrupt FIFO. 2. Interrupt controller asserts LINT (if enabled). 3. Microprocessor reads interrupt FIFO. Microprocessor Figure 4-19 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification Data Sheet 137 05.2001 PEB 3456 E Functional Description 4.13.2.1 General Interrupt Vector Structure * 15 14 13 LAST STYPE LAST 7 STATUS(6:0) 6 5 MID(1:0) 4 0 INFO(4:0) Last indication LAST indicates that at least one more valid interrupt vector is stored in the internal interrupt FIFO. This bit is generated at read access time. STYPE 0 There is at least one more interrupt in the internal interrupt FIFO. 1 This interrupt is the last interrupt that is stored in the internal interrupt FIFO. Subtype of interrupt vector This bit is used to indicate different subtypes of interrupt vectors. STATUS Interrupt status The interrupt status depends on STYPE and MID. Please refer to the detailed description of the interrupt vectors in the next chapters. MID Module ID The bit field identifies the interrupt source. INFO 00B T1/E1 Framer Interrupts 01B Facility Data Link Interrupts 10B M13 Multiplexer and DS2/DS3 framer Interrupts 11B Mailbox Interrupt Information The content of this bit field contains further information about the interrupt, e.g. the affected port. Data Sheet 138 05.2001 PEB 3456 E Functional Description 4.13.2.2 T1/E1 Framer Interrupts The framer interrupts are divided into type 0 and type I interrupts. The distinction is made in bit 14 of the interrupt vector. Interrupt Type 0 15 14 LAST 0 13 12 11 AISS LOSS RAS 10 ES 9 8 7 6 SEC LLBS PRBSS 5 4 00B 0 PORT(4:0) Interrupt Type I 15 14 LAST 1 AISS 11 0 0 10 T400 CRC 9 8 7 PDEN FAS MFAS /AUX 6 5 00B 4 0 PORT(4:0) Alarm Indication Signal Status The `Alarm Indication Signal Status' interrupt vector is generated, whenever the TE3-CHATT detects a change in the alarm indication. The actual state, i.e. active/not active, is shown in FRS.AIS. LOSS Loss of Signal Status The 'Loss of Signal Status' interrupt vector is generated, whenever the TE3-CHATT detects a change in FRS.LOS. RAS Remote Alarm Status The 'Remote Alarm Status' interrupt vector is generated, whenever the TE3-CHATT received remote alarm status changes. The actual state, i.e. active/not active, is shown in FRS.RRA. ES Errored Second The 'Errored Second' interrupt vector is generated for the first errored second event in a time interval of one second. Errored second events are: 1. Loss of frame alignment (this includes indirectly AIS or Loss of Signal) 2. CRC error received (CRC-6 or CRC-4). SEC One Second Tick The 'One Second Tick' interrupt vector is generated, when the internal one second timer has expired. The timer is derived from the incoming receive clock of the corresponding port. Data Sheet 139 05.2001 PEB 3456 E Functional Description LLBS Line Loopback Status The `Line Loopback Status' interrupt vector is generated, whenever the TE3-CHATT detects a change in either the line loopback deactuation signal or the line loopback actuate signal. The actual state of the signals is shown in FRS.LLBDD and FRS.LLBAD. PRBS PRBS Status The 'PRBS Status' interrupt vector is generated, whenever the TE3CHATT synchronization state of the PRBS receiver changes. The actual state of the receiver, i.e. synchronized/not synchronized, is shown in FRS.PRBS. T400 400 Millisecond This interrupt vector is generated when the framer has found the double framing (basic framing) and is searching for the multiframing. This interrupt vector will be generated to indicate that no multiframing could be found within a time window of 400 ms after basic framing has been achieved. In multiframe synchronous state this interrupt will not be generated. CRC Receive CRC Error This interrupt vector is generated, when the CRC-6 checksum of an T1 ESF multiframe or the CRC-4 checksum of an E1 CRC-4 multiframe was incorrect. PDEN/AUX Pulse Density Violation Detected / Auxiliary Pattern Detected This interrupt vector is generated, whenever the TE3-CHATT detects a change in bit FRS.PDEN/AUX. Bit PDEN/AUX is set whenever bit FRS.PDEN.AUX toggles. FAS Frame Alignment Status The 'Frame Alignment Status' interrupt vector is generated, whenever the TE3-CHATT detects a change in frame alignment. The actual state, i.e. aligne/not aligned, is shown in bit FRS.LFA. MFAS Multiframe Alignment Status The 'Multiframe Alignment Status' interrupt vector is generated, whenever the TE3-CHATT detects a change in multiframe alignment. The actual state, i.e. aligned/not aligned, is shown in bit FRS.LMFA. PORT Port Number 0..27 The port number the interrupt vector is associated with. Data Sheet 140 05.2001 PEB 3456 E Functional Description 4.13.2.3 Facility Data Link Interrupts Receive Interrupts * 15 14 LAST 0 RSA 11 0 0 10 9 8 7 RSA SSM RPF RME 6 ISF 5 01B 4 0 PORT(4:0) Receive Sa Data Valid Sa data in RSAW1 - RSAW3 is valid. SSM SSM Data Valid This bit is set, when a new synchronization status message has been received. The synchronization status message is stored in register RSAW4. RPF Receive Pool Full This bit is set, when 32 bytes of a frame have been received and are stored in the receive FIFO. The frame is not yet completely received. RME Receive Message End This bit is set, when one complete message of length less than 32 bytes or the last part of a frame at least 32 bytes long is stored in the receive FIFO. The number of bytes in RFF.RFIFO can be determined reading the port status register PSR. ISF Incorrect Synchronization Format This bit is set, when no eight consecutive `1's are detected within 32 bits in BOM mode. Only valid if BOM receiver has been activated. PORT Port Number 0..27 The port number the interrupt vector is associated with. Data Sheet 141 05.2001 PEB 3456 E Functional Description Transmit Interrupts * 15 14 LAST 1 TXSA 10 0 0 0 9 8 7 TXSA ALLS XDU XPR 6 5 01B 4 0 PORT(4:0) Transmit Sa Data Sent The 'Transmit Sa Data Sent' is generated, when Sa data stored in XSAW1 - XSAW3 has been sent N times, where N is defined prior to transmission in XSAW3.XSAV. ALLS All Sent The 'All Sent' interrupt vector is generated, when the last bit of a frame to be transmitted is completely sent out and XFF.XFIFO is empty. XDU Transmit Data Underrun The 'Transmit Data Underrun' interrupt vector is generated, when the transmit FIFO runs out of data during transmission of a frame. The signalling controller terminates the affected frame with an abort sequence. XPR Transmit Pool Ready The 'Transmit Pool Ready' interrupt vector is generated, when a new data block of up to 32 bytes can be written to transmit FIFO. 'Transmit Pool Ready' is the fastest way to access the transmit FIFO. It has to be used for transmission of long frames, back-to-back frames or frames with shared flag. PORT Port Number 0..27 The port number the interrupt vector is associated with. Data Sheet 142 05.2001 PEB 3456 E Functional Description 4.13.2.4 DS3, DS2 and Test Unit Interrupts Note: The DS3, DS2 and test unit interrupts are seperated by the INFO field (bits 4 through 0). DS3 Interrupts Type 0 * 15 14 13 12 LAST 0 AIC 11 10 9 8 7 6 XBIT IDLES AISS REDS LOSS FAS 5 4 0 00111H 10B DS3 Interrupts Type 1 * 15 14 13 LAST 1 0 CLKS 12 11 10 9 8 7 CLKS RSDL TSDL LPCS SEC Nr 6 5 4 10B 0 00111H DS3 Clock Status The `DS3 Clock Status' interrupt vector is generated whenever the TE3CHATT detects a change in the transmit clock or the receive clock, i.e. clock is activated/deactivated. The actual status of the clock is shown in D3RSTAT.LRXC and D3RSTAT.LTXC. RSDL Receive Spare Data Link Transfer Buffer Full The `Receive Spare Data Link Transfer Buffer Full' interrupt vector is generated when the receive spare data link buffer needs to be emptied. TSDL Transmit Spare Data Link Transfer Buffer Empty The `Transmit Spare Data Link Transfer Buffer Empty' interrupt vector is generated when the transmit spare data link buffer needs to be filled. LPCS Loopback Code Status The `Loopback Code Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the received loopback codes. Actual loopback codes can be found in register D3RLPCS. SEC 1 Second Interrupt The `1 Second Interrupt' is generated every second. Nr Received new Nr-Bit The `Received new Nr-Bit' interrupt vector is generated whenever the TE3-CHATT detects a change in the NA overhead bits and when its state is persistent for at least three multiframes. Data Sheet 143 05.2001 PEB 3456 E Functional Description AIC Received new AIC-Bit The `Received new AIC-Bit' interrupt vector is generated whenever the TE3-CHATT detects a change in the AIC overhead bits and when its state is persistent for at least three multiframes. XBIT Received X-Bit The `Received new X-Bit' interrupt vector is generated whenever the TE3-CHATT detects a change in the X overhead bits and when its state is persistent for at least three multiframes. IDLES DS3 Idle Signal Status The `DS3 Idle Signal Status' interrupt vector is generated whenever the TE3-CHATT detects a change of the idle signal. D3RSTAT.IDLES contains the actual state of the idle state, i.e. active/not active. AISS DS3 Alarm Indication Signal Status The `DS3 Alarm Indication Signal Status' is generated whenever the TE3-CHATT detects a change in the AIS alarm state. D3RSTAT.AISS shows the actual AIS alarm state, i.e. active/not active. REDS DS3 Red Alarm Status The `DS3 Red Alarm' interrupt vector is generated whenever the TE3CHATT detects a change in the red alarm state. D3RSTAT.RED shows the actual red alarm state, i.e. active/not active. LOSS DS3 Input Signal Status The `DS3 Input Signal Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the DS3 input signal state, i.e. loss/no loss. D3RSTAT.LOSS shows the actual state of the DS3 input signal. FAS DS3 Frame Alignment Status The `DS3 Frame Alignment Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the DS3 frame alignment. D3RSTAT.FAS shows the actual state. Data Sheet 144 05.2001 PEB 3456 E Functional Description DS2 Framer Interrupts Note: The effected DS2 tributary is encoded in the INFO field (bits 4..0). * 15 14 LAST 0 LPCS 12 0 11 10 9 8 7 LPCS AISS REDS RES RAS FAS 6 5 10B 4 0 00000H - 00110H Loop Code Status The `Loopback Code Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the received loopback codes. Actual loopback codes can be found in register D2RLPCD. AISS DS2 Alarm Indication Signal Status The `DS2 Alarm Indication Signal Status' is generated whenever the TE3-CHATT detects a change in the AIS alarm state. D2RSTAT.AIS shows the actual AIS alarm state, i.e. active/not active. REDS DS2 Red Alarm Status The `DS2 Red Alarm Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the red alarm state. D3RSTAT.RED shows the actual red alarm state, i.e. active/not active. RES Received new Reserved ITU-T G.747 Overhead Bit The `Received new Reserved ITU-T G.747 Overhead Bit' interrupt vector is generated whenever the TE3-CHATT detects a change in the reserved ITU-T G.747 overhead bit and when its state is persistent for at least three multiframes. D2R[].[] shows the actual state of the overhead bit. RAS Remote Alarm Status The 'Remote Alarm Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the remote alarm indication and when its state is persistent for at least three multiframes. D2RSTAT.RA shows the actual state of the remote alarm indication. FAS DS2 Frame Alignment Status The `DS2 Frame Alignment Status' interrupt vector is generated whenever the TE3-CHATT detects a change in the DS2 frame alignment. D2RSTAT.LFA shows the actual status of frame alignment. Data Sheet 145 05.2001 PEB 3456 E Functional Description Test Unit Interrupts Type 0 * 15 14 LAST 0 0 OOS 0 11 10 9 8 7 EMI LBE A1 A0 OOS 6 5 4 10B 0 01000H Receiver Out Of Synchronization The 'Receiver Out of Synchronization' interrupt vector is generated whenever the test unit detects a change in synchronization. The actual state of the receiver is shown in TURSTAT.OOS. A0 Input all `0's The `Input all `0's' interrupt vector is generated whenever the TE3CHATT detects 32 continuous `0's or when this consition is resolved. The actual state is shown in TURSTAT.A0. A1 Input all `1's The `Input all `1's' interrupt vector is generated whenever the TE3CHATT detects 32 continuous `1's or when this consition is resolved. The actual state is shown in TURSTAT.A1. LBE Latched Bit Error Detected Flag The 'Latched Bit Error Detected Flag' interrupt vector is generated with the first occurance of a bit error. EMI End of Measurement Interval The `End of Measurement Interval' interrupt vector is generated when the end of the programmed measurement interval is reached. 4.13.2.5 Mailbox Interrupts * 15 14 LAST 0 13 7 STATUS(6:0) 6 5 11B 4 0 00000B The 'Mailbox' interrupt vector is generated, in case that the host CPU on PCI side has written data to the mailbox status register MBP2E0. The bit field STATUS contains a copy of MBE2P0.MB(6:0). Data Sheet 146 05.2001 PEB 3456 E Interface Description 5 Interface Description 5.1 PCI Interface A 32-bit and 66 MHz capable PCI bus controller provides the interface between the TE3CHATT and the host system. PCI Interface pins are measured as compliant to the 3.3V signalling environment according to the PCI specification Rev. 2.1. The PCI bus controller operates as initiator or target. Commands are supported as follows: * * * * Master memory read single DWORD/burst of up to 64 DWORDs with zero wait cycles. Master memory write single DWORD/burst of up to 64 DWORDs with zero wait cycles. Slave memory read single DWORD. Slave memory write single DWORD. Fast back-to-back transfers are provided for slave accesses only. All read/write accesses to the TE3-CHATT must be 32-bit wide, that is all bytes must be enabled. Non 32-bit accesses result in system interrupt. Refer also to the PCI specification Rev. 2.1 for detailed information about PCI bus protocol. 5.1.1 PCI Read Transaction The transaction starts with an address phase which occurs during the first cycle when FRAME is activated (clock 1 in Figure 5-1). During this phase the bus master (initiator) outputs a valid address on AD(31:0) and a valid bus command on C/BE (3:0). The first clock of the first data phase is clock 3. During the data phase C/ BE indicate which byte lanes on AD(31: 0) are involved in the current data phase. The first data phase on a read transaction requires a turnaround cycle. In Figure 5-1 the address is valid on clock 2 and then the master stops driving AD. The target drives the AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once enabled, the AD output buffers of the target stay enabled through the end of the transaction. A data phase may consist of a data transfer and wait cycles. A data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted. When either is deasserted a wait cycle is inserted. In the example below, data is successfully transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The first data phase completes in the minimum time for a read transaction. The second data phase is extended on clock 5 because TRDY is deasserted. The last data phase is extended because IRDY is deasserted on clock 7. The Master knows at clock 7 that the next data phase is the last. However, the master is not ready to complete the last Data Sheet 147 05.2001 PEB 3456 E Interface Description transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs on clock 8. * 1 2 3 4 5 6 7 8 CLK FRAME Data 3 Wait IRDY TRDY Data Transfer BE's Wait Command Data 2 Data Transfer C/BE Data 1 Wait Address Data Transfer AD DEVSEL Address phase Data phase Data phase Data phase Bus transaction Figure 5-1 5.1.2 PCI Read Transaction PCI Write Transaction The transaction starts when FRAME is activated (clock 1 in Figure 5-2). A write transaction is similar to a read transaction except no turnaround cycle is required following the address phase. In the example, the first and second data phases complete with zero wait cycles. The third data phase has three wait cycles inserted by the target. Both initiator and target insert a wait cycle on clock 5. In the case where the initiator inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are withdrawn. The last data phase is characterized by IRDY being asserted while the FRAME signal is deasserted. This data phase is completed when TRDY goes active (clock 8). Data Sheet 148 05.2001 PEB 3456 E Interface Description * 1 2 3 4 5 6 7 8 CLK FRAME AD Address Data 1 Data 2 C/BE Command BE 1 BE 2 Address phase Data phase Data 3 Wait Data Transfer TRDY Wait Wait IRDY Wait Data Transfer BE 3 DEVSEL Data phase Data phase Bus transaction Figure 5-2 5.2 PCI Write Transaction SPI Interface (ROM Load Unit) Additional pins, which are not covered from the PCI specification, but are closely related, are the SPI pins. Via the SPI pins the vendor ID and the vendor subsystem ID can be loaded into the corresponding PCI configuration registers during start-up of the device. The SPI Interface supports EEPROMs with an eight bit address space. After a system reset, the TE3-CHATT starts reading the first byte out of the connected EEPROM at address 00H. If this byte is equal AAH, the device continues reading out the memory contents. Everytime four bytes are read out of the EEPROM (starting with byte address 01H), the EEPROM interface writes the read information to the PCI configuration space. The first four bytes will be written to the PCI configuration space address 00H, the next four bytes to the PCI configuration space address 04H and so on. So the contents of the EEPROM, starting with EEPROM byte address 01H, will be mapped over the PCI configuration space after a system reset. During this configuration phase, all accesses to the PCI interface will be answered with `retry' by the PCI interface. If the first byte in the EEPROM is not equal AAH, the EEPROM interface stops loading the PCI configuration space immediately, and the PCI interface can be accessed. The PCI configuration space in this case contains the default values. The configuration mechanism through the serial interface can be disabled by pin SPLOAD. If this pin is connected to `0', the configuration mechanism is disabled. The Data Sheet 149 05.2001 PEB 3456 E Interface Description bridge can be accessed through the PCI Interface directly after a system reset. In this case the PCI configuration space contains the default values. 5.2.1 Accesses to a SPI EEPROM The EEPROM contents can also be controlled (read and write) by the software. For this, a special EEPROM control register is implemented as part of the PCI configuration space. To start a read/write transaction to an connected EEPROM, you have to set the command, the byte address (for read-/write data commands), the data to be written and the start indication by writing to the EEPROM control register SPI in the PCI configuration space. If the interface detects SPI.START asserted (= `1'), it interprets the command and starts the read-/write transaction to the connected EEPROM. After the transaction has finished, the EEPROM control module deasserts the start bit. If the command was a read command (Read Status Register, Read Data from Memory Array), the byte that was read out of the EEPROM is available in the data register. For transactions started with the EEPROM Control register, the interface does not check if an EEPROM is connected to the SPI bus, because the EEPROM is full passive. A full functional description of the SPI commands and their usage as well as a description of the EEPROMs status register can be found in the description of the EEPROM that will be selected by a board vendor. Byte Address For read and write transaction to the connected EEPROM, the byte address must be written in this register before the transaction is started. Data For the write status register transaction and the write data to memory array transactions, the data that has to be written to the EEPROM must be written to this register before the transaction is started. After a read status register transaction or a read data from memory array transaction has finished (Bit SPI.START is deasserted), the byte received from the EEPROM is available in this register. Start To start the EEPROM transaction defined via register SPI the bit SPI.START must be set to `1' by a write transaction through the PCI interface. After the transaction is finished, the EEPROM start bit is deasserted by the EEPROM interface controller. This signal has to be polled by system software. 5.2.2 SPI Read Sequence The TE3-CHATT selects an external EEPROM by pulling SPCS low. The eight bit read sequence is transmitted followed by the eight bit address. After the read instruction and Data Sheet 150 05.2001 PEB 3456 E Interface Description address is sent, the data stored in the memory at the selected address is shifted in on the SPSI pin. The read operation is terminated by setting SPCS high (see Figure 5-3). * SPCS 0 1 2 0 0 0 3 4 5 6 7 8 9 1 1 7 6 14 15 16 17 18 19 20 21 22 23 SPCLK instruction SPSO 0 0 0 8 bit address 0 data in SPSI Figure 5-3 5.2.3 7 6 5 4 3 2 1 0 SPI Read Sequence SPI Write Sequence Prior to any attempt to write data to an external EEPROM, the write enable latch must be set by issuing the WREN instruction. This is done by setting SPCS low and then clocking out the WREN instruction. After all eight bits of the instruction are transmitted, the SPCS will be brought high to set the write enable latch. Once the write enable latch is set, the user may proceed by issuing a write instruction, followed by the eight bit address and then the data to be written. In order that data will actually be written to the EEPROM, the SPCS is set high after the least significant bit (D0) of the data byte has been clocked in. Refer to Figure 5-4 for detailed illustrations on the byte write sequence. While the write is in progress, the register bit SPI.START may be read to check the status of the transaction. When a write cycle is completed, the register bit SPI.START is reset. * SPCS 0 1 2 0 0 0 3 4 5 6 7 8 9 1 0 7 6 14 15 16 17 18 19 20 21 22 23 SPCLK instruction SPSO 0 0 0 8 bit address data out 0 7 6 5 4 3 2 1 0 SPSI Figure 5-4 Data Sheet SPI Write Sequence 151 05.2001 PEB 3456 E Interface Description 5.3 Local Microprocessor Interface The Local Microprocessor Interface is a demultiplexed switchable Intel or Motorola style interface with master and slave functionality. In slave mode it is used to operate the M13 multiplexer, DS3/DS2 framer, T1/E1 framer and the facility data link of the TE3-CHATT. The TE3-CHATT provides a local clock output LCLK, which is a feed through of the PCI system clock as clock reference for the local microprocessor interface. The local bus master capability allows to access peripherals located on the local bus via the PCI interface. Bit FCONF.LME enables the bus master capability. The base address register two is disabled per default and can be enabled during startup of the internal PCI interface. This is done by setting bit MEM.BAR2 in the PCI configuration space. The TE3-CHATT supports a maximum of three 8 kByte pages of memory on the local address bus. The correspondence between the accessed PCI memory space (mapped via base address register 2) and the asserted chip selects is shown in table 5-1. The mapping of the PCI byte enables to the local bus address is dependent on the selected bus mode and is explained in detail in the corresponding section. Table 5-1 Page Correspondence between PCI memory space and chip select AD(14:0) LCS2 LCS1 0 0000H - 1FFFH 1 0 1 2000H - 3FFFH 0 1 2 4000H - 5FFFH 0 0 3 6000H - 7FFFH Data Sheet Not valid 152 05.2001 PEB 3456 E Interface Description 5.3.1 Intel Mode 5.3.1.1 Slave Mode In Intel slave mode the bus interface supports 16-bit transactions in demultiplexed bus operation. It uses the local bus port pins LA(12:1) for the 16 bit address and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by placing an address on the address bus and asserting LCS0 (Figure 5-5). The external processor then activates the respective command signal (LRD, LWR). Data is driven onto the data bus either by the TE3-CHATT (for read cycles) or by the external processor (for write cycles). After a period of time, which is determined by the access time to the internal registers valid data is placed on the bus, which is indicated by asserting the active low signal LRDY. Note: LCS0 need not be deasserted between two subsequent cycles to the same device. Read cycles Input data can be latched and the command signal can be deactivated now. This causes the TE3-CHATT to remove its data from the data bus which is then tri-stated again. LRDY is driven high and will be tri-stated as soon as LCS0 is deasserted. Write cycles The command signal can be deactivated now. If a subsequent bus cycle is required, the external processor can place the respective address on the address bus. 5.3.1.2 Master Mode A read/write access from the PCI bus to the 16 bit demultiplexed local bus is initiated by accessing the PCI memory space base which is controlled by the base address register 2. Each valid read or write access to this base address triggers the local bus master interface which in turn starts arbitration for the local bus by asserting LHOLD (see (1) in Figure 5-6). As soon as the TE3-CHATT gets access to the local bus (LHLDA asserted) it starts the local bus latency timer and begins a read/write transaction as the bus master. The signal LHOLD remains asserted while a transaction is in progress or as long as the local bus latency timer is not expired. A read/write transaction begins when the TE3-CHATT places a valid address on the address bus, sets the LBHE signal which indicates a 8- or 16-bit bus access and asserts the chip select signals LCS1 and/or LCS2. Then the TE3-CHATT activates the respective command signals (LRD, LWR). Data is driven onto the data bus either by the TE3-CHATT (for write cycles) or by the accessed device (for read cycles). A transaction is finished on the local bus when the external device asserts LRDY (ready controlled bus cycles) or when the internal wait state timer expires. Data Sheet 153 05.2001 PEB 3456 E Interface Description * Read Cycle (16 Bit) Write Cycle (8 bit1) Address Address LA(12:0) LBHE1 LCS0 (In) LCS1,2 (Out) LRD LWR LRDY2 Data LD(15:0) Data Note 1: Supported in local bus master mode only. Note 2: Ready controlled bus cycles only. Figure 5-5 Intel Bus Mode * LHOLD remains asserted as long as a transaction is in progress or while the latency timer is not expired 1 LHOLD 2 LHLDA Bus Cycle Read/Write Cycle 3 One or more read/write cycles as bus master Figure 5-6 Intel Bus Arbitration Valid C/BE combinations and the correspondence between local address, LBHE and the mapping of PCI data to the local data bus are shown in table 5-2 and table 5-3. All Data Sheet 154 05.2001 PEB 3456 E Interface Description accesses not shown in the table result in generation of a 'PCI Access Error' interrupt vector. Table 5-2 C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode) C/BE(3:0) LA(1:0) LBHE LD(15:8) LD(7:0) 1110B 00B 1 - AD(7:0) 1101B 01B 1 - AD(15:8) 1011B 10B 1 - AD(23:16) 0111B 11B 1 - AD(31:24) Table 5-3 C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode) C/BE(3:0) LA(1:0) LBHE LD(15:8) LD(7:0) 1110B 00B 1 - AD(7:0) 1101B 01B 0 AD(15:8) - 1011B 10B 1 - AD(23:16) 0111B 11B 0 AD(31:24) - 1100B 00B 0 AD(15:8) AD(7:0) 0011B 10B 0 AD(31:24) AD(23:16) Data Sheet 155 05.2001 PEB 3456 E Interface Description 5.3.2 Motorola Mode 5.3.2.1 Slave Mode The demultiplexed bus modes use the local bus port pins LA(12:1) for the 16- bit address and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by placing an address on the address bus and asserting LCS0 together with the command signal LWRRD (see "Motorola Bus Mode" on Page 157). The data cycle begins when the signal LDS is asserted. Data is driven onto the data bus either by the TE3-CHATT (for read cycles) or by the external processor (for write cycles). After a period of time, which is determined by the access time to the internal registers valid data is placed on the bus, which is indicated by asserting the active low signal LDTACK. Note: LCS0 need not be deasserted between two subsequent cycles to the same device. Read cycles Input data can be latched and the data strobe signal can be deactivated now. This causes the TE3-CHATT to remove its data from the data bus which is then tri-stated again. LDTACK is driven high and will be tri-stated as soon as LCS0 is deasserted. Write cycles The data strobe signal can be deactivated now. If a subsequent bus cycle is required, the external processor can place the respective address on the address bus. 5.3.2.2 Master Mode As in Intel mode a read/write access from the PCI bus to the 16 bit demultiplexed local bus is initiated by accessing the PCI memory space base mapped by the base address register 2. Each valid read or write access to this base address triggers the local bus master interface which in turn starts arbitration for the local bus using the interface signals LBR and LBG and LBGACK. As soon as the TE3-CHATT gets access to the local bus it places a valid address on the address bus, sets the LSIZE0 signal which indicates a 8- or 16-bit bus access and asserts the corresponding chip select signal. The signal LWRRD indicates a read or write operation. The data cycle begins when the signal LDS is asserted. Data is driven onto the data bus either by the TE3-CHATT or by the external component. A transaction is finished on the local bus when the external device asserts the active low signal LDTACK or when the internal wait state timer expires. Data Sheet 156 05.2001 PEB 3456 E Interface Description * LA(12:0) Read Cycle (8 bit1) Write Cycle (16 bit) Address Address LSIZE01 LCS0 (In) LCS1,2 (Out) LDS LRDWR LDTACK2 Data LD(15:0) Data Note 1: Supported in local bus master mode only. Note 2: LDTACK controlled bus cycles only. Figure 5-7 Motorola Bus Mode * LBGACK remains asserted as long as a transaction is in progress or while the latency timer is not expired. 1 LBR 2 LBG LBGACK Bus Cycle RD/WR Cycle 3 One or more read/write cycles as bus master Figure 5-8 Data Sheet Motorola Bus Arbitration 157 05.2001 PEB 3456 E Interface Description The address and byte enable signals on the PCI bus are mapped to the local bus according to table 5-4 and table 5-5. It can be seen that the TE3-CHATT supports different valid C/BE combinations which result in either a 8- or 16-bit access to the local bus interface. All accesses not shown in the table result in generation of a 'PCI Access Error' interrupt vector. Byte swapping for 16 bit data transfers can be disabled. C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode) Table 5-4 C/BE(3:0) LA(1:0) LSIZE0 1110B 00B 1 AD(7:0) - 1101B 01B 1 AD(15:8) - 1011B 10B 1 AD(23:16) - 0111B 11B 1 AD(31:24) - Table 5-5 LD(15:8) LD(7:0) C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode) C/BE(3:0) LA(1:0) LSIZE0 LD(15:8) 1110B 00B 1 AD(7:0) 1101B 01B 1 - AD(15:8) 1011B 10B 1 AD(23:16) - 0111B 11B 1 - AD(31:24) 1100B 00B 0 AD(7:0) AD(15:8) 0011B 10B 0 AD(23:16) AD(31:24) 5.4 LD(7:0) Serial Line Interface The DS3 interface of the TE3-CHATT consists of one receive port and one transmit port. The receive port provides a clock input (RC44) and one (RD44) or two data inputs (RD44P, RD44N) for unipolar or dual-rail input signals. Receive data can be sampled on the rising or falling edge of the receive clock. In transmit direction the port interface consists of two clock signals, the transmit clock input TC44 and a clock output signal TC44O. The data signals consists of one (TD44) or two data outputs (TD44P, TD44N) for unipolar or dual-rail output signals. The transmit port can be clocked by the receive clock RC44 or by the transmit clock TC44. The selected clock is provided as an output on TC44O. Transmit data is updated on the rising or falling edge of TC44O. The TE3-CHATT provides two additional serial interfaces, one for DS3 overhead bit access and one for DS3 stuff bit access (M13 asynchronous format only). The overhead access is provided via an overhead clock signal (ROVHCK, TOVHCK), an overhead data signal (ROVHD, TOVHD) and an synchronization signal (ROVHSYN, Data Sheet 158 05.2001 PEB 3456 E Interface Description TOVHSYN) which marks the X overhead bit of the first subframe of a DS3 signal. In transmit direction the overhead enable signal (TOVHEN) marks those bits which shall be inserted in the overhead bits of the DS3 signal. All overhead signals are updated or sampled on the rising edge of the corresponding overhead clock, i.e. ROVHCK or TOVHCK. See Figure 5-9 and Figure 5-10 for details. * 7th subframe 1st subframe RC44 RD44 F1 84 data bits X 84 data bits F1 84 data bits C11 ROVHCK ROVHD F1 X F1 ROVHSYN Figure 5-9 Data Sheet Receive Overhead Access 159 05.2001 PEB 3456 E Interface Description * 1. Transmit Overhead Bit Access (TOVHSYN in output mode) 7th subframe 1st subframe TC44O TD44 C73 84 data bits F1 84 data bits X 84 data bits F1 TOVHCK TOVHD F1 X F1 TOVHSYN (Output mode) TOVHEN 2. Transmit Overhead Bit Access (TOVHSYN in input mode) 7th subframe 1st subframe TC44O TD44 C73 84 data bits F1 84 data bits X 84 data bits F1 TOVHSYN (Input mode) TOVHCK TOVHD F1 X F1 TOVHEN Figure 5-10 Transmit Overhead Access The stuff bit access is provided via a receive and transmit stuff bit clock (RSBCK, TSBCK) and the two stuff bit signals RSBD and TSBD. Stuff bits are updated and sampled on the rising edge of the of stuff bit clock. Data Sheet 160 05.2001 PEB 3456 E Interface Description 5.5 JTAG Interface A test access port (TAP) is implemented in the TE3-CHATT. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 5-11 gives an overview about the TAP controller. * Test Access Port (TAP) TCK CLOCK Pins Clock Generation 1 2 TMS Test Control TDI Data in TDO TAP Controller Control Bus - Finite State Machine - Instruction Register (4 bit) - Test Signal Generator Enable ID Data out SS Data out Data out Boundary Scan (n bit) Reset Identification Scan (32 bit) CLOCK TRST . . . . . . n Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit If no boundary scan operation is planned TRST has to be connected with VSS. TMS and TDI do not need to be connected since pull- up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put the unused inputs to defined levels. In this case, if the JTAG is not used: TMS = TCK = `1' is recommended. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, i. e. TRST is connected to VDD3 or it remains unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant `1' on TMS leads to normal operation of the chip. An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that most functional output and input pins of the TE3-CHATT are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of the TE3-CHATT Data Sheet 161 05.2001 PEB 3456 E Interface Description contains a total of n = 484 scan cells. The desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1'). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip, i. e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1'). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle. SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. The ID code field is set to Version : 2H Part Number : 0077H Manufacturer : 083H (including LSB, which is fixed to '1') Note: Since in test logic reset state the code `0011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. CLAMP allows the state of signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between TDI and TDO. Signals driven from the TE3-CHATT will not change while the CLAMP instruction is selected. HIGHZ places all of the system outputs in an inactive drive state. Data Sheet 162 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept 6 Channel Programming / Reprogramming Concept For channel programming the TE3-CHATT provides a on-chip channel specification data structure. All information necessary to setup a channel has to be provided using this data structure. As soon as all channel information has been written to the channel specification registers the information can be released using simple channel commands, which have to be written to register CSPEC_CMD. The relevant channel information will then be copied to the chip internal channel database. The channel specification registers, which need to be programmed before a command can be executed, are shown in Table 6-1. Before initializing a channel the time slot assignment process for the affected channel must be completed. Vice versa after shutting down a channel the time slots associated with the affected channel should be set to inhibit. Otherwise if a time slot is reprogrammed afterwards, strange behavior can be expected on the serial side. For each channel a simple sequence of channel commands must be ensured. After reset each channel is in its 'off' state. Therefore, the first command to start a channel is 'Transmit Init' or 'Receive Init'. This brings the channel into the operational state. In this state all commands except 'Transmit Init', 'Receive Init' or 'Transmit Idle can be given. To bring a channel back into the idle state a 'Transmit Off' or 'Receive Off' command has to be programmed. For certain channel commands system software has to wait before new commands can be given for the same channel. This is due to internal buffer allocation functions which require some processing time. Notification of system software is done in form of command interrupt vectors, which signal that a command has successful or even unsuccessful completed. Channel Specification Registers and Channel Commands Receive Debug Receive Hold Reset Receive Abort/Branch Receive Off Receive Init Receive Commands Transmit Update FNUM Transmit Debug Transmit Idle Transmit Hold Reset Transmit Abort/Branch Transmit Commands Transmit Init Register Transmit Off Table 6-1 CSPEC_MODE_REC CSPEC_REC_ACCM CSPEC_MODE_XMIT Data Sheet 163 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept Receive Debug Receive Hold Reset Receive Abort/Branch Receive Off Receive Init Receive Commands Transmit Update FNUM Transmit Debug Transmit Idle Transmit Hold Reset Transmit Abort/Branch Transmit Off Transmit Commands Transmit Init Register CSPEC_XMIT_ACCM CSPEC_BUFFER CSPEC_FRDA CSPEC_FTDA CSPEC_IMASK 6.1 Channel Commands The following section describes all receive and transmit channel commands and the programming sequence in details. 6.2 Transmit Channel Commands Transmit Init Before a 'Transmit Init' command is given, the TE3-CHATT will not transmit data for a channel. After the 'Transmit Init' command the channel database of the affected channel is initialized according to the parameters in the channel specification registers. After initialization the transmit buffer prepares the buffer locations for the selected channel and the data management unit starts processing the linked list and fills the prepared buffer locations. In order to prevent a transmit underrun condition, the transmit buffer is filled up to the transmit forward threshold before data is sent to the serial side. The protocol machine formats data according to the given channel parameters and the data is placed in the time slots assigned to the selected channel. When no or not sufficient data is available, the device sends the idle code according the selected protocol mode. If the command was successful, a 'Transmit Command Complete' interrupt vector is generated after the first transmit descriptor is read pointed to by register CSPEC_FTDA. In case that there is insufficient transmit buffer space, the command cannot be Data Sheet 164 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept completed internally and the device responds with a 'Transmit Command Failed' interrupt vector. Furthermore the TE3-CHATT will not start processing the linked list for this particular channel. New commands for the same channel may be given after the user received the 'Transmit Command Complete' interrupt vector. Prior to new initialization of the same channel it must be turned off using the 'Transmit Off' command. Transmit Off After 'Transmit Off' the transmit channel is disabled immediately and the time slots assigned to the selected channel are set to '1'. The transmit buffer releases all buffer locations assigned to the channel. The data management unit updates the last processed descriptor with the complete bit if enabled and generates a 'Transmit Host Initiated' interrupt vector if the THI bit in the last descriptor was set. All channel related informations are cleared from the internal channel database. A 'Transmit Command Complete' interrupt vector is generated when the channel command is finished. After that time processing of the linked list is completely stopped. New commands for the same channel may be given after the user received the 'Transmit Command Complete' interrupt vector. Transmit Abort/Branch The 'Transmit Abort/Branch' command is performed on the serial side and in the data management unit. The data management unit stops immediately processing the current descriptor and branches to a new descriptor pointed to by CSPEC_FTDA. Data which is already stored in the transmit buffer is sent on the serial side. The protocol machine will append an abort sequence if data in transmit buffer was not complete due to 'Transmit Abort/Branch' command. System software is informed about the aborted frame by a 'Transmit Abort' channel interrupt vector. If no data is stored in the transmit buffer this command does not affect the serial side and no 'Transmit Abort' interrupt vector is generated. Data transmission is continued with a new frame when the data management unit branched to the new descriptor list. A 'Transmit Command Complete' interrupt vector is generated after the management unit released the old descriptor list. New commands for the same channel may be given after the user received the 'Transmit Command Complete' interrupt vector. Transmit Hold Reset The 'Transmit Hold Reset' command must be given after system software has set the HOLD bit of a descriptor from '1' to '0'. In case that the TE3-CHATT is in hold condition it reads the descriptor which had its HOLD bit set and tests the HOLD bit of the descriptor. If the HOLD bit is set to '0' the data management unit branches to the next descriptor and continues data transmission. Otherwise the particular channel remains in hold condition. Data Sheet 165 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept The TE3-CHATT will NOT generate a 'Transmit Command Complete' interrupt vector after this command is programmed. Transmit Update FNUM The 'Transmit Update FNUM' command changes the parameter CSPEC_MODE_XMIT.FNUM in the internal channel database, which allows to change dynamically the number of idle flags that are inserted between two frames. The TE3-CHATT will NOT generate a 'Transmit Command Complete' interrupt vector after this command is programmed. Transmit Idle The 'Transmit Idle' command starts the TE3-CHATT to send the value CSPEC_MODE_XMIT.TFLAG in the time slots of the selected channel. This command can only be given if a channel is turned off. The TE3-CHATT will NOT generate a 'Transmit Command Complete' interrupt vector after this command is programmed. Transmit Debug The 'Transmit Debug' command allows to read back the current settings of the internal channel database. After the 'Transmit Debug' command has been programmed system software can read back the current values of the channel specification registers. Register CSPEC_FTDA contains the value of the next transmit descriptor. The TE3-CHATT will NOT generate a 'Transmit Command Complete' interrupt vector after this command is programmed. Note: The setting of the internal channel database is not copied into the channel specification registers and therefore the values read can not be used to program another channel. After system software has used the 'Transmit Debug' command it must reprogram the channel specification registers to setup a new channel. 6.3 Receive Channel Commands Receive Init Before a 'Receive Init' command is given, the TE3-CHATT will not process data for a channel. After the 'Receive Init' command the channel database of the affected channel is initialized according to the parameters programmed in channel specification registers. After initialization data received in those time slots assigned to the selected channel is processed and stored in the internal receive buffer. The data management unit starts storing this data in the linked list which starts at CSPEC_FRDA. The protocol machine deformats and checks data according to the given channel parameters. Data Sheet 166 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept A 'Receive Command Complete' interrupt vector is generated after the channel information is copied into the internal channel database. New commands for the same channel may be given after the TE3-CHATT issued the 'Receive Command Complete' interrupt vector. Prior to new initialization of the same channel it must be turned off using the 'Receive Off' command. Receive Off The 'Receive Off' command disables the receive channel immediately. Further incoming data is discarded until the next 'Receive Init' command is given. Data already stored in the receive buffer is written to system memory. If a frame is destroyed by the 'Receive Off' command a 'Receive Abort' channel interrupt vector is generated. A 'Receive Command Complete' interrupt vector is generated after remaining data in the receive buffer is written to system memory. After that time processing of the linked list is stopped and the channel information is cleared from the internal channel database. New commands for the same channel may be given after the TE3-CHATT issued the 'Receive Command Complete' interrupt vector. Receive Abort/Branch The 'Receive Abort/Branch' command is performed in the data management unit. The data management unit stops immediately processing the current descriptor and branches to a new descriptor pointed to by CSPEC_FRDA. In case that the 'Receive Abort/Branch' command is issued while a packet is written to system memory a 'Receive Abort' interrupt vector is generated and the rest of the frame already stored in receive buffer is discarded. Data reception is continued with a new frame when the data management unit branched to the new descriptor list. A 'Receive Command Complete' interrupt vector is generated after the channel information is copied into the internal channel database. New commands for the same channel may be given after the TE3-CHATT issued the 'Receive Command Complete' interrupt vector. Receive Hold Reset The 'Receive Hold Reset' command must be given after system software has set the HOLD bit of a receive descriptor from '1' to '0'. In case that the TE3-CHATT is in hold condition it reads the descriptor which had its HOLD bit set and tests the HOLD bit of the descriptor. If the HOLD bit is set to '0' the data management unit branches to the next descriptor and continues data reception. Otherwise the particular channel remains in hold condition. The TE3-CHATT will NOT generate a 'Receive Command Complete' interrupt vector after this command is programmed. Data Sheet 167 05.2001 PEB 3456 E Channel Programming / Reprogramming Concept Receive Debug The 'Receive Debug' command allows to read back the current settings of the internal channel database. After the 'Receive Debug' command has been programmed system software can read back the current values of the channel specification registers. Register CSPEC_FRDA contains the value of the next receive descriptor. The TE3-CHATT will NOT generate a 'Receive Command Complete' interrupt vector after this command is programmed. Note: The setting of the internal channel database is not copied into the channel specification registers and therefore the values read can not be used to program another channel. After system software has used the 'Receive Debug' command it must reprogram the channel specification registers to setup a new channel. Data Sheet 168 05.2001 PEB 3456 E Reset and Initialization procedure 7 Reset and Initialization procedure Since the term "initialization" can have different meanings, the following definition applies: Chip Initialization Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc. Mode Initialization Software procedure, that prepares the device to its required operation, i.e. mainly writing on-chip registers to prepare the device for operation in the respective system environment. Operational programming Software procedures that setup, maintain and shut down operational modes, i.e. initialize logical channel or maintain framing operations on selected ports. 7.1 Chip Initialization Hardware reset The hardware reset RST has to be applied to the device. Chip input TRST must be activated prior to or while asserting RST and should be held asserted as long as the boundary scan operation is not required. System clock must start running during reset. During reset: * All I/Os and all outputs are tri-state. * All registers, state machines, flip-flops etc. are set asynchronously to their reset values and all internal modules are set to their initial state. * All interrupts are masked. * The register bit CONF1.STOP is set to `1'. After hardware reset (RST deasserted) system clock CLK is assumed to be running. Serial clocks must be low/high or running. The PCI and the local bus interface pins go into their idle state. All serial line outputs are tri-state. The PCI interface becomes active and depending on input pin SPLOAD starts to read subsystem ID/subsystem vendor ID and Memory commands out of external EEPROM via the SPI interface. The serial clock is derived from the PCI clock. As long as this procedure is active, the PCI interface answers all accesses with retry. After the PCI interface has finished its self initialization it can be configured with PCI configuration cycles. In parallel to PCI self initialization the internal modules start their RAM initialization. As long as the RAM initialization is running the internal modules indicate this condition with Data Sheet 169 05.2001 PEB 3456 E Reset and Initialization procedure their initialization in progress signal. The register bit CONF1.IIP is the result of all signals. As soon as all internal modules have finished their RAM initialization the register bit CONF1.IIP is deasserted. Software must poll the register bit CONF1.IIP until this bit has been deasserted. Read access to registers other than CONF1 is prohibited and may result in unexpected behavior of the design. Write accesses are not allowed. Chip initialization is finished when CONF1.IIP is `0'. Software Reset Alternately the TE3-CHATT provides the capability to issue a software reset via register bit CONF1.SRST. During software reset all interfaces except PCI interface are forced into their idle state. After software reset is set the TE3-CHATT starts its self initialization and IIP will be asserted. Chip initialization is finished when CONF1.IIP is deasserted. Afterwards the software reset bit must be set to `0' to allow further operation. 7.2 Mode Initialization After chip initialization is finished the system software has to setup the device for the required function. The system software has to poll bit CONF1.IIP (FCONF.IIP). As soon as CONF1.IIP is deasserted, the system software has to clear bit CONF1.STOP and has to set the general operating modes in register CONF1. The M13 multiplexer, DS3/DS2 framer mode, T1/E1 framer mode and the DS1/E1 and DS3 port interface has to be programmed. It is assumed, that the DS3 port clock and CTCLK are active. The T1/E1 ports shall be disabled, thus no incoming data is forwarded to the time slot assigner and to the T1/E1 framer. Transmit direction The T1/E1s have to be enabled via register XPI.TEN. After the tributaries are enabled, the F-Bit (T1 mode) respectively time slot zero (E1 mode) are generated by the on-chip T1/E1 framer and the signalling controller. To synchronize the first bit of a frame to an external reference the common transmit frame synchronization pulse CTFS can be used (in external timing mode only). After a tributary has been enabled, payload data is provided from the time slot assigner. Since the time slot assignment is in reset state, that is all time slots are set to inhibit, data bits are sent as `1'. Receive direction The tributaries have to be enabled via register XPI.REN. After they are enabled, the onchip T1/E1 framer tries to achieve frame alignment. As soon as frame alignment has been achieved, incoming payload data is passed to the time slot assigner. Since time slot assignment is in reset state, that is all time slots are set to inhibit, data bits are discarded. Data Sheet 170 05.2001 PEB 3456 E Register Description 8 Register Description The register description of the TE3-CHATT is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 8.1 Register Overview The first part of the register overview describes the PCI configuration space registers. The second part describes the register set which can be accessed from PCI side only. These registers are used to setup the main operation modes and to run the channel engines of the device. The last part describes the register set of the framing engines, the signalling controller, the mailbox and the local interrupt FIFO. These registers may be accessed through the local microprocessor interface or via PCI. Note: Register locations not contained in the following register tables are "reserved". In general all write accesses to reserved registers are discarded and read access to reserved registers result in 00000000H. Nevertheless, to allow future extensions, system software shall access documented registers only, since writes to reserved registers may result in unexpected behavior. The read value of reserved registers shall be handled as don't care. Unused and reserved bits are marked with a gray box. The same rules as given for register accesses apply to reserved bits, except that system software shall write the documented default value in reserved bit locations. 8.1.1 Table 8-1 Register PCI Configuration Register Set (Direct Access) PCI Configuration Register Set Access Address Reset value Comment Page Standard configuration space register DID/VID STA/CMD CC/RID R 00H 2108110AH Device ID/Vendor ID 183 R/W 04H 02A00000H Status/Command 184 R 08H 02800001H Class Code/Revision ID 186 BIST/ HEAD/ LATIM/ CLSIZ R/W 0CH 00000000H BAR1 R/W 10H 00000000H Base Address 1 188 BAR2 R/W 14H 00000000H Base Address 2 189 BARX R Data Sheet Built-in Self Test/ Header Type/ Latency Timer/ Cache Line Size 187 14H-24H 00000000H Base Address Not Used 171 05.2001 PEB 3456 E Register Description Register Access Address Reset value Comment CISP R 28H 00000000H Cardbus CIS Pointer SSID/ SSVID R 2CH 00000000H Subsystem ID/ Subsystem Vendor ID ERBAD R 30H 00000000H Expansion ROM Base Adr. Reserved R 34H 00000000H Reserved Reserved R 38H 00000000H Reserved MAXLAT/ MINGNT/ INTPIN/ INTLIN R/W 3CH 06020100H Maximum Latency/ Minimum Grant/ Interrupt Pin/ Interrupt Line Page 190 191 User defined configuration space register SPI R/W 40H 0000001FH SPI Access Register 192 REQ R/W 44H 00000000H REQ/GNT Config Register 194 MEM R/W 48H 000007E6H PCI Memory Command 195 R 4CH 00000000H PCI Debug Support 197 DEBUG Data Sheet 172 05.2001 PEB 3456 E Register Description 8.1.2 PCI Slave Register Set (Direct Access) This section shows all registers which are located on the first configuration bus. These registers are used to setup the basic operating modes of the device and to setup the port, time slots and channels. System software has access to these registers via the PCI bus. Table 8-2 PCI Slave Register Set Register Access Address Reset value Comment Page General Control CONF1 R/W 040H Configuration Register 1 215 CONF2 R/W 044H 00000000H Configuration Register 2 218 CONF3 R/W 048H 00090000H Configuration Register 3 220 RBAFT W 04CH 00000000H Receive Buffer Access Failed Interrupt Threshold SFDT W 050H 00000000H Small Frame Dropped Interrupt Threshold Register 222 221 Interrupt control PCI bus side IQIA R/W 0E0H 00000000H Interrupt Queue Initialization 239 IQBA R/W 0E4H 00000000H Interrupt Queue Base Addr. 241 IQBL R/W 0E8H 00000000H Interrupt Queue Length 242 IQMASK R/W 0ECH 00000000H Interrupt Queue Mask 243 Global Interrupt Status/ Global Interrupt Acknowledge GISTA/GIACK R/W 0F0H 00000000H GMASK R/W 0F4H FFFFFFFFH Interrupt Mask 244 246 Channel specification registers (* = CSPEC) *_CMD *_MODE_REC W 000H 00000000H Command 198 R/W 004H 00000000H Mode Receive 200 *_REC_ACCM R/W 008H 00000000H Receiver ACCM Map 203 *_MODE_XMIT R/W 014H 00000000H Mode Transmit 204 *_XMIT_ACCM R/W 018H 00000000H Transmit ACCM Map 207 *_BUFFER R/W 020H 00200000H Buffer Configuration 208 *_FRDA Data Sheet R/W 024H 00000000H 173 First Receive Descriptor Addr. 211 05.2001 PEB 3456 E Register Description Register Reset value Access Address Comment First Transmit Descriptor Address *_FTDA R/W 028H 00000000H *_IMASK R/W 02CH 00000000H Interrupt Vector Mask Page 212 213 Port and time slot control registers PMIAR R/W 060H 00000000H Port Mode Indirect Access 223 PMR R/W 064H 0104C000H Port Mode 224 REN R/W 068H 00000000H Receive Enable 226 TEN R/W 06CH 00000000H Transmit Enable 227 TSAIA R/W 070H 00000000H TSAD R/W 074H 02000000H Time slot Assignment Data Time slot Assignment Indirect Access 228 230 PPP character map/ demap registers REC_ACCMX R/W 080H 00000000H Receive Extended ACCM Map 232 XMIT_ACCMX R/W 090H 00000000 Transmit Extended ACCM Map 236 Receive buffer control R 0B0H 02000BFFH Receive Buffer Monitor R/W 0B4H 02000001H Receive Buffer Threshold Report 238 RBAFC R 084H 00000000H Receive Buffer Access Failed Counter 233 SFDIA R/W 088H 00000000H Small Frame Dropped Indirect Access 234 SFDC R 08CH 00000000H Small Frame Dropped Counter 235 RBMON RBTH 237 Maintenance Data Sheet 174 05.2001 PEB 3456 E Register Description 8.1.3 PCI and Local Bus Register Set (Direct Access) This section describes the registers which are located on the configuration bus II (see also These registers can be accessed either from PCI bus via the internal bus bridge or from the local bus side. Note: Since the local bus is 16-bit wide and the PCI bus is 32-bit wide, the upper 16 bit of data coming from/to PCI are discarded. Note: Please note that read accesses to local bus registers via PCI bus and therefore the internal bus bridge may result in latencies which exceed the 16 clock rule of PCI specification. Exceeding the 16 clock rule results in target initiated retry on PCI bus. In this case the read cycle needs to be repeated. Table 8-3 PCI and Local Bus Slave Register Set Address Address (Local (PCI) Bus) Register Access FCONF R/W 100H MTIMER R/W 104H Reset value Comment Page 00H 8080H Configuration Register 247 00H 0001H Master Local Bus Timer 249 Interrupt control for local bus side INTCTRL R/W 108H 04H 0001H Interrupt Control 250 INTFIFO R 10CH 06H FFFFH Interrupt FIFO 251 DS3 Clock Configuration and Status Register D3CLKCS R/W 180H 40H 0000H DS3 Clock Configuration and Status 263 TUCLKC R/W 184H 42H 0000H Test Unit Clock Configuration 265 DS3 Transmit Control Registers D3TCFG R/W 188H 44H 0000H Transmit Configuration 266 D3TCOM R/W 18CH 46H 0070H Transmit Command 268 270 D3TLPB R/W 190H 48H 0000H Remote DS2 Loopback D3TLPC R/W 194H 4AH 0000H Transmit Loopback Code Insertion 271 D3TAIS R/W 198H 4CH 0000H Transmit AIS Insertion 272 D3TFINS R/W 19CH 4EH 0000H Transmit Fault Insertion Control 273 Data Sheet 175 05.2001 PEB 3456 E Register Description Address Address (Local (PCI) Bus) Reset value Register Access D3TTUC R/W 1A0H 50H 0000H Transmit Test Unit Control 274 D3TSDL R/W 1A4H 52H 01FFH Transmit Spare Data Link 275 Comment Page DS3 Receive Control/Status Registers D3RCFG R/W 1C0H 60H 0000H Receive Configuration 276 D3RCOM R/W 1C4H 62H 0000H Receive Command 279 281 D3RIMSK R/W 1C8H 64H 1FFFH Receive Interrupt Mask D3RESIM R/W 1CCH 66H 0000H Receive Error Simulation 282 D3RTUC R/W 1D0H 68H 0000H Receive Test Unit Control 283 D3RSTAT R 1D4H 6AH 0841H Receive Status 284 D3RLPCS R 1D8H 6CH 0000H Receive Loopback Code Status 287 D3RSDL R 1DCH 6EH 01FFH Receive Spare Data Link 288 D3RCVE R/W 1E0H 70H 0000H Receive B3ZS Code Violation Error Counter 289 D3RFEC R/W 1E4H 72H 0000H Receive Framing Bit Error Counter 289 D3RPEC R/W 1E8H 74H 0000H Receive Parity Bit Error Counter 290 D3RCPEC R/W 1ECH 76H 0000H Receive CP-Bit Error Counter 290 D3RFEBEC R/W 1F0H 78H 0000H Receive FEBE Error Counter 291 D3REXZ R/W 1F4H 7AH 0000H Receive Exzessive Zero Counter 291 D3RAP R/W 1F8H 7CH 0000H Alarm Timer Parameter 292 Data Sheet 176 05.2001 PEB 3456 E Register Description Register Access Address Address (Local (PCI) Bus) Reset value Comment Page DS2 Transmit Control Registers D2TSEL R/W 200H 80H 0000H DS2 Transmit Group Select 293 D2TCFG R/W 204H 82H 0000H Transmit Configuration 294 D2TCOM R/W 208H 84H 0000H Transmit Command 295 D2TLPC R/W 20CH 86H 0000H Transmit Loopback Code Insertion 296 DS2 Receive Control Registers D2RSEL R/W 220H 90H 0000H DS2 Receive Group Select 297 D2RCFG R/W 224H 92H 0000H Receive Configuration 298 D2RCOM R/W 228H 94H 0000H Receive Command 299 301 D2RIMSK R/W 22CH 96H 003FH Receive Interrupt Mask D2RSTAT R 230H 98H 0001H Receive Status 302 304 D2RLPCS RD 234H 9AH 0000H Receive Loopback Code Status D2RFEC R/W 238H 9CH 0000H Receive Framing Bit Error Counter 305 D2RPEC R/W 23CH 9EH 0000H Receive Parity Bit Error Counter 305 D2RAP R/W 240H A0H 0000H Alarm Timer Parameter 306 Test Unit Transmit Registers TUTCFG R/W 280H C0H 0000H Transmit Configuration 308 TUTCOM W 284H C2H 0000H Transmit Command 309 TUTEIR R/W 288H C4H 0000H Transmit Error Insertion Rate 311 TUTFP0 R/W 28CH C6H 0000H TUTFP1 R/W 290H C8H 0000H Transmit Fixed Pattern 312 D0H 0000H Receive Configuration 313 Test Unit Receive Registers TURCFG Data Sheet R/W 2A0H 177 05.2001 PEB 3456 E Register Description Register Access TURCOM W Address Address (Local (PCI) Bus) 2A4H D2H Reset value Comment Page 0000H Receive Command 315 317 TURERMI R/W 2A8H D4H 0000H Receive Error Rate Measurement Interval TURIMSK R/W 2ACH D6H 001FH Receive Interrupt Mask 318 TURSTAT R 2B0H D8H 0021H Receive Status 319 TURBC0 R 2B4H DAH 0000H TURBC1 R 2B8H DCH 0000H Receive Bit Counter 321 TUREC0 R 2BCH DEH 0000H TUREC1 R 2C0H E0H 0000H Receive Error Counter 323 TURFP0 R 2C4H E2H 0000H TURFP1 R 2C8H E4H 0000H Receive Fixed Pattern 325 T1/E1 Framer transmit registers TREGSEL R/W 110H 08H 0000H Transmit T1/E1 Framer Port & Register Select 252 TDATA R/W 114H 0AH 0000H Transmit T1/E1 Framer Data 253 T1/E1 Framer receive registers RREGSEL R/W 118H 0CH 0000H Receive T1/E1 Framer Port & Register Select 254 RDATA R/W 11CH 0EH 0000H Receive T1/E1 Framer Data 255 Facility data link registers FREGSEL R/W 120H 10H 0000H Facility Data Link Port & Register Select 256 FDATA R/W 124H 12H 0000H Facility Data Link Data 258 140H 20H 0000H Mailbox Local Bus to PCI Command 259 Mailbox registers MBE2P0 Data Sheet R/W 178 05.2001 PEB 3456 E Register Description Register MBE2P1 MBE2P2 MBE2P3 MBE2P4 MBE2P5 MBE2P6 MBE2P7 MBP2E0 MBP2E1 MBP2E2 MBP2E3 MBP2E4 MBP2E5 MBP2E6 MBP2E7 Data Sheet Access Address Address (Local (PCI) Bus) Reset value Comment Page R/W 144H 148H 14CH 150H 154H 158H 15CH 22H 24H 26H 28H 2AH 2CH 2EH 0000H Mailbox Local Bus to PCI Data Registers 1 through 7 260 R/W 160H 30H 0000H Mailbox PCI to Local Bus Command 261 R/W 164H 168H 16CH 170H 174H 178H 17CH 32H 34H 36H 38H 3AH 3CH 3EH 0000H Mailbox PCI to Local Bus Data Registers 1 through 7 262 179 05.2001 PEB 3456 E Register Description 8.1.4 Transmit T1/E1 Framer Registers (Indirect Access) Note: The transmit framer registers will be accessed via registers TREGSEL and TDATA as part of the Local Bus direct access register set. Please refer to page 252 for description of TREGSEL and to page 253 for description of TDATA. Table 8-4 Register Transmit T1/E1 Framer Registers Access Address Reset value Comment Page Control registers TCMDR R/W 00H 0000H Command 326 TFMR R/W 01H 0000H Mode 328 TLCR0 R/W 02H 0000H Loop Code Register 0 330 TLCR1 R/W 03H 0000H Loop Code Register 0 331 TPRBSC R/W 04H 001FH PRBS Control 332 TFPR0 R/W 05H 0000H TFPR1 R/W 06H 0000H Fixed Pattern Register 333 TPTSL0 R/W 07H FFFFH TPTSL1 R/W 08H FFFFH PRBS Time slot Register 334 XSP R/W 09H 0000H Spare bit Register 335 Data Sheet 180 05.2001 PEB 3456 E Register Description 8.1.5 Receive T1/E1 Framer Registers (Indirect Access) Note: The receive framer registers will be accessed via the registers RREGSEL and RDATA. Please refer to page 254 for description of RREGSEL and to page 255 for description of RDATA. Table 8-5 Register Receive T1/E1 Framer Registers Access Address Reset value Comment Page Control Registers RCMDR R/W 00H 0000H Command 336 RFMR R/W 01H 0000H Mode Register 339 RLCR0 R/W 02H 0000H Loop Code Register 0 344 RLCR1 R/W 03H 0000H Loop Code Register 1 345 RPRBSC R/W 04H 001FH PRBS Control 346 PFPR0 R/W 05H 0000H RFPR1 R/W 06H 0000H Fixed Pattern Register 347 RPTSL0 R/W 07H FFFFH RPTSL1 R/W 08H FFFFH PRBS Time slot Register 348 IMR R/W 09H 0000H Interrupt Mask 349 RFMR1 R/W 0AH 0000H Mode Register 1 350 PCD R/W 0BH 0015H Pulse Count Detection 351 PCR R/W 0CH 0015H Pulse Count Recovery 352 R 40H 0000H Status 353 Status registers FRS FEC R 41H 0000H Framing Error Counter 356 CEC R 42H 0000H CRC Error Counter 357 EBC R 43H 0000H Errored Block Counter 358 BEC R 44H 0000H Bit Error Counter 359 Data Sheet 181 05.2001 PEB 3456 E Register Description 8.1.6 Facility Data Link Registers (Indirect Access) Note: The FDL registers will be accessed via registers FREGSEL and FDATA. Table 8-6 Register Facility Data Link Registers Access Address Reset Comment value Page RCR1 R/W 00H 0000H Receive Configuration Register 1 360 RCR2 R/W 01H 0000H Receive Configuration Register 2 363 R 02H 0000H Receive FIFO 365 366 RFF XCR1 R/W 03H 0000H Transmit Configuration Register 1 XCR2 R/W 04H 0000H Transmit Configuration Register 2 368 W 05H 0000H Transmit FIFO 369 XFF PSR R 06H 0000H Port Status 370 HND W 07H 0000H Handshake 372 MSK R/W 08H 0000H Interrupt Mask 375 RAL R/W 09H 0000H Receive Address Low 376 RAH R/W 0AH 0000H Receive Address High 377 RSAW1 R 0BH 0000H Receive Sa Word 1 378 RSAW2 R 0CH 0000H Receive Sa Word 2 379 RSAW3 R 0DH 0000H Receive Sa Word 3 380 RSAW4 R 0EH 0000H Receive Sa Word 4 381 CRCS1 R 0FH 0000H CRC Status Counter 1 382 CRCS2 R 10H 0000H CRC Status Counter 2 383 XSAW1 R/W 11H 0000H Transmit Sa Word 1 384 XSAW2 R/W 12H 0000H Transmit Sa Word 2 385 XSAW3 R/W 13H 0000H Transmit Sa Word 3 386 VSSM R/W 14H 0000H Valid SSM Pattern 387 VCRC R/W 15H 0000H Valid CRC Count Pattern 388 Data Sheet 182 05.2001 PEB 3456 E Register Description 8.2 Detailed Register Description 8.2.1 PCI Configuration Register DID/VID Device ID/Vendor ID Access : read Address : 00H Reset Value : 2108110AH 31 16 DID(15:0) 15 0 VID(15:0) DID Device ID The device ID identifies the particular device. It is hardwired to value 2108H. VID Vendor ID The vendor ID identifies the manufacturer of the device. It is hardwired to value 110AH. Data Sheet 183 05.2001 PEB 3456 E Register Description STAT/CMD Status/Command Register Access : read/write Address : 04H Reset Value : 02A00000H 31 30 29 28 DPE SSE RMA RTA 27 26 0 25 01B 24 23 22 21 DPED 1 0 1 15 0 8 0 DPE 0 0 0 0 0 16 0 0 6 SE 0 PER 0 0 0 0 0 0 2 1 0 BM MS 0 Detected Parity Error This bit will be asserted whenever the TE3-CHATT detects a parity error. SSE 0 No parity error detected. 1 Parity error detected. This bit will be cleared by writing a `1' to this bit position. Signaled System Error This bit will be asserted whenever the TE3-CHATT asserted SERR. For system error conditions see bit SE. RMA 0 No system error signaled. 1 System error has been signaled. This bit will be cleared by writing a `1' to this bit position. Received Master Abort This bit will set whenever a transaction in which the TE3-CHATT acted as bus master was terminated with master abort. Data Sheet 0 No master abort detected. 1 Transaction terminated with master abort. This bit will be cleared by writing a `1' to this bit. 184 05.2001 PEB 3456 E Register Description RTA Received Target Abort This bit will be set whenever a transaction in which the TE3-CHATT acted as bus master was terminated with target abort. DPED 0 No target abort detected. 1 Transaction terminated with target abort. This bit will be cleared by writing a `1' to this bit. Data Parity Error Detected 0 No data parity error detected. 1 The following three conditions are met: *The bus agent asserted PERR itself or observed PERR asserted. *The bus agent acted as bus master for the operation in which the error occurred. *The Parity Error Response Bit is set SE SERR Enable This bit enables assertion of SERR in case of severe system errors. 0 Assertion of SERR disabled. 1 Enables report of *Address parity errors *Master abort *Target abort PER Parity Error Response This bit enables reporting of parity errors via pin PERR. BM 0 Assertion of PERR disabled. 1 Enables the assertion of PERR. See also Data Parity Error Detected. Bus Master This bit controls a device ability to act as a master on PCI bus. MS 0 Disables the device from generating PCI accesses. 1 Allows the device to act as bus master. Memory Space This bit controls the device response to memory space accesses. Data Sheet 0 Response to memory space accesses disabled. 1 Allows a device to respond to memory space accesses. 185 05.2001 PEB 3456 E Register Description CC/RID Class Code/Revision ID Access : read Address : 08H Reset Value : 02800001H 31 24 23 BCL(7:0) 15 16 SCL(7:0) 8 7 ICL(7:0) 0 RID(7:0) The class code, consisting of base class, subsystem class and interface class, is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. BCL Base Class The base class is hardwired to 02H, which identifies this device as a network controller. SCL Sub Class The sub class is hardwired to 80H, which together with the base class identifies this device as 'Other network controller'. ICL Interface Class The interface class is hardwired to 00H. RID Revision ID The revision ID identifies the current version of the device. It is hardwired to 01H. Data Sheet 186 05.2001 PEB 3456 E Register Description BIST/Header Type/Latency Timer/Cache Line Size Access : read/write Address : 0CH Reset Value : 00000000H 31 24 23 00H 15 00H 11 10 LT(7:3) LT 16 8 7 0 00H 000B Latency Timer The value of this register times eight specifies, in units of PCI clocks, the value of the latency timer for this PCI bus master. Data Sheet 187 05.2001 PEB 3456 E Register Description BAR1 Base Address 1 Access : read/write Address : 10H Reset Value : 00000000H 31 16 BAR(31:12) 15 12 BAR(31:12) 2 0 0 0 0 0 0 0 0 0 1 00B 0 0 The first base address of the TE3-CHATT is marked as non-prefetchable and can be relocated anywhere in 32 bit address space of PCI memory. The TE3-CHATT supports memory accesses only. BAR Base Address The base address will be used for determining the address space of the TE3-CHATT and to do the mapping of the address space. Since the device allocates a total of 4 kByte address space BAR(31:12) are implemented as read/writable. Data Sheet 188 05.2001 PEB 3456 E Register Description BAR2 Base Address 2 Access : read/write Address : 14H Reset Value : 00000000H 31 16 BAR(31:15) 15 3 0 0 0 0 0 0 0 0 0 0 0 0 2 1 00B 0 0 The second base address of the TE3-CHATT is marked as non-prefetchable and can be relocated anywhere in 32 bit address space of PCI memory. The TE3-CHATT supports memory accesses only. All accesses to memory regions defined by BAR2 will be mapped to the local bus. BAR Base Address The base address will be used for determining the address space of the memory regions located on the local bus of the TE3-CHATT and to set the mapping of the address space. The TE3-CHATT can access a total of 24 kByte address space on the local bus as a bus master. In those applications where the master functionality of TE3-CHATT is not needed the second base address register BAR2 may be disabled using bit MEM.BAR2 in the PCI user configuration space. Data Sheet 189 05.2001 PEB 3456 E Register Description SID/SVID Subsystem ID/Subsystem vendor ID Access : read Address : 2CH Reset Value : 00000000H 31 16 SID(15:0) 15 0 SVID(15:0) SID Subsystem ID The subsystem ID uniquely identifies the add-in board or subsystem where the system resides. The value of SID may be reconfigured after the reset phase of the system via the SPI interface. SVID Subsystem Vendor ID The subsystem vendor ID identifies the vendor of an add-in board or subsystem. The value may be reconfigured after the reset phase of the system via the SPI interface. Data Sheet 190 05.2001 PEB 3456 E Register Description ML/MG/IP/IL Maximum Latency/Minimum Grant/Interrupt Pin/Interrupt Line Access : read/write Address : 3CH Reset Value : 06020100H 31 24 23 ML(7:0) 15 MG(7:0) 8 7 IP(7:0) ML 16 0 IL(7:0) Maximum Latency This value specifies how often the device needs to access the PCI bus in multiples of 1/4 us. The value is hardwired to 06H. MG Minimum Grant This value specifies how long of a burst period the device needs, assuming a clock rate of 33 MHz in multiples of 1/4 us. The value is hardwired to 02H. IP Interrupt Pin The interrupt pin register tells which interrupt pin the device uses. Refer to section 6.2.4 and to section 2.2.6 of the PCI specification Rev. 2.1. The value is hardwired to 01H. IL Interrupt Line The interrupt line register is used to communicate interrupt line routing information. Data Sheet 191 05.2001 PEB 3456 E Register Description SPI SPI Access Register Access : read/write Address : 40H Reset Value : 0000001FH 31 0 24 0 0 0 0 0 15 0 23 SPIS 8 SCMD(7:0) 7 SBA(7:0) SPIS 16 0 SWD(7:0) SPI Start To start the EEPROM transaction, which is defined in the SPI command, the byte address, and the data field, this bit must be set to `1' by a write transaction through the PCI interface. After the transaction is finished, the start bit is deasserted by the SPI interface controller. This signal must be polled by system software. SCMD SPI Command In this register, the SPI command for the next EEPROM transfer must be written before the transaction is started. The following SPI commands are supported: SBA 01H WRSR Write Status Register 02H WRITE Write Data to Memory Array 03H READ Read Data from Memory Array 04H WRDI Reset Write Enable Latch 05H RDSR Read Status Register 06H WREN Set Write Enable Latch SPI Byte Address For read and write transaction to the connected EEPROM, the byte address must be written in this register before the transaction is started. Data Sheet 192 05.2001 PEB 3456 E Register Description SD SPI Data For the write status register transactions and the write data to memory array transactions, the data, that has to be written to the EEPROM, must be written to this register before the transaction is started. After a read status register transaction or read data from memory array transaction has finished (start bit is deasserted), the byte received from the EEPROM is available in this register. Data Sheet 193 05.2001 PEB 3456 E Register Description LR Long Request Register Access : read/write Address : 44H Reset Value : 00000000H 31 0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 LR Data Sheet 0 0 0 0 0 0 0 0 0 0 0 0 0 LR Long Request 0 The PCI interface deasserts the REQ signal in parallel with the assertion of the FRAME signal. 1 The REQ signal will be deasserted in parallel with the deassertion of FRAME. 194 05.2001 PEB 3456 E Register Description MEM PCI Memory Command Register Access : read/write Address : 48H Reset Value : 000007E6H 31 30 0 0 0 0 15 0 0 0 0 11 0 BAR2 0 0 0 0 8 7 MW(3:0) 0 0 MRL(3:0) 0 0 4 3 0 17 16 BAR2 0 0 MR(3:0) Enable Base Address Register 2 Setting this bit enables Base Address Register 2. Per default base address register two is disabled. If an EEPROM is connected to the SPI interface the value of this bit can be loaded via the EEPROM. Additionally this bit can set using standard PCI configuration write commands. MW 0 Base Address Register 2 is disabled. 1 Base Address Register 2 is enabled. Memory Write Command The value of this register contains the write command to be used during initiator transfers and is set to memory write after reset. The value of this register is configurable during setup of the bridge either by loading the value from EEPROM or by writing from PCI side. MRL Memory Read Command (Long transfers) The value of this register defines command to be used for read transfers which are equal or more than two DWORDs and is set to memory read line after reset. The value of this register is configurable during run time of the bridge either by loading the value from EEPROM or by writing from PCI side. MR Memory Read Command The value of this register defines command to be used for read transfers of single DWORDs.The value of this register is configurable during run Data Sheet 195 05.2001 PEB 3456 E Register Description time of the bridge either by loading the value from EEPROM or by reading or writing from PCI side. Data Sheet 196 05.2001 PEB 3456 E Register Description DEBUG PCI Debug Support Register Access : read Address : 4CH Reset Value : 00000000H 31 16 DSR(31:0) 15 0 DSR(31:0) DSR Debug Support register The value of this register contains the address of the next initiator transfer during normal operation. In case of disconnect, retry, master abort and target abort the register contains the address of the failed transaction. Data Sheet 197 05.2001 PEB 3456 E Register Description 8.2.2 PCI Slave Register CSPEC_CMD Channel Specification Command Register Access : read/write Address : 000H Reset Value : 00000000H 31 24 23 CMDX(7:0) CMDR(7:0) 15 0 16 7 0 0 0 0 0 0 0 0 CHAN(7:0) The channel specification registers are the access registers to the chip internal channel database. In order to program or reprogram a channel the channel information must be setup in the channel specification data registers before a channel command can be given. As soon as the channel command is issued the channel information is copied to the chip internal channel database and the device is reconfigured for the intended operation. Since reconfiguration time is dependent on the given command, certain commands generate acknowledge/fail command interrupt vectors to report status of configuration.During this time (command has been given and command interrupt) no further commands are allowed for the same channel. Please note that any command for one channel does not affect operation of any other channel. For configuration of multiple channels the system software needs to program the channel data registers only once and then can issue channel commands for multiple channels without reprogramming the channel data registers. Note: Debugging of channel information using the commands 'Receive Debug' or 'Transmit Debug' requires new programming of channel data registers for further operation. For detailed description of register concept and command concept refer to chapter "Channel Programming / Reprogramming Concept" on Page 163. Data Sheet 198 05.2001 PEB 3456 E Register Description CMDX Command Transmit For detailed description of transmit commands and programming sequences refer to Chapter 6.2. CMDR 01H Transmit Init 02H Transmit Off 04H Transmit Abort/Branch 08H Transmit Hold Reset 10H Transmit Debug 20H Transmit Idle 40H Transmit Update Command Receive For detailed description of receive commands and programming sequences refer to Chapter 6.3. CHAN 01H Receive Init 02H Receive Off 04H Receive Abort/Branch 08H Receive Hold Reset 10H Receive Debug Channel select 0..255 Selects the channel to be programmed or debugged. Note: Transmit init for a channel must be programmed only after reset or after a transmit off command, i.e. two transmit init commands for the same channel are not allowed. Data Sheet 199 05.2001 PEB 3456 E Register Description CSPEC_MODE_REC Channel Specification Mode Receive Register Access : read/write Address : 004H Reset Value : 00000000H 31 28 0 0 0 DEL 15 14 13 12 0 SFDE TFF DEL INV 27 24 23 16 ACCMX(3:0) 11 10 9 RFLAG(7:0) 8 1 TMP CRCX CRC CRC 32 DIS 0 0 0 0 0 0 0 PMD(1:0) DEL (Delete) Demap This bit enables demapping of the control character DEL (7FH ). This bit is valid in PPP modes only. ACCMX 0 Disable demapping of control character DEL. 1 Enable demapping of control character DEL. Extended ACCM In addition to the Channel Specification Receive ACCM Map the user can select four global user definable characters for character demapping in PPP modes. Setting one or more of the bits ACCM(3) through ACCM(0) enables the corresponding character which can be found in register REC_ACCMX. RFLAG 0 Disable the selected character in REC_ACCMX for character demapping. 1 Enable the corresponding character in register REC_ACCMX for character demapping. Receive Flag Used in transparent mode only. The RFLAG constitutes the flag that is filtered from the received bit stream if enabled via bit TFF. Data Sheet 200 05.2001 PEB 3456 E Register Description SFDE Short/Small Frame Drop Enable This bit enables either the drop of short frames or the drop of small frames. This bit is valid in HLDC and PPP modes only. TFF 0 Short Frame Drop. Frames smaller than four bytes payload data (CRC32) or smaller than two bytes payload data (CRC16) are dropped. This function is not available if bit CRCX is enabled. 1 Small Frame Drop. Frames (Payload and CRC) which are smaller or equal to CONF3.MINFL are dropped. TMA Flag This bit enabled flag extraction in TMA mode and is available if non of the bits belonging to this channel is masked. INV 0 No flag extraction 1 Enable flag extraction. The flag specified in RFLAG will be extracted from the received data stream. Bit Inversion When bit inversion is enabled incoming channel data is inverted before processed by the protocol machine. E.g. incoming octet 81H will be recognized as idle flag in HDLC mode. TMP 0 No Bit Inversion 1 Bit Inversion Transparent Mode Packing This bit enables the transparent mode packing and is valid in TMA mode only. This feature is applicable if at least one bit in any time slot is masked. CRCX 0 Incoming masked bits are substituted with `1'. The non-used (masked) data bits are substituted by `1's. 1 If subchanneling is used in transparent mode (i.e. less than 8 bits of a time slot are used), the non-used (masked) data bits are discarded. CRC Transfer This bit enables the capability to store the CRC checksum of incoming data packets in system memory together with the payload data. Data Sheet 0 The CRC checksum from the incoming data packet will be removed from the packet and not transferred to the shared memory. 1 The CRC checksum together with the payload data is transferred to the shared memory. 201 05.2001 PEB 3456 E Register Description CRC32 CRC32 Select This bit selects the generator polynomial in the receiver. The checksum of incoming data packets will be compared against CRC16 or CRC32. CRC Select is valid in HDLC and PPP modes only. CRCDIS 0 Select CRC16 checksum. 1 Select CRC32 checksum. CRC Check Disable This bit disables CRC Check in HDLC and PPP protocol modes. PMD 0 CRC check is enabled. 1 CRC check is disabled. Protocol Machine Mode These bit fields select the protocol machine mode in receive direction. Data Sheet 00B Select HDLC operation. 01B Select Bit synchronous PPP. 10B Select Byte synchronous PPP. 11B Select Transparent Mode. 202 05.2001 PEB 3456 E Register Description CSPEC_REC_ACCM Channel Specification Receive ACCM Map Register Access : read/write Address : 008H Reset Value : 00000000H 31 1FH 16 1EH 1DH 1CH 1BH 1AH 19H 18H 17H 16H 15H 14H 13H 12H 11H 15 0FH 10H 0 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H Any of the given characters can be selected for character demapping. If a bit is set the corresponding character is expected to be mapped by the control ESC character and is removed if received. These bits are valid in octet synchronous PPP modes only. Note: If this register needs to be reprogrammed, it must be done before accessing the register CSPEC_MODE_REC. Data Sheet 203 05.2001 PEB 3456 E Register Description CSPEC_MODE_XMIT Channel Specification Mode Transmit Register Access : read/write Address : 014H Reset Value : 00000000H 31 24 23 16 FNUM(7:0) 15 IFTF 0 FNUM 13 12 11 FA INV TMP TFLAG(7:0) 9 0 8 7 CRC CRC 32 DIS 4 ACCMX(3:0) 3 DEL 1 0 0 PMD(1:0) Flag number FNUM denotes the number of flags send between two frames. The flag number can be updated during transmission with command 'Transmit Update'. 0 One flag is sent between two frames (shared flag). 1..255 FNUM+1 flags are sent between two frames. TFLAG Transparent flag Only valid if transparent mode is selected and if FA is enabled. TFLAG constitutes the flag that is inserted into the transmit bit stream. IFTF Interframe Time Fill This bit determines the interframe time fill in HDLC and PPP modes. FA 0 Interframe time fill is 7EH. 1 Interframe time fill is FFH. Flag Adjustment Only valid if transparent mode is selected. Data Sheet 0 The value FFH is sent in sent in all TMA mode exception conditions. 1 The value specified in TFLAG is sent in all TMA mode exception conditions (e.g. idle). This bit can be set only when none of the bits belonging to this channels is masked. 204 05.2001 PEB 3456 E Register Description INV Bit Inversion If bit inversion is enabled outgoing channel data is inverted after processed by the protocol machine. E.g. a outgoing idle flag is transmitted as octet 81H in HDLC mode. TMP 0 Disable bit inversion. 1 Enable bit inversion. Transparent Mode Pack This bit enables the transparent mode packing and is valid in TMA mode only. This feature is applicable if at least one bit in any time slot is masked. CRC32 0 If subchanneling is used outgoing masked bits of data octet are discarded and substituted with `1'. 1 If subchanneling is used outgoing masked bits are sent as `1'. The remaining bits of data are sent in the next time slot. CRC 32 Select This bit selects the generator polynomial in the transmitter. The checksum of outgoing data packets will be generated according to CRC16 or CRC32. CRC32 Select is valid in HDLC and PPP modes only. CRCDIS 0 Select CRC16 generation. 1 Select CRC32 generation. CRC Disable This bit enables generation and transmission of a CRC checksum. CRC disable is valid in HDLC and PPP modes only. ACCMX 0 CRC generation and transmission is disabled. 1 CRC generation and transmission is enabled. Enable extended ACCM character The selected bits in bit field ACCMX denote the enabled characters in XMIT_ACCMX. In addition to the Channel Specification Transmit ACCM Map the user can select four global user definable characters for character mapping in PPP modes. Setting one or more of the bits ACCM(3) through ACCM(0) enables the corresponding character which can be found in register XMIT_ACCMX. Data Sheet 0 Disable the selected character in XMIT_ACCMX for character mapping. 1 Enable the corresponding character in register XMIT_ACCMX for character mapping. 205 05.2001 PEB 3456 E Register Description DEL DEL (Delete) Map Flag This bit enables mapping of the control character DEL (7FH ). This bit is valid in PPP modes only. PMD 0 Disable mapping of DEL. 1 Enable mapping of DEL. Protocol Machine Mode This bit field selects the protocol machine mode in transmit direction. Data Sheet 00B Select HDLC operation. 01B Select Bit synchronous PPP. 10B Select Byte synchronous PPP. 11B Select Transparent Mode. 206 05.2001 PEB 3456 E Register Description CSPEC_XMIT_ACCM Channel Specification Transmit ACCM Map Register Access : read/write Address : 018H Reset Value : 00000000H 31 1FH 16 1EH 1DH 1CH 1BH 1AH 19H 18H 17H 16H 15H 14H 13H 12H 11H 15 0FH 10H 0 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H Any of the given characters can be selected for character mapping. If a bit is set the corresponding character will be mapped by the control ESC character. These bits are valid in octet synchronous PPP modes only. Data Sheet 207 05.2001 PEB 3456 E Register Description CSPEC_BUFFER Channel Specification Buffer Configuration Register Access : read/write Address : 020H Reset Value : 00200000H 31 29 28 16 TQUEUE(2:0) ITBS(12:0) 15 12 TBFTC(3:0) TQUEUE 11 8 6 0 TBRTC(3:0) 4 RQUEUE(2:0) 3 0 RBTC(3:0) Transmit Interrupt Vector Queue This bit field determines the interrupt queue where channel interrupts transmit will be stored. ITBS Individual transmit buffer size Note: Please note that the internal architecture is 32 bit wide. Therefore each buffer location corresponds to four data octets. The transmit buffer size configures the number of internal transmit buffer locations for a particular channel. Buffer locations will be allocated on command transmit init and released after command transmit off. Note: The sum of transmit forward threshold and transmit refill threshold must be smaller than the internal buffer size. TBRTC Transmit Buffer Refill Threshold Code Note: Please note that the internal architecture is 32 bit wide. Therefore each buffer location corresponds to four data octets. TBRTC is a coding for the transmit refill threshold. Please refer to Table 8-7 for correspondence between code and threshold. The internal transmit buffer has a programmable number of buffer locations per channel. When the number of free locations reaches the transmit buffer refill threshold the internal transmit buffer requests new data from the data management unit. Data Sheet 208 05.2001 PEB 3456 E Register Description TBFTC Transmit Buffer Forward Threshold Code Note: Please note that the internal architecture is 32 bit wide. Therefore each buffer location corresponds to four data octets. TBFTC is a coding for the transmit buffer forward threshold. Please refer to Table 8-7 for correspondence between code and threshold. The transmit buffer forward threshold code determines the number of buffer locations which must be filled until the protocol machine starts transmission. Nevertheless the transmit buffer forwards data packets to the protocol machine as soon as a whole packet or the end of a packet is stored in the transmit buffer. RQUEUE Receive Interrupt Queue. This bit field determines the interrupt queue number where channel interrupts receive will be stored. RBTC Receive Buffer Threshold Code Note: Please note that the internal architecture is 32 bit wide. Therefore each buffer location corresponds to four data octets. RBTC is a coding for the receive buffer threshold. Please refer to Table 8-7 for correspondence between code and threshold. The receive buffer threshold determines the maximum packet size in DWORDs which will be stored in the internal receive buffer for a specific channel. When the packet size reaches the receive buffer threshold or a packet has been completely received, the packet will be forwarded to system memory. Table 8-7 Threshold Codings Coding Threshold in DWORDs RBTC TBRTC TBFTC TPBL 0000B 1 x x x x 0001B 4 x x x x 0010B 8 x x x x 0011B 12 x x x x 0100B 16 x x x x 0101B 24 x x x x 0110B 32 x x x x 0111B 40 x x x x 1000B 48 x x x x Data Sheet 209 05.2001 PEB 3456 E Register Description Coding Threshold in DWORDs RBTC TBRTC TBFTC TPBL 1001B 64 x x x x 1010B 96 x 1011B 128 x 1100B 192 1101B 256 x 1110B 384 x 1111B 512 x Data Sheet Not Valid 210 x Not Valid 05.2001 PEB 3456 E Register Description CSPEC_FRDA Channel Specification FRDA Register Access : read/write Address : 024H Reset Value : 00000000H 31 16 FRDA(31:2) 15 2 FRDA(31:2) FRDA 1 0 0 0 First Receive Descriptor Address This 30-bit pointer contains the start address of the first receive descriptor. The receive descriptor is read entirely after the first request of the receive buffer and stored in the on-chip channel database. Therefore all information in the descriptor pointed to by FRDA must be valid when the data management unit branches to this descriptor. The user can specify a new First Receive Descriptor Address using receive abort/branch command. In this case the First Receive Descriptor Address (FRDA) is used as a pointer to a new linked list. See details on commands in section "Channel Commands" on Page 164. Data Sheet 211 05.2001 PEB 3456 E Register Description CSPEC_FTDA Channel Specification FTDA Register Access : read/write Address : 028H Reset Value : 00000000H 31 16 FTDA(31:2) 15 0 FTDA(31:2) FTDA 0 0 First Transmit Descriptor Address This 30-bit pointer contains the start address of the first transmit descriptor. The transmit descriptor is read entirely after the first request of the transmit buffer and stored in the on-chip channel database. Therefore all information in the descriptor pointed to by FTDA must be valid when the data management unit branches to this descriptor. The user can specify a new First Transmit Descriptor Address using the 'Transmit Abort/Branch' command. In this case the first transmit descriptor address (FTDA) is used as a pointer to a new linked list. See details on commands in Chapter 6.2. Data Sheet 212 05.2001 PEB 3456 E Register Description CSPEC_IMASK Channel Specification Interrupt Vector Mask Register Access : read/write Address : 02CH Reset Value : 00000000H 31 30 0 TAB 0 HTAB 0 0 0 15 14 13 12 11 10 9 0 28 23 22 0 UR TFE 0 8 7 6 5 RAB RFE HRAB MFL RFOD CRC ILEN RFOP SF 16 IFTC 0 0 0 0 3 2 SFD SD 0 TCC 0 0 RCC For each channel or command related interrupt vector an interrupt vector generation mask is provided. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see Chapter 4.13.1. The following definition applies: 1 The device will not generate the corresponding interrupt vector, i.e. the interrupt vector is masked. 0 An interrupt condition results in generation of the corresponding interrupt vector. Channel Interrupt Vector Transmit TAB Mask 'Transmit Abort' HTAB Mask 'Hold Caused Transmit Abort' UR Mask 'Transmit Underrun' TFE Mask 'Transmit Frame End' Command Interrupt Vector Transmit TTC Data Sheet Mask 'Transmit Command Complete' 213 05.2001 PEB 3456 E Register Description Command Interrupt Vector Receive RAB Mask 'Receive Abort' RFE Mask 'Receive Frame End' HRAB Mask 'Hold Caused Receive Abort' MFL Mask 'Maximum Frame Length Exceeded' RFOD Mask 'Receive Frame Overflow DMU' CRC Mask 'CRC Error' ILEN Mask 'Invalid Length' RFOP Mask 'Receive Frame Overflow' SF Mask 'Short Frame Detected' IFTC Mask 'Interframe Time-fill Flag' and 'Interframe Time-fill Idle' SFD Mask 'Short Frame Dropped' SD Mask 'Silent Discard' RCC Mask 'Receive Command Complete' Data Sheet 214 05.2001 PEB 3456 E Register Description CONF1 Configuration Register 1 Access : read/write Address : 040H Reset Value : 820000F0H 31 IIP 25 0 0 0 0 0 15 23 STOP SRST 8 MFL(12:0) IIP 24 21 0 0 MFLE 7 6 5 20 16 MFL(12:0) 4 3 2 1 0 MBIM PBIM RBIM RFIM SFL RBM LBE 0Dev Initialization in Progress (Read Only) After reset (hardware reset or software reset) the internal RAM's are self initialized by the TE3-CHATT. During this time (approx. 250 s) no other accesses to the device than reading register CONF1 or FCONF are allowed. This bit must be polled until it has been deasserted by the TE3CHATT. STOP 0 Self initialization has finished. 1 Self initialization in progress. Stop After reset the TE3-CHATT can be switched to 'Fast Initialization' mode. During stop mode internal RAM's will not be accesses by internal state machines. This mode is for test purposes only and allows writing or reading the internal RAM's. SRST 0 Device is in normal operation. This bit must be set to zero after chip initialization. See also "Mode Initialization" on Page 170. 1 Device is in `Fast Initialization Mode'. This function is used for test purposes only. Software Reset This bit issues a software reset to the TE3-CHATT. During software reset all interfaces except PCI interface are forced into their idle state. After software reset is set the TE3-CHATT starts its self initialization and Data Sheet 215 05.2001 PEB 3456 E Register Description IIP will be asserted. When IIP is deasserted system software can reset SRST to '0' to start normal operation again. MFLE MFL 0 Normal operation 1 Start software reset. Maximum Frame Length Check Enable 0 Disable maximum frame length check. 1 Enable maximum frame length check. Maximum Frame Length MFL defines the maximum length of incoming data packets. Packets exceeding the specified length are reported in the status field of the receive descriptor and if selected in an additional channel interrupt. MBIM Mailbox Interrupt Vector Mask This bit enables or disables mailbox system interrupt vectors generated by the mailbox. PBIM 0 Enable interrupt vector. 1 Disable interrupt vector. PCI Bridge Interrupt Vector Mask This bit enables or disables the 'PCI Access Error' interrupt vector generated by the PCI bridge. RBIM 0 Enable interrupt vector. 1 Disable interrupt vector. Receive Buffer Interrupt Vector Mask This bit enables or disables system interrupt vectors 'Receive Buffer Queue Early Warning' and 'Receive Buffer Action Queue Early Warning' which are generated by the receive buffer. RBIM is valid only if bit RBM is set. RFIM 0 Enable interrupt vector. 1 Disable interrupt vector. Receive Buffer Failed Interrupt Vector Mask This bit enables or disables the 'Receive Buffer Access Failed' interrupt vector. Data Sheet 0 Enable interrupt vector. 1 Disable interrupt vector. 216 05.2001 PEB 3456 E Register Description SFL Short Frame Length This bit is a global parameter which defines the length of short frames for all channels. RBM 0 Short frame is defined as a frame containing less than 4 bytes (CRC16) or less than 6 bytes (CRC32). 1 Short frame is defined as a frame containing less than 2 bytes (CRC16) or less than 4 bytes (CRC32). Receive Buffer Monitor This bit is provided to switch between two monitoring functions of the receive buffer. Receive buffer monitor functions are available in register RBTH and RBMON. LBE 0 The minimum free pool count is captured in register RBTH. 1 An interrupt is generated, if the free pool counter falls below the value programmed in register RBTH. Little/Big Endian Byte Swap This bit enables the little or big endian mode, which affects the data structures pointed to by data pointer of receive or transmit descriptor in system memory. Registers, interrupt vectors or descriptors are not affected by little/big endian byte swap. Data Sheet 0 Switch data section to little endian mode. 1 Switch data section to big endian mode. 217 05.2001 PEB 3456 E Register Description CONF2 Configuration Register 2 Access : read/write Address : 044H Reset Value : 00000000H 31 30 28 0 SYSQ(2:0) 15 13 RCL 0 SYSQ 27 0 26 23 PORTQ(2:0) 12 0 24 22 21 20 TBE RSPEN 8 SPA(4:0) 7 LPID(4:0) 16 0 LCID(7:0) System Interrupt Queue SYSQ sets up the interrupt queue where system interrupt vectors will be written to. One system interrupt queue can be selected for system interrupts. PORTQ(2:0) Port Interrupt Vector Queue PORTQ sets up the interrupt queue where port interrupt vectors will be written to. One interrupt queue can be selected for port interrupts. TBE Test Breakout Enable This bit enables the test breakout function. The incoming signals of the port selected via LPID are switched to the test ports and the incoming signals on the test port replace the output signals of the selected port. Setting TBE enables the selected port (tri-state no longer active) and has priority over functions selected in register PMR and priority over bit RSPEN. The port may be disabled using register REN and TEN to disable internal processing while test function is active. RSPEN 0 Disable test function. 1 Enable test function. Receive Synchronization Pulse Enable 0 Data Sheet The selected transmit clock of port zero is visible on pin TCLKO. This function is available when port zero is operated in unchannelized mode. 218 05.2001 PEB 3456 E Register Description 1 SPA The internally generated synchronization pulse of input port CONF2.SPA is switched to pin RSPO for test purposes. Synchronization Pulse Access This bit field selects one framer 0..27 whose synchronization pulse can be externally monitored. Only valid if RSPEN is set. RCL Remote Channel Loop The remote channel loop switches incoming data of one channel to the outgoing bit stream of the same channel. The bit rate of the receiver and the transmitter must be the same. The channel to be looped can be selected using bit field LCID. One channel at a time can be looped. LPID 0 Disable remote channel loop. 1 Enable remote channel loop. Port Identifier This bit field selects the port which shall be switched to the test port. See also bit CONF1.TBE. LCID Loop Channel Identifier This bit field selects the channel which shall be looped through the internal loop buffer. Data Sheet 219 05.2001 PEB 3456 E Register Description CONF3 Configuration Register 3 Access : read/write Address : 048H Reset Value : 00090000H 31 0 19 0 15 0 0 0 0 0 0 13 0 TPBL 0 0 0 0 0 16 TPBL(3:0) 8 0 MINFL(5:0) 0 0 0 0 0 0 0 0 Transmit Packet Burst Length This bit field is a coding for the maximum burst length on PCI bus, when data management unit fetches transmit packets. Please refer to Table 87 "Threshold Codings" on Page 209 for correspondence between code and maximum burst length. MINFL Minimum Frame Length Only valid for those channel which have bit CSPEC_MODE_REC.SFDE set. MINFL sets the minimum frame length in bytes (payload bytes and CRC bytes) for frames which will be forwarded to system memory. If enabled the receive buffer will drop frames which are smaller or equal to the programmed value MINFL to avoid wasting of PCI bandwidth in case of error conditions. The small frame check is disabled, if MINFL is set to zero. Note: Since the receive packets will be dropped inside the receive buffer, the receive packet threshold CSPEC_BUFFER.RTC has to be greater than MINFL/4 in order to work properly. Data Sheet 220 05.2001 PEB 3456 E Register Description RBAFT Receive Buffer Access Failed Interrupt Threshold Register Access : read/write Address : 04CH Reset Value : 00000000H 31 16 RBAFT(31:0) 15 0 RBAFT(31:0) RBAFT Receive Buffer Access Failed Interrupt Threshold This register sets the threshold for the 'Receive Buffer Access Failed' interrupt vector. Data Sheet 221 05.2001 PEB 3456 E Register Description SFDT Small Frame Dropped Interrupt Threshold Register Access : read/write Address : 050H Reset Value : 00000000H 31 16 SFDIT(31:0) 15 0 SFDIT(31:0) SFDIT Small Frame Dropped Interrupt Vector Threshold The programmed threshold defines the threshold for the 'Small Frame Dropped' interrupt vector. As soon as the internal number of dropped, small frames reaches the programmed value a channel interrupt vector with bit SFD set will be generated. The actual value of dropped frames can be read using register SFDC. The value is applied to all 256 channels. Data Sheet 222 05.2001 PEB 3456 E Register Description PMIAR Port Mode Indirect Access Register Access : read/write Address : 060H Reset Value : 00000000H 31 0 23 0 0 0 0 0 0 0 AIP 0 0 15 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT(4:0) Note: This register is an indirect access register which must be programmed before accessing the register PMR. AIP Auto Increment Port This bit enables the auto increment function of bit field PORT. Each read/ write access to register PMR increments PORT. This allows to program multiple, consecutive ports without accessing PMIAR again. PORT 0 Disable auto increment function. 1 Enable auto increment function. Port Select This bit field selects the port number, which can be accessed via register PMR. 0..27 Port Number Data Sheet 223 05.2001 PEB 3456 E Register Description PMR Port Mode Register Access : read/write Address : 064H Reset Value : 0104C000H 31 28 PCM(3:0) 24 0 0 0 22 000B 18 0 15 14 13 12 11 10 9 8 7 6 5 RIM TIM 0 TXR 0 0 CTFSD LT RLL RPL LPL 0 0 16 000B 0 0 0 0 0 0 Note: Effected port is selected via register PMIAR. All settings in this register affect the selected port only. PCM Select Port Mode This bit field selects the port mode. 0000B T1 mode (1.544 MHz) 1000B E1 mode (2.048 MHz) 1111B Unchannelized mode RIM Receive Synchronization Error Interrupt Vector Mask This bit disables generation of the port interrupt vector receive. See "Port Interrupts" on Page 128 for description of interrupt vectors. TIM 0 Enable 1 Disable Transmit Synchronization Error Interrupt Vector Mask This bit disables generation of the port interrupt vector transmit. See "Port Interrupts" on Page 128 for description of interrupt vectors. Data Sheet 0 Enable 1 Disable 224 05.2001 PEB 3456 E Register Description TXR Transmit Data Rising This bit defines the edge the common transmit frame synchronization pulse CTFS is sampled on with respect to the common transmit clock CTCLK. CTFSD LT 0 CTFS is sampled on the rising edge of CTCLK. 1 CTFS is sampled on the falling edge of CTCLK. Common transmit frame synchronization disable 0 Bit 0 of transmit data is synchronized to CTFS. 1 Synchronization of data to CTFS is disabled. Looped Timing This bit selects the transmit clock in TE3-CHATT. Per default the transmit clock of the selected tributary is the common transmit clock. If set to `1' the corresponding tributary is switched into looped timed mode. RLL 0 Select normal operation mode. 1 Select looped timing mode. Remote Line Loop This bit enables the remote line loop of the selected port. RPL 0 Disable remote line loop. 1 Enable remote line loop. Remote Payload Loop This bit enables the remote payload loop of the selected port. LPL 0 Disable remote payload loop. 1 Enable remote payload loop. Local Port Loop This bit enables the local port loop on the selected port. When local loops are closed, the corresponding transmit clock and the synchronization pulse is switched to the receive port. Data Sheet 0 Disable local port loop. 1 Enable local port loop. 225 05.2001 PEB 3456 E Register Description REN Receive Enable Register Access : read/write Address : 068H Reset Value : 00000000H 31 0 27 0 0 16 0 REN(27:0) 15 0 REN(27:0) REN Receive Enable Setting a bit in this bit field enables the receive function of the selected port. After reset all ports are disabled and thus all incoming receive data is discarded. While a port is disabled communication between port handler, time slot assigner and synchronization function is disabled. A port should be enabled if it is correctly configured using registers PMIAR and PMR. Data Sheet 0 Disable receive port. 1 Enable receive port. 226 05.2001 PEB 3456 E Register Description TEN Transmit Enable Register Access : read/write Address : 06CH Reset Value : 00000000H 31 0 27 0 0 16 0 TEN(27:0) 15 0 TEN(27:0) TEN Transmit Enable This bit field enables the transmit function of the selected port. After reset all transmit ports are disabled and thus all TD lines are set to tri-state. While a port is reset the communication between port handler, time slot assigner and synchronization function is disabled. After the port mode has been selected using register PMIAR and PMR a transmit port can be enabled. Data Sheet 227 05.2001 PEB 3456 E Register Description TSAIA Time slot Assignment Indirect Access Register Access : read/write Address : 070H Reset Value : 00000000H 31 DIR 23 0 0 0 15 0 0 0 12 0 AIT 0 8 0 0 0 0 0 4 PORT(4:0) DIR 16 0 0 0 TSNUM(4:0) Direction This bit select the direction for which programming is valid. AIT 0 Program time slots in receive direction. 1 Program time slots in transmit direction. Auto Increment Time slot This bit enables the auto increment function of bit field TSNUM. Each read/write access to register TSAD increments TSNUM. This allows to program multiple, consecutive time slots without accessing TSAIA again. PORT 0 Disable auto increment function. 1 Enable auto increment function. Port Select This bit field selects the port number, which can be accessed via register TSAIA. 0..27 Port number Data Sheet 228 05.2001 PEB 3456 E Register Description TSNUM Time Slot Number This bit field selects the time slots, which can be accessed via register TSAIA. Valid time slot numbers are: 0..23 0..31 Data Sheet T1, Unchannelized E1 229 05.2001 PEB 3456 E Register Description TSAD Time slot Assignment Data Register Access : read/write Address : 074H Reset Value : 02000000H 31 0 25 0 0 0 0 0 15 24 INHI TMA BIT 1ST 8 0 0 0 0 0 0 7 CHAN(7:0) 0 0 0 MASK(7:0) Note: The time slot assignment data register assigns a channel and a mask to a specific port/time slot combination. The related port/time slot must be chosen by accessing TSAIA. The time slot assignment has to be done before a specific channel is configured for operation. After operation the port/time slot assignment of a particular channel has to be set to inhibit. INHIBIT Inhibit Time slot This bit disabled processing of the selected port/time slot. TMA1ST 0 The time slot is enabled. 1 The time slot is disabled. In receive direction incoming octets are discarded. In transmit direction the octet of this time slot and port is set to FFH. TMA First This bit marks the first time slot belonging to a TMA superchannel for TMA synchronization. Receiver starts processing data on the marked time slot. In transmit direction data transmission is started on the marked time slot. If TMA channel uses only one time slot this bit must be set. CHAN Channel Number This bit field selects the channel number which will be associated to the port and time slot which is selected in register TSAIA. Data Sheet 230 05.2001 PEB 3456 E Register Description MASK Mask Bits Setting a bit in this bit field selects the corresponding bit in a time slot which is enabled for operation. Data Sheet 0 In receive direction the corresponding bit is discarded. In transmit direction the bit is sent as `1'. 1 In receive direction the corresponding bit is forwarded to the protocol machine (via time slot assigner). In transmit direction data on the serial line is generated by the protocol machine. 231 05.2001 PEB 3456 E Register Description REC_ACCMX Receive Extended ACCM Map Register Access : read/write Address : 080H Reset Value : 00000000H 31 24 23 CHAR3(7:0) 15 16 CHAR2(7:0) 8 7 CHAR1(7:0) 0 CHAR0(7:0) This register is only used by channels operated in octet synchronous PPP mode. A character written to this register is mapped with a control escape sequence, if the corresponding enable flag is set in the corresponding bit CSPEC_MODE_REC.ACCMX(3:0). Data Sheet 232 05.2001 PEB 3456 E Register Description RBAFC Receive Buffer Access Failed Counter Register Access : read Address : 084H Reset Value : 00000000H 31 16 RBAFC(31:0) 15 0 RBAFC(31:0) RBAFC Receive Buffer Access Failed Counter The read value of this register defines the number of packets which have been discarded due to inaccessibility of the internal receive buffer. A read access resets the counter to zero. Data Sheet 233 05.2001 PEB 3456 E Register Description SFDIA Small Frame Dropped Indirect Access Register Access : read/write Address : 088H Reset Value : 00000000H 31 0 0 0 0 0 0 0 0 23 22 AIC CLR 15 0 16 0 0 0 0 7 0 AIC 0 0 0 0 0 0 0 0 0 CHAN(7:0) Auto Increment Channel This bit enables the auto increment function of bit field CHAN. Each read/write access to register SFD increments CHAN by two. This allows to read the status of multiple channels without accessing SFDIA again. CLR 0 Disable auto increment function. 1 Enable auto increment function. Clear This bit enables the counter mode on reads to register SFDC. CHAN 0 Read of register SFDC does not affect the small frame dropped counter. 1 After reading register SFDC the value of the small frame dropped counter will be reset to zero. Channel Number This bit field selects the channel, whose status can be read in register SFDC. 0..255 Channel number Data Sheet 234 05.2001 PEB 3456 E Register Description SFDC Small Frame Dropped Counter Register Access : read Address : 08CH Reset Value : 00000000H 31 16 SFDC++(15:0) 15 0 SFDC(15:0) These both bit fields show the current value of the small frame dropped counter of the channel N and N+1 selected via SFDIA.CHAN. Dependent on bit field SFDIA.CLR the counter will be cleared after they are read. SFDC++ Small Frame Dropped Counter for Channel N+1 The number of dropped, small frames of channel SFDIA.CHAN+1. SFDC Small Frame Dropped Counter The number of dropped, small frames of channel SFDIA.CHAN. Data Sheet 235 05.2001 PEB 3456 E Register Description XMIT_ACCMX Transmit Extended ACCM Map Access : read/write Address : 090H Reset Value : 00000000H 31 24 23 CHAR3(7:0) 15 16 CHAR2(7:0) 8 7 CHAR1(7:0) 0 CHAR0(7:0) This register is only used by a channel in octet synchronous PPP mode. A character written to this register will be mapped with a Control Escape sequence, if the corresponding enable flag is set in the CSPEC_MODE_XMIT register (ACCMX(3:0)). Data Sheet 236 05.2001 PEB 3456 E Register Description RBMON Receive Buffer Monitor Indirect Access Register Access : read Address : 0B0H Reset Value : 02000BFFH 31 0 25 0 0 0 15 0 0 16 0 RBAQC(9:0) 11 0 RBAQC 0 0 0 RBFPC(11:0) Receive Buffer Action Queue Free Count The value of this register determines the actual number of free actions inside the receive buffer. RBFPC Receive Buffer Free Pool Count The value of this register determines the actual number of free buffer locations inside the receive buffer. After reset a total number of 3072 receive buffer locations, which equals 12kB receive buffer, is available. Data Sheet 237 05.2001 PEB 3456 E Register Description RBTH Receive Buffer Threshold Register Access : read/write Address : 0B4H Reset Value : 02000001H 31 0 25 0 0 0 15 0 0 16 0 RBAQTH(9:0) 11 0 RBAQTH 0 0 0 RBTH(11:0) Receive Buffer Action Queue Free Pool Threshold Function of RBAQTH is dependent on bit CONF1.RBM. CONF1.RBM = '0': The minimum value of RBMON.RBAQC, which occurred since the last reset or the last read of this register, is captures in here. CONF1.RBM = '1': A 'Receive Buffer Action Queue Early Warning' interrupt will be generated, if the receive buffer action queue free pool drops below the value programmed in bit field RBAQTH. The value to be programmed must be in the range of 000H to 1FFH. RBTH Receive Buffer Free Pool Threshold Function of RBTH is dependent on CONF1.RBM. CONF1.RBM = '0': The minimum value of RBMON.RBFP, which occurred since the last reset or the last read of this register, is captured in here. CONF1.RBM = '1': A 'Receive Buffer Queue Early Warning' interrupt vector will be generated, if the receive buffer free pool drops below the value programmed in bit field RBTH. Data Sheet 238 05.2001 PEB 3456 E Register Description IQIA Interrupt Queue Indirect Access Register Access : read/write Address : 0E0H Reset Value : 00000000H 31 0 19 0 0 0 0 0 0 0 0 0 0 0 15 0 18 17 DBG SIQM SIQL SIQBA 3 0 DBG 0 0 0 0 0 0 0 0 0 0 16 0 Q(3:0) Debug This bit selects the debug mode of the interrupt controller. When DEBUG is set, the actual values of interrupt queue base address, interrupt queue length and high priority interrupt queue mask of queue Q are copied to register IQBA, IQL and IQMASK. The value can be read with a following access to these registers. Note: Setting DEBUG is only allowed, if neither SIQBA, SIQL and SIQM are set. SIQM 0 No operation 1 Enable debug mode. Set High Priority Interrupt Queue Mask This bit field enables setup of the high priority interrupt queue mask of queue Q. The value to be programmed has to be configured via register IQMASK prior to a write access to this bit. Data Sheet 0 No operation 1 Set high priority mask. 239 05.2001 PEB 3456 E Register Description SIQL Set Interrupt Queue Length This bit field enables setup of the interrupt queue length of queue Q. The value to be programmed has to be configured via register IQL prior to a write access to this bit. SIQBA 0 No operation 1 Set interrupt queue length. Set Interrupt Queue Base address This bit field enables setup of the interrupt queue base address of queue Q. The value to be programmed has to be configured via register IQBA prior to a write access to this bit. Q 0 No operation 1 Update interrupt queue base address with value programmed in register IQBA. Interrupt Queue Number This bit field determines the interrupt queue number for which programming is valid. The first eight (0..7) interrupt queues are used for channel, port and system interrupt vectors, while the last interrupt queue (8) is used for command interrupt vectors. Interrupt queue number seven is per default the high priority interrupt queue. System software may setup the interrupt queue high priority mask, the interrupt queue length and the interrupt queue base address simultaneously by setting SIQL, SIQBA and SIQM. The command interrupt queue has a fixed length of two times 256 DWORDs, that is one DWORD for each interrupt vector. It is possible to setup the interrupt queue high priority mask, the interrupt queue length and the interrupt queue base address concurrently by setting SIQBA, SIQL and SIQM to '1'. Note: Programming of interrupt queue length or interrupt queue high priority mask is not valid for the command interrupt queue (interrupt queue 8). Note: Programming of interrupt queue high priority mask is not valid for the high priority interrupt queue (interrupt queue 7). 0..8 Data Sheet Interrupt Queue 240 05.2001 PEB 3456 E Register Description IQBA Interrupt Queue Base Address Register Access : read/write Address : 0E4H Reset Value : 00000000H 31 16 IQBA(31:2) 15 2 IQBA(31:2) IQBA 1 0 0 0 Interrupt Queue Base Address The interrupt queue base address register assigns a base address to the eight channel interrupt queues and the command interrupt queue. To set a new base address for a specific queue, system software must first program IQBA. Afterwards the value is released by selecting the associated queue via bit field IQIA.Q and setting of bit IQIA.SIQBA. The interrupt queue base address has to be DWORD aligned. Whenever the base address of a particular interrupt queue is modified, the next interrupt vector written to that queue is stored in the first location of the queue. Data Sheet 241 05.2001 PEB 3456 E Register Description IQL Interrupt Queue Length Register Access : read/write Address : 0E8H Reset Value : 00000000H 31 0 16 0 0 0 0 0 0 0 0 15 0 0 0 0 0 7 0 IQL 0 0 0 0 0 0 0 0 0 0 IQL(7:0) Interrupt Queue Length This bit field assigns a interrupt queue length to the eight channel interrupt queues. To set the interrupt queue length of a specific queue, system software must first program IQL. Afterwards the value is released by selecting the associated queue via bit field IQIA.Q and setting of bit IQIA.SIQL. IQL specifies the interrupt queue length L (number of DWORDs) in the shared memory with L=(IQL+1)*16 (maximum of 4092 DWORDs). Note: IQL = 255 equals a queue length of 1 DWORD. Whenever the length of a particular interrupt queue is modified, the next interrupt vector written to that queue is stored in the first location of the queue. Data Sheet 242 05.2001 PEB 3456 E Register Description IQMASK Interrupt Queue High Priority Mask Access : read/write Address : 0ECH Reset Value : 00000000H 31 30 THI TAB 0 HTAB 0 0 0 15 14 13 12 11 10 9 RHI 28 23 22 0 UR TFE 0 8 7 6 5 RAB RFE HRAB MFL RF0D CRC ILEN RFOP SF 16 IFTC 0 0 0 0 3 2 SFD SD 0 0 0 0 0 For a description of the interrupt concept and interrupt vectors see Chapter 4.13.1. In normal operation each channel interrupt vector is written to the interrupt queue associated with a specific channel, that is interrupt queue 0 to 7. The interrupt queue mask provides the functionality to forward selected channel interrupts to the high priority interrupt queue, which is hardwired as queue 7.Therefore a mask can be set for each of the interrupt queues, which specifies the channel interrupt vector to be forwarded to the high priority interrupt queue. To set the IQMASK for interrupt queues 0 to 6, system software must first program IQMASK. Afterwards the mask is released by selecting the affected interrupt queue via bit field IQIA.Q and setting of bit SIQM. Those interrupt vectors which have an interrupt bit set, that is also masked in this high priority mask are forwarded to the high priority interrupt queue instead of the regular interrupt queue associated with a specific channel. If a channel interrupt vector has at least one interrupt bit set, that is also masked in the high priority mask, the interrupt vector will be forwarded to the high priority interrupt queue. In case that a channel interrupt vector has at least one bit set, that is not masked in the high priority mask, the interrupt vector is queued into the regular interrupt queue associated with the corresponding channel. Data Sheet 243 05.2001 PEB 3456 E Register Description GISTA/GIACK Interrupt Status/Interrupt Acknowledge Register Access : read/write Address : 0F0H Reset Value : 00000000H 31 INTOF 0 0 0 0 0 0 15 0 0 0 0 0 0 0 17 16 0 0 0 0 0 0 0 LBI IF 8 7 6 5 4 3 2 1 0 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Depending on the corresponding bits in register GMASK, an interrupt indication in this register will be flagged at pin INTA. If an interrupt bit is masked (set to '1') in register GMASK, system software has to poll this register in order to get status information of the disabled interrupt bit. INTOF Interrupt Overflow This bit indicates that interrupt information has been lost due to overload conditions of the internal interrupt controller. This interrupt indicates a severe system problem. If this bit is set and INTOF is not masked in register GMASK, the interrupt pin INTA will be asserted. INTOF is cleared, when an '1' is written to this bit. LBI 0 No interrupt overflow. 1 Interrupt overflow. The interrupt will be cleared by writing a `1' to the corresponding bit. Local Bus Interrupt The TE3-CHATT supports bridging of interrupts from the local bus to the PCI bus. In this application the pin LINT is used as an input and as soon Data Sheet 244 05.2001 PEB 3456 E Register Description as LINT changes from an inactive to an active state the interrupt pin INTA will be asserted. Note: This bit does not clear by writing a '1'. This bit is set as long as the interrupt pin LINT is asserted. IF 0 LINT not asserted. 1 LINT asserted. Interrupt FIFO This bit indicates that there is an interrupt vector stored in the internal interrupt FIFO. The IF interrupt is available if the interrupt pin LINT is switched to input mode (INTCTRL.ID = '1') and when the interrupt mask GMASK.IF is set to '0'. Note: This bit does not clear by writing a '1'. This bit is set as long as an interrupt vector is stored in the interrupt FIFO. Q8..Q0 0 No Interrupt vector in interrupt FIFO. 1 Interrupt vector stored in internal interrupt FIFO. Interrupt Queue 8..0 On reads each bit flags one or more interrupt vectors that have been written to the corresponding interrupt queue. If one of the bits is set and the same bit is not masked in register GMASK, the interrupt pin INTA will be asserted. A bit is cleared, when an '1' is written to the specific bit. 0 No interrupt vector written. 1 Read: One or more interrupt vectors have been written to interrupt queue. Write: Clear bit Data Sheet 245 05.2001 PEB 3456 E Register Description GMASK Global Interrupt Mask Register Access : read/write Address : 0F4H Reset Value : FFFFFFFFH 31 INTOF 1 1 1 1 1 1 15 1 1 1 1 1 1 1 17 16 1 1 1 1 1 1 1 LINT IF 8 7 6 5 4 3 2 1 0 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Each bit in this register mask the interrupts, which are flagged in register GISTA/GIACK. INTOF Mask Interrupt Overflow This bit masks the interrupt overflow interrupt. LINT Local Bus Interrupt This bit masks bridging of interrupt from the local bus to the PCI bus. IF 0 Bridging of LINT to INTA enabled. 1 Bridging of LINT to INTA disabled. Interrupt FIFO This bit masks the internal mailbox/layer one interrupt FIFO. Q8..Q0 0 IF interrupt is enabled. 1 IF interrupt is disabled. Mask Interrupt Queue 8..0 Each of the bits Q8..Q0 masks an interrupt, which will be asserted, when an interrupt vector has been written to the corresponding interrupt queue 8..0. Masking an interrupt does not suppress generation of the interrupt vector itself. Data Sheet 0 Enable interrupt, when interrupt vector has been written to selected interrupt queue. 1 Mask (Disable) interrupt, when interrupt vector has been written to selected interrupt queue. 246 05.2001 PEB 3456 E Register Description 8.9.2 PCI and Local Bus Slave Register Set FCONF Framer and FDL Configuration Register Access : read/write Address : 100H (PCI), 00H (Local Bus) Reset Value : 8080H 15 14 IIP 0 IIP 7 0 0 0 0 0 0 6 5 MBID WSE BSD 4 3 2 1 0 P28 P18 P08 LAE LME Initialization in Progress (Read Only) After reset (hardware reset or software reset) the internal RAM's are self initialized by the TE3-CHATT. During this time (approx. 250 s) no other accesses to the device than reading register CONF1 or FCONF are allowed. This bit must be polled until it has been deasserted by the TE3CHATT. MBID WSE 0 Self initialization has finished. 1 Self initialization in progress. Mailbox Interrupt Vector Disable 0 Enable generation of mailbox interrupt vectors. As soon as system software on PCI side writes to register MBP2E0 an interrupt vector indicating a mailbox interrupt will be forwarded to the internal interrupt FIFO and can be read by the local CPU. 1 Disable generation of mailbox interrupt vectors. Wait State Enable This bit enables the wait state controlled master mode. Data Sheet 0 LRDY (Intel), LDTACK (Motorola) controlled bus mode. 1 Wait state controlled bus mode. Wait states are defined in register MTIMER.WS. 247 05.2001 PEB 3456 E Register Description BSD Byte Swap Disable This bit disables byte swapping on 16-bit transfers when the local bus is operated in Motorola master mode. P28..P08 0 Enable byte swap. 1 Disable byte swap. Switch Page 2..0 to 8-bit mode The TE3-CHATT maps three pages of 8 kByte each to the local bus in master mode. Each page accessed from the PCI side can be mapped in 8-bit mode or 16-bit mode. In 8-bit mode the data bits LD(15:8) are unused. LAE 0 Set page mode to 16-bit mode. 1 Set page mode to 8-bit mode. Local Bus Arbiter Enable This bit enables the local bus arbiter. In case that the local bus arbiter is enabled the TE3-CHATT will arbitrate for each bus access on the local bus using the arbitration signals. If local bus arbiter functionality is disabled it assumes bus ownership and does not arbitrate for the local bus. LME 0 Disable the local bus arbiter. 1 Enable the local bus arbiter. Local Bus Master Enable This bit enables the local bus master functionality. As long as the local bus master functionality is disabled the TE3-CHATT can be accessed from the local bus as slave only. Data Sheet 0 Disable Local Bus Master. 1 Enable Local Bus Master. 248 05.2001 PEB 3456 E Register Description MTIMER Master Local Bus Timer Register Access : read/write Address : 104H (PCI), 02H (Local Bus) Reset Value : 0000H 15 4 TIMER(15:4) TIMER 3 0 WS(3:0) Local Bus Latency Timer TIMER*16 determines the time in clock cycles the TE3-CHATT holds the local bus as bus master after it was granted the bus. It holds the bus as long as the first transaction is in progress or the latency timer is counting. In case that the TE3-CHATT shall release the bus after it each transaction the latency TIMER value must be set to zero. WS Wait State Timer The value of this register determines the time in clock cycles the TE3CHATT asserts LRD, LWR (Intel Mode) respectively LDS (Motorola Bus Mode). See also FCONF.WSE. Data Sheet 249 05.2001 PEB 3456 E Register Description INTCTRL Interrupt Control Register Access : read/write Address : 108H (PCI), 04H (Local Bus) Reset Value : 0001H 15 0 0 ID 0 0 0 0 0 0 0 0 0 0 3 2 1 0 ID IP CLIQ IM Interrupt Direction This pin determines the direction of the interrupt pin LINT. IP CLIQ 0 LINT is output. 1 LINT is input. Interrupt Polarity 0 LINT is active low. 1 LINT is active high. Clear Interrupt Queue Setting this bit will clear the internal interrupt FIFO. This effects all interrupts of facility data link, framer and mailbox interrupts to the local bus. IM 0 No action 1 Clear interrupt FIFO. Interrupt Mask This bit masks assertion of the pin LINT when interrupts are stored in the internal interrupt FIFO. If the interrupt direction bit is set to output mode interrupt are flagged at interrupt pin LINT. If the interrupt direction is set to input mode interrupts are flagged at pin INTA. Data Sheet 0 Enable assertion of interrupt pin LINT. 1 Disable assertion of interrupt pin LINT. 250 05.2001 PEB 3456 E Register Description INTFIFO Interrupt FIFO Access : read Address : 10CH (PCI), 06H (Local Bus) Reset Value : FFFFH 15 0 IV(15:0) IV Interrupt Vector After the TE3-CHATT asserted interrupt pin LINT on the local bus side, this bit field contains an interrupt vector containing interrupt information. Please refer to section "Layer One Interrupts" on Page 137 for a detailed description of interrupt vector contents. Data Sheet 251 05.2001 PEB 3456 E Register Description TREGSEL Transmit T1/E1 Framer Port & Register Select Access : read/write Address : 110H (PCI), 08H (Local Bus) Reset Value : 0000H 15 14 0 AIP 12 0 8 PORT(4:0) 7 AIA 3 0 0 0 0 ADDR(3:0) Note: This register is an indirect access register, which must be programmed before accessing the register TDATA. AIP Auto Increment Port This bit enables the auto increment function of bit field PORT. Each read/ write access to register TDATA increments PORT. This allows to program multiple, consecutive ports without accessing TREGSEL again. PORT 0 Disable auto increment function. 1 Enable auto increment function. Port Select This bit field selects the port number, which can be accessed via register TDATA. 0..27 Port Number. AIA Auto Increment Address This bit enables the auto increment function of bit field ADDR. Each read/write access to register TDATA increments ADDR. This allows to program multiple, consecutive registers without accessing TREGSEL again. ADDR 0 Disable auto increment function. 1 Enable auto increment function. Register Address This bit field selects the register address of the transmit framer, which can be accessed via register TDATA. 0H..FH Register address. Data Sheet 252 05.2001 PEB 3456 E Register Description TDATA Transmit T1/E1 Framer Data Register Access : read/write Address : 114H (PCI), 0AH (Local Bus) Reset Value : 0000H 15 0 DATA(15:0) Note: Effected port and address is selected via register TREGSEL. All settings in this register affect the selected port only. DATA Data register The transmit framer data register assigns a value to the transmit framer of port TREGSEL.PORT and the register selected via bit field TREGSEL.ADDR. Read/write operation depends on the selected register. Data Sheet 253 05.2001 PEB 3456 E Register Description RREGSEL Receive T1/E1 Framer Port & Register Select Access : read/write Address : 118H (PCI), 0CH (Local Bus) Reset Value : 0000H 15 14 0 AIP 12 0 8 PORT(4:0) 7 6 AIA 0 ADDR(6:0) Note: This register is an indirect access register, which must be programmed before accessing the register RDATA. AIP Auto Increment Port This bit enables the auto increment function of bit field PORT. Each read/ write access to register RDATA increments PORT. This allows to program multiple, consecutive ports without accessing RREGSEL again. PORT 0 Disable auto increment function. 1 Enable auto increment function. Port Select This bit field selects the port number, which can be accessed via register RDATA. 0..27 Port Number. AIA Auto Increment Address This bit enables the auto increment function of bit field ADDR. Each read/write access to register RDATA increments ADDR. This allows to program multiple, consecutive registers without accessing RREGSEL again. ADDR 0 Disable auto increment function. 1 Enable auto increment function. Register Address This bit field selects the register address of the transmit framer, which can be accessed via register RDATA. 0H..7FHRegister address. Data Sheet 254 05.2001 PEB 3456 E Register Description RDATA Receive T1/E1 Framer Data Register Access : read/write Address : 11CH (PCI), 0EH (Local Bus) Reset Value : 0000H 15 0 DATA(15:0) Note: Effected port and address is selected via register RREGSEL. All settings in this register affect the selected port only. DATA Data register The receive framer data register assigns a value to the receive framer of port RREGSEL.PORT and the register selected via bit field RREGSEL.ADDR. Read/write operation depends on the selected register. Data Sheet 255 05.2001 PEB 3456 E Register Description FREGSEL FDL Port & Register Select Access : read/write Address : 120H (PCI), 10H (Local Bus) Reset Value : 0000H 15 AIP 12 0 0 8 PORT(4:0) 7 AIA 4 0 0 0 ADDR(4:0) Note: This register is an indirect access register which must be programmed before accessing the register FDATA. AIP Auto Increment Port This bit enables the auto increment function of bit field PORT. Each read/ write access to register FDATA increments PORT. This allows to program multiple, consecutive ports without accessing FREGSEL again. PORT 0 Disable auto increment function. 1 Enable auto increment function. Port Select This bit field selects the port number, which can be accessed via register FDATA. 0..27 Port Number for T1/E1. 28 Far End Alarm and Control Channel (DS3) 29 C-bit parity path maintenance data link channel (DS3) Setup FDL in T1 mode, enable BOM transfer. Setup FDL in E1 mode and assign Sa-bit access for bits Sa4, Sa5 and Sa6 .Disable access for Sa7 and Sa8. AIA Auto Increment Address This bit enables the auto increment function of bit field ADDR. Each read/write access to register FDATA increments ADDR. This allows to program multiple, consecutive registers without accessing FREGSEL again. Data Sheet 0 Disable auto increment function. 1 Enable auto increment function. 256 05.2001 PEB 3456 E Register Description ADDR Register Address This bit field selects the register address of the facility data link channel, which can be accessed via register FDATA. 0H..1FHRegister address. Data Sheet 257 05.2001 PEB 3456 E Register Description FDATA FDL Data Register Access : read/write Address : 124H (PCI), 12H (Local Bus) Reset Value : 0000H 15 0 DATA(15:0) Note: Effected port and address is selected via register FREGSEL. All settings in this register affect the selected port only. DATA Data register The FDL data register assigns a value to the facility data link controller of port FREGSEL.PORT and the register selected via bit field FREGSEL.ADDR. Read/write operation depends on the selected register. Data Sheet 258 05.2001 PEB 3456 E Register Description MBE2P0 Mailbox Local Bus to PCI Command Register Access : read/write Address : 140H (PCI), 20H (Local Bus) Reset Value : 0000H 15 0 MB(15:0) MB Mailbox Data register This register can be written and read from local bus side. From PCI side this register should be used as read only in order to allow stable interprocessor communication. Write access to this register results in mailbox interrupt vectors on local bus side to the internal interrupt FIFO when FCONF.MBID is set to `0'. Data Sheet 259 05.2001 PEB 3456 E Register Description MBE2P1-7 Mailbox Local Bus to PCI Data Register 1-7 Access : read/write Address : 144H-15CH (PCI), 22H-2EH (Local Bus) Reset Value : 0000H 15 0 MB(15:0) MB Mailbox Data register This register can be written and read from local bus side. From PCI side this register should be used as read only in order to allow stable interprocessor communication. Data Sheet 260 05.2001 PEB 3456 E Register Description MBP2E0 Mailbox PCI to Local Bus Status Register Access : read/write Address : 160H (PCI), 30H (Local Bus) Reset Value : 0000H 15 0 MB(15:0) MB Mailbox Status Register This register can be written and read from PCI side. From local bus side this register should be used as read only in order to allow stable interprocessor communication. Write access to this register results in mailbox interrupt vectors to PCI side when CONF1.MBIM is set to `0'. Data Sheet 261 05.2001 PEB 3456 E Register Description MBP2E1-7 Mailbox PCI to Local Bus Data Register 1-7 Access : read/write Address : 164H-17CH (PCI), 32H-3EH (Local Bus) Reset Value : 0000H 15 0 MB(15:0) MB Mailbox Data Register This register can be written and read from PCI side. From local bus side this register should be used as read only in order to allow stable interprocessor communication. Data Sheet 262 05.2001 PEB 3456 E Register Description 8.9.2.1 M13 Transmit Registers D3CLKCS DS3 Clock Configuration and Status Register Access : read/write Address : 180H (PCI), 40H (Local bus) Reset Value : 0000H 15 0 6 0 0 0 0 0 0 0 0 5 4 3 2 1 0 RCA TCA RRX RTX T2RL R2TL TXLT Note: When this register is reset, it takes aproximately 150 ns to fully reset the recevie and transmit clock units. During this time, write access to DS3 registers is not guaranteed. As this reset delay is difficult to gurantee in software, it is recommended to read this register to verify DS3 clock activity before writing to any DS3 registers. RCA Receive Clock Activity This bit monitors the receive clock activity (RC44). TCA 0 No receive DS3 clock since last read of this register. This bit is set to `0' approx. 125 s after the last active clock was detected. 1 At least one receive DS3 clock since last read of this register. Transmit Clock Activity This bit monitors the transmit clock activity (TC44). RRX 0 No transmit DS3 clock since last read of this register. This bit is set to `0' approx. 125 s after the last active clock was detected. 1 At least one transmit DS3 clock since last read of this register. Reset Receiver Clock Unit This bit resets the receivers clock unit. RTX 0 Normal operation. 1 Reset DS3 receiver clock unit. This bit is self clearing. Reset Transmitter Clock Unit This bit resets the transmitters clock unit. Data Sheet 263 05.2001 PEB 3456 E Register Description T2RL 0 Normal operation. 1 Reset DS3 transmitter clock unit. This bit is self clearing. Transmit to Receive Loop (Local DS3 Loopback) This bit enables the local DS3 loop where the outgoing DS3 bit stream is mirrored to the DS3 input. R2TL 0 Disable local loop. 1 Enable local loop. Receive to Transmit Loop (Remote DS3 Loopback) This bit enables the remote DS3 line loop where the complete incoming DS3 bit stream is mirrored to the transmitter. TXLT 0 Disable remote loop. 1 Enable remote loop. Transmit Loop Timing Mode This bit enables DS3 looped timing where the transmitter uses the receivers DS3 input clock. Data Sheet 0 Disable looped timing. 1 Enabled looped timing. 264 05.2001 PEB 3456 E Register Description TUCLKC Test Unit Clock Configuration Register Access : read/write Address : 184H (PCI), 42H (Local bus) Reset Value : 0000H 15 0 1 0 RTUR 0 0 0 0 0 0 0 0 0 0 0 0 0 RTUR TUL Reset Test Unit Receiver This bit resets the test unit receiver. TUL 0 Normal operation. 1 Reset Receiver (automatically removed). This bit is self clearing. Test Unit Transmit to Receive Loop This bit switches a local loop from the test unit transmitter to the test unit receiver. While operating in loop mode the test unit is operated with TC44. Data Sheet 0 Normal operation. 1 Test unit transmitter output connected to test unit receiver input. 265 05.2001 PEB 3456 E Register Description D3TCFG DS3 Transmit Configuration Register Access : read/write Address : 188H (PCI), 44H (Local bus) Reset Value : 0000H 15 0 8 0 FAM 0 0 0 0 0 7 FAM ITCK 6 ITD 5 4 UTD AISC 3 2 LPC(1:0) 1 0 FPL CBP TOVHSYN Mode This bit switches between input mode and output mode of the signal pin TOVHSYN. If TOVHSYN is operated in input mode it marks the position of the X-bit. Therefor the outgoing DS3 frame is aligned to TOVHSYN. If TOVHSYN is switched to output mode TOVHSYN is asserted when the X-bit needs to be inserted via the transmit overhead interface. ITCK 0 TOVHSYN switched to input. 1 TOVHSYN switched to output. Invert Transmit Clock This bit sets the clock edge for data transmission. ITD 0 Update transmit data on the rising edge of transmit clock. 1 Update transmit data on the falling edge of transmit clock. Invert Transmit Data This bit enables inversion of transmit data. UTD 0 Transmit data is logic high (not inverted). 1 Transmit data is logic low (inverted). Unipolar data mode This bit sets the port mode to dual-rail mode or unipolar mode. Data Sheet 0 B3ZS (dual rail data) 1 Unipolar mode (single rail data) 266 05.2001 PEB 3456 E Register Description AISC AIS Code Type This bit field sets the AIS code. LPC 0 Set AIS to '1010... ' between overhead bits, C-bits all `0's, X-bits all `1's (standard) 1 Set AIS to unframed all `1's (non-standard). Loopback Code. This bit field selects the C-bit which will be inverted when loopback requests are transmitted. FPL 00 Invert 1st C-bit. 01 Invert 2nd C-bit. 10 Invert 3rd C-bit. Full Payload Mode This bit enables the M23 multiplex operation or the full payload rate format. CBP 0 Enable M23 multiplex operation. Payload is formed by interleaving 7 asynchronous DS2 tributaries 1 Enable full payload rate format. The payload is one single, high speed data stream without stuffing. C-bit parity mode This bit enables M13 asynchronous mode or C-bit parity mode. Data Sheet 0 M13 asynchronous mode 1 C-bit parity mode 267 05.2001 PEB 3456 E Register Description D3TCOM DS3 Transmit Command Register Access : read/write Address : 18CH (PCI), 46H (Local bus) Reset Value : 0000H Reset Value : 0000H Note - It is recommended to set this register to 000070H after reset for normal operation. 15 0 6 0 TAIC 0 0 0 0 0 0 0 5 4 3 2 1 0 TAIC TNrB TXBIT SIDLESAISA SAIS 0 Transmitted AIC-bit This bit sets the value to be transmitted in the DS3 overhead bit of block 3, subframe 1. This function is available in C-pit parity format only. TNrB 0 AIC-bit = `0' 1 AIC-bit = `1' Transmitted Nr-bit This bit sets the value to be transmitted in the DS3 overhead bit of block 5, subframe 1. This function is available in C-pit parity format only. TXBIT 0 Nr-bit = `0' 1 Nr-bit = `1' Transmitted X-bits This bit sets the value to be transmitted in the DS3 overhead bit of block 1, subframes 1 and 2. TXBIT is synchronized to the M23 multiframe. Both X-bits in a multiframe are guaranteed identical. Software should limit changes to maximum of 1 per second. This bit should be set to `1', if transmission of IDLE or AIS is enabled. SIDLE Data Sheet 0 X-bit = `0' 1 X-bit = `1' Send DS3 Idle Code 268 05.2001 PEB 3456 E Register Description This bit enables transmission of the DS3 idle code ('1010' between overhead bits, X-bits all `1's, C-bits all `0's). SAISA 0 Normal operation. 1 Send DS3 idle code. Send AIS in DS3 output and on DS3 loop This bit enables transmission of AIS on the DS3 output. If the DS3 is additionally switched to local DS3 loopback mode the DS3 signal including AIS is mirrored to the receiver. The AIS code transmitted depends on D3TCFG.AISC. SAIS 0 Normal operation. 1 Enable transmission of AIS. Send AIS at DS3 output This bit enables transmission of AIS on the DS3 output. If the DS3 signal is switched into local DS3 loopback mode the DS3 signal without AIS code is mirrored to the DS3 receiver. The AIS code transmitted depends on D3TCFG.AISC. Data Sheet 0 Normal operation. 1 Enable transmission of AIS. 269 05.2001 PEB 3456 E Register Description D3TLPB DS3 Transmit Remote DS2 Loopback Register Access : read/write Address : 190H (PCI), 48H (Local bus) Reset Value : 0000H 15 0 6 0 LPB 0 0 0 0 0 0 0 0 LPB(6:0) Remote DS2 Loopback Setting LPB(x) enables the remote DS2 loopback of tributary x. In this mode the demultiplexed DS2 tributary is internally looped and multiplexed into the outgoing DS3 signal. Data Sheet 0 Normal operation. 1 Enable remote DS2 loopback of tributary x. 270 05.2001 PEB 3456 E Register Description D3TLPC DS3 Transmit Loopback Code Insertion Register Access : read/write Address : 194H (PCI), 4AH (Local bus) Reset Value : 0000H 15 0 6 0 LPC 0 0 0 0 0 0 0 0 LPC(6:0) Send Loopback Setting LPC(x) enables transmission of the loopback code in tributary x of the DS3 signal. The loopback code inserted depends on D3TCFG.LPC. Data Sheet 0 Normal operation. 1 Enable transmission of loopback code in tributary x. 271 05.2001 PEB 3456 E Register Description D3TAIS DS3 Transmit AIS Insertion Register Access : read/write Address : 198H (PCI), 4CH (Local bus) Reset Value : 0000H 15 0 7 0 AISE 0 0 0 0 0 0 6 AISE 0 AIS(6:0) AIS Error Insertion Toggling this bit inserts one `0' in all DS3 tributaries which transmit AIS. AIS Send DS2 Alarm Indication Signal Setting AIS(x) enables insertion of the DS2 alarm indication signal in the outgoing tributary x of the DS3 signal. AIS is an all '1' signal. Data Sheet 0 Normal operation 1 Enable transmission of AIS in tributary x. 272 05.2001 PEB 3456 E Register Description D3TFINS DS3 Transmit Fault Insertion Control Register Access : read/write Address : 19CH (PCI), 4EH (Local bus) Reset Value : 0000H 15 0 3 0 FINSC 0 0 0 0 0 0 0 0 0 0 0 FINSC(3:0) Fault Insertion Code. Fault insertion is service affecting and is intended for testing only. Codes are not self clearing, i.e. errors are continuously generated as indicated until bit cleared. A single FEBE, P, CP, or code violation is guaranteed to be inserted if the respective code is written and then immediately cleared. Data Sheet 0 Normal operation (no fault insertion) 1 Insert FEBE event every multiframe (106 sec). 2 Insert P-bit errors every 2nd multiframe (212 sec). 3 Insert CP-bit errors every 2nd multiframe (212 sec). 4 Insert 4 F-bit errors/multiframe (satisfies 3 out of 15 threshold trigger). 5 Insert 5 F-bit errors/multiframe (satisfies 3 out of 7 threshold trigger). 6 Insert 3 M-bit errors/multiframe (caution: receiver can frame on emulator). 7 Force DS3 output to all `0's. 8 Insert B3ZS violation/multiframe (violation of alternate polarity rule). 9 Insert 3 zero string/multiframe (B3ZS code word suppressed) 273 05.2001 PEB 3456 E Register Description D3TTUC DS3 Transmit Test Unit Control Register Access : read/write Address : 1A0H (PCI), 50H (Local bus) Reset Value : 0000H 15 0 7 0 EN 0 0 0 0 0 0 EN 6 4 TUDS2(2:0) 3 2 TUDS1(1:0) 1 0 TUIM Enable Test Unit Insertion Setting this bit enables insertion of the test unit data. TUDS2 0 Normal operation 1 Enable insertion of test unit data. Test Unit DS2 Group This bit field selects the DS2 group the test unit is attached to. Only valid if TUIM is 10B, 01B or 00B. 0..6 TUDS1 Selects DS2 group 0..6. Test Unit DS1 Tributary This bit field selects the DS1 tributary the test unit is attached to. Only valid if TUIM is 00B. The DS2 group is selected via TUDS2. 0..3 TUIM DS1/E1 tributary Bit Error Rate Test Unit (TU) Insertion Mode This bit field selects the interface the test unit is attached to. Data Sheet 00B Insert test stream into DS1/E1 tributary (unframed) 01B Insert test stream into DS2 tributary (unframed, bypass M12) 10B Insert test stream into DS2 payload (framed) 11B Insert test stream into DS3 payload (framed) 274 05.2001 PEB 3456 E Register Description D3TSDL DS3 Transmit Spare Data Link Register Access : read/write Address : 1A4H (PCI), 52H (Local bus) Reset Value : 01FFH 15 0 8 0 0 0 0 0 0 7 6 5 4 3 2 1 0 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23 Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh of this register. The software must write these registers within 106 sec to avoid an underrun. DL(S)(B) Overhead bit for block B of subframe S These bits store the DL bits to be transmitted in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh of this register. The software must write these registers within 106 sec to avoid an underrun. Data Sheet 275 05.2001 PEB 3456 E Register Description D3RCFG DS3 Receive Configuration Register Access : read/write Address : 1C0H (PCI), 60H (Local bus) Reset Value : 0000H 15 CVM 11 0 0 0 10 9 8 6 IVM STTM ECM FEBM 0 5 4 3 2 1 AISX MFM MDIS FFM IRCK IRD 0 URD Note: M13 mode, Full payload mode, loopback code, and AIS mode are controlled by bits CBP, FPL, LPC, and AISC in register DS3 transmit configuration register D3TCFG. CVM B3ZS Code Word ("00V" or "10V" Acceptance Condition) This bit selects the B3ZS violations alternate polarity to maintain line balance. IVM 0 Convert all B3ZS codeword patterns to "000" regardless of polarity. 1 Convert codeword only if alternate violation polarity rule is satisfied. Interrupt Vector Mode This bit selects the interrupt vector mode. STTM 0 Interrupt vector flags are set when corresponding condition has changed. 1 Interrupt vector flags contain actual status of condition. Select Transmit Tributary Monitoring for receive test unit This bit selects the T1/E1 tributary observed by the test unit receiver. The test unit can be connected to the upstream T1/E1 tributary (T1/E1 tributary going towards the DS3 interface) or to the downstream T1/E1 tributary (T1/E1 tributary coming from the DS3 interface). Data Sheet 0 Monitor downstream T1/E1 tributary. 1 Monitor upstream T1/E1 tributary. 276 05.2001 PEB 3456 E Register Description ECM Error Counter Mode DS3 errors are counted in background and copied to foreground (error counter registers) when condition selected via ECM is met. FEBM 0 Counter values are copied to foreground when copy command is executed. See also register DS3COM. 1 The counter values are copied to the foreground register in one second intervals. At the same time the background registers are reset to zero. This operation is synchronous with the periodic one second interrupt which alerts software to read the register. Far End Block Error (FEBE) Mode This bit selects the event which leads to FEBE indication. It is available in C-bit parity mode only. AISX 0 Receive multiframe parity error. 1 Receive multiframe parity error or framing error. AIS X-bit Check Disable This bit disables checking of the X-bit for AIS and idle detection. MFM 0 Check X-bit. 1 Disable check of X-bit. Multiframe Framing Mode This bit selects the M-bit error condition which triggers the DS3 framer to start a new frame search. To enable reframing in case of M-bit errors MDIS must be set to `0'. MDIS 0 Start new F-frame search if M-bit errors are detected in two out of four consecutive M-frames. 1 Start new F-frame search if M-bit errors are detected in three out of four consecutive M-frames. Multiframe Reframe Disable This bit disables reframing due to M-bit errors. Data Sheet 0 Enable reframe due to M-bit errors. 1 Disable reframe due to M-bit errors. 277 05.2001 PEB 3456 E Register Description FFM F Framing Mode This bit selects the F-bit error condition which triggers the DS3 framer to start a new frame search. IRCK 0 A new frame search is started when 3 out of 8 contiguous F-bits are in error. 1 A new frame search is started when 3 out of 16 contiguous F-bits are in error. Invert Receive Clock This bit sets the clock edge for data sampling. IRD 0 Sample data on the rising edge of receive clock. 1 Sample data on the falling edge of receive clock. Invert Receive Data This bit enables inversion of receive data. URD 0 Receive data is logic high (not inverted). 1 Receive data is logic low (inverted). Unipolar Receive Data This bit sets the port mode to dual-rail mode or unipolar mode. Data Sheet 0 B3ZS (dual rail data input) 1 Unipolar mode (single rail data input) 278 05.2001 PEB 3456 E Register Description D3RCOM DS3 Receive Command Register Access : read/write Address : 1C4H (PCI), 62H (Local bus) Reset Value : 0000H 15 0 4 0 C3NC 0 0 0 0 0 0 0 0 0 3 2 1 0 C3NC C3C CNCA CCA FRS Copy DS3 Error Counters Values of DS3 background registers are copied to foreground. Background registers are NOT cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. Note: Usage of this function in not recommend in 'One Second' error counter mode (D3RCFG.ECM = `1'). C3C 0 No operation. 1 Copy background counters to foreground. Copy and Clear DS3 Error Counters Values of DS3 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. 0 No operation. 1 Copy background counters to foreground. Clear background counters. Note: Usage of this function in not recommend in 'One Second' error counter mode (D3RCFG.ECM = `1'). CCNA Copy Error Counters Only valid for counters which are not operating in `One Second' error counter mode. Values of DS2 and DS3 background registers are copied to foreground. Background registers are NOT cleared. Command is self Data Sheet 279 05.2001 PEB 3456 E Register Description clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. CCA 0 No operation. 1 Copy background counters to foreground. Copy and Clear DS2/DS3 Error Counters Only valid for counters which are not operating in `One Second' error counter mode. Values of DS2 and DS3 background registers are copied to foreground. Background registers are cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. FRS 0 No operation. 1 Copy background counters to foreground. Clear background counters. Force Resynchronization This bit enables a new frame search on the DS3 input. The command is self clearing after frame search has begun. Data Sheet 0 Normal operation. 1 Force new frame search. 280 05.2001 PEB 3456 E Register Description D3RIMSK DS3 Receive Interrupt Mask Register Access : read/write Address : 1C8H (PCI), 64H (Local bus) Reset Value : 1FFFH 15 0 12 0 0 11 10 9 8 CLKS RSDL TSDL LPCS SEC 7 6 Nr AIC 5 4 3 2 1 0 XBIT IDLES AISS REDS LOSS FAS This register provides the interrupt mask for DS3 status interrupts and DS3 loopback code interrupts. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One Interrupts" on Page 137. The following definition applies: 1 The corresponding interrupt vector will not be generated by the device. 0 The corresponding interrupt vector will be generated. RSDL Mask 'Receive Spare Data Link Transfer Buffer Full' TSDL Mask 'Transmit Spare Data Link Transfer Buffer Empty' LPCS Mask 'Loopback Code Status' (flagged in D3RLPCS) SEC Mask '1 Second Interrupt' CLKS Mask 'DS3 Clock Status' Nr Mask 'Nr-bit Image' (C-bit parity mode only) AIC Mask 'AIC-bit Image' (C-bit parity mode) XBIT Mask 'X-bit Image' IDLES Mask 'DS3 Idle Signal State' AISS Mask 'DS3 Alarm Indication Signal State' REDS Mask 'DS3 Red Alarm State' LOSS Mask 'DS3 Input Signal State' FAS Mask 'Frame Alignment State' Data Sheet 281 05.2001 PEB 3456 E Register Description D3RESIM DS3 Receive Error Simulation Register Access : read/write Address : 1CCH (PCI), 66H (Local bus) Reset Value : 0000H 15 0 4 0 FTMR 0 0 0 0 0 0 0 0 0 FTMR 2 0 0 ESIMC(2:0) Fast Timer This bit enables alarm timer test function (manufacturing test only). 0 Normal Operation 1 Test Operation DS3 RED/AIS/Idle timer period reduced by 56. DS2 READ/AIS timer period reduced by 24. Second interrupt period reduced to 140 sec ESIMC Error Simulation Code This bit enables error simulation. During error simulation the device generates error interrupts and error status messages. Nevertheless the service is not affected. Data Sheet 0 Normal operation (no error simulation). 1 Simulate one F-bit error/multiframe (106 sec). 2 Simulate M-bit error in every other multiframe. 3 Simulate FEBE event/multiframe (106 sec). 4 Simulate P/CP event/multiframe (106 sec). 5 Simulate Loss of DS3 input (all zeros). 6 Simulate B3ZS code violations. 7 Simulate Loss of Receive Clock 282 05.2001 PEB 3456 E Register Description D3RTUC DS3 Receive Test Unit Control Register Access : read/write Address : 1D0H (PCI), 68H (Local bus) Reset Value : 0000H 15 0 7 0 EN 0 0 0 0 0 0 EN 6 4 TUDS2(2:0) 3 2 TUDS1(1:0) 1 0 TURM Enable Test Unit Receive Clock This bit enables the receive clock of the test unit. The clock speed is dependent on the selected test mode. TUDS2 0 Receive clock disabled. 1 Receive clock enabled. Test Unit DS2 Group This bit field selects the DS2 group the test unit is attached to. Only valid if TURM is 10B, 01B, or 00B. 0..6 TUDS1 Selects DS2 group 0..6. Test Unit DS1/E1 Tributary This bit field selects the DS1/E1 tributary the test unit is attached to. Only valid if TURM is 00B. The DS2 group is selected via TUDS2. 0..3 TURM DS1/E1 tributary Test Unit Receive Mode This bit field selects the interface the test unit is attached to. Data Sheet 00B DS1/E1 tributary (unframed) 01B DS2 tributary (unframed, bypass M12) 10B DS2 payload (framed) 11B DS3 payload (framed) 283 05.2001 PEB 3456 E Register Description D3RSTAT DS3 Receive Status Register Access : read Address : 1D4H (PCI), 6AH (Local bus) Reset Value : 0841H (Immediately after reset) : 084DH (After some clock cycles) : Depends on time register will be read after reset. : Status register will change after some clock cycles becaues LOSS : (loss of signal) and REDS (loss of frame alignment) will be set : because no signal is available. 15 0 14 13 12 11 10 9 LRXC LTXC RSDL TSDL LPCD SEC 8 7 AIC Nr AICC 6 5 4 3 2 1 0 XBIT IDLES AISS REDS LOSS COFA FAS Each bit in the DS3 framer receive status register declares a specific condition dependent on the selected modes. The following convention applies to the individual bits: 0 The named status is not or no longer existing. 1 The named status is currently effective. Except for COFA every bit can be used to generate a DS3 interrupt vector. See also register D3RIMSK which describes how to enable/disable interrupt vector generation and refer to the description of DS3 framer interrupts on page "Layer One Interrupts" on Page 137. LRXC Loss of Receive DS3 Clock This bit indicates loss of DS3 receive clock. LTXC Loss of Transmit DS3 Clock This bit indicates loss of DS3 transmit clock. RSDL Receive Spare Data Link Buffer Full This bit indicates that the spare data link receive buffer (register D3RSDL) is full. TSDL Data Sheet Transmit Spare Data Link Buffer Empty 284 05.2001 PEB 3456 E Register Description This bit indicates that the spare data link transmit buffer (register D3TSDL) is empty. LPCD Loopback Code Detected This bit indicates a changes in register D3RLPCS. SEC 1 Second Flag This bit toggles every second synchronously with the one second interrupt. It can be used by software to synchronize 1 second events when the 'One second interrupt' vector is masked. Nr/AICC Nr-bit Image (C-bit parity format only) This bit contains an image of the DS3 frame overhead bit in block 5 of subframe 1. It is updated only if its state persists for 3 multiframes and DS3 frame is aligned. AIC-bit changed (M13 asynchronous format) This bit indicates a change of the AIC-bit (first C-bit of the first subframe) since the last read of this register. AIC AIC bit Image (DS3 frame overhead bit in block 3 of subframe 1) This bit contains an image of the DS3 frame overhead bit in block 3 of subframe 1. It is updated only if its state persists for 3 multiframes and DS3 frame is aligned. XBIT X bit Image (DS3 frame overhead bit in block 1 of subframes 1 and 2) This bit contains an image of the DS3 frame overhead bit in block 1 of subframes 1 and 2. It is updated only if both bits in a DS3 multiframe have the same value, its state persists for at least 3 multiframes and when the DS3 framer is in synchronous state. IDLES Idle State This bit indicates that the idle pattern (framed ...1100... with C-bits='0' in subframe 3 and X-bits='1') was persistent as per alarm timing parameters defined in register D3RAP. Idle is considered active in a multiframe when fewer than 15 errors are detected. At 10-3 error rates, 5 errors per multiframe are typical. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag is set or cleared respectively. AISS AIS Alarm State. This bit indicates the AIS alarm state. AIS can be a framed '..1010..' pattern with C-bits='0' and X-bits='1' or an unframed all `1' pattern. This is determined by D3TCFG.AISC. AIS is considered active in a Data Sheet 285 05.2001 PEB 3456 E Register Description multiframe when fewer than 15 errors are detected and is declared when it was persistent as per alarm timing parameters defined in register D3RAP. At 10-3 error rates, 5 errors per multiframe are typical. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag is set or cleared respectively. REDS Red Alarm State (loss of frame alignment) This bit indicates that red alarm was persistent as per alarm timing parameter defined in register D3RAP. The red alarm flag nominally changes when loss of frame alignment condition persists for either 32 or 128 multiframes. This is determined by bit D3RCFG.SAIT. The exact time necessary to change the flag could be greater if the FAS flag is not constant. The frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag set or cleared respectively. LOSS Loss of DS3 Input Signal This bit indicates that the received DS3 bit stream contained at least 175 consecutive `0's. It is deasserted when 59 `1' bits are detected in 175 clocks (1/3 density). Following removal of LOS, a 10 msec guard timer is started. If a new LOS occurs, the release condition is extended so that the 1/3 density condition must persist for at least 10 msec. This prevents chatter and excessive interrupts. COFA Change of Frame Alignment. This bit indicates a change of frame alignment event. It is set when the DS3 framer found a new frame alignment and when the new frame position differs from the expected frame position. FAS DS3 Frame Alignment State This bit indicates that the DS3 framer is not aligned. Data Sheet 286 05.2001 PEB 3456 E Register Description D3RLPCS DS3 Receive Loopback Code Status Register Access : read Address : 1D8H (PCI), 6CH (Local bus) Reset Value : 0000H 15 0 6 0 LPCD 0 0 0 0 0 0 0 0 LPCD(6:0) Loopback Detected LPCD(x) indicates that a loopback request was received. A loopback request for tributary x is indicated by inverting one of the 3 C-bits of the xth subframe. The C-bit is determined by D3TCFG.LPC. A command state change must persist for 5 contiguous multiframes before it will be reported. This function is available in M13 asynchronous mode only. Data Sheet 0 No loopback code being received 1 Loopback code being received 287 05.2001 PEB 3456 E Register Description D3RSDL DS3 Receive Spare Data Link Register Access : read Address : 1DCH (PCI), 6EH (Local bus) Reset Value : 01FFH 15 0 8 0 DL(S)(B) 0 0 0 0 0 7 6 5 4 3 2 1 0 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23 Overhead Bit for Block B of Subframe S These bits buffer the spare DL bits received in blocks 3, 5, and 7 of subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt every multiframe to synchronize reading of this register. The register must be read within 106 sec to avoid an overrun. Data Sheet 288 05.2001 PEB 3456 E Register Description D3RCVE DS3 Receive B3ZS Code Violation Error Counter Access : read/write Address : 1E0H (PCI), 70H (Local bus) Reset Value : 0000H 15 0 CVE(15:0) CVE(15:0) B3ZS Code Violation Errors Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of B3ZS Code Violation errors. The error counter will not be incremented during asynchronous state. D3RFEC DS3 Receive Framing Bit Error Counter Access : read/write Address : 1E4H (PCI), 72H (Local bus) Reset Value : 0000H 15 0 FEC(15:0) FEC(15:0) Framing Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of F-bit and M-bit errors. Errors are not counted in out of frame state. Data Sheet 289 05.2001 PEB 3456 E Register Description D3RPEC DS3 Receive Parity Error Counter Access : read/write Address : 1E8H (PCI), 74H (Local bus) Reset Value : 0000H 15 0 PE(15:0) PE(15:0) Parity Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of parity errors (P-bits in DS3 overhead bits). The P-bit is duplicated in the DS3 frame structure but only one error is counted per multiframe. Errors are not counted in out of frame state. D3RCPEC DS3 Receive Path Parity Error Counter Access : read/write Address : 1ECH (PCI), 76H (Local bus) Reset Value : 0000H 15 0 CPE(15:0) CPE(15:0) Path Parity Error Counter Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Count of path parity errors (CP bits in DS3 C-bit parity overhead bits). CP-bits are triplicated in the DS3 frame structure but only single error maximum is counted per multiframe. Errors are not counted in out of frame state. Data Sheet 290 05.2001 PEB 3456 E Register Description D3RFEBEC DS3 Receive FEBE Error Counter Access : read/write Address : 1F0H (PCI), 78H (Local bus) Reset Value : 0000H 15 0 FEBE(15:0) FEBEC(15:0) FEBE error events Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. This register counts the occurence of a received `not all `1's'. FEBE-bits are triplicated in the DS3 frame structure but only one single error maximum is counted per multiframe. Errors are not counted in out of frame state. D3REXZ DS3 Receive Excessive Zeroes Counter Access : read/write Address : 1F4H (PCI), 7AH (Local bus) Reset Value : 0000H 15 0 EXZ(15:0) EXZ(15:0) Exzessive Zeroes Error counter mode (Clear on Read or Errored Second) depends on register D3RCFG.ECM. Violations are 3 zero strings. The error counter will not be incremented during asynchronous state. Data Sheet 291 05.2001 PEB 3456 E Register Description D3RAP DS3 Alarm Parameters Access : read/write Address : 1F8H (PCI), 7CH (Local bus) Reset Value : 0000H 15 0 7 0 AIS 0 0 0 0 0 0 AIS 5 0 0 CV(5:0) AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS depends on value defined in bit field CV. CV 0 AIS is recognized when the alarm indication signal is received with less than 8 errors per multiframe. 1 AIS is recognized when the alarm indication signal is received with less than 15 errors per multiframe. Counter Value This bit specifies the number of frames when the TE3-CHATT declares AIS, RED or Idle. 0..63 Counter Value. Data Sheet 292 05.2001 PEB 3456 E Register Description 8.9.2.2 DS2 Control and Status Registers D2TSEL DS2 Transmit Group Select Register Access : read/write Address : 200H (PCI), 80H (Local bus) Reset Value : 0000H 15 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 GN(2:0) Note: This register is an indirect access register, which must be programmed before accessing the register DS2 transmit registers. GN Group Number This bit field selects the DS2 group, which can be accessed via the DS2 transmit registers. 0..6 Data Sheet Group Number. 293 05.2001 PEB 3456 E Register Description D2TCFG DS2 Transmit Configuration Register Access : read/write Address : 204H (PCI), 82H (Local bus) Reset Value : 0000H 15 0 2 0 LPC 0 0 0 0 0 0 0 0 0 0 0 1 0 LPC(1:0) E1 Loopback Code This bit selects the C-bit which will be inverted when loopback requests are transmitted. E1 00 Invert 1st C-bit. 01 Invert 2nd C-bit. 10 Invert 3rd C-bit. G.747 Select This bit selects the operation mode of the low speed multiplexer. Data Sheet 0 Select M12 mode (4 DS1 into DS2). 1 Select ITU-T G.747 mode (3 E1 into DS2). 294 05.2001 PEB 3456 E Register Description D2TCOM DS2 Transmit Command Register Access : read/write Address : 208H (PCI), 84H (Local bus) Reset Value : 0000H 15 0 3 0 FINSC 0 0 0 0 0 0 0 0 0 0 2 1 0 FINSC(1:0) SRA RES Fault Insertion Code This bit enables transmission of faults for testing purposes. SRA 0 No fault insertion. 1 Insert F-bit errors at low rate (2 out of 5 F-bits). 2 Insert F-bit errors at high rate (2 out of 4 F-bits). 3 Insert M-bit framing bit error (DS1 mode) or P-bit error (ITU-T G.747) Set Remote Alarm This bit enables transmission of the DS3 remote alarm. In DS1 modes remote alarm is transmitted in subframe 4, block 1 overhead bit and in ITU-T G.747 remote alarm is transmitted in bit 2 of "set II". RES 0 Normal operation. 1 Enable transmission of remote alarm. ITU-T G.747 Reserved Bit This bit sets the value to be transmitted in the reserved bit of ITU-T G.747 format. Data Sheet 0 Transmit reserved bit as '0'. 1 Transmit reserved bit as '1'. 295 05.2001 PEB 3456 E Register Description D2TILPC DS2 Transmit E1/T1 Remote Loopback/Loopback Code InsertionRegister Access : read/write Address : 20CH (PCI), 86H (Local bus) Reset Value : 0000H 15 0 3 0 LPC 0 0 0 0 0 0 0 0 0 0 0 LPC(3:0) Send Loopback Code for Tributary N Setting LPC(x) enables transmission of the loopback code in tributary x. The loopback code inserted is specified in D2TCFG.LPC. Data Sheet 0 Disable transmission of loopback code. 1 Enable transmission of loopback code. 296 05.2001 PEB 3456 E Register Description D2RSEL DS2 Receive Group Select Register Access : read/write Address : 220H (PCI), 90H (Local bus) Reset Value : 0000H 15 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 GN(2:0) Note: This register is an indirect access register, which must be programmed before accessing the register DS2 transmit registers. GN Group Number This bit field selects the DS2 group number, which can be accessed via the DS2 receive registers. 0..6 Data Sheet Group Number. 297 05.2001 PEB 3456 E Register Description D2RCFG DS2 Receive Configuration Register Access : read/write Address : 224H (PCI), 92H (Local bus) Reset Value : 0000H 15 0 3 0 0 0 0 0 0 0 0 0 0 0 ECM 1 0 0 MFM FFM Note: ITU-T G.747 mapping and loopback codes are controlled by bits E1 and LPC in the DS3 transmit configuration register D2TCFG. E1/T1 and loopback codes are controlled by E1 and LPC fields of the D2TCFG register. ECM Error Counter Mode DS2 errors are counted in background and copied to foreground (error counter registers) when condition selected via ECM is met. MFM 0 Counter values are copied to foreground when copy command is executed. See also register DS3COM. 1 The counter values are copied to the foreground register in one second intervals. At the same time the background registers are reset to zero. This operation is synchronous with the periodic one second interrupt which alerts software to read the register. Multiframe Framing Mode This bit selects the M-bit error condition which triggers the DS2 framer to start a new frame search. It is valid in DS1 mode only. FFM 0 F-frame search started if 3 contiguous multiframes have M-bit errors. 1 Inhibit new F-frame search due to M-bit errors. F-Framing Mode This bit selects the F-bit error condition which triggers the DS2 framer to start a new frame search. Data Sheet 0 A new frame search is started when 2 out of 4 contiguous F-bits are in error. 1 A new frame search is started when 2 out of 5 contiguous F-bits are in error. 298 05.2001 PEB 3456 E Register Description D2RCOM DS2 Receive Command Register Access : read/write Address : 228H (PCI), 94H (Local bus) Reset Value : 0000H 15 0 6 0 ESIMC 0 0 0 0 0 0 0 4 ESIMC(2:0) 1 0 0 0 C2NC C2C Error Simulation Code This bit field enables error simulation. During error simulation the device generates error interrupts and error status messages. Nevertheless the service is not affected. C2NC 0 Normal operation (no error simulation) 1 Simulate 2 receive F-bit errors/multiframe (186 sec) 2 Simulate 2 receive M-bit errors/multiframe (186 sec) (DS-1 mode) Receive parity error/multiframe (133 sec) (ITU-T G.747 mode) 3 Simulate remote alarm 4 Simulate loss of frame (RED alarm timer) 5 Simulate AIS (AIS alarm timer) 6 Simulate receive loop command Copy DS2 Error Counters Only valid when D2RCFG.ECM is set to `0'. Values of DS2 background registers are copied to foreground. Background registers are NOT cleared. Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. C2C 0 No operation. 1 Copy background counters to foreground. Copy and Clear DS2 Error Counters Only valid when D2RCFG.ECM is set to `0'. Values of DS2 background registers are copied to foreground. Background registers are cleared. Data Sheet 299 05.2001 PEB 3456 E Register Description Command is self clearing and completes before next register access is possible i.e. software can write command and then immediately read the counters without starting a delay timer. Data Sheet 0 No operation. 1 Copy background counters to foreground. Clear background counters. 300 05.2001 PEB 3456 E Register Description D2RIMSK DS2 Receive Interrupt Mask Register Access : read/write Address : 22CH (PCI), 96H (Local bus) Reset Value : 003FH 15 0 5 0 0 0 0 0 0 0 0 0 4 3 2 1 0 LPCS AISS REDS RES RAS FAS This register provides the interrupt mask for DS2 status interrupts and DS2 loopback code interrupts. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One Interrupts" on Page 137. The following definition applies: 1 The corresponding interrupt vector will not be generated by the device. 0 The corresponding interrupt vector will be generated. LPCS Mask 'Loopback Code Status' (flagged in D2RLPCS) AISS Mask 'AIS State' REDS Mask 'Red Alarm State' RES Mask 'Reserved Bit' RAS Mask 'DS2 Remote Alarm State' FAS Mask 'DS2 Frame Alignment State' Data Sheet 301 05.2001 PEB 3456 E Register Description D2RSTAT DS2 Receive Status Register Access : read Address : 230H (PCI), 98H (Local bus) Reset Value : 0001H (Immediately after reset) : 0011H (After some clock cycles) : Depends on time register will be read after reset. : Status register will change after some clock cycles becaues REDS : (loss of frame alignment) will be set, because no signal is available. 15 0 5 0 0 0 0 0 0 0 0 0 4 3 2 1 0 AISS REDS RES RAS COFA FAS Each bit in the DS2 framer receive status register declares a specific condition dependent on the selected modes. The following convention applies to the individual bits: 0 The named status is not or no longer existing. 1 The named status is currently effective. The change of status bit can also be used to generate a DS2 interrupt vector. See also register D2RIMSK which describes how to enable/disable interrupt vector generation and refer to the description of DS2 framer interrupts on page "Layer One Interrupts" on Page 137. AISS DS2 AIS Alarm State (unframed all `1's pattern) AIS is considered valid in a multiframe when fewer than 5 zeros are detected. At 10-3 error rates, 1 zero per multiframe is typical. A valid DS2 signal without any bit errors has at least 5 zeros. The AIS flag nominally changes when the AIS condition is persistent as per alarm timing parameters defined in register D2RAP. The exact time necessary to change the flag could be greater in extremely high error rates. The AIS state is integrated by incrementing or decrementing a counter at the end of each multiframe depending on the AIS condition being valid or invalid respectively. REDS Data Sheet DS2 Red Alarm State (loss of frame alignment). 302 05.2001 PEB 3456 E Register Description The red alarm flag nominally changes when loss of frame alignment condition is persistent as per alarm timing parameters defined in register D2RAP. The exact time necessary to change the flag could be greater if the FAS flag is not constant because the frame alignment state is integrated by incrementing or decrementing a counter at the end of each multiframe when the FAS flag set or cleared respectively. Note that the framer's verification algorithm is designed to prevent a bouncing FAS flag. RES Reserved Bit This bit indicates the status of bit 3 in set II of ITU-T G.747 mode. Is it updated if the state persists for at least 8 multiframes. Reserved Bit changes are not reported when the DS2 framer is not aligned. RRA Remote Alarm This bit indicates that remote alarm is active. Changes are reported when they persist for at least 8 multiframes. In DS1 mode changes on Mx bit are reported, in ITU-T G.747 mode changes of bit 1 of set II are reported. Changes are not reported when the DS2 framer is not aligned. COFA Change of Frame Alignment. This bit indicates a change of frame alignment event. It is set when the DS2 framer found a new frame alignment and when the new frame position differs from the expected frame position. FAS Demultiplexer Loss of Frame Alignment This bit indicates that the DS2 framer is not aligned. Data Sheet 303 05.2001 PEB 3456 E Register Description D2RLPCS DS2 Receive Loopback Code Status Register Access : read Address : 234H (PCI), 9AH (Local bus) Reset Value : 0000H 15 0 3 0 LPCD(N) 0 0 0 0 0 0 0 0 0 0 0 LPCD(3:0) Loopback Command Detected LPCD(x) indicates that a loopback request was received. A loopback request for tributary x is indicated by inverting one of the 3 C-bits of the xth subframe. The C-bit is determined by D2TCFG.LPC. A command state change must persist for 5 contiguous multiframes before it will be reported. Data Sheet 0 No loopback code being received. 1 Loopback code being received. 304 05.2001 PEB 3456 E Register Description D2RFEC DS2 Receive Framing Bit Error Counters Access : read/write Address : 238H (PCI), 9CH (Local bus) Reset Value : 0000H 15 0 FE(15:0) FE(15:0) Framing Bit Errors Error counter mode (Clear on Read or Errored Second) depends on register D2RCFG.ECM. For DS1 mode framing bit errors include F-bit and M-bit errors. For G747 mode, individual bits in the Frame Alignment Signal (FAS) are counted. Errors are not counted in out of frame state. D2RPEC DS2 Receive Parity Bit Error Counter (ITU-T G.747) Access : read/write Address : 23CH (PCI), 9EH (Local bus) Reset Value : 0000H 15 0 PE(15:0) PE(15:0) Parity Errors in ITU-T G.747 mode Error counter mode (Clear on Read or Errored Second) depends on register D2RCFG.ECM. Errors are not counted in out of frame state. Data Sheet 305 05.2001 PEB 3456 E Register Description D2RAP DS2 Receive Alarm Timer Parameters Access : read/write Address : 240H (PCI), A0H (Local bus) Reset Value : 00H 15 0 0 AIS 0 0 0 0 0 0 7 6 AIS CM 5 0 CV(5:0) AIS criteria This bits sets the error rate for AIS detection. Declaration of AIS is specified by bits CM and CV. ITU-T G.747: 0 AIS condition is recognized when the alarm indication signal is received with less than 5 errors in each of 2 consecutive multiframes. 1 AIS condition is recognized when the alarm indication signal is received with less than 9 errors in each of 2 consecutive multiframes. M12 format: CM 0 AIS condition is recognized when the alarm indication signal is received with less than 3 errors in 3156 bits. 1 AIS condition is recognized when the alarm indication signal is received with less than 9 errors in 3156 bits. Counter Mode This bit selects the alarm timer mode. If counter mode is set to multiframes (`0') the value in CV determines the number of multiframes after which the TE3-CHATT declares AIS or RED. When counter mode is set to `1/2 milliseconds' (`1') the value in CV determines the time in CV x 0.5 ms after which AIS or RED is declared. Data Sheet 0 Multiframes. 1 1/2 Milliseconds. 306 05.2001 PEB 3456 E Register Description CV Counter Value Dependent on bit CM the counter value specifies the number of frames or the time in multiples of 0.5 milliseconds when AIS or RED is declared, i.e. setting CV to 20 and CM to `1' sets the alarm integration time to 10 milliseconds. 0..63 Counter Value. Data Sheet 307 05.2001 PEB 3456 E Register Description 8.9.3 Test Unit Registers TUTCFG Test Unit Transmit Configuration Register Access : read/write Address : 280H (PCI), C0H (Local bus) Reset Value : 0000H 15 0 13 0 INV 12 INV 8 6 FBT(4:0) 0 2 LEN(4:0) 1 0 ZS MD Invert output This bit enables inversion of the test unit output. Bit inversion is done after the zero suppression insertion point. FBT 0 No inversion 1 Invert pattern generator output Feedback Tap This bit field sets the feedback tap in pseudorandom pattern mode. PRBS shift register input bit 0 is XOR of shift register bits LEN and FBT. LEN Pattern Generator Length This bit field sets the pattern generator length to 1..32. ZS Enable Zero Suppression This bit enables zero suppression where a '1' bit is inserted at the output if the next 14 bits in the shift register are '0'. MD 0 No zero suppression 1 Zero suppression. Generator Mode This bit selects the generator mode of the test unit to be either PRBS or fixed pattern mode. Data Sheet 0 Pseudorandom Pattern (PRBS) 1 Fixed Pattern 308 05.2001 PEB 3456 E Register Description TUTCOM Test Unit Transmit Command Register Access : write Address : 284H (PCI), C2H (Local bus) Reset Value : 0000H 15 0 3 0 0 0 0 0 0 0 0 0 0 0 2 1 0 LDER IN1E STOP STRT Note: All commands are self clearing i.e. user does not have to clear command. The maximum command rate is limited by clock rate of unit under test and the associated synchronization process. Write interval should be > 4 transmit clock periods e.g. 2.6 s for T1 tributary test or 634 ns for T2 tributary test. LDER Load Error Rate Register This bit loads the value of the error rate register TUTEIR to the test unit transmitter. The command can be given while the transmitter is running. IN1E 0 No function. 1 Copy value of register TUTEIR to transmit clock region. Insert One Error in Output This bit enables a single error insertion in the next bit after command was written. STOP 0 No function 1 Single error insertion. Stop Pattern Generation. This bit stops the test unit transmitter. When stopped output becomes all '1'. Data Sheet 0 No function. 1 Stop pattern generation. 309 05.2001 PEB 3456 E Register Description STRT Load/Start Transmitter. This bit starts the test unit transmitter with the parameters defined in register TUTCFG. In fixed pattern mode the pattern needs to be programmed via register TUTFP0/1 prior to starting the transmitter. Data Sheet 0 No operation. 1 Load/Start test unit. 310 05.2001 PEB 3456 E Register Description TUTEIR Test Unit Transmit Error Insertion Rate Register Access : read/write Address : 288H (PCI), C4H (Local bus) Reset Value : 0000H 15 0 3 0 MTST 0 0 0 0 0 0 0 0 0 0 MTST 2 0 TXER(2:0) Manufacturing test. Must be written to `0' for normal operation. TXER Transmit Error Insertion Rate. This bit field determines the error insertion rate of the test unit transmitter. Data Sheet 000 No errors 001 10-1 (1 in 10) 010 10-2 (1 in 100) 011 10-3 (1 in 1 000) 100 10-4 (1 in 10 000) 101 10-5 (1 in 100 000) 110 10-6 (1 in 1 000 000) 111 10-7 (1 in 10 000 000) 311 05.2001 PEB 3456 E Register Description TUTFP0 Test Unit Transmit Fixed Pattern Low Word Access : read/write Address : 28CH (PCI), C6H (Local bus) Reset Value : 0000H 15 0 FP(15:0) FP Fixed Pattern Low Word See description below. TUTFP1 Test Unit Transmit Fixed Pattern High Word Access : read/write Address : 290H (PCI), C8H (Local bus) Reset Value : 0000H 15 0 FP(31:15) FP Fixed pattern High Word The 32 bit fixed pattern is distributed over two 16 bit registers and contains the pattern which is transmitted repetitively from bit FP(TUTCFG.LEN) down to FP(0) when test unit is operated in fixed pattern generator mode. Data Sheet 312 05.2001 PEB 3456 E Register Description TURCFG Test Unit Receive Configuration Register Access : read/write Address : 2A0H (PCI), D0H (Local bus) Reset Value : 0000H 15 AIM 13 0 AIM 12 DAS 8 6 FBT(4:0) 0 2 LEN(4:0) 1 0 ZS MD Auxiliary Interrupt Mode This bit field enables the auxiliary interrupt mask AIM of register TURIMSK. In normal operation and if not masked every status event generates an interrupt event. In auxiliary interrupt mode an individual status event generates one interrupt event and further status events of the same class, i.e. 'Bit Error Detected', are masked via an internal mask. This prevents excessive interrupt floods. See register TURIMSK for further details. DAS 0 Normal Operation 1 Auxiliary Interrupt Mode Disable Automatic Synchronization This bit disables automatic resynchronization in case of high bit error rates. If automatic resynchronization is enables the receiver automatically tries to resynchronize to the received test pattern. FBT 0 Enable automatic resynchronization. 1 Disable automatic resynchronization. Feedback Tap This bit field sets the feedback tap of the test unit synchronizer (receiver) in pseudorandom pattern mode. Next input to PRBS reference shift register (bit 0) is XOR of shift register bits LEN and FBT. LEN Reference shift register length This bit field sets the length of the receiver's test pattern register. Data Sheet 313 05.2001 PEB 3456 E Register Description ZS Enable Zero Suppression This bit enables zero suppression at the test unit receiver. A '1' is expected and inserted at the input if the next 14 bits in the shift register are set to '0'. MD 0 No zero suppression. 1 Enable zero suppression. Generator Mode This bit sets the generator mode of the test unit to either PRBS or fixed pattern. Data Sheet 0 Pseudorandom Pattern (PRBS) 1 Fixed Pattern 314 05.2001 PEB 3456 E Register Description TURCOM Test Unit Receive Command Register Access : write Address : 2A4H (PCI), D2H (Local bus) Reset Value : 0000H 15 0 4 0 0 0 0 0 0 0 0 0 0 3 2 1 0 RDF RDC CAIM STOP STRT Note: All commands are self clearing i.e. user does not have to clear command. The maximum command rate is limited by clock rate of unit under test and the associated synchronization process. Write interval should be > 4 transmit clock periods e.g. 2.6 s for T1 tributary test or 634 ns for DS2 tributary test. RDF Copy Receiver's 32 bit Pattern This bit loads the test units internal receiver pattern to register TURFP in fixed pattern mode. In synchrones state TURFP will be loaded with the pattern received. In asynchronous state TURFP with a 32-bit sample of the last received bit stream. RDC 0 No function. 1 Update register TURFP with synchronizer pattern. Copy bit counter and error counter This bit loads the test units internal bit counter and error counter to registers TURBC0,1 and TUREC0,1. CAIM 0 No function. 1 Copy counter. Clear Auxiliary Interrupt Masks. This bit resets the internal auxililiary mask. See TURCFG.AIM. STRT 0 no operation 1 clear auxiliary interrupts Start Receiver. This bit loads and starts the test unit receiver with the parameters defined in register TURCFG. Data Sheet 315 05.2001 PEB 3456 E Register Description Data Sheet 0 No operation. 1 Load/Start test unit receiver. 316 05.2001 PEB 3456 E Register Description TURERMI Test Unit Receive Error Measurement Interval Register Access : read/write Address : 2A8H (PCI), D4H (Local bus) Reset Value : 0000H 15 0 3 0 TST 0 0 0 0 0 0 0 0 0 0 TST 2 0 RXMI(2:0) Test Mode This bit enables measurement interval timer test. RXMI 0 Normal operation 1 Auto test of measurement interval function. End of Measurement interrupt should be asserted after approximately 4250 receive clock cycles (if enabled). The lower three bits of register FPAT should be "111". Receive Error Rate Measurement Interval This bit field defines the measurement interval in terms of input bits for measurement of receive bit error rate. At the end of the measurement window, contents of background error counter are automatically copied to foreground error counter and reset for next measurement interval. An interrupt can be generated at the end of each measurement interval. Data Sheet 000B Max measurement interval of 232-1 001B 103 bits 010B 104 bits 011B 105 bits 100B 106 bits 101B 107 bits 110B 108 bits 111B 109 bits 317 05.2001 PEB 3456 E Register Description TURIMSK Test Unit Receive Interrupt Mask Register Access : read/write Address : 2ACH (PCI), D6H (Local bus) Reset Value : 001FH 15 0 12 0 0 8 4 AIM(4:0) 0 0 0 3 2 1 0 ERXM BED ALL1 LOS SYN This register provides the interrupt masks for the test unit interrupts. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One Interrupts" on Page 137. The following definition applies: 1 The corresponding interrupt vector will not be generated by the device. 0 The corresponding interrupt vector will be generated. ERXM Mask 'End of Receive Error Rate Measurement' BED Mask 'Bit Error Detected' ALL1 Mask 'All `1' Pattern Received' LOS Mask 'Loss of Signal' SYN Mask 'Change in Receiver Synchronization State' AIM flags have same layout as the above five mask but are internal masks that are set automatically following the interrupt in the AIM mode. This mask prevents excessive bus load in error conditions. AIM flags are cleared by the TURCOM.CAIM command. They are "read only" flags in this register. Data Sheet 318 05.2001 PEB 3456 E Register Description TURSTAT Test Unit Receive Status Register Access : read Address : 2B0H (PCI), D8H (Local bus) Reset Value : 0021H 15 0 8 0 INV 0 0 0 0 0 7 INVS LA1 6 5 4 LA0 LOOS EMI 3 2 1 0 LBE A1 A0 OOS Inverted Pattern This bit indicates that the received PRBS sequence is inverted. LA1 0 Not Inverted. 1 Inverted. Latched 'Input all '1'' This bit indicates that the condition 'Input all '1'' was active since last status register read. LA0 Latched 'Input all '0'' This bit indicates that the condition 'Input all '0'' was active since last status register read. LOOS Latched Out of Synchronization This bit indicates that the receiver was out of synchronization since last status register read. EMI End of Measurement Interval This bit indicates that the end of the measurement internal was reached since last read of error counter or that command TURCMD.RDC was given. The results of the bit error rate test are available in register TURBC0,1 and TUREC0,1. This flag is cleared when the error counter is read. Counters will not be overwritten while EMI is '1'. LBE Latched Bit Error Detected Flag This bit indicates that at least '1' one bit error occurred since last read of this register. It is cleared by status register read. A1 Input all `1's This bit indicates that the input contained all '1' during the last 32 bits. It is reset if at least one '0' occurs in 32 bits. Data Sheet 319 05.2001 PEB 3456 E Register Description A0 Input all `0's This bit indicates that the input contained all '0' during the last 32 bits. It is reset if at least one '1' occurs in 32 bits. OOS Receiver Out of Synchronization This bit indicates the status of the test unit synchronizer. Data Sheet 320 05.2001 PEB 3456 E Register Description TURBC0 Test Unit Receive Bit Counter Low Word Access : read Address : 2B4H (PCI), DAH (Local bus) Reset Value : 0000H 15 0 BC(15:0) BC(31:0) Bit Counter See description below. TURBC1 Test Unit Receive Bit Counter High Word Access : read Address : 2B8H (PCI), DCH (Local bus) Reset Value : 0000H 15 0 BC(31:16) BC(31:0) Bit Counter BC is a 32 bit counter which is split between two 16 bits registers. It counts receive clock slots when the receiver is enabled. Bits are counted in a background register which is not directly readable. The values are transferred to the two 16 bit foreground (readable) registers and cleared in one of the two ways: 1. Assert command TURCOM.RDC. 2. Automatically at end of measurement interval. The background register is transferred to the foreground register and cleared in the same way as the bit error counter (see previous section). Data Sheet 321 05.2001 PEB 3456 E Register Description When the error registers are read in response to the "End of Measurement Interval" interrupt vector , reading this register is not necessary because the measurement interval would be known. However the user could assert command TURCOM.RDC to terminate the measurement interval early and transfer the current bit error count and bit count to the foreground registers (polling mode). Data Sheet 322 05.2001 PEB 3456 E Register Description TUREC0 Test Unit Receive Error Counter Low Word Access : read Address : 2BCH (PCI), DEH (Local bus) Reset Value : 0000H 15 0 EC(15:0) EC(31:0) Error Counter See description below. TUREC1 Test Unit Receive Error Counter High Word Access : read Address : 2C0H (PCI), E0H (Local bus) Reset Value : 0000H 15 0 EC(31:16) EC(31:0) Error Counter This 32 bit counter counts receive errors detected when receiver is enabled and in synchronized state. When the 'Bit Error Detected' interrupt is enabled, it will be asserted and then automatically masked when this counter is incremented. Errors are counted in a background register (not directly readable) until: 1. The user asserts command TURCOM.RDC. 2. The end of measurement interval is reached and the last result was read. In both cases the value of the background register is copied to TUREC.EC and the measured values are accessible. An 'End of Data Sheet 323 05.2001 PEB 3456 E Register Description Receive Error Rate Measurement' interrupt vector is optionally generated. Data Sheet 324 05.2001 PEB 3456 E Register Description TURFP0 Test Unit Receive Fixed Pattern Low Word Access : read Address : 2C4H (PCI), E2H (Local bus) Reset Value : 0000H 15 0 FP(15:0) FP(31:0) Fixed pattern See description below. TURFP1 Test Unit Receive Fixed Pattern High Word Access : read Address : 2C8H (PCI), E4H (Local bus) Reset Value : 0000H 15 0 FP(31:16) FP(31:0) Fixed Pattern This 32 bit field is distributed over two 16 bit registers and is used in the fixed pattern mode (TURCFG.MD='1'). The TURCOM.RDF command will copy the current state of the receiver's 32 bit pattern generator to this register. If the receiver is synchronized, bits FP(TURCFG.LEN:0) contain the fixed pattern being received. Bit 0 is the most recently received. If not synchronized, the register contains a 32 bit sample of input data. Data Sheet 325 05.2001 PEB 3456 E Register Description 8.9.4 Transmit Framer Register TCMDR T1/E1 Transmit Command Register Access : read/write Address : 00H Reset Value : 0000H 15 0 5 0 XAP 0 0 0 0 0 0 0 0 4 3 2 XAP XPRBS XAIS XRA 1 0 XLU XLD Transmit Auxiliary Pattern This bit enables transmission of auxiliary pattern in the outgoing bit stream. The auxiliary pattern is defined as a continuous pattern of `01'. XPRBS 0 Disable transmission of auxiliary pattern. 1 Enable transmission of auxiliary pattern. This function is not available if bit XAIS is set to `1'. Transmit PRBS This bit enables the transmission of the pseudo-random bit sequence defined in register TPRBSC. XAIS 0 Disable transmission of PRBS. 1 Enable transmission of PRBS. Transmit AIS This bit enables transmission of alarm indication signal towards the remote end. AIS is an all one unframed signal. Data Sheet 0 Disable transmission of AIS. 1 Enable transmission of AIS. 326 05.2001 PEB 3456 E Register Description XRA Transmit Remote Alarm (Yellow Alarm) This bit enables the transmission of remote alarm in the outgoing bit stream. Clearing the bit will remove the remote alarm pattern. T1 0 Disable transmission of remote alarm. 1 Enable transmission of remote alarm. Remote alarm pattern is selected via register FMR.SRAF. E1 XLU XLD Data Sheet 0 Disable transmission of remote alarm. 1 Set A-bit in transmitted service word. Transmit Line Loopback Actuate (Up) Code 0 Normal operation. 1 A one in this bit position will cause the transmitter to replace normal transmit data with the line loopback actuate code continuously until this bit is reset. The line loopback actuate code will be optionally overwritten by the framing/DL/CRC bits. Transmit Line Loopback Deactuate (Down) Code 0 Normal operation. 1 A one in this bit position will cause the transmitter to replace normal transmit data with the line loopback deactuate code continuously until this bit is reset. The line loopback deactuate code will be optionally overwritten by the framing/DL/CRC bits. 327 05.2001 PEB 3456 E Register Description TFMR T1/E1 Transmit Mode Register Access : read/write Address : 01H Reset Value : 0000H 15 0 5 0 XAS 0 0 0 0 0 0 0 0 4 3 2 XAS AXRA SRAF T1E1 1 0 FM(1:0) Automatic Spare Bit Insertion E1: CRC-4 Multiframe AXRA 0 Normal operation. Content of register XSP.XS13 and XSP.XS15 is inserted in the E-Bit of time slot 0 in frame 13 and frame 15 respectively. 1 Submultiframe status will be automatically set in the outgoing data stream. Each received, errored submultiframe causes bit one of time slot 0 of frame 13 and frame 15 to be `0'. Otherwise these bits are set to `1'. Automatic Transmit Remote Alarm Setting this bit enables automatic transmission of remote alarm. Data Sheet 0 Normal operation. 1 The Remote Alarm (yellow alarm) bit will be automatically set in the outgoing data stream if the receiver is in asynchronous state (FRS.LFA bit is set). In synchronous state the remote alarm bit will be reset. 328 05.2001 PEB 3456 E Register Description SRAF Select Remote (Yellow) Alarm Format Setting this bit enables the remote alarm format in T1 mode. This bit has no function in E1 mode. T1: F4 1 Bit 2 = 0 in every channel T1: F12 0 FS bit of frame 12. 1 Bit 2 = 0 in every channel. T1: ESF T1E1 0 Pattern `1111 1111 0000 0000...' in data link channel. 1 Bit 2 = 0 in every channel. T1/E1 mode selection This bit switches the transmit framer into T1 and E1 mode. FM 0 Select T1 mode. 1 Select E1 mode. Select Frame Mode This bit field determines the framing mode of the transmit framer. T1 00B Select ESF format. 01B Select F12 format. 10B Select F4 format. Other Reserved E1 00B Select Double frame format. 01B Select CRC-4 multiframe format. Other Reserved Data Sheet 329 05.2001 PEB 3456 E Register Description TLCR0 T1/E1 Transmit Loop Code Register 0 Access : read/write Address : 02H Reset Value : 0000H 15 14 FLLB LCS FLLB 9 0 0 0 0 8 1 LDCL(1:0) 0 0 0 0 0 0 0 LACL(1:0) Disable Framed Line Loopback This bit switches between framed and unframed transmission of line loopback. In unframed transmission the FS/DL bit the line loopback code overwrites the FS/DL bits, while in framed transmission the FS/DL bits will not be overwritten by the line loopback code. LCS 0 Set framed line loopback transmission. 1 Set unframed line loopback transmission. Loop Code Select This bit switches between line loopback code defined in ANSI T1.403 or a user definable loopback code defined in register TLCR1. LDCL 0 Select ANSI codes. 1 Select line loopback code defined in register TLCR1. Line Loopback Deactuate Code Length This bit field determines the length of the line loopback deactuate code specified in register TLCR1. The length of the loopback code can be specified in a range of 5 to 8 bits. 00B..11BSpecifies code length in the range of 5 to 8 bits. LACL Line Loopback Actuate Code Length (5-8 bit) This bit field determines the length of the line loopback actuate code specified in register TLCR1. The length of the loopback code can be specified in a range of 5 to 8 bits. 00B..11BSpecifies code length in the range of 5 to 8 bits. Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write 001001 to TLCR1 register and define code length of 6 bits. Data Sheet 330 05.2001 PEB 3456 E Register Description TLCR1 T1/E1 Transmit Loop Code Register 1 Access : read/write Address : 03H Reset Value : 0000H 15 8 7 LDC(7:0) LDC 0 LAC(7:0) Line Loopback Deactuate Code This bit field is sent in the outgoing bit stream if enabled via bit TCMDR.XLD and TLCR0.LCS. Note: Most significant bit is sent first. E.g. TCLR0.LDCL = 01B specifies code length to be six bits long. In this case LDC(5) is sent first. LAC Line Loopback Actuate Code This bit field is sent in the outgoing bit stream if enabled via bit TCMDR.XLU and TLCR0.LCS. Note: Most significant bit is sent first. E.g. TCLR0.LACL = 01B specifies code length to be six bits long. In this case LAC(5) is sent first. Data Sheet 331 05.2001 PEB 3456 E Register Description TPRBSC T1/E1 Transmit PRBS Control Register Access : read/write Address : 04H Reset Value : 001FH 15 FPRBS 12 0 FPRBS 0 IPRBS 9 0 0 8 4 PRP(1:0) 0 0 0 0 FPL(4:0) Framed PRBS This bit field enables framed or unframed transmission of the pseudorandom bit sequence. IPRBS 0 Transmit framed PRBS. 1 Transmit unframed PRBS. Invert PRBS This bit field enables inversion of the pseudo-random bit sequence in transmit direction. PRP 0 PRBS is not inverted. 1 PRBS is inverted. Pseudo-Random Pattern This bit field determines the generator polynomial for the pseudorandom bit sequence. FPL 00B PRBS is generated according to 215 -1 (ITU-T O. 151) 01B PRBS is generated according to 220 -1 (ITU-T O. 151) 1-B For PRBS the fixed pattern, defined in TFPR0 and TFPR1, is selected. Fixed Pattern Length This bit field sets the length of the fixed pattern FP which is located in register TFPR0 and TFPR1. E.g.: FPL(4:0) = 10010B means pattern length is equal to 19, which implies that the bits FP(18)..FP(0) form the PRBS. Data Sheet 332 05.2001 PEB 3456 E Register Description TFPR0 T1/E1 Transmit Fixed Pattern Register Low Word Access : read/write Address : 05H Reset Value : 0000H 15 0 FP(15:0) FP(31:0) Fixed Pattern Low Bytes See description below. TFPR1 T1/E1 Transmit Framer Fixed Pattern Register High Word Access : read/write Address : 06H Reset Value : 0000H 15 0 FP(31:16) FP(31:0) Fixed Pattern High Bytes This bit field together with bit field TFPR0.FP defines a bit sequence, which can be sent instead of a pseudo-random bit sequence. FP is sent in the order FP(TPRBSC.FPL-1) down to FP(0) and will be repeated until deactivated. Data Sheet 333 05.2001 PEB 3456 E Register Description TPTSL0 T1/E1 Transmit PRBS Time Slot Number Register Low Word Access : read/write Address : 07H Reset Value : FFFFH 15 0 TSL(15:0) TSL(31:0) Time slot 15..0 Select See description below. TPTSL1 T1/E1 Transmit PRBS Time Slot Number Register High Word Access : read/write Address : 08H Reset Value : 00FFH 15 0 TSL(31:16) TSL(31:0) Time slot 31..16 Select Selected bits in bit field TSL and TPTSL0.TSL determine those time slots, which are used for PRBS generation. Time slots can be programmed arbitrarily. E.g. if TPTSL0.TSL(1) and TPTSL0.TSL(2) are set to `1', the PRBS is sent continuously over both time slots combined. Data Sheet 334 05.2001 PEB 3456 E Register Description XSP T1/E1 Transmit Spare Bit Register Access : read/write Address : 09H Reset Value : 0000H 15 0 1 0 XS13, XS15 0 0 0 0 0 0 0 0 0 0 0 0 0 XS13 XS15 Transmit Spare Bit E1: CRC-4 Multiframe Dependent on bit FMR.XAS and framer mode spare bits of service word in CRC-4 multiframe 13 and 15 are replaced by XS13 and XS15. Data Sheet 335 05.2001 PEB 3456 E Register Description 8.9.5 Receive Framer Registers RCMDR T1/E1 Receive Command Register Access : read/write Address : 00H Reset Value : 0000H 15 0 5 0 SIM 0 0 0 0 0 0 0 0 0 4 1 SIM(3:0) 0 FRS Alarm Simulation This bit field enables alarm simulation in the receive framer. See codes for specific function. 0000B Disable alarm simulation. 0001B Simulate loss of signal Setting this code: - Generate 'Loss of Signal Status' interrupt vector. - Flag 'Loss of Signal' via bit FSR.LOS. - Generate PDEN interrupt vector. - Flag 'Pulse Density Code Violation Detected' via bit FSR.PDEN/ AUX. Removing this code: - Generate 'Loss of Signal Status' interrupt vector. - Remove signalling of 'Loss of Signal'. - Generate PDEN interrupt vector. - Remove signalling of 'Pulse Density Code Violation Detected'. 0010B Simulate Alarm Indication Signal Setting this code: - Generate 'Loss of Frame Alignment' interrupt vector. - Flag 'Loss of Frame Alignment' via bit FRS.LFA. - Generate 'Alarm Indication Signalled' interrupt vector. - Flag 'Alarm Indication Signalled' via bit FRS.AIS. Data Sheet 336 05.2001 PEB 3456 E Register Description Removing this code: - Generate 'Loss of Frame Alignment Status' interrupt vector. - Remove signalling of 'Loss of Frame Alignment'. - Generate 'Alarm Indication Signal Status' interrupt vector. - Remove signalling of 'Alarm Indication Signalled'. 0011B Simulate auxiliary pattern ('...010101...' pattern) This sequence simulates also loss of frame (required for auxiliary pattern). Setting this code: - Generate 'Auxiliary Pattern Status' interrupt vector. - Generate 'Loss of Frame Alignment Status' interrupt vector. - Flag 'Loss of Signal' via bit FRS.LFA. - Flag 'Auxiliary Pattern detected' via bit FRS.PDEN/AUX. - Flag 'Loss of Multiframe Alignment' via bit FRS.LMFA (CRC-4 Multiframe mode). - Increment framing error counter by 3 or 4 depending on RFMR.SSP Removing this code: - Generate 'Auxiliary pattern Status' interrupt vector. - Generate 'Loss of Frame Alignment Status' interrupt vector. - Remove signalling of 'Loss of Frame Alignment'. - Remove signalling of FRS.PDEN/AUX. - Remove signalling of 'Loss of Multiframe Alignment'. 0100B Simulate loss of frame Setting this code: - Generate 'Loss of Frame Alignment Status' interrupt vector. - Flag 'Loss of Signal' via bit FRS.LFA. - Flag 'Loss of Multiframe Alignment' via bit FRS.LMFA (CRC-4 multiframe mode). - Increment framing error counter by 2, 3, or 4 (depends on RFMR.SSP). - Increment errored seconds (T1 mode only). Removing this code: - Generate 'Loss of Frame Alignment Status' interrupt vector. - Remove signalling of 'Loss of Frame Alignment'. - Remove signalling of 'Loss of Multiframe Alignment'. Data Sheet 337 05.2001 PEB 3456 E Register Description 0101B Simulate remote alarm Setting this code: - Generate 'Remote Alarm Status' interrupt vector. - Flag 'Received Remote Alarm' bit FRS.RRA. Removing this code: - Generate 'Remote Alarm Status' interrupt vector. - Remove signalling of 'Receive Remote Alarm'. 0110B Simulate CRC error (T1 ESF or E1 CRC-4 multiframe mode) Setting this code: - Generate CRC interrupt vector. - Increment CRC error counter. Removing this code: - Stop generation of CRC interrupt vector. - Stop increment of CRC error counter. FRS Force Resynchronization A transition from low to high will force the frame aligner to execute a resynchronization of the pulse frame. The procedure depends on the status of bit FMR.SSP. Data Sheet 0 No operation. 1 Change from '0' to '1' forces resynchronization. 338 05.2001 PEB 3456 E Register Description RFMR T1/E1 Receive Mode Register Access : read/write Address : 01H Reset Value : 0000H 15 0 11 0 LOSR 0 0 10 9 8 7 LOSR ALMF RRAM AIS3 SSP 6 5 SSC(1:0) 3 0 2 SRAF T1E1 1 0 FM(1:0) Loss of Signal Recovery This bit sets the conditions for 'Loss of Signal' detection. T1 0 Loss of signal cleared, when pulse density defined by register PCR is detected during a time interval declared by register PCD. 1 Loss of signal cleared, when pulse frame density defined by register PCR is detected during a time interval declared by register PCD and a pulse density of at least N `1's in every N+1 octets (0<N<24) during recovery interval defined in register PCD is detected. E1 ALMF 0 Loss of signal cleared, when pulse density defined by register PCR is detected during a time interval declared by register PCD. 1 No function. Automatic Loss of Multiframe This bit selects condition for automatic loss of multiframe. T1 0 CRC errors do not cause loss of frame alignment. 1 320 or more CRC errors in one second cause loss of frame alignment. E1 Data Sheet 0 CRC errors do not cause loss of frame alignment. 1 915 or more CRC-4 errors in one second cause loss of frame alignment. 339 05.2001 PEB 3456 E Register Description RRAM Receive Remote Alarm Mode The conditions for remote (yellow) alarm detection can be selected via this bit to allow detection even in the presence of BER 10-3. Remote alarm detection is flagged in register FRS.RRA and can be signalled as an interrupt. T1: F4 0 Normal operation Detection: Bit 2 = `0' in every speech channel per frame. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection with BER 10-3 Detection: Bit 2 = `0' in 255 consecutive speech channels. Release: The alarm will be reset when receiver does not detect the Bit 2 = '0' condition for three consecutive pulseframes. T1: F12 0 Normal operation Depending on bit FMR0.SRAF: 0 Detection: FS-bit of frame 12 is forced to `1'. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection: Bit 2 = `0' in every speech channel per frame. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection with BER 10-3 Remote alarm detection depending on bit FMR0.SRAF: 0 Detection: FS-bit of frame 12 is forced to `1'. Release: The alarm will be reset when receiver does not detect the 'Fs-bit' condition for three consecutive multiframes. Data Sheet 340 05.2001 PEB 3456 E Register Description 1 Detection: Bit 2 = `0' in 255 consecutive speech channels. Release: The alarm will be reset when receiver does not detect the Bit 2 = '0' condition for three consecutive pulseframes. T1: ESF 0 Normal operation Remote alarm detection depending on bit FMR0.SRAF: 0 Detection Pattern `1111 1111 0000 0000...' in data link channel. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection: Bit 2 = `0' in every speech channel per frame. Release: The alarm will be reset when above conditions are no longer detected. 1 Detection with BER 10-3 Remote alarm detection depending on bit FMR0.SRAF: 0 Detection Pattern `1111 1111 0000 0000...' in data link channel. Release: The alarm will be reset when receiver does not detect `DL pattern' for three times in a row. 1 Detection: Bit 2 = `0' in 255 consecutive speech channels. Release: The alarm will be reset when receiver does not detect the Bit 2 = '0' condition for three consecutive pulseframes. AIS3 Select AIS Condition This bit selects the condition which leads to AIS reporting. T1: F4, F12 Data Sheet 0 AIS (blue alarm) is indicated, when two or less zeros in the received bit stream are detected in a time interval of 12 frames. 1 AIS (blue alarm) detection is only enabled, when framer is in asynchronous state. The alarm is indicated, when three or less 341 05.2001 PEB 3456 E Register Description zeros within a time interval of 12 frames are detected in the received bit stream. T1: ESF SSP 0 AIS (blue alarm) is indicated, when two or less zeros in the received bit stream are detected in a time interval of 24 frames. 1 AIS (blue alarm) detection is only enabled, when framer is in asynchronous state. The alarm is indicated, when five or less zeros within a time interval of 24 frames are detected in the received bit stream. Select Synchronization/Resynchronization Procedure T1: F12 0 Specified number of errors in FT framing or specified number of errors in FS framing leads to loss of synchronization (FRS.LFA). In the case of FS bit framing errors, bit FRS.LMFA is set additionally. A complete new synchronization procedure is initiated to regain pulseframe alignment and then multiframe alignment. 1 Specified number of errors in FT framing has the same effect as above. Specified number of errors in FS framing only initiates a new search for multiframe alignment without influencing pulseframe synchronous state (FRS.LMFA is set). T1: ESF SSC 0 Synchronization is achieved only on verification of the framing pattern. 1 Synchronous state is reached when framing pattern and CRC-6 checksum are correctly found. Select Synchronization Conditions T1 Loss of Frame Alignment (FRS.LFA or opt. FRS.LMFA) is declared if 00B 01B 10B 11B 2 out of 4 framing bits 2 out of 5 framing bits F12 2 out of 6 framing bits ESF 2 out of 6 framing bits per multiframe period 4 consecutive incorrect multiframe pattern It depends on the selected multiframe format and optionally on bit FMR.SSP which framing bits are observed: Data Sheet 342 05.2001 PEB 3456 E Register Description F12 SSP = 0: FT bits FRS.LFA: FS bits FRS.LFA and FRS.LMFA SSP = 1:FT FRS.LFA FS FRS.LMFA ESF ESF framing bits FRS.LFA E1 00B 01B 10B 11B SRAF 3 out of 4 consecutive FAS or service word errors 4 out of 4 consecutive FAS or service word errors 3 out of 3 FAS errors 4 out of 4 FAS errors Select Remote (Yellow) Alarm Format This bit is valid for T1 mode only. T1: F4 0/1 Bit 2 = `0' in every channel. T1: F12 0 FS bit of frame 12. 1 Bit 2 = `0' in every channel. T1: ESF T1E1 0 Pattern `1111 1111 0000 0000...' in data link channel. 1 Bit 2 = `0' in every channel. T1/E1 Mode Selection This bit switches the receive framer into T1 or E1 mode. FM 0 Select T1 mode. 1 Select E1 mode. Select Frame Mode This bit field selects the framing mode of the receive framer. T1 00B ESF-Format 01B F12-Format 10B F4-Format Other Reserved E1 00B Doubleframe 01B CRC-4 10B CRC-4 Interworking mode Other Reserved Data Sheet 343 05.2001 PEB 3456 E Register Description RLCR0 T1/E1 Receive Loop Code Register 0 Access : read/write Address : 02H Reset Value : 0000H 15 14 0 LCS LCS 9 0 0 0 0 8 1 LDCL(1:0) 0 0 0 0 0 0 0 LACL(1:0) Loop Code Select This bit switches between line loopback code defined in ANSI T1.403 or a user definable loopback code defined in register RLCR1. LDCL 0 Select ANSI codes. 1 Select line loopback code defined in register RLCR1. Line Loopback Deactuate Code Length This bit field determines the length of the line loopback deactuate code specified in register TLCR1. The length of the loopback code can be specified in a range of 5 to 8 bits. 00B..11BSpecifies code length in the range of 5 to 8 bits. LACL Line Loopback Actuate Code Length (5-8 bit) This bit field determines the length of the line loopback actuate code specified in register TLCR1. The length of the loopback code can be specified in a range of 5 to 8 bits. 00B..11BSpecifies code length in the range of 5 to 8 bits. Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write 001001 to LCR1 register and define code length of 6 bits. Data Sheet 344 05.2001 PEB 3456 E Register Description RLCR1 T1/E1 Receive Loop Code Register 1 Access : read/write Address : 03H Reset Value : 0000H 15 8 7 LDC(7:0) LDC 0 LAC(7:0) Line Loopback Deactuate Code This incoming bit stream will be compared against this bit field if enabled via bit RLCR0.LCS. Note: Most significant bit is sent first. E.g. TCLR0.LDCL = 01B specifies code length to be six bits long. In this case LDC(5) is sent first. LAC Line Loopback Actuate Code This incoming bit stream will be compared against this bit field if enabled via bit RLCR0.LCS. Note: Most significant bit is sent first. E.g. TCLR0.LACL = 01B specifies code length to be six bits long. In this case LAC(5) is sent first. Data Sheet 345 05.2001 PEB 3456 E Register Description RPRBSC T1/E1 Receive PRBS Control Register Access : read/write Address : 04H Reset Value : 001FH 15 0 13 0 EPRM 9 EPRM 0 0 0 8 4 PRP(1:0) 0 0 0 0 FPL(4:0) Enable PRBS Monitor This bit enables the PRBS monitoring function. When PRBS monitor is enabled the pseudo-random pattern synchronizer logs onto the pseudo-random pattern defined in PRB. PRP 0 PRBS monitor is disabled. 1 PRBS monitor is enabled. Pseudo-Random Pattern 00B The incoming pattern is compared according to 215 -1 (ITU-T O.151) 01B The incoming pattern is compared according to 220 -1 (ITU-T O.151) 11B The incoming pattern is compared to the fixed pattern, defined in RFPR0 and RFPR1. The pattern length is defined in FPL. Other Reserved FPL Data Sheet Fixed Pattern Length, e.g.: =10010 means pattern length is equal to 19, which implies that the bits RFPR1/0.FP(18)..FP(0) form the PRBS. 346 05.2001 PEB 3456 E Register Description RFPR0 T1/E1 Receive Fixed Pattern Register Low Word Access : read/write Address : 05H Reset Value : 0000H 15 0 FP(15:0) FP Fixed Pattern Low Bytes See description below. RFPR1 T1/E1 Receive Fixed Pattern Register High Word Access : read/write Address : 06H Reset Value : 0000H 15 0 FP(31:16) FP Fixed Pattern High Bytes This bit field together with RFPR0.FP defines a bit sequence, which will be monitored in the PRBS synchronous state. FP is compared in the order FP(RPRBSC.FPL-1) down to FP(0) and comparison will be repeated until deactivated. Data Sheet 347 05.2001 PEB 3456 E Register Description RPTSL0 T1/E1 Receive PRBS Time Slot Number Register Low Word Access : read/write Address : 07H Reset Value : FFFFH 15 0 TSL(15:0) TSL Time slot 15..0 Select See description below. RPTSL1 T1/E1 Receive PRBS Time Slot Number Register High Word Access : read/write Address : 08H Reset Value : 00FFH 15 0 TSL(23:16) TSL Time slot 31..16 Select Selected bits in bit field TSL and RPTSL0.TSL determine those time slots, which are used for PRBS monitoring. Time slots can be programmed arbitrarily. E.g. if RPTSL0.TSL(1) and RPTSL0.TSL(2) are set to `1', the PRBS is monitored continuously over both time slots combined. Data Sheet 348 05.2001 PEB 3456 E Register Description IMR T1/E1 Receive Interrupt Mask Register Access : read/write Address : 09H Reset Value : 0000H 15 0 11 0 0 0 10 T400 CRC 9 8 7 6 5 4 PDEN FAS MFAS AISS LOSS RAS /AUX 3 ES 2 1 0 SEC LLBS PRBSS For each framer interrupt vector an interrupt vector generation mask is provided. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One Interrupts" on Page 137. The following definition applies: 1 The corresponding interrupt vector is suppressed by the device. 0 The corresponding interrupt vector is generated. T400 Mask '400 millisecond Timer' CRC Mask 'CRC Error' PDEN/AUX Mask 'Pulse Density / Auxiliary Pattern' FAS Mask 'Frame Alignment Status' MFAS Mask 'Multiframe Alignment Status' AIS Mask 'Alarm Indication Status' LOSS Mask 'Loss of Signal Status' RAS Mask 'Remote Alarm Status' ES Mask 'Errored Second' SEC Mask 'One Second Tick' LLBS Mask 'Line Loopback Status' PRBSS Mask 'PRBS Status' Data Sheet 349 05.2001 PEB 3456 E Register Description RFMR1 T1/E1 Receive Mode Register 1 Access : read/write Address : 0AH Reset Value : 0000H 15 0 4 0 FRST 0 0 0 0 0 0 0 0 0 2 FRST(2:0) 1 0 EACM ECM Force Resynchronization Timer This bit field defines the time after which the framer automatically starts resynchronization if Emulator Automatic Check Mode is enabled. 0..7 EACM Automatic resynchronization after (FRST+1)*8 milliseconds. Enable Emulator Automatic Check Mode This bit enables automatic resynchronization mode. After loss of frame the receive framer starts resynchronization after (FRST+1)*8ms when frame search is not started by system software. If EACM is disabled system software has to force resynchronization by setting bit RCMDR.FRS. ECM Data Sheet Error Counter Mode 0 Unbuffered error counter mode. Counters are updated when respective error occurs. Counter registers are directly readable and cleared automatically at the end of a read cycle. 1 Buffered error counter mode. Actual error counts are hidden from user and updated in background. The counter is copied to the bus register at one second intervals and reset automatically. This operation is synchronous with the periodic one second interrupt which alerts software to read the register. 350 05.2001 PEB 3456 E Register Description PCD T1/E1 Receive Pulse Count Detection Register Access : read/write Address : 0BH Reset Value : 0015H 15 0 5 0 PCD 0 0 0 0 0 0 0 0 0 PCD(5:0) Pulse Count Detection A 'Loss of Signal' alarm will be detected, if the incoming data stream has zero octets for a programmable number T of consecutive octets. The number T is programmable via the PCD register and can be calculated as follows: T = 8*(PCD+1), 1 PCD 63. E.g. PCD = 21 sets loss of signal threshold to 176 (=(21+1)*8) zeros. Note: For T1 mode time detection interval has cumulative uncertainty of 1 per 193 clocks. Data Sheet 351 05.2001 PEB 3456 E Register Description PCR T1/E1 Receive Pulse Count Recovery Register Access : read/write Address : 0CH Reset Value : 0015H 15 0 5 0 PCR 0 0 0 0 0 0 0 0 0 PCR(5:0) Pulse Count Recovery 'Loss of Signal' alarm will be cleared, when a programmable pulse density is detected in the received bit stream. A pulse is a logical '1' in the received bit stream. The number of pulses M which must occur in a certain time interval, which is programmable via register PCR, can be calculated as follows: M = PCR, 1 PCR 63. Additional 'Loss of Signal' recovery condition may be selected by using RFMR.LOSR. Data Sheet 352 05.2001 PEB 3456 E Register Description FRS T1/E1 Receive Status Register Access : read/write Address : 40H Reset Value : 0000H 15 0 14 13 NMF LOS 12 11 AIS LFA 10 9 8 3 RRA LMFA FSRF 0 0 0 0 2 1 0 PDEN LLBDD LLBAD PRBS AUX Each bit in the framer receive status register declares a specific condition dependent on the selected modes. The following convention applies to the individual bits: 0 The named status is not or no longer existing. 1 The named status is currently effective. The change of status bit (except FSRF) can also be used to generate a framer interrupt vector. See also register IMR which describes how to enable/disable interrupt vector generation and refer to the description of framer interrupt vector on page "Layer One Interrupts" on Page 137. NMF No Multiframe Found E1: CRC-4 Interworking This bit is set, if no multiframe is found after 400 milliseconds. LOS Loss of Signal (Red Alarm) This bit is set, when the 'Loss of Signal' condition has been detected. T1 Detection An alarm will be generated if the incoming data stream remain at logical zero for 168 cycles. Recovery The recovery procedure starts after detecting a logical 1. The LOS alarm is cleared if 21 one's are detected within 168 bits (12.5%). E1 see T1 and "Error Performance Monitoring and Alarm Handling" on Page 98. Data Sheet 353 05.2001 PEB 3456 E Register Description AIS Alarm Indication Signal (AIS) This bit is set, when the alarm indication condition defined by bit RFMR.AIS3 has been detected. The flag stays active for at least one multiframe. It will be reset with the beginning of the next following multiframe, if no alarm condition is detected. LFA Loss of Frame Alignment T1 This bit is set, when the 'Loss of Frame Alignment' condition defined by bits RFMR.SSP and RFMR.SSC has been detected. The flag is cleared, when synchronization has been regained. E1 This bit is set, when the 'Loss of Frame Alignment' condition defined by bit RFMR.SSC has been detected. The flag is cleared, when synchronization has been regained. RRA Received Remote Alarm (Yellow Alarm) Condition for receive remote alarm is defined by bit FMR.RRAM. The flag is set after detecting remote alarm (yellow alarm). LMFA Loss of Multiframe Alignment T1: F12 This bit is set, when the condition for 'Loss of Multiframe Alignment' defined by bit RFMR.SSC has been detected. The flag is cleared after multiframe synchronization has been regained. E1: CRC-4 Multiframe, CRC-4 Interworking This bit is set in CRC-4 multiframe or CRC-4 interworking mode, when double frame alignment is lost. This bit is reset, when the multiframe pattern is acquired or after 400 milliseconds in CRC-4 interworking mode, when NMF is asserted. FSRF Frame Search Restart Flag This bit toggles on each new pulse frame search started. This function can be used to recognize multiple candidates. If FSRF does not toggle, but LFA and LMFA remain active, the synchronizer has multiple candidates and cannot determine which one is correct. Note: This flag can not be used to generate an interrupt vector. Data Sheet 354 05.2001 PEB 3456 E Register Description PDEN/AUX T1 Pulse Density Code Violation Detected This bit is set, when the pulse density of the received data stream is below the requirement defined by ANSI T1.403. E1 Auxiliary Pattern Detected This bit is set, when the pattern '...010101...' has been detected concurrent with loss of frame. LLBDD Line Loop-Back Deactuation Signal Detected This bit is set, when line loopback deactuate signal is detected and then received over a period of more than 33,16ms with a bit error rate less than 1/100. The bit remains set as long as the bit error rate does not exceed 1/100. If framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. If frame alignment state is not synchronized, all received data bits are searched for the LLBD pattern. LLBAD Line Loop-Back Actuation Signal Detected This bit is set to one in case the LLB actuate signal is detected and then received over a period of more than 33,16ms with a bit error rate less than 1/100. The bit remains set as long as the bit error rate does not exceed 1/100. If framing is aligned, the first bit position of any frame is not taken into account for the error rate calculation. If frame alignment state is not synchronized, all receive data bits are searched for the LLBA pattern. PRBS PRBS status This bit is set, when the PRBS receiver is in the synchronous state. It is set high if the synchronous state is reached even in the presence of a BER 1/10. A data stream containing all zeros with / without framing bits is also a valid pseudo-random bit sequence. Data Sheet 355 05.2001 PEB 3456 E Register Description FEC T1/E1 Receive Framing Error Counter Access : read/write Address : 41H Reset Value : 0000H 15 0 FE(15:0) FE Framing Error Counter The counter will not be incremented during asynchronous state. Error counter mode (Clear on Read or Errored Second) depends on register RFMR1.ECM. In errored second mode the counter is 10 bit wide, otherwise 16 bit. T1: F12 The counter will be incremented when incorrect FT and FS bits are received. T1: ESF The counter will be incremented when incorrect FAS bits are received. E1 The counter will be incremented when incorrect FAS words are received. Data Sheet 356 05.2001 PEB 3456 E Register Description CEC T1/E1 Receive CRC Error Counter Access : read/write Address : 42H Reset Value : 0000H 15 0 CR(15:0) CR CRC Errors The counter will not be incremented during asynchronous state. Error counter mode (Clear on Read or Errored Second) depends on register RFMR1.ECM. In errored second mode the counter is 10 bit wide, otherwise 16 bit. T1: F12 No function. T1: ESF The counter will be incremented when a multiframe has been received with a CRC error. E1: Doubleframe No function. E1: CRC-4 Multiframe In CRC-4 multiframe mode the counter will be incremented when a submultiframe has been received with a CRC error. Data Sheet 357 05.2001 PEB 3456 E Register Description EBC T1/E1 Receive Errored Block Counter Access : read/write Address : 43H Reset Value : 0000H 15 0 EB(15:0) EB E-Bit or Errored Block counter The counter will not be incremented during asynchronous state. Error counter mode (Clear on Read or Errored Second) depends on register RFMR1.ECM. In errored second mode the counter is 10 bit wide, otherwise 16 bit. T1 The counter will be incremented once per multiframe if a submultiframe has been received with a CRC error or an errored frame alignment has been detected. E1: Doubleframe No function. E1: CRC-4 Multiframe The counter will be incremented each time the framer receives a CRC-4 multiframe with Si bit in frame 13 or frame 15 set to zero. Data Sheet 358 05.2001 PEB 3456 E Register Description BEC T1/E1 Receive Bit Error Counter Access : read/write Address : 44H Reset Value : 0000H 15 0 BE(15:0) BE Bit Error Counter Error counter mode (Clear on Read or Errored Second) depends on register RFMR1.ECM. In errored second mode the counter is 10 bit wide, otherwise 16 bit. T1 This bit counter will be incremented with every received PRBS bit error in the PRBS synchronous state. Data Sheet 359 05.2001 PEB 3456 E Register Description 8.9.6 Facility Data Link Registers Facility data link registers control the signalling channels of T1, E1 as well as the signalling channels of the DS3 C-bit parity format (Path Maintenance Data Link and Far End Alarm and Control Channel). RCR1 Receive Channel Configuration Register 1 Access : read/write Address : 00H Reset Value : 0000H 15 0 14 13 12 RAH2 RAH1 RAH2 11 RTF(1:0) 10 9 8 7 6 5 4 3 INV RIFTF BFE BRM BRAC RAL2 RAL1 XCRC 2 1 0 CRC RON HDLC DIS Receive Address High Byte 2 Valid This bit enables byte RAH.RAH2 for address comparison. RAH1 0 Disable 1 Enable Receive Address High Byte 1 Valid This bit enables byte RAH.RAH1 for address comparison. RTF 0 Disable 1 Enable RFIFO Threshold Level This bit field sets the threshold of the receive FIFO and is applied to both pages of the receive FIFO. A 'Receive Pool Full' interrupt vector will be generated, when the programmed threshold is reached. The threshold value is given as follows: Data Sheet 00B 32 byte threshold 01B 16 byte threshold 10B 4 byte threshold 11B 2 byte threshold 360 05.2001 PEB 3456 E Register Description INV Invert data input from Receive Framer This bit enables data inversion between receive framer and receive signalling controller. RIFTF 0 Disable data Inversion. 1 Enable data inversion. Report Interframe Time-fill Change This bit selects, that interframe time-fill changes should be reported. BFE 0 Disable IFF status messages. 1 Enable IFF status messages. Enable BOM Filter Mode This bit selects, that byte oriented messages have to be filtered. The BOM is reported only if 7 out 10 data is received. This bit is valid in BOM mode only. BRM 0 Disable BOM filter mode. 1 Enable BOM filter mode. BOM Receive Mode This bit switches continuous and 10 byte packet reception of the receive signalling controller. This bit is valid in BOM mode only. BRAC 0 Enable continuous reception. 1 Enable 10 bytes packets. BOM Receiver Active T1: ESF This bit switches the BOM receiver to operational state (on) or inoperational state (off). When BOM Receiver is switched on, an automatic switching between HDLC mode and BOM mode is enabled. If eight or more consecutive '1's are detected, the BOM mode is entered. Upon detection of a flag in the data stream, the signalling controller switches back to HDLC mode. RAL2 0 Switch BOM receiver off. 1 Switch BOM receiver on. Receive Address Low Byte 2 Valid This bit enables byte RAL.RAL2 for address comparison. Data Sheet 0 Disable 1 Enable 361 05.2001 PEB 3456 E Register Description RAL1 Receive Address Low Byte 1 Valid This bit enables byte RAL.RAL1 for address comparison. XCRC 0 Disable 1 Enable Transfer CRC to RFIFO This bit defines, that CRC of incoming data packets shall be transferred to the receive FIFO or not. CRCDIS 0 No transfer of CRC to RFIFO. 1 Transfer of CRC to RFIFO. CRC Check Disable This bit enables or disables the CRC check of incoming data packets. RON 0 Enable CRC check. 1 Disable CRC check. Receiver On/Off This bit switches the receiver of the facility data link channel to operational (on) or inoperational state (off). HLDC 0 Switch receiver off. 1 Switch receiver on. HDLC Mode This bit identifies the protocol mode of the facility data link receiver. Data Sheet 0 Set protocol mode to transparent. 1 Set protocol mode to HDLC. 362 05.2001 PEB 3456 E Register Description RCR2 Receive Channel Configuration Register 2 Access : read/write Address : 01H Reset Value : 0000H 15 14 13 12 PAS SAUM SAUP PAS 10 9 SACRC(2:0) 7 SASSM(2:0) 6 5 4 3 2 1 0 SA8E SA7E SA6E SA5E SA4E SMF T1E1 Pattern Select for SSM and CRC Count Function This bit selects the default pattern for synchronization status messages and bit error indication. SAUM 0 Use pattern defined in ETS 300233. 1 Use patterns specified in registers VSSM and VCRC. Sa-bit Update Mode This bit selects the update mode for the Sa-bits located in register RSAW1..RSAW3. E1: Doubleframe 0 Sa-bits are updated after eight frames. 1 Sa-bits are updated only, if Sa data changes. Update is done after eight frames. E1: CRC-4 Multiframe SAUP 0 Sa-bits are updated after every multiframe. 1 Sa-bits are updated only, if Sa data changes. Update is done on a multiframe start. Sa-Bit Update This bit enables the Sa-bit update function. Data Sheet 0 Disable update of Sa-bits. 1 Enable update of Sa-bits using RSAW1..RSAW3 registers. 363 05.2001 PEB 3456 E Register Description SACRC Sa-bit Select for CRC Function This bit field enables the CRC count function of the selected Sa-bit. 0 Disable CRC count function. 1..5 Enable CRC count function for bit Sa4..Sa8, e.g. SACRC = 2 selects bit Sa8 for CRC count function. Other Reserved SASSM Sa-bit Select for SSM Function This bit field enables the synchronization status message function of the selected Sa-bit. The SSM function checks incoming messages and reports any change if a synchronization status message has been received three times in a row. 0 Disable SSM function. 1..5 Enable SSM function for bit Sa4..Sa8, e.g. SASSM = 2 selects bit Sa8 for SSM function. Other Reserved SA8E..SA4E Sa-bit Signalling Enable Setting one of the bits switches between Sa-bit access or protocol access of the selected bits. SMF 0 Enable Sa-bit access via register RSAW1-3. 1 Enable protocol access (HDLC, transparent). Selected bits will be combined to receive protocol data. Select Multiframe Format This bit switches between doubleframe and CRC-4 multiframe format. T1E1 0 Select doubleframe format. 1 Select CRC-4 multiframe format. T1/E1 Mode Selection This bit switches the receive signalling controller into T1 or E1 mode. Data Sheet 0 Select T1 mode. 1 Select E1 mode. 364 05.2001 PEB 3456 E Register Description RFF Receive FIFO Register Access : read Address : 02H Reset Value : 0000H 15 0 RFIFO(15:0) RFIFO Receive FIFO Data This bit field contains the first 16 bit word of the receive FIFO of the signalling controller. The receive FIFO itself consists of two pages with 32 bytes, thus 16 words can be stored inside the receive FIFO at a time. Port status and FIFO operations can be accessed via register PSR and register HND. The first bit received is stored in bit 0. Data Sheet 365 05.2001 PEB 3456 E Register Description XCR1 Transmit Channel Configuration Register 1 Access : read/write Address : 03H Reset Value : 0000H 15 8 7 PBYTE(7:0) PBYTE 4 PCNT(3:0) 3 2 1 0 INV XON DIS CRC SF Preamble Byte This bit field selects the preamble byte to be sent after interframe timefill transmission is stopped. PCNT Preamble Count This bit field selects the amount of preamble repetitions. INV Invert Data This bit enables data inversion between transmit signalling controller and transmit framer. XON 0 Disable data Inversion. 1 Enable data inversion. Transmitter On/Off This bit switches the transmitter of the facility data link to operational (on) or inoperational state (off). DISCRC 0 Switch transmitter off. 1 Switch transmitter on. Disable CRC This bit enables CRC generation and transmission on transmission of HDLC packets. Data Sheet 0 Enable CRC generation. 1 Disable CRC generation. 366 05.2001 PEB 3456 E Register Description SF Shared Flags This bit enables transmission of protocol data with shared flags. Data Sheet 0 Disable shared flags. 1 Enable shared flags. 367 05.2001 PEB 3456 E Register Description XCR2 Transmit Channel Configuration Register 2 Access : read/write Address : 04H Reset Value : 0000H 15 0 8 0 IFTF 0 0 0 0 0 0 7 6 5 4 3 2 1 0 IFTF SA8E SA7E SA6E SA5E SA4E SMF T1E1 Interframe Time Fill This bit determines the interframe time of the transmit signalling controller. SA8E..SA4E 0 Interframe time fill is 7EH. 1 Interframe time fill is FFH. Sa-bit Signalling Enable Setting one of the bits switches between normal Sa-bit access or protocol access of the selected bits. SMF 0 Enable Sa-bit access via register XSAW1-3. 1 Enable protocol access (HDLC, transparent). Selected bits will be combined for protocol data transmission. Select CRC-4 Multiframe Format This bit switches between doubleframe and multiframe format. E1 T1E1 0 Select doubleframe format. 1 Select CRC-4 multiframe format. T1/E1 Mode Selection This bit switches the receive signalling controller into T1 or E1 mode. Data Sheet 0 Select T1 mode. 1 Select E1 mode. 368 05.2001 PEB 3456 E Register Description XFF Transmit FIFO Register Access : write Address : 05H Reset Value : 0000H 15 0 XFIFO(15:0) XFIFO Transmit FIFO Data This bit field writes a 16 bit word to the transmit FIFO of the signalling controller. The transmit FIFO itself consists of two pages with 32 bytes, thus 16 words can be written to the transmit FIFO at a time. Port status and FIFO operations can be accessed via register PSR and register HND. Data written to the transmit FIFO is sent starting with bit 0 up to bit 15. Data Sheet 369 05.2001 PEB 3456 E Register Description PSR Port Status register Access : read Address : 06H Reset Value : 0000H 15 14 13 12 XRA XFW XRA 8 7 RBC(4:0) 6 5 SMODE(1:0) BRFO 4 0 STAT(4:0) Transmit Repeat Active This bit indicates that the transmit signalling controller is operating in repeat mode. XFW 0 Normal operation 1 Repeat operation Transmit FIFO Write Enable This bit indicates that data can be written to XFF.XFIFO. This bit is for polling use with the same meaning as the 'Transmit Pool Ready' interrupt vector. RBC Receive Byte Count This bit field indicates the amount of data stored in the receive FIFO. Valid after a 'Receive Message End' interrupt vector is generated. Receive byte count will be cleared, when a 'Receive Message Clear' command is executed via register HND. A zero byte count in combination with a `Receive Pool Full' or 'Receive Message End' interrupt vector means that 32 bytes are available in the receive FIFO. SMODE Receiver Status Mode This bit indicates the status of the receive signalling controller. If BOM mode is selected via bit RCR1.BRM the receiver switches automatically between HDLC mode and BOM mode. 10B HDLC mode 01B BOM mode Other Reserved Data Sheet 370 05.2001 PEB 3456 E Register Description BRFO BOM Receive FIFO Overflow 0 No overflow 1 RFF overflow The status word will be cleared after a 'Receive Message Clear' command is issued. STAT Receive FIFO Status This bit field reports the status of the data stored in the receive FIFO. HDLC mode 00000B Valid HDLC Frame 00001B Receive Data Overflow 00010B Receive Abort 00011B Not Octet 00100B CRC Error 00101B Channel Off BOM MODE Data Sheet 00000B BOM Filtered data declared 00001B BOM data available 00010B BOM End 00011B BOM filtered data undeclared 00100B BOM header error (ISF, incorrect synchronization format) 371 05.2001 PEB 3456 E Register Description HND Handshake Register Access : write Address : 07H Reset Value : 0000H 15 0 8 0 0 0 0 0 0 5 RMC 0 4 3 ABORT XRES XREP OBI 2 XHF 1 0 XTF XME Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be issued at the same time. Doing so will cause the facility data link to omit the transmit commands. RMC Receive Message Complete This bit is a confirmation from CPU that a data block has been read from RFIFO following a 'Receive Pool Full' or 'Receive Message End' interrupt vector and that the occupied page can now be released. 0 No function 1 Release page of receive FIFO. Note: If this bit is set, the low byte (transmit commands) of the register HND is ignored. ABORT Abort Frame Setting this bit aborts HDLC frames which are transmitted. XRES 0 Normal operation 1 Abort HDLC frame. Transmitter Reset This bit resets the signalling controller transmit. However, the contents of the control register will not be reset. XREP 0 Normal operation 1 Transmitter reset Transmission Repeat Setting this bit together with bit XTF indicates that the contents stored in XFF.XFIFO shall be repeatedly transmitted by the TE3-CHATT. 0 Data Sheet No cyclic transmission. 372 05.2001 PEB 3456 E Register Description 1 OBI Enable cyclic transmission. Odd Byte Count Indicator Setting this bit together with bit XME indicates the number of bytes written to XFF.XFIFO is odd. This means the lower byte of the last write transfer to the transmit FIFO is valid only. In HDLC mode the status byte written to transmit FIFO must be included in calculation. XHF 0 Even number of bytes stored in XFF.XFIFO. 1 Odd number of bytes stored in XFF.XFIFO. Transmit HDLC frame Setting this bit indicates that the contents written to XFF.XFIFO shall be transmitted as HDLC frame. If data written to XFF.XFIFO completes a HDLC frame, bit XME must be set together with XHF in order to generate CRC and flag. XTF 0 No function 1 Transmit data stored in XFF.XFIFO in HDLC format. Transmit transparent frame Setting this bit indicates that the contents written to XFF.XFIFO shall be transmitted in transparent mode. XME 0 No function 1 Transmit data stored in XFF.XFIFO fully transparent, i.e. without bit stuffing and CRC. Transmit Message End Setting this bit indicates that the last data block written to XFF.XFIFO completes the current frame. The last byte of the data block written to the transmit FIFO is a status word indicating the message status. The signalling controller terminates the transmission properly by appending CRC and the closing flag to the data sequence if the status word written as the last entry to the transmit FIFO does not contain an abort indication. * Data Sheet 373 05.2001 PEB 3456 E Register Description Table 8-26 Signalling Controller Transmit Commands XRES XREP OBI XHF XTF XME Function 1 - - - - - Reset Port 0 0 0 1 0 0 Transmit HDLC Frames Send FIFO content as HDLC frame. 0 0 0/1 1 0 1 End Transmit HDLC Send FIFO content as HDLC frame. Add CRC (if enabled) and flag after last byte stored in FIFO. 0 1 0/1 1 0 0 Repeat HDLC Frame Send FIFO content as HDLC frame. Add CRC (if enabled) and flag after last byte stored in FIFO. Then repeat transmission of FIFO content. 0 1 0/1 1 0 1 Stop Repeat HDLC Frame Stop transmission after last byte stored in FIFO. This command is issued when repetitive transmission started by command 'Repeat HDLC Frame' shall be stopped. 0 0 0 0 1 0 Transmit Transparent Send FIFO content in transparent mode. 0 0 0/1 0 1 1 End Transmit Transparent Send FIFO content in transparent mode. End transmission after last byte stored in FIFO. 0 1 0/1 0 1 0 Repeat Transmit Transparent Send FIFO content in transparent mode. Repeat transmission of FIFO content after last byte was sent. 0 1 0/1 0 1 1 Stop Repeat Transmit Transparent Stop transparent transmission after last byte stored in FIFO. This command is issued when repetitive transmission started by command 'Repeat transmit transparent' shall be stopped. Data Sheet 374 05.2001 PEB 3456 E Register Description MSK Interrupt Mask Register Access : read/write Address : 08H Reset Value : 0000H 15 0 11 0 0 0 10 9 8 4 TXSA ALLS XDU XPR 0 0 0 3 2 1 0 RSA SSM RPF RME ISF For each facility data link interrupt vector an interrupt vector generation mask is provided. Generation of an interrupt vector itself does not necessarily result in assertion of the interrupt pin. For description of interrupt concept and interrupt vectors see "Layer One Interrupts" on Page 137. The following definition applies: 1 The corresponding interrupt vector will not be generated by the device. 0 The corresponding interrupt vector will be generated. Facility Data Link Interrupt Vector Transmit TXSA Mask 'Transmit Sa Data' ALLS Mask 'All Sent' XDU Mask ''Transmit Data Underrun' XPR Mask 'Transmit Pool Ready' Facility Data Link Interrupt Vector Receive RSA Mask 'Receive Sa Data Valid' SSM Mask 'Synchronization Status Message Received' RPF Mask 'Receive Pool Full' RME Mask 'Receive Message End' ISF Mask 'Incorrect Synchronization Format' Data Sheet 375 05.2001 PEB 3456 E Register Description RAL Receive Address Low Access : read/write Address : 09H Reset Value : 0000H 15 8 7 RAL2(7:0) RAL2 0 RAL1(7:0) Receive Address Low Byte This bit field defines the low byte of the second receive address. RAL1 Receive Address Low Byte This bit field defines the low byte of the first receive address. Data Sheet 376 05.2001 PEB 3456 E Register Description RAH Receive Address High Access : read/write Address : 0AH Reset Value : 0000H 15 8 7 RAH2(7:0) RAH2 0 RAH1(7:0) Receive Address High Byte This bit field defines the high byte of the second receive address. RAH1 Receive Address High Byte This bit field defines the high byte of the first receive address. Data Sheet 377 05.2001 PEB 3456 E Register Description RSAW1 Receive Sa Word 1 Access : read Address : 0BH Reset Value : 0000H 15 8 7 SA5(7:0) SA5 0 SA4(7:0) Received Sa5 Data Byte This bit field contains data received in Sa5 of an E1 doubleframe or an E1 CRC-4 multiframe. E1: CRC-4 Multiframe Received data byte is aligned to a multiframe boundary. SA5(0) is the data bit receive in frame one, while SA5(7) is the data byte received in frame 15 of a multiframe. SA4 Received Sa4 Data Byte This bit field contains data received in Sa4 of an E1 doubleframe or an E1 multiframe. E1: CRC-4 Multiframe Received data byte is aligned to a multiframe boundary. SA4(0) is the data bit receive in frame one, while SA4(7) is the data byte received in frame 15 of a multiframe. Data Sheet 378 05.2001 PEB 3456 E Register Description RSAW2 Receive Sa Word 2 Access : read Address : 0CH Reset Value : 0000H 15 8 7 SA7(7:0) SA7 0 SA6(7:0) Received Sa7 Data Byte This bit field contains data received in Sa7 of an E1 doubleframe or an E1 CRC-4 multiframe. E1: CRC-4 Multiframe Received data byte is aligned to a multiframe boundary. SA7(0) is the data bit receive in frame one, while SA7(7) is the data byte received in frame 15 of a multiframe. SA6 Received Sa6 Data Byte This bit field contains data received in Sa6 of an E1 doubleframe or an E1 multiframe. E1: CRC-4 Multiframe Received data byte is aligned to a multiframe boundary. SA6(0) is the data bit receive in frame one, while SA6(7) is the data byte received in frame 15 of a multiframe. Data Sheet 379 05.2001 PEB 3456 E Register Description RSAW3 Receive Sa Word 3 Access : read Address : 0DH Reset Value : 0000H 15 0 8 0 SADV 0 0 0 0 0 7 SADV 0 SA8(7:0) Received Sa4..Sa8 Data Valid This bit indicates that new Sa data in register RSAW1..RSAW3 is available. The signalling controller will not update Sa data while this bit is set. SADV will be cleared on reads to this register. SA8 0 No Sa data available. 1 Sa data available in register RSAW1..RSAW3. Received Sa8 Data Byte This bit field contains data received in Sa8 of an E1 doubleframe or an E1 multiframe. E1: CRC-4 Multiframe Received data byte is aligned to a multiframe boundary. SA8(0) is the data bit receive in frame one, while SA8(7) is the data byte received in frame 15 of a multiframe. Data Sheet 380 05.2001 PEB 3456 E Register Description RSAW4 Receive Sa Word 4 Access : read Address : 0EH Reset Value : 0000H 15 0 7 0 SSMD 0 0 0 0 0 0 4 SSMD(3:0) 3 0 0 1 0 0 SSMV SSM Data Pattern This bit field contains the received synchronization status message. The synchronization status message reported depends on bit RCR2.PAS and, if selected, on pattern enabled in register VSSM. Only valid if SSMV is set. SSMV Synchronization Status Message Valid This bit indicates that a new synchronization status message has been received. A new SSM is reported every time a message has been received three time in a row on the Sa-bit selected via register RCR2.SASSM. This bit is reset after the user performs a read on this register. Data Sheet 0 No new SSM data available. 1 New SSM data available. 381 05.2001 PEB 3456 E Register Description CRC1 CRC Status Counter 1 Access : read Address : 0FH Reset Value : 0000H 15 0 CRCS1(15:0) CRC1 CRC1 counter The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit sequences 0001B and 0011B or user programmable values specified in register VCRC in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors are reported from the TE via Sa6. Incrementing is only possible in the multiframe synchronous state. The counter is increased with every received bit error indication if enabled in register RCR2. The counter will not be incremented once it reaches FFFFH. A read will clear this counter. Data Sheet 382 05.2001 PEB 3456 E Register Description CRC2 CRC Status Counter 2 Access : read Address : 10H Reset Value : 0000H 15 0 CRCS(15:0)2 CRC2 CRC2 counter The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit sequences 0010B and 0011B or user programmable values specified in register VCRC in every submultiframe on a selectable Sa-bit. In the primary rate access digital section CRC errors detected at Treference points are reported via Sa6. Incrementing is only possible in the multiframe synchronous state. The counter is increased with every received bit error indication if enabled in register RCR2. The counter will not be incremented once it reaches FFFFH. A read will clear this counter. Data Sheet 383 05.2001 PEB 3456 E Register Description XSAW1 Transmit Sa Word 1 Access : read/write Address : 11H Reset Value : 0000H 15 8 7 SA5(7:0) SA5 0 SA4(7:0) Transmit Sa5 Data Byte This bit field contains data to be transmitted in Sa5 of an E1 doubleframe or an E1 CRC-4 multiframe. SA5 will be inserted into the data stream, if selected via bit XCR2.SA5E. E1: CRC-4 Multiframe Transmit data will be aligned to a multiframe boundary. SA5(0) is the data bit transmitted in frame one while SA5(7) is the data bit transmitted in frame 15 of a multiframe. SA4 Transmit Sa4 Data Byte This bit field contains data to be transmitted in Sa4 of an E1 doubleframe or an E1 CRC-4 multiframe. SA4 will be inserted into the data stream, if selected via bit XCR2.SA4E. E1: CRC-4 Multiframe Transmit data will be aligned to a multiframe boundary. SA4(0) is the data bit transmitted in frame one while SA4(7) is the data bit transmitted in frame 15 of a multiframe. Data Sheet 384 05.2001 PEB 3456 E Register Description XSAW2 Transmit Sa Word 2 Access : read/write Address : 12H Reset Value : 0000H 15 8 7 SA7(7:0) SA7 0 SA6(7:0) Transmit Sa7 Data Byte This bit field contains data to be transmitted in Sa7 of an E1 doubleframe or an E1 multiframe. SA7 will be inserted into the data stream, if selected via bit XCR2.SA7E. E1: CRC-4 Multiframe Transmit data will be aligned to a multiframe boundary. SA7(0) is the data bit transmitted in frame one while SA7(7) is the data bit transmitted in frame 15 of a multiframe. SA6 Transmit Sa6 Data Byte This bit field contains data to be transmitted in Sa6 of an E1 doubleframe or an E1 CRC-4 multiframe. SA6 will be inserted into the data stream, if selected via bit XCR2.SA6E. E1: CRC-4 Multiframe Transmit data will be aligned to a multiframe boundary. SA6(0) is the data bit transmitted in frame one while SA6(7) is the data bit transmitted in frame 15 of a multiframe. Data Sheet 385 05.2001 PEB 3456 E Register Description XSAW3 Transmit Sa Word 3 Access : read/write Address : 13H Reset Value : 0000H 15 14 0 XSAV XSAV 13 8 7 XSAR(5:0) 0 SA8(7:0) Sa Data Valid This bit indicates that new Sa data has been written to register XSAW1..XSAW3 from system processor. XSAR 0 No new Sa data available. 1 New Sa data available. Sa Data Repetitions This bit field defines the number of repetitions of the Sa data bytes. A 'Transmit Sa Data' interrupt vector will be generated after programmed number of repetitions. SA8 Transmit Sa8 Data Byte This bit field contains data to be transmitted in Sa8 of an E1 doubleframe or an E1 CRC-4 multiframe. SA8 will be inserted into the data stream, if selected via bit XCR2.SA8E. E1: CRC-4 Multiframe Transmit data will be aligned to a multiframe boundary. SA8(0) is the data bit transmitted in frame one while SA8(7) is the data bit transmitted in frame 15 of a multiframe. Data Sheet 386 05.2001 PEB 3456 E Register Description VSSM Valid SSM Pattern Access : read/write Address : 14H Reset Value : 0000H 15 0 PA(15:0) PA Pattern 15..0 Setting one or more of the bits enables the selected pattern for SSM comparison. E.g. setting PA(3) and PA(1) enables pattern 0010B and 0001B for SSM comparison. Identified SSM pattern are reported via register RSAW4. Only valid if RCR2.PAS is set to '1'. Data Sheet 387 05.2001 PEB 3456 E Register Description VCRC Valid CRC Count Pattern Access : read/write Address : 15H Reset Value : 0000H 15 12 CRC22(3:0 11 8 7 CRC21(3:0) 4 CRC12(3:0) 3 0 CRC11(3:0) CRC22 CRC21 CRC2 Pattern Definition The bit fields CRC21 and CRC22 determine the Sa-bit error indication pattern to be reported in register CRC2. Only valid if RCR2.PAS is set to '1'. CRC12 CRC11 CRC1 Pattern Definition The bit fields CRC11 and CRC12 determine the Sa-bit error indication pattern to be reported in register CRC1. Only valid if RCR2.PAS is set to '1'. Data Sheet 388 05.2001 PEB 3456 E Electrical Characteristics 9 Electrical Characteristics 9.1 Important Electrical Requirements Both VDD3 and VDD25 can take on any power-on sequence. Within 50 milliseconds of power-up the voltages must be within their respective absolute voltage limits. At powerdown, within 50 milliseconds of either voltage going outside its operational range, both voltages must be returned below 0.1V. 9.2 Absolute Maximum Ratings Table 9-1 Absolute Maximum Ratings Parameter Symbol Ambient temperature under bias PEB 3456 E TA Junction temperature under bias TJ Limit Values Voltage on any pin with respect to ground max 0 -40 70 85 C Tstg VS Storage temperature min Unit 125 C -65 125 C -0.5 VDD3+0.5 V Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9.3 DC Characteristics a) Power Supply Pins Table 9-2 DC Characteristics Parameter Symbol Limit Values Unit Test Condition min. max. Core Supply Voltage VDD25 2.25 2.75 V I/O Supply Voltage VDD3 3.0 3.6 V Data Sheet 389 05.2001 PEB 3456 E Electrical Characteristics Parameter Symbol Limit Values min. Core supply current VDD25 max. Unit Test Condition operationa l ICC25 < 400 mA power down (no clocks) ICCPD25 <2 mA ICC3 < 200 mA ICCPD3 <2 mA ILI < 10 A <3 W I/O supply operationa current l VDD3 power down (no clocks) Sum of Input leakage current and Output leakage current (Outputs Hi-z) Power Dissipation Inputs at VSS/VDD3 No output loads. ILO P b) Non-PCI Interface Pins Table 9-3 DC Characteristics (Non-PCI Interface Pins) TA = -40 to 85C, VDD3 = 3.3 V =0.3 V, VDD25 = 2.5 V =0.25 V, VSS = 0 V Parameter Symbol Limit Values min. L-input voltage H-input voltage L-output voltage H-output voltage Data Sheet VIL VIH VOL VOH Unit Test Condition max. -0.4 0.8 V 2.0 VDD3+0.4 V 0.45 V 2.4 390 V IQL = 2 mA IQH = -400 A 05.2001 PEB 3456 E Electrical Characteristics c) PCI Interface Pins Table 9-4 DC Characteristics (PCI Interface Pins) TA = -40 to 85C, VDD3 = 3.3 V =0.3 V, VDD25 = 2.5 V =0.25 V, VSS = 0 V Parameter Symbol Limit Values Unit Test Condition min. max. L-input voltage VIL -0.5 0.3VDD3 80mV V H-input voltage VIH VOL VOH 0.5VDD3 VDD3+0.5 V 0.1VDD3 V L-output voltage H-output voltage 9.4 0.9VDD3 V IQL = 1500 A IQH = -500 A AC Characteristics a) Non-PCI interface pins TA = -40 to 85C, VDD3 = 3.3 V =0.3 V, VDD25 = 2.5 V =0.25 V, VSS = 0 V Inputs are driven to 2.4 V for a logical `1' and to 0.4 V for a logical `0'. Timing measurements are made at 2.0 V for a logical `1' and at 0.8 V for a logical `0'. The AC testing input/output waveforms are shown below. * 2.4 2.0 2.0 Device Under Test test points 0.8 0.8 0.45 Figure 9-1 Cload = 50pF Input/Output Waveform for AC Tests b) PCI interface pins PCI interface pins are measured as pins compliant to the 3.3V signalling environment according to the PCI Specification Rev. 2.1. Data Sheet 391 05.2001 PEB 3456 E Electrical Characteristics 9.4.1 PCI Bus Interface Timing * tcyc thigh tlow 0.6 VDD3 0.5 VDD3 0.4 VDD3, p-to-p (minimum) 0.4 VDD3 0.3 VDD3 0.2 VDD3 Figure 9-2 PCI Clock Cycle Timing Table 9-5 PCI Clock Characteristics Parameter Symbol Limit Values min. Unit max. CLK cycle time tcyc 15 ns CLK high time thigh 6 ns CLK low time tlow 7 ns CLK slew rate (see note) 1.5 4 V/ns Note: Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform shown in Figure 9-3. * Vth Clock Vtest Vtl tsu Input delay Figure 9-3 Data Sheet Vth Vtl Vtest th Inputs valid Vtest Vmax PCI Input Timing Measurement Conditions 392 05.2001 PEB 3456 E Electrical Characteristics * Clock Vth Vtest Vtl tval Output delay Vtest toff ton Tri-state output Vtest Vtest Figure 9-4 PCI Output Timing Measurement Conditions Table 9-6 PCI Interface Signal Characteristics Parameter Symbol Limit Values Unit Notes min. max. CLK to signal valid - bussed signals tval 2 8 ns 1, 2 CLK to REQ valid tval 2 7 ns 1, 2 Float to active delay ton 2 Active to float delay toff Input setup time to CLK - bussed signals tsu 4 2 Input setup time to CLK - GNT tsu 5 2 Input hold time from CLK th 0.5 ns 14 Note: 1. Minimum times are measured for 3.3V signalling environment according to the PCI Specification Rev. 2.1. 2. REQ and GNT are point-to-point signals. All other signals are bussed. Data Sheet 393 05.2001 PEB 3456 E Electrical Characteristics 9.4.2 SPI Interface Timing * SPCS 1 3 4 2 SPCLK 5 6 SPSO 7 8 SPSI Figure 9-5 SPI Interface Timing Table 9-7 SPI Interface Timing * No. Parameter Limit Values min. Unit Notes 1 max. 1 SPCS low to SPCLK delay 500 ns 2 SPCLK to SPCS delay 500 ns 3 SPCLK high time 500 ns 4 SPCLK low time 500 5 SPCS to SPSO delay ns 100 100 ns 6 SPCLK to SPSO delay 7 SPSI to SPCLK setup time 100 ns ns 8 SPSI to SPCLK hold time 100 ns Note: 1 SPI clock is related to PCI clock where the SPI frequency is 1/78 of the PCI frequency. All timings for SPI interface are calculated with a PCI clock running at 33 MHz. Data Sheet 394 05.2001 PEB 3456 E Electrical Characteristics 9.4.3 Local Microprocessor Interface Timing 9.4.3.1 Intel Bus Interface Timing (Slave Mode) * LA 21 20 LCS0 22 23 32 LRD 24 26 25 LRDY 27 28 29 LD Figure 9-6 Intel Read Cycle Timing (Slave Mode) * LA 20 21 LCS0 22 32 23 LWR 24 25 26 LRDY 30 31 LD Figure 9-7 Data Sheet Intel Write Cycle Timing (Slave Mode) 395 05.2001 PEB 3456 E Electrical Characteristics Table 9-8 Intel Bus Interface Timing No. Parameter Limit Values 20 LA to LRD, LWR setup time 20 ns 21 LA to LRD, LWR hold time 0 ns 22 LCS0 to LRD, LWR setup time 20 ns 23 LCS0 to LRD, LWR hold time 0 ns 24 LCS0 low to LRDY active delay 20 ns 25 LRD, LWR high to LRDY high delay 20 ns 26 LCS0 high to LRDY float delay 20 ns 27 LRD low to LD active delay 20 ns 28 LRD high to LD float delay 20 ns 29 LRDY low to LD valid delay 20 ns min. Unit max. 30 LD to LWR setup time 20 ns 31 LD to LWR hold time 0 ns 32 LRD, LWR minimum high time 20 ns Data Sheet 396 05.2001 PEB 3456 E Electrical Characteristics 9.4.3.2 Intel Bus Interface Timing (Master Mode) * LCLK 60a 60b 61a 61b 62a 62b LA LCS2,1 LBHE 63a 67a 63b LRD 65 66 LRDY 67b LD Figure 9-8 Intel Read Cycle Timing (Master Mode, LRDY controlled) * LCLK 60a 60b 61a 61b 62a 62b LA LCS2,1 LBHE 63a 65 63b LWR 66 LRDY 69a 69b LD Figure 9-9 Data Sheet Intel Write Cycle Timing (Master Mode, LRDY controlled) 397 05.2001 PEB 3456 E Electrical Characteristics * WS*tCYC LCLK 60a 60b 61a 61b 62a 62b 63a 63b LA LCS2,1 LBHE LRD 68a 68b LD Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled) * WS*tCYC LCLK 60a 60b 61a 61b 62a 62b 63a 63b 69a 69b LA LCS2,1 LBHE LWR LD Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled) Data Sheet 398 05.2001 PEB 3456 E Electrical Characteristics * LCLK Read/ Write 70 71 LHOLD 72 LHLDA Figure 9-12 Intel Bus Arbitration Timing Table 9-9 No. Intel Bus Interface Timing (Master Mode) Parameter Limit Values Unit min. max. LCLK to LA active delay 0 10 ns 60b LCLK to LA float delay 0 10 ns 61a LCLK to LCS2,1 active delay 0 10 ns 61b LCLK to LCS2,1 float delay 0 10 ns 62a LCLK to LBHE active delay 0 10 ns 62b LCLK to LBHE float delay 0 10 ns 63a LCLK to LRD, LWR active delay 0 10 ns 63b LCLK to LRD, LWR float delay 0 10 ns 65 LRDY low to LRD, LWR high delay 2 tCYC 60a 66 LRDY to LRD, LWR hold time 0 ns 67a LD to LRD setup time 0 ns 67b LD to LRD hold time 0 ns 68a LD to LCLK setup time 10 ns 68b LD to LCLK hold time 0 ns 69a LCLK to LD delay 0 10 ns 69b LCLK to LD float delay 0 10 ns 70 LCLK to LHOLD delay 0 10 ns 71 LHLDA asserted to Read/Write Cycle start 1 tCYC 72 LHLDA minimum pulse width 2 tCYC Note: tCYC is the clock period of the PCI clock. Data Sheet 399 05.2001 PEB 3456 E Electrical Characteristics 9.4.3.3 Motorola Bus Interface Timing (Slave Mode) * LA 41 40 LCS0 42 54 43 LDS 45 44 LRDWR 46 48 47 LDTACK 49 50 51 LD Figure 9-13 Motorola Read Cycle Timing (Slave Mode) * LA 40 41 LCS0 42 54 43 LDS 44 45 LRDWR 46 47 48 LDTACK 52 53 LD Figure 9-14 Motorola Write Cycle Timing (Slave Mode) Data Sheet 400 05.2001 PEB 3456 E Electrical Characteristics Table 9-10 Motorola Bus Interface Timing No. Parameter Limit Values 40 LA to LDS setup time 20 ns 41 LA to LDS hold time 0 ns 42 LCS0 to LDS setup time 20 ns 43 LCS0 to LDS hold time 0 ns 44 LRDWR to LDS setup time 20 ns 45 LRDWR to LDS hold time 0 46 LCS0 low to LDTACK active delay min. Unit max. ns 20 ns 47 LDS high to LDTACK high delay 20 ns 48 LCS0 high to LDTACK float delay 20 ns 49 LDS low to LD active delay 20 ns 50 LDS high to LD float delay 20 ns 51 LDTACK low to LD valid delay 20 ns 52 LD to LDS setup time 53 LD to LDS hold time 0 ns 54 LDS minimum high time 20 ns Data Sheet 20 401 ns 05.2001 PEB 3456 E Electrical Characteristics 9.4.3.4 Motorola Bus Interface Timing (Master Mode) * LCLK 80a 80b 81a 81b 82a 82b 83a 83b LA LCS2,1 LSIZE0 LRDWR 84a 85 84b LDS 86 LDTACK 87a 87b LD Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled) * LCLK 80a 80b 81a 81b 82a 82b 83a 83b LA LCS2,1 LSIZE0 LRDWR 84a 85 84b LDS 86 LDTACK 89a 89b LD Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled) Data Sheet 402 05.2001 PEB 3456 E Electrical Characteristics * WS*tCYC LCLK 80a 80b 81a 81b 82a 82b 83a 83b 84a 84b LA LCS2,1 LSIZE0 LRDWR LDS 88a 88b LD Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled) * WS*tCYC LCLK 80a 80b 81a 81b 82a 82b 83a 83b 84a 84b 89a 89b LA LCS2,1 LSIZE0 LRDWR LDS LD Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled) Data Sheet 403 05.2001 PEB 3456 E Electrical Characteristics * LCLK Read/ Write 90 91 LBR 92 LBG 94 93 LBGACK Figure 9-19 Motorola Bus Arbitration Timing Table 9-11 Motorola Bus Interface Timing (Master Mode) No. Parameter Limit Values Unit min. max. 80a LCLK to LA active delay 0 10 ns 80b LCLK to LA float delay 0 10 ns 81a LCLK to LCS2,1 active delay 0 10 ns 81b LCLK to LCS2,1 float delay 0 10 ns 82a LCLK to LSIZE0 active delay 0 10 ns 82b LCLK to LSIZE0 float delay 0 10 ns 83a LCLK to LRDWR active delay 0 10 ns 83b LCLK to LRDWR float delay 0 10 ns 84a LCLK to LDS active delay 0 10 ns 84b LCLK to LDS float delay 0 10 ns 85 LDTACK low to LDS high delay 2 tCYC 86 LDTACK to LDS hold time 0 ns 87a LD to LDTACK setup time 0 ns 87b LD to LDTACK hold time 0 ns 88a LD to LCLK setup time 10 ns 88b LD to LCLK hold time 0 89a LCLK to LD delay 0 Data Sheet 404 ns 10 ns 05.2001 PEB 3456 E Electrical Characteristics No. Parameter Limit Values min. max. Unit 89b LCLK to LD float delay 0 10 ns 90 LCLK to LBR delay 0 10 ns 91 LBGACK to LBR delay 1 tCYC 92 LBG to LBGACK hold time 0 ns 93 LBG to LBGACK delay 1 tCYC 94 LCLK to LBGACK delay 0 Data Sheet 405 10 ns 05.2001 PEB 3456 E Electrical Characteristics 9.4.4 tCYC is the clock period of the PCI clock.Serial Interface Timing 9.4.4.1 DS3 Serial Interface Timing Note: The clock input timings are calculated assuming a PCI clock frequency of 33 MHz or more. * 100 101 TC44 RC44 102 103 104 Figure 9-20 Clock Input Timing Table 9-12 Clock Input Timing No. Parameter 100 Clock frequency Limit Values min. Unit max. nom. 44.736 MHz 101 Clock high timing 7.5 ns 102 Clock low timing 7.5 ns 103 Clock fall time 2 ns 104 Clock rise time 2 ns Data Sheet 406 05.2001 PEB 3456 E Electrical Characteristics * TC44 RC44 (Note 1) 110 110 TC44O Figure 9-21 DS3 Transmit Cycle Timing Note: 1. Actual clock reference depends on selected clock mode: * TC44O (Note 2) TC44O (Note 3) 111 TD44, TD44P/N Figure 9-22 DS3 Transmit Data Timing Note: 2. Timing for transmit data which is updated on the rising edge of TC44O. 3. Timing for transmit data which is updated on the falling edge of TC44O. Table 9-13 No. DS3 Transmit Cycle Timing Parameter Limit Values min. max. Unit 110 RC44, TC44 to TC44O delay 2 15 ns 111 TC44O to TD44, TD44P/TD44N delay 0 5 ns Data Sheet 407 05.2001 PEB 3456 E Electrical Characteristics * RC44 (Note 1) RC44 (Note 2) 130 131 RD44, RD44P/N Figure 9-23 DS3 Receive Cycle Timing Note: 1. Timing for data which is sampled on the rising edge of the receive clock. 2. Timing for data which is sampled on the falling edge of the receive clock. Table 9-14 No. DS3 Receive Cycle Timing Parameter Limit Values min. Unit max. 130 RD44, RD44P/RD44N to RC44 setup time 5 ns 131 RD44, RD44P/RD44N to RC44 hold time 5 ns Data Sheet 408 05.2001 PEB 3456 E Electrical Characteristics * CLK 132 RLOS 132 RLOF 132 RAIS 132 RRED Note: DS3 Status Signal Timing Note: Status signals are generated synchronous to the PCI clock. Table 9-15 DS3 Status Signal Timing No. Parameter 132 CLK to RLOS/RLOF/RAIS/RRED delay Data Sheet Limit Values 409 min. max. 2 10 Unit ns 05.2001 PEB 3456 E Electrical Characteristics 9.4.4.2 Overhead Bit Timing * TOVHCK 150 TOVHSYN (Output Mode) 153 154 155 156 TOVHD TOVHEN Figure 9-24 DS3 Transmit Overhead Timing * TC44O 151 152 TOVHSYN (Input Mode)) Figure 9-25 DS3 Transmit Overhead Synchronization Timing Table 9-16 No. DS3 Transmit Overhead Timing Parameter Limit Values min. Unit max. 150 TOVHCK to TOVHSYN delay 151 TOVHSYN to TCLKO44 setup time 5 ns 152 TOVHSYN to TCLKO44 hold time 5 ns 153 TOVD to TOVHCK setup time 25 ns 154 TOVD to TOVHCK hold time 5 ns 155 TOVHEN to TOVHCK setup time 25 ns 156 TOVHEN to TOVHCK hold time 5 ns Data Sheet 75 410 ns 05.2001 PEB 3456 E Electrical Characteristics * ROVHCK 157 ROVHSYN 158 ROVHD Figure 9-26 DS3 Receive Overhead Timing Table 9-17 No. DS3 Receive Overhead Timing Parameter Limit Values min. Unit max. 157 ROVHCK to ROVHSYN delay 75 ns 158 ROVHCK to ROVHD delay 75 ns Data Sheet 411 05.2001 PEB 3456 E Electrical Characteristics 9.4.4.3 Stuff Bit Timing * TSBCK 160 161 TSBD Figure 9-27 DS3 Transmit Stuff Bit Timing Table 9-18 No. DS3 Transmit Stuff Timing Parameter Limit Values min. Unit max. 160 TSBD to TSBCK setup time 25 ns 161 TSBD to TSBCK hold time 5 ns * RSBCK 162 RSBD Figure 9-28 DS3 Receive Stuff Bit Timing Table 9-19 DS3 Receive Stuff Bit Timing No. Parameter 162 RSBCK to RSBD delay Limit Values min. Data Sheet max. 75 412 Unit ns 05.2001 PEB 3456 E Electrical Characteristics 9.4.4.4 T1/E1 Tributary Timing * 105 106 107 CTCLK 108 109 Figure 9-29 T1/E1 Tributary Clock Input Timing Table 9-20 No. T1/E1 Tributary Clock Input Timing Parameter Limit Values min. typ Unit max. Tributaries operated in E1 Mode 105 Clock frequency 2.048 MHz 50 ppm 106 Clock high timing 40 ns 107 Clock low timing 40 ns 108 Clock fall time 10 ns 109 Clock rise time 10 ns Tributaries operated in T1 Mode 1.544 MHz 130 ppm 105 Clock frequency 106 Clock high timing 40 ns 107 Clock low timing 40 ns 108 Clock fall time 10 ns 109 Clock rise time 10 ns Data Sheet 413 05.2001 PEB 3456 E Electrical Characteristics * CTCLK CTCLK 120 121 CTFS Figure 9-30 T1/E1 Tributary Synchronization Timing Table 9-21 No. T1/E1 Tributary Synchronization Timing Parameter Limit Values min. Unit max. 120 CTFS to CTCLK setup time 5 ns 121 CTFS to CTCLK hold time 5 ns Data Sheet 414 05.2001 PEB 3456 E Electrical Characteristics 9.4.4.5 Test Port Timing * 170 171 TTCLK 172 173 174 Figure 9-31 T1/E1 Test Transmit Clock Timing Table 9-22 No. T1/E1 Test Transmit Clock Timing Parameter Limit Values min. typ Unit max. Test port operated in E1 Mode 170 Clock period 2.048 MHz 50 ppm 171 Clock high timing 100 ns 172 Clock low timing 100 ns 173 Clock fall time 10 ns 174 Clock rise time 10 ns Test port operated in T1 Mode 1.544 MHz 130 ppm 170 Clock period 171 Clock high timing 100 172 Clock low timing 100 173 Clock fall time 10 ns 174 Clock rise time 10 ns Data Sheet 415 ns ns 05.2001 PEB 3456 E Electrical Characteristics * TTCLK 175 176 TTD Figure 9-32 T1/E1 Test Transmit Data Timing Table 9-23 No. T1/E1 Test Transmit Data Timing Parameter Limit Values min. Unit max. 175 TTD(x) to TTC(x) setup time 25 ns 176 TTD(x) to TTC(x) hold time 75 ns * 180 181 182 TRCLK Figure 9-33 T1/E1 Test Receive Clock Timing Table 9-24 No. T1/E1 Test Receive Clock Timing Parameter Limit Values min. typ Unit max. Test port operated in E1 Mode 180 Clock period 469 2056 ns 181 Clock high timing 182 Clock low timing 156 335 ns 312 1900 ns Test Port operated in T1 Mode 180 Clock period 625 1587 ns 181 Clock high timing 310 495 ns 182 Clock low timing 310 1275 ns Data Sheet 416 05.2001 PEB 3456 E Electrical Characteristics * TRCLK 185 TRD Figure 9-34 T1/E1 Test Receive Data Timing Table 9-25 No. 185 Test T1/E1 Receive Data Timing Parameter Limit Values RTC(x) to RTD(x) delay Data Sheet 417 min. max. -5 25 Unit ns 05.2001 PEB 3456 E Electrical Characteristics 9.4.5 JTAG Interface Timing * TRST 200 201 202 TCK 203 204 TMS 205 206 TDI 207 TDO Figure 9-35 JTAG Interface Timing Table 9-26 JTAG Interface Timing No. Parameter Limit Values 200 TCK period 120 ns 201 TCK high time 60 ns 202 TCK low time 60 ns 203 TMS setup time 20 ns 204 TMS hold time 20 ns 205 TDI setup time 20 ns 206 TDI hold time 20 ns 207 TDO valid time 50 ns min. Data Sheet 418 Unit max. 05.2001 PEB 3456 E Electrical Characteristics 9.4.6 Reset Timing * power-on VDD3 221 CLK 220 RST Figure 9-36 Reset Timing Table 9-27 Reset Timing No. Parameter Limit Values 220 RST pulse width 221 Number of CLK cycles during RST active min. Data Sheet 419 Unit max. 120 ns 2 CLK cycles 05.2001 10 Package Outline ((420)) PEB 3456 E List of Abbreviations 11 List of Abbreviations Abbreviation Definition A/C Analogue to Digital ADC Analogue to Digital Converter AIS Alarm indication signal (blue alarm) AGC Automatic gain control ALOS Analog loss of signa AMI Alternate mark inversion ANSI American National Standards Institute ATM Asynchronous transfer mode SDH Synchornous Digital Hierarchy SONET Synchronous Optical Network ESF Extended Superframe SF Super Frame HDLC High Level Data Link Control SDLC Synchronous Level Data Link Control PCI Peripheral Component Interconnect. DS3 Digital Signal Level 3 PLL Phase Locked Loop FDL Facility Data link SPI Serial Peripheral Interface BOM Bit Oriented Massage FIFO First in First out AUXP Auxiliary pattern Line 0 B8ZS Line coding to avoid too long strings of consecutive 0 BER Bit error rate BFA Basic frame alignment BOM Bit orientated message Bellcore Bell Communications Research BPV Bipolar violation Data Sheet 421 05.2001 PEB 3456 E List of Abbreviations Abbreviation Definition A/C Analogue to Digital BSN Backward sequence number CAS Channel associated signaling CAS-BR Channel associated signaling - bit robbing CAS-CC Channel associated signaling - common channel CCS Common channel signaling CMI coded mark inversion (also known as 1T2B code) CR Command/Response (special bit in PPR) CRC Cyclic redundancy check CSU Channel service unit CVC Code violation counter DCO Digitally controlled oscillator DL Digital loop DPLL Digitally controlled phase locked loop DS1 Digital signal level 1 EA Extended address (special bit in PPR) PRBS Pseudo Random Binary Sequence LOS Loss of Signal LOF Loss of Frame WAN Wide Area Network DMA Direct Memory Access ACCM Asynchronous Control Character Map FCM Frame Check Sum DWORD Double Word ( 4 bytes ) DMU Data Management Unit Data Sheet 422 05.2001 PEB 3456 E List of Abbreviations Data Sheet 423 05.2001 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG