TE3-CHATT
Channelized T3 Termination with
DS3 Framer, M13 Multiplexer, T1/
E1 Framers and 256 Channel
HDLC/PPP controller
PEB 3456 E Version 2.1
Data Sheet, DS2, May 2001
Datacom
Never stop thinking.
Edition 05.2001
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 5/21/01.
All Rights Reserved.
Atten t io n please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineo n Techn olog i es is an approved CECC manufacturer.
Information
For furthe r information on technology, del ivery term s and conditions and prices please contact y our nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon T e chnologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Datacom
TE3-CHATT
Channelized T3 Termination with
DS3 Framer, M13 Multiplexer, T1/
E1 Framers and 256 Channel
HDLC/PPP controller
PEB 3456 E Version 2.1
Data Sheet, DS2, May 2001
Never stop thinking.
PEB 3456 E
Data Sheet 4 05.2001
Revision History: 05.2001 DS2
Previous Version: Preliminary Data Sheet 11.1999
Major changes to document since last version
Page Description
27 Pin Diagram Added
162 Corrected Part Number from 0076 to 0077.
208 Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER
registe r as their bit postitions we re not correct in the prelim inary data shee t.
209 Sw ap the posti ons of TBRTC wit h TBFTC in Table 8-7, as their column
positions were not correct in the preliminary data sheet
213 Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD
243 Fixed typo in IQMASK, replaced ROFD with RFOD
256 Added note to clarify configuration of FDL links 28 and 29.
263 Added special programming note for reseting D3CLKCS register
268 Added text to clarify function of TXBIT in D3TCOM
268 Reset value of D3TCOM Register was incorrectly documented.
268 Note adde d to recommend seting regis ter D3TCOM to 0070 after r eset, for
normal ope rati on.
284 Note added to explain that reset value of D3RSTAT will be different after
some time.
302 Note added to explain that reset value of D2RSTAT will be different after
some time
389 Update voltage min/max information for Table 9-1 Absolute Maximum
Ratings
391 Update timing Information for Table 9-4 DC Characteristics (PCI
Interface Pins)
392 Update timing Information for Table 9-5 PCI Clock Characteristics
393 Update timing Information for Table 9-6 PCI Interface Signal
Characteristics
396 Update timing Information for Table 9-8 Intel Bus Interfa ce Timi ng
397 Intel Bus In terface Timin g Diagra m mod ified. The set up and hold ti mes f or
“LD to LRDY” was not a valid timing parameter. Instead, the setup a nd hold
parameters for “LD to LRD” were specified.
PEB 3456 E
Data Sheet 5 05.2001
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
399 Update timing Information for Table 9-9 Intel Bus Interfa ce Timi ng
(Master Mode)
399 Timing pa rameter (setup time) 67a was changed from “L D to LDRY” to ”LD
to LRD”, because it was not a valid timing parameter.
399 Timing para meter (hold tim e) 6 7b wa s c ha nge d fro m “L D t o LDRY ” to ”LD
to LRD”, because it was not a valid timing parameter.
401 Update t iming Informati on for Table 9-10 Motorola Bus Interfac e Timing
404 Update timing Information for Table 9-11 Motorola Bus Interface Timing
(Master Mode)
407 Update timing Information for Table 9-13 DS3 Transmit Cycle Timing
Revision History: 05.2001 DS2
Previous Version: Preliminary Data Sheet 11.1999
Major changes to document since last version
Page Description
PEB 3456 E
Data Sheet 6 05.2001
Preface
The Channelized T3 Termination with DS3 Framer, M13 Mu ltiplexer, T1/E1 Fram ers and
256 Channel HDLC/PPP controller is a Multichannel Protocol Controller for a wide area
of telecommunication and data communication applications.
Organization of this Document
This Data Sheet is divided into ten chapters and is organized as follows:
•Chapter 1 TE3-CHATT Overview
Gives a general description of the product and its family, lists the key features, and
presents some typical applications
.
•Chapter 2 Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and descri bes sign al s.
•Chapter 3 General Overview
This chapter provides short descriptions of all the internal functional blocks.
•Chapter 4 Functional Description
Gives a detailed description of all functions
•Chapter 5 Interfa ce Desc ri ption
This chapter provides functional diagrams of all interfaces.
•Chapter 6 Channel Programming / Reprogramming Concept
This chapter provides a detailed description of the channel programming concept.
•Chapter 7 Reset and Initialization procedure
Gives examples of the initialzation procedure and operation.
•Chapter 8 Register Description
Gives a detailed description of all on-chip registers.
•Chapter 9 Elect rical C harac ter is tics
PEB 3456 E
Data Sheet 7 05.2001
Gives a detailed description of all electrical DC and AC characteristics, and provides
timing diagrams for all interfaces.
•Chapter 10 Package Outline.
Shows the mechanical values of the device package.
PEB 3456 E
Data Sheet 8 05.2001
PEB 3456 E
Table of Contents Page
Data Sheet 9 05.2001
1 TE3-CHATT Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.1 M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.2 M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1.3 Frame Alignment T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.4 Signaling Controller T1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.5 Frame Alignment E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.6 Signaling Controller E1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.7 Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3 General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2 Pin Definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.5 Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7 Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8 Power Supply, Reserved Pins and No-connect Pins . . . . . . . . . . . . . . . . . 45
3 Ge neral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 Internal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.4 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1 Port Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.1.1 Local Port Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.2 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.3 Test Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2 Time slot Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.1 Channelized Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.2 Unchannelized Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 Data Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.1 Descriptor Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.2 Receive Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.3 Data Management Unit Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.4 Transmit Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3.5 Data Management Unit Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.3.6 Byte Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.3.7 Transmission Bit/Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PEB 3456 E
Table of Contents Page
Data Sheet 10 05.2001
4.4 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.4.1 Internal Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.4.2 Internal Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.5 Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.5.1 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.5.2 Bit Synchronous PPP with HDLC Framing Structure . . . . . . . . . . . . . . 77
4.5.3 Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5.4 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.6 T1 Framer and FDL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.6.1 4-Frame Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6.2 ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6.2.1 Multiframe Synchronization Procedure of the Receiver . . . . . . . . . . . 81
4.6.2.2 CRC-6 Generation / Check according to ITU-T G.706 . . . . . . . . . . . 81
4.6.2.3 Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . 82
4.6.2.4 Facility Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.6.3 SF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.6.3.1 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 85
4.6.3.2 Remote Alarm (Yellow Alarm) Generation / Detection . . . . . . . . . . . 86
4.6.4 Common Features for SF and ESF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.4.1 AIS (Blue Alarm) Generation/Detection . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.4.2 Loss of Signal (Red Alarm) Detection . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.4.3 In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . . 88
4.6.4.4 Pulse Density Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6.4.5 Error Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6.4.6 Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . . 89
4.7 E1 Framing and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.1 Doubleframe Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.7.1.1 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 90
4.7.1.2 A-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.7.1.3 Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.7.2 CRC-4 Multiframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.7.2.1 Synchronization Procedure of the Receiver . . . . . . . . . . . . . . . . . . . 93
4.7.2.2 CRC-4 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.7.2.3 A-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.7.2.4 Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.7.2.5 E-Bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.7.3 Common Features for E1 Doubleframe and CRC-4 Multiframe . . . . . . 98
4.7.3.1 Error Performance Monitoring and Alarm Handling . . . . . . . . . . . . . . 98
4.7.3.2 Loss of Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.7.3.3 In-Band Loop Generation and Detection . . . . . . . . . . . . . . . . . . . . . 100
4.7.3.4 Pseudo-random Bit Sequence Generator and Monitor . . . . . . . . . . 100
4.8 Signaling Controller Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PEB 3456 E
Table of Contents Page
Data Sheet 11 05.2001
4.8.1 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.8.2 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.8.3 BOM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.8.4 Sa-bit Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.8.5 Signalling Controller FIFO Operations . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.9 M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . 108
4.9.1 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.9.1.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.9.1.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.9.1.3 Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.9.1.4 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.9.2 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.9.2.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.9.2.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.9.2.3 Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.9.2.4 Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.9.2.5 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.10 M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.10.1 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.10.1.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.10.1.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.10.1.3 X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.10.1.4 Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.10.1.5 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.10.1.6 Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.10.2 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.10.2.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.10.2.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.10.2.3 X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.10.2.4 Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . 118
4.10.2.5 Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . . . . . . . . 118
4.10.2.6 Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.10.2.7 Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.10.2.8 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.10.2.9 Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.10.3 Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.11 Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.12 Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.13 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.13.1 Layer Two interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.13.1.1 General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.13.1.2 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PEB 3456 E
Data Sheet 12 05.2001
4.13.1.3 Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.13.1.4 Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.13.1.5 Command Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.13.2 Layer One Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.13.2.1 General Interrupt Vector Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 138
4.13.2.2 T1/E1 Framer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.13.2.3 Facility Data Link Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.13.2.4 DS3, DS2 and Test Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.13.2.5 Mailbox Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.1.1 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.1.2 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.2 SPI Interface (ROM Load Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.2.1 Accesses to a SPI EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.2.2 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.2.3 SPI Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.3 Local Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.1 Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1.1 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.2 Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.3.2.1 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.3.2.2 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.4 Serial Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6 Channel Programming / Reprogramming Concept . . . . . . . . . . . . . . 163
6.1 Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.2 Transmit Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3 Receive Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
7 Reset and Initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.1 Chip Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.2 Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.1.1 PCI Configuration Register Set (Direct Access) . . . . . . . . . . . . . . . . . 171
8.1.2 PCI Slave Register Set (Direct Access) . . . . . . . . . . . . . . . . . . . . . . . . 173
8.1.3 PCI and Local Bus Register Set (Direct Access) . . . . . . . . . . . . . . . . . 175
8.1.4 Transmit T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . 180
8.1.5 Receive T1/E1 Framer Registers (Indirect Access) . . . . . . . . . . . . . . . 181
8.1.6 Facility Data Link Registers (Indirect Access) . . . . . . . . . . . . . . . . . . . 182
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Data Sheet 13 05.2001
8.2 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.2.1 PCI Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
8.2.2 PCI Slave Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
8.2.2.1 Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.2.2.2 Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.2.2.3 T1/E1 Tributary Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.2.2.4 Test Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.2.3 Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.2.3.1 DS3, DS2 and Test Unit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3 M12 Multiplexer/Demultiplexer and DS2 framer . . . . . . . . . . . . . . . . . . . 215
8.3.1 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.1.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.1.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.1.3 Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.1.4 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2.3 Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2.4 Remote Alarm Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.3.2.5 Alarm Indication Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4 M23 multiplexer and DS3 framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.3 X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.4 Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.5 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.1.6 Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.1 Synchronization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.2 Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.3 X-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.4 Far End Alarm and Control Channel . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.5 Path Maintenance Data Link Channel . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.6 Loopback Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.7 Alarm Indication Signal, Idle Signal . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.8 Loss of Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.2.9 Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.4.3 Full Payload Rate Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.5 Test Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.5.1 Local Port Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.5.2 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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Data Sheet 14 05.2001
8.5.3 Test Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.7 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.8 General System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.8.1 Bit Error Rate Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.8.2 M12 Multiplexer and DS2 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.8.3 M23 Multiplexer and DS3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9.1 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9.1.1 DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9.1.2 DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9.1.3 M13 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
8.9.2 PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . 247
8.9.2.1 M13 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.9.2.2 DS2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 293
8.9.3 Test Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.9.4 Transmit Framer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.9.5 Receive Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
8.9.6 Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
9 Electrical Char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
9.1 Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
9.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
9.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
9.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
9.4.1 PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
9.4.2 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
9.4.3 Local Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 395
9.4.3.1 Intel Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . 395
9.4.3.2 Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . 397
9.4.3.3 Motorola Bus Interface Timing (Slave Mode) . . . . . . . . . . . . . . . . . 400
9.4.3.4 Motorola Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . 402
9.4.4 tCYC is the clock period of the PCI clock.Serial Interface Timing . . . . 406
9.4.4.1 DS3 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
9.4.4.2 Overhead Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
9.4.4.3 Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
9.4.4.4 T1/E1 Tributary Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
9.4.4.5 Test Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
9.4.5 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
9.4.6 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
11 List of Abbrev iations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
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List of Figures Page
Data Sheet 15 05.2001
Figure 1-1 TE3-CHATT Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 1-2 System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-1 TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3-1 TE3-CHATT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4-1 Port configuration in M13 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 4-2 Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4-3 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4-4 Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 4-5 Time slot Assignment in Channelized Modes . . . . . . . . . . . . . . . . . . . 58
Figure 4-6 Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-7 Receive Buffer Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 4-8 Transmit Buffer Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 4-9 HDLC Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure. . . . . . . . . . . . . . 77
Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithms. . . . . . . . . . . . . . . 95
Figure 4-12 Interrupt Driven Reception Sequence Example. . . . . . . . . . . . . . . . . 107
Figure 4-13 Interrupt Driven Transmit Sequence Example. . . . . . . . . . . . . . . . . . 108
Figure 4-14 Test Unit Access Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 4-15 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 4-16 Mailbox Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 4-17 Layer Two Interrupts (Channel, command, port and system interrupts. . .
124
Figure 4-18 Interrupt Queue Structure in System Memory . . . . . . . . . . . . . . . . . . 125
Figure 4-19 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . .
137
Figure 5-1 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 5-2 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 5-3 SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 5-4 SPI Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 5-5 Intel Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 5-6 Intel Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 5-7 Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 5-8 Motorola Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 5-9 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 5-10 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 161
Figure 8-1 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-2 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 215
Figure 8-3 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-4 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-5 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-6 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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List of Figures Page
Data Sheet 16 05.2001
Figure 8-7 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-8 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-9 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-10 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-11 T1/E1 Test Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-12 Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-13 Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-14 Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . .
215
Figure 8-15 Test Unit Access Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-16 Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-17 Port configuration in M13 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-18 Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-19 Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-20 Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-21 TE3-CHATT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-22 TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-23 System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-24 TE3-CHATT Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-25 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-26 DS3 Transmit Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-27 DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 8-28 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 9-1 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 9-2 PCI Clock Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Figure 9-3 PCI Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . 392
Figure 9-4 PCI Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . 393
Figure 9-5 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Figure 9-6 Intel Read Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 9-7 Intel Write Cycle Timing (Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 9-8 Intel Read Cycle Timing (Master Mode, LRDY controlled) . . . . . . . . 397
Figure 9-9 Intel Write Cycle Timing (Master Mode, LRDY controlled). . . . . . . . . 397
Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled) . . . . . 398
Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled) . . . . . 398
Figure 9-12 Intel Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 9-13 Motorola Read Cycle Timing (Slave Mode). . . . . . . . . . . . . . . . . . . . 400
Figure 9-14 Motorola Write Cycle Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . 400
Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled). . . 402
Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled). . . 402
Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled). . 403
Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled). . 403
Figure 9-19 Motorola Bus Arbitration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
PEB 3456 E
Data Sheet 17 05.2001
Figure 9-20 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 9-21 DS3 Transmit Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 9-22 DS3 Transmit Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Figure 9-23 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 9-24 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 9-25 DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 410
Figure 9-26 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Figure 9-27 DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 9-28 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 9-29 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 9-30 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 414
Figure 9-31 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Figure 9-32 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 9-33 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Figure 9-34 T1/E1 Test Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 9-35 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 9-36 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
PEB 3456 E
Data Sheet 18 05.2001
PEB 3456 E
List of Tables Page
Data Sheet 19 05.2001
Table 4-1 Receive Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 4-2 Transmit Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 4-3 Example for little/big Endian with BNO = 3 . . . . . . . . . . . . . . . . . . . . . 72
Table 4-4 Example for little big Endian with BNO = 7 . . . . . . . . . . . . . . . . . . . . . 72
Table 4-5 4-Frame Multiframe Structure.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 4-6 ESF Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 4-7 SF Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 4-8 Allocation of Bits 1 to 8 of Time slot 0 . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 4-9 CRC-4 Multiframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 4-10 Summary of Alarm Detection and Alarm Release . . . . . . . . . . . . . . . . 98
Table 4-11 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 4-12 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 4-13 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 4-14 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 4-15 Interrupt Vector Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 5-1 Correspondence between PCI memory space and chip select. . . . . 152
Table 5-2 C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode) . . . . 155
Table 5-3 C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode) . . . 155
Table 5-4 C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode) 158
Table 5-5 C/BE to LA/LSIZE0 mapping in Motorola bus mode (16 bit port mode) . .
158
Table 6-1 Channel Specification Registers and Channel Commands . . . . . . . . 163
Table 8-1 PCI Configuration Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 8-2 PCI Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 8-3 PCI and Local Bus Slave Register Set . . . . . . . . . . . . . . . . . . . . . . . 175
Table 8-4 Transmit T1/E1 Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 8-5 Receive T1/E1 Framer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 8-6 Facility Data Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 8-7 Threshold Codings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 8-8 DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-9 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-10 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-11 DS3 Transmit Stuff Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-12 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-13 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-14 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-15 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-16 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-17 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-18 Test T1/E1 Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-19 M12 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-20 ITU-T G.747 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
PEB 3456 E
Data Sheet 20 05.2001
Table 8-21 M23 multiplex format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-22 C-bit parity format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-23 Clock Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-24 DS3 Transmit Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-25 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 8-26 Signalling Controller Transmit Commands . . . . . . . . . . . . . . . . . . . . 374
Table 9-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Table 9-2 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Table 9-3 DC Characteristics (Non-PCI Interface Pins). . . . . . . . . . . . . . . . . . . 390
Table 9-4 DC Characteristics (PCI Interface Pins). . . . . . . . . . . . . . . . . . . . . . . 391
Table 9-5 PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Table 9-6 PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 393
Table 9-7 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Table 9-8 Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Table 9-9 Intel Bus Interface Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . 399
Table 9-10 Motorola Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Table 9-11 Motorola Bus Interface Timing (Master Mode). . . . . . . . . . . . . . . . . . 404
Table 9-12 Clock Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Table 9-13 DS3 Transmit Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Table 9-14 DS3 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Table 9-15 DS3 Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
Table 9-16 DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Table 9-17 DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Table 9-18 DS3 Transmit Stuff Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Table 9-19 DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Table 9-20 T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Table 9-21 T1/E1 Tributary Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . 414
Table 9-22 T1/E1 Test Transmit Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Table 9-23 T1/E1 Test Transmit Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Table 9-24 T1/E1 Test Receive Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Table 9-25 Test T1/E1 Receive Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Table 9-26 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Table 9-27 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
PEB 3456 E
Data Sheet 21 05.2001
PEB 3456 E
TE3-CHATT Overview
Data Sheet 22 05.2001
1 TE3-CHATT Overview
The TE3-CHATT is a highly integrated protocol controller that implements HDLC, PPP
and tr anspa rent (TM A) protoc ol proc essing for 2 56 channe ls as wel l as frame align ment
for up to 28 T1 signals or 21 E1 signals. An integrated M13 multiplexer together with a
DS3 fram er con centrates the da ta link s for d irect c onnecti on t o a DS3 l ine int erface unit.
Option ally the device supp orts unchannel ized DS3 applicati ons. An internal bit error rate
tester can be attached to different test points and provides flexible PRBS and fixed
pattern tests. An on-chip data management unit is optimized to transfer data packets via
a PCI interface by minimizing the bus load.
Note: The TE3-CHATT does not contain DS3 Line Interface Units.
1.1 General Features
• Protocol processing on a channelized or unchannelized DS3 link for frame relay or
router applications
• Direct connection to DS3 line interface unit or DS3 to STS-1 mapper
• Support of 256 bidirectional channels, which can be assigned arbitrarily to a maximum
of 28 links, for HDLC, PPP or transparent mode (TMA) processing
• Concatenation of any, not necessarily consecutive, time slots to logical channels on
each physical link. Supports DS0, fractional T1/E1 or T1/E1 channels
• Provides 32kB data buffer in transmit direction and 12kB data buffer in receive
direction
• Integrates 28T1/21E1 framers (frame alignment function) and 28T1/21E1 signalling
controllers
• Integrates a DS2/DS3 multiplexer and framer
• Remote loopbacks selectable for either DS3 signal, DS2 signal or T1/E1 signal/
payload
• System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which
supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM
interface. PCI bus interface can be operated in the range of 33 MHz to 66 MHz
• Integrates a local microprocessor master and slave interface (demultiplexed 16 bit
address and data bus in Intel mode or Motorola mode) which allows access to the
local bus via the PCI bus or which can communicate with a PCI host processor
through an on-chip mailbox
• For debugging purposes optional access to the framer and signalling controller
functions via the PCI interface
• JTAG boundary scan according to IEEE1149.1 (5 pins).
• 0.25 µm, 2.5V core technology
• I/Os are 3.3V tolerant and have 3.3V driving capability
• Package P-BGA 388 (35mm x 35mm; pitch 1.27mm)
PEB 3456 E
TE3-CHATT Overview
Data Sheet 23 05.2001
• Full scan path and BIST of on-chip RAMs for production test
• Performance: 45Mbit/s (DS3) throughput per direction
• Estimated power consumption: 2W
• Also available as device with extended temperature range -40..+85°C
1.1.1 M12 Multiplexer and DS2 Framer
• Multiplexing/Demultiplexing of four asynchronous DS1 bit streams into/from M13
asynchronous format
• Multiplexing/Demultiplexing of 3 E1 signals int o/from ITU G.747 compl iant DS2 signal.
• DS2 line loopback detection/generation
• Framing according to ANSI T1.107, T1.107a or ITU-T G.747
• Insertion and extraction of X-bit
• Insertion and Extraction of alarms (remote alarm, AIS)
• Detection of AIS in presence of BER 10-3
• Alarm and performance monitoring (framing bit errors, parity errors)
• Reframe time below 7ms (TR-TSY-000009) for DS2 format and below 1 ms for ITU
G.747 format
• Bit Stuffing/Destuffing in M12 multiplex format or C-bit parity format
1.1.2 M23 Multiplexer and DS3 Framer
• Multiplexing/demultiplexing of seven DS2 into/from M13 asynchronous format
according to ANSI T1.107, ANSI T1.107a
• Multiplexing/demultiplexing of seven DS2 into/from C-bit parity format according to
ANSI T1.107, ITU-T G.704
• DS3 framing according to ANSI T1.107, T1.107a, ITU-T G.704
• Support of unipolar and B3ZS encoded signals
• Provides access to the DS3 overhead bits and the DS3 stuffing bits via a serial clock
and data interface (overhead interface)
• Insertion and Extraction of alarms according to ANSI T1.404 (remote alarm, AIS, far
end receive failure)
• Supports HDLC (Path Maintenance Data Link) and bit oriented message mode (Far
End Alarm and Control Channel) in C-bit parity mode. An integrated signalling
controller provides 2x32 byte deep FIFO’s for each direction of both channels
• Detection of AIS and idle signal in presence of BER 10-3
• Detection of excessive zeroes and LOS
• Alarm and performance monitoring with 16-bit counters for line code violations,
excessiv e zeroe s, pari ty e rror (P -bit), framin g er rors (F-bi t erro rs wi th o r with out M-b it
errors, far end block error (FEBE-bit) and CP-bit errors.
• Automatic insertion of severely errored frame and AIS defec t indi cati on
PEB 3456 E
TE3-CHATT Overview
Data Sheet 24 05.2001
1.1.3 Frame Alignment T1 Features
• Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704
• Supports T1 frame alignment for F4, SF (F12) and ESF (F24) mode
• Error checking via CRC-6 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC, framing errors, loss of frame alignment,
loss of signal AIS
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm)
• Dete ction of LOS (Red Alarm )
• Pseudo-random bit sequence generator and monitor for one logical channel
according to ITU-T O.151
• Programmable in-band loop code detection/generation according to TR 62411
1.1.4 Signaling Controller T1 Features
• FDL-channel protocol for ESF format according to ANSI T1.403 specification or
according to AT&T TR54016
• Supports HDLC mode with address recognition
• Supports BOM mode
• FIFO Buffers (64 bytes deep) for efficient transfer of data packets
1.1.5 Frame Alignment E1 Features
• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704
• Programmable formats: Doubleframe, CRC-4 Multiframe
Selectable conditions for recover / loss of frame alignment
• CRC-4 to Non-CRC-4 Interworking of ITU-T G.706 Annex B
• Error checking via CRC-4 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC-, framing errors, error monitoring via E-
bit and Sa6 bit
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, ...)
• Pseudo-random bit sequence (PRBS) generator and monitor for one logical channel
• Programmable in-band loop code detection / generation according to TR 62411
1.1.6 Signaling Controller E1 Features
• HDLC controller with address recognition and programmable preamble
• Tim e slot 0 Sa8-4 HDLC handling via FIFOs
• HDLC access to any Sa-bit combination
• FIFO Buffers (64 byte deep) for efficient transfer of data packets
1.1.7 Bit Error Rate Tester
• User specified PRBS/Fixed Pattern with programmable length of 1 to 32 bits
• Optional Bit Inversion
PEB 3456 E
TE3-CHATT Overview
Data Sheet 25 05.2001
• Two error insertion modes: Single or programmable bit rates
• Optional zero suppression
• 32-bit counters for errors and received bits
• Programmable bit intervals for receive measurements
1.2 Logic Symbol
•
Figure 1-1 TE3-CHATT Logic Symbol
1.3 General System Integration
The TE3-CHATT provides the HDLC/PPP protocol handling, T1/E1 framing and
signal lin g fun cti ons , an inte grat ed M 13 m ul tipl ex er an d a D S3 fram er . The l ine inte rfac e
of the TE3-CHATT directly connects to a DS3 line interface unit. Protocol data is
TE3-CHATT
PEB 3456 E
V
SS
V
DD25
V
DD3
TRST
TMS
TDO
TDI
TCK
SCAN
JTAG
RD44N
RD44P
RC44
TD44P
TD44N
TC44
Serial
Interface
TC44O
CTFS
CTCLK
LMODE
LA(12:0)
LD(15:0)
LHOLD/LBR
LHLDA/LBG
LBGACK
LCLK
LCS0
LCS1
LBHE/LSIZE0
LINT
LRDY/LDTACK
LRD/LDS
LWR/LRDWR
Local
Bus
LCS2
TOVHCK
TOVHD
TOVHDEN
TOVHSYN
TSBD
TSBDCK
ROVHCK
ROVHD
ROVHSYN
RSBD
RSBDCK
Overhead
Bits
SPCLK
SPLOAD
SPO
SPI
SPCS
SPI
TM
PCI
AD[31:0]
C/BE[3:0]
PAR
FRAME
IRDY
TRDY
STOP
IDSEL
PERR
SERR
REQ
GNT
CLK
RST
INTA
DEVSEL
DS3
Status
Signals
Test and
Reference
Signals
RRED
RLOF
RAIS
RLOS
TTD
TRD
TTCLK
TRCLK
RSPO
PEB 3456 E
TE3-CHATT Overview
Data Sheet 26 05.2001
transferred to the packet RAM via the PCI bus and handled (e.g. for layer3 protocol
handling) by the line card processor. An external processor provides control of the
integrated T1/E1 framer, M13 multiplexer, DS3 framer and the signalling channels. A
mailbox allows the transfer of information between both CPUs.
•
Figure 1-2 System Integration of the TE3-CHATT
DS3 LIU
Local CPU
PCI
Bus
TE3-CHATT
Backplane
Connection
Router
Backplane
Packet
RAM
Linecard
Processor
T3 Linecard
PEB 3456 E
Pin Description
Data Sheet 27 05.2001
2 Pin Description
2.1 Pi n Diagra m
(Top view)
Figure 2-1 TE3-CHATT Pin Configuration
VDD3 RES58
RES54 RES60
RES59
RES57 RES61
RES63
RES65
VDD3
RES67
RES69
RES66 RES68
RES70
VSS RLOF
RLOS
RAIS
RRED
RES75
RES76
RES77
RES79
RES82
RES80 RES81
TD44N
RES83
TD44/
TD44P
RSPO/
TRCLK
RES84
TDO
NC12
TCK
TRST
NC14
NC15
NC13
VSS
RES5
NC4
RES90
RES1
RES93
RES2 RES6
RES3
NC26
NC27
NC25
NC30
LRD/
LDS
LD(4)
LD(3) NC22
LD(1)
LD(2)
VSS
LD(0)
VDD3
TMS
RES74
RES78
RES73
SCAN
VDD25
TDI
VDD25
RES62
VSS
RES71
RES72
RES56RES53
RES55TRD
TC44O
RES51TTCLK
VDD3RES47
RES52
RES9
RES25RES23
RSBCK
ROVH
SYN
TSBD
TOVH
CK
RES91
TSBCK
TOVH
D
RES92
RES89
TOVHE
N
RES4
NC6
NC5
NC2
NC3
NC0
RC44
RD44N RES86
RES85
CTFS
RD44/
RD44P
TTD
RES87
RSBD
CTCLK
RES88
TOVHS
YNC
ROVH
CK
NC7
RES7
RES20
RES21RES8
RES27
TC44
RES24
RES22
RES11
LA(3)
LA(8)
AD(1)
RST
SPO
LA(6) LBHE/
LSIZE0
INTA
AD(2)
AD(4)
LA(12)
LA(7)
LA(11) AD(12)
AD(14)
AD(15)
AD(13)
LD(12)
LD(9)
LD(6)
LA(1)
LD(10)
LD(13)
LA(0)
VDD3 LD(14)
LD(15)
LA(4)
NC29
C/
BE(2)
STOP
NC31
NC28
FRAM
E
VSS
VSS
VSS
VSS
VSS
VSSVSS
VSS
VSS
VSS
AD(16)
VSSVSS
VSSVSS
VSSVSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSSVSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSSVSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSSVSS
VSSVSS
NC1VSSVSS
VSS
VSS
VSS
VSSVSS
VSS
VDD25
VDD25
VDD25
VDD25VDD25
VDD25
VDD25
VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25VDD25
VDD25
VDD25
VDD25
VDD25VDD25
VDD25
VDD25
VDD25
VDD3
VDD3VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3VDD3
AD(22)
C/
BE(3)
VDD3
VDD3
AD(31)
VDD3
SPCLKVDD3
RES14
VDD3
VDD3
RES64
VDD3VDD3
VDD3
VDD3
VDD3
ROVH
D
VDD3
VDD3
VDD3VDD3
VDD3
RES44 RES40 VDD3
RES43 LBGAC
K
RES38 RES37 LMOD
E
LCS2
LWR/
LRD
WR
NC17
NC23
LD(5)
NC16
NC18
NC20
RES39RES41
LCS1
RES36
LCLK
LHOLD
/LBR
LCS0
LHLDA/
LBG
LINT
LRDY
RES29
RES12RES10
RES26
RES49RES50
RES42RES45
RES48 RES46
LD(7) LD(2)
LA(5)
LA(10)
LA(9)
AD(0)
AD(3) AD(7)
AD(5) AD(6)
AD(27)
AD(30)
AD(26)
REQ
CLK
AD(29)
GNT
SPLOA
DSPI
RES34
AD(20)
AD(18)
AD(21)
AD(19)
AD(23)
VDD3
AD24
IDSEL
AD(25)
AD(28)
AD(8)
C/
BE(0)
AD(9)
AD(10)
AD(11)
C/
BE(1)
PAR
SERR
IRDY
AD(17)
RES35
RES31
SPCS
RES30
RES32
RES16
RES13
RES33
RES28
RES15
NC19
LD(8)
LD(11)
NC21
1234567891011121314151617181920212223242526
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
PERR
TRDY
NC24
DEVSE
L
PEB 3456 E
Pin Description
Data Sheet 28 05.2001
2.2 Pin Definition and functions
Signal Type Definition s:
The following signa l type definitions are partly taken from the PCI Specification Rev. 2. 1:
IInput is a standard in put- only si gnal .
OTotem Pole Output is a standard active driver.
t/s, I/O Tri-State or I/O is a bidirectional, tri-state input/output pin.
s/t/s Sust ain ed Tri -Stat e is an ac tiv e lo w tri-s tate signal owned and dr iven by
one and only a gen t at a time. T he a gent th at drive s an s /t/s pin low mus t
drive it high for at least one clock before letting it float. A new agent
cannot start driving a s/t/s signal any sooner than one clock after the
previous owner tri-states it. A pullup is required to sustain the inactive
state until another agent drives it, and must be provided by the central
resource.
o/d Op en D rai n all ow s multiple devic es to sh are a li ne a s a w ire-OR . A pul l-
up is required to sustain the inactive state until another agent drives it,
and m ust be provided by the central resource.
Signal Name Conventio ns:
NCn No-co nne ct Pin n
Such pins are not bonded with the silicon. Although any potential at
these pins will not impact the device it is recommended to leave them
unconn ec ted . N o-c onn ec t pi ns m ig ht b e us ed for a ddi tio nal fun cti ona lity
in later vers ions of the device. Leavi ng them unconnected will guarantee
hardware compatibility to later device versions.
Reserved Reserve d pins are f or vendor spec ific use only a nd shoul d be conne cted
as recommended to guarantee normal operation.
Note: The signal type definition specifies the functional usage of a pin. This does not
reflect necessarily the implementation of a pin, e.g. a pin defined of signal type
‘Input’ may be implemented with a bidirectional pad.
PEB 3456 E
Pin Description
Data Sheet 29 05.2001
2.3 PCI Bus Interface
•
Pin No. Symbol Input (I)
Output (O) Function
T3, T4, U1, U3,
V2, W1, W2,
V4, AA2, W4,
AC1, AB2, Y3,
Y4, AD1, AC2,
AC8, AE6,
AD8, AF6,
AC9, AE8,
AF7, AD10,
AC11, AF8,
AF10, AD11,
AC12, AE11,
AD12, AF11
AD(31:0) t/s Address/Data Bus
A bus transaction consists of an address
phase followed by one or more data
phases.
When the TE3-CHATT is the bus master,
AD(31:0) are outputs in the address
phase of a transaction. During the data
phases, AD (31:0) remain outputs for write
transactions, and become inputs for read
transactions.
When the TE3-CHATT is bus slave,
AD(31:0) are inputs in the address phase
of a transaction. During the data phases,
AD(31:0) remain inputs for write
transactions, and become outputs for
read transactions.
AD(31:0) are tri-state when the TE3-
CHATT is not involved in the current
transaction.
AD(31:0) are updated and sampled on
the rising edge of CLK.
PEB 3456 E
Pin Description
Data Sheet 30 05.2001
V3, AA4, AD7,
AE9 C/BE(3:0) t/s Command/Byte Enable
During the address phase of a
transaction, C/BE(3:0) define the bus
command. During the data phase, C/
BE(3:0) are used as byte enable lines.
The byte enable lines are valid for the
entire data phase and determine which
byte lanes carry meaning ful data. C/ BE(0)
applies to byte 0 (LSB) and C/BE(3)
applies to byte 3 (MSB).
When the TE3-CHATT is bus master, C/
BE(3:0) are outputs.
When the TE3-CHATT is bus slave, C/
BE(3:0) are inputs.
C/BE(3:0) are tri-stated when the TE3-
CHATT is not involved in the current
transaction.
C/BE(3:0) are updated and sampled on
the rising edge of CLK.
AF4 PAR t/s Parity
PAR is even parity across AD(31:0) and
C/BE(3:0). PAR is stable and valid one
clock after the address phase. PAR has
the same timing as AD(31:0) but delayed
by one clock.
When the TE3-CHATT is Master, PAR is
output during address phase and write
data phases and input during read data
phase. When the TE3-CHATT is Slave,
PAR is out put during read data phase an d
input du ring write data phas e.
PAR is tri- sta ted w hen the TE3 -C HA TT is
not involved in the current transaction.
Parity errors detected by the device are
indicated on PERR output.
PAR is updated and sampled on the rising
edge of CLK.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 31 05.2001
AB3 FRAME s/t/s Frame
FRAME indicates the beginning and end
of an access. FRAME is asserted to
indicate a bus transaction is beginning.
While FRAME is asserted, data transfers
continue. When FRAME is deasserted,
the transacti on is in the fina l phas e.
When the TE3-CHATT is bus master,
FRAME is an output. When the TE3-
CHATT is bus slave, FRAME is an input.
FRAME is tri-stated when the TE3-
CHATT is not involved in the current
transaction.
FRAME is updated and sampled on the
rising edge of CLK.
AC6 IRDY s/t/s Initiator Ready
IRDY indicates the bus master’s ability to
complete the current data phase of the
transaction. It is used in conjunction with
TRDY. A data p has e i s c ompl eted on an y
clock where both IRDY and TRDY are
sampled asserted. During a write, IRDY
indicates that valid data is present on
AD(31:0). During a read, it indicates the
master is prepared to accept data. Wait
cycles are inserted until both IRDY and
TRDY are asserted together.
When the TE3-CHATT is bus master,
IRDY is an output. Whe n the TE3-CH ATT
is bus slave, IRDY is an input. IRDY is tri-
stated, when the TE3-CHATT is not
involve d in the curre nt transaction.
IRDY is updated and sampled on the
rising edge of CLK.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 32 05.2001
AD5 TRDY s/t/s Target Ready
TRDY indicates a slave’s ability to
complete the current data phase of the
transaction. During a read, TRDY
indicates that valid data is present on
AD(31:0). During a write, it indicates the
target is prepared to accept data.
When the TE3-CHATT is Master, TRDY is
an input. When the TE3-CHATT is Slave,
TRDY is an output. TRDY is tri-stated,
when the TE3-CHATT is not involved in
the current transa cti on.
TRDY is updated and sampled on the
rising edge of CLK.
AF3 STOP s/t/s Stop
STOP is used by a slave to request the
current master to stop the current bus
transaction.
When the TE3-CHATT is bus master,
STOP is a n in pu t. Wh en the TE 3-C HA T T
is bus slave, STOP is an output. STOP is
tri-stated, when the TE3-CHATT is not
involve d in the curre nt transaction.
STOP is updated and sampled on the
rising edge of CLK.
AA1 IDSEL I Initialization Device Select
When the TE3-CHATT is slave in a
transaction, where IDSEL is active in the
address phase and C/BE(3:0) indicates
an configuration read or write, the TE3-
CHATT assumes a read or write to a
configuration register. In response, the
TE3-CHATT asserts DEVSEL during the
subsequent CLK cycle.
IDSEL is sampled on the rising edge of
CLK.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 33 05.2001
AE4 DEVSEL s/t/s Devi ce Select
When activated by a slave, it indicates to
the current bus master that the slave has
decoded its address as the target of the
current transaction. If no bus slave
activates DEVSEL within six bus CLK
cycles, the master should abort the
transaction.
When the TE3-CHATT is bus master,
DEVSEL is input. If DEVSEL is not
activated within six clock cycles after an
address is output on AD(31:0), the TE3-
CHATT aborts the transaction.
When the TE3-CHATT is bus slave,
DEVSEL is output. DEVSEL is tri-stated,
when the TE3-CHATT is not involved in
the current transa cti on.
AC7 PERR s/t/s Parity Error
When activated, indicates a parity error
over the AD(31:0) and C/BE(3:0) signals
(compared to the PAR input). It has a
delay of two CLK cycles with respect to
AD and C/BE(3:0) (i.e., it is valid for the
cycle immediately following the
corresponding PAR cycle).
PERR is asserted relative to the rising
edge of CLK.
AE5 SERR o/d System Error
The TE3-CHATT asserts this signal to
indicate an address parity error and report
a fatal system error.
SERR is an open drain output activated
on the rising edge of CLK.
T2 REQ t/s Request
Used by the TE3-CHATT to request
control of the PCI bus. It is tri-state during
reset.
REQ is activated on the rising edge of
CLK.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 34 05.2001
T1 GNT IGrant
This signal is asserted by the arbiter to
grant control of the PCI to the TE3-
CHATT in response to a bus request via
REQ. After GNT is asserted, the TE3-
CHATT will begin a bus transaction only
after the current bus Master has
deasserted the FRAME signal.
GNT is sampled on the rising edge of
CLK.
R4 CLK I Clock
Provides timing for all PCI transactions.
Most PCI signals are sampled or output
relative to the risi ng edge o f CLK. The PC I
clock is used as internal system clock.
The maximum CLK frequency is 66 MHz.
R3 RST IReset
An active RST signal brings all PCI
registers, sequencers and signals into a
consistent state. All PCI output signals
are driven to high impedance.
AC13 INTA o/d Interrupt Request
When an interrupt status is active and
unmaske d, the TE3-CHATT activates this
open-drain output.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 35 05.2001
2.4 SPI Interface
•
Pin No. Symbol Input (I)
Output (O) Function
P2 SPI I SPI Serial Input
SPI is a data input pin, where dat a coming
from an external EEPROM is shifted in.
SPI is sampled on the rising edge of
SPCLK. A pull-up resistor is
recommended if the SPI interface is not
used.
P1 SPO O SPI Serial Output
SPO is a push/pull serial data output pin.
Opcodes, byte addresses and data is
updated on the falling edge of SPCLK. It
is tri-state during reset.
N4 SPCLK O SPI Clock Signal
SPCLK controls the serial bus timing of
the SPI bus. SPCLK is derived from the
PCI bus clock with a frequency of 1/78 of
the PCI bus clock. It is tri-state during
reset.
N3 SPCS OSPI Chip Select
SPCS is used to select an external
EEPROM. It is tri-state during reset.
P4 SPLOAD I Enable SPI Load Functionality
Connecting SPLOAD to VDD3 enables the
SPI bus after reset. In this case parts of
the PCI configuration space can be
configured via an external EEPROM.
PEB 3456 E
Pin Description
Data Sheet 36 05.2001
2.5 L ocal Micr o proces so r Inte rf ace
•
Pin No. Symbol Input (I)
Output (O) Function
W24 LMODE I Local Bus Mode
By connecting this pin to either VSS or
VDD3 the bus interface can be adapted to
either Intel or Motorola environment.
LMODE = VSS selects Intel bus mode.
LMODE = VDD3 selects Motorola bus
mode.
Y24 LCLK O Local Clock
Reference output clock derived from the
PCI clock.
AE13, AF13,
AF14, AE14,
AF16, AC14,
AD15, AE16,
AF17, AC15,
AD16, AF19,
AE18
LA(12:0) I/O Address bus
These input address lines select one of
the internal registers for read or write
access.
Note: Only LA(7:0) are evaluated during
read/write accesses to the TE3-CHATT.
In local bus master mode the address
lines are output. If local bus master
functionality is disabled these pins are
input on ly.
AC16, AD17,
AF20, AE19,
AF21, AC18,
AD19, AE21,
AD20, AC19,
AF23, AE24,
AF25, AE26,
AD25, AB23
LD(15:0) I/O Data Bus
Bidirectional tri-state data lines.
Y23 LCS0 IChip Select
This active low signal selects the TE3-
CHATT as bus slave for read/write
operations.
PEB 3456 E
Pin Description
Data Sheet 37 05.2001
AC24 LRD
or
LDS
I/O
I/O
Read (Intel Bus Mode)
This active low signal selects a read
transaction.
Data strobe (Motorola Bus Mode)
This active low signal indicates that valid
data has to be placed on the data bus
(read cycle) or that valid data has been
placed on the data bus (write cycle).
AB24 LWR
or
LRDWR
I/O
I/O
Write Enable (Intel Bus Mode)
This active low signal selects a write
cycle.
Read Write Signal (Motorola Bus
Mode)
This input signal distinguishes write from
read operations.
AA23 LRDY
or
DTACK
I/O
I/O
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. The TE3-CHATT
asserts LRDY during a read cycle if valid
output data has been placed on the data
bus. In write direction LRDY will be
asserted when input data has been
latched.
In local bus master mode TE3-CHATT
evaluates LRDY to finish a transaction.
Data Transfer Acknowledge (Motorola
bus mode)
This active low input indicates that a data
transfer ma y be perf ormed. Du ring a rea d
cycle data becomes valid at the falling
edge of DTACK. The data is latched
internally an d the bus c yc le is term in ate d.
During a write cycle the falling edge of
DTACK marks the latching of data and the
bus cycle is termin ated .
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 38 05.2001
AC26 LINT I/od Interrupt Request
This line indicates general interrupt
requests of the layer one functions or the
mailbox. The interrupt sources can be
masked via regist ers.
In local bus master mode the TE3 -CHATT
can monitor external interrupts indicated
via LI NT.
AC25, W23 LCS2,
LCS1 OChip Select 2, 1
These signals select external peripherals
when TE3-CHATT is the local b us master.
As long as the local bus master
functionality is disabled these outputs are
set to tri-state.
AD13 LBHE
or
LSIZE0
O
O
Byte High Enable (Intel Bus Mode)
In local bus master mode this signal
indicates a data transfer on the upper byte
of the data bus LD(15:8).
This signal has no function in slave mode.
When local bus master functionality is
disabled this output is tri-state.
Byte Access (Motorola Bus Mode)
In local bus master mode this signal
indicates byte transfers.
This sign al has no fun ction when the T E3-
CHATT is local bus sl ave. When local bus
master functionalit y is disable d this output
is tri-state.
AA25 LHOLD
or
LBR
O
O
Bus Request (Intel Bus Mode)
This pin indicates a requests to become
local bus master.
When local bus master functionality is
disabled this output is tri-state.
Bus Request (Motorola Bus Mode)
LBR indicates a request to become local
bus master.
When local bus master functionality is
disabled this output is set to tri-state.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 39 05.2001
2.6 Serial Interface
•
AB25 LHLDA
or
LBG
I
I
Hold (Intel Bus Mode)
LHLDA indicates that the external
processor has released control of the
local bus.
Bus Grant (Motorola B us Mode )
LBG indicates that the TE3-CHATT may
access the local bus.
V23 LBGACK OBus Grant Acknowledge (Motorola
Bus Mode)
LBGACK is driven low when the TE3-
CHATT has become bus master.
When local bus master functionality is
disabled this output is tri-state.
Pin No. Symbol Input (I)
Output (O) Function
D12 CTCLK I Common Transmit Clock
CTCLK is the external transmit clock for
the T1 or E1 tributaries configured in
external timing mode.
A11 CTFS I Common Transmit Frame
Synchronization
CTFS is used to synchronize the T1/E1
transmit lines, which are clocked with
CTCLK in external timing mode.
If not used CTFS should be connected to
VSS.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 40 05.2001
C15 RSPO
or
TRCLK
O
O
Regenerated Sync Pulse
RSPO supports debugging of the on-chip
T1/E1 framing function. If the T1/E1
framer achieved synchronization, the
internal synchronization pulse of one
selected T1/E1 framer can be monitored
on RSPO.
Test Receive Clock
In serial test mode the receive clock of
one selected T1/E1 interface is directly
feed to this output.
M24 TRD O Test Receive Data
In serial test mode the incoming data
stream of one T1/E1 tributary is directly
feed to this output. Test receive data is
updated on the falling edge of the TRCLK.
N26 TTCLK I Test Transmit Clock
In serial test mo de this cl oc k pro vi des the
clock reference for the tributary provided
via TTD.
C12 TTD I Test Transmit Data
In serial test mode the data stream
provided via TTD replaces th e E1/T1 da ta
stream of the selected tributary. TTD is
sampled o n the rising edge of the TT CLK.
C14 TC44 I DS3 Transmit Clock Input
This clock provides a reference clock for
the DS3 interface. The frequency of this
clock is nominally 44. 736 MHz.
D14 TC44O O DS3 Transmit Clock Output
This output is a buffered version of the
selected transmit clock which can be set
to RC44 or TC44.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 41 05.2001
B16
TD44
or
TD44P
O
O
D3TCFG.UTD is used to select the
operating mode for this pin.
DS3 Transmit Data
In Single rail mode, this unipolar serial
data output represents the DS3 signal.
TD44 is updated on the falling or rising
edge of TC44.
DS3 Transmit Positive Pulse
In dual-rail mode this pin represents the
positive pulse of the B3ZS encoded DS3
si gnal. TD44P is updated on th e fall ing
edge or rising edge of TC44O.
C16 TD44N O DS3 Transmit Negative Pulse
In dual-rail mode this pin represents the
negative p ulse of the B3 ZS encoded DS3
signal. TD 44N is updated on the falli ng or
rising edge of TC44O.
B14 RC44 I DS3 Receive Clock Input
The frequency of this clock is nominally
44.736 MHz .
D13
RD44
or
RD44P
I
I
D3RCFG.URD is used to select the
operating mode for this pin.
DS 3 Receive Data
This unipolar serial data input represents
the DS3 signal. RD44 is sampled on the
falling or rising edge of RC44.
DS 3 Receive Positive Pulse
In dual-rail mode this pin represents the
positive pulse of the B3ZS encoded DS3
signal. RD44P is sampled on the falling or
rising edge of RC44.
A14 RD44N I DS3 Receive Negative Pulse
In dual-rail mode this pin represents the
negative p ulse of the B3 ZS encoded DS3
signal. RD44 is sampled on the falling or
rising edge of RC44.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 42 05.2001
A21 RRED O Received RED
This signal is asserte d whenever the DS3
receive framer is in RED alarm state.
B21 RLOS O Received LOS
This signal is asserted whenever the
received DS3 bit stream contained at
least 175 consecutive ‘0’s.
D19 RLOF O Rece ive LO F
This signal is asserte d whenever the DS3
receive framer is in ’Loss of frame’ state.
C19 RAIS O Received AIS
This signal is asserte d whenever the DS3
receive framer is in AIS state.
B8 TOVHCK O Transmit Overhead Bit Clock
This signal provides the bit clock for the
DS3 overhead bits of the outgoing DS3
frame. TOVHCK is nominally a 526 kHz
clock.
C8 TOVHD I Tra nsmit Overhead Data
The overhead bits of the outgoing DS3
frame can be provided via TOVHD.
Transmit overhead data is sampled on
the risi ng edge of TOVH CK and those bits
which are enabled by TOVHEN are
inserted in the overhead bit positions of
the DS3 frame.
D8 TOVHEN I Enable Transmit Overhead Data
The asserted TOVHEN signal marks the
bits to be inserted in the DS3 frame.
TOVHEN is sampled together with
TOVHD on the rising edge of TOVHD.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 43 05.2001
A8 TOVHSYN I/O Transmit Overhead Synchronization
TOVHSYN provides the means to align
TOVHD to the first M-frame of the DS3
signal. If operated in output mode
TOVHSYN it is asserted w hen the X-bit of
the 1st subframe of the DS3 overhead bits
has to be inserted via TOVHD. TOVHSYN
is updated on the rising edge of TOVHCK.
If operated in input mode TOVHSYN must
be asserted together with the X-bit of the
1st subframe of the DS3 signal which is
input on TOVHD. TOVHSYN is sampled
on the rising edge of TOVHCK.
D9 TSBCK O Transmit Stuff Bit Clock
This signal provides the bit clock for DS3
stuff bit data. Transmit stuff bit data is
sampled on the ris ing edge of TSBCK.
A7 TSBD I Transmit Stuff Bit Data
Data provided via TSBD is optionally
inserted in the stuffed bit positions of the
DS3 signal. TSBD is sampled on the
rising edge of TSBD. This function is
available in M13 asynchronous format
only.
B9 ROVHCK O Receive Ov erhead Bit Clock
This signal provides the bit clock for the
received DS3 overhead bits. ROVHCK is
nominally a 526 kHz clock.
C9 ROVHD O Receive Ov erhead Data
ROVHD contains the extracted overhead
bits of the DS 3 frame . It is update d on the
rising edge of ROVHCK.
C10 ROVHSYN OReceive Over hea d Synchronization
ROVHSYN is asserted while the X-bit of
the 1st subframe of the DS3 overhead bits
is provided via RO VHD. I t is sam pled on
the rising edge of ROVHCK.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 44 05.2001
2.7 Test Interface
•
D11 RSBCK O Receive Stuff Bit Clock
This signal provides the bit clock for DS3
stuff bit data. Transmit stuff bit data is
sampled on the ris ing edge of TSBCK.
A10 RSBD O Rece ive Stuff Bit Data
ROVHD provides data which was
inserted in the stuffed bit positions of the
DS3 signal. RSBD is updated on the
rising edge of RSBD. This function is
available in M13 asynchronous format
only.
Pin No. Symbol Input (I)
Output (O) Function
C25 TCK I JTAG Test Clock
This pin is connected with an internal pull-
up resistor.
F23 TMS I JTAG Test Mode Select
This pin is connected with an internal pull-
up resistor.
A24 TDI I JTAG Test Data Input
This pin is connected with an internal pull-
up resistor.
D24 TDO O JTAG Test Data Output
B26 TRST IJTAG Test Reset
This pin is connected with an internal pull-
down resistor.
E24 SCAN I Full Scan Path Test
When co nn ect ed to VDD3 the TE3-CHATT
works in a vendor specific test mode. It is
recommended to connect this pin to VSS.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
Pin Description
Data Sheet 45 05.2001
2.8 Power Supply, Reserved Pins and No-connect Pins
•
Pin No. Symbol Input (I)
Output (O) Function
AF1, AE7, AF9, AE12,
AE15, AF18, AE20,
AF26, AD3, AD24, AD26,
Y2, Y25, V1, V26, R2,
T12, T11, R12, R11, T14,
T13, R14, R13, T16, T15,
R16, R15, R25, P12, P11,
N12, N11, P14, P13, N14,
N13, P16, P15, N16, N15,
M2, M1 2, M 11 , L 12, L1 1,
M14, M13, L14, L13,
M16, M15, L16, L15,
M25, J1, J26, G2, G25,
C3, C24, D25, A1, B7,
A9, B12, B15, A18, B20,
A26, B23, A25
VSS IGround 0V
All pins must have the same level.
AE2, AF5, AE10, AF12,
AF15, AE17, AF22,
AE25, AB1, AB26, Y1,
Y26, U2, U25, R1, R26,
M1, M26, K2, K25, G1,
G26, E1, E26, B2, A5,
B10, A12, A15, B17, A22,
B25, C22, D21
VDD25 ISupply Voltage 2.5V ± 0.25V
All pins must have the same level.
AC4, AD6, AD9, AC10,
AD14, AD18, AC17,
AD21, AC23, AA3, AA24,
W3, U4, V24, U23, P3,
P23, N24, L24, J3, K23,
J24, H23, F3, F24, D4,
C6, D10, C13, D17, C18,
C21, D23
VDD3 ISupply Voltage 3.3V ± 0.3V
All pins must have the same level.
PEB 3456 E
Pin Description
Data Sheet 46 05.2001
B5, C5, D5, A4, B4, C4,
E3, D2, H3, H2, J4, H1,
J2, K4, K3, K1, F4, D1,
E2, G4, F2, G3, F1, H4,
L3, L4, L2, L1, M3, M4,
N1, N2, AA26, W25,
W26, T23, U24, T24,
R23, V25, U26, R24, T25,
P24, T26, P25, P26, N25,
N23, L26, K26, M23, L25,
H26, L2 3, J25, K24, H25,
F26, J23, H24, F25, G24,
D26, G23, E25, C26,
D20, B22, A23, C20, D18,
B19, A20, B18, C17, A19,
A17, D16, D15, A16, B13,
A13, B11, C11, C7, D7,
A6, B6, D6
RES1..16,
RES20..93 Reserved Pins 1..16, 20..93
A pull-up resistor to VDD3 is
recommended.
E4, C1, B1, C2, A3, A2,
B3, D3, E23, B24, C23,
D22, AC22, AD23, AD22,
AC21, AE22, AC20,
AF24, AE23, AF2, AE3,
AC5, AD4, AE1, AD2,
AB4, AC3
NC0..7
NC12..31 No-conn ect Pins 0..7 , 12..31
It is recommended not to
connect these pins.
Pin No. Symbol Input (I)
Output (O) Function
PEB 3456 E
General Overview
Data Sheet 47 05.2001
3 Gen eral Overview
3.1 Functi onal Overview
TE3-CHATT
The TE3-CHATT is a highly integrated WAN protocol controller that performs HDLC,
PPP and tr ans pa rent (TM A) prot oc ol p r oces sin g o n 25 6 fu ll d upl ex se rial ch ann el s fo r a
channel ized or unc hannelized DS3 link. The d evice prov ides the fram ing functions for 28
T1 links or 21 E1 links. Signalling controller functions for DS3, T1 and E1 mode are
integrated as well.
The foll owing opera ting modes are provided (assuming a PCI c lock freque ncy of 33 MH z
or more):
• 28 t imes T1 signa ls opera ting at 1 .54 4 MBit/s mapped into M1 3 asyn chrono us form at
or C-bit parity format
• 21 times E1 signals operating at 2.048 MBit/s mapped into ITU-T G.747 compliant
signal.
• Full payload rate DS3 signal in C-bit parity format
The serial interface operates in unipolar or dual-rail mode and connects directly to
available DS3 LIUs.
Each T1 or E1 tributary can be operated in external timing mode, where the tributary is
clocked with the common transmit clock CTCLK, or in looped timing mode, where data
of the selected tributaries is s ent synchronous to the incoming receiv e clock.
A variety of loop modes is provided to support remote as well as inloop testing of the
device. Remote loops are provided on DS3-, DS2-, DS1- or payload level.
Two bus interfaces, a PCI Rev. 2.1 compliant bus interface and a 16 bit Intel/Motorola
style bu s interface , connect the device to s ystem enviro nment. De vice conf iguration an d
channel operation is provided through the PCI bus interface, whereas the 16 bit bus
interfac e provide s access to th e framing fun ctions and the signall ing controlle r. The TE3-
CHATT supports PCI PnP capability by loading the subsystem ID and the subsystem
vendor ID via a SPITM interface into the PCI configuration space.
PEB 3456 E
General Overview
Data Sheet 48 05.2001
3.2 Block Diagram
•
Figure 3-1 TE3-CHATT Block Diagram
3.3 Internal Interface
The device consists of several macro functions as shown in Figure 3-1. The internal
modules are connected by busses/signals according to Infineons on-chip bus.
The main busses are:
• The initiator bus, on which the DMA requests of the data management units and the
interrupt controller are arbitrated and funneled into the PCI interface.
T1/E1 Interface/Unchannelized Interface
Framer
Facility data link
Message FIFO
Interrupt FIFO
Mailbox/
Bridge
Protocol handler
Internal B uffe r
Data managem ent unit
PCI Interface Local Bus Interface
Interrupt
controller
DS3 interface unipolar or
B3ZS encoded
PCI local uP interfac e
Initiator bus
SPI
TM
JTAG
interface
JTAG
Configuration bus I
Configuration bus I
Interru p t bu s I
Interrupt bus II
SPI
TM
Interface
synchronization
M13 Multiplexer
12 28
RC44
RD44P
RD44N
TC44O
TD44P
TD44N
TC44
Clock
References
CTCLK
TestPort
DS3 framer Overhead
Access
Loop buffer
BERT
PEB 3456 E
General Overview
Data Sheet 49 05.2001
• The configuration busses, which serve as the standard programming interface to
access the c hip internal registe r s and fun cti on s either v ia PC I bu s o r v ia the local bu s
interface.
• The interrupt busses, which collect all interrupt information and forward them to the
corresponding interrupt handler.
The chip’ s core functions are all operated with the PCI clock. Transfers between cloc king
regions (serial clocks and system clock) are implemented only in the serial interface.
3.4 Block Description
The following se cti on g iv es a brie f ov erv ie w t o the fun cti on o f eac h b loc k. For a detaile d
description of each function refer to “Functional Description” on Page 53.
T1/E1 Interfa ce/ Un cha nnel ize d Inter fac e
The T1/E1 interface consists of the subfunctions receive and transmit. This block
provides the function of serial/parallel and parallel/serial conversion for up to 28
incoming and up to 28 outgoing tributaries of the DS3 signal. Serial data is transferred
between the internal clocking system, which is derived from the PCI clock, and the
various line clocks. This provides a unique clocking scheme on the internal interfaces.
The aggregate bandwidth of all enabled tributaries can be up to 45 Mbit/s in each
direction.
Time slot assigne r
The time slot assigner exchanges data with the serial interface on a 8 bit parallel bus,
thus funneling all data of up to 28 interfaces. The time slot assigner provides freely
programmable mapping of any time slot or any combination of time slots to 256 logical
channels. A programmable mask can be provided to allow subchanneling of the
ava ilable time slots which allo ws ch annel data rates s tarting at 8kbit/s.
At the protocol machine interface the time slot assigner and the protocol machine
exchanges channel oriented data (8 bit) together with the time slots masks.
Protocol handler
Two protocol machines, one for receive direction and one for transmit direction, provide
protocol handling for up to 256 logical channels and a maximum serial aggregate data
rate of up to 45 Mbit/s per direction. The pro tocol machine s implement four modes, which
can be programmed independently for each logical channel: HDLC, bit-synchronous
PPP, octet-synchronous PPP and Transparent Mode A, including frame synchronous
TMA.
PEB 3456 E
General Overview
Data Sheet 50 05.2001
Internal buffer
The internal buffers provides channelwise buffering of raw (unformatted/deformatted)
data for 256 logical channels. Channel specific thresholds can be programmed
independently in transmit and receive direction. In order to avoid transmit underrun
conditions each transmit channel has two control parameters for smoothing the filling/
emptying process (transmit forward threshold, transmit refill threshold). In receive
directio n each channel has a receive burst threshold. To av oid unnecessary wast e of bus
bandw idth , e.g . in c ase of tran sm is si on errors , the receive buf fer pro vi des the cap abi lit y
to discard frames which are smaller than a programmable threshold.
Data management units
The data management units provide direct data transfer between the system memory
and the in ternal buffe rs. Each ch annel has an assoc iated lin ked list of des criptors, which
is locat ed in syste m memory and handled by the data ma nagemen t units. This linke d list
is the in terface between th e system process or and the TE3-CHAT T for exchange of da ta
packet s. The de scrip tors and the d ata pac kets can b e st ored arbi trarily in 32 bi t addres s
space of system m emory , thus all owing fu ll sca tter/gath er asse mbly of packets . In order
to optimize PCI bus utilization, each descriptor is read in one burst and held on-chip
afterwards.
Interrupt controller
Two interrupt controllers manage internal interrupts. Interrupts from the mailbox, the
framing engines and the signalling controller are passed in the form of interrupt vectors
to an internal interrupt FIFO which can be read from the local bus. All system, port and
channel related interrupt information is passed to the main interrupt controller which is
connected to the PCI system. A programmable DMA with nine channels stores these
interrupts in th e form of interru pt vectors in d ifferent in terrupt queues in s ystem m emory.
PCI interface
The PCI interface unit combines all DMA requests from the internal data management
unit and the interrupt controller and translates them into PCI Rev. 2.1 compliant bus
accesses. The PCI interface optionally includes the function of loading the subsystem
vendor ID and the subsystem ID from an external SPI compliant EEPROM.
Mailbox, intern al bridge and globa l registe rs
The mailbox is used to exchange data between the PCI attached microprocessor and
the local bus microprocessor and provides a doorbell function between the two
interfaces.
Controlled by an arbiter an internal bridge connects the configuration bus I and the
configuration bus II. It is therefore possible to access the “layer one” registers from the
PEB 3456 E
General Overview
Data Sheet 51 05.2001
PCI interface directly. Thus the device could also be operated without a local
microprocessor connected to it, e.g. for debugging purposes. It is NOT possible to
acces s the co nfigura tion bus I and the refore th e ’HDLC ’ regi sters o r the PCI b ridg e from
the local bus.
Local bus interface
The local bus interface provides access between the local microprocessor and the on-
chip c on fig urati on bus II, in o r der to a cc es s the re gis ters of the o n-ch ip M 13 m ultiplex er,
DS2/D S3 fram er, T1/E1 framer, the regis ters of the signallin g controller and the m ailbox.
The local bus interface provides a switchable Intel-style or Motorola-style processor
interface.
M23 multiplexer/demultiplexer and DS3 framer
In chann elized o perating mod es the M23 mul tiplexer/dem ultiplexer m aps/demaps s even
DS2 sign als into/fro m M13 asynch ronous form at or C-bit parity format. In unch annelize d
mode one logical input stream is mapped into the information bits of the DS3 stream
accordi ng to ANSI T1.1 07. The D S3 frame r perform s frame a nd mult iframe alignment in
receive direction and inserts the frame and multiframe alignment bits. Performance
monitors provide for counting of framing bit errors, parity errors, CP-bit errors, far end
block errors, excessive zeroes or line code violations. The framer detects loopback
requests and allows insertion of loopback requests under microprocessor control.
M12 multiplexer/demultiplexer and DS2 framer
The M12 multiplexer/demultiplexer operates in two modes. It maps either 28 T1 signals
or 21 E1 si gna ls into /from seven ANSI T1.10 7 or ITU -T G.74 7 co mp lia nt D S2 s ign als . It
perfor ms inversion of th e second and fourt h DS1 signal. The DS2 framer perfor ms frame
and multiframe alignment in receive direction and vice versa inserts the framing bits
according to ANSI T1.107 or ITU-T G.704. It detects loopback requests or enables
insertion of loopback requests under microprocessor control.
T1/E1 framer
Synchron izati on is achieve d wi th the on-ch ip fram ing fu nctio n. T1/E1 mode is supp orted
for up to 2 8 p orts . O nc e th e fr ame r ac hi ev ed sy nch ron iza tion for a l in e, th at i s the fram e
alignm ent i nformation in the incom in g bit stre am h as been iden tified corre ct ly, it inform s
the port interface and the facility data link about the frame position. In transmit direction
the framing bits are inserted according to T1 F4 format, T1 SF (F12) format, T1 ESF
(F24) format, E1 doubleframe format or E1 CRC-4 multiframe format. Performance
monitors provide for counting framing errors, CRC errors, block errors, E-bit errors or
PRBS bit erro rs. The fram er dete cts loopba ck requ ests a nd allo ws inser tion of loopb ack
requests or pseudo-random bit sequences under microprocessor control.
PEB 3456 E
General Overview
Data Sheet 52 05.2001
Facility data link, Signaling controller
The faci lity data l ink ex c han ges the ‘F-b its ’ o f the T1 l in ks or th e Sa-bits of time slot zero
of the E1 links with the framer block and it provides the function of HDLC formatting or
BOM mode in receive and transmit direction.
The signalling controller also provides access to the DS3 signalling bits (Far End Alarm
and Control Channel, Path Maintenance Data Link Channel).
Message FIFO
For intermediate buffering of data link messages two FIFOs are integrated, one for
transmi t and one for rec eive direc tion. Eac h FIFO provid es two pages of 32 bytes buf fer
per line and direction.
JTAG
Boundary Scan logic according to IEEE 1149.1.
PEB 3456 E
Functional Description
Data Sheet 53 05.2001
4 Functional Description
4.1 Port Handler
The port handler is the interface between the serial ports and the chip internal protocol
and framing functions. It converts incoming serial data into parallel data for further
internal processing and in the outgoing direction it converts parallel data into a serial bit
stream.
The TE3-CHATT provides one port for operation at DS3 signal speeds. It provides
unipolar data transmission or B3ZS encoded data transmission.
The system interface consists of one receive clock input and either one receive data
input in unipolar mode or two receive data inputs in dual-rail mode, one for the positive
pulse and one for the negative pulse. In transmit direction the system interface is build
of one transmit clock input and one or two transmit data outputs.
•
Figure 4-1 Port configuration in M13 mode
M23 multiplexer stage
TD44P
TD44N
RD44P
RD44N
T1/E1
Transmit
Path
T1/E1
Receive
Path
TC44O
RC44
TC44
M12 multiplexer stage
+ DS2 framer
CTCLK
tributary looped timing mode exter nal tim i ng
mode
171
28
Overhead
Access
DS3 looped timing mode
DS3 framer
PEB 3456 E
Functional Description
Data Sheet 54 05.2001
4.1.1 Local Port Loop
Local port loops are provided on DS3, DS2 and DS1 level on a per port/tributary basis.
In the loca l loop the outgoin g bit strea m of a port/tr ibutary is mirror ed to the rec eive data
path. This allows to prepare data in system memory, which is processed by the TE3-
CHATT in transmit direction, mirrored to the respective receiver and stored in system
memory again. In order to ensure that the local port loop works even without incoming
receive clock, each receiver looped uses the corresponding transmit clock.
•
Figure 4-2 Local Port Loops in M13 mode
4.1.2 Remote Line Loops
The TE3-CHATT supports remote line loops in different stages of the M13 data path. In
DS3 line loopback mode the incoming DS3 signal is mirrored and placed on the DS3
signal output. While operating in DS3 line loopback mode, the incoming receive clock
RCLK is used to update outgoing transmit data. In DS2 line loopback mode one
arbitr arily sel ectable D S2 signa ls is loo ped in the M 12 stage of the TE3- CHATT. The T 1/
E1 line loopback mode mirrors one or more incoming lines. Transmit data coming from
the transmit data path is replaced with the mirrored data stream.
DS2
Receive
Framer
Protocol
Data
DS2
Demux
DS2
Transmit
Framer
DS2
Multiplexer
T1/E1
Receive
Framer
T1/E1
Transmit
Framer
Protocol
Data
DS3
Receive
Framer
M23
Demux
M23
Multiplexer
DS3
Transmit
Framer
RD44P
RC44
RD44N
TD44P
TC44O
TD44N
TC44
DS2
Receive
Framer
Protocol
Data
DS2
Demux
DS2
Transmit
Framer
DS2
Multiplexer
T1/E1
Receive
Framer
T1/E1
Transmit
Framer
Protocol
Data
DS3
Receive
Framer
M23
Demux
M23
Multiplexer
DS3
Transmit
Framer
RD44P
RC44
RD44N
TD44P
TC44O
TD44N
TC44
PEB 3456 E
Functional Description
Data Sheet 55 05.2001
•
Figure 4-3 Remote Line Loops
The T1/E1 line loopback mode mirrors one or more incoming lines. Transmit data
coming from the tran sm it d ata path is repl ac ed wi th the mirror ed d ata s tre am . Whi le T 1/
E1 line loop is closed the transmit framer and the protocol machines are disabled.
DS3
Receive
Framer
M23
Demux
M23
Multiplexer
DS2
Receive
Framer
DS3
Transmit
Framer
RD44P
RC44
Protocol
Data
RD44N
TD44P
TC44O
TD44N
M12
Demux
DS2
Transmit
Framer
M12
Multiplexer
T1/E1
Receive
Framer
T1/E1
Transmit
Framer
Protocol
Data
DS3
Receive
Framer
M23
Demux
M23
Multiplexer
DS2
Receive
Framer
DS3
Transmit
Framer
Protocol
Data
DS2
Demux
DS2
Transmit
Framer
DS2
Multiplexer
T1/E1
Receive
Framer
T1/E1
Transmit
Framer
Protocol
Data
DS3
Receive
Framer
M23
Demux
M23
Multiplexer
DS2
Receive
Framer
Protocol
Data
DS2
Demux
DS2
Transmit
Framer
DS2
Multiplexer
T1/E1
Receive
Framer
T1/E1
Transmit
Framer
Protocol
Data
RD44P
RC44
RD44N
RD44P
RC44
RD44N
TC44
TD44P
TC44O
TD44N
TC44
DS3
Transmit
Framer
TD44P
TC44O
TD44N
TC44
PEB 3456 E
Functional Description
Data Sheet 56 05.2001
4.1.3 Test Breakout
The test breakout function provides the capability to multiplex one of the incoming 28
receive tributaries to the outgoing test receive port, where an external T1/E1 analyzer
can be e asily conn ected to. A se lecta ble inco ming t ribu tary sign al can be mapp ed to th e
test receive port where RCLK(x) is mapped to TRCLK and RD(x) to TRD. TRD is
updated on the falling edge of TRCLK. In the opposite direction one of the 28 transmit
tributaries can be replaced with the incoming test transmit data input TTD and the test
transmit clock input TTCLK. TTD is sampled on the rising edge of TTCLK.
•
Figure 4-4 Test Breakout
4.2 Time slot Handler
4.2.1 Channelized Modes
The time slot handler assigns any combination of time slots of ports configured in T1 or
E1 mode to logical channels. The assigned time slots are connected internally and the
bit stream of one logical channel is mapped continuously over the selected time slots.
TCLK(27)
TD(27)
RCLK(27)
RD(27)
TRCLK
TRD
TTCLK
TTD
TCLK(0)
TD(0)
RCLK(0)
RD(0)
To/From time slot assigner, T1/E1Framer
DS3
Receive
Framer
+
M23
Demux
RD44P
RC44
RD44N
DS2
Receive
Framer
+
M12
Demux
DS2
Transmit
Framer
+
M12
Multiplexer
DS3
Transmit
Framer
+
M23
Multiplexer
TD44P
TC44
TD44N
TC44O
PEB 3456 E
Functional Description
Data Sheet 57 05.2001
Since the receiver and the transmitter operate independently of each other, the
assignment of time slots to logical channels can be done separately in receive and
transmit direction. Any time slot can be assigned to any channel and any sequence of
time slots can be assigned to one channel.
In normal operation each time slot consists of eight bits and all bits are used for data
transmission. An available mask function provides the capability to mask selected bits,
which in turn are disabled for data transmission. This provides the possibility to operate
time slots with less than 64 kBit/s throughput. So, instead of mapping the bit stream of
one logical channel over all bits of the assigned time slots, the bit stream is mapped
continuously over all unmasked bits of the time slots belonging to that channel.
Masked bits are transmitted as ‘1’. In receive direction masked data bits are
discardedFigure 4-5 shows a simple assignment process. In this case one port is
configured in E1 mode and time slots two and three are assigned to logical channel 5.
The bit mask of time slot two is set to FEH, which disables bit zero of that time slot, and
the bit mask of the third time slot is set to FDH, which disables bit one.
PEB 3456 E
Functional Description
Data Sheet 58 05.2001
•
Figure 4-5 Time slot Assignment in Channelized Modes
4.2.2 Unchannelized Mode
In uncha nnelized mode the co mplete inc oming an d outgoing serial bit s tream belon gs to
one logi cal DS3 c ha nne l. T o operate the link in u nc han nel iz ed mode tri bu t ary ze ro (p ort
zero) has to be prog ramme d for unc hannel ized o peratio n and all ‘time slots’, tha t is tim e
slot 0 to 23 must be assigned to one channel. Additionally the M13 multiplexer must be
switched into un channeli zed DS3 mod e. The funct ion of bit m asks, whic h is avai lable for
the T1/E1 tributaries, is not available in unchannelized mode.
0 1 2 29 30 31 012 29 30 31
1 2 3 4 5 6 70 1 2 3 4 5 6 70
Frame 1 Frame 2
Timeslot 2 Timeslot 3
3 3
76 10
1 1 1 1 1 1 10
Timeslot Mask
0 1 1 1 1 1 11
Timeslot Mask
Time
Example configuration:
Port three in mode E1.
Timeslot 2 and 3 are assigned to channel 5.
Bit 0 of timeslot 2 and bit 1 of timeslot 3 are masked.
Programming sequence:
1. Port mode configuration
3
H
031
PMIAR
PMR
8
H
2. Timeslot assignment
Register Data
TSAIA
TSAD
TSAIA
TSAD
111011115
H
111101115
H
3
H
2
H
3
H
3
H
Selec t por t 3
E1 mode
Selec t por t 3, time s lot 2
Set channel 5, mask
Selec t por t 3, time s lot 3
Set channel 5, mask
PEB 3456 E
Functional Description
Data Sheet 59 05.2001
4.3 Data Management Unit
Each pac ket or part of a packet is reference d by a descrip tor. The des criptors fo rm a link
list, thus con nec tin g a ll p ac ket s to ge ther. Packe t dat a as w el l as de sc rip tors are loc ate d
in system memory. Both the TE3-CHATT and the system CPU operate on these data
structures.
Each lo gical chann el has i ts de dicate d lin ked li st of desc riptors, one f or re ceiv e direc tion
and one for transmit direction. This type of data structure allows channel specific
memory organization which can be specified by the system processor. It provides an
optimized way to transfer data packets between the system processor and the TE3-
CHATT.
The TE3-CHATT has a flexible DMA controller to transfer data either from the internal
receive buffer to the shared memory (receive direction) or from the shared memory to
the intern al transmi t buffer (trans mit directio n). Each DM A works on on e linked lis t. Each
linked list loca ted in s ystem m emory is associa ted wit h one of the 256 transm it ch annel s
or one of 256 receive channels.
The address generator of the DMA controller supports full link list handling. Descriptors
are stored independently from the data buffers, thus allowing full scatter/gather
assembly and disassembly of data packets.
4.3.1 Descript or Co ncept
A descriptor is used to build a linked list, where each member of the linked list points to
a data section. A descriptor consists of four DWORDS1). The first three DWORDS,
containing link and packet information, are provided by the system CPU and the last
DWORD contains s tatus inform ation, which is written when the TE3-CHATT has finished
operation on a descriptor.
The data section itself can be of any size up to the maximum size of 65535 bytes per
descriptor and is defined in the first DWORD of a descriptor. Each logical data packet
can be split into one or multiple parts, where each part is referenced by one descriptor,
and all parts are referenced by a linked list of descriptors. The descriptor containing the
last part of a data packet is marked with a frame end bit. The descriptor following the
marked descripto r therefore c ontains the begin ning of th e next data pack et (Figure 4- 6).
The last descriptor in a linked list is marked with a hold indication.
For ease of programming the transmit descriptor and the receive descriptor are
structure d the sam e way, thus allowing to link a rec eive des criptor dire ctly into the linke d
list of the transmit queues with minimum descriptor processing.
1)
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Functional Description
Data Sheet 60 05.2001
•
Figure 4-6 Descriptor Structure
Although the data management unit works 32-bit oriented, it is possible to begin a
transmi t data se ction at an unev en add ress. Th e two leas t sign ifica nt bits o f the trans mit
data pointer determine the beginning of the data section and the number of bytes in the
first DWORD of the data section, respectively. In receive direction the address of the
data sections must be DWORD aligned.
4.3.2 Receive Descriptor
Each receive descriptor is initialized by the host CPU and stored in system memory as
part of a linked list. The TE3-CHATT reads a descriptor, when requested to do so from
the host by a receive command or after branching from one receive descriptor to the next
receive descrip tor. Each receive des criptor c ontains four DW ORDs, wh ere the fi rst three
DWORDs contain link and packet information and the last DWORD contains status
informat ion. Onc e th e de sc rip tor i s p r oc es se d the st atu s i nformation w il l be w ritt en b ac k
to system memory by the TE3-CHATT (Receive status update). When the TE3-CHATT
Next Descriptor Pointer
Data Pointer
010 2 08
H
08
H
01 00000
0F
H
0E
H
0D
H
0C
H
13
H
12
H
11
H
10
H
14
H
Next Descriptor Pointer
Data Pointer
000 1 10
H
09
H
11 00000
Next Descriptor Pointer
Data Pointer
000 0 0C
H
0C
H
01 00000
0F
H
0E
H
0D
H
0C
H
13
H
12
H
11
H
10
H
14
H
Flag
CRC
CRC
7E
H
Flag
CRC
Payload
Linked l ist in system m em ory in little en dian m ode Dat a on ser ial link
03
H
02
H
01
H
00
H
07
H
06
H
05
H
04
H
0B
H
08
H
09
H
0A
H
03
H
02
H
01
H
00
H
07
H
06
H
05
H
04
H
0B
H
08
H
09
H
0A
H
7E
H
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Functional Description
Data Sheet 61 05.2001
branches to a new desc r ipt or i t rea ds th e l ink an d p ac ke t in form at ion entire ly and s tore s
it in its on-chip channel database.
Table 4-1 Receive Descriptor Structure
HOLD Hold indication
HOLD indicates that a descriptor is the last element of a linked list
containing valid information.
0 Next desc riptor is availab le in the shared memory . After ch ecking
the HOLD bit the data management unit branches to the next
receive descriptor.
1 This des cript or is the last o ne that i s ava ilable for a ch annel. This
means that the data section where this descriptor points to is the
last data section which is available for data storage. After
processing of descriptor has finished, the data management unit
repolls the descriptor one time to check if HOLD has already
been cleared. If HOLD is still set the corresponding receive
channel is deactivated as long as the system CPU does not
request a ne w activ ation via a ’Recei ve Hold R eset’ c ommand or
forces the TE3-CHATT to branch to a new linked list via a
’Receive Abort/Branch’ command.
Note: When repolling a descriptor the TE3-CHATT checks the HOLD
bit and the bit field NextReceiveDescriptorPointer. All other
information are NOT updated in the internal channel database.
DWORD
ADDR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
00H0 HOLD RHI OFFSET(2:0) 0000 DescriptorID(5:0)
04HNextReceiveDescriptorPointer(31:2)
08HReceiveDataPointer(31:2)
0CHFE C 000000000 MFL RFOD CRC ILEN RAB
DWORD
ADDR. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00HNO(15:0)
04HNextReceiveDescriptorPointer(31:2) 0 0
08HReceiveDataPointer(31:2) 0 0
0CHBNO(15:0)
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Functional Description
Data Sheet 62 05.2001
RHI Receive Host Initiated Interrupt
This bit indicates that the TE3-CHATT shall generate a ’Receive Host
Initiated’ interrupt vector after it has finished processing the descriptor.
0 Data management unit does not generate an interrupt vector
after it has processed the receive descriptor.
1 Data ma nag em ent unit gene rate s an i nterrupt v ec tor, as so on as
all data bytes are tran sferred into th e current data sec tion and the
status information is updated.
OFFSET Offset of unused data section.
This bi t field all ows to reserv e memory sp ace in inc rements o f DWORDs
for an a dditional header. I f the mark ed desc riptor is the first one of a new
packet the data management unit will write data at the address
ReceiveDataPointer+4xOFFSET.
Note: Offset x 4 must be smaller than NO.
Note: This option is not available in transparent mode.
Descr iptorID This b it field i s read b y the data manage ment unit and wri tten back in the
corresponding interrupt status of a channel interrupt vector which is
generated by the data management unit. This value provides a link
between the descriptor and the corresponding interrupt vector.
NO Byte Number
This bit field defi nes the s ize of the receiv e data sectio n alloc ated by the
host. The maximum buffer length is 65535 bytes and it has to be a
multiple of 4 bytes. Data bytes are stored in the receive data section
according to the selected mode (little endian or big endian).
Note: Please note that the device handles the status (CRC, flag and
frame stat us) o f fram e bas ed pro tocols (HDLC, PPP) i nterna lly i n
the same way as payload data. Therefore byte number should
include four bytes more than the maximum length of incoming
frames. Nevertheless, the frame status will be deleted from the
end of the data stream and be attached as a status word to the
receive descriptor. The frame status will no t be written to the da ta
section.
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Functional Description
Data Sheet 63 05.2001
NextReceiveDescriptorPointer
This pointer contains the start address of the next valid receive
descriptor. After completion of the current receive descriptor the data
management unit branches to the next receive descriptor to continue
data reception.
System CPU can force the TE3-CHATT to branch to the beginning of a
new l inked list via th e comm and ’R ecei ve Abo rt/Branch ’. In t his c ase th e
receive descriptor address provided via register CSPEC_FRDA is used
as the next receive descriptor pointer to be branched to.
ReceiveDataPointer
This pointer contains the start address of the receive data section. The
start address must be DWORD aligned.
FE Frame End
It indicates that the current receive data section (addressed by
ReceiveDataPointer) contains the end of a frame. This bit is set by the
data ma nagemen t unit after transferring the last data of a frame from th e
internal receive buffer into the receive data section which is located in
the shared memory. Moreover the bit field BNO and the status bits are
updated , the c ompl ete (C) bi t is s et and a ’Fra me End ’ inte rrupt ve ctor i s
generated.
C Complete
This bit indicates that
•filling the data section has completed (with or without errors),
•processing of this descriptor was aborted by a ’Receive Abort/Branch’
command,
•or the end of frame (PPP, HDLC) was st ored in the re ceive data sec tion.
The complete bit releases the descriptor.
BNO Byte Number of Received Data
The d ata manageme nt unit writ es the nu mber of data b ytes store d in the
current data section into bit field BNO.
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Functional Description
Data Sheet 64 05.2001
When the TE3-CHATT completes a data section, which included the end of a frame
(C bit and FE bit are set), or when the TE3-CHATT branches to a new linked list due to
a 'Receive Abort/Branch' command the status information bits RAB, ILEN, CRC, RFOD
and MFL are updated as part of the receive status update. In the abort scenario, the C
bit will always be set. Bit FE will be set only, if the particular channel operates in HDLC
or PPP mode.
RAB Receive Abort
This bit is set when
•the incoming serial data stream contained an abort sequence, or
•an incoming frame was aborted by the command ’Receive Abort/
Branch’, or
•when a channel is switched off while a frame is being received.
ILEN Illegal length
This bit is set, when the length of the incoming data packet was not a
multiple of eight bits.
CRC CRC Error
This bit is set, when the checksum of an incoming data packet was
different to the internally calculated checksum.
RFOD R eceive Frame Overfl ow
This bit is set, when a receive buffer overflow occurred during data
reception.
MFL Maximum Frame Length
This b it is set, w hen the leng th of the inc oming data p acket exce eded the
value programmed in CONF1.MFL.
4.3.3 Data Management Unit Receive
The data management unit receive transfers data for each of the 256 logical receive
channels from the internal receive buffer to the data sections of the corresponding
channel. To fulfill the task it has to be initialized for operation, which is described in
“Channel Programming / Reprogramming Concept” on Page 163. Relevant part of
the channel information for the data management unit is the address pointer to the first
receive descriptor, the channel interrupt queue and the channel interrupt mask.
The first receive descriptor of a channel is fetched from system memory and stored in
the chip internal channel database the first time the receive buffer requests a data
transfer for th e channel. Th e descripto r contains a point er to the data sec tion, the size of
the provided data section and a pointer to the next receive descriptor.
The data transfer is requested as soon as a programmed receive buffer threshold is
reached. This threshold is programmed during channel setup on a per channel basis.
Task of the dat a manage ment unit is to cal culate the maximu m numbe r of byt es that ca n
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Functional Description
Data Sheet 65 05.2001
be store d in the rece ive data se ction and to compare thi s with the le ngth of the re quested
data transfe r .
In case that the requested transfer length from the receive buffer fits into the provided
data sec tion the data ma nagement unit tr ansfers the data block to system memor y in one
single burst. If the requested transfer length exceeds the available space of the data
sectio n the transfer is divid ed into two or mo re parts. Data packe ts are written to the da ta
section until the given data section is filled or the end of a packet is reached.
If the data section in the shared memory is completely filled with data, the data
management unit updates the status word of the receive descriptor by setting the
comple te (C) bit and the nu mber o f byte s (BNO), w hic h are s tored i n the da ta sec tion. In
this case the number of bytes written to the data section equals the size of the data
section.
If the data packet, which is written to system memory, contains the remaining part of a
completely received packet, the data management unit updates the status word of the
receive descriptor by setting the complete bit together with the frame end (FE) bit. The
BNO field is upd ate d on the ac tual valu e of byt es wr itt en to the da ta sec tio n. If ena ble d,
the data management unit generates a ‘Frame End’ channel interrupt vector.
With the next receive buffer request the data management unit branches to the next
receive descriptor, which was referenced in the next descriptor field of the current
proce ssed desc riptor. To k eep t rack of th e linked list the data man agement unit prov ides
the poss ibility to is sue a ‘Rece ive Host Initia ted’ interrupt ve ctor, which is generated af ter
the status word was updat ed. To enabl e this in terrupt vec tor the bit RHI mus t be set i n a
descriptor.
Descriptor hold operation
Process ing of the descript or list is c ontrolled b y the HOL D bit, whi ch is loca ted in the first
DWORD of each receive descriptor. The HOLD bit indicates that the marked descriptor
is the last descriptor containing a valid data buffer. The data management unit will not
branch to a next descriptor until the hold condition is removed or a ‘Receive Abort’
command forces the TE3-CHATT to branch to the beginning of a new linked list. Since
the HOLD bit mark s the last descr iptor in a linked lis t, it may prevent th at further receive d
data packets can be written to system memory.
When a given data section is filled, and does not contain the end of a frame (frame b ased
protocols) and the requested transfer length could not be satisfied, the data
management unit polls the HOLD bit of the current receive descriptor once more. If the
HOLD bit is removed, it branches to the next descriptor. When the HOLD bit is still ’1’,
an internal poll bit is set and the data management unit does not branch to the next
descrip tor. Additi onally a ’Hold Caused Re ceive Ab ort’ inter rupt ve ctor is generated . The
status o f the des cri pto r in th e s hare d mem ory is a bor ted (R AB b it s et) a nd th e c omple te
bit and the frame end bit are set in the receive descriptor. The rest of the frame will be
discarded. As long as the HOLD bit remains set further data of the same channel is
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Functional Description
Data Sheet 66 05.2001
discarded and for each discarded frame a ’Silent Discard’ interrupt vector with the bits
HRAB and RAB set is generated.
If the current data section was filled and does contain the end of frame a ’Frame End’
interrupt vector is generated and the descriptor is updated on the FE bit and the C bit.
Therefore the status of this receive descriptor is error free. With the next request of the
receive buffer, the data management unit repolls the HOLD bit of the current receive
descriptor. If the hold bit is removed, it branches to the next descriptor. If the HOLD bit
is still ’1’, an internal poll bit is set. As long as the HOLD bit remains set, further data of
the same channel is discarded and for each discarded frame a ’Silent Discard’ interrupt
vector with bits HRAB and RAB set is generated.
When the receive buffer request matches exactly the remaining size of the data section
and the data block does not contain the end of a packet, it is stored completely in the
data section. The descriptor is updated immediately (C bit set). With the next receive
buffer request, the data management unit repolls the HOLD bit of the current receive
descriptor. If the HOLD bit is removed, it branches to the next descriptor. If the HOLD Bit
is still ’1’, an internal poll bit is set. Additionally a ’Hold Caused Receive Abort’ interrupt
vector is generated and the rest of the frame is discarded. As long as the HOLD bit
remains set furthe r data of the sam e channel is disc arded and for each disc arded fram e
a ’Silent Discard’ interrupt vector is generated.
The system CPU can remove the hold condition, when the next receive descriptor is
available in shared memory. Therefore the CPU has to execute a ‘Receive Hold Reset’
command, which will reactivate the channel. When the receive buffer requests a new
data transfer, the data management unit will repoll the last receive descriptor. If the
HOLD bit was removed, the data management unit branches to the next receive
descriptor pointed to by bit field NextReceiveDescriptor.
Note: In protocol modes HDLC and PPP data from receive buffer is discarded until the
end of a received frame is reached. As soon as the beginning of a new frame is
received, the data management unit starts to fill the data section.
Note: In transp aren t m ode data trans ferre d fro m re ce iv e bu ffer is wr itte n im m edi ate ly to
the data section of the next receive descriptor.
If the CPU issues a ’Receive Hold Reset’ command and does not remove the HOLD bit
(erroneo us pro gram ming), no ac tion will take place.
4.3.4 Transmit Descriptor
The transmit descriptor in shared memory is initialized by the host CPU and is read
afterwards by the TE3-CHATT. The address pointer to the first transmit descriptor is
stored in the on-chip channel database, when requested to do so by the host CPU via
the ’Transmit Init’ command. The first three DWORDs of a transmit descriptor are read
when the transmit buffer requests a data transfer for this channel and then they are
stored in the on-chip memory. Also they are read when branching from one transmit
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Functional Description
Data Sheet 67 05.2001
descrip tor to th e n ext tran smit descri ptor. Th erefore all in formati on in t he nex t desc riptor
must be valid when the data management unit branches to a descriptor. The last
DWORD of a transmit descriptor optionally is written by the TE3-CHATT when
processing of a descriptor has f inished.
Table 4-2 Transmit Descriptor Structure
FE Frame end
It ind icates that the cu rrent trans mit dat a sect ion (ad dressed by trans mit
data po inter) c ontain s the end o f a fram e. After t he las t byte is read from
system memory this bit is passed to the transmit buffer and to the
protocol machine. The bit FE informs the transmit buffer to move a
stored frame to the protocol machine even if the programmed transmit
forward threshold is not reached (see “Internal Transmit Buffer” on
Page 74). The protocol machine is informed to append the checksum
(HDLC, PPP) and then to send the interframe time-fill. Providing a
transmit descriptor with FE = ’0’ and HOLD = ’1’ is an error.
HOLD Hold indication
It indicates that this descriptor is the last valid element of a linked list.
0 Next descriptor is available in the shared memory. The data
management unit branches to the next descriptor as soon as
processing of the current descriptor has finished.
1 The current descriptor is the last descriptor containing valid data
in the data section. As soon as the data management unit has
transferred the data contained in the data section to the internal
buffer, it tries one more time to read the descriptor. In case that
DWORD
ADDR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
00HFE HOLD THI CEN 000000 DescriptorID(5:0)
04HNextTransmitDescriptorPointer(31:2)
08HTransmitDataPointer(31:0)
0CH0C00000000000000
DWORD
ADDR. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00HNO(15:0)
04HNextTransmitDescriptorPointer(31:2) 0 0
08HTransmitDataPointer(31:0)
0CH0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Functional Description
Data Sheet 68 05.2001
the hold indication is still set, it stores further requests of the
receive buffer in its channel database. The channel can be
reactivated by issuing a ’Transmit Hold Reset’ command or by
providing a new linked list via the ’Transmit Abort/Branch’
command, in which case not served requests are processed.
Note: When repolling a descriptor the TE3-CHATT checks the HOLD
bit and the bit field NextTransmitDescriptorPointer. All other
information are NOT updated in the internal channel database.
NO Byte Number
The byte num ber de fines the nu mb er of by te s stored in the data sectio n
to be transmitted. Thus the maximum length of data buffer is 65535
bytes. In o r der to provide dummy tra ns mi t d es cri ptor s NO = 0 is al lowed
in conj unc tio n with the FE bi t se t. In thi s c as e (NO = 0) a ’Tran smit Hos t
Init iate d’ inte rrupt vec tor a nd/ or the C-b it wi ll be generated/set wh en th e
data management unit recognizes this condition. It is an error to set
NO = 0 without FE bit set.
THI Transmit Host Initiated Interrupt
This bit indicates that the TE3-CHATT shall generate a ’Transmit Host
Init iated’ interrup t vect or af ter it ha s fini shed o peratin g on the desc riptor.
0 Data management unit does not generate an interrupt vector
after it has processed the transmit descriptor.
1 Data ma nag em ent unit gene rate s an i nterrupt v ec tor, as so on as
all data bytes are transferred to the internal transmit buffer and
the status information is updated.
Descr iptorID This b it field i s read b y the data manage ment unit and wri tten back in the
corresponding interrupt status of a channel interrupt vector which is
generate d by data m anagemen t unit. This value prov ides a lin k between
the descriptor and the corresponding interrupt vector.
NextTransmitDescriptorPointer
This pointer contains the start address of the next transmit descriptor. It
has to be DWORD aligned. After sending the indicated number of data
bytes, the data management unit branches to the next transmit
descriptor. The transmit descriptor is read entirely at the beginning of
transmission and stored in on -chip memory. Therefore all informations in
the descriptor must be valid.
System CPU can force the TE3-CHATT to branch to the beginning of a
new link ed list via the command ’ Transmit Abort/Branc h’. In this cas e the
transm it des cripto r a ddre ss p rov ide d via re gis ter CSPEC_FT D A i s use d
as the next transmit descriptor pointer to be branched to.
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Functional Description
Data Sheet 69 05.2001
TransmitDataPointer
This 32-bit pointer contains the start address of the transmit data section.
Although the data management unit works DWORD oriented, it is
possible to begin transmit data section at byte addresses.
CEN Complete Enable
This bit is set by the CPU if the complete bit mechanism is desired:
0 The data management unit will NOT update the transmit
descrip tor with the C bit. In this m ode the us e of the THI interru pt
is recommended.
1 The data management unit will set the C bit.
C Complete
This bit is set by the data management unit, when the bit CEN of a
descriptor is set and when it
•completed reading a data section normally, or
•it was aborted by a ’Transmit Off’ command or by a ’Transmit Abort/
Branch’ com m and .
The complete bit releases the descriptor.
4.3.5 Data Management Unit Transmit
The data management unit transmit provides the interface between system memory on
one side and the internal transmit buffer on the other side. The data management unit
handles requests of the transmit buffer, controls the address and burst length
calculation, initiates data transfers from system memory to the transmit buffer and
handles the linked lists on a per channel basis.
For initialization the CPU programs the first transmit descriptor address, the interrupt
mask, the interrupt queue and starts the channel with the ’Transmit Init’ command. For
detailed description of channel commands refer to “Channel Commands” on
Page 164.The data management unit then fetches the given information and stores
them in its on-chip channel database.
The first transmit descriptor is fetched from system memory and stored in the chip
internal channel database the first time the transmit buffer requests data for a channel.
It conta in s a pointer to the data buffe r, the le ngth of the da ta secti on as w e ll as a po inter
to the next transmit descriptor. After the first descriptor is stored internally a ’Transmit
Command Complete’ interrupt vector is generated.
Data transfers are requested as long as the number of empty locations is below a
programmable refill threshold. The number of empty locations is reported from the
transmit buffer to the data management unit. Task of the data management unit is to
calcul ate the numb er of bytes tha t can be loade d from the data section based on the NO
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Functional Description
Data Sheet 70 05.2001
field of the transmit descriptor and to compare this with the number of bytes requested
by the transmit buffer.
Depending on the bit field NO in the transmit descriptor several read accesses must be
performed by the data management unit. It stops serving the request as soon as the
requested amount of data was transferred to the transmit buffer, when a Frame End bit
(FE) in the processed transmit descriptor is set or when the channel was aborted using
a ‘Transmit Abort’ command. Serving the request can also be suspended, when the
programmed transmit burst length (CONF3.TPBL) is reached. All these events may
result in open transmit buffer locations, but the data management unit stores this
information as open requests in the channel database and processes these requests
continuously.
The data management unit alternately serves requests issued by the transmit buffer or
open requests stored in its internal channel database. If there are open requests for a
channel, data transmission will be initiated. The procedure is the same as described
above. It st ops , if the requested am oun t of dat a is s erve d or w hen the FE bit field is se t.
If a transmit descriptor has its FE bit set and all data of the data section is moved to the
transmit buffer, the data management unit serves requests of further channels or looks
for open requests in its database. Therefore open requests from other channels are
served faster and possible underruns can be avoided. The next transmit descriptor will
be retrieved with the next data transfer of the channel.
When the data management unit completed reading a data section associated with a
transmit descriptor, it updates the complete (C) bit in the status word of the transmit
descrip tor if the comp lete enab le (CEN) bit is se t. Addition ally a ’Transm it Host Initi ated’
interrupt v ector is gene rated if the THI bit is s et in the transmit des criptor. Afterw ards the
data management unit the TE3-CHATT branches to the next transmit descriptor.
Descriptor hold operation
The data transfer is controlled by the HOLD bit, which is located in the first DWORD of
a transmit descriptor. The HOLD bit indicates that the marked descriptor is the last
descrip tor in a linked list. The data m anagement unit will not branch to the next descrip tor
until the hold condition is removed or a ’Transmit Abort’ command forces the TE3-
CHATT to branch to a new linked list.
If the HOLD bit and the frame end bit are set together in a descriptor, the data
management unit transfers all data of the belonging data section to the transmit buffer
and optio nally sets the C-bit in the c urrent transm it descriptor. When a new da ta transfer
is requested (either from the transmit buffer or an open request) the data management
unit repolls the descriptor. If the HOLD bit is r emoved, it will branch to the next transmit
descriptor. If the HOLD bit is still set, that channel is suspended for further operation.
Following requests from the transmit buffer will not be served, but the number of
requested data is stored in the open request registers.
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Functional Description
Data Sheet 71 05.2001
If the HOLD bit is detected in a descriptor and the frame end bit is not set, the data
management unit will transfer all data of the belongi ng data section to the transmit buffer.
Afterwards it generates a ’Hold Caused Transmit Abort’ interrupt vector in order to inform
the host CPU about the erroneous descriptor structure. In PPP and HDLC mode the
abort sta tus is propagated to the transmit buffer and the protocol m achine, so that a abort
sequence is sent on the serial side. In TMA mode the data management unit generates
a ’Hold Caused Transmit Abort’ interrupt vector every time it recognizes the HOLD bit.
Then it reads the transmit descriptor once more. If the HOLD bit is removed it branches
to the next tran smit descript or and proceeds with no rmal operation. Othe rwise, when the
HOLD bit is still set, the channel is suspended for further operation and an internal poll
bit is set. Following requests from the transmit buffer will not be served, but the number
of requested data is stored in the open request register.
The host CPU can remove the hold condition, when the next transmit descriptor is
availa ble in sy stem m emory. There fore the CPU has to execu te a ’Trans mit Hold Rese t’
comma nd, which will reactive the channel. Wh en the transm it buffer requ ests a new da ta
transfer o r when open re quest a re st ored in the on- chip d atabas e the da ta man ageme nt
unit repolls the transmit descriptor and checks the HOLD bit again. If the HOLD bit is
removed it branches to next transmit descriptor.
If the CPU issues a ’T ransm it Hold R eset’ com mand an d does not remove the HOLD bit
(erroneous programming), no action will take place. Nevertheless, the CPU always has
to issue a ’Transmit Hol d Reset’ co mmand when it re moves the H OLD bit in a des criptor,
no matter the data management unit has already seen the HOLD bit or not.
4.3.6 Byte Swapping
The TE3-CHATT operates per default as a little endian device. To support integration
into big endian environments, the data management unit provides an internal byte
swapping mechanism, which can be enabled via bit CONF1.LBE.
The big endian swapping applies only to the data section pointed to by the receive and
transmit descriptors in the shared memor y .
Note: Byte s wap ping only effe cts th e organiza tion of pac ke t data in sy st em memory. Al l
internal registers, as wel l as the descriptors, addres s pointers or interrupt v ectors
are handled with lit tle e ndian byte ordering.
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Functional Description
Data Sheet 72 05.2001
Table 4-3 Example for little/big Endian with BNO = 3
Table 4-4 Example for little big Endian with BNO = 7
4.3.7 Transmissi on Bit/ Byte Orde ring
Data is transmitted beginning with byte zero in increasing order. Vice versa data
received is stored starting with byte zero. The position of byte zero depends on the
selected endian mode.
Each byte itself consists of eight bits starting with bit zero (LSB) up to bit seven (MSB).
Data on the se rial l ine i s tran smitte d sta rting wi th the LSB. Th e firs t bit received is s tored
in bit zero.
4.4 Buffer Management
4.4.1 Internal Receive Buffer
The internal receive buffer provides buffering of frame data and status between the
protocol handler and the receive data management units. Internal buffers are essential
to avoid data loss due to the PCI bus latency, especially in the presence of multiple
devices on the same PCI bus, and to enable a minimized bus utilization through burst
accesses.
The incom ing data from the prot oc ol han dle r is sto red in a receiv e ce ntral buffe r share d
by all the 256 channels. The buffer is written by the protocol handler every time a
comple te D W ORD i s read y o r th e l ast by te o f a frame has be en rec eiv ed . Eac h c ha nnel
has an individual programmable threshold code, which determines after how many
DWORDs a da ta t r ans fer int o th e s hare d m em ory is gen era ted . The threshold the r efo re
defines the maximum burst length for a particular channel in receive direction. A data
transfer is also requested as soon as a frame end has been reached. Programming the
burst length to be greater than 1 DWORD avoids too frequent accesses to the PCI bus,
thereby optimizing use of this resource.
For real time channels with lowest possible latency (example: constant bit rate) a value
of one DWORD can be selected for the burst length.
BNO Little Endian Big Endian
3 - Byte 2Byte 1Byte 0Byte 0Byte 1Byte 2 -
BNO Little Endian Big Endian
7 Byte 3 Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 Byte3
- Byte 6Byte 5Byte 4Byte 4Byte 5Byte 6 -
PEB 3456 E
Functional Description
Data Sheet 73 05.2001
The t otal siz e of th e inte rnal re cei ve buffer is 12 k Byte. If all t he 256 ch annel s are activ e,
the aver age burst thresho ld should be pro grammed with 8 DWORDs, so that 4 DWORDs
are available on the average to compensate for PCI latency and avoid data loss.
Howeve r if les s tha n 25 6 cha nne ls are ac tiv e or if on ly 64 KBit/s cha nn els are us ed, the
burst threshold may be programmed to a higher value. In other words, the sum of all
channel thresholds shall not exceed the maximum receive buffer locations.
In order t o prev ent an overlo ad co ndition f rom one p articular cha nnel (e.g. receivi ng only
small or invali d frames) , the recei ve buffer provides the capabil ity to de lete frame s which
are sma ller o r equal than a p rogram mable thresh old. Al l fr ames tha t hav e been droppe d
will be counted and an interrupt vector will be generated as soon as a programmable
threshold has been reached. The actual value of the counter can be read in the small
frame dropped counter register.
PEB 3456 E
Functional Description
Data Sheet 74 05.2001
•
Figure 4-7 Receive Buffer Thresholds
For performance monitoring the receive buffer provides the capability to monitor the
receive buffer utilization and to generate interrupts when certain fill thresh olds have been
reached.
4.4.2 Internal Transmit Buffer
The internal transmit buffer with a total size of 32 kByte stores protocol data before it is
processed by the protocol machine. The transmit buffer is essential to ensure that
enough data is available during transmission, since PCI latency and usage of multiple
minimum frame length
receive burst threshold receive burst threshold
data management unit
receive buffer
frame
protocol machine
minimum fra me length
receive burst threshold
receive buffer
protocol machine
data management unit
1
st
burst 2
nd
burst
frame
delete
Example B:
Drop of small frames
Example A:
Normal operation
PEB 3456 E
Functional Description
Data Sheet 75 05.2001
channels limit access to system memory for a particular channel. A programmable
transmit buffer size and two programmable threshold are configurable by the host CPU
for each channel.
Note: The sum of both thresholds must be smaller than the transmit buffer size of a
particular channel.
•
Figure 4-8 Transmit Buffer Thresholds
The threshold values have the following effect:
• Data belonging to one channel stored in the internal transmit buffer will only be
transferred to th e protoco l ma chine when the tra nsmi t forw ard th reshol d is rea ched or
if a complete frame is stored inside the transmit buffer. This mechanism avoids data
underrun conditions.
transmit forward threshold
transmit refill threshold
data management unit
transmit buffer
protocol machine
frame
wait with data trans-
mission until buffer level
reaches transmit forward
threshold
request new data as long
as number of empty
locations is above
transmit refill threshold
programmable number of
buffer locations per
channel
PEB 3456 E
Functional Description
Data Sheet 76 05.2001
• As long as the amount of data stored in the transmit buffer is below the transmit refill
threshold the data management unit will keep filling the buffer by initiating PCI burst
transfers.
Note: Since th ere is a delay be tween the tim e the t ransm it buffe r requests data fro m the
data m anagement u nit and the time the data manage ment unit s erves the request,
the actual number of empty locations may be higher than the transmit refill
threshol d. To determin e the maximum PCI bu rst length an ad ditional pa rameter is
available which limits these requests up to a maximum of 64 DWORDs.
4.5 Prot ocol Descripti on
The protocol machines provide protocol handling for up to 256 channels. The protocol
machines implement 4 modes, which can be programmed independently for each
channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and transparent mode A.
The configuration of each logical channel is programmed via the PCI bus and will be
stored inside the protocol machines. Furthermore the current state for the protocol
processing (CRC check, 1 bit count,...) is also stored inside the protocol machines.
Each protocol machine (receive, transmit) handles a maximum of 256 channels and a
maximum aggregate bit rate of up to 45 Mbit/s.
4.5.1 HDLC Mode
•
Figure 4-9 HDLC Frame Format
The frame begin and frame end synchronization is performed with the flag character
7EH. Shared opening and closing flag is supported in receive direction and can be
programmed in the channel configuration register for transmit direction. Shared ‘0’ bit
between two flags is only supported in receive direction. Interframe time-fill can be
programmed to either flag 7EH or FFH indicating idle.
In receive operation, prior to Frame check sum (FCS) computation, any ‘0’ bit that
directly follows five contiguous ‘1’ bits is discarded. When closing flag is recognized, a
CRC check, octet boundary check, MFL (maximum frame length) check, a sho rt frame
check and an additional small frame check are performed. Short frames have less than
4 octets if CRC16 is used or less than 6 octets if CRC32 is used. An aborted frame is
recognized if 7 or more ‘1’s are received.
In transmit operation after the CRC computa tion a ‘0’ b it is inserted afte r every sequence
of five contiguous ‘1’ bits. When frame end is indicated in the belonging transmit
descriptor the calculated CRC is transmitted and a flag is generated. If an underrun
Flag
0111 1110 Address
8 bits Control
8 bits Information
<=0 Bits CRC
16/32 bits Flag
0111 1110
PEB 3456 E
Functional Description
Data Sheet 77 05.2001
occurs in the internal transmit buffer (because of PCI latency e.g.) an abort sequence
with 7 ‘1’s is transmitted and an underrun interrupt is generated. The abort sequence is
also generated if the host CPU resets or aborts a channel during the transmission of a
frame.
An invert option is provided to invert all the data output or data input between serial line
and protocol machines or vice versa.
The following CRC modes are supported:
• 16 b it CRC 1+x 5+x12+x16
• 32 b it CRC 1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
Optionally CRC transfer and check can be disabled.
4.5.2 Bit Synchronous PPP with HDLC Framing Structure
•
Figure 4-10 Bit Synchronous PPP with HDLC Framing Structure
Same as HDLC. The handling of the abort sequence differs from that in HDLC mode. If
7EH is programmed as interframe time fill character, the abort sequence consists of 7
“1”s. If FFH is program med as inte rframe tim e fill ch aracter, t he abort se quenc e consi sts
of 15 “1”s.
The same programmable parameters as in HDLC mode apply to bit synchronous PPP.
4.5.3 Octet Synchronous PPP
This mode uses a frame structure similar to the bit synchronous PPP mode. The frame
begin and end synchronization is performed with the flag character (7EH). Use of a
shared op ening and clo sing flag is sup ported if program med in the cha nnel configur ation
register. Use of a shared ’0’ bit between two flags is not supported. A 16 or 32 bit CRC
is com puted o ver all servi ce dat a read fro m the tr ansmi t buffer and app end ed to th e end
of the frame.
The octet synchronous PPP mode uses oc tet stuffin g instead of ‘0’ bit stuffin g in order to
replace control characters used by intervening hardware equipment. This allows
transparent transmission and also recognition and removal of spurious characters
inserted by such equipment.
A 32 bit per channel asynchronous control character map (ACCM) specifies characters
in the range 00H-1FH to be stuffed/destuffed in service data and FCS field. In addition,
the DEL control character (7FH ) and any of 4 ACCM extension characters stored in a
programmable 32 bit register can be selected for character stuffing/destuffing. When a
Flag
0111 1110 Address
1111 1111 Control
0000 0011 Protocol
8/16 bit s Information Padding FCS
16/32 bits Flag
0111 1110
PEB 3456 E
Functional Description
Data Sheet 78 05.2001
charact er s pec ifi ed to b e m ap ped is fou nd in s erv ic e d ata or th e F CS fie ld, it i s re pl ace d
by a 2 octet sequence consisting of 7DH (Control Escape) followed by the character
EXORed with 20H (e.g. 13H is mapped to 7DH 33H). In addition to the per channel
specification of characters to be mapped, the control escape sequence 7DH and 7EH in
the serv ice data stream are always ma pped. Openi ng and closing fl ags are not affe cted.
The abo rt sequence consists o f the c ontrol escape character fo llowed by a flag cha racter
7EH (not stuffed).
Between two frames, the interframe time fill character is always 7EH.
If in the transmit d irection a data u nderrun oc curs durin g transmi ssion o f a frame an d the
frame has not finished, an abort sequence is automatically sent (escape character
follow ed by a flag) and an unde rrun int erru pt vect or wil l gene rate d. If the tran sm it buf fer
indicates an empty condition for a channel between two frames (idle or interframe fill),
the protocol machine will continue to send interframe time fill characters. Also an abort
sequence will be generated if a channel is reset or an abort command is issued during
transmission of a frame.
The following CRC modes are supported:
• 16 b it CRC 1+x 5+x12+x16
• 32 b it CRC 1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
CRC computat ion/check o r removing can be d isabled.
4.5.4 Transparent Mode
When programmed in transparent mode, the protocol machine performs fully
transparent data transmission/reception without HDLC framing, i.e. without
• Flag insertion/removing
• CRC generation/CRC check
• Bit stuffing/destuffing (0 bit insertion/removal).
An option ‘Transparent Mode Pack’ is provided to support subchanneling. If
subchanneling is used (logical channels of less than 64 kbit/s), masked bits in the
protocol data are set high and each bit in shared memory maps directly to enabled (not
maske d) bits on th e serial lin e. Ot herwise they contai n pr otocol d ata, th at i s each byte i n
shared memory maps directly to a time slot.
A programmable transparent flag can be programmed which will be inserted between
payload data or is removed during reception of a payload data.
An invert option is provided to invert the outgoing or incoming data stream.
4.6 T1 Framer and FDL Function
The T1 framer includes frame alignment, CRC-6 check/generation, facility data link
(FDL) sup port and bit error rate test. Three modes can be progra mmed for each T1 link:
F4, ESF (F24), SF (F12).
PEB 3456 E
Functional Description
Data Sheet 79 05.2001
4.6.1 4-Frame Multiframe
The allo catio n of the F T bits (bi t 1 of frames 1 and 3) f or frame a lignment signal i s show n
in Table 4-5.
The FS bit may be used for signaling.
Remote alarm (yellow alarm) is indicated by setting bit(2) to ‘0’ in each channel.
Table 4-5 4-Frame Multiframe Structure.
Synchronization Procedure
For multiframe synchronization, the terminal framing bits (FT bits) are observed. The
synchronous state is reached if at least one terminal framing candidate is definitely
found, or the synchronizer is forced to lock onto the next available candidate
(RCMDR.FRS).
Frame Number FTFS
1
2
3
4
1
–
0
–
Service bit
Service bit
PEB 3456 E
Functional Description
Data Sheet 80 05.2001
4.6.2 ESF Mode
The ESF multif rame consi sts of 24 consec utive frames. Th e first bit of each frame (F bit)
is used as frame alignment, data link channel and CRC-6 channel (see Table 4-6).
Table 4-6 ESF Multiframe Structure
F bits
Frame
number Superframe
bit number
Framing Pattern
Sequence
(FPS)
Data link
(DL)
Cyclic
redundancy
check
(CRC-6)
10 - m -
2193 - - c1
3386 - m -
4579 0 - -
5772 - m -
6965 - - c2
7 1158 - m -
8 1351 0 - -
9 1544 - m -
10 1737 - - c3
11 1930 - m -
12 2123 1 - -
13 2316 - m -
14 2509 - - c4
15 2702 - m -
16 2895 0 - -
17 3088 - m -
18 3281 - - c5
19 3474 - m -
20 3667 1 - -
21 3860 - m -
22 4053 - - c6
PEB 3456 E
Functional Description
Data Sheet 81 05.2001
Frame 1 is transmitted first. Bit 1 (most significant bit) of each frame is transmitted first.
4.6.2.1 Multiframe Synchronization Procedure of the Receiver
The F-bit of every fourth frame forms the pattern 001011. This multiframe alignment
allow s to identi fy where eac h par ticula r frame is loca ted wit hin the mu ltifram e in order to
extract the cyclic redundancy check code (CRC-6) and the data link information.
In the synchronous state two errors within 4 or 5 framing bits, two or more erroneous
framing bi ts within one ESF multifra me or 4 conse cu tiv e erro red m ult ifra me s w ill lea d to
the asynchronous state.
There are two multiframe synchronization modes selectable via RFMR.SSP:
0 In the synchronous state, the setting of RCMDR.FRS resets the synchronizer
and initi ates a new frame s earch . The s ynchro nous state wi ll be reache d a gain,
if there is onl y one def inite frami ng ca ndidate. In the case of repeated app arent
simulated candidates, the synchronizer remains in the asynchronous state.
In asynchronous state, setting bit RCMDR.FRS induces the synchronizer to
lock onto the next available framing candidate if there is one. At the same time
the internal framing pattern memory will be cleared and other possible framing
candidates are lost.
1 In the sync hronous stat e, the setting of RCMR.FR S resets the syn chronizer an d
initiates a new frame search. Synchronization is achieved if there is only one
definite framing candidate AND the CRC-6 checksum is received without an
error. If the CRC-6 check failed on the assumed framing pattern the TE3-
CHATT will stay in the asynchronous state, searching for an alternate framing
pattern.
In case no alternate framing pattern can be found, setting bit RCMDR.FRS
starts a totally new multiframe search. At the same time the internal framing
pattern memory will be cleared and other possible framing candidates are lost.
4.6.2.2 CRC-6 Generation / Check according to ITU-T G.706
Generation
In calculating the CRC-6 bits, the F-bits are replaced by binary 1s. All information in the
other bit positions will be identical to the information in the corresponding multiframe bit
positions.
The CRC-6 bit sequence c1, c2, c3, c4, c5, c5 and c6 calculated on multiframe N is
transmitted in multiframe N+1. This CRC polynomial is defined as the remainder after
23 4246 - m -
24 4439 1 - -
PEB 3456 E
Functional Description
Data Sheet 82 05.2001
multipl ic ati on by x6 and then di vi si on (m odulo 2) by the generator polynom ial x6+ x+ 1 of
the polynomial corresponding to multiframe N. The first check bit c1 is the most
significant bit of the remainder; the last check bit c6 is the least significant bit of the
remainder.
Check
At the receiver, the received multiframe, with each F-bit having first been replaced by a
binary 1, is acted upon by the multiplication/division process described above. The
resulting remainder is compared on a bit-by-bit basis, with the CRC-6 check bits
contained in the subse que ntly receiv ed mu ltif ram e.
In synchronous state a received CRC-6 error may g enerate an interrupt status and will
increment a CRC-6 counter.
4.6.2.3 Remote Alarm (Yellow Alarm) Generation / Detection
Generation
If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing
data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote
Alarm is also sent unconditionally when TCMDR.XRA=’1’. ESF RA is sent by repeating
the pattern ‘1111 1111 0000 0000’ in the Data Link (DL).
Detection
Remote Ala rm (yellow alarm) is detected and flagged with bit FRS.RRA when the pattern
’1111 1111 0000 0000’ is received in the DL bits if RFMR.SRAF=0. If RFMR.SRAF=1,
yellow alarm is detected when every bit2 of each time slot is 0. If RFMR.RRAM is set,
Remote Alarm can be detected even in the presence of BER 1/1000. FRS.RRA will be
reset automatically when the alarm condition is no longer detected.
4.6.2.4 Facility Data Link
The Facility Data Link (FDL) contains bit oriented messages (priority or command/
response) or HDLC-based message oriented signals that are processed by a HDLC
machine. Each T1 port has its dedicated FDL controller. In HDLC mode CRC16 is
supported. Additionally one or two byte address comparison is supported.
Note: CAS - BR (Channel Associated Signalling - bit robbing) is not supported. The
proto col machines support acce ss to 56 kBi t/s or 64 kB it/s data channe ls with the ir
bit masking function. If CCS (Common Channel Signalling) is used, the
corresponding channel (usually time slot 24) is handled as a standard data time
slot by the HDLC/PPP machine and the data is transferred via the PCI bus.
PEB 3456 E
Functional Description
Data Sheet 83 05.2001
In transm it a nd receive direct ion 64 b yte dee p FIFOs di vi ded into tw o pa ge s of 32 bytes
are provided for the intermediate storage of data between the HDLC machine and the
CPU interface.
Receive Signaling Controller
Each of the signaling controllers may be programmed to operate in various signaling
modes. The TE3-CHATT will perform the following signaling and data link methods on
the DL-Channel of the ESF format:
•HDLC/SDLC Access
In case of common channel signaling the signaling procedure HDLC/SDLC will be
supported. The signaling controller of the TE3-CHATT performs the flag detection,
CRC checking, address comparison and zero bit-removing. Depending on the
selected address mode, the TE3-CHATT may perform a 1 or 2 byte address
recognition. If a 2-byte address field is selected, the high address byte is compared
with two individually programmable values in register RAH. Buffering of receive data
is done in the RFIFO. Refer also to Chapter 4.8.1.
•Transparent Access
In signaling controller transparent mode, fully transparent data reception without
HDLC framing is performed, i.e. without flag recognition, CRC checking or bit-stuffing.
This allows the user spec if ic prot oc ol vari ati ons .
•Bit Oriented Messages in ESF-DL Channel
The TE3-CHAT T suppo rts t he DL-cha nnel p rotocol for ESF form at accordi ng to ANSI
T1.403 specification or according to AT&T TR54016. The Bit Oriented Message
(BOM) receiver may be switched on/off separately. If the TE3-CHATT is used for
HDLC formats only, the BOM receiver has to be switched off. If BOM-receiver has
been swi tched on, an autom atic switchi ng between HDL C and BO M mode is enable d.
If eight or more consecutive ones are detected, the BOM mode is entered. Upon
detectio n of a flag in th e dat a stream, the TE3 -CH ATT swit ches bac k to HDLC- mode.
In BOM-mo de, the fol lowing byte form at is as sumed (the left most bit is receiv ed first).
111111110xxxxxx0
The TE3-CHATT uses the FFH byte for synchronization, the next byte is stored in
RFIFO (first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting or ending
with a ‘1’ are not store d. If there are no 8 conse cutive one’s detected wi thin 32 bits an d
the TE3-CHATT is currently in the BOM mode, an interrupt is generated. However,
byte sampling is not stopped.
Transmit Signaling Controller
Similar to the receive signaling controller the same signaling method is provided. The
TE3-CHATT will perform the following signaling and data link methods on the DL-
channel of the ESF format:
PEB 3456 E
Functional Description
Data Sheet 84 05.2001
•HDLC access
The t ransmi t signa ling cont rolle r of t he TE3- CHATT pe rforms the FLA G generat ion,
CRC generation, zero bit-stuffing and programmable IDLE code generation. Buffering
of transmit data is done in the 2x32 byte deep transmit FIFO. The signaling
informati on wi ll be interna lly mult ipl ex ed with the dat a appl ied to the outgoi ng ports .
•Transpare n t/BO M mode
In signaling controller transparent mode, fully transparent data transmission without
HDLC framing is performed. Optionally the TE3-CHATT supports the continuous
transmission of the XFF.XFIFO contents with a maximum of 32 bytes.
Operati ng in H DLC or BOM mode “flag s” or “idl e” may b e transmitted as inte rframe tim e-
fill.
PEB 3456 E
Functional Description
Data Sheet 85 05.2001
4.6.3 SF Mode
The SF multiframe consists of 12 consecutive frames. The first bit of each frame (F-bit)
the TE3-CHATTis used as frame alignment (see following table).
Table 4-7 SF Multiframe Structure
The Fs-bits are used to get a higher synchronization probability but no CAS - BR
(Channel Associated Signalling - bit robbing) is supported. Only frame alignment is
provided in this mode.
4.6.3.1 Synchronization Procedure of th e Receiver
In the synchronous state terminal framing (Ft-bits) and multiframing (Fs-bits) are
observed, independently. Further reaction on framing errors depends on the selected
synchronization/resynchronization procedure (via bit RFMR0.SSP):
0 Terminal frame and multiframe synchronization are combined. Two errors
within 4/5/ 6 F t-bi ts or two e rrors w ith in 4/5 /6 in Fs-bits (v ia bi ts R FM R.SSC ) wil l
lead to the asynchronous state for terminal framing and multiframing.
Additionally to the bit FRS.LFA, loss of multiframe alignment is reported via bit
FRS.LMFA. The resynchronization procedure starts with synchronizing upon
the terminal framing. If the pulseframing has been regained, the search for
F-bits
Frame
number S uperframe bit
number Terminal Framing (Ft) Signaling Framing (Fs)
10 1 -
2 193 - 0
3 386 0 -
4 579 - 0
5 772 1 -
6 965 - 1
71158 0 -
81351 - 1
91544 1 -
10 1737 - 1
11 1930 0 -
12 2123 - 0
PEB 3456 E
Functional Description
Data Sheet 86 05.2001
multif rame alignm ent is in itiated. Multifra me synchron ization has been regained
after two consecutive correct multiframe patterns have been received.
1 Terminal frame and multiframe synchronization are separated. Two errors
within 4/5/6 terminal framing bits will lead to the same reaction as described
above for the ’combined’ mode. Two errors within 4/5/6 multiframing bits will
lead to the asynchronous state only for the multiframing. Loss of multiframe
alignment is reported via bit FRS.LMFA. The state of terminal framing is not
influenced. Now, the resynchronization procedure includes only the search for
multiframe alignment. Multiframe synchronization has been regained after two
consecutive correct multiframe patterns have been received.
4.6.3.2 Remote Alarm (Yellow Alarm) Generation / Detection
There are two possibilities of remote alarm (yellow alarm) indication:
• Bit 2 = ’0’ in each time slot of the frame, selected with bit R/TFMR.SRAF = 0
• The last bit of the multiframe alignment signal (bit 1 of frame 12) changes from ’0’ to
‘1’, select ed with bit R /TFM R.SR AF = 1.
Generation
If TFMR.AXRA=1, the remote alarm sequence will be automatically sent in the outgoing
data stream when the receiver is in asynchronous state (FRS.LFA bit is set). Remote
Alarm is also sent unconditionally when TCMDR.XRA = 1.
Detection
Remote alarm (yellow alarm) is detected and flagged with bit FRS.RRA which will be
reset automatically when the alarm condition is no longer detected.
PEB 3456 E
Functional Description
Data Sheet 87 05.2001
4.6.4 Common Features for SF and ESF
4.6.4.1 AIS (Blue Alarm) Generation/Detection
Generation
The alarm indication signal is an all one unframed signal and will be transmitted if
enabled via bit TCMDR.XAIS.
Detection
The detec tion of AIS i s done, if 2 or less ’0’s a re de tected in a mult iframe . This co nditio n
is flagge d by bit FRS .AIS. AIS detectio n can also only be enab led in asyn chronous state
by bit RFMR0.AIS3. In this case AIS is indicated if three or less zeros within a time
interval of 12 frames (in SF mode), or if five or less zeros within a time interval of 24
frames (ESF mode) are detected in the received bit stream.
4.6.4.2 Loss of Signal (Red Alarm) Detection
The TE3-CHATT can be programmed to satisfy the different definitions for detecting
Loss of Signal (LOS) alarms in ITU-T G.775 and AT&T TR54016. Loss of signal is
indica ted by a flag in the rece ive fra mer's s tatus re gister (F RS.LO S). In add ition, a ’Los s
of Signal Status’ interrupt vector is generated, if not masked.
LOS detection and recovery conditions are set by a flag RFMR.LOSR and the two
parameters PCD and PCR.
Detection
’Loss of Signal’ alarm will be generated, if the incoming data stream has no pulses (no
’1’) for a c erta in n umb er N of con se cu tiv e bi ts. ’N o pu ls e’ i n the rec eiv e i nte rfac e m ean s
a logi cal ze ro oc tet o n recei ve dat a input s. Th e numb er N can be set via re giste r PCD
and is calculated as 8*(PCD+1).
Recovery
The rec overy proce dure s tarts a fter de tectin g a l ogica l ’1’ in th e rec eived bit stre am. Th e
value via register PCR defines the number of pulses, which must occur during the time
interval 8*(PCD+1), to clear the LOS alarm.
Additionally, if selected via RFMR.LOSR, any pulse density violation resets the
measurement interval. I.e. in addition to the basic pulse density required for recovery, a
density of at least N ‘1’s in every N+1 octets (0 < N < 24) is required during 8*(PCD+1)
bit intervals.
PEB 3456 E
Functional Description
Data Sheet 88 05.2001
4.6.4.3 In-Band Loop Generation and Detection
The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate
(00001) and down/deactuate (001) pattern according to ANSI T1.403 even in the
prese nce of bit error rates as high as 1/100. Replac ing the transmit data with the in-ban d
loop codes is done by TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3-
CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate
and down/deactuate pattern. The loop up and down pattern is individual programmable
in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Actuate- or Deactuate
code was detected, but the CPU must activate the loop-back.
4.6.4.4 Pulse Density Detection
The framer examines the receive data stream of each port on the pulse density
requirement defined by ANSI T1. 403. More than 15 consecutive zeros or less than N
ones in each and every time window of 8(N+1) data bits, where N=23 will be detected.
Violations of these rules are indicated by setting the status bit FRS.PDEN. Moreover the
PDEN bit in the interrupt vector will be set.
4.6.4.5 Error Performance Monitoring
The TE3-CHATT supports the error performance monitoring by detecting following
alarms in the rec eived data.
• Framing errors
• CRC errors
• Loss of frame alignment
• Los s of signal
• Alar m indication signal
Loss of frame alignment, Loss of signal and AIS are indicated with interrupt status bits.
With a prog rammable inte rrupt mask (regi ster IMR) all thes e error events co uld generate
an Errored Second interrupt (ES) if enabled. Additionally a one Second interrupt could
be genera ted to ind icate that the ES interru pt has to be re ad. If the ES interrupt is set the
enabled alarm status bits or the error counters have to be examined.
The following counters are implemented in the T1 framer:
• Framing Error Counter: This counter will be incremented when incorrect FT and FS
bits in SF mode or incorrect FPS bits in ESF format are received. Framing errors will
not be counted during asynchronous state.
• CRC Error Counter (Only ESF mode): The counter will be incremented when a
multiframe has been received with a CRC error. CRC errors will not be counted during
asynchronous state.
PEB 3456 E
Functional Description
Data Sheet 89 05.2001
• Errored block counter: This counter will be incremented, if a multiframe has been
received with framing errors or CRC errors (ESF only).
Cleari ng and u pda tin g of the counters is don e accord ing to b it R FMR1.ECM. If thi s bi t i s
reset, the error counter is permanently updated. Reading of actual error counter status
is always possible. The error counters are reset by reading the corresponding status
register. If RFMR1.ECM is set, every second the error counter will be latched and then
automatically reset. The latched error counter state should be read within the next
second.
4.6.4.6 Pseudo-random Bit Sequence Generator and Monitor
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers . Each PRBS bit err or will increm ent an error c ounter. An a dditio nal counter wil l
accum ulate the total number of rec eived bits. Synchro nization wi ll be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
4.7 E1 Framing and Signaling
The opera ting mod e of the T E3-CHATT is selec ted by p rogrammin g the ca rrier data ra te
and characteristics, multiframe structure, and signaling scheme.
The TE3-CHAT T im ple me nts the standard fram in g stru ctures for E1 o r PCM 30 (CEPT,
2048 Kbit/s) carriers. The internal HDLC controller supports signaling procedures like
signaling frame synchronization/synthesis and signaling alarm detection in all framing
formats.
Summary of E1- Framing Modes:
• Doubleframe format according to ITU-T G. 704.
• Multiframe format according to ITU-T G. 704
CRC-4 processing according to ITU-T G. 706.
• Multiframe format with CRC-4 to non CRC-4 interworking according to ITU-T G. 706.
After reset, the TE3-CHATT is switched into doubleframe format automatically.
Switching between the framing formats is done via bit T/RFMR.FM
PEB 3456 E
Functional Description
Data Sheet 90 05.2001
4.7.1 Doubleframe Format
The framing structure is defined by the contents of time-slot 0 (refer to Tab le 4-8).
Table 4-8 Allocation of Bits 1 to 8 of Time slot 0
1) Si-bits:
Reserved for international use. They are fixed to ‘1’.
2) Fixed to ‘1’. Used for synchronization.
3) Remote alarm indication:
In undisturbed operation ‘0’; in alarm condition ‘1’.
4) Sa-bits:
Reserved for national use. If not used, they should be fixed at ‘1’. Access to received information
via registers RSAW1-3. Transmission via registers XSAW1-XSAW3. HDLC signalling in bits
Sa4 -S
a8 is selectable.
4.7.1.1 Synchronization Procedure of th e Receiver
Synchronization status is reported via bit FRS.LFA. Framing errors are counted by the
Framing Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4
consec utive in cor rect FAS w ords or 3 or 4 consecu tive i ncorre ct serv ice wo rds (bi t 2 = 0
in time-slot 0 of every other frame not containing the frame alignment word), the
selection is done via bit RFMR.SSC. Additionally, the service word condition can be
disabled. When the framer lost its synchronization an status bit FRS.LFA is generated.
In asynchronous state, counting of framing errors will be stopped.
The r esynchr onizati on proc edure s tarts au tomati cally a fter reachi ng the as ynchron ous
state. Additionally, it may be invoked user controlled via bit RCMDR.FRS (Force
Resynchronization: the FAS word detection is interrupted. In connection with the above
conditions this will lead to asynchronous state. After that, resynchronization starts
automatically).
Bit
Alternate Number
Frames
12345678
Frame Containing t he
Frame Alignment Signal Si 0 0 1 1 0 1 1
1) Frame Alignment Signal
Frame not Containi ng
the Frame Alignment
Signal Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
1) 2) 3) 4)
PEB 3456 E
Functional Description
Data Sheet 91 05.2001
Synchronous state is established after detecting:
• a correct FAS word in frame n,
• the presence of the correct service word (bit 2 = 1) in frame n + 1,
• a correct FAS word in frame n + 2.
If th e ser vic e wo rd i n fram e n + 1 or t he FA S wo rd in fra me n + 2 or b oth ar e no t fo und
searchi ng f or th e ne xt F AS w ord wi ll b e s tart in frame n + 2 just after the prev io us fram e
alignm ent signal.
Reaching the asynchronous state causes the removal of FSR.LFA and additionally an
interrupt vector with LFA bit reset (if not masked). Undisturbed operation starts with the
beginning of the next doubleframe.
4.7.1.2 A-bit Access
If the TE3-CHATT detects a remote alarm indication in the received data stream the
interrupt status bit FRS.RRA will be set.
By setting TFMR.AXRA the TE3-CHATT automatically transmits the remote alarm
bit = 1 in the outgoing data stream if the receiver detects a loss of frame alignment
FRS.LFA = 1. If the receiver is in synchronous state FRS.LFA = 0 the remote alarm bit
will be reset.
4.7.1.3 Sa- bit Acce ss
The TE3-CHATT allows access to the Sa-bits via registers RSAW1-3 and XSAW1-3.
PEB 3456 E
Functional Description
Data Sheet 92 05.2001
4.7.2 CRC-4 Multiframe
The multiframe structure shown in Table 4-9 is enabled by setting TFMR.FM for the
transmitter and RFMR.FM for the receiver.
Multiframe : 2 submultiframes = 2 ×8 frames
Frame alignment: refer to Chapter 4.7.1 Doubleframe Format
Multiframe alignment: bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern ‘001011’
CRC bits : bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14
CRC block size: 2048 bit (length of a submultiframe)
CRC procedure: CRC-4, according to ITU-T G.704, G.706
Table 4-9 CRC-4 Multiframe Structure
ESpare bits for international use. E bits are replaced by XSP.XS13 and XSP.XS15 or automatic
transmission for submultiframe error indication.
SaSpare bits for national use. Sa-bit access via registers RSAW1-3 and XSAW1-3 is provided.
HDLC-signaling in bits Sa4 -S
a8 is selectable.
C1…C
4
Cyclic redundancy check bits.
ARemote alarm indication. Automatic transmission of the A-bit is selectable.
Sub-
Multiframe Frame
Number Bits 1 to 8 of the Frame
12345678
Multiframe I 0
1
2
3
4
5
6
7
C1
0
C2
0
C3
1
C4
0
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa5
1
Sa5
1
Sa5
1
Sa5
0
Sa61
0
Sa62
0
Sa63
0
Sa64
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa8
1
Sa8
1
Sa8
1
Sa8
II 8
9
10
11
12
13
14
15
C1
1
C2
1
C3
E
C4
E
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
Sa4
1
Sa4
1
Sa4
1
Sa4
1
Sa5
1
Sa5
1
Sa5
1
Sa5
0
Sa61
0
Sa62
0
Sa63
0
Sa64
1
Sa7
1
Sa7
1
Sa7
1
Sa7
1
Sa8
1
Sa8
1
Sa8
1
Sa8
PEB 3456 E
Functional Description
Data Sheet 93 05.2001
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16 bit CRC Error Counter
CEC (one error per submu lti fram e, ma xi mum ).
Additionally a CRC error interrupt vector with CRC set can be generated if enabled.
4.7.2.1 Synchronization Procedure of th e Receiver
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (fla gged at status bits FR S.LFA and FRS.LMFA) . Either edge of the se bits will caus e
an LFA interrupt.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by a FAS interrupt vector. For Doubleframe
synch roni za tion refer to Chapter 4.7.1. It may also be in vo ked by the us er by setti ng bit
RFMR.FRS for complete doubleframe and multifra me resynchronizat ion.
The CRC checking mechanism will be enabled after the first correct multiframe pattern
has been found. However, CRC errors will not be counted in asynchronous state.
The multiframe synchronous state is established after detecting two correct multiframe
alignment signals at an interval of n ×2 ms (n = 1, 2, 3 …). The loss of multiframe
alignment flag FRS.LMFA will be reset. Additionally a multiframe alignment status
interrupt MFAS is generated on the falling edge of bit FRS.LMFA.
Automatic Force Resynchronization
In addition, a search for Doubleframe alignment is automatically initiated if two
multifra me pa tter n with a dis tance of n ×2 ms hav e not been found w ithin a time inte rval
of 8 ms after doubleframe alignment has been regained. The new search for frame
ali gnment wil l be started just after the previous f rame alignment signal.
CRC-4 Interworking Mode
CRC-4 interworking is implemented according to ITU-T G.706 Appendix B. For
operational description refer to Figure 4-11.
4.7.2.2 CRC-4 Performance Monitoring
In the synchronous state checking of multiframe pattern is disabled. However, with bit
RFMR.ALMF an automatic multiframe resynchronization mode can be activated. If 915
out of 1000 errored CRC submultiframes are found then a false frame alignment will be
assumed and a search for double- and multiframe pattern is initiated. The new search
for frame alignment will be started just after the previous basic frame alignment signal.
The internal CRC-4 resynchronization counter will be reset when the multiframe
synchronization has been regained.
PEB 3456 E
Functional Description
Data Sheet 94 05.2001
4.7.2.3 A-Bit Access
If the TE3-C HATT de tects a remot e alarm in dication (bit 2 in TS 0 not conta ining the FAS
word) in the received data stream a RAS interrupt will be generated. With the
deactivation of the remote alarm the remote alarm status interrupt with RAS=’0’ is
generated.
By setting TFMR.AXRA the TE3-CHATT automatically transmits the remote alarm
bit = ’1’ in the outgoing data stream if the receiver detects a loss of frame alignment
(FRS.LFA = ’1’). If the recei ver is in synchron ous state (FR S.LFA = ’0’) the rem ote alarm
bit will be reset in the outgoing data stream.
PEB 3456 E
Functional Description
Data Sheet 95 05.2001
•
Figure 4-11 CRC-4 Multiframe Alignment Recovery Algorithm s
Out of primary B FA:
Inhibit incoming CRC-4 performance monito ring
Reset all timers
Set FRS.LFA/LMFA/NMF = 110
B
.
Primary
BFA search ?
In primary BFA:
Start 400 ms timer
Enable primary BFA (loss checking procedure)
Reset internal frame alignment status
(FRS.LFA = 0)
CRC-4 MFA search
Start 8 ms timer
Parallel
BFA search
good ?
400 ms
timer
elapsed ?
Can CRC-4
MFA be found
in 8 ms ?
Assume CRC-4 to non CRC-4 interworking
Confirm primary BFA
Set internal 400 ms timer expiration status bit
(FRS.T400 = 1)
Assume CRC-4 to CRC-4 interworking
Confirm primary BFA associated with CRC-4 MFA
Adjust primary BFA if necessary
Reset internal multiframe alignment status
(FRS.L MFA = 0)
Start CRC-4 performance monitoring
CRC-4
error count > 914
or LFA Continue CRC-4 performance monitoring
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
PEB 3456 E
Functional Description
Data Sheet 96 05.2001
4.7.2.4 Sa- bit Acce ss
Due to s ignaling proced ures using the five Sa-bits (Sa4 …S
a8) of every other frame of the
CRC-4 multiframe structure, two possibilities of access via the microprocessor are
implemented.
• The standard procedure, allows read ing/writing th e Sa-bit registers RSAW1 to RSAW3
and XSAW1 through XSAW3.
Registers RSAW1-3 contains the service word information of the previously received
CRC-4 multiframe or 8 doubleframes (bit slots 4-8 of every service word). These
registers will be updated on every multiframe. Optionally TE3-CHATT provides the
possibi lity to check th e rece ived Sa-da ta with the Sa-da ta received e arlier. An interru pt
vector is generated on Sa-data change in order to reduce microprocessor bus load.
With the transmit multiframe begin the contents of this registers XSAW1-3 will be
copied into shadow registers. The contents will subsequently sent out in the service
words of the next outgoing CRC-4 multiframe (or doubleframes). The TXSA interrupt
request tha t these regis ters should be se rviced. If requ ests for new info rmation w ill be
ignored, current contents will be repeated.
• The ex tended acc ess via the receive an d transmit FIFO s of the sign aling con troller. In
this mode it is po ssible to transm it / rece ive a H DLC fra me or a trans parent b it strea m
in any combination of the Sa-bits.
Sa-bit Detecti on accord ing t o ETS 300233
Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit
combinations. The TE3-CHATT can be programmed to detect any bit combination on
one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via
register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The
correspo nding st atus in re gister RSAW4 will be set. Regis ter RSAW4 is from t ype “Clear
on Read”. With any change of state of the selected Sa-bit combinations a ’SSM Data
Valid’ interrupt vector will be generated.
During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit
combin ations can be do ne eit her sy nchron ous o r asy nchron ous to the sub multi frame. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch . state. I n asynchro nous detection mode upd ating is indepen dent to the mu ltiframe
synchronous state.
Sa-bit Error Indication Counters
The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit
sequenc e 0001B a nd 001 1B or two use r programm ab le val ue s d efi ned in register VCR C
in every submultiframe on a selectable Sa-bit . In th e prim ary r ate ac cess digi tal secti on
CRC errors are reported from the TE via Sa6. Incrementing is only possible in the
multiframe synchronous state.
PEB 3456 E
Functional Description
Data Sheet 97 05.2001
The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit
sequenc e 0010B a nd 001 1B or two use r programm ab le val ue s d efi ned in register VCR C
in every submultiframe on a selectable Sa-bit . In th e prim ary r ate ac cess digi tal secti on
CRC errors detected at T-reference points are reported via Sa6. Incrementing is only
possib le in the multifram e syn ch ronous state.
4.7.2.5 E-Bit Access
Due to signalling procedures, the E-bits of frame 13 and frame 15 of the CRC-4
multiframe can be used to indicate received errored submultiframes:
no CRC error : E = ’1’
CRC error : E = ’0’
Standard Procedure
E-bits of the service word are replaced by values of bit XSP.XS13 and XSP.XS15.
Automatic Procedure
Values programmed in register Status information of received submultiframes is
automatically inserted in E-bit position of the outgoing CRC-4 Multiframe without any
further interventions of the microprocessor.
In the double- and multiframe asynchronous state the E-bits are set to zero. In the
multiframe synchronous state the E-bits are processed according to ITU-T G.704.
Submultiframe Error Indication Counter
The Error Bi t Counter counts z eros in E-b it position of frame 1 3 and 15 o f every re ceived
CRC-4 multiframe. This counter option gives information about the outgoing transmit line
if the E-bits a re used by the remot e end for su bmulti frame erro r indicatio n. Incre mentin g
is only possible in the multiframe synchronous state.
PEB 3456 E
Functional Description
Data Sheet 98 05.2001
4.7.3 Common Features for E1 Doubleframe and CRC-4 Multiframe
4.7.3.1 Error Performance Monitoring and Alarm Handling
Alarm detection and generation
Alarm Indication Signal:
Detection and re covery is flagged by bit FRS.AIS and the ’Alarm Indica tion Signal Status’
interrupt vector. Transmission is enabled via bit TFMR.XAIS.
Los s of Si gnal:
Detection and re covery is flag ged via b it FRS.LOS and a ’Loss o f Signal Status’ interrupt
vector.
Remote Alarm Indication:
Detec tion and relea se is flagg ed by bit FRS.RR A and a ’Remote Ala rm Sta tus ’ in terrupt
vector. Transmission is enabled via bit TCMDR.XRA.
Table 4-10 Summary of Alarm Detection and Alarm Release
Alarm Detection Conditi on Clear Condition
Los s of Si gnal
(LOS) PCD Register
No transitions (log. zero
octets) in a programmable
time interval of 16 - 512
co nsecutive pulse periods.
PCR Register
Programmable amount of ones
(1-63) in a progr. time interval of
16 - 512 consecutive pulse
periods. The pulse density is
fulfilled and no more than 15 or 99
contiguous zeros during the
recovery interval are detected.
Alarm Indication
Signal (AIS) FMR0.ALM = 0:
less than 3 zeros in
250 µs and loss of frame
alignment declared
FMR0.ALM = 1:
less than 3 zeros in each of
two consecutive double
frame periods
FMR0.ALM = 0:
more than 2 zeros in 250 µs and
frame alignm en t found
FMR0.ALM = 1:
more than 2 zeros in each of two
consec utive doubl e frame period s
Remote Alarm
(RRA) bit 3 = 1 in time-slot 0 not
containing the FAS word set conditi ons no l onger dete cted.
PEB 3456 E
Functional Description
Data Sheet 99 05.2001
Automatic remote alarm access
If the receiver has lost its synchronization a remote alarm could be sent if enabled via
TFMR.AXRA to the distant end. The remote alarm bit will be automatically set in the
outgoing data stream if the receiver is in asynchronous state (FRS.LFA bit is set). In
synchronous state the remote alarm bit will be removed.
Error Counter
The TE3-CHATT framer offers four error counters, each of them has a length of 16 bit.
They record framing bit errors, CRC-4 bit errors. Updating the buffer is done in two
modes:
- one second boundary
- clear on read
In the o ne seco nd mode an inter nal one second timer will updat e these buffers an d reset
the counter to accumulating the error events. The error counter can not overflow. Error
events occurring during reset will not be lost.
Status: Errored Second
TE3-CHATT supports the error performance monitoring by detecting alarms or error
events in the received data.
Loss of frame alignment, including alarm indication signal and loss of signal, as well as
CRC errors could generate an Errored Second interrupt if enabled.
Second Timer
An one-sec on d tim er i nterr upt c oul d be inte rna lly gen erat ed to ind ica te th at the enabled
alarm status bits or the error counters have to be checked.
4.7.3.2 Loss of Signal Detection
The TE3-CHATT can be programmed to satisfy the different definitions for detecting
Loss of Signa l (LOS) alarms in ITU-T G.77 5 and ETS 300233. Loss of signa l is indicated
by a fl ag in the recei ve fram er's s tatu s r egi ste r (FRS.LOS). In ad di tion, a ’L os s o f Si gna l
Status’ interrupt vector is generated, if not masked.
Detection
’Loss of Signal’ alarm will be generated, if the incoming data stream has no pulses (no
’1’) for a certain number N of consecutive pulse periods. ’No pulse’ in the receive
interface means a logical zero on receive data inputs. The number N can be set via
register PCD and is calculated as 8*(PCD+1).
PEB 3456 E
Functional Description
Data Sheet 100 05.2001
Recovery
The rec overy proce dure s tarts a fter de tectin g a l ogica l ’1’ in th e rec eived bit stre am. Th e
value via register PCR defines the number of pulses, which must occur during the time
interval 8*(PCD+1), to clear the LOS alarm.
4.7.3.3 In-Band Loop Generation and Detection
The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate
(00001) an d down /deactuat e (001) pat tern acc ording to ANSI T1.403 with bit erro r rates
as high as 1/100. Replacing the transmit data with the in-band loop codes is done by
TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3-
CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate
and down/deactuate pattern. The loop up and down pattern is individual programmable
in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Up - or Loop Down
code was detected, but the CPU must activate the loop-back.
4.7.3.4 Pseudo-random Bit Sequence Generator and Monitor
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 215-1 or 220-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers . Each PRBS bit err or will increm ent an error c ounter. An a dditio nal counter wil l
accum ulate the total number of rec eived bits. Synchro nization wi ll be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
PEB 3456 E
Functional Description
Data Sheet 101 05.2001
Alarm Simulation
Alarm simulation does not affect the normal operation of the device, i.e. all channels
remain available for transmission. However, possible ‘real’ alarm conditions are not
reported to the processor or to the rem ote end when the dev ice is in the alarm simul ation
mode.
The alarm simulation is initiated by setting different code words in bit field FMR0.SIM.
The following alarms are simulated:
• Loss of Signal
• Alarm Indication Signal (AIS)
• Auxiliary pattern
• Loss of pulse frame
• Remote alarm indication
• Framing error counter
• CRC-4 error counter
• E-Bit error counter
Some of the above indications are only simulated if the TE3-CHATT is configured in a
mode where the alarm is applicable (e.g. no CRC-4 error simulation when doubleframe
format is enabled).
Setting a code word in bit field FMR0.SIM initiates alarm simulation. Error counting and
indication will occurs while this bit is set. After it is reset all simulated error conditions
disappear.
4.8 Signaling Controller Proto col Modes
The sign alling con trolle r provides a ccess to the da ta link and Sa bits of the T1 /E1 signals
and provides acce ss to the far end alarm and control channel (FEAC) and the C-bit parity
path maintenance data link channel. It operates in HDLC, BOM or automatic modes.
4.8.1 HDLC Mode
In HDLC mode the transmit signaling controller of the TE3-CHATT performs the FLAG
generation, CRC generation, zero b it-stuffing and programmable IDLE code ge neration.
Buffering of transmit data is done in the 2x32 byte deep transmit FIFO. The signaling
information will be internally multiplexed with the data applied to the outgoing ports and
is inserted in or extracted from the DL-Bits in T1 ESF mode or the Sa-bits in E1 modes.
Any sequence of Sa-bits can be specified for protocol insertion.
Shared Flags
The closi ng flag of a previou sl y tran sm itte d fram e simultan eously bec om es the ope nin g
flag of the following frame if there is one to be transmitted. The Shared Flag feature is
enabled by setting XCR1.SF.
PEB 3456 E
Functional Description
Data Sheet 102 05.2001
CRC check
As an option in HDLC mode the internal handling of received and transmitted CRC
checksum can be influenced via control bits RCR1.XCRC and XCR1.DISCRC.
• Receive Direction
The received CRC checksum is always assumed to be in the last two bytes of a frame,
immediately preceding a closing flag. If RCR1.XCRC is set, the received CRC
checksum will be written to RFIFO where it precedes the frame status byte. The
received CRC checksum is additionally checked for correctness.
• Transmit Direction
If XCR1.DISCRC is set, the CRC checksum is not generated internally. The checksum
has to be provided via the transmit FIFO (XFF.XFIFO) as the last two bytes. The
transmitted frame will only be closed automatically with a (closing) flag.
The TE3-CHATT does not check whether the length of the frame, i.e. the number of
bytes to be transmitted makes sense or not.
Address com par is on
An optional address comparison feature forwards all frames which match a
programmable address to the receive FIFO. Frames not matching the address are
discarded.
If a 2-byte address field is selected, the high address byte is compared with two
individually programmable values defined in register RAH. Similarly, two values can be
programmed in register RAL for the low address byte. A valid address is recognized
when the high byte and the low byte of the address field correspond to one of the
compare values. Thus, the TE3-CHATT can be called (addressed) with 4 different
address combinations.
In case of a 1-byte address, RAL will be used as compare registers. The HDLC control
field, da ta in the I -field and an additiona l status by te are tempo rarily sto red in the rec eive
FIFO.
Preamble Transmission
If enabled, a programmable 8-bit pattern XCR1.PBYTE is transmitted with a selectable
number of repetitions after interframe time-fill transmission is stopped and a new frame
is ready to be sent out.
Zero Bit Insertion is disabled during preamble transmission. To guarantee correct
function the programmed preamble value should be diffe rent from Receive Address Byte
values.
PEB 3456 E
Functional Description
Data Sheet 103 05.2001
4.8.2 Transparent Mode
In transparent mode, fully transparent data transmission/reception without HDLC
framing is performed, i.e. without FLAG generation/recognition, CRC generation/check,
or bit-stuffing. This feature can be profitably used e.g for:
• Specific protocol variations
• Tes t purposes
Data transmission is always performed out of the transmit FIFO (XFF.XFIFO). In
transparent mode receive data is shifted into the receive FIFO without protocol
processing.
If the transparent mode is selected, the TE3-CHATT supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to transmit FIFO, the command HND via the CMDR
register forces the TE3-CHATT to repeatedly transmit the data stored in transmit FIFO
to the remote end.
The cyc lic transm iss ion co ntinues until a reset com mand (HND. SRES ) is iss ued or wi th
resetting CMDR.XREP, after which continuous ‘1’-s are transmitted.
4.8.3 BOM Mode
The signalling controller supports the DL channel protocol for ESF format according to
ANSI T1.40 3 or according to AT&T TR5 4016. The Bit Orient ed Message (BOM ) rece iver
can be switched on or of f separate ly. If the signal ling con troller is used fo r HDLC form ats
only, the BOM receiver has to be switched off (RCR1.BRAC = ’0’). If HDL C and BOM
receiver are switched on, an automatic switching between HDLC and BOM mode is
done, which depends on the received bit sequence ( 01111110B or 11111111B). If eight
or more consecutive ones are detected, the BOM mode is entered automatically. Upon
detection of a flag in the data stream, the FDL-Macro switches back to HDLC-mode.
Once in BOM mode, if eight consecutive ones are not detected in 32 bits, a BOM header
error will be declared.
Transmi ssio n of BO M da ta is don e vi a the transparent mode of the sig nal li ng c ontro ll er.
BOM Regular Mode
The following byte format is assumed (the left most bit is received first):
111111110xxxxxx0B
The sign allin g cont roller u ses th e FFH by te for s ynchroni zatio n, th e next by te is s tored i n
the receive FIFO (first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting or
ending with a ‘1’ are not stored. If there are no 8 consecutive one’s detected within 32
bits and the FDL-Macro is currently in the BOM mode, an ’Incorrect Synchronization
Format’ interrupt vector is generated. However, byte sampling is not stopped.
PEB 3456 E
Functional Description
Data Sheet 104 05.2001
After d ete cti ng an H DLC fl ag , by te sa mpling is stopped, the rece ive statu s by te m ar kin g
a BOM fram e is stored in the receive FIFO and a ’Receive Message End ’ interrupt vec tor
is generated.
Byte sampling may be stopped by deactivating the BOM receiver (RCR1.BRAC). In this
case the receive status byte marking a BOM frame is added, a ’Receive Message End’
interrupt vector is generated and HDLC mode is entered.
BOM Filte r Mod e
In BOM filter mode the received BOM data is validated and then filtered. If same valid
BOM pattern is receiv ed for 7 out of 1 0 pat terns, then BO M data is written to the receive
FIFO along with the status byte indicating that filtered BOM data was received.
Filtered BOM mode will be exited if one of the following conditions occurs:
• 4 valid BOM patterns are consecutively received but none of these equals the BOM
data received earlier.
• 4 times idle pattern is received.
• A HDLC flag is received.
4.8.4 Sa- bit Acce ss
The TE3-CHATT supports the Sa-bit signaling of time-slot 0 of the T1/E1 signals in
several ways. The access via registers RSAW and XSAW, capable of storing the
information for a complete multiframe, and the most effective one is the access via the
receive/ transmit F IFOS of the integrated signalin g cont roller.
The extended Sa-bit access gives the opportunity to transmit/receive a transparent bit
stream as well as HDLC frames where the signaling controller automatically processes
the HDLC protocol.
Data written to the transmit FIFO will subsequently be transmitted in the selected Sa-bit
positions. Any combination of Sa-bits can be selected. After the data have been
completely sent out an “all ones” or flags will be transmitted. The continuous
transmission of a transparent bit stream, which is stored in the XFF.XFIFO, can be
enabled.
The access to and from the FIFOs is supported by status and interrupts.
Sa-Bit Detection according to ETS 300233
Four consecutive received Sa-bits are checked on the by ETS 300233 defined Sa-bit
combinations. The TE3-CHATT can be programmed to detect any bit combination on
one Sa-bit out of Sa4 through Sa8. Enabling of specific bit combination can be done via
register RCR2.SASSM. A valid Sa-bit combination must occur three times in a row. The
correspo nding st atus in re gister RSAW4 will be set. Regis ter RSAW4 is from t ype “Clear
on Read”. With any change of state of the selected Sa-bit combinations a ’SSM Data
Valid’ interrupt vector will be generated.
PEB 3456 E
Functional Description
Data Sheet 105 05.2001
During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the Sa-bit
combin ations can be do ne eit her sy nchron ous o r asy nchron ous to the sub multi frame. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch . state. I n asynchro nous detection mode upd ating is indepen dent to the mu ltiframe
synchronous state.
Sa-bit Error Indication Counters
The Sa-bit error indication counter CRC1 (16 bits) counts either the received bit
sequence 0001B or 0011B or user programmable values in every submultiframe on a
select able Sa-bit. In the primary rate access digital section CRC errors are reporte d from
the TE via Sa6. Incrementing is only possible in the multiframe synchronous state.
The Sa-bit error indication counter CRC2 (16 bits) counts either the received bit
sequence 0010B or 0011B or user programmable values in every submultiframe on a
selectable Sa-bit. In the primary rate access digital section CRC errors detected at T-
reference points are reported via Sa6. Incrementing is only possible in the multiframe
synchronous state.
4.8.5 Signalling Controller FIFO Operations
Access to the FIFO’s of the signalling controllers is handled via registers RFF and XFF.
FIFO stat us a nd c omm an ds are ex ch anged usi ng th e port stat us registers PSR and the
handshake register HND. Additional facility data link interrupt vectors inform system
software about protocol and FIFO status.
Receive FIFO
In receive d ire cti on there are d ifferent i nterrupt indicat ion s as sociated w i th the re ception
of data:
• A ’Re ceive Pool Fu ll’ (RPF) in terrupt v ector i s indica ting th at a data block can b e read
from the rec ei ve F IFO an d the rec eiv ed message is not yet comp lete. It is g ene rate d,
when the amount of data bytes has reached the programmed threshold.
• A ’Re ceive Message End’ (RME) in terrupt vector is indicating that the recep tion of one
message is completed. After this interrupt system software has to read the PSR
register in order to get the number of bytes stored in the receive FIFO. This number
include s the status byte whic h is written into the recei ve FIFO as the last byte afte r the
received frame. The status byte includes information about the CRC result, valid
frame indication, abort sequence or data overflow. The format of the status byte is
shown in the tabl e belo w :
7654 0
SMODE(1:0) BRFO STAT(4:0)
PEB 3456 E
Functional Description
Data Sheet 106 05.2001
SMODE Receiver S tatus Mode
This bit indicates the type of data received.
10BHDLC data
01BBOM data
BRFO BOM Receive FIFO Overflow
0 No overflow
1 Receive FIFO overflow
STAT Receive FIFO Status
This bit field reports the status of the data stored in the receive FIFO.
After the rec eiv ed data has be en re ad from the FIFO, the rec eiv e FI FO can be re le ase d
by the CPU by issuing a ’Receive Message Complete’ (HND.RMC) command. The CPU
has to process a ’Receive Pool Full’ interrupt vector and issue the ’Receive Message
Complete’ command before the second page of the FIFO becomes full. Otherwise a
’Receive Data Overflow’ condition will occur. This time is dependent on the threshold
programmed (smaller t hreshold results in shorter time).
HDLC mode BOM MODE
00000BValid HDLC Frame BOM Filtered data declared
00001BR ece ive D ata Over flow BOM data availab l e
00010BReceive Abort BOM End
00011BN ot Octet BOM filter ed dat a unde clar ed
00100BCRC Error BOM header error (ISF, incorrect
synchroni za tion for mat )
00101BChannel Off
PEB 3456 E
Functional Description
Data Sheet 107 05.2001
•
Figure 4-12 Interrupt Driven Reception Sequence Example
Transmit FIFO
In the transmit direction after checking the transmit FIFO status by polling the transmit
FIFO write enable bit (PSR.XFW) o r after a ’Transmit Pool Ready’ (XPR) interrupt vect or,
up to 32 bytes may be written to the transmit FIFO (bit field XFF.XFIFO) by the CPU.
Transmi ssion of a f rame can be sta rted by issu ing a ’Trans mit Transpare nt Frame’ (XTF)
or ’Transmit HDLC Frame’ (XHF) command via register HND. If the transmit command
does not include a ’Transmit Message End’ indication (HND.XME), the signalling
controller will repeatedly request for the next data block by means of a XPR interrupt
vector as soon as the transmit FIFO becomes free. This process will be repeated until
the local CPU writes the last bytes to the transmit FIFO. The end of message is then
indicated per HND.XME command, after which frame transmission is finished correctly
by appending the CRC and closing flag sequence. Consecutive frames may share a flag
(enabled via bit XCR1.SF) or may be transmitted as back-to-back frames, if service of
transmit FIFO is quick enough. In case that no more data is availab le in the transmit FIFO
prior to the arrival of HND.XME, th e transmission of the frame is terminated with a n abort
sequenc e and the C PU is notifi ed via a ’Tr ansmit Data Underrun’ interrupt v ector (XDU).
The frame may also be aborted per software by setting the XAB bit in the handshake
register HND.
RD
32 bytes RD
32 bytes RD
15 bytes
RD
RBC RD
status
RPF RPF RME
RMC RMC
32 bytes 32 byt e s 15 byte s
RMC
Receive frame (79 bytes)
FDL channel
Local Bus
Interface
PEB 3456 E
Functional Description
Data Sheet 108 05.2001
•
Figure 4-13 Interrupt Driven Transmit Sequence Example
Note: Transmit FIFO is 16 bit wide. In the given example writing 32 bytes requires 16
write accesses. Writing 15 byte requires 8 accesses.
4.9 M12 Multiplexer/Demultiplexer and DS2 framer
The M12 multiplexer and the DS2 framer can be operated in two modes:
• M12 multiplex format according to ANSI T1.107
• ITU-T G. 747 format
4.9.1 M12 multiplex format
The framing structure of the M12 signal is shown in Table 4-11. A DS2 multiframe
consists of four subframes. Each subf rame combines 6 blocks with 49 bits each. The first
bit of each block contains an overhead (OH) bit and 48 information bits. The 48
information bits are divided into four time slots of 12 bits each. The first time slot is
WR
15 bytes
WR
32 bytes
XTF
32 byt es32 bytes 15 bytes
XTF
Transmit fra me (79 bytes)
FDL channel
Local Bus
Interface
WR
32 bytes XTF+XMEXPR XPR XPR ALLS
PEB 3456 E
Functional Description
Data Sheet 109 05.2001
assigned to the 1st tributary DS1 signal, the second time slot is assigned to the 2nd
tributary DS1 signal and so forth.
Table 4-11 M12 multiplex format
F0, F1
F0 and F1 form the frame alignment pattern. Eac h DS2 frame consists of eight F-bits, two per
subframe in block 3 and 6. F0 and F1 form the pattern ’01’. This pattern is repeated in every
subframe.
XThis bit is the forth bit of the multiframe alignment signal and can be set to either ’0’ or ’1’. It is
accessible via an internal register.
M0, M1,MX
M0 and M1 and M X form t he m ultiframe alignment signal. E ach subf rame consist s of four M -bits
and they are located in bit 0 of each subframe. The multiframe alignment signal is ’011-’.
C11..C43
The C-bits control the bit stuffing procedure of the multipexed DS1 signals.
[48]
These bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12
bit and each time slot is assigned to one of four participating DS1 signals.
4.9.1.1 Synchronization Procedure
The integrated DS2 framer searches for the frame alignment pattern ’01’ and the
multiframe alignment pattern in each of the seven DS2 frames which are contained in a
DS3 signal. Frame alignment is declared, when the DS2 framer has found the basic
frame alignment pattern (F-bit) and the multiframe alignment pattern (M-bit).
Loss of fram e is declared, whe n 2 out of 4 or 3 out of 5 incorrect F-b its are found or whe n
one or more incorrect M-bits are found in 3 out of 4 subframes.
Subframe Block 1 through 6 of a subframe
123456
DS2-
Multiframe
10
M[48] C11 [48] F0[48] C12 [48] C13 [48] F1[48]
21
M[48] C21 [48] F0[48] C22 [48] C23 [48] F1[48]
31
M[48] C31 [48] F0[48] C32 [48] C33 [48] F1[48]
4X[48]C
41 [48] F0[48] C42 [48] C43 [48] F1[48]
PEB 3456 E
Functional Description
Data Sheet 110 05.2001
4.9.1.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts four DS1 signals out of each DS2 signal. If two out of three
bits of Ci1, Ci2, Ci3 are set to ’1’ t he first inform ation bit in the i th subf rame and the 6th bl ock
which is assigned to the ith DS1 sig nal is discarded.
The demultiplexer performs inversion of the 2nd and 4th tributary DS1 signal.
Multiplexer
The multiplexer combines four DS1 signals to form a DS2 signal. Stuffing bits are
inserted and th e Ci1-, Ci2-, Ci3-bits, which are assi gned t o the i th DS1 s ignal, are se t to ’1’
in case that not enough data is available.
The 2nd and 4th DS1 signal are automatically inverted in transmit direction.
4.9.1.3 Loopback Control
Detection
Loopback requests encoded in the C-bits of the DS2 signal are flagged when they are
repeated for at least five DS2 multiframes. Loops must be initiated by an external
microprocessor.
Generation
A loopback request, whi ch is transmitte d in lieu of the C-bi ts, can be place d in each DS2
signal.
4.9.1.4 Alarm Indication Signal
Detection
AIS is declared, when the AIS condition (the received DS2 data stream contains an all
‘1’ signal with less then 3/9 zeros within 3156 bits while the DS2 framer is out of frame)
is present within a time interval that is determined by register D2RAP.
Generation
The ala rm indic ation sign al is an all ’1’ un framed signal and will be transmi tted if ena bled.
PEB 3456 E
Functional Description
Data Sheet 111 05.2001
4.9.2 ITU-T G.747 format
The multiplexing frame structure is shown in Table 4-12.
Table 4-12 ITU-T G.747 format
4.9.2.1 Synchronization Procedure
The integrated framer searches for the frame alignment pattern ’111010000’ in each of
the seven frames which are contained in a DS3 signal. Frame alignment is declared,
when the framer has found three consecutive correct frame alignment signals. If the
frame a lignm ent s ignal has been rece ive d in correc tly i n one of the follo wing frame s af ter
the receiver found the first correct frame alignment signal a new search is started.
Loss of frame is declared, when four consecutive frame alignment signals have been
received incorr ectly .
4.9.2.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts three E1 signals from each 6.312 MHz signal. If two out of
three bits of Cj1, Cj2, Cj3 are set to ’1’ the available justification bit of the jth E1 signal is
discarded.
Set Content Bit
ITU-T
G.747
Frame
I Frame Alignment Signal 111010000 1 to 9
Bits from tributaries 10 to 168
II Alarm indication to the remote multiplex
equipment 1
Parity Bit 2
Reserved 3
Bits from tributaries 4 to 168
III Justification control bits Cj1 1 to 3
Bits from tributaries 4 to 168
IV Justification control bits Cj2 1 to 3
Bits from tributaries 4 to 168
V Justification control bits Cj3 1 to 3
Bits from tributaries available for justification 4 to 6
Bits from tributaries 7 to 168
PEB 3456 E
Functional Description
Data Sheet 112 05.2001
Multiplexer
The multiplexer combines three E1 signals to form a DS2 signal. Stuffing bits are
inserted and the Cj1-, Cj2-, Cj3-bits, which are assigned to the jth E1 signal, are set to ’1’
in case that not enough data is available.
4.9.2.3 Parity Bit
Detection
The receiver optionally calculates the parity of all tributary bits and compares this value
with the received parity bit. Differences are counted in the parity error counter.
Generation
The parity bit is automatically calculated according to ITU-T G.747 or programmable to
a fixed value under microprocessor control.
4.9.2.4 Remote Alarm Indication
Detection
Remot e a larm i s reported w h en bit 1 of set II chan ges a nd w hen th e c ha nge p ersi st s for
at least three multiframes.
Generation
Remot e alarm is trans mitted in bit 2 of “set II” and can be in serted un der micropro cessor
control.
4.9.2.5 Alarm Indication Signal
Detection
AIS is declared, when the AIS condition (the received DS2 data stream contains an all
‘1’ signal with less then 5/9 zeros within two consecutive multiframes while the DS2
framer is out of frame) is present within a time interval that is determined by register
D2RAP.
Generation
The ala rm indic ation sign al is an all ’1’ un framed signal and will be transmi tted if ena bled.
4.10 M23 multiplexer and DS3 framer
The M23 multiplexer and the DS3 framer can be operated in three modes:
PEB 3456 E
Functional Description
Data Sheet 113 05.2001
• M23 multiplex format
• C-bit parity format with modified M23 multiplex operation
• C-bit parity format with non-M23 multiplex operation (Full payload rate format)
4.10.1 M23 multiplex format
The framing structure of the M23 multiplex signal is shown in Table 4-13. Each DS3
multiframe consists of 7 subframes and each subframe of eight blocks. One block
consists of 85 bits, where the first bit is the overhead (OH) bit and the remaining 84 bits
are the information bits. The 84 information bits are divided into seven time slots of 12
bits each. The first time slot is assigned to the 1st tributary DS2 signal, the second time
slot is assigned to the 2nd tributary DS2 signal and so forth.
Table 4-13 M23 multiplex format
F0, F1
F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per
subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern ’1001’. This pattern is repeated in
every subframe.
M0, M
M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first
block in subframe 5,6 and 7. The multiframe alignment signal is ’010’.
C11..C73
The C-bits control the bit stuffing procedure of the multipexed DS2 signals.
PThe P-bits co ntain parity inform ation and are calculated as even parit y on all information bits of
the previous DS3 frame. Both P-bits are identical.
XThe X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be
identical and may not change more than once every second.
Sub-
frame Block 1 through 8 of a subframe
12345678
DS3-
Multi-
frame
1X[84]F
1[84] C11 [84] F0[84] C12 [84] F0[84] C13 [84] F1[84]
2X[84]F
1[84] C21 [84] F0[84] C22 [84] F0[84] C23 [84] F1[84]
3P[84]F
1[84] C31 [84] F0[84] C32 [84] F0[84] C33 [84] F1[84]
4P[84]F
1[84] C41 [84] F0[84] C42 [84] F0[84] C43 [84] F1[84]
5M
0[84] F1[84] C51 [84] F0[84] C52 [84] F0[84] C53 [84] F1[84]
6M
1[84] F1[84] C61 [84] F0[84] C62 [84] F0[84] C63 [84] F1[84]
7M
0[84] F1[84] C71 [84] F0[84] C72 [84] F0[84] C73 [84] F1[84]
PEB 3456 E
Functional Description
Data Sheet 114 05.2001
[84]
These bits represent a data block, which consists of 84 bits.
[84] consists of seven time slots with 12 bits each and they are assigned to one of the seven
participating DS2 signals.
4.10.1.1 Synchronization Procedure
The integrated DS3 framer searches for the frame alignment pattern ’1001’ and when
found for the multiframe alignment pattern in each of the seven DS3 subframes. When
the multiframe alignment pattern is found in three consecutive DS3 frames while frame
alignm ent is still valid frame alignm ent is de cl ared. Th e P-bits an d the X-b its are ignore d
during sy nchronization.
Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or
when one or more incorrect M-bits are found in 3 out of 4 subframes.
4.10.1.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. If two or
three bit s out of Ci1, Ci2, Ci3 are set to ’1 ’ the firs t bit follo wing the F1 bit in th e ith subframe
which is assigned to the ith DS2 sig nal is discarded.
Multiplexer
The multiplexer combines seven DS2 signals to form a DS3 signal. If not sufficient data
is available for a DS2 signal, it automatically inserts a stuffing bit and sets the bits Ci1,
Ci2, Ci3 assigned to the ith DS2 signal to ’1’.
4.10.1.3 X-bit
The TE3-CHATT provides access to the X-bit of each tributary via an internal registers.
Data written to the X-bit register is copied to an internal shadow register which is then
locked for one second after each write access.
4.10.1.4 Alarm Indication Signal, Idle Signal
Detection
Alarm indication signal or Idle signal is declared, when the selected signal format was
received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one
multiframe. The alarm indication signal can be selected as:
• Unframed all ’1’s
PEB 3456 E
Functional Description
Data Sheet 115 05.2001
• Framed ’10 10’ sequ enc e, s tart ing with a bi nary ’1 ’ aft er ea ch OH -b it. C- b its are set to
‘0’. X-bit can be checked as ‘1’ or X-bit check can be disabled.
The idle signal is a
• Framed ’1100’ sequence, starting with a binary ’11’ after each OH-bit. C-bits are set
to ‘0’ in M-subframe 3. X-bit can be checked as ‘1’ or X-bit check can be disabled.
Generation
The alarm indication signal or idle signal will be generated according to the selected
signal format. X-bit needs to be set seperately to ‘1’.
4.10.1.5 Loss of Signal
Detection
Loss of signal is declared, when the incoming data stream contains more than 1022
consecutive ’0’s.
Recovery
Loss of signal is removed, when two or more ones are detected in the incoming data
stream.
4.10.1.6 Performance Monitor
The following conditions are counted:
• Line code violations
• Excessive zeroes
• P-bit errors, CP-bit errors
• Framing bit errors
• Multiframe bit errors
• Far end block errors
PEB 3456 E
Functional Description
Data Sheet 116 05.2001
4.10.2 C-bit parity format
The framin g structure of the C-bi t parit y form at is sh own in Table 4-13. The assignment
of the i nforma tio n bits [ 84] is iden tical to th e M23 mult iplex forma t, but the fu nction of th e
C-bits is redefined for path maintenance and data link channels.
Table 4-14 C-bit parity format
F0, F1
F0 and F1 form the frame alignment pattern. Each DS3 frame consists of 28 F-bits, four per
subframe in block 2, 4, 6 and 8. F0 and F1 form the pattern ’1001’. This pattern is repeated in
every subframe.
M0, M
M0 and M1 form the multiframe alignment signal. The M-bit is contained in the OH-bit of the first
block in subframe 5,6 and 7. The multiframe alignment signal is ’010’.
NrReserved. Set to ’1’ in transmit direction.
AIC
Application Identification Channel.
DLt
The terminal-to-terminal path maintenance data link uses the HDLC protocol. Access to the DLt
bits is possible via the DS3 transmit and receive FIFO.
DLReserved. Set to ’1’ in transmit direction.
FEAC
The alarm or status inform ation of a far end terminal is sent back over t he far end and control
channel. This bit also contains DS3 or DS1 line loopback requests. Messages are sent in bit
oriented mode. Message codes can be accessed via an internal register.
FEBE
The far end block err or bits indicate a CP-bit parity e rror or a framing error. They are used to
Sub-
frame Block 1 through 8 of a subframe
12345678
DS3-
Multi-
frame
1X[84]F
1[84] AIC [84] F0[84] Nr[84] F0[84]
FEAC
[84] F1[84]
2X[84]F
1[84] DL [84] F0[84] DL [84] F0[84] DL [84] F1[84]
3P[84]F
1[84] CP [84] F0[84] CP [84] F0[84] CP [84] F1[84]
4P[84]F
1[84]
FEBE
[84] F0[84]
FEBE
[84] F0[84]
FEBE
[84] F1[84]
5M
0[84] F1[84] DLt[84] F0[84] DLt[84] F0[84] DLt[84] F1[84]
6M
1[84] F1[84] DL [84] F0[84] DL [84] F0[84] DL [84] F1[84]
7M
0[84] F1[84] DL [84] F0[84] DL [84] F0[84] DL [84] F1[84]
PEB 3456 E
Functional Description
Data Sheet 117 05.2001
monitor the performance of a DS3 signal. Upon detection of either error in the incoming data
stream the FEBE -bits are set automatically to ’000’ in the outgoing direction. Received far end
block errors are counted.
CPThe CP-bits are used to carry path parity information and are set to the same value as the P-bits.
In receive direction the CP-bits are checked against the calculated parity and differences are
counted.
PThe P-bits contain parity information and are automatically calculated as even parity on all
information bits of the previous DS3 frame.
XThe X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be
identical and may not change more than once every second. Access to the X-bits is possible via
a register.
[84]
These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with
12 bits each and they are assigned to one of the seven participating DS2 signals.
4.10.2.1 Synchronization Procedure
The integrated DS3 framer searches for the frame alignment pattern ’1001’ and when
found for the multiframe alignment pattern in each of the seven DS3 subframes. Frame
alignment is declared when the multiframe alignment pattern is found in three
consecutive DS3 frames. The P-bits and the X-bits are ignored during synchronization.
Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or
when one or more incorrect M-bits are found in 3 out of 4 subframes.
4.10.2.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. Since the
DS3 signal is always stuffed the stuffing bit assigned to each DS2 signal is discarded.
Multiplexer
The multiplexer combines seven DS2 signals to form a DS3 signal and automatically
inserts a stuffing bit for each DS2 signal.
4.10.2.3 X-bit
The TE3-CHATT provides access to the X-bits via internal registers.
PEB 3456 E
Functional Description
Data Sheet 118 05.2001
4.10.2.4 Far End Alarm and Control Channel
The far end alarm and control channel is accessible via the signalling controller in BOM
mode.
4.10.2.5 Path Maintenance Data Link Channel
The path maintenance data link channel is accessible via the signalling controller in
HDLC mode.
4.10.2.6 Loopback Control
Detection
Loopback requests are encoded in the messages of the far end alarm and control
channel. The microprocessor has access to the messages as described in
Chapter 4.10.2.4.
Generation
A loopback request can be initiated via the far end alarm and control channel.
4.10.2.7 Alarm Indication Signal, Idle Signal
Detection
Alarm indication signal or Idle signal is declared, when the selected signal format was
received with less than 8/15 bit errors (selectable via bit D3RAP.AIS) for at least one
multiframe. The alarm indication signal can be selected as:
• Unframed all ’1’s
• Framed ’10 10’ sequ enc e, s tart ing with a bi nary ’1 ’ aft er ea ch OH -b it. C- b its are set to
‘0’. X-bit can be checked as ‘1’ or X-bit check can be disabled.
The idle signal is a
• Framed ’1100’ sequence, starting with a binary ’11’ after each OH-bit. C-bits are set
to ‘0’ in M-subframe 3. X-bit can be checked as ‘1’ or X-bit check can be disabled.
Generation
The alarm indication signal or idle signal will be generated according to the selected
signal format. X-bit needs to be set seperately to ‘1’.
PEB 3456 E
Functional Description
Data Sheet 119 05.2001
4.10.2.8 Loss of Signal
Detection
Loss of signal is declared, when the incoming data stream contains more than 1022
consecutive ’0’s.
Recovery
Loss of signal is removed, when two or more ones are detected in the incoming data
stream.
4.10.2.9 Performance Monitor
The following conditions are counted:
• Line code violations
• Excessive zeroes
• P-bit errors, CP-bit errors
• Framing bit errors
• Multiframe bit errors
• Far end block errors
PEB 3456 E
Functional Description
Data Sheet 120 05.2001
4.10.3 Full Payload Rate Format
In full pay load rate form at the DS3 multi frame struc ture can be s elected acco rding to the
M13 multiplex structure or the C-bit parity structure. In either case the data blocks [84]
carry one continuous data stream which is provided via the tributary interface one.
Multiplexing/Demultiplexing of the data block [84] does NOT apply.
4.11 Test Unit
The test uni t of the TE3-CHATT inc orpo rate s a test pa ttern generato r and a test patte rn
synchronizer which can be attached to different test points as shown in Figure 4-14.
Controlled by a small set of registers it can generate and synchronize to polynomial
pseudorandom test patterns or repetitive fixed length test patterns.
Test patterns can be generated in the following modes:
•Framed DS3
• Unframed DS2
•Framed DS2
• Unframed DS1/E1
•
Figure 4-14 Test Unit Access Points
In pseudorandom test mode the receiver tries to achieve synchronization to a test
pattern which satisfies the programmed receiver polynomial. In fixed pattern mode it
synchronizes to a repetitive pattern with a programmable length. An all ’1’ pattern or an
all ’0’ pattern, which satisfies this condition, is flagged. Measurement intervals as well as
receiver synchronization can be controlled by the user. When a test is finished an
interrupt is generated and the bit count and the bit error count are readable.
DS3
Framer
DS2 Framer
DS2 Framer
DS2 Framer
M23
(De)multi-
plexer
M12
M12
Test Unit
Test
Mode
Select
Test Port
Select Test Port
Select
06 06 Test Port
Select
027
To T1/E1 Framer
PEB 3456 E
Functional Description
Data Sheet 121 05.2001
•
Figure 4-15 Pattern Generator
Bit Error Insertion
The test unit provides the optional capability to insert bit errors in the range of 10-7 (1
error in 10.000.000 bits) up to 10-1 bit errors (1 error in 10 bits).
4.12 Mailbox
The TE3-CHATT contains a mailbox to allow communication between two intelligent
peripherals connected to the P CI bus and the local microprocessor bus. The mailbo x is
organ ized in two pages of eight reg isters. The first p age is used to stor e information from
the PCI si de and to read th e informati on from the local microproces sor side. Th e second
page is used for the opposite direction, from the local microprocessor side to the PCI
side. Each page consists of one status register and seven data registers.
The mailbox provides a ‘doorbell’ capability. In this case an interrupt vector can be
generated to inform the addressed intelligent peripheral that new information has been
stored in the mailbox. This interrupt vector will be generated on write accesses to the
status register of the selected page.
As an example, consider when the PCI host system wants to transfer data to an
intelli gen t pe ripheral. Fi rst it l oads data in to the mai lbo x d ata regi ste r s MBP2 E1 th roug h
MBP2E7, and then writes a status information to the mailbox status register MBP2E0.
This last action causes an interrupt vector to be written to the interrupt FIFO which is
connec ted to the l ocal bus . The pres ence of an in terrupt vec tor results in asserti on of pin
LINT. The intelligent peripheral recognizes the interrupt pin asserted and reads the
interrupt vector out of the interrupt FIFO (which results in deassertion of pin LINT), and
then reads data from the mailbox data registers.
1N-2XX-10N-1
+
N Pattern length
X Feedback Tap
+
Bit error
insertion
Feedback in
Pseudorandon pattern
mode only
PEB 3456 E
Functional Description
Data Sheet 122 05.2001
•
Figure 4-16 Mailbox Structure
Alternately, cons ider whe n an intell igent pe riphera l connec ted to the loc al bus want s to
transfer data to the PCI host system. First it loads data into the mailbox data registers
MBE2P1 through MBE2P7 and then it writes status information to the mailbox status
register MBE2P0. This causes a system interrupt vector to be written to the PCI host
system, indicating that valid data is contained in the mailbox data registers.
This in terrupt vector wil l be wri tten to the in terrupt queue specifie d in CONF1. SYSQ and
together with this the pin INTA will be asserted. The processor sees the interrupt pin
asserted, reads the register GISTA in order to determine the interrupt queue, and then
writes a ‘1’ to the interrupt status acknowledge register GIACK to clear the interrupt.
Next, it reads the interrupt vector which contains a copy of the mailbox status register
and then reads the mailbox data registers.
4.13 Interrupt Controller
Since the TE3-CHATT is divided into the basic functions mailbox, layer one functions
(T1/E1 framer, facility data link, M13 multiplexer and DS2/DS3 framer) and layer two
protocol functions (HDLC, PPP, TMA), the same partitioning is used for the interrupt
handling.
All layer two interrupts (channel, port, system and command interrupts) are handled via
an internal interrupt controller which forwards those interrupts to external interrupt
queues. This interrupt controller is connected to the PCI interrupt pin INTA.
Mailbox registers
PCI --> Local Bus
Interru pt Cont roll er
Local Bus
Interrupt C ontr olle r
PCI Side MBE2P1..MBE2P7
MBP2E0
MBE2P0
PCI Interface Local Bus Interface
MBP2E1..MBP2E7
Mailbox registers
Local Bus --> PCI
Configuration Bus I
Configuration Bus II
Interrupt Vector
Interrupt Vector
LINT
INTA
read
only
read
only
PEB 3456 E
Functional Description
Data Sheet 123 05.2001
Mailbox interrupts and layer one interrupts are handled via an internal interrupt FIFO
which is connected to the local bus interrupt pin LINT (normal operation). Additionally th e
interrupts stored in the internal interrupt FIFO can be notified via the PCI interrupt pin
INTA.
The TE3- CHATT also pro vides the capabil ity to brid ge the loc al bus interrup t LINT to the
PCI bus.
4.13.1 Layer Two interrupts
All channel interrupts, port interru pts and syst em interrupts are written in form of interrupt
vectors to interrupt queues.
Each in terrupt vec tor has a n interrup t source. An int errupt sou rce is e ither a chan nel, the
port handler or certain device functions (system interrupts). Afte r reset no interrupt vector
is generated since port and system interrupts are masked and channels are in their idle
state.
Each interrupt source forwa rds its interrupt vector to the interrupt controller, together with
the information in which interrupt queue the vector should be forwarded. The interrupt
controller moves the interrupt vector to the selected interrupt queue. Channel interrupts
can optio na lly be fo rw arde d to a dedi ca ted high prio rity int errupt queue (i nte rrupt queue
seven). A programmable interrupt queue high priority mask determines channel
interrupts, which shall be forwarded into the high priority interrupt queue instead of
queueing them in the selected interrupt queue. This function is available for each
interrupt queue and allows to queue important interrupt conditions in the high priority
queue.
PEB 3456 E
Functional Description
Data Sheet 124 05.2001
•
Figure 4-17 Layer Two Interrupts (Channel, command, port and system
interrupts
As soon as the interrupt controller has written an interrupt vector to one of the nine
interrupt queues the PCI interrupt pin INTA is asserted. The global interrupt status
register in dicat es in wh ich inte rrupt queu e the inter rupt vector can be fou nd. Each of the
PCI
interface
System memory
System
interrupts
Channel,
Command
interrupts
Interrupt
controller
Interrupt queue
Interrupt status:
GISTA, GMASK
Interrupt queue setup:
IQIA, IQBA, IQL, IQMASK
00000000
H
FFFFFFFF
H
IQBA
IV
PCI bus
Interrupt bus
Port
interrupts
Int. vector setup:
CONF1, CONF2
1256
Int. vector setup:
CSPEC_IVMASK,
CSPEC_BUFFER
Int. vector setup:
PM R, CONF2
1
2
3
4
Microprocessor
1. Interrupt source forwards interrupt vector to
interrupt controller.
2. Interrupt controller moves interrupt vector to
interrupt queue.
3. Interrupt controller asserts INTA (if enabled).
4. Microprocessor reads status register GISTA.
5. Microprocessor reads interrupt queue.
INTA
5
from l ayer one
interrupt FIFO
LINT
PEB 3456 E
Functional Description
Data Sheet 125 05.2001
nine in terrupt que ues can be ma sked . In thi s ca se the interru pt pin INTA is not asserted,
but the interrupt vector is still written into the assigned interrupt queue.
An interru pt queues is a reserved memory locations in system memory. The TE3-CHATT
supports up to eight interrupt queues which are organized in form of ring buffers with a
programmable start address and a programmable size per interrupt queue. Additionally
there is on e fixed size d command in terrupt queue w here comman d interrupts are s tored.
The size of this queue is two times 256 DWORDs (Figure 4-18).
•
Figure 4-18 Interrupt Queue Structure in System Memory
4.13.1.1 General Interrupt Vector Structure
Each interrupt vector is 32 bit wide and contains several subfields, which indicate the
interrupt group an d de pend on the interrupt gro up the i nte rrupt informati on. Bi t 31 of th e
interrupt vector is generally set to ’1’ by the TE3-CHATT and allows the system CPU to
clear the bit in order to mark processed interrupts.
Table 4-15 Interrupt Vector Structure
31 30 29 28 27 26 24 23 16
1 TYPE(1:0) STYPE(1:0) QUEUE(2:0) INT(23:0)
15 0
INT(23:0)
ring buff er
Channel 255: Transmit Command IV
Channel 0: Trans mi t Command IV
Channel 255: Rec eiv e Comm and IV
Channel 0: Receive Command IVInterrupt Vector 1
Interrupt Vector 2
Interrupt Vector 3
Interrupt Vector IQL*16
Channel, Port and System
Interrupt Queue Command Int e r r up t Queue
IQBA
Note: IV = Interrupt Vector
IQBA+4
H
IQBA
IQBA+4
H
Channel 1: Receive Command IV
PEB 3456 E
Functional Description
Data Sheet 126 05.2001
TYPE Interrupt type
The interrupt vectors are divided into four basic groups, where TYPE
determines the interrupt group. A further classification of interrupts is
done with the subtype indication.
00BCommand interrupts
01BChannel interrupts
10BPort interrupts
11BSystem interrupts
STYPE Interrupt subtype
A specific interrupt type is divided into several subtypes. In general
STYPE(1) indicates the data path (transmit, receive) generating the
interrupt.
QUEUE Interrupt queue
The interrupt v ec tors are w rit ten into 9 ex tern al interrupt qu eue s locate d
in the shared memory. Corresponding to these 9 queues are 9 interrupt
queue start addresses and 8 interrupt queue length registers, since the
interrupt queue 8 has a fixed length of 2 x 256).
INT Interrupt Information
INT itself contains the interrupt information. The meaning of INT is
dependent on TYPE and STYPE indication.
PEB 3456 E
Functional Description
Data Sheet 127 05.2001
4.13.1.2 System Interrupts
•
MB Mailbox
The ’Mailbox’ interrupt vector is generated, in case that the local
microp roces sor has wri tten dat a to the ma ilbox status registe r MBE2P0.
The bit field IN FO conta ins a copy of MBE2P0 .
RBAF Receive Buffer Access Failed
The ’Receive Buffer Access Failed’ interrupt vector is generated, when
the protocol machine discarded packets due to permanent
inaccessibility of the receive buffer. This interrupt is issued as soon as
the programmable threshold stored in register RBAFT is reached. The
actual value of discarded packets is stored in register RBAFC.
RBEW Receive Buffer Queue Early Warning
The ’Re ceive Buffer Qu eue Early Warn ing’ interru pt vector is generated,
when the receive buffer data threshold has been exceeded
(RBTH.RBTH). This interrupt can be masked via bit CONF1.RBIM.
RAEW Receive Buffer Action Queue Early Warning
The ’Receive Buffer Action Queue Early Warning’ interrupt vector is
generated, when the receive data action queue threshold
(RBTH.RBAQTH) has been exceeded. The receive buffer action queue
stores all requests of the receive buffer to forward data packets to
system memory. This interrupt vector can be masked via bit
CONF1.RBIM.
PB PCI Access Error
The ’PCI Access Error’ interrupt vector is generated, when system
software tries to read/write internal registers with accesses that do not
enable all byte lanes, e.g. the access is not a full 32 bit access. The bit
field INFO contains the register address which was tried to access.
INFO Conta ins additi onal in terrupt in format ion data accord ing to th e bit, w hich
is set: See specific interrupt for details.
31 30 29 28 27 26 24 20 19 18 17 16
111
B00BQUEUE(2:0) 000 MB RBF RBEWRAEW PB
15 0
INFO(15:0)
PEB 3456 E
Functional Description
Data Sheet 128 05.2001
4.13.1.3 Port Interrupts
Port interrupt vectors indicate the synchronous or asynchronous state of a port.
Immediately after enabling both, the port and the port interrupts, port interrupts are
generated indicating the synchronous or asynchronous state of a port. After this initial
interrupt vector generation, further interrupts are written only when the state of a port
changes from synchronous stat e to async hronous state or vi ce versa. Port interrupts are
enabled by resetting the corresponding mask bit in register PMR.
Transmit interrupts
•
PORT Port Number
This bit field identifies the port for which the information in the interrupt
vector is valid .
SYN Synchronization achieved
Port has changed from asynchronous state to synchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
unchannelized mode there is no synchronous state.
A transmit port changes to the synchronous state, if common transmit
frame synchronization is enabled and the number of bits between two
synchronization pulses is equal to the number of frame bits of the
selected mode or is equal to a multiple of that number. The first CTFS
pulse after a port is enabled causes the transmitter to change to the
synchronous stat e.
In case the common transmit frame synchronization is disabled, i.e. the
looped timing bit or the CTFS disable bit of a port is set in PMR, the initial
asynchronous state will not be left.
ASYN Asynchronous State
The transmitter generates an ’Asynchronous State’ interrupt vector if a
port has changed from synchronous to asynchronous state. This
interrupt is available for ports configured in T1, E1 mode. In
31 30 29 28 27 26 24 17 16
110
B10BQUEUE(2:0) 000000 SYN ASYN
15 5 4 0
00000000000PORT(4:0)
PEB 3456 E
Functional Description
Data Sheet 129 05.2001
unchan nelized mode there is no async hronous s tate. In gen eral a port i s
in asynchronous state when a port is disabled.
A transm it p ort c hanges to the asyn ch ronous mo de i f the numb er of bits
between two synchronization pulses is not equal to a multiple of the
number of frame bits of the selected mode
Receive Interrupts
•
PORT Port Number
This bit field identifies the port for which the information in the interrupt
vector is valid .
SYN Synchronization achieved
Port has changed from asynchronous state to synchronous state. This
interrupt is available for ports configured in T1, E1 mode. In
unchannelized mode there is no synchronous state.
A receive port changes to the synchronous state, if the number of bits
between two synchronization pulses generated by the port related
framer i s exactl y equal to the num ber of fram e bits of the selecte d mode.
The first framer pulse after a port is enabled causes the receive port to
change to the synchronous state.
ASYN Asynchronous state
Port has changed from synchronous to asynchronous state. This
interrupt is available for ports configured in T1 or E1 mode. In
unchan nelized mode there is no async hronous s tate. In gen eral a port i s
in asynchronous state when a port is disabled.
A receive port changes to the asynchronous state if the number of bits
between two framer synchronization pulses is not equal to the number
of frame bits of the selected mode. The synchronization pulses are
generated internally by the T1/E1 framer.
31 30 29 28 27 26 24 17 16
110
B00BQUEUE(2:0) 000000 SYN ASYN
15 40
00000000000PORT(4:0)
PEB 3456 E
Functional Description
Data Sheet 130 05.2001
4.13.1.4 Channel Interrupts
Channel interrupt are divided into two subtypes:
• Receive Interrupt I and Transmit Interrupt I
• Receive Interrupt II and Transmit Interrupt II
Subtype I contains interrupts which indicate the general status of a channel. These
interrupts are not linked to a descriptor.
Subtype II contains interrupts which indicate a channel or packet status that is linked to
a descriptor. Each interrupt vector contains a descriptor ID which can be used for
tracking purposes.
Receive Interrupt I
•
ROFP Receive Buffer Overflow
The ’Re ceive Buffer Overfl ow’ interrupt v ector is generat ed, when one or
more whole frames or short frames or changes of interframe time-fill
(HLDC, PPP) or data in general (TMA) has been discarded due to the
inaccessibility of the internal receive buffer.
SF Sh ort Frame De tected
The ’Short Frame Detected’ interrupt vector is generated, when the
rece iver d etecte d a fr ame whi ch len gth ma tches the co nditio n de fined i n
CONF1.SFL.
IFFL Interframe Time-fill Flag
The ’Interframe Time-fill Flag’ interrupt vector is generated, when the
receiver detected a interframe time-fill change from FFH to 7EH.
IFID Interframe Time-fill Idle
The ’Interframe Time-fill Idle’ interrupt vector is generated, when the
receiver detected a interframe time-fill change from 7EH to FFH.
31 30 29 28 27 26 24
101
B00BQUEUE(2:0) 00000000
15 14 13 12 11 7 0
ROFP SF IFFL IFID SFD 0 0 0CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 131 05.2001
SFD Small Frames Dropped
The ’Small Frames Dropped’ interrupt vector is generated, when the
receiver discarded N small frames. The length of small frames is defined
in CON F3.MINFL and the th reshol d valu e N is defi ned in re giste r SFDT.
CHAN Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
Transmit Interrupt I
•
UR Underrun
The ’Underrun’ interrupt vector is generated, when the transmit buffer
was not able to provide data to the protocol machine transmit. If this
happens during transmission of a HDLC or PPP packet, the transmitter
will end the already started data packet with an abort sequence.
FE Frame End
The ’Frame End’ interrupt vector is generated, when one complete data
packet has been transmitted via serial side.
CHAN Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
31 30 29 28 27 26 24 16
101
B10BQUEUE(2:0) 00000000
15 14 7 0
UR FE 000000CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 132 05.2001
Receive Interrupt II
•
CHAN Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
RHI (Receive) Host Initiated Interrupt
The ’(Receive) Host Initiated’ interrupt vector will be issued, if bit RHI is
set in a receive d escriptor and processi ng of this descripto r has finishe d.
After receiving this interrupt vector, system software can release the
descriptor, e.g. put the descriptor into a free pool.
RAB Receive Abort
The ’Receive Abort’ interrupt vector is generated, when an incoming
data packet is aborted (more than 6 ‘1’ in case of HDLC or more than 15
‘1’ in case of PPP) or if the receiver got a receive abort command from
the system CPU.
FE Frame End
The ’Frame End’ interrupt Vector is generated, when one complete
frame has been received completely and has been stored in system
memory.
HRAB Hold Caused Receive Abort
The ’H old Caused Receive Ab ort’ interrupt vector is generated, when the
receiver discarded the first data packet after it has found a HOLD bit in
a receive descriptor.
RAB, HRAB Si le nt Discard
The ’Silent Discard’ interrupt vector (bit RAB and HRAB set together)
occurs, if two or more frames have been discarded by the receiver due
to co ntinuous i naccess ibility of receive des criptor. Thi s occurs, if receive
descri pto r has HOLD bi t se t and rece iv er ge ts further data pac ke ts. Th e
interrupt vector will be generated for each packet discarded.
31 30 29 28 27 26 24 23 22 21 16
101
B01BQUEUE(2:0) 00 DESID(5:0)
15 14 13 12 11 10 9 8 7 0
RHI RAB FE HRAB MFL RFOD CRC ILEN CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 133 05.2001
MFL Maximum Frame Length Exceeded
The ’Maximum Frame Length Exceeded’ interrupt vector is generated,
when the length of a received data packet exceeded the frame length
defined in CONF1.MFL.
RFOD Receive Frame Overflow DMA
The ’Receive Frame Overflow DMA’ interrupt indicates that protocol
handler was unable to transfer data to the receive buffer. As soon as
receive buffer can store data again, this interrupt is generated.
CRC CRC Error
The ’CRC Error’ interrupt vector is generated, when the internally
calculated CRC and the CRC of a received packet did not match.
ILEN Invalid Length
The ’Invalid Length’ interrupt vector is generated, when the bit length of
received frame was not divisible by 8.
Transmit Interrupt II
•
DESID Descriptor ID
This bit field is a copy of the descriptor ID of the transmit descriptor which
is currently in use. It can be used for tracking purposes.
THI (Tran smit) Ho st Ini tiat ed Inte rrupt
The ’(Transmit) Host Initiated’ interrupt vector is generated, if bit THI is
set in a transmit descriptor and processing of this desc riptor has finished.
After receiving this interrupt vector, system software can release the
descriptor, e.g. put the descriptor into a free pool.
TAB Transmit Abort
The ’Transmit Abort’ interrupt vector is generated, either when the
’Transmit Abort/Branch’ command was given and therefore one frame
could not be t ransm itted c omple tely or when NO and FE w ere set to 0 in
a transmit descriptor and previous frame was incompletely specified.
31 30 29 28 27 26 24 21 16
101
B11BQUEUE(2:0) 00 DESID(5:0)
15 14 12 7 0
THI TAB 0HTAB0000CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 134 05.2001
HTAB Hold C aus ed Transm it Abort
The ’Hold Caused Transmit Abort’ interrupt vector is generated, when
data management unit retrieved a transmit descriptor where HOLD was
set and FE equals 0. The interrupt will be generated after the data
section was transferred completely. After transmission of frame based
protocols (HDLC, PPP) protocol machine appends abort sequence due
to in complete packet.
CHAN Channel Number
This bit field identifies the channel for which the information in the
interrupt vector is valid.
PEB 3456 E
Functional Description
Data Sheet 135 05.2001
4.13.1.5 Command Interrupts
Command inte rrupts are w ritten to the c ommand inte rrupt q ueue (interru pt qu eue eight).
Transmit Interrupts
•
TCF Transmit Command Failed
The ’Transmit Command Failed’ interrupt vector is issued, if the
command ’Transmit Init’ given via register CSPEC_CMD.XCMD could
not be finished. This happens, when
•system software tried to allocate more buffer locations for a channel
than were available.
•system software specified thresholds (transmit forward threshold,
transmit refill threshold), which were greater than the specified
transmit buffer size.
Note:The sum of both thresholds must be smaller than the transmit
buffer siz e o f a pa rtic ula r ch ann el. Er rone ous pro gramm ing doe s
NOT result in the ’Transmit Command Failed’ interrupt vector.
TCC Transmit Command Complete
The ’Transmit Command Complete’ interrupt vector is issued after
successful completion of commands ’Transmit Init’ and ’Transmit Off’,
which can be issued via register CSPEC_CMD.XCMD.
CHAN Channel Number
This bit field contains the channel number of the affected channel.
31 30 27 17 16
1 0010B000000000TCFTCC
15 7 0
00000000CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 136 05.2001
Receive Interrupts
•
RCC Receive Command Complete
The ’Receive Command Complete’ interrupt vector is issued after
successful completion of commands ’Receive Init’ and ’Receive Off’,
which can be issued via register CSPEC_CMD.RCMD.
CHAN Channel Number
This bit field contains the channel number of the affected channel.
31 30 27 16
1 0000B0000000000 RCC
15 7 0
00000000CHAN(7:0)
PEB 3456 E
Functional Description
Data Sheet 137 05.2001
4.13.2 Layer One Interrupts
All layer one related interrupts, that is interrupts issued by either the T1/E1 framer, the
M13 multiplexer and DS2/DS3 framer, the facility data link or the PCI to Local Bus
mailbo x, are stored in an in tern al interru pt FIFO whi ch is l oc ated i nsi de the TE3-CHA TT
and can be read from either the local microprocessor or (for test purposes) via the chip
internal bridge from the host processor located on the PCI bus.
The T1/E1 framer, the facility data link, the M13 multiplexer and DS2/DS3 framer, and
the mailbox forward their specific interrupts to the internal interrupt FIFO. The interrupt
FIFO triggers the LINT pin which indicates that there is at least one interrupt vector
available. The interrupt FIFO then can be read from either PCI side or loc al bus side. The
interrupt vector contains a coding for the interrupt reason and a last indication when
there is no further interrupt vector stored in the internal interrupt FIFO. The interrupts of
the inte rnal layer one interru pt FIFO or the lo cal bus inte rrup t LIN T can also be reported
via pin INTA.
•
Figure 4-19 Framer, M13 an d Facility Data Link and Mailbox Interrupt Notification
EBU
Facility data
link Framer
Inter r upt FIFO
Inter rupt Contro l:
INTCTRL
Inter rupt status:
INTFIFO
IV
Local uP in ter f ace
Interrupt bu s I I
Mailbox
Int . vector setup:
MSK
In t. vector setup:
IMR
Int. vector setup:
FCONF.MID
TE3-CHATT
1
LINT
2
3
1. Interru pt sour ce forwards i nte rrupt
vector to interrupt FIFO.
2. Interrupt controller asserts LINT (if
enabled).
3. Micr oprocess or reads interru pt FIF O.
Microprocessor
M13
Test unit
Int. vector setup:
[]
optional i nterrupt
notification on INTA
PEB 3456 E
Functional Description
Data Sheet 138 05.2001
4.13.2.1 General Interrupt Vector Structure
•
LAST Last indication
LAST indicates that at least one more valid interrupt vector is stored in
the internal interrupt FIFO. This bit is generated at read access time.
0 There is at least one mo re interru pt in the internal interrup t FIFO.
1 This interrupt is the last interrupt that is stored in the internal
interr upt FIFO.
STYPE Subtype of interrupt vector
This bit is used to indicate different subtypes of interrupt vectors.
STATUS Interrupt status
The interrupt status depends on STYPE and MID. Please refer to the
detailed description of the interrupt vectors in the next chapters.
MID Module ID
The bit field identifies the interrupt source.
00BT1/E1 Framer Interrupts
01BFacility Data Link Interrupts
10BM13 Multiplexer and DS2/DS3 framer Interrupts
11BMailbox Interrupt
INFO Information
The content of this bit field contains further information about the
interrupt, e.g. the affected port.
15 14 13 7 6 5 4 0
LAST STYPE STATUS(6:0) MID(1:0) INFO(4:0)
PEB 3456 E
Functional Description
Data Sheet 139 05.2001
4.13.2.2 T1/E1 Framer Interrupts
The fr amer interrupts are divide d into type 0 an d type I inte rrupts. The distinction i s made
in bit 14 of the interrupt vector.
Interrupt Type 0
Interrupt Type I
AISS Alarm Indication Signal Status
The ‘Alarm Indication Signal Status’ interrupt vector is generated,
whene ver the T E3-CHATT detects a change in the al arm indicat ion. Th e
actual state, i.e. active/not active, is shown in FRS.AIS.
LOSS Loss of Signal S tatus
The ’Loss of Signal Status’ interrupt vector is generated, whenever the
TE3-CHATT detects a change in FRS.LOS.
RAS Remote Alarm Status
The ’Remote Alarm Status’ interrupt vector is generated, whenever the
TE3-CHATT received remote alarm status changes. The actual state,
i.e. active/not active, is shown in FRS.RRA.
ES Errored Second
The 'Errored Second' interrupt vector is generated for the first errored
second event in a time interval of one second. Errored second events
are:
1. Loss of frame alignment (this inclu des indirectly AIS or Loss of Signal)
2. CRC error received (CRC-6 or CRC-4).
SEC One Second Tick
The ’One Second Tick’ interrupt vector is generated, when the internal
one second timer has expired. The timer is derived from the incoming
receive clock of the corresponding port.
151413121110987654 0
LAST 0 AISS LOSS RAS ES SEC LLBS PRBSS 00BPORT(4:0)
1514 1110987654 0
LAST 1 00T400CRC
PDEN
/AUX FAS MFAS 00BPORT(4:0)
PEB 3456 E
Functional Description
Data Sheet 140 05.2001
LLBS Line Loopback Status
The ‘Line Loopback Status’ interrupt vector is generated, whenever the
TE3-CHATT detects a change in either the line loopback deactuation
signal or the l ine loopb ack a ctuate signa l. The actual st ate of th e sig nals
is shown in FRS.LLBDD and FRS.LLBAD.
PRBS PRBS Status
The ’PRBS Status’ interrupt vector is generated, whenever the TE3-
CHAT T synchroni zation st ate of t he PRBS receiv er chang es. The actual
state of the receiver, i.e. synchronized/not synchronized, is shown in
FRS.PRBS.
T400 400 Millis econd
This inte rrupt vec tor is generate d when the framer has f ound the do uble
framing (basic framing) and is searching for the multiframing. This
interrupt vector will be generated to indicate that no multiframing could
be found within a time window of 400 ms after basic framing has been
achieved. In multiframe synchronous state this interrupt will not be
generated.
CRC Receive CRC Error
This interrupt vector is generated, when the CRC-6 checksum of an T1
ESF mul tiframe or th e CRC-4 c hecksum of an E1 CRC-4 m ultiframe wa s
incorrect.
PDEN/AUX Pulse Density Violation Detected / Auxiliary Pattern Detected
This interrupt vector is generated, whenever the TE3-CHATT detects a
change in bit FRS.PDEN/AUX. Bit PDEN/AUX is set whenever bit
FRS.PDEN.AUX toggles.
FAS Frame Alignment Stat us
The ’Frame Alignment Status’ interrupt vector is generated, whenever
the TE3-CHATT detects a change in frame alignment. The actual state,
i.e. aligne/not aligned, is shown in bit FRS.LFA.
MFAS Multiframe Alignment Status
The ’Multiframe Alignment Status’ interrupt vector is generated,
whenever the TE3-CHATT detects a change in multiframe alignment.
The actual state, i.e. aligned/not aligned, is shown in bit FRS.LMFA.
PORT Port Number
0..27 The port number the interrupt vector is associated with.
PEB 3456 E
Functional Description
Data Sheet 141 05.2001
4.13.2.3 Facility Data Link Interrupts
Receive Interrupts
•
RSA Receive Sa Data Valid
Sa data in RSAW1 - RSAW3 is valid.
SSM SSM Data Valid
This bit is set, when a new synchronization status message has been
received. The synchronization status message is stored in register
RSAW4.
RPF R eceive Pool Full
This bit is set, when 32 bytes of a frame have been received and are
stored in the receive FIFO. The frame is not yet completely received.
RME Receive Message E nd
This bi t is se t, whe n one co mplet e m essag e of len gth les s than 32 byte s
or the last part of a frame at least 32 bytes long is stored in the receive
FIFO. The number of bytes in RFF.RFIFO can be determined reading
the port status regis ter PS R.
ISF Incorrect Synchronization Format
This bi t is se t, whe n no eig ht cons ecutive ‘1’s a re detec ted wi thin 32 bits
in BOM mode. Only valid if BOM receiver has been activated.
PORT Port Number
0..27 The port number the interrupt vector is associated with.
1514 1110987654 0
LAST 0 00 RSA SSM RPF RME ISF 01BPORT(4:0)
PEB 3456 E
Functional Description
Data Sheet 142 05.2001
Transmit Interrupts
•
TXSA Transmit Sa Data Sent
The ’Transmit Sa Data Sent’ is generated, when Sa data stored in
XSAW1 - XSAW3 has been sent N times, where N is defined prior to
transmission in XSAW3.XSAV.
ALLS All Sent
The ’All Sent’ interrupt vector is generated, when the last bit of a frame
to be transmitted is completely sent out and XFF.XFIFO is empty.
XDU Transmit Data Underrun
The ’Transmit Data Underrun’ interrupt vector is generated, when the
transmit FIFO runs out of data during transmission of a frame. The
signalling controller terminates the affected frame with an abort
sequence.
XPR Transmit Pool Ready
The ’Transmit Pool Ready’ interrupt vector is generated, when a new
data block of up to 32 bytes can be written to transmit FIFO. ’Transmit
Pool Ready’ is the fastest way to access the transmit FIFO. It has to be
used for transmission of long frames, back-to-back frames or frames
with shared flag.
PORT Port Number
0..27 The port number the interrupt vector is associated with.
1514 10987654 0
LAST 1 000 TXSA ALLS XDU XPR 01BPORT(4:0)
PEB 3456 E
Functional Description
Data Sheet 143 05.2001
4.13.2.4 DS3, DS2 and Test Unit Interrupts
Note: The DS3, DS2 and test unit interrupts are seperated by the INFO field (bits 4
through 0).
DS3 Interrup ts Type 0
•
DS3 Interrup ts Type 1
•
CLKS DS3 Clock Status
The ‘DS3 Clock Stat us’ inte rrupt vec tor is gen erated whe never the TE3-
CHATT detect s a chang e in the tr ansmit cl ock or t he recei ve clock , i.e.
clock is ac tiv at ed/d ea cti va ted. The ac tua l s tatus of th e c loc k is sh ow n i n
D3RSTAT.LRXC and D3RSTAT.LTXC.
RSDL Receive Spare Data Link Transfer Buffer Full
The ‘Receive Spare Data Link Transfer Buffer Full’ interrupt vector is
generated when the receive spare data link buffer needs to be emptied.
TSDL Transmit Spare Data Link Transfer Buffer Empty
The ‘Tran smit Spare Data Link T ransfer B uffer Emp ty’ in terrupt v ector is
generated when the transmit spare data link buffer needs to be filled.
LPC S Loopback Code Stat us
The ‘Loopback Code Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the received loopback codes. Actual
loopback codes can be found in register D3RLPCS.
SEC 1 Second Interrupt
The ‘1 Second Interrupt’ is generated every second.
NrReceived new Nr-Bit
The ‘Received new Nr-Bit’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the NA overhead bits and when its
state is persistent for at least three multiframes.
151413121110987654 0
LAST 0 AIC XBIT IDLES AISS REDS LOSS FAS 10B00111H
151413121110987654 0
LAST 1 0 CLKS RSDL TSDL LPCS SEC Nr10B00111H
PEB 3456 E
Functional Description
Data Sheet 144 05.2001
AIC Received ne w AIC -Bit
The ‘Received new AIC-Bit’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the AIC overhead bits and when its
state is persistent for at least three multiframes.
XBIT Received X-Bit
The ‘Received new X-Bit’ interrupt vector is generated whenever the
TE3-CH ATT dete ct s a cha nge in the X ov erh ead bits a nd w h en i ts sta t e
is persisten t for at least three mult iframes .
IDLES DS3 Idle Signal Status
The ‘DS3 Idle Signal Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change of the idle signal. D3RSTAT.IDLES
contains the actual state of the idle state, i.e. active/not active.
AISS DS3 Alarm Indication Signal Status
The ‘DS3 Alarm Indication Signal Status’ is generated whenever the
TE3-CHATT detects a change in the AIS alarm state. D3RSTAT.AISS
shows the actual AIS alarm state, i.e. active/not active.
REDS DS3 Red Alarm Status
The ‘DS3 Red Alarm’ interrupt vector is generated whenever the TE3-
CHATT detects a change in the red alarm state. D3RSTAT.RED shows
the actual red alarm state, i.e. active/not active.
LOSS DS3 Input Signal Status
The ‘D S3 Input Signal Status’ inter rupt vector is generated whenever the
TE3-CHATT detects a change in the DS3 input signal state, i.e. loss/no
loss. D3RSTAT.LOSS shows the actual state of the DS3 input signal.
FAS DS3 Frame Alignment Status
The ‘DS3 Frame Alignment Status’ interrupt vector is generated
whenever the TE3-CHATT detects a change in the DS3 frame
alignment. D3RSTAT.FAS shows the actual state.
PEB 3456 E
Functional Description
Data Sheet 145 05.2001
DS2 Framer Interrupts
Note: The effected DS2 tributary is encoded in the INFO field (bits 4..0).
•
LPC S Loop Code Status
The ‘Loopback Code Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the received loopback codes. Actual
loopback codes can be found in register D2RLPCD.
AISS DS2 Alarm Indication Signal Status
The ‘DS2 Alarm Indication Signal Status’ is generated whenever the
TE3-CHATT detects a change in the AIS alarm state. D2RSTAT.AIS
shows the actual AIS alarm state, i.e. active/not active.
REDS DS2 Red Alarm Status
The ‘DS2 Red Alarm Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the red alarm state. D3RSTAT.RED
shows the actual red alarm state, i.e. active/not active.
RES Received new Reserved ITU-T G.747 Overhead Bit
The ‘Received new Reserved ITU-T G.747 Overhead Bit’ interrupt
vector is generated whenever the TE3-CHATT detects a change in the
rese rved ITU-T G .747 overh ead bit an d when its state i s persisten t for at
least three multiframes. D2R[].[] shows the actual state of the overhead
bit.
RAS Remote Alarm Status
The ’Remote Alarm Status’ interrupt vector is generated whenever the
TE3-CHATT detects a change in the remote alarm indication and when
its state is persistent for at least three multiframes. D2RSTAT.RA shows
the actual state of the remote alarm indication.
FAS DS2 Frame Alignment Status
The ‘DS2 Frame Alignment Status’ interrupt vector is generated
whenever the TE3-CHATT detects a change in the DS2 frame
alignment. D2RSTAT.LFA shows the actual status of frame alignment.
1514 121110987654 0
LAST 0 0 LPCS AISS REDS RES RAS FAS 10B00000H - 00110H
PEB 3456 E
Functional Description
Data Sheet 146 05.2001
Test Unit Interrupts Type 0
•
OOS Rece iv er Out Of Syn ch ronization
The ’Receiver Out of Synchronization’ interrupt vector is generated
whenever the test unit detects a change in synchronization. The actual
state of th e receiver is shown in TURSTAT.OOS.
A0 Input all ‘0’s
The ‘Input all ‘0’s’ interrupt vector is generated whenever the TE3-
CHATT detects 32 continuous ‘0’s or when this consition is resolved.
The actual state is shown in TURSTAT.A0.
A1 Input all ‘1’s
The ‘Input all ‘1’s’ interrupt vector is generated whenever the TE3-
CHATT detects 32 continuous ‘1’s or when this consition is resolved.
The actual state is shown in TURSTAT.A1.
LBE Latched Bit Error Detected Flag
The ’Latched Bit Error Detected Flag’ interrupt vector is generated with
the first occurance of a bit error.
EMI End of Measurement Interval
The ‘End of Measurement Interval’ interrupt vector is generated when
the end of the programmed measurement interval is reached.
4.13.2.5 Mailbox Interrupts
•
The ’Mailbox’ interrupt vector is generated, in case that the host CPU on PCI side has
written data to the mailbox status register MBP2E0. The bit field STATUS contains a
copy of MBE2P0.MB(6:0).
1514 1110987654 0
LAST 0 00 EMI LBE A1 A0 OOS 10B01000H
15 14 13 7 6 5 4 0
LAST 0 STATUS(6:0) 11B00000B
PEB 3456 E
Interface Description
Data Sheet 147 05.2001
5 Interface Description
5.1 PCI Interface
A 32-bit and 66 MHz capable PCI bus cont roller provides the in terface between the TE3-
CHATT and the host system. PCI Interface pins are measured as compliant to the 3.3V
signalling environment according to the PCI specification Rev. 2.1.
The PCI bus controller operates as initiator or target. Commands are supported as
follows:
• Master memory read single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Master memory write single DWORD/burst of up to 64 DWORDs with zero wait cycles.
• Slave memory read single DWORD.
• Slave memory write single DWORD.
Fast back-to-back transfers are provided for slave accesses only. All read/write
acces ses to the TE3-CHATT mu st be 32-bit wide, that is al l bytes must be enable d. Non
32-bit accesses result in system interrupt.
Refer also to the PCI specification Rev. 2.1 for detailed information about PCI bus
protocol.
5.1.1 PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when
FRAME is acti va ted (c lo c k 1 in Figure 5-1). During this phase the bus master (initiator)
outputs a valid address on AD(31:0) and a valid bus command on C/BE (3:0). The first
clock of the firs t dat a pha se is cl ock 3. During the data ph as e C / BE indi cat e wh ic h by te
lanes on AD(31: 0) are involved in the current data phase.
The first d ata phase o n a read transa ction requ ires a turnaro und cycl e. In Figure 5-1 the
addr ess is vali d on cl ock 2 an d th en the ma ste r stop s dri vin g AD. The tar get drive s the
AD lines following the turnaround when DEVSEL is asse rted . (TRDY cannot be driven
until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once
enabled, the AD output buffers of the target stay enabled through the end of the
transaction.
A data phase may consist of a data transfer and wait cycles. A data phase completes
when da ta is t rans fer red, w hi ch occurs when both IRDY an d TR DY are as s erte d. Whe n
either is deasserted a wait cycle is inserted. In the example below, data is successfully
transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The
first data phase complete s in the mi nimum ti me for a read transacti on. The sec on d da ta
phase is extended on clock 5 because TRDY is deasserted. The last data phase is
extende d becaus e IR DY is dea ss erte d o n c lo ck 7. The Master know s at cloc k 7 that th e
next data phase is the last. However, the master is not ready to complete the last
PEB 3456 E
Interface Description
Data Sheet 148 05.2001
transfer, so IRDY is dea sserted on clock 7, an d FRAME stays asser ted. Only when IRDY
is asserted can FRAME be deasserted, which occurs on clock 8.
•
Figure 5-1 PCI Read Transaction
5.1.2 PCI Write Transaction
The transaction starts when FRAME is activated (clock 1 in Figure 5-2). A write
transaction is similar to a read transaction except no turnaround cycle is required
follow ing th e addre ss p hase. In the example , t he firs t and seco nd data phas es c omple te
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clo ck 8).
Address Data 1 Data 2 Data 3
Command BE's
12345678
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
Wait
Wait
Wait
Data Transfer
Data Transfer
Data Transfer
Address
phase Data
phase Data
phase
Data
phase
Bus transaction
PEB 3456 E
Interface Description
Data Sheet 149 05.2001
•
Figure 5-2 PCI Write Transaction
5.2 SPI Interface (ROM Load Unit)
Addition al pins, which a re not covered f rom the PCI spe cification, but a re closely rel ated,
are the SPI pins. Via the SPI pins the vendor ID and the vendor subsystem ID can be
loaded into the corresponding PCI configuration registers during start-up of the device.
The SPI Interface supports EEPROMs with an eight bit address space.
After a system reset, the TE3-CHATT starts reading the first byte out of the connected
EEPROM at address 00H. I f th is by te is e qua l AAH, the dev ic e c on tin ues re adi ng out th e
memory cont ents. Ever yti me four byte s are read out of the EEPROM (startin g with byte
address 01H), the EEPROM int erface writes the read i nformation to the PCI configur ation
space. The first four b ytes will be wri tten to the PCI confi guration s pace ad dress 00H, the
next four bytes to the PCI configuration space address 04H and so on. So the contents
of the EEPROM, starting wit h EEPROM byt e addres s 01H, will be mapped over the PCI
configuration space after a system reset. During this configuration phase, all accesses
to the PCI interface will be answered with ‘retry’ by the PCI interface.
If the first byte in the EEPROM is not equal AAH, the EEPROM interface stops loading
the PCI configuration space immediately, and the PCI interface can be accessed. The
PCI configuration space in this case contains the default values.
The configuration mechanism through the serial interface can be disabled by pin
SPLOAD. If this pin is connected to ‘0’, the configuration mechanism is disabled. The
Address Data 1 Data 2 Data 3
Command
12345678
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
Wait
Wait
Data Transfer
Data Transfer
Address
phase Data
phase Data
phase
Data
phase
Bus transaction
BE 1 BE 2 BE 3
Wait
Wait
PEB 3456 E
Interface Description
Data Sheet 150 05.2001
bridge can be accessed through the PCI Interface directly after a system reset. In this
case the PCI configuration space contains the default values.
5.2.1 Accesses to a SPI EEPROM
The EEPROM conten ts can also be controlle d (read and write) by the software . For this,
a special EEPROM control register is implemented as part of the PCI configuration
space. To start a read/write transaction to an connected EEPROM, you have to set the
command, the by te ad dres s (for read-/w ri te data c om ma nds ), t he dat a to be wr i tten an d
the start indication by writing to the EEPROM control register SPI in the PCI
configu ration spa ce. If the int erfa ce d ete cts SPI.ST ART as se rted ( = ‘1’ ), it inte rpre ts th e
command and starts the read-/write transaction to the connected EEPROM. After the
transaction has finished, the EEPROM control module deasserts the start bit. If the
command was a read com mand (Read Sta tus Register, Re ad Data from M emory Array),
the byte that was read out of the EEPROM is available in the data register. For
transactions started with the EEPROM Control register, the interface does not check if
an EEPROM is connected to the SPI bus, because the EEPROM is full passive. A full
functional description of the SPI commands and their usage as well as a description of
the EEPROMs status register can be found in the description of the EEPROM that will
be selected by a board vendor.
Byte Address
For read and write transaction to the connected EEPROM, the byte address must be
written in this regis te r before the tran saction is sta r ted .
Data
For the w rite stat us regis ter transac tion and the write da ta to mem ory array transacti ons,
the data that h as to be writte n to t he EEPROM m ust be wri tten to this register b efore th e
transaction is started. After a read status register transaction or a read data from memory
array tran saction has finis hed (Bit SPI.STA RT is deas serted), th e byte receiv ed from th e
EEPROM is available in this register.
Start
To start the EEPROM transaction defined via register SPI the bit SPI.START must be
set to ‘1’ by a write transactio n through the PCI interface. After the transaction is finished,
the EEPROM start bit is de asserted by the EEPROM inte rface controller. Th is signal has
to be polled by system software.
5.2.2 SPI Read Sequence
The TE3-CHATT selects an external EEPROM by pulling SPCS low. The eight bit read
sequence is transmitted followed by the eight bit address. After the read instruction and
PEB 3456 E
Interface Description
Data Sheet 151 05.2001
address is sent, the data stored in the memory at the selected address is shifted in on
the SPSI pin. The read operation is terminated by setting SPCS high (see Figure 5-3).
•
Figure 5-3 SPI Read Sequence
5.2.3 SPI Write Sequence
Prior to any attempt to write data to an external EEPROM, the write enable latch must
be set by issuing the WREN instruction. This is done by setting SPCS low and then
clocking out the WREN instruction. After all eight bits of the instruction are transmitted,
the SPCS will be brought high to set the write enable latch.
Once the write enable latch is set, the user may proceed by issuing a write instruction,
followed by the eight bit address and then the data to be written. In order that data will
actually be written to the EEPROM, the SPCS is set high after the least significant bit
(D0) of the data byte has been clocked in. Refer to Figure 5-4 for detailed illustrations
on the byte write sequence. While the write is in progress, the register bit SPI.START
may be read to chec k the s tatus of the transac tion. When a write cycl e is c ompl eted, th e
register bit SPI.START is reset.
•
Figure 5-4 SPI Write Sequence
0123456789 14151617181920212223
7 6 0
7 6 5 4 3 2 1 0
00000011
instruction 8 bit address
data in
SPCS
SPCLK
SPSO
SPSI
0123456789 14151617181920212223
7 6 0 7 6 5 4 3 2 1 000000010
instruction 8 bit address data out
SPCS
SPCLK
SPSO
SPSI
PEB 3456 E
Interface Description
Data Sheet 152 05.2001
5.3 L ocal Micr o proces so r Inte rf ace
The Loca l Micr opro cessor In terfa ce is a demultip lexed swit chabl e Int el or Mo torola s tyle
interface with master and slave functionality. In slave mode it is used to operate the M13
multipl ex er, D S3 /D S2 fra me r, T1 /E1 framer an d th e facilit y d ata link o f the TE3-C HATT.
The TE 3-CH ATT prov id es a l oc al c lo ck ou tput LCL K, which is a feed thr ough of the PC I
system clock as clock reference for the local microprocessor interface. The local bus
master capability allows to access peripherals located on the local bus via the PCI
interface. Bit FCONF.LME enables the bus master capability.
The base address register two is disabled per default and can be enabled during start-
up of the internal PCI interface. This is done by setting bit MEM.BAR2 in the PCI
configuration space.
The TE3-CHATT supports a maximum of three 8 kByte pages of memory on the local
address bus. The correspondence between the accessed PCI memory space (mapped
via base address register 2) and the asserted chip selects is shown in table 5-1. The
mapping of the PCI byte enables to the local bus address is dependent on the selected
bus mode and is explained in detail in the corresponding section.
Table 5-1 Correspondence between PCI memory space and chip select
Page AD(14:0) LCS2 LCS1
00000
H - 1FFFH10
12000
H - 3FFFH01
24000
H - 5FFFH00
36000
H - 7FFFHN ot va lid
PEB 3456 E
Interface Description
Data Sheet 153 05.2001
5.3.1 Intel Mode
5.3.1.1 Slave Mode
In Intel slave mode the bus interface supports 16-bit transactions in demultiplexed bus
operatio n. It uses the loc al bus port pins LA (12:1) for the 16 bit a ddress and the loca l bus
port pins LD(15:0) for 16 bit data. A read/write access is initiated by placing an address
on the address bus and asserting LCS0 (Figure 5-5). The external processor then
activates the respective command signal (LRD, LWR). Data is driven onto the data bus
either by the TE3-CHA TT (for read cycl es) or by the external proc essor (for write cycles).
After a period of time, which is determined by the access time to the internal registers
valid data is placed on the bus, which is indicated by asserting the active low signal
LRDY.
Note: LCS0 need not be deasserted between two subsequent cycles to the same
device.
Read cycles
Input data can be latc hed and the comm and sig nal can be deac tivated n ow. This c auses
the TE3-CHATT to remove its data from the data bus which is then tri-stated again.
LRDY is driven high and will be tri-stated as soon as LCS0 is deass erte d.
Write cycles
The comm and s ignal c an be de activate d now . If a subs equen t bus cyc le is req uired, th e
external processor can place the respective address on the address bus.
5.3.1.2 Master Mode
A read/w rite a cc es s f rom th e PCI bus to the 16 bit dem ulti pl exe d loc al bu s is in iti ated by
accessing the PCI memory space base which is controlled by the base address
register 2. Each valid read or write access to this base address triggers the local bus
master interface which in turn starts arbitra tion for the local bus by asserting LHOLD (see
(1) in Figure 5-6). As soon as the TE3-CHATT gets access to the local bus (LHLDA
asserted) it starts the local bus latency timer and begins a read/write transaction as the
bus mas ter. The sign al LHOLD remai ns asserted w hile a transac tion is in prog ress or as
long as the local bus latency timer is not expired. A read/write transaction begins when
the TE3- CHATT place s a val id addre ss on t he addre ss bus, se ts the LB HE signal which
indicates a 8- or 16-bit bus access and asserts the chip select signals LCS1 and/or
LCS2. Then the TE3-CHATT activates the respective command signals (LRD, LWR).
Data is driven onto the data bus either by the TE3-CHATT (for write cycles) or by the
accessed device (for read cycles).
A transaction is finish ed on the loc al b us w he n the external d ev ice a ss erts LRD Y (read y
controlled bus cycles) or when the internal wait state timer expires.
PEB 3456 E
Interface Description
Data Sheet 154 05.2001
•
Figure 5-5 Intel Bus Mode
•
Figure 5-6 Intel Bus Arbitration
Valid C/BE c ombination s and the co rrespondence between loca l address, L BHE and th e
mapping of PCI data to the local data bus are shown in table 5-2 and table 5-3. All
Address Address
Data Data
Read Cycle (16 Bit) Write Cycle (8 bit
1
)
LA(12:0)
LCS0 (In)
LCS 1,2 (Out)
LRD
LWR
LRDY
2
LD(15:0)
LBHE
1
Note 1: Supported in local bus master mode only.
Note 2: Ready controlled bus cycles only.
LHOLD
LHLDA
Bus
Cycle
1
2
One or more
read/write cycles as bus master
3
LHOLD remains asserted as long as a transaction is in
progress or while the latency timer is not expired
Read/Write Cycle
PEB 3456 E
Interface Description
Data Sheet 155 05.2001
accesses not shown in the table result in generation of a ’PCI Access Error’ interrupt
vector.
Table 5-2 C/BE to LA/LBHE mapping in Intel bus mode (8 bit port mode)
Table 5-3 C/BE to LA/LBHE mapping in Intel bus mode (16 bit port mode)
C/BE(3:0) LA(1:0) LBHE LD(15:8) LD(7:0)
1110B00B1-AD(7:0)
1101B01B1-AD(15:8)
1011B10B1 - AD(23:16)
0111B11B1 - AD(31:24)
C/BE(3:0) LA(1:0) LBHE LD(15:8) LD(7:0)
1110B00B1-AD(7:0)
1101B01B0AD(15:8)-
1011B10B1 - AD(23:16)
0111B11B0 AD(31:24) -
1100B00B0 AD(15:8) AD(7:0)
0011B10B0 AD(31:24) AD(23:16)
PEB 3456 E
Interface Description
Data Sheet 156 05.2001
5.3.2 Motorola Mode
5.3.2.1 Slave Mode
The demultiplexed bus modes use the local bus port pins LA(12:1) for the 16- bit address
and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by
placin g an ad dre ss on the add ress bus and ass erting LC S0 togeth er with the c omm an d
signal L WR R D (see “Motorola Bus Mode” on Page 157). The da ta cyc le begin s when
the signal LDS is asserted. Data is driven onto the data bus either by the TE3-CHATT
(for read cycles) or by the external processor (for write cycles). After a period of time,
which is determined by the access time to the internal registers valid data is placed on
the bus, which is indicated by asserting the active low signal LDTACK.
Note: LCS0 need not be deasserted between two subsequent cycles to the same
device.
Read cycles
Input data can be latched and the data strobe signal can be deactivated now. This
causes the TE3-CHATT to remove its data from the data bus which is then tri-stated
again. LDTACK is driven high and will be tri-stated as soon as LCS0 is deasserted.
Write cycles
The data strobe signal can be deactivated now. If a subsequent bus cycle is required,
the external processor can place the respective address on the address bus.
5.3.2.2 Master Mode
As in Intel mode a read/write access from the PCI bus to the 16 bit demultiplexed local
bus is initiated by accessing the PCI memory space base mapped by the base address
register 2. Each valid read or write access to this base address triggers the local bus
master interface which in turn starts arbitration for the local bus using the interface
signal s LBR and LBG and LBGACK. As soon as the TE3-CHATT gets access to th e local
bus it places a valid ad dress on the ad dress bus, s ets the LSIZE0 si gnal which ind icates
a 8- or 16-bit bus access and asserts the corresponding chip select signal. The signal
LWRRD indicates a read or w rite opera tion. The data cyc le begin s when the si gnal LDS
is asse rted. Data is driven onto the data bu s either by the TE3-CH ATT or by the external
component.
A transact ion is fini shed on the local bus when the e xternal dev ice asserts the active low
signal LDTACK or when the internal wait state timer expires.
PEB 3456 E
Interface Description
Data Sheet 157 05.2001
•
Figure 5-7 Motorola Bus Mode
•
Figure 5-8 Motorola Bus Arbitration
Address Address
Data Data
Read Cycle (8 bit
1
)Write Cycle (16 bit)
LA(12:0)
LDS
LRDWR
LDTACK
2
LD(15:0)
LSIZE0
1
LCS0 (In)
LCS1,2 (Out)
Note 1: Supported in local bus master mode only.
Note 2: LDTACK controlled bus cycles only.
LBR
LBG
Bus
Cycle
1
2
One or more
read/write cycles as bus master
3
LBGACK remains asserted as l ong as a
transaction is in progress or while the latency
timer is not expired.
LBGACK
RD/WR Cycle
PEB 3456 E
Interface Description
Data Sheet 158 05.2001
The address and byte enable signals on the PCI bus are mapped to the local bus
according to table 5-4 and table 5-5. It can be seen that the TE3-CHATT supports
different valid C/BE combinations which result in either a 8- or 16-bit access to the local
bus interface. All accesses not shown in the table result in generation of a ’PCI Access
Error’ interrupt vector. Byte swapping for 16 bit data transfers can be disabled.
Table 5-4 C/BE to LA/LSIZE0 mapping in Motorola bus mode (8 bit port mode)
Table 5-5 C/BE to LA/LSIZE0 m apping in Motorola bus m ode (16 bit port mode)
5.4 Serial Line Interface
The DS3 interfac e of the T E3-CHATT consists of one rec eive po rt and one transmit po rt.
The receive port provides a clock input (RC44) and one (RD44) or two data inputs
(RD44P, R D44N) for un ipolar or du al-rail inp ut signals. R eceive data can be sam pled on
the rising or falling edge of the receive clock. In transmit direction the port interface
consists of two clock signals, the transmit clock input TC44 and a clock output signal
TC44O. The data signals consists of one (TD44) or two data outputs (TD44P, TD44N)
for unipolar or dual-rail output signals. The transmit port can be clocked by the receive
clock RC44 or by the transmit clock TC44. The selected clock is provided as an output
on TC44O. Transmit data is updated on the rising or falling edge of TC44O.
The TE3-CHATT provides two additional serial interfaces, one for DS3 overhead bit
access and one for DS3 st uff bit access (M13 asynchronous format only).
The ove rhead acces s is provided via an overh ead clock sig nal (ROVHC K, TOVHCK), an
overhead data signal (ROVHD, TOVHD) and an synchronization signal (ROVHSYN,
C/BE(3:0) LA(1:0) LSIZE0 LD(15:8) LD(7:0)
1110B00B1 AD(7:0) -
1101B01B1AD(15:8)-
1011B10B1 AD(23:16) -
0111B11B1 AD(31:24) -
C/BE(3:0) LA(1:0) LSIZE0 LD(15:8) LD(7:0)
1110B00B1 AD(7:0)
1101B01B1-AD(15:8)
1011B10B1 AD(23:16) -
0111B11B1 - AD(31:24)
1100B00B0 AD(7:0) AD(15:8)
0011B10B0 AD(23:16) AD(31:24)
PEB 3456 E
Interface Description
Data Sheet 159 05.2001
TOVHSYN) which marks the X overhead bit of the first subframe of a DS3 signal. In
transmi t direction th e overhead e nable signa l (TOVHEN) mark s those bi ts which shal l be
inserted in the overhead bits of the DS3 signal. All overhead signals are updated or
sampled on the rising edge of the corresponding overhead clock, i.e. ROVHCK or
TOVHCK. See Figure 5-9 and Figure 5-10 for details.
•
Figure 5-9 Receive Overhead Access
X84 data bits F
1
F
1
C
11
84 data bits 84 data bits
RD44
RC44
F
1
X
ROVHCK
ROVHD
ROVHSYN
7
th
subframe 1
st
subframe
F
1
PEB 3456 E
Interface Description
Data Sheet 160 05.2001
•
Figure 5-10 Transmit Overhead Access
The stuff bit access is provided via a receive and transmit stuff bit clock (RSBCK,
TSBCK) and the two stuff bit signals RSBD and TSBD. Stuff bits are updated and
sampled on the rising edge of the of stuff bit clock.
TOVHEN
X84 data bits F
1
F
1
C
73
84 data bits 84 data bits
TD44
TC44O
F
1
X
TOVHCK
TOVHD
TOVHSYN
(Output mode)
7
th
subframe 1
st
subframe
F
1
TOVHEN
X84 data bits F
1
F
1
C
73
84 data bits 84 data bits
TD44
TC44O
F
1
X
TOVHCK
TOVHD
TOVHSYN
(Inp ut mode)
7
th
subframe 1
st
subframe
F
1
1. Transmit Overhead Bit Access (TOVHSYN in output mode)
2. Transmit Overhead Bit Access (TOVHSYN in input mode)
PEB 3456 E
Interface Description
Data Sheet 161 05.2001
5.5 JTAG Interface
A test access port (TAP) is implemented in the TE3-CHATT. The essential part of the
TAP is a finite state machine (16 states) controlling the different operational modes of
the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE 1149.1. Figure 5-11 gives an o verview about th e TAP
controller.
•
Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit
If no bounda ry scan op era t io n i s pl ann ed TR ST ha s to be c on nec ted wi th VSS. TMS and
TDI do n ot need to be co nnected sin ce pull- up tran sistors ens ure high input l evels in this
case. Nev ertheless it would be a good p ractice to put the unu sed inputs to defined lev els.
In this case, if the JTAG is not used:
TMS = TCK = ‘1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i. e. TRST is connected to VDD3 or it remains
unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal
connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state to
another; constant ‘1’ on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells
(data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note
that most functional output and input pins of the TE3-CHATT are tested as I/O pins in
boundary scan, hence using three cells. The boundary scan unit of the TE3-CHATT
Clock Generation
Test Access Port (TAP)
TAP Controller
- Finite State Machine
- Instruction Register (4 bit)
- Test Signal Generator
CLOCK
TCK
TRST
TMS
Reset
Data in
TDI
Test
Control
TDO
Enable
Data out
CLOCK
Identification Scan (32 bit)
Boundary Scan (n bit)
Control
Bus
ID Data out
SS Data
out n
.
.
.
.
.
.
1
2
Pins
PEB 3456 E
Interface Description
Data Sheet 162 05.2001
contains a total of n = 484 scan cells. The desired test mode is selected by serially
loading a 4-bit instruction code into the instruction register via TDI (LSB first).
EXTEST is u sed to ex am ine the interc on nec tio n of the device s on the board. In th is tes t
mode at first all input pins capture the current level on the corresponding external
intercon necti on lin e, wh ereas a ll out put pin s are h eld at const ant value s (‘0’ or ‘1’). Then
the contents of the boundary scan is shifted to TDO. At the same time the next scan
vector is loaded from TDI. Subs equently all outp ut pins are updated a ccording to the new
boundary scan contents and all input pins again capture the current external level
afterwards, and so on.
INTEST support s internal testing of the chip, i. e. the ou tput pins capture the current level
on the corr esp ondin g intern al line wherea s all i nput pin s are he ld on co nstan t val ues (‘0 ’
or ‘1’). The resulting boundary scan vector is shifted to TDO. The next test vector is
serially loaded via TDI. Then all input pins are updated for the following test cycle.
SAMPLE/PRELOAD is a test mode which provides a snapshot of pin levels during
normal operat ion.
IDCODE: A 32-bit identification register is serially read out via TDO. It contains the
version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits).
The LSB is fixed to ‘1’.
The ID code field is set to
Version : 2H
Part Number : 0077H
Manufacturer : 083H (including LSB, which is fixed to ’1’)
Note: Since in test logic reset state the code ‘0011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
CLAMP allows the state of signals driven from component pins to be determined from
the boundary-scan register while the bypass register is selected as the serial path
between TDI and TDO. Signals driven from the TE3-CHATT will not change while the
CLAMP instruction is selected.
HIGHZ places all of the system outputs in an inactive drive state.
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 163 05.2001
6 Channel Programming / Reprogramming Concept
For chann el programming the TE3-CHATT provides a on-chip channel specifi cation data
structure. All information necessary to setup a chann el has to be provided using this data
structure. As soon as all channel information has been written to the channel
specif ication regis ters the informat ion can be relea sed using simpl e channel com mands,
which ha ve to be writ ten to re giste r CSPEC_CMD. The relevant chann el info rmation wil l
then be copied to the chip internal channel database. The channel specification
registers, which need to be programmed before a command can be executed, are shown
in Table 6-1.
Before initializing a channel the time slot assignment process for the affected channel
must be completed. Vice versa after shutting down a channel the time slots associated
with the affected channel should be set to inhibit. Otherwise if a time slot is
reprogrammed afterwards, strange behavior can be expected on the serial side.
For each channel a simple sequence of chan nel commands must be ensured. After reset
each channel is in its ’off’ state. Therefore, the first command to start a channel is
’Transmit Init’ or ’Receive Init’. This brings the channel into the operational state. In this
state all commands except ’Transmit Init’, ’Receive Init’ or ’Transmit Idle can be given.
To brin g a channel back into the idle sta te a ’Transmit O ff’ or ’Receive Of f’ command ha s
to be programmed. For certain channel commands system software has to wait before
new commands can be given for the same channel. This is due to internal buffer
alloca tion functi ons which requ ire some pro cessing tim e. Notifica tion of syste m software
is done in form of command interrupt vectors, which signal that a command has
successful or even unsuccessful completed.
Table 6-1 Channel Specification Registers and Channel Commands
Register Transmit Commands Receive
Commands
Transmit Init
Transmit Off
Transmit Abort/Branch
Transmit Hold Reset
Transmit Idle
Transmit Debug
Transmit Update FNUM
Receive Init
Receive Off
Receive Abort/Branch
Receive Hold Reset
Receive Debug
CSPEC_MODE_REC
CSPEC_REC_ACCM
CSPEC_MODE_XMIT
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 164 05.2001
6.1 Channel Commands
The following section describes all receive and transmit channel commands and the
progra mmin g sequ en ce in details.
6.2 Transmit Channel Commands
Transmit Init
Before a ’Transmit Init’ command is given, the TE3-CHATT will not transmit data for a
channel . After the ’ Transmit Init’ com mand the ch annel dat abase of the affe cted cha nnel
is initialized according to the parameters in the channel specification registers.
After initialization the transmit buffer prepares the buffer locations for the selected
channel and the data management unit starts processing the linked list and fills the
prepa red buff er loca tions . In orde r to prev ent a transm it unde rrun co nditio n, the t ransm it
buffer is filled up to the transmit forward threshold before data is sent to the serial side.
The protocol machine formats data according to the given channel parameters and the
data is placed in the time slots assigned to the selected channel. When no or not
sufficient data is available, the device sends the idle code according the selected
protocol mode.
If the command was successful, a ’Transmit Command Complete’ interrupt vector is
generate d after the first tran smit descrip tor is read pointe d to by register CSPEC_ FTDA.
In case that there is insufficient transmit buffer space, the command cannot be
CSPEC_XMIT_ACCM
CSPEC_BUFFER
CSPEC_FRDA
CSPEC_FTDA
CSPEC_IMASK
Register Transmit Commands Receive
Commands
Transmit Init
Transmit Off
Transmit Abort/Branch
Transmit Hold Reset
Transmit Idle
Transmit Debug
Transmit Update FNUM
Receive Init
Rece ive Off
Receive Abort/Branch
Receive Hold Reset
Receive Debug
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 165 05.2001
completed internally and the device responds with a ’Transmit Command Failed’
interrupt vector. Furthermore the TE3-CHATT will not start processing the linked list for
this particular channel.
New commands for the same channel may be given after the user received the ’Transmit
Command Complete’ interrupt vector. Prior to new initialization of the same channel it
must be turned off using the ’Transmit Off’ command.
Transmit Off
After ’Transmit Off’ the transmit channel is disabled immediately and the time slots
assigned to the selected channel are set to ’1’. The transmit buffer releases all buffer
locations assigned to the channel. The data management unit updates the last
processed descriptor with the complete bit if enabled and generates a ’Transmit Host
Initiated’ interrupt vector if the THI bit in the last descriptor was set. All channel related
informations are cleared from the internal channel database.
A ’Transmit Command Complete’ interrupt vector is generated when the channel
command is finished. After that time processing of the linked list is completely stopped.
New commands for the same channel may be given after the user received the ’Transmit
Command Complete’ interrupt vector.
Transmit Abort/Branch
The ’Transmit Abort/Branch’ command is performed on the serial side and in the data
manage ment uni t. The data ma nagem ent unit st ops imme di ately pro cessin g the curre nt
descriptor and bra nches to a new des cript or pointed to by CSPEC_FTDA. Da ta whic h is
already store d in th e tran sm it bu ffer is sen t on th e ser ial sid e. The proto col mac hi ne w il l
append an abort sequence if data in transmit buffer was not complete due to ’Transmit
Abort/Branch’ command. System software is informed about the aborted frame by a
’Transmit Abort’ channel interrupt vector. If no data is stored in the transmit buffer this
command does not affect the serial side and no ’Transmit Abort’ interrupt vector is
generate d. Data transmission is continued with a new frame when the data management
unit branched to the new descriptor list.
A ’Transmit Command Complete’ interrupt vector is generated after the management
unit released the old descriptor list. New commands for the same channel may be given
after the user received the ’Transmit Command Complete’ interrupt vector.
Transmit Hold Reset
The ’Transmit Hold Reset’ command must be given after system software has set the
HOLD bit of a descriptor from ’1’ to ’0’. In case that the TE3-CHATT is in hold condition
it reads the descriptor which had its HOLD bit set and tests the HOLD bit of the
descriptor. If the HOLD bit is set to ’0’ the data management unit branches to the next
descrip tor an d con tinues data trans miss ion. Otherwi se th e parti cular chan nel re mains in
hold condition.
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 166 05.2001
The TE3-CHATT will NOT generate a ’Transmit Command Complete’ interrupt vector
after this command is programmed.
Transmit Update FNUM
The ’Transmit Update FNUM’ command changes the parameter
CSPEC_MODE_XMIT.FNUM in the internal channel database, which allows to change
dynamically the number of idle flags that are inserted between two frames.
The TE3-CHATT will NOT generate a ’Transmit Command Complete’ interrupt vector
after this command is programmed.
Transmit Idle
The ’Transmit Idle’ command starts the TE3-CHATT to send the value
CSPEC_MODE_XMIT.TFLAG in the time slots of the selected channel. This command
can only be given if a channel is turned off.
The TE3-CHATT will NOT generate a ’Transmit Command Complete’ interrupt vector
after this command is programmed.
Transmit Debug
The ’Transmit Debug’ command allows to read back the current settings of the internal
channel database. After the ’Transmit Debug’ command has been programmed system
software can read back the current values of the channel specification registers. Register
CSPEC_FTDA contains the value of the next transmit descriptor.
The TE3-CHATT will NOT generate a ’Transmit Command Complete’ interrupt vector
after this command is programmed.
Note: The setting of the internal channel database is not copied into the channel
specification registers and therefore the values read can not be used to program
another c ha nne l. After sy ste m s oft ware has us ed the ’Transmi t Deb ug’ comm an d
it must repr ogra m the ch ann el spe ci fic ati on regi sters to setup a new ch ann el.
6.3 Receive Channel Commands
Receive Init
Before a ’Receive Init’ command is given, the TE3-CHATT will not process data for a
channel . After the ’ Re ce ive Init’ c om m and th e channel database of the affecte d c ha nne l
is ini tializ ed ac cordi ng to the p arame ters p rogramm ed i n cha nnel spec ificat ion re gisters.
Afte r init ializ ation da ta rece ived i n thos e time s lots ass igned to the se lect ed chan nel is
processed and stored in the internal receive buffer. The data management unit starts
storing this data in the linked list which starts at CSPEC_FRDA. The protocol machine
deformats and checks data according to the given channel parameters.
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 167 05.2001
A ’Receive Command Complete’ interrupt vector is generated after the channel
information is copied into the internal channel database.
New commands for the same channel may be given after the TE3-CHATT issued the
’Receive Command Complete’ interrupt vector. Prior to new initialization of the same
channel it must be turned off using the ’Receive Off’ command.
Receive Off
The ’R eceive Off’ com mand di sables the recei ve chann el imme diately. Further incomin g
data is discarded until the next ’Receive Init’ command is given. Data already stored in
the receive buffer is written to system memory. If a frame is destroyed by the ’Receive
Off’ command a ’Receive Abort’ channel interrupt vector is generated.
A ’Receiv e Command Compl ete’ interrupt v ector is genera ted after remain ing data in the
receive buffer is written to syst em memory . After that ti me proc essi ng of the li nked li st is
stopped and the channel information is cleared from the internal channel database.
New commands for the same channel may be given after the TE3-CHATT issued the
’Receive Command Complete’ interrupt vector.
Receive Abort/Branch
The ’Receive Abort/Branch’ command is performed in the data management unit. The
data management unit stops immediately processing the current descriptor and
branches to a new descriptor pointed to by CSPEC_FRDA. In case that the ’Receive
Abort/Branc h’ command is iss ued while a pack et is written to system memo ry a ’Receive
Abort’ interrupt vector is generated and the rest of the frame already stored in receive
buffer is discarded. Data reception is continued with a new frame when the data
management unit branched to the new descriptor list.
A ’Receive Command Complete’ interrupt vector is generated after the channel
information is copied into the internal channel database. New commands for the same
channel may be given after the TE3-CHATT issued the ’Receive Command Complete’
interr upt ve ctor.
Receive Hold Reset
The ’Receive Hold Reset’ command must be given after system software has set the
HOLD bit of a receive descriptor from ’1’ to ’0’. In case that the TE3-CHATT is in hold
conditi on it reads the descr iptor which had its HOL D bit set an d tests the HOLD bit of th e
descriptor. If the HOLD bit is set to ’0’ the data management unit branches to the next
descriptor and continues data reception. Otherwise the particular channel remains in
hold condition.
The TE3-CHATT will NOT generate a ’Receive Command Complete’ interrupt vector
after this command is programmed.
PEB 3456 E
Channel Programmin g / Reprogramming Conc ept
Data Sheet 168 05.2001
Receive Debug
The ’Receive Debug’ command allows to read back the current settings of the internal
channel database. After the ’Receive Debug’ command has been programmed system
software can read back the current values of the channel specification registers. Register
CSPEC_FRDA contains the value of the next receive descriptor.
The TE3-CHATT will NOT generate a ’Receive Command Complete’ interrupt vector
after this command is programmed.
Note: The setting of the internal channel database is not copied into the channel
specification registers and therefore the values read can not be used to program
another channel. After system software has used the ’Receive Debug’ command
it must repr ogra m the ch ann el spe ci fic ati on regi sters to setup a new ch ann el.
PEB 3456 E
Reset and Initialization procedure
Data Sheet 169 05.2001
7 Reset and Initialization procedure
Since the term “initialization” can have different meanings, the following definition
applies:
Chip Initialization
Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc.
Mode Initialization
Software procedu re, that p repares the devic e to its required operat ion, i.e . mainly writing
on-chip registers to prepare the device for operation in the respective system
environment.
Operational programming
Software procedure s that setup, maintain and shut down oper ational modes, i.e. initialize
logical channel or maintain framing operations on selected ports.
7.1 Chip Initialization
Hardware reset
The hardware reset RST has to be applied to the device. Chip input TRST must be
activated prior to or while asserting RST and should be held asserted as long as the
boundary scan operation is not required. System clock must start running during reset.
During reset:
• All I/Os and all outputs are tri-state.
• All registers, state machines, flip-flops etc. are set asynchronously to their reset
values and all internal modules are set to their initial state.
• All interrupts are masked.
• The register bit CONF1.STOP is set to ‘1’.
After hardware reset (RST deasserted) system clock CLK is assumed to be running.
Serial clocks must be low/high or running. The PCI and the local bus interface pins go
into their idle state. All serial line outputs are tri-state.
The PCI interface becomes active and depending on input pin SPLOAD starts to read
subsystem ID/subsystem vendor ID and Memory commands out of external EEPROM
via the SPI interface. The serial clock is derived from the PCI clock. As long as this
procedure is active, the PCI interface answers all accesses with retry. After the PCI
interface has finished its self initialization it can be configured with PCI configuration
cycles.
In parallel to PCI self initialization the internal modules start their RAM initialization. As
long as the R AM in iti ali zation is run ni ng the intern al modules ind ic ate this c ond iti on w i th
PEB 3456 E
Reset and Initialization procedure
Data Sheet 170 05.2001
their init ialization in progress signal. The register bit CONF1.IIP is the result of all signals.
As soon as all internal modules have finished their RAM initialization the register bit
CONF1.I IP is dea sserted. So ftware must p oll the register bit CONF1.II P until this bit ha s
been deasserted. Read access to registers other than CONF1 is prohibited and may
result in unexpected behavior of the design. Write accesses are not allowed.
Chip initialization is finished when CONF1.IIP is ‘0’.
Software Reset
Alternatel y the TE 3-CH ATT prov id es the cap ab ility to is s ue a so ftw are res et v ia reg is ter
bit CONF1.SRST. During software reset all interfaces except PCI interface are forced
into the ir i dle s tate . Afte r s oftwa re re se t is s et the TE3-CHAT T s tarts i ts sel f i nitializ atio n
and IIP will be asserted. Chip initialization is finished when CONF1.IIP is deasserted.
Afterwards the software reset bit must be set to ‘0’ to allow further operation.
7. 2 Mode In itialization
After chip initialization is finished the system software has to setup the device for the
required func ti on.
The system software has to poll bit CONF1.IIP (FCONF.IIP). As soon as CONF1.IIP is
deasserted, the system software has to clear bit CONF1.STOP and has to set the
general operating modes in register CONF1.
The M13 multiplexer, DS3/DS2 framer mode, T1/E1 framer mode and the DS1/E1 and
DS3 port interface has to be programmed. It is assumed, that the DS3 port clock and
CTCLK are active. The T1/E1 ports shall be d isabled, thus no incomi ng data is forwarded
to the time slot assigner and to the T1/E1 framer.
Transmit direction
The T1/E1s have to be enabled via register XPI.TEN. After the tributaries are enabled,
the F-Bit (T1 mode) respectively time slot zero (E1 mode) are generated by the on-chip
T1/E1 framer and the signalling controller. To synchronize the first bit of a frame to an
external reference the co mmon transm it frame synchroni zation pulse CTFS can be use d
(in external timing mode only). After a tributary has been enabled, payload data is
provi ded from the time slo t assig ner. Since the time slo t assignment is in rese t state, that
is all time slots are set to inhibit, data bits are sent as ‘1’.
Receive direction
The tr ibu tari es ha ve to be ena ble d v ia reg is ter XPI.R EN. Af ter they a re e nab led , the on-
chip T1/E1 framer tries to achieve frame alignment. As soon as frame alignment has
been achieved, incoming payload data is passed to the time slot assigner. Since time
slot assignment is in reset state, that is all time slots are set to inhibit, data bits are
discarded.
PEB 3456 E
Register Description
Data Sheet 171 05.2001
8 Register De sc ript ion
The register description of the TE3-CHATT is divided into two parts, an overview of all
internal registers and in the second part a detailed description of all internal registers.
8.1 Register Overview
The first part of the register overview describes the PCI configuration space registers.
The second part describes the register set which can be accessed from PCI side only.
These registers are used to setup the main operation modes and to run the channel
engines of the device. The last part des cribes t he regist er set of the framing engin es, the
signalling controller, the mailbox and the local interrupt FIFO. These registers may be
accessed through the local micropro cessor interface or via PCI.
Note: Register locations not contained in the following register tables are “reserved”. In
general all w ri te a cc es se s to rese rve d regi ste rs are discarde d a nd read acc es s to
reserved registers result in 00000000H. Nevertheless, to allow future extensions,
system soft ware sh all a cces s doc ument ed regi sters only , since write s to reserve d
register s ma y resu lt in une xpect ed beha vior . The read value of reserv ed regis ters
shall be handled as don’t care.
Unused and reserved bits are marked with a gray box. The same rules as given
for register accesses apply to reserved bits, except that system software shall
write the documented default value in reserved bit locations.
8.1.1 PCI Configuration Register Set (Direct Access)
Table 8-1 PCI Configuration Register Set
Register Access Address Reset
value Comment Page
Standard configuration space register
DID/VID R 00H2108110AHDevice ID/Vendor ID 183
STA/CMD R/W 04H02A00000HStatus/Command 184
CC/RID R 08H02800001HClass Code/Revision ID 186
BIST/
HEAD/
LATIM/
CLSIZ
R/W 0CH00000000H
Built-in Self Test/
Header Type/
Latency Timer/
Cache Line Size
187
BAR1 R/W 10H00000000HBase Address 1 188
BAR2 R/W 14H00000000HBase Address 2 189
BARX R 14H-24H00000000HBase Address Not Used
PEB 3456 E
Register Description
Data Sheet 172 05.2001
CISP R 28H00000000HCardbus CIS Pointer
SSID/
SSVID R2C
H00000000HSubsystem ID/
Subsystem Vendor ID 190
ERBAD R 30H00000000HEx pan si on R OM Base Adr.
Reserved R 34H00000000HReserved
Reserved R 38H00000000HReserved
MAXLAT/
MINGNT/
INTPIN/
INTLIN
R/W 3CH06020100H
Maximum Latency/
Min imu m Gr a nt/
Interrupt Pin/
Interrupt Line
191
User defined configuration space register
SPI R/W 40H0000001FHSPI Access Register 192
REQ R/W 44H00000000HREQ/GNT Config Register 194
MEM R/W 48H000007E6HPCI Memory Command 195
DEBUG R 4CH00000000HPCI Debug Support 197
Register Access Address Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 173 05.2001
8.1.2 PCI Slave Register Set (Direct Access)
This section shows all registers which are located on the first configuration bus. These
registers are used to setu p the basic opera ting modes of the device and to setup the port,
time slo ts and chan nels. Syst em softwa re has acce ss to these regi sters v ia the PCI bus.
Table 8-2 PCI Slave Register Set
Register Access Address Reset
value Comment Page
General Control
CONF1 R/W 040HConfiguration Registe r 1 215
CONF2 R/W 044H00000000HConfiguratio n Register 2 218
CONF3 R/W 048H00090000HConfiguratio n Register 3 220
RBAFT W 04CH00000000HReceive Buffer Access Failed
Interrupt Threshold 221
SFDT W 050H00000000HSmall Frame Dropped
Interrupt Threshold Register 222
Interrupt control PCI bus side
IQIA R/W 0E0H00000000HInterrupt Queue Initialization 239
IQBA R/W 0E4H00000000HInterrupt Queue Base Addr. 241
IQBL R/W 0E8H00000000HInterrupt Queue Length 242
IQMASK R/W 0ECH00000000HInterrupt Queue Mask 243
GISTA/GIACK R/W 0F0H00000000H
Global Interrupt Status/
Global Interrupt
Acknowledge 244
GMASK R/W 0F4HFFFFFFFFHInterrupt Mask 246
Channel specification registers (* = CSPEC)
*_CMD W 000H00000000HCommand 198
*_MODE_REC R/W 004H00000000HMode Receive 200
*_REC_ACCM R/W 008H00000000HReceiver ACCM Map 2 03
*_MODE_XMIT R/W 014H00000000HMode Transmit 204
*_XMIT_ACCM R/W 018H00000000HTransmit ACCM Map 207
*_BUFFER R/W 020H00200000HBuffer Configura tio n 208
*_FRDA R/W 024H00000000HFirst Receive Descriptor
Addr. 211
PEB 3456 E
Register Description
Data Sheet 174 05.2001
*_FTDA R/W 028H00000000HFirst Transmit Descriptor
Address 212
*_IMASK R/W 02CH00000000HInterrupt Vector Mask 213
Port and time slot control registers
PMIAR R/W 060H00000000HPort Mode Indirect Access 223
PMR R/W 064H0104C000HPort Mode 224
REN R/W 068H00000000HRece ive Enable 226
TEN R/W 06CH00000000HTransmit Enable 227
TSAIA R/W 070H00000000HTime slot Assignment
Indi rect Access 228
TSAD R/W 074H02000000HTime slot Assignment Data 230
PPP character map/ demap registers
REC_ACCMX R/W 080H00000000HReceive Extended ACCM
Map 232
XMIT_ACCMX R/W 090H00000000 Transmit Extended ACCM
Map 236
Receive buffer control
RBMON R 0B0H02000BFFHReceive Buffer Monitor 237
RBTH R/W 0B4H02000001HReceive Buffer Threshold
Report 238
Maintenance
RBAFC R 084H00000000HReceive Buffer Access Failed
Counter 233
SFDIA R/W 088H00000000HSmall Frame Dropped
Indi rect Access 234
SFDC R 08CH00000000HSmall Frame Dropped
Counter 235
Register Access Address Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 175 05.2001
8.1.3 PCI and Local Bus Register Set (Direct Access)
This section describes the registers which are located on the configuration bus II (see
also Thes e reg is ters can be ac ces s ed ei the r from PCI bu s via the inte rnal bus bridge or
from the local bus sid e.
Note: Since the local bus is 16-bit wide and the PCI bus is 32-bit wide, the upper 16 bit
of data coming from/to PCI are discarded.
Note : Ple ase note t hat re ad access es to loc al bus reg isters via P CI bus an d theref ore
the internal bus bridge may result in latencies which exceed the 16 clock rule of
PCI specification. Exceeding the 16 clock rule results in target initiated retry on
PCI bus. In this case the read cycle needs to be repeated.
Table 8-3 PCI and Local Bus Slave Register Set
Register Access Address
(PCI)
Address
(Local
Bus)
Reset
value Comment Page
FCONF R/W 100H00H8080HConfiguration Register 247
MTIMER R/W 104H00H0001HMaster Local Bus
Timer 249
Interrupt control for local bus side
INTCTRL R/W 108H04H0001HInterrupt Control 250
INTFIFO R 10CH06HFFFFHInterrupt FIFO 251
DS3 Clock Configuration and Status Register
D3CLKCS R/W 180H40H0000HDS3 Clock Confi -
guration and Status 263
TUCLKC R/W 184H42H0000HTest Unit Clock
Configuration 265
DS3 Transmit Control Registers
D3TCFG R/W 188H44H0000HTransmit Configuration 266
D3TCOM R/W 18CH46H0070HTransmit Command 268
D3TLPB R/W 190H48H0000HRe mo t e DS 2
Loopback 270
D3TLPC R/W 194H4AH0000HTransmit Loopback
Code Insertion 271
D3TAIS R/W 198H4CH0000HTransmit AIS Insertion 272
D3TFINS R/W 19CH4EH0000HTransmit Fault
Insertion Control 273
PEB 3456 E
Register Description
Data Sheet 176 05.2001
D3TTUC R/W 1A0H50H0000HTransmit Test Unit
Control 274
D3TSDL R/W 1A4H52H01FFHTransmit Spare Data
Link 275
DS3 Receive Control/Status Registers
D3RCFG R/W 1C0H60H0000HReceiv e Confi gurat ion 276
D3RCOM R/W 1C4H62H0000HReceive Command 279
D3RIMSK R/W 1C8H64H1FFFHReceive Interrupt
Mask 281
D3RESIM R/W 1CCH66H0000HReceive Error
Simulation 282
D3RTUC R/W 1D0H68H0000HReceive Test Unit
Control 283
D3RSTAT R 1D4H6AH0841HReceive Status 284
D3RLPCS R 1D8H6CH0000HReceive Loopback
Code Status 287
D3RSDL R 1DCH6EH01FFHReceive Spare Data
Link 288
D3RCVE R/W 1E0H70H0000HReceive B3ZS Code
Violation Error Coun ter 289
D3RFEC R/W 1E4H72H0000HReceive Framing Bit
Error Counter 289
D3RPEC R/W 1E8H74H0000HReceive Parity Bit
Error Counter 290
D3RCPEC R/W 1ECH76H0000HReceive CP-Bit Error
Counter 290
D3RFEBEC R/W 1F0H78H0000HReceive FEBE Error
Counter 291
D3REXZ R/W 1F4H7AH0000HReceive Exzessive
Zero Counter 291
D3RAP R/W 1F8H7CH0000HAlarm Timer
Parameter 292
Register Access Address
(PCI)
Address
(Local
Bus)
Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 177 05.2001
DS2 Transmit Co ntrol Regis t ers
D2TSEL R/W 200H80H0000HDS2 Transmit Group
Select 293
D2TCFG R/W 204H82H0000HTransmit Configuration 294
D2TCOM R/W 208H84H0000HTransmit Command 295
D2TLPC R/W 20CH86H0000HTransmit Loopback
Code Insertion 296
DS2 Receive Control R egis ters
D2RSEL R/W 220H90H0000HDS2 Receive Group
Select 297
D2RCFG R/W 224H92H0000HReceive Configuration 298
D2RCOM R/W 228H94H0000HReceive Command 299
D2RIMSK R/W 22CH96H003FHReceive Interrupt
Mask 301
D2RSTAT R 230H98H0001HReceive Status 302
D2RLPCS RD 234H9AH0000HReceive Loopback
Code Status 304
D2RFEC R/W 238H9CH0000HReceive Framing Bit
Error Counter 305
D2RPEC R/W 23CH9EH0000HReceive Parity Bit
Error Counter 305
D2RAP R/W 240HA0H0000HAlarm Timer
Parameter 306
Test Unit Transmit Registers
TUTCFG R/W 280HC0H0000HTransmit Configuration 308
TUTCOM W 284HC2H0000HTransmit Command 309
TUTEIR R/W 288HC4H0000HTransmit Error
Insertion Rate 311
TUTFP0 R/W 28CHC6H0000HTran smit Fixed Patt ern 312
TUTFP1 R/W 290HC8H0000H
Test Unit Receive Registers
TURCFG R/W 2A0HD0H0000HReceive Configuration 313
Register Access Address
(PCI)
Address
(Local
Bus)
Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 178 05.2001
TURCOM W 2A4HD2H0000HReceive Command 315
TURERMI R/W 2A8HD4H0000HReceive Error Rate
Measurement Interval 317
TURIMSK R/W 2ACHD6H001FHReceive Interrupt
Mask 318
TURSTAT R 2B0HD8H0021HReceive Status 319
TURBC0 R 2B4HDAH0000HReceive Bit Counter 321
TURBC1 R 2B8HDCH0000H
TUREC0 R 2BCHDEH0000HReceive Error Counter 323
TUREC1 R 2C0HE0H0000H
TURFP0 R 2C4HE2H0000HReceive Fixed Pattern 325
TURFP1 R 2C8HE4H0000H
T1/E1 Framer transmit registers
TREGSEL R/W 110H08H0000H
Transmit T1/E1
Framer Port &
Register Select 252
TDATA R/W 114H0AH0000HTransmit T1/E1
Framer Data 253
T1/E1 Framer receive registers
RREGSEL R/W 118H0CH0000HReceive T1/E1 Framer
Port & Register Select 254
RDATA R/W 11CH0EH0000HReceive T1/E1
Framer Data 255
Facility data link registers
FREGSEL R/W 120H10H0000HFacility Data Link Port
& Register Select 256
FDATA R/W 124H12H0000HFacility Data Link Data 258
Mailbox registers
MBE2P0 R/W 140H20H0000HMailbox Local Bus to
PCI Command 259
Register Access Address
(PCI)
Address
(Local
Bus)
Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 179 05.2001
MBE2P1
MBE2P2
MBE2P3
MBE2P4
MBE2P5
MBE2P6
MBE2P7
R/W
144H
148H
14CH
150H
154H
158H
15CH
22H
24H
26H
28H
2AH
2CH
2EH
0000H
Mailbox Local Bus to
PCI Data Registers 1
through 7 260
MBP2E0 R/W 160H30H0000HMailbox PCI to Local
Bus Command 261
MBP2E1
MBP2E2
MBP2E3
MBP2E4
MBP2E5
MBP2E6
MBP2E7
R/W
164H
168H
16CH
170H
174H
178H
17CH
32H
34H
36H
38H
3AH
3CH
3EH
0000H
Mailbox PCI to Local
Bus Data Regi ste rs 1
through 7 262
Register Access Address
(PCI)
Address
(Local
Bus)
Reset
value Comment Page
PEB 3456 E
Register Description
Data Sheet 180 05.2001
8.1.4 Transmit T1/E1 Framer Registers (Indirect Access)
Note: The transmit framer registers will be accessed via registers TREGSEL and
TDATA as part of the Local Bus direct access register set. Please refer to page
252 for description of TREGSEL and to page 253 for description of TDATA.
Table 8-4 Transmit T1/E1 Framer Registers
Register Access Address Reset
value Comment Page
Control registers
TCMDR R/W 00H0000HCommand 326
TFMR R/W 01H0000HMode 328
TLCR0 R/W 02H0000HLoop Code Register 0 330
TLCR1 R/W 03H0000HLoop Code Register 0 331
TPRBSC R/W 04H001FHPRBS Control 332
TFPR0 R/W 05H0000HFix ed Patte rn Regis ter 333
TFPR1 R/W 06H0000H
TPTSL0 R/W 07HFFFFHPRBS Time slot Re gister 334
TPTSL1 R/W 08HFFFFH
XSP R/W 09H0000HSpare bit Register 335
PEB 3456 E
Register Description
Data Sheet 181 05.2001
8.1.5 Receive T1/E1 Framer Registers (Indirect Access)
Note: The receive framer registers will be accessed via the registers RREGSEL and
RDATA. Please refer to page 254 for description of RREGSEL and to page 255
for description of RDATA.
Table 8-5 Receive T1/E1 Framer Registers
Register Access Address Reset
value Comment Page
Control Registers
RCMDR R/W 00H0000HCommand 336
RFMR R/W 01H0000HMode Register 339
RLCR0 R/W 02H0000HLoop C ode Register 0 344
RLCR1 R/W 03H0000HLoop C ode Register 1 345
RPRBSC R/W 04H001FHPRBS Control 346
PFPR0 R/W 05H0000HFixed Pattern Register 347
RFPR1 R/W 06H0000H
RPTSL0 R/W 07HFFFFHPRBS Time slot Register 348
RPTSL1 R/W 08HFFFFH
IMR R/W 09H0000HIn terru pt Ma sk 349
RFMR1 R/W 0AH0000HMode Register 1 350
PCD R/W 0BH0015HPulse Count Detection 351
PCR R/W 0CH0015HPulse Count Recovery 352
Status registers
FRS R 40H0000HStatus 353
FEC R 41H0000HFraming Error Counter 356
CEC R 42H0000HCRC Error Counter 357
EBC R 43H0000HError ed Block Counter 358
BEC R 44H0000HBit Error Counter 359
PEB 3456 E
Register Description
Data Sheet 182 05.2001
8.1.6 Facility Data Link Registers (Indirect Access)
Note: The FDL registers will be accessed via registers FREGSEL and FDATA.
Table 8-6 Facility Data Link Registers
Register Access Address Reset
value Comment Page
RCR1 R/W 00H0000HReceive Configuration Register 1 360
RCR2 R/W 01H0000HReceive Configuration Register 2 363
RFF R 02H0000HReceive FIFO 3 65
XCR1 R/W 03H0000HTransmit Configuration
Register 1 366
XCR2 R/W 04H0000HTransmit Configuration
Register 2 368
XFF W 05H0000HTransmit FIFO 369
PSR R 06H0000HPort Status 370
HND W 07H0000HHandshake 372
MSK R/W 08H0000HIn terru pt Mask 375
RAL R/W 09H0000HRece ive Ad dress Low 376
RAH R/W 0AH0000HReceive Address High 377
RSAW1 R 0BH0000HReceive Sa Word 1 378
RSAW2 R 0CH0000HReceive Sa Word 2 379
RSAW3 R 0DH0000HReceive Sa Word 3 380
RSAW4 R 0EH0000HReceive Sa Word 4 381
CRCS1 R 0FH0000HCRC Status Counter 1 382
CRCS2 R 10H0000HCRC Status Counter 2 383
XSAW1 R/W 11H0000HTransmit Sa Word 1 384
XSAW2 R/W 12H0000HTransmit Sa Word 2 385
XSAW3 R/W 13H0000HTransmit Sa Word 3 386
VSSM R/W 14H0000HValid SSM Pattern 387
VCRC R/W 15H0000HValid CRC Count Pattern 388
PEB 3456 E
Register Description
Data Sheet 183 05.2001
8.2 Detailed Register Description
8.2.1 PCI Configuration Register
DID/VID
Device ID/Vendor ID
Access : read
Address : 00H
Reset Value : 2108110AH
DID Device ID
The device ID identifies the particular device. It is hardwired to value
2108H.
VID Vendor ID
The vendor ID identifies the manufacturer of the device. It is hardwired
to value 110AH.
31 16
DID(15:0)
15 0
VID(15:0)
PEB 3456 E
Register Description
Data Sheet 184 05.2001
STAT/CMD
Status/Command Register
Access : read/write
Address : 04H
Reset Value : 02A00000H
DPE Detected Parity Error
This bit will be asserted whenever the TE3-CHATT detects a pari ty error.
0 No parity error detected.
1 Parity error detected. This bit will be cleared by writing a ‘1’ to this
bit position.
SSE Signaled System Error
This bit will be asserted whenever the TE3-CHATT asserted SERR. For
system error conditions see b it SE.
0 No syst em error signaled .
1 System error has been signaled. This bit will be cleared by writing
a ‘1’ to this bit position.
RMA Received Master Abort
This bit will set whenever a transaction in which the TE3-CHATT acted
as bus master was terminated with master abort.
0 No master abort detected.
1 Transac tion term inated with mast er abort. Thi s bit w ill be cl eared
by writing a ‘1’ to this bit.
31 30 29 28 27 26 25 24 23 22 21 16
DPE SSE RMA RTA 0 01BDPED 1 0 1 00000
15 8 6 210
0000000SE0 PER 0 0 0BMMS0
PEB 3456 E
Register Description
Data Sheet 185 05.2001
RTA Received Ta rget Abort
This bit will be set whenever a transaction in which the TE3-CHATT
acted as bus master was terminated with target abort.
0 No target abort detected.
1 Transaction terminated with target abort. This bit will be cleared
by writing a ‘1’ to this bit.
DPED Data Parity Error Detected
0 No data parity error detected.
1 The foll owin g three conditio ns are met:
•The bus agent asserted PERR itself or observed PERR
asserted.
•The bus agent acted as bus master for the operation in which the
error occurred.
•The Parity Error Response Bit is set
SE SERR Enable
This bit enables assertion of SERR in case of severe sy stem err ors.
0 Assertion of SERR disabled.
1 Enables report of
•Address parity errors
•Master abort
•Target abort
PER Parity Error Response
This bit enables reporting of parity errors via pin PERR.
0 Assertion of PERR disabled.
1 Enables the assertion of PERR. See also Data Parity Error
Detected.
BM Bus Master
This bit controls a device ability to act as a master on PCI bus.
0 Disables the device from generating PCI accesses.
1 Allows the device to act as bus master.
MS Me mory Space
This bit controls the device response to memory space accesses.
0 Response to memory space accesses disabled.
1 Allows a device to respond to memory space accesses.
PEB 3456 E
Register Description
Data Sheet 186 05.2001
CC/RID
Class Code/Revis ion ID
Access : read
Address : 08H
Reset Value : 02800001H
The class code, consisting of base class, subsystem class and interface class, is used
to identi fy the ge neric f unctio n of the devi ce and , in s ome c ases, a spe cific regist er-leve l
programming interface.
BCL Bas e Clas s
The base class is hardwired to 02H, which identifies this device as a
network contro ller.
SCL Sub Class
The sub class is hardwired to 80H, which together with the base class
identifies this device as ’Other network controller’.
ICL Interface Class
The interfac e cla ss is hardwi red to 00H.
RID Revision ID
The revision ID identifies the current version of the device. It is hardwire d
to 01 H.
31 24 23 16
BCL(7:0) SCL(7:0)
15 8 7 0
ICL(7:0) RID(7:0)
PEB 3456 E
Register Description
Data Sheet 187 05.2001
BIST/Header Type/Latency Timer/Cache Line Size
Access : read/write
Address : 0CH
Reset Value : 00000000H
LT Latency Timer
The val ue of this reg ister time s eight sp ecifies, in units of PC I clocks, th e
value of the latency timer for this PCI bus master.
31 24 23 16
00H00H
15 11 10 8 7 0
LT(7:3) 000B00H
PEB 3456 E
Register Description
Data Sheet 188 05.2001
BAR1
Base Address 1
Access : read/write
Address : 10H
Reset Value : 00000000H
The first base address of the TE3-CHATT is marked as non-prefetchable and can be
relocated anywhere in 32 bit address space of PCI memory. The TE3-CHATT supports
memory accesses only.
BAR Base Address
The bas e a ddre ss w ill be us ed f or de term in ing the add res s s pa ce of th e
TE3-CHATT and to do the mapping of the address space. Since the
device allocates a total of 4 kByte address space BAR(31:12) are
implemented as read/writable.
31 16
BAR(31:12)
15 12 2 1 0
BAR(31:12) 00000000000
B0
PEB 3456 E
Register Description
Data Sheet 189 05.2001
BAR2
Base Address 2
Access : read/write
Address : 14H
Reset Value : 00000000H
The sec ond base address of the TE3 -CHATT i s marked as non-p refetchab le and ca n be
relocated anywhere in 32 bit address space of PCI memory. The TE3-CHATT supports
memory accesses only. All accesses to memory regions defined by BAR2 will be
mapped to the local bus.
BAR Base Address
The bas e a ddre ss w ill be us ed f or de term in ing the add res s s pa ce of th e
memory regions located on the local bus of the TE3-CHATT and to set
the mapping of the address space. The TE3-CHATT can access a total
of 24 kByte address space on the l ocal bus as a bus master.
In those applications where the master functiona lity of TE3-CHATT is n ot
needed the second base address register BAR2 may be disabled using
bit MEM.BAR2 in the PCI user configuration space.
31 16
BAR(31:15)
15 3210
000000000000 00
B0
PEB 3456 E
Register Description
Data Sheet 190 05.2001
SID/SVID
Subsystem ID/Subsystem vendor ID
Access : read
Address : 2CH
Reset Value : 00000000H
SID Subsyst em ID
The subsystem ID uniquely identifies the add-in board or subsystem
where the system resides. The value of SID may be reconfigured after
the reset phase of the system via the SPI interface.
SVID Subsystem Vendor ID
The subsystem vendor ID identifies the vendor of an add-in board or
subsystem. The value may be reconfigured after the reset phase of the
system via the SPI interface.
31 16
SID(15:0)
15 0
SVID(15:0)
PEB 3456 E
Register Description
Data Sheet 191 05.2001
ML/MG/IP/IL
Maximum Latency/Minimum Grant/Interrupt Pin/Interrupt Line
Access : read/write
Address : 3CH
Reset Value : 06020100H
ML Maximum Latenc y
This value specifies how often the device needs to access the PCI bus
in multiples of 1/4 us. The value is hardwired to 06H.
MG Minimum Grant
This value specifies how long of a burst period the device needs,
assuming a clock rate of 33 MHz in multiples of 1/4 us. The value is
hardwired to 02H.
IP Interrupt Pin
The int erru pt pin reg is ter tell s whic h interrupt pin the devi ce uses . Re fer
to section 6.2.4 and to section 2.2.6 of the PCI specification Rev. 2.1.
The value is hardwired to 01H.
IL Interrupt Line
The in terru pt line re gister is used to co mmunic ate inte rrupt li ne routi ng
information.
31 24 23 16
ML(7:0) MG(7:0)
15 8 7 0
IP(7:0) IL(7:0)
PEB 3456 E
Register Description
Data Sheet 192 05.2001
SPI
SPI Access Regis ter
Access : read/write
Address : 40H
Reset Value : 0000001FH
SPIS SPI Start
To start the EEPROM transaction, whic h is defined in the SPI co mmand,
the byte address, and the data field, this bit must be set to ‘1’ by a write
transaction through the PCI interface. After the transaction is finished,
the sta rt bit is deasserted by th e SPI interface controller. This si gnal must
be polled by system software.
SCMD SPI Command
In this register, the S PI command for the ne xt EEPROM transfer mu st be
written before the transaction is started. The following SPI commands
are supported:
01HWRSR Write Status Register
02HWRITE W rite Data to Memory Array
03HREAD Read Data from Memory Array
04HWRDI Reset Write Enable Latch
05HRDSR Read Status Register
06HWREN Set Write Enable Latch
SBA SPI Byte Address
For read and write transaction to the connected EEPROM, the byte
addr ess m us t be w ritten in th is reg is ter b efo re the trans act ion is started.
31 24 23 16
0000000 SPIS SCMD(7:0)
15 8 7 0
SBA(7:0) SWD(7:0)
PEB 3456 E
Register Description
Data Sheet 193 05.2001
SD SPI Data
For the write status register transactions and the write data to memory
array tr ansactio ns, the data, that has to be writ ten to th e EEPROM, m ust
be written to this register before the transaction is started. After a read
status register transaction or read data from memory array transaction
has finished (start bit is deasserted), the byte received from the
EEPROM is available in this register.
PEB 3456 E
Register Description
Data Sheet 194 05.2001
LR
Long Request Register
Access : read/write
Address : 44H
Reset Value : 00000000H
LR Long Request
0 The PCI interface deasserts the REQ signal in parallel with the
assertion of the FRAME signal.
1The REQ signal will be deasserted in parallel with the deasse rtion
of FRAME.
31 16
0000000000000000
15 0
000000000000000LR
PEB 3456 E
Register Description
Data Sheet 195 05.2001
MEM
PCI Memory Command Register
Access : read/write
Address : 48H
Reset Value : 000007E6H
BAR2 Enable Base Address Register 2
Setting this bit enables Base Address Register 2. Per default base
addr ess register t w o is di sa ble d. If an EEPROM is co nne cted to the SPI
interface the value of this bit can be loaded via the EEPROM.
Additionally this bit can set using standard PCI configuration write
commands.
0 Base Address Register 2 is disabled.
1 Base Address Register 2 is enabled.
MW Memory Write Command
The val ue of this regi ste r contains th e w rit e c om man d to be us ed d urin g
initiat or transf ers and is set to memory writ e after reset. The value o f this
register is configurable during setup of the bridge either by loading the
value from EEPROM or by writing from PCI side.
MRL Memory Read Command (Long transfers)
The valu e of this regi ster define s comman d to be used fo r read transfers
which are equal or more than two DWORDs and is set to memory read
line after reset. The value of this register is configurable during run time
of the bridge either by loading the value fr om EEPROM or by writing from
PCI side.
MR Memory Read Command
The valu e of this regi ster define s comman d to be used fo r read transfers
of single DWORDs.The value of this register is configurable during run
31 30 17 16
00000000000000BAR20
15 11 87 43 0
0000 MW(3:0) MRL(3:0) MR(3:0)
PEB 3456 E
Register Description
Data Sheet 196 05.2001
time of the bridge either by loading the value from EEPROM or by
reading or writing from PCI side.
PEB 3456 E
Register Description
Data Sheet 197 05.2001
DEBUG
PCI Debug Support Register
Access : read
Address : 4CH
Reset Value : 00000000H
DSR Debug Support register
The value of this register contains the address of the next initiator
transfer during normal operation. In case of disconnect, retry, master
abort and target abort the register contains the address of the failed
transaction.
31 16
DSR(31:0)
15 0
DSR(31:0)
PEB 3456 E
Register Description
Data Sheet 198 05.2001
8.2.2 PCI Slave Register
CSPEC_CMD
Channel Specification Command Register
Access : read/write
Address : 000H
Reset Value : 00000000H
The channel specification registers are the access registers to the chip internal channel
database. In order to program or reprogram a channel the channel information must be
setup in the channel specification data registers before a channel command can be
given. As soon as the channel command is issued the channel information is copied to
the chip internal channel database and the device is reconfigured for the intended
operation. Since reconfiguration time is dependent on the given command, certain
commands generate acknowledge/fail command interrupt vectors to report status of
configuration.During this time (command has been given and command interrupt) no
further c omma nds ar e allo wed for the same chan nel. Pl ease n ote th at any comma nd for
one channel does not affect operation of any other channel.
For configuration of multiple channels the system software needs to program the
channel data registers only once and then can issue channel commands for multiple
channels without reprogramming the channel data registers.
Note: Debugging of channel information using the commands ’Receive Debug’ or
’Transmit Debug’ requires new programming of channel data registers for further
operation.
For detailed description of register concept and command concept refer to chapter
“Channel Programming / Reprogramming Concept” on Page 163.
31 24 23 16
CMDX(7:0) CMDR(7:0)
15 7 0
00000000CHAN(7:0)
PEB 3456 E
Register Description
Data Sheet 199 05.2001
CMDX Command Transm it
For detailed description of transmit commands and programming
sequences refer to Chapter 6.2.
01HTransmit Init
02HTransmit Off
04HTransmit Abort/Branch
08HTransmit Hold Reset
10HTransmit Debug
20HTransmit Idle
40HTransmit Update
CMDR Comma nd Receive
For detailed description of receive commands and programming
sequences refer to Chapter 6.3.
01HReceive Init
02HRece ive Off
04HReceive Abort/Branch
08HRece ive Hold Reset
10HRece ive Debug
CHAN Channel select
0..255 Selects the channel to be programmed or debugged.
Note: Transmi t init for a channe l must be programmed only afte r reset or a fter a t ransmit
off command, i.e. two transmit init commands for the same channel are not
allowed.
PEB 3456 E
Register Description
Data Sheet 200 05.2001
CSPEC_MODE_REC
Channel Specification Mode Receive Register
Access : read/write
Address : 004H
Reset Value : 00000000H
DEL DEL (Delete) Demap
This bit enables demapping of the control character DEL (7FH ). This bit
is valid in PPP modes only.
0 Disable demapping of control character DEL.
1 Enable demapping of control character DEL.
ACCMX Extended ACCM
In addition to the Channel Specification Receive ACCM Map the user
can s elect four global use r definable characters for charact er demappin g
in PPP modes. Setting one or more of the bits ACCM(3) through
ACCM(0) enables the corresponding character which can be found in
register REC_ACCMX.
0 Disable the selected character in REC_ACCMX for character
demapping.
1 Enable the c orrespo nding ch aracter in regi ster REC_ACCMX for
character demapping.
RFLAG Receive Flag
Used in transparent mode only. The RFLAG constitutes the flag that is
filtered from the received bit stream if enabled via bit TFF.
31 28 27 24 23 16
000 DEL ACCMX(3:0) RFLAG(7:0)
15 14 13 12 11 10 9 8 1 0
0 SFDE TFF INV TMP CRCX CRC
32 CRC
DIS 000000 PMD(1:0)
PEB 3456 E
Register Description
Data Sheet 201 05.2001
SFDE Short/Small Frame Drop Enable
This bit enables either the drop of short frames or the drop of small
frames. This bit is valid in HLDC and PPP modes only.
0 Short Frame Drop. Frames smaller than four bytes payload data
(CRC32) or smaller than two bytes payload data (CRC16) are
dropped. This function is not available if bit CRCX is enabled.
1 Small Frame Drop. Frames (Payload and CRC) which are
smaller or equal to CONF3.MINFL are dropped.
TFF TMA Flag
This bit enabled flag extraction in TMA mode and is available if non of
the bits belonging to this channel is masked.
0 No flag extracti on
1 Enable flag extraction. The flag specified in RFLAG will be
extracted from the received data stream.
INV Bit Inversion
When bit inversion is enabled incoming channel data is inverted before
processed by the protocol machine. E.g. incoming octet 81H will be
recognized as idle flag in HDLC mode.
0No Bit Inversion
1 Bit Inversion
TMP Transparent Mode Packing
This bi t enables the trans parent mod e packing a nd is val id in TMA mod e
only. This feature is applicable if at least one bit in any time slot is
masked.
0 Incoming masked bits are substituted with ‘1’. The non-used
(masked) data bits are substituted by ‘1’s.
1 If subch anneling is used in transpar ent mode (i .e. less than 8 bits
of a time slot are used), the non-used (masked) data bits are
discarded.
CRCX CRC Transfer
This bit enab les the capabili ty to store the CRC checks um of incomi ng
data packets in system memory together with the payload data.
0 The CRC checksum from the incoming data packet will be
removed from the packet and not transferred to the shared
memory.
1 The CRC checksum together with the p ayload data is transferred
to the shared memory.
PEB 3456 E
Register Description
Data Sheet 202 05.2001
CRC32 CRC32 Select
This bit selects the generator polynomial in the receiver. The checksum
of incoming data packets will be compared against CRC16 or CRC32.
CRC Select is valid in HDLC and PPP modes only.
0 Select CRC16 checksum.
1 Select CRC32 checksum.
CRCDIS CRC Check Disable
This bit disables CRC Check in HDLC and PPP protocol modes.
0 CRC check is enabled.
1 CRC check is disabled.
PMD Protocol Machine Mode
These bit fields select the protocol machine mode in receive direction.
00BSelect HDLC operation.
01BSelect Bit synchronous PPP.
10BSelect Byte synchronous PPP.
11BSelect Transparent Mode.
PEB 3456 E
Register Description
Data Sheet 203 05.2001
CSPEC_REC_ACCM
Channel Specification Receive ACCM Map Register
Access : read/write
Address : 008H
Reset Value : 00000000H
Any of the given characters can be selected for character demapping. If a bit is set the
corresponding character is expected to be mapped by the control ESC character and is
removed if received. These bits are valid in octet synchronous PPP modes only.
Note : If t hi s r egi s ter ne e ds to be r e pro g r am med, i t m us t be do ne before ac ce ss in g t he
register CSPEC_MODE_REC.
31 16
1FH1EH1DH1CH1BH1AH19H18H17H16H15H14H13H12H11H10H
15 0
0FH0EH0DH0CH0BH0AH09H08H07H06H05H04H03H02H01H00H
PEB 3456 E
Register Description
Data Sheet 204 05.2001
CSPEC_MODE_XMIT
Channel Specification Mode Transmit Register
Access : read/write
Address : 014H
Reset Value : 00000000H
FNUM Flag number
FNUM denotes the number of flags send between two frames. The flag
number can be updated during transmission with command ’Transmit
Update’.
0 One flag is sent between two frames (shared flag).
1..255 FNUM+1 flags are sent between two frames.
TFLAG Transparent flag
Only valid if transparent mode is selected and if FA is enabled. TFLAG
constitutes the flag that is inserted into the transmit bit stream.
IFTF Interframe Time Fill
This bit determines the interframe time fill in HDLC and PPP modes.
0 Interframe time fill is 7EH.
1 Interframe time fill is FFH.
FA Flag Adjustment
Only valid if transparent mode is selected.
0The value FF
H is sent in sent in all TMA mode exception
conditions.
1 The value specified in TFLAG is sent in all TMA mode exception
conditions (e.g. idle). This bit can be set only when none of the
bits belonging to this channels is masked.
31 24 23 16
FNUM(7:0) TFLAG(7:0)
15 131211 987 43 10
IFTF 0FAINVTMP0 CRC
32 CRC
DIS ACCMX(3:0) DEL 0 PMD(1:0)
PEB 3456 E
Register Description
Data Sheet 205 05.2001
INV Bit Inversion
If bit inversion is enabled outgoing channel data is inverted after
processed by the protocol machine. E.g. a outgoing idle flag is
transmitted as octet 81H in HDLC mode.
0 Disable bit inversion.
1 Enable bit inversion.
TMP Transparent Mode Pack
This bi t enables the trans parent mod e packing a nd is val id in TMA mod e
only. This feature is applicable if at least one bit in any time slot is
masked.
0 If subchanneling is used outgoing masked bits of data octet are
discarded and substituted with ‘1’.
1 If subchanneling is used outgoing masked bits are sent as ‘1’.
The remaining bits of data are sent in the next time slot.
CRC32 CRC 32 Sele ct
This bit selects the generator polynomial in the transmitter. The
checksum of outgoing data packets will be generated according to
CRC16 or CRC32. CRC32 Select is valid in HDLC and PPP modes only.
0 Select CRC16 generation.
1 Select CRC32 generation.
CRCDIS CRC Disable
This bit enab les generation a nd transmission o f a CRC checksum. CRC
disable is valid in HDLC and PPP modes only.
0 CRC generation and transmission is disabled.
1 CRC generation and transmission is enabled.
ACCMX Enable extended ACCM character
The selected bits in bit field ACCMX denote the enabled characters in
XMIT_ACCMX.
In addition to the Channel Specification Transmit ACCM Map the user
can sel ect four global user d efinable characte rs for character mapp ing in
PPP modes . Setting one or more of t he bits ACCM(3) throu gh ACCM (0)
enables the corresponding character which can be found in register
XMIT_ACCMX.
0 Disable the selected character in XMIT_ACCMX for character
mapping.
1 Enable the co rresponding character in register XMIT_ACCMX for
character mapping.
PEB 3456 E
Register Description
Data Sheet 206 05.2001
DEL DEL (Delete) Map Flag
This bit enables mapping of the control character DEL (7FH ). This bit is
valid in PPP modes only.
0 Disable mapping of DEL.
1 Enable mapping of DEL.
PMD Protocol Machine Mode
This bit field selects the protocol machine mode in transmit direction.
00BSelect HDLC operation.
01BSelect Bit synchronous PPP.
10BSelect Byte synchronous PPP.
11BSelect Transparent Mode.
PEB 3456 E
Register Description
Data Sheet 207 05.2001
CSPEC_XMIT_ACCM
Channel Specification Transmit ACCM Map Register
Access : read/write
Address : 018H
Reset Value : 00000000H
Any of the given characters can be selected for character mapping. If a bit is set the
corresponding character will be mapped by the control ESC character. These bits are
valid in octet synchronous PPP modes only.
31 16
1FH1EH1DH1CH1BH1AH19H18H17H16H15H14H13H12H11H10H
15 0
0FH0EH0DH0CH0BH0AH09H08H07H06H05H04H03H02H01H00H
PEB 3456 E
Register Description
Data Sheet 208 05.2001
CSPEC_BUFFER
Channel Specification Buffer Configuration Register
Access : read/write
Address : 020H
Reset Value : 00200000H
TQUEUE Transmit Interrupt Vector Queue
This bit field determines the interrupt queue where channel interrupts
transmit will be stored.
ITBS Individual transmit buffer size
Note: Please note that the interna l architecture is 32 bit wide . Therefore
each buffer location corresponds to four data octets.
The trans mit buffer size configures the nu mber of internal transmit buf fer
locations for a particular channel. Buffer locations will be
allocated on command transmit init and released after command
transmit off.
Note: The sum of transmit forward threshold and transmit refill
threshold must be smaller than the internal buffer size.
TBRTC Transmit Buffer Refill Threshold Code
Note: Please note that the interna l architecture is 32 bit wide . Therefore
each buffer location corresponds to four data octets.
TBRTC is a coding for the transmi t refill th reshold. Ple ase refe r to Table
8-7 for correspondence between code and threshold.
The internal transmit buffer has a programmable number of buffer
locations per channel. When the number of free locations reaches the
transmit buffer refill threshold the internal transmit buffer requests new
data from the data management unit.
31 29 28 16
TQUEUE(2:0) ITBS(12:0)
15 12 11 8 6 4 3 0
TBFTC(3:0) TBRTC(3:0) 0RQUEUE(2:0) RBTC(3:0)
PEB 3456 E
Register Description
Data Sheet 209 05.2001
TBFTC Transmit Buffer Forward Threshold Code
Note: Please note that the interna l architecture is 32 bit wide . Therefore
each buffer location corresponds to four data octets.
TBFTC is a cod ing for the transmit buf fer forward threshold. Please refer
to Table 8-7 for correspond enc e betw e en co de and thresh old .
The transmit buffer forward threshold code determines the number of
buffer locations which must be filled until the protocol machine starts
transmission. Nevertheless the transmit buffer forwards data packets to
the protocol machine as soon as a whole packet or the end of a packet
is stored in the tran sm it buffe r.
RQUEUE Receive Interrupt Queue.
This bit field determines the interrupt queue number where channel
interrupts receive will be stored.
RBTC Receive Buffer Threshold Code
Note: Please note that the interna l architecture is 32 bit wide . Therefore
each buffer location corresponds to four data octets.
RBTC is a coding for the rec ei ve bu ffer thre sh old . Pleas e refer to Table
8-7 for correspondence between code and threshold.
The receive buffer threshold determines the maximum packet size in
DWORD s whi ch will be stor ed in th e intern al rec eive b uffer for a spec ific
channe l. Whe n the p acke t size re aches the re ceive buffe r thresh old or a
packet has been completely received, the packet will be forwarded to
system memory.
Table 8-7 Threshold Codings
Coding Threshold
in DWORDs RBTC TBRTC TBFTC TPBL
0000B1xxxx
0001B4xxxx
0010B8xxxx
0011B12xxxx
0100B16xxxx
0101B24xxxx
0110B32xxxx
0111B40xxxx
1000B48xxxx
PEB 3456 E
Register Description
Data Sheet 210 05.2001
1001B64xxxx
1010B96
Not Valid
x
Not
Valid
1011B128 x
1100B192 x
1101B256 x
1110B384 x
1111B512 x
Coding Threshold
in DWORDs RBTC TBRTC TBFTC TPBL
PEB 3456 E
Register Description
Data Sheet 211 05.2001
CSPEC_FRDA
Channel Specification FRDA Register
Access : read/write
Address : 024H
Reset Value : 00000000H
FRDA First Receive Descriptor Address
This 30-bit pointer contains the start address of the first receive
descriptor. The receive descriptor is read entirely after the first request
of the receive buffer and stored in the on-chip channel database.
Therefore all information in the descriptor pointed to by FRDA must be
valid when the data management unit branches to this descriptor.
The user can specify a new First Receive Descriptor Address using
rece ive abort/bran ch comman d. In this case t he First Rec eive Descrip tor
Address (FRDA ) is us ed as a poi nte r to a new linked lis t. See deta ils on
commands in se ction “Channel Commands” on Page 164.
31 16
FRDA(31:2)
15 210
FRDA(31:2) 0 0
PEB 3456 E
Register Description
Data Sheet 212 05.2001
CSPEC_FTDA
Channel Specification FTDA Register
Access : read/write
Address : 028H
Reset Value : 00000000H
FTDA First Transmit Descriptor Address
This 30-bit pointer contains the start address of the first transmit
descriptor. The transmit descriptor is read entirely after the first request
of the transmit buffer and stored in the on-chip channel database.
Ther efore all inform ation i n the des criptor pointed t o by FTD A must be
valid when the data management unit branches to this descriptor.
The user can s pecify a ne w Firs t Tra ns mit D es cri pto r Add ress u sin g the
’Transmit Abort/Branch’ command. In this case the first transmit
descriptor address (FTDA) is used as a pointer to a new linked list. See
details on commands in Chapter 6.2.
31 16
FTDA(31:2)
15 0
FTDA(31:2) 0 0
PEB 3456 E
Register Description
Data Sheet 213 05.2001
CSPEC_IMASK
Channel Specification Interrupt Vector Mask Register
Access : read/write
Address : 02CH
Reset Value : 00000000H
For each channel or command related interrupt vector an interrupt vector generation
mask is provided. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see Chapter 4.13.1.
The following definition applies:
1 The device will not generate the corresponding interrupt vector, i.e. the
interrupt vector is masked.
0 An interrupt con dition resul ts in gen eration of t he correspon ding interru pt
vector.
Channel Interrupt Vector Transmit
TAB Mask ’Transmit Abort’
HTAB Mask ’Hold Caused Transmit Abort’
UR Mask ’Transmit Underrun’
TFE Mask ’Transmit Frame End’
Command Interrupt Vector Transmit
TTC Mask ’Transmit Command Co mplete’
31 30 28 23 22 16
0TAB0HTAB0000URTFE00000TCC
15141312111098765 32 0
0 RAB RFE HRAB MFL RFOD CRC ILEN RFOP SF IFTC 0SFDSD 0 RCC
PEB 3456 E
Register Description
Data Sheet 214 05.2001
Command Interrupt Vector Receive
RAB Mask ’Receive Abort’
RFE Mask ’Receive Frame End’
HRAB Mask ’Hold Caused Receive Abort’
MFL Mask ’Maximum Frame Length Exceeded’
RFOD Mask ’Receive Frame Overflow DMU’
CRC Mask ’CRC Error’
ILEN Mask ’Invalid Length’
RFOP Mask ’Receive Frame Overflow’
SF Mask ’Short Frame Detected’
IFTC Mask ’Interframe Time-fill Flag’ and ’Interframe Time-fill Idle’
SFD Mask ’Short Frame Dropped’
SD Mask ’Silent Discard’
RCC Mask ’Receive Command Complete’
PEB 3456 E
Register Description
Data Sheet 215 05.2001
CONF1
Configuration Register 1
Access : read/write
Address : 040H
Reset Value : 820000F0H
IIP Initialization in Progress (Read Only)
After rese t (hardware reset o r software reset) th e internal RAM’s are self
initial ized by the TE3-C HATT. Durin g this time (appro x. 250 µs) no other
accesses to the device than reading register CONF1 or FCONF are
allow ed. Th is bi t must be po lled u ntil i t ha s bee n deas serted by th e TE3-
CHATT.
0 Self initialization has finished.
1 Self initialization in progress.
STOP Stop
After reset the TE3-CHATT can be switched to ’Fast Initialization’ mode.
During stop mode internal RAM’s will not be accesses by internal state
machines. This mode is for test purposes only and allows writing or
reading the internal RAM’s.
0 Device is in normal operation. This bit must be set to zero after
chip initialization. See also “Mode Initialization” on Page 170.
1 Device i s in ‘Fast Initializ ation Mode’. This function is used for test
purposes only.
SRST Software Reset
This bit issues a software reset to the TE3-CHATT. During software
reset all interfaces except PCI interface are forced into their idle state.
After soft ware rese t is set the TE3-CHATT starts its self initi alizatio n and
31 25 24 23 21 20 16
IIP 00000STOPSRST0 0 MFLE MFL(12:0)
15 876543210
MFL(12:0) MBIM PBIM RBIM RFIM SFL RBM LBE 0Dev
PEB 3456 E
Register Description
Data Sheet 216 05.2001
IIP will be asserted. When IIP is deasserted system software can reset
SRST to ’0’ to start normal operation again.
0 Normal operation
1 Start software reset.
MFLE Maximum Frame Leng th Check Enable
0 Disable maximum frame length check.
1 Enable maximum frame length check.
MFL Maximum Frame Length
MFL defines the maximum length of incoming data packets. Packets
exceeding the specified length are reported in the status field of the
receive descriptor and if selected in an additional channel interrupt.
MBIM Mailbox Inte rrupt Vector Ma sk
This bit enables or disables mailbox system interrupt vectors generated
by the mailbox.
0 Enable interrupt vector.
1 Disable interrupt vector.
PBIM PCI Bridge Interrupt Vector Mask
This bit enables or disables the ’PCI Access Error’ interrupt vector
generated by the PCI bridge.
0 Enable interrupt vector.
1 Disable interrupt vector.
RBIM Receive Buffer Interrupt Vector Mask
This bit enables or disables system interrupt vectors ’Receive Buffer
Queue Early Warni ng’ and ’ Receive Bu ffer Action Queue Ear ly Warning ’
which are generated by the receive buffer. RBIM is valid only if bit RBM
is set.
0 Enable interrupt vector.
1 Disable interrupt vector.
RFIM Receive Buffer Failed Interrupt Vector Mask
This bit enables or disables the ’Receive Buffer Access Failed’ interrupt
vector.
0 Enable interrupt vector.
1 Disable interrupt vector.
PEB 3456 E
Register Description
Data Sheet 217 05.2001
SFL Short Fram e Leng th
This bit is a global parameter which defines the length of short frames for
all channels.
0 Short frame is defined as a frame containing less than 4 bytes
(CRC16) or less than 6 bytes (CRC32).
1 Short frame is defined as a frame containing less than 2 bytes
(CRC16) or less than 4 bytes (CRC32).
RBM Receive Buffer Monitor
This bit is provided to switch between two monitoring functions of the
rece iv e buff er. Rece iv e buffe r mon ito r functions are av ail ab le in reg is ter
RBTH and RBMON.
0 The minimum free pool count is captured in register RBTH.
1 An interrupt is generated, if the free pool counter falls below the
value progr ammed in register RBTH.
LBE Little/Big Endian Byte Swap
This bit enables the little or big endian mode, which affects the data
structures pointed to by data pointer of receive or transmit descriptor in
system memory. Registers, interrupt vectors or descriptors are not
affected by little/big endian byte swap.
0 Switch data section to little endian mode.
1 Switch data section to big endian mode.
PEB 3456 E
Register Description
Data Sheet 218 05.2001
CONF2
Configuration Register 2
Access : read/write
Address : 044H
Reset Value : 00000000H
SYSQ System Interrupt Queue
SYSQ se ts up the interrupt qu eue where system interrup t vectors w ill be
written to. One system interrupt queue can be selected for system
interrupts.
PORTQ(2:0) Port Interrupt Vector Queue
PORTQ sets up the interrupt queue where port interrupt vectors will be
written to. One interrupt queue can be selected for port interrupts.
TBE Test Breakout Enable
This bit enables the test breakout function. The incoming signals of the
port selected via LPID are switched to the test ports and the incoming
signals on the test port replace the output signals of the selected port.
Setting TBE enable s the selected port (tri-state no longer active) and has
priority over functions selected in register PMR and priority over bit
RSPEN. The port may be disabled using register REN and TEN to
disable internal processing while test function is active.
0 Disable test function.
1 Enable test function.
RSPEN Receive Synchronization Pulse Enable
0 The selected transmit clock of port zero is visible on pin TCLKO.
This function is available when port zero is operated in
unchannelized mode.
31 30 28 27 26 24 23 22 21 20 16
0 SYSQ(2:0) 0 PORTQ(2:0) TBE RSPEN SPA(4:0)
15 13 12 8 7 0
RCL 00 LPID(4:0) LCID(7:0)
PEB 3456 E
Register Description
Data Sheet 219 05.2001
1 The internally generated synchronization pulse of input port
CONF2.SPA is switched to pin RSPO for test purposes.
SPA Synchronization Pulse Access
This bit field selects one framer 0..27 whose synchronization pulse can
be externally monitored. Only valid if RSPEN is set.
RCL Remote Channel Loop
The remote channel loop switches incoming data of one channel to the
outgoin g bit stream of th e same chan nel. The bit rate of the receiver and
the transmitter must be the same. The channel to be looped can be
selected using bit field LCID. One channel at a time can be looped.
0 Disable remote channel loop.
1 Enable remote channel loop.
LPID Port Identifier
This b it field s elects the port whi ch shal l be switc hed to th e test po rt. See
also bit CONF1.T BE.
LCID Loop C hannel Identifier
This bit field selects the channel which shall be looped through the
internal loop buffer.
PEB 3456 E
Register Description
Data Sheet 220 05.2001
CONF3
Configuration Register 3
Access : read/write
Address : 048H
Reset Value : 00090000H
TPBL Transmit Packet Burst Length
This bit field is a coding for the maximum burst length on PCI bus, when
data ma nagement unit fe tches transmit packets. Please refer to Table 8-
7 "Threshold Codings" on Page 209 for correspondence between
code and maximum burst length.
MINFL Minimum Frame Length
Only valid for those chan nel which hav e bit CSPEC_MODE_REC.SFDE
set. MINFL sets the minimum frame length in bytes (payload bytes and
CRC bytes) for frames which will be forwarded to system memory. If
enable d t he receiv e buf fer will dr op fram es w hich are s mall er or e qual to
the pr ogrammed value M INFL to avoid wa sting of PCI bandw idth in case
of error conditio ns . The sm al l fram e c he ck is dis ab led , if M IN FL is set to
zero.
Note: Since the receive packets will be dropped inside the receive
buffer, the receive packet threshold CSPEC_BUFFER.RTC has
to be greater than MINFL/4 in order to work properly.
31 19 16
000000000000 TPBL(3:0)
15 13 8 0
00 MINFL(5:0) 00000000
PEB 3456 E
Register Description
Data Sheet 221 05.2001
RBAFT
Receive Buffer Access Failed Interrupt Threshold Register
Access : read/write
Address : 04CH
Reset Value : 00000000H
RBAFT Receive Buffer Access Failed Interrupt Threshold
This register sets the threshold for the ’Receive Buffer Access Failed’
interrupt vector.
31 16
RBAFT(31:0)
15 0
RBAFT(31:0)
PEB 3456 E
Register Description
Data Sheet 222 05.2001
SFDT
Small Frame Dropped Interrupt Threshold Register
Access : read/write
Address : 050H
Reset Value : 00000000H
SFDIT Small Frame Dropped Interrupt Vector Threshold
The programmed threshold defines the threshold for the ’Small Frame
Dropped’ interrupt vector. As soon as the internal number of dropped,
small frames reaches the programmed value a channel interrupt vector
with bit SFD set will be generated. The actual value of dropped frames
can be read using register SFDC. The value is applied to all 256
channels.
31 16
SFDIT(31:0)
15 0
SFDIT(31:0)
PEB 3456 E
Register Description
Data Sheet 223 05.2001
PMIAR
Port Mode Indirect Access Register
Access : read/write
Address : 060H
Reset Value : 00000000H
Note: This register is an indirect access register which must be programmed before
accessing the register PMR.
AIP Auto Increm ent Port
This bit enables the auto increment function o f bit field PORT. Each read/
write access to register PMR increments PORT. This allows to program
multiple, consecutive ports without accessing PMIAR again.
0 Disable auto increment function.
1 Enable auto increment function.
PORT Port Select
This bi t field selects the port number, wh ich can be acc essed via regis ter
PMR.
0..27 Port Number
31 23
00000000AIP0000000
15 40
00000000000PORT(4:0)
PEB 3456 E
Register Description
Data Sheet 224 05.2001
PMR
Port Mode Register
Access : read/write
Address : 064H
Reset Value : 0104C000H
Note: Effected port is selected via register PMIAR. All settings in this register affect the
selected port only.
PCM Sel ect Port Mode
This bit field selects the port mode.
0000BT1 mode (1.544 MHz)
1000BE1 mode (2.048 MHz)
1111BUnchannelized mode
RIM Receive Synchronization Error Interrupt Vector Mask
This bit disables generation of the port interrupt vector receive. See
“Port Interrupts” on Page 128 for description of interrupt vectors.
0 Enable
1Disable
TIM Transmit Synchronization Error Interrupt Vector Mask
This bit disables generation of the port interrupt vector transmit. See
“Port Interrupts” on Page 128 for description of interrupt vectors.
0 Enable
1Disable
31 28 24 22 18 16
PCM(3:0) 0 0 0000
B0 0 0000
B
15141312111098765 0
RIM TIM 0 TXR 0 0 CTFSD LT RLL RPL LPL 00000
PEB 3456 E
Register Description
Data Sheet 225 05.2001
TXR Transmit Data Rising
This bit defines the edge the common transmit frame synchronization
pulse CTFS is sampled on with respect to the common transmit clock
CTCLK.
0 CTFS is sampled on the rising edge of CTCLK.
1 CTFS is sampled on the falling edge of CTCLK.
CTFSD Common transmit fram e synchroni zati on disa ble
0 Bit 0 of transmit data is synchronized to CTFS.
1 Synchronization of data to CTFS is disabled.
LT Loop ed Timing
This bit selects the transmit clock in TE3-CHATT. Per default the
transmit clock of the selected tributary is the common transmit clock. If
set to ‘1’ t he corres ponding tributary i s swit ched in to looped timed m ode.
0 Select norma l operation mode .
1 Select looped timing mode.
RLL Remote Line Loop
This bit enables the remote line loop of the selected port.
0 Disable remote line loop.
1 Enable remote line loop.
RPL Remote Payload Loop
This bit enables the remote payload loop of the selected port.
0 Disable remote payload loop.
1 Enable remote payload loop.
LPL Local Port Loop
This bi t enables the lo cal port loop on the selected port. When loca l loops
are closed, the corresponding transmit clock and the synchronization
pulse is switched to the receive port.
0 Disable local port loop.
1 Enable local port loop.
PEB 3456 E
Register Description
Data Sheet 226 05.2001
REN
Receive Enable Reg ister
Access : read/write
Address : 068H
Reset Value : 00000000H
REN Receive E nable
Setting a bit in this bit field enables the receive function of the selected
port. After res et all po rts ar e disabled and thus all inc oming rec eive da ta
is discarded. While a port is disabled communication between port
handler, time slot assigner and synchronization function is disabled. A
port sho uld be ena bled if it i s correctl y configur ed using r egisters PM IAR
and PMR.
0 Disable receive port.
1 Enable receive port.
31 27 16
0000REN(27:0)
15 0
REN(27:0)
PEB 3456 E
Register Description
Data Sheet 227 05.2001
TEN
Transmit Enab le Register
Access : read/write
Address : 06CH
Reset Value : 00000000H
TEN Transmit Enable
This bit field enables the transmit function of the se lected port. After reset
all transmit ports are disabled and thus all TD lines are set to tri-state.
While a port is reset the communication between port handler, time slot
assigner and synchronization function is disabled. After the port mode
has been selected using register PMIAR and PMR a transmit port can
be enabled.
31 27 16
0000TEN(27:0)
15 0
TEN(27:0)
PEB 3456 E
Register Description
Data Sheet 228 05.2001
TSAIA
Time slot Assig nme nt Indir ect Acce ss Regis ter
Access : read/write
Address : 070H
Reset Value : 00000000H
DIR Direction
This bit select the direction for which programming is valid.
0 Program time slots in receive direction.
1 Program time slots in transmit direction.
AIT Auto Increment Time slot
This bit enables the auto increment function of bit field TSNUM. Each
read/write access to register TSAD increments TSNUM. This allows to
program multiple, consecutive time slots without accessing TSAIA
again.
0 Disable auto increment function.
1 Enable auto increment function.
PORT Port Select
This bi t field selects the port number, wh ich can be acc essed via regis ter
TSAIA.
0..27 Port number
31 23 16
DIR 0000000AIT0000000
15 12 8 4 0
PORT(4:0) 0TSNUM(4:0)
PEB 3456 E
Register Description
Data Sheet 229 05.2001
TSNUM Time Slot Number
This bit field selects the time slots, which can be accessed via register
TSAIA.
Valid time slot numbers are:
0..23 T1, Unchannelized
0..31 E1
PEB 3456 E
Register Description
Data Sheet 230 05.2001
TSAD
Time slot Assig nme nt Data Register
Access : read/write
Address : 074H
Reset Value : 02000000H
Note: The ti me slot as signme nt data regis ter assig ns a chan nel and a m ask to a sp ecific
port/time slot combinati on. The related port/time slo t must be chosen by accessing
TSAIA.
The time slot assignment has to be done before a specific channel is configured for
operatio n. Af ter ope ration the po rt/time slot assig nmen t of a part icula r chan nel ha s to b e
set to inhibit.
INHIBIT Inhibit Time slot
This bit disabled processing of the selected port/time slot.
0 The time slot is enabled.
1 The time slot is disabled. In receive direction incoming octets are
discard ed. In tran smit directi on the oc tet of this time slot and p ort
is set to FFH.
TMA1ST TMA First
This bit marks the first time slot belonging to a TMA superchannel for
TMA synchronization. Receiver starts processing data on the marked
time s lot. In transm it direction d ata transmis sion is st arted on the ma rked
time slot. If TMA channel uses only one time slot this bit must be set.
CHAN Channel Number
This bit field selects the channel number which will be associated to the
port and time slot which is select ed in register TSAIA.
31 25 24
000000 INHI
BIT TMA
1ST 00000000
15 8 7 0
CHAN(7:0) MASK(7:0)
PEB 3456 E
Register Description
Data Sheet 231 05.2001
MASK Mask Bits
Setting a bit in this bit field selects the corresponding bit in a time slot
which is enabled for operation.
0 In receiv e direction the c orresponding bit is disca rded. In transm it
direction the bit is sent as ‘1’.
1 In receive direction the corresponding bit is forwarded to the
protocol machine (via time slot assigner). In transmit direction
data on the serial line is gen erat ed by the prot oc ol mac hi ne.
PEB 3456 E
Register Description
Data Sheet 232 05.2001
REC_ACCMX
Receive Extended ACCM Map Register
Access : read/write
Address : 080H
Reset Value : 00000000H
This register is only used by channels operated in octet synchronous PPP mode. A
character written to this register is mapped with a control escape sequence, if the
corresponding enable flag is set in the corresponding bit
CSPEC_MODE_REC.ACCMX(3:0).
31 24 23 16
CHAR3(7:0) CHAR2(7:0)
15 8 7 0
CHAR1(7:0) CHAR0(7:0)
PEB 3456 E
Register Description
Data Sheet 233 05.2001
RBAFC
Receive Buffer Access Failed Counter Register
Access : read
Address : 084H
Reset Value : 00000000H
RBAFC Receive Buffer Access Failed Counter
The read value of this register defines the number of pac kets which hav e
been discarded due to inaccessibility of the internal receive buffer. A
read access resets the counter to zero.
31 16
RBAFC(31:0)
15 0
RBAFC(31:0)
PEB 3456 E
Register Description
Data Sheet 234 05.2001
SFDIA
Small Frame Dropped Indirect Access Register
Access : read/write
Address : 088H
Reset Value : 00000000H
AIC Auto Increment Channel
This bit enables the auto increment function of bit field CHAN. Each
read /write acces s to regis ter SFD increm ents CH AN by two. Th is allow s
to read the status of multiple channels without accessing SFDIA again.
0 Disable auto increment function.
1 Enable auto increment function.
CLR Clear
This bit enables the counter mode on reads to register SFDC.
0 Read of register SFDC does not affect the small frame dropped
counter.
1 After reading r egister SF DC the value o f the small frame dro pped
counter will be reset to zero.
CHAN Channel Number
This bit field selects the channel, whose status can be read in register
SFDC.
0..255 Channel numb er
31 23 22 16
00000000AICCLR000000
15 7 0
00000000CHAN(7:0)
PEB 3456 E
Register Description
Data Sheet 235 05.2001
SFDC
Small Frame Dropped Counter Register
Access : read
Address : 08CH
Reset Value : 00000000H
These both bit fields show the current value of the small frame dropped counter of the
channel N and N+1 selected via SFDIA.CHAN. Dependent on bit field SFDIA.CLR the
counter will be cleared after they are read.
SFDC++ Small Frame Dropped Counter for Channel N+1
The numbe r of dropped , sma ll fram es of chann el SFD IA.CH AN +1.
SFDC Small Frame Dropped Counter
The numbe r of dropped , sma ll frames of chann el SFD IA.CH AN .
31 16
SFDC++(15:0)
15 0
SFDC(15:0)
PEB 3456 E
Register Description
Data Sheet 236 05.2001
XMIT_ACCMX
Transmit Extended ACCM Map
Access : read/write
Address : 090H
Reset Value : 00000000H
This register is only used by a channel in octet synchronous PPP mode. A character
written to this register will be mapped with a Control Escape sequence, if the
corresponding enable flag is set in the CSPEC_MODE_XMIT register (ACCMX(3:0)).
31 24 23 16
CHAR3(7:0) CHAR2(7:0)
15 8 7 0
CHAR1(7:0) CHAR0(7:0)
PEB 3456 E
Register Description
Data Sheet 237 05.2001
RBMON
Receive Buffer Monitor Indirect Access Register
Access : read
Address : 0B0H
Reset Value : 02000BFFH
RBAQC Receive Buffer Action Queue Free Count
The value of this register determines the actual number of free actions
inside the receive buffer.
RBFPC Receive Buffer Free Pool Count
The value of this register determines the actual number of free buffer
locations inside the receive buffer. After reset a total number of 3072
receive buffer locations, which equals 12kB receive buffer, is available.
31 25 16
000000 RBAQC(9:0)
15 11 0
0000 RBFPC(11:0)
PEB 3456 E
Register Description
Data Sheet 238 05.2001
RBTH
Receive Buffer Threshold Register
Access : read/write
Address : 0B4H
Reset Value : 02000001H
RBAQTH Receive Buffer Action Queue Free Pool Threshold
Function of RBAQTH is dependent on bit CONF1.RBM.
CONF1.RBM = ’0’:
The minimum value of RBMON.RBAQC, which occurred since the last
reset or the last read of this register, is captures in here.
CONF1.RBM = ’1’:
A ’Receive Buffer Action Queue Early Warning’ interrupt will be
generated, if the receive buffer action queue free pool drops below the
value programmed in bit field RBAQTH. The value to be programmed
must be in the range of 000H to 1FFH.
RBTH Receive Buffer Free Pool Threshold
Function of RBTH is dependent on CONF1.RBM.
CONF1.RBM = ’0’:
The minimum value of RBMON.RBFP, which occurred since the last
reset or the last read of this register, is captured in here.
CONF1.RBM = ’1’:
A ’Receive Buffer Queue Early Warning’ interrupt vector will be
generated, if the receive buffer free pool drops below the value
programmed in bit field RBTH.
31 25 16
000000 RBAQTH(9:0)
15 11 0
0000RBTH(11:0)
PEB 3456 E
Register Description
Data Sheet 239 05.2001
IQIA
Interrupt Queue Indirect Access Regi ster
Access : read/write
Address : 0E0H
Reset Value : 00000000H
DBG Debug
This bit selects the debug mode of the interru pt controller. When DEBUG
is set, th e actual values o f interrupt que ue base address, i nterrupt queue
length and high priority interrupt queue mask of queue Q are copied to
registe r IQBA, IQL and IQMASK. The va lue ca n be read wit h a foll owing
access to these registers.
Note: Setting DEBUG is only allowed, if neither SIQBA, SIQL and SIQM
are set.
0 No operation
1 Enable debug mode.
SIQM Set High Priority Interrupt Queue Mask
This bit field enables setup of the high priority interrupt queue mask of
queue Q. Th e v al ue to be programm ed has t o b e c on f ig ured v ia reg is ter
IQMASK prior to a write access to this bit.
0 No operation
1 Set high priority mask.
31 19 18 17 16
000000000000 DBG SIQM SIQL SIQBA
15 30
000000000000Q(3:0)
PEB 3456 E
Register Description
Data Sheet 240 05.2001
SIQL Set Interrupt Queue Length
This bit fi eld enables set up of the interrupt queu e length of queue Q. The
value to be programmed has to be configured via register IQL prior to a
write acces s to this bit.
0 No operation
1 Set interrupt queue length.
SIQBA Set Interrupt Queue Base address
This b it field enables setup of the in terrupt qu eue base address of queu e
Q. The value to be programmed has to be configured via register IQBA
prior to a write access to this bit.
0 No operation
1 Update interrupt queue base address with value programmed in
register IQBA.
Q Interrupt Queue Number
This bit field determines the interrupt queue number for which
prog rammi ng is vali d. The firs t eig ht (0..7 ) interru pt que ue s are use d for
channe l, port an d system i nterrupt v ectors, w hile the la st in terrupt queue
(8) is used for command in terrupt vectors. Interrupt queue numb er seven
is per default the high priority interrupt queue.
System software may setup the interrupt queue high priority mask, the
interrupt queue length and the interrupt queue base address
simultaneously by setting SIQL, SIQBA and SIQM.
The command interrupt queue has a fixed length of two times 256
DWORDs, that is one DWORD for each interrupt vector.
It is po ssible t o setup th e interrupt q ueue hig h priority mas k, the in terrupt
queue length and the interrupt queue base address concurrently by
setting SIQBA, SIQL and SIQM to ’1’.
Note: Programming of interrupt queue length or interrupt queue high
priority mask is not valid for the command interrupt queue
(interrupt queue 8).
Note: Programming of interru pt que ue hig h prio rity m ask is not v alid for
the high priority interrupt queue (interrupt queue 7).
0..8 Interrupt Queue
PEB 3456 E
Register Description
Data Sheet 241 05.2001
IQBA
Interrupt Queue Base Address Register
Access : read/write
Address : 0E4H
Reset Value : 00000000H
IQBA Interrupt Queue Base Address
The in terrupt que ue base a ddress registe r assigns a base address to the
eight c hannel interru pt queues an d the command interrupt queu e. To set
a new base address for a specific queue, system software must first
program IQBA. Afterwards the value is released by selecting the
associa ted queue via bi t fi eld IQIA.Q an d s ett ing of bit IQI A.SIQ BA. Th e
interrup t queu e bas e add ress has t o be DWORD align ed. Wh eneve r the
base address of a particular interrupt queue is modified, the next
interrupt vector written to that queue is stored in the first location of the
queue.
31 16
IQBA(31:2)
15 210
IQBA(31:2) 0 0
PEB 3456 E
Register Description
Data Sheet 242 05.2001
IQL
Interrupt Queue Length Register
Access : read/write
Address : 0E8H
Reset Value : 00000000H
IQL Interrupt Queue Length
This bit field assigns a interrupt queue length to the eight channel
interrupt queues. To set the interrupt queue length of a specific queue,
system software must first program IQL. Afterwards the value is released
by selecting the associated queue via bit field IQIA.Q and setting of bit
IQIA.SIQL. IQL specifies the interrupt queue length L (number of
DWORDs) in the shared memory with
L=(IQL+1)*16 (maximum of 4092 DWORDs).
Note: IQL = 255 equals a queue length of 1 DWORD.
Whenev er the leng th of a particu lar interrupt qu eue is mo dified , the next
interrupt vector written to that queue is stored in the first location of the
queue.
31 16
0000000000000000
15 7 0
00000000IQL(7:0)
PEB 3456 E
Register Description
Data Sheet 243 05.2001
IQMASK
Interrupt Queue High Priority Mask
Access : read/write
Address : 0ECH
Reset Value : 00000000H
For a description of the interrupt concept and interrupt vectors see Chapter 4.13.1.
In normal operation each channel interrupt vector is written to the interrupt queue
associated with a specific channel, that is interrupt queue 0 to 7. The interrupt queue
mask provid es the functi onality to forwar d selected c hannel interr upts to the high pri ority
interr upt queue , which is ha rdwired as qu eue 7.The refo re a mask can be se t for each of
the interru pt queues, w hi ch spe ci fies the cha nne l int errup t ve cto r to be forward ed to the
high priority interrupt queue. To set the IQMASK for interrupt queues 0 to 6, system
software must first program IQMASK. Afterwards the mask is released by selecting the
affected interrupt queue via bit field IQIA.Q and setting of bit SIQM.
Those interrupt vectors which have an interrupt bit set, that is also masked in this high
priority mask are forwarded to the high priority interrupt queue instead of the regular
interrupt queue associated with a specific channel.
If a channel interrupt vector has at least one interrupt bit set, that is also masked in the
high priority mask, the interrupt vector will be forwarded to the high priority interrupt
queue.
In case that a channel interrupt vector has at least one bit set, that is not masked in the
high priority mask, the interrupt vector is queued into the regular interrupt queue
associated with the corresponding channel.
31 30 28 23 22 16
THI TAB 0HTAB0000URTFE000000
15141312111098765 32 0
RHI RAB RFE HRAB MFL RF0D CRC ILEN RFOP SF IFTC 0SFDSD 0 0
PEB 3456 E
Register Description
Data Sheet 244 05.2001
GISTA/GIACK
Interrupt Status/Interrupt Acknowledge Register
Access : read/write
Address : 0F0H
Reset Value : 00000000H
Depending on the corresponding bits in register GMASK, an interrupt indication in this
register will be flagged at pin INTA. If an interrupt bit is masked (set to ’1’) in register
GMASK, sy stem softw are has t o poll thi s register in order to get status information of the
disabled interrupt bit.
INTOF Interrupt Overflow
This bi t indicate s that inte rrupt in formation has been lost due to o verload
conditions of the internal interrupt controller. This interrupt indicates a
severe system problem. If this bit is set and INTOF is not masked in
register GMASK, the interrupt pin INTA will be asserted. INTOF is
cleared, when an ’1’ is written to this bit.
0 No interrup t overf low.
1 Interrupt overflow. The interrupt will be cleared by writing a ‘1’ to
the corresponding bit.
LBI Local Bus Interrup t
The T E3-CHATT sup ports bridg ing of inte rrupts fr om the loc al bus to the
PCI bus . In this appli cation th e pi n LINT is used a s an in put and as soo n
31 17 16
INTOF 0000000000000LBIIF
15 876543210
0000000 Q8Q7Q6Q5Q4Q3Q2Q1Q0
PEB 3456 E
Register Description
Data Sheet 245 05.2001
as LINT changes from an inactive to an active state the interrupt pin
INTA will be asserted.
Note : This bit does not clea r by wr iting a ’1’. Th is bit is set as long as
the interrupt pin LINT is asserted.
0LINT
not asserted.
1LINT asserted.
IF Interrupt FIFO
This bit indicates that there is an interrupt vector stored in the internal
interrupt FIFO. The IF interrupt is available if the interrupt pin LINT is
switche d t o i npu t m ode (IN T CTR L.ID = ’ 1’) and w he n th e i nte rrup t m ask
GMASK.IF is set to ’0’.
Note: This bit does not cl ear by writin g a ’1’. This bit is set as lo ng as an
interrupt vector is stored in the interrupt FIFO.
0 No Interrupt vector in interrupt FIFO.
1 Interrupt vector stored in internal interrupt FIFO.
Q8..Q0 Interrupt Queue 8..0
On reads each bit flags one or more interrupt vectors that have been
written to the corresponding interrupt queue. If one of the bits is set and
the sam e bit is not masked in registe r GMASK, the interrupt pi n INTA will
be asserted. A bit is cleared, when an ’1’ is written to the specific bit.
0 No interrupt vector written.
1 Read: One or more interrupt vectors have been written to
inter rupt que ue.
Write: Clear bit
PEB 3456 E
Register Description
Data Sheet 246 05.2001
GMASK
Global Interrupt Mask Register
Access : read/write
Address : 0F4H
Reset Value : FFFFFFFFH
Each bit in th is register m ask the inter rupts, which are flagged in regist er GISTA/GIAC K.
INTOF Mask Interrupt Overflow
This bit masks the interrupt overflow interrupt.
LINT Local Bus Interrupt
This bit masks bridging of interrupt from the local bus to the PCI bus.
0 Bridging of LIN T to INTA enable d.
1 Bridging of LIN T to INTA disabled.
IF Interrupt FIFO
This bit masks the internal mailbox/layer one interrupt FIFO.
0 IF interrupt is enabled.
1 IF interrupt is disabled.
Q8..Q0 Mask Interrupt Queue 8..0
Each of the bits Q8..Q0 mas ks an interrupt, whic h will be asserte d, when
an inte rrupt vector has been writ ten to the corre sponding in terrupt queue
8..0. Masking an interrupt does not suppress generation of the interrupt
vector itself.
0 Enable interrupt, when interrupt vector has been written to
selected interrupt queue.
1 Mask (Disable) interrupt, when interrupt vector has been written
to selected interrupt queue.
31 17 16
INTOF 1111111111111LINTIF
15 876543210
1111111 Q8Q7Q6Q5Q4Q3Q2Q1Q0
PEB 3456 E
Register Description
Data Sheet 247 05.2001
8.9.2 PCI and Local Bus Slave Register Set
FCONF
Framer and FDL Configuration Register
Access : read/write
Address : 100H (PCI), 00H (Local Bus)
Reset Value : 8080H
IIP Initialization in Progress (Read Only)
After rese t (hardware reset o r software reset) th e internal RAM’s are self
initial ized by the TE3-C HATT. Durin g this time (appro x. 250 µs) no other
accesses to the device than reading register CONF1 or FCONF are
allow ed. Th is bi t must be po lled u ntil i t ha s bee n deas serted by th e TE3-
CHATT.
0 Self initialization has finished.
1 Self initialization in progress.
MBID Mailb ox Inte rrupt Vector Disa bl e
0 Enable generation of mailbox interrupt vectors. As soon as
system software on PCI side writes to register MBP2E0 an
inter rupt vect or indicati ng a mai lbox in terrupt w ill be for warde d to
the internal interrupt FIFO and can be read by the local CPU.
1 Disable generation of mailbox interrupt vectors.
WSE Wait State Enable
This bit enables the wait state controlled master mode.
0LRDY
(Intel), LDTACK (Motorola) controlled bus mode.
1 Wait state controlled bus mode. Wait states are defined in
register MTIMER.WS.
1514 76543210
IIP 0 000000 MBID WSE BSD P28 P18 P08 LAE LME
PEB 3456 E
Register Description
Data Sheet 248 05.2001
BSD Byte Swap Disable
This b it disab les b yte s wapping o n 16-bit transfers wh en the l oca l bus i s
operated in Motorola master mode.
0 Enable byte swap.
1 Disable byte swap.
P28..P08 Switch Page 2..0 to 8-bit mode
The TE3-CHATT maps three pages of 8 kByte each to the local bus in
master mode . Each pa ge ac cess ed fro m the PCI si de ca n b e ma pped i n
8-bit mode or 16-bit mode. In 8-bit mode the data bits LD(15:8) are
unused.
0 Set page mode to 16-bit mode.
1 Set page mode to 8-bit mode.
LAE Local Bus Arbiter Enable
This b it e nab les th e local bus ar bite r. In cas e th at t he loc al bus a r bit er i s
enabled the TE3-CHATT will arbitrate for each bus access on the local
bus using the arbitration signals. If local bus arbiter functionality is
disabled it assumes bus ownership and does not arbitrate for the local
bus.
0 Disable the local bus arbiter.
1 Enable the local bus arbiter.
LME Loca l Bus M aster Enable
This bit enables the local bus master functionality. As long as the local
bus master functionality is disabled the TE3-CHATT can be accessed
from the local bus as slave only.
0 Disable Local Bus Master.
1 Enable Local Bus Master.
PEB 3456 E
Register Description
Data Sheet 249 05.2001
MTIMER
Master Local Bus Timer Register
Access : read/write
Address : 104H (PCI), 02H (Local Bus)
Reset Value : 0000H
TIMER Local Bus Latenc y Timer
TIMER*16 determines the time in clock cycles the TE3-CHATT holds the
local bus as bus master after it was granted the bus. It holds the bus as
long as the first transaction is in progress or the latency timer is counting.
In case that the TE3-CHATT shall release the bus after it each
transaction the latency TIMER value must be set to zero.
WS Wait State Timer
The value of this register determines the time in clock cycles the TE3-
CHAT T asse rts LRD , LWR (In tel M ode) res pecti vely LD S (Moto rola Bu s
Mode). See also FCONF.WS E.
15 43 0
TIMER(15:4) WS(3:0)
PEB 3456 E
Register Description
Data Sheet 250 05.2001
INTCTRL
Interrupt Control Register
Access : read/write
Address : 108H (PCI), 04H (Local Bus)
Reset Value : 0001H
ID Interrupt Direction
This pin determines the direction of the interrupt pin LINT.
0LINT
is output.
1LINT is input.
IP Interrupt Polarity
0LINT
is active low.
1LINT is active high.
CLIQ Clear Interrupt Queue
Setting this bit will clear the internal interrupt FIFO. This effects all
interrupts of facility data link, framer and mailbox interrupts to the local
bus.
0 No action
1 Clear interrupt FIFO.
IM Interrupt Mask
This bi t masks ass ertion of the p in LINT when int errupts are st ored in the
internal interrupt FIFO. If the interrupt direction bit is set to output mode
interrupt are flagged at interrupt pin LINT. If the interrupt direction is set
to input mode interrupts are flagged at pin INTA.
0 Enable assertion of interrupt pin LINT.
1 Disable assertion of interrupt pin LINT.
15 3210
000000000000IDIPCLIQIM
PEB 3456 E
Register Description
Data Sheet 251 05.2001
INTFIFO
Interrupt FIFO
Access : read
Address : 10CH (PCI), 06H (Local Bus)
Reset Value : FFFFH
IV Interrupt Vector
After the TE3-CHATT asserted interrupt pin LINT on the local bus side,
this bi t fiel d c ontains an interrupt ve ctor containing i nte rrupt informa tion.
Please refer to section “Layer One Interrupts” on Page 137 for a
detailed description of interrupt vector contents.
15 0
IV(15:0)
PEB 3456 E
Register Description
Data Sheet 252 05.2001
TREGSEL
Transmit T1/E1 Framer Port & Regi ster Select
Access : read/write
Address : 110H (PCI), 08H (Local Bus)
Reset Value : 0000H
Note: This register is an indirect access register, which must be programmed before
accessing the register TDATA.
AIP Auto Increm ent Port
This bit enables the auto increment function o f bit field PORT. Each read/
write access to register TDATA increments PORT. This allows to
prog ram multiple, co nsecutive p orts without ac cessing TREG SEL again.
0 Disable auto increment function.
1 Enable auto increment function.
PORT Port Select
This bi t field selects the port number, wh ich can be acc essed via regis ter
TDATA.
0..27 Port Number.
AIA Auto Increm ent Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register TDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing TREGSEL
again.
0 Disable auto increment function.
1 Enable auto increment function.
ADDR Register Address
This bit field selects the register address of the transmit framer, which
can be accessed via register TDATA.
0H..FHRegis ter add res s.
15 14 12 8 7 3 0
0AIP0PORT(4:0)AIA000 ADDR(3:0)
PEB 3456 E
Register Description
Data Sheet 253 05.2001
TDATA
Transmit T1/E1 Framer Data Register
Access : read/write
Address : 114H (PCI), 0AH (Local Bus)
Reset Value : 0000H
Note: Effected port and address is selected via register TREGSEL. All settings in this
register affect the selected port only.
DATA Data register
The transmit framer data register assigns a value to the transmit framer
of port TREGSEL.PORT and the register selected via bit field
TREGSEL.ADDR. Read/write operation depends on the selected
register.
15 0
DATA(15:0)
PEB 3456 E
Register Description
Data Sheet 254 05.2001
RREGSEL
Receive T1/E1 Framer Port & Register Select
Access : read/write
Address : 118H (PCI), 0CH (Local Bus)
Reset Value : 0000H
Note: This register is an indirect access register, which must be programmed before
accessing the register RDATA.
AIP Auto Increm ent Port
This bit enables the auto increment function o f bit field PORT. Each read/
write access to register RDATA increments PORT. This allows to
program multi ple, consecutive ports without accessing RREGSEL again.
0 Disable auto increment function.
1 Enable auto increment function.
PORT Port Select
This bi t field selects the port number, wh ich can be acc essed via regis ter
RDATA.
0..27 Port Number.
AIA Auto Increm ent Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register RDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing RREGSEL
again.
0 Disable auto increment function.
1 Enable auto increment function.
ADDR Register Address
This bit field selects the register address of the transmit framer, which
can be accessed via register RDATA.
0H..7FHRegister address.
15 14 12 8 7 6 0
0AIP0 PORT(4:0) AIA ADDR(6:0)
PEB 3456 E
Register Description
Data Sheet 255 05.2001
RDATA
Receive T1/E1 Framer Data Register
Access : read/write
Address : 11CH (PCI), 0EH (Local Bus)
Reset Value : 0000H
Note: Effected port and address is selected via register RREGSEL. All settings in this
register affect the selected port only.
DATA Data register
The recei ve framer da ta register ass igns a valu e to the recei ve framer of
port RREGSEL.PORT and the register selected via bit field
RREGSEL.ADDR. Read/write operation depends on the selected
register.
15 0
DATA(15:0)
PEB 3456 E
Register Description
Data Sheet 256 05.2001
FREGSEL
FDL Port & Register Select
Access : read/write
Address : 120H (PCI), 10H (Local Bus)
Reset Value : 0000H
Note: This register is an indirect access register which must be programmed before
accessing the register FDATA.
AIP Auto Increm ent Port
This bit enables the auto increment function o f bit field PORT. Each read/
write access to register FDATA increments PORT. This allows to
prog ram multiple, co nsecutive p orts without ac cessing FREG SEL again.
0 Disable auto increment function.
1 Enable auto increment function.
PORT Port Select
This bi t field selects the port number, wh ich can be acc essed via regis ter
FDATA.
0..27 Port Number for T1/E1.
28 Far End Alarm and Control Channel (DS3)
Setup FDL in T1 mode, enable BOM transfer.
29 C-bit pa rity path main tenance data li nk channel (DS3)
Setup FDL in E1 mode and assign Sa-bit access for bits Sa4, Sa5
and Sa6 .Disable access for Sa7 and Sa8.
AIA Auto Increm ent Address
This bit enables the auto increment function of bit field ADDR. Each
read/write access to register FDATA increments ADDR. This allows to
program multiple, consecutive registers without accessing FREGSEL
again.
0 Disable auto increment function.
1 Enable auto increment function.
15 12 8 7 4 0
AIP 00 PORT(4:0) AIA 00 ADDR(4:0)
PEB 3456 E
Register Description
Data Sheet 257 05.2001
ADDR Register Address
This b it field selects th e re gis ter ad dress of the facilit y data l ink c ha nnel,
which can be accessed via register FDATA.
0H..1FHRegister address.
PEB 3456 E
Register Description
Data Sheet 258 05.2001
FDATA
FDL Data Register
Access : read/write
Address : 124H (PCI), 12H (Local Bus)
Reset Value : 0000H
Note: Effected port and address is selected via register FREGSEL. All settings in this
register affect the selected port only.
DATA Data register
The FDL data register assigns a value to the facility data link controller
of port FREGSEL.PORT and the register selected via bit field
FREGSEL.ADDR. Read/write operation depends on the selected
register.
15 0
DATA(15:0)
PEB 3456 E
Register Description
Data Sheet 259 05.2001
MBE2P0
Mailbox Local Bus to PCI Command Register
Access : read/write
Address : 140H (PCI), 20H (Local Bus)
Reset Value : 0000H
MB Mailbox Data register
This register can be written and read from local bus side. From PCI side
this register should be used as read only in order to allow stable
interprocessor communication. Write access to this register results in
mailbox interrupt vectors on local bus side to the internal interrupt FIFO
when FCONF.MBID is set to ‘0’.
15 0
MB(15:0)
PEB 3456 E
Register Description
Data Sheet 260 05.2001
MBE2P1-7
Mailbox Local Bus to PCI Data Register 1-7
Access : read/write
Address : 144H-15CH (PCI), 22H-2EH (Local Bus)
Reset Value : 0000H
MB Mailbox Data register
This register can be written and read from local bus side. From PCI side
this register should be used as read only in order to allow stable
interprocessor communication.
15 0
MB(15:0)
PEB 3456 E
Register Description
Data Sheet 261 05.2001
MBP2E0
Mailbox PCI to Local Bus Status Register
Access : read/write
Address : 160H (PCI), 30H (Local Bus)
Reset Value : 0000H
MB Mailbox Status Register
This regi ster can be writte n and read from PCI side. From loca l bus sid e
this register should be used as read only in order to allow stable
interprocessor communication. Write access to this register results in
mailbox interrupt vectors to PCI side when CONF1.MBIM is set to ‘0’.
15 0
MB(15:0)
PEB 3456 E
Register Description
Data Sheet 262 05.2001
MBP2E1-7
Mailbox PCI to Local Bus Data Register 1-7
Access : read/write
Address : 164H-17CH (PCI), 32H-3EH (Local Bus)
Reset Value : 0000H
MB Mailbox Data Register
This regi ster can be writte n and read from PCI side. From loca l bus sid e
this register should be used as read only in order to allow stable
interprocessor communication.
15 0
MB(15:0)
PEB 3456 E
Register Description
Data Sheet 263 05.2001
8.9.2.1 M13 Transmit Registers
D3CLKCS
DS3 Clock Configuration and Status Register
Access : read/write
Address : 180H (PCI), 40H (Local bus)
Reset Value : 0000H
Note: When this register is reset, it takes aproximately 150 ns to fully reset the recevie
and transmit clock units. During this time, write access to DS3 registers is not
guaranteed. As this reset delay is difficult to gurantee in software, it is
recomm ended to read this register to verify DS3 clock activi ty before wri ting to any
DS3 registers.
RCA Receive Cloc k Activity
This bit monitors the receive clock activity (RC44).
0 No receive DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 s after the last active clock was detected.
1 At least one receive DS3 clock since last read of this register.
TCA Transmit Clock Activity
This bit monitors the transmit clock activity (TC44).
0 No transmit DS3 clock since last read of this register. This bit is
set to ‘0’ approx. 125 s after the last active clock was detected.
1 At least one transmit DS3 clock since last read of this register.
RRX Reset Receive r Clock Unit
This bit resets the receivers clock unit.
0 Normal operation.
1 Reset DS3 receiver clock unit. This bit is self clearing.
RTX R eset Transm itter Clock Unit
This bit resets the transmitters clock unit.
15 6543210
000000000 RCA TCA RRX RTX T2RL R2TL TXLT
PEB 3456 E
Register Description
Data Sheet 264 05.2001
0 Normal operation.
1 Reset DS3 transmitter clock unit. This bit is self clearing.
T2RL Transmit to Receive Loop (Local DS3 Loopback)
This bit enables the local DS3 loop where the outgoing DS3 bit stream
is mirrored to the DS3 input.
0 Disable local loop.
1 Enable local loop.
R2TL Receive to Transmit Loop (Remote DS3 Loopback)
This bit enables the remote DS3 line loop where the complete incoming
DS3 bit stream is mirrored to the transmitter.
0 Disable remote loop.
1 Enable remote loop.
TXLT Transmit Loop Timing Mode
This bit enables DS3 looped timing where the transmitter uses the
receivers DS3 input clock.
0 Disable looped timing.
1 Enabl ed loo ped timin g.
PEB 3456 E
Register Description
Data Sheet 265 05.2001
TUCLKC
Test Unit Clock Configuration Register
Access : read/write
Address : 184H (PCI), 42H (Local bus)
Reset Value : 0000H
RTUR Reset Test Unit Receiver
This bit resets the test unit receiver.
0 Normal operation.
1 Reset Rece iver (aut om ati cal ly rem oved). This bit i s se lf c lea rin g.
TUL Test Unit Transmit to Receive Loop
This b it swi tches a loc al l oop fro m the test unit tr ansmi tter to the test unit
receiver. While operating in loop mode the test unit is operated with
TC44.
0 Normal operation.
1 Test unit transmitter output connected to test unit receiver input.
15 10
00000000000000RTURTUL
PEB 3456 E
Register Description
Data Sheet 266 05.2001
D3TCFG
DS3 Transmit Configuration Register
Access : read/write
Address : 188H (PCI), 44H (Local bus)
Reset Value : 0000H
FAM TOVHSYN Mode
This bi t s wi tc hes be tw een in put mo de a nd output m od e of the si gnal pin
TOVHSYN. If TOVHSYN i s ope rate d in input m ode it mark s the p os itio n
of the X-b it. There for the o utgoin g DS3 frame is a ligned to TOVHSYN. If
TOVHSYN is switched to output mode TOVHSYN is asserted when the
X-bit needs to be inserted via the transmit overhead interface.
0 TOVHSYN switched to input.
1 TOVHSYN switched to output.
ITCK Invert Transmit Clock
This bit sets the clock edge for data transmission.
0 Update transmit data on the rising edge of transmit clock.
1 Update transmit data on the falling edge of transmit clock.
ITD Invert Transmit Data
This bit enables inversion of transmit data.
0 Transmit data is logic high (not inverted).
1 Transmi t data is logic low (inverted).
UTD Unipolar data mode
This bit sets the port mode to dual-rail mode or unipolar mode.
0 B3ZS (dual rail data)
1 Unipolar mode (single rail data)
15 876543210
0000000 FAM ITCK ITD UTD AISC LPC(1:0) FPL CBP
PEB 3456 E
Register Description
Data Sheet 267 05.2001
AISC AIS Code Type
This bit field sets the AIS code.
0 Set AIS to ’1010... ’ between overhead bits, C-bits all ‘0’s, X-bits
all ‘1’s ( standard)
1 Set AIS to unframed all ‘1’s (non-standard).
LPC Loopback Code.
This bit field selects the C-bit which will be inverted when loopback
requests are transmitted.
00 Invert 1st C-bit.
01 Invert 2nd C-bit.
10 Invert 3rd C-bit.
FPL Full Payload Mode
This bit enables the M23 multiplex operation or the full payload rate
format.
0 Enable M23 multiplex operation. Payload is formed by
interleaving 7 asynchronous DS2 tributaries
1 Enable full payload rate format. The payload is one single, high
speed data stream without stuffing.
CBP C-b it pari ty mo de
This bit enables M13 asynchronous mode or C-bit parity mode.
0 M13 asynchronous mode
1 C-bit parity mode
PEB 3456 E
Register Description
Data Sheet 268 05.2001
D3TCOM
DS3 Transmit Command Re gis ter
Access : read/write
Address : 18CH (PCI), 46H (Local bus)
Reset Value : 0000H
Reset Value : 0000H
Note - It is recommended to se t this register to 000070H after reset for normal operation.
TAIC Transmitted AIC-bit
This bit sets the value to be transmitted in the DS3 overhead bit of
block 3, subframe 1. This function is available in C-pit parity format only.
0 AIC-bit = ‘0’
1 AIC-bit = ‘1’
TNrB Transmitted Nr-bit
This bit sets the value to be transmitted in the DS3 overhead bit of
block 5, subframe 1. This function is available in C-pit parity format only.
0N
r-bit = ‘0’
1N
r-bit = ‘1’
TXBIT Transmitted X-bits
This bit sets the value to be transmitted in the DS3 overhead bit of
block 1, subfram es 1 and 2.
TXBIT is synchronized to the M23 multiframe. Both X-bits in a multiframe
are guaranteed identical. Software should limit changes to maximum of
1 per s ec on d. Thi s bit should be set to ‘ 1’, if transmiss ion of IDL E or AIS
is enable d.
0 X-bit = ‘0’
1 X-bit = ‘1’
SIDLE Send DS3 Idle Code
15 6543210
000000000TAICTN
rB TXBITSIDLESAISA SAIS 0
PEB 3456 E
Register Description
Data Sheet 269 05.2001
This bit enables transmission of the DS3 idle code (’1010’ between
overhead bits, X-bits all ‘1’s, C-bits all ‘0’s).
0 Normal operation.
1 Send DS3 idle co de.
SAISA Send AIS in DS3 output and on DS3 loop
This bit enables transmission of AIS on the DS3 output. If the DS3 is
additionally switched to local DS3 loopback mode the DS3 signal
including AIS is mirrored to the receiver. The AIS code transmitted
depends on D3TC FG.A ISC.
0 Normal operation.
1 Enable transmission of AIS.
SAIS Send AIS at DS3 output
This bit en ables transmiss ion of AIS on the DS3 output. If the D S3 signal
is switched into local DS3 loopback mode the DS3 signal without AIS
code is mirrored to the DS3 recei ver. The AIS c ode transm itted dep ends
on D3TCFG.AISC.
0 Normal operation.
1 Enable transmission of AIS.
PEB 3456 E
Register Description
Data Sheet 270 05.2001
D3TLPB
DS3 Transmit Remote DS2 Loopback Register
Access : read/write
Address : 190H (PCI), 48H (Local bus)
Reset Value : 0000H
LPB Remote DS2 Loopback
Setting LPB(x) enables the remote DS2 loopback of tributary x. In this
mode the demultiplexed DS2 tributary is internally looped and
multiplexed into the outgoing DS3 signal.
0 Normal operation.
1 Enable remote DS2 loopback of tributary x.
15 6 0
000000000LPB(6:0)
PEB 3456 E
Register Description
Data Sheet 271 05.2001
D3TLPC
DS3 Transmit Loopback Code Insertion Register
Access : read/write
Address : 194H (PCI), 4AH (Local bus)
Reset Value : 0000H
LPC Send Loopback
Setting LPC(x) enables transmission of the loopback code in tributary x
of the DS3 signal. The loopback code inserted depends on
D3TCFG.LPC.
0 Normal operation.
1 Enable transmission of loopback code in tributary x.
15 6 0
000000000LPC(6:0)
PEB 3456 E
Register Description
Data Sheet 272 05.2001
D3TAIS
DS3 Transmit AIS Insertion Register
Access : read/write
Address : 198H (PCI), 4CH (Local bus)
Reset Value : 0000H
AISE AIS Error Insertion
Toggling this bit inserts one ‘0’ in all DS3 tributaries which transmit AIS.
AIS Send DS2 Alarm Indication Signal
Setting AIS(x) enables insertion of the DS2 alarm indication signal in the
outgoing tributary x of the DS3 signal. AIS is an all ’1’ signal.
0 Normal operation
1 Enable transmission of AIS in tributary x.
15 7 6 0
00000000 AISE AIS(6:0)
PEB 3456 E
Register Description
Data Sheet 273 05.2001
D3TFINS
DS3 Transmit Fault Insertion Control Regis ter
Access : read/write
Address : 19CH (PCI), 4EH (Loc al bus)
Reset Value : 0000H
FINSC Fault Insertion Code.
Fault ins ertion is servic e affecting and is intended for tes ting only. Code s
are not self clearing, i.e. errors are continuously generated as indicated
until bit cl eared . A sing le FE BE, P, CP, or code vi olati on is g uarant eed
to be inserted if the respective code is written and then immediately
cleared.
0 Normal operation (no fault insertion)
1 Insert FEBE event every multi fram e (106 µsec).
2 Insert P-bit errors every 2nd multiframe (212 µsec).
3 Insert CP-bit errors every 2nd multiframe (212 µsec).
4 Insert 4 F-bit errors/multiframe (satisfies 3 out of 15 threshold
trigger).
5 Insert 5 F-bit errors/multiframe (satisfies 3 out of 7 threshold
trigger).
6 Insert 3 M-bit errors/multiframe (caution: receiver can frame on
emulator).
7 Force DS3 output to all ‘0’s.
8 Insert B3ZS violation/multiframe (violation of alternate polarity
rule).
9 Insert 3 zero string/multiframe (B3ZS code word suppressed)
15 30
000000000000 FINSC(3:0)
PEB 3456 E
Register Description
Data Sheet 274 05.2001
D3TTUC
DS3 Transmit Test Unit Control Register
Access : read/write
Address : 1A0H (PCI), 50H (Local bus)
Reset Value : 0000H
EN Enable Test Unit Insertion
Setting this bit enables insertion of the test unit data.
0 Normal operation
1 Enable insertion of test unit data.
TUDS2 Test Unit DS2 Group
This bi t field sel ects the D S2 group th e test u nit is atta ched to. Onl y valid
if TUIM is 10B, 01B or 00B.
0..6 Selects DS2 group 0..6.
TUDS1 Test Unit DS1 Tributary
This bit field selects the DS1 tributary the test unit is attached to. Only
valid if TUIM is 00B. The DS2 group is sel ected via TUDS2.
0..3 DS1/E1 tributary
TUIM Bit Error Rate Test Unit (TU) Insertion Mode
This bit field selects the interface the test unit is attached to.
00BInsert test stream into DS1/E1 tributary (unframed)
01BInsert test stream into DS2 tributary (unframed, bypass M12)
10BInsert test stream into DS2 payload (framed)
11BInsert test stream into DS3 payload (framed)
15 76 43210
00000000 EN TUDS2(2:0) TUDS1(1:0) TUIM
PEB 3456 E
Register Description
Data Sheet 275 05.2001
D3TSDL
DS3 Transmit Spar e Data Link R egis ter
Access : read/write
Address : 1A4H (PCI), 52H (Local bus)
Reset Value : 01FFH
Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 of subframes 2, 6,
and 7. If e nabled, the M13 will generate an interrupt every multiframe to request a re fresh
of this register. The software must write these registers within 106 µsec to avoid an
underrun.
DL(S)(B) Overhead bit for block B of subframe S
These bits store the DL bits to be transmitted in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every m ul tiframe to requ es t a r efres h o f th is regi st er. T he s oft w are m ust
write thes e register s withi n 106 µsec to avoid an underrun.
15 876543210
0000000 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
PEB 3456 E
Register Description
Data Sheet 276 05.2001
D3RCFG
DS3 Receive Configuration Register
Access : read/write
Address : 1C0H (PCI), 60H (Local bus)
Reset Value : 0000H
Note: M13 mode, Full payload mode, loopback code, and AIS mode are controlled by
bits CBP, FPL, LPC, and AISC in register DS3 transmit configuration register
D3TCFG.
CVM B3ZS Code Word (“00V” or “10V” Acceptance Condition)
This bit selects the B3ZS violations alternate polarity to maintain line
balance.
0 Convert all B3ZS codeword patterns to “000” regardless of
polarity.
1 Convert codeword only if alternate violation polarity rule is
satisfied.
IVM Interrupt Vector Mode
This bit selects the interrupt vector mode.
0 Interrupt vector flags are set when corresponding condition has
changed.
1 Interrupt vector flags contain actual status of condition.
STTM Select Transmit Tributary Monitoring for receive test unit
This bit selects the T1/E1 tributary observed by the test unit receiver.
The test unit can be connected to the upstream T1/E1 tributary (T1/E1
trib utar y going towar ds th e DS3 inte rface) or to the downst ream T1/E1
tributary (T1/ E1 tributary coming fr om the DS3 interface).
0 Monitor downstream T1/E1 tributary.
1 Monitor upstream T1/E1 tributary.
15 111098 6543210
CVM 000 IVM STTM ECM FEBM 0 AISX MFM MDIS FFM IRCK IRD URD
PEB 3456 E
Register Description
Data Sheet 277 05.2001
ECM Error Counter Mode
DS3 errors are counted in background and copied to foreground (error
counter registers) when condition selected via ECM is met.
0 Counte r valu es are copie d to fore ground when copy comm and i s
execut ed. See als o regi ste r DS3CO M.
1 The counter values are copied to the foreground register in one
second intervals. At the same time the background registers are
reset to zero . This operation is sync hronous with the peri odic one
second interrupt which alerts software to read the register.
FEBM Far End Block Error (FEBE) Mode
This bit selects the event which leads to FEBE indication. It is available
in C- bit parity mode on ly.
0 Receive multiframe parity error.
1 Receive multiframe parity error or framing error.
AISX AIS X-bit Check Disable
This bit di sables checking of the X-bit for AIS an d idle detection.
0 Check X-bit.
1 Disable check of X-bit.
MFM Multiframe Framing Mode
This bit se lects the M-bit error co ndition which trig gers the DS3 framer to
start a new frame search. To enable reframing in case of M-bit errors
MDIS must be set to ‘0’.
0 Start new F-frame search if M-bit errors are detected in two out
of four consecutive M-frames.
1 Start new F-frame search if M-bit errors are detected in three out
of four consecutive M-frames.
MDIS Multiframe Re frame Di sable
This bit disables reframing due to M-bit errors.
0 Enable reframe due to M-bit errors.
1 Disable reframe due to M-bit errors.
PEB 3456 E
Register Description
Data Sheet 278 05.2001
FFM F Framing Mode
This bi t sele cts th e F-bit e rror conditi on wh ich trigg ers the DS3 fra mer to
start a new frame search.
0 A new frame search is started when 3 out of 8 contiguous F-bits
are in error.
1 A new fram e search is started whe n 3 out of 16 co ntiguous F-bits
are in error.
IRCK Invert Receive Clock
This bit sets the clock edge for data sampling.
0 Sample data on the rising edge of receive clock.
1 Sample data on the falling edge of receive clock.
IRD Invert Receive Data
This bit enables inversion of receive data.
0 Receive data is logic high (not inverted).
1 Receive data is logic low (inverted).
URD Unipolar Receive Data
This bit sets the port mode to dual-rail mode or unipolar mode.
0 B3ZS (dual rail data input)
1 Unipolar mode (single rail data input)
PEB 3456 E
Register Description
Data Sheet 279 05.2001
D3RCOM
DS3 Receive Command Register
Access : read/write
Address : 1C4H (PCI), 62H (Local bus)
Reset Value : 0000H
C3NC Copy DS3 Error Counters
Values of DS3 background registers are copied to foreground.
Background registers are NOT cleared. Command is self clearing and
compl etes bef ore next regis ter acc ess is poss ible i. e. so ftware can write
command and then immediately read the counters without starting a
delay timer.
Note: Usage of this function in not recommend in ’One Second’ error
counter mo de ( D3R CFG .ECM = ‘1’).
0 No operation.
1 Copy background counters to foreground.
C3C Copy and Clear DS3 Error Counters
Values of DS3 background registers are copied to foreground.
Background registers are cleared. Command is self clearing and
compl etes bef ore next regis ter acc ess is poss ible i. e. so ftware can write
command and then immediately read the counters without starting a
delay timer.
0 No operation.
1 Copy background counters to foreground. Clear background
counters.
Note: Usage of this function in not recommend in ’One Second’ error
counter mo de ( D3R CFG .ECM = ‘1’).
CCNA Copy Error Counters
Only valid for counters which are not operating in ‘One Second’ error
counte r mode. Values of DS2 and D S3 bac kgroun d regis ters are copie d
to foreground. Bac kg roun d reg is ters are N OT c lea red. Comman d is self
15 43210
00000000000 C3NC C3C CNCA CCA FRS
PEB 3456 E
Register Description
Data Sheet 280 05.2001
clearing and completes before next register access is possible i.e.
software can write command and then immediately read the counters
without starting a delay timer.
0 No operation.
1 Copy background counters to foreground.
CCA Copy and Clear DS2/DS3 Error Counters
Only valid for counters which are not operating in ‘One Second’ error
counte r mode. Values of DS2 and D S3 bac kgroun d regis ters are copie d
to foreground. Background registers are cleared. Command is self
clearing and completes before next register access is possible i.e.
software can write command and then immediately read the counters
without starting a delay timer.
0 No operation.
1 Copy background counters to foreground. Clear background
counters.
FRS For ce Resynchroni zation
This b it enable s a new fra me s earc h on the D S3 i nput. The comm an d i s
self clearing after frame search has begun.
0 Normal operation.
1 Force new frame search.
PEB 3456 E
Register Description
Data Sheet 281 05.2001
D3RIMSK
DS3 Receive Interrupt Mask Register
Access : read/write
Address : 1C8H (PCI), 64H (Local bus)
Reset Value : 1FFFH
This register provides the interrupt mask for DS3 status interrupts and DS3 loopback
code interrupts. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see “Layer One Interrupts” on Page 137.
The following definition applies:
1 The corresponding interrupt vector will not be generated by the device.
0 The corresponding interrupt vector will be generated.
RSDL Mask ’Receive Spare Data Link Transfer Buffer Full’
TSDL Mask ’Transmit Spare Data Link Transfer Buffer Empty’
LPCS Mask ’Loopback Code Status’ (flagged in D3RLPCS)
SEC Mask ’1 Second Interrupt’
CLKS Mask ’DS3 Clock Status’
NrMask ’Nr-bit Image’ (C-bit parity mode only)
AIC Mask ’AIC-bit Image’ (C-bit parity mode)
XBIT Mask ’X-bit Image’
IDLES Mask ’DS3 Idle Signal State’
AISS Mask ’DS3 Alarm Indication Signal State’
REDS Mask ’DS3 Red Alarm State’
LOSS Mask ’DS3 Input Signal State’
FAS Mask ’Frame Alignment State’
15 1211109876543210
000 CLKS RSDL TSDL LPCS SEC NrAIC XBIT IDLES AISS REDS LOSS FAS
PEB 3456 E
Register Description
Data Sheet 282 05.2001
D3RESIM
DS3 Receive Error Simulation Register
Access : read/write
Address : 1CCH (PCI), 66H (Local bus)
Reset Value : 0000H
FTMR Fast Timer
This bit enables alarm timer test function (manufacturing test only).
0 Normal Operation
1 T est Operation
DS3 RED/AIS/Idle timer period reduced by 56.
DS2 READ/AIS timer period reduced by 24.
Second interrupt period reduced to 140 µsec
ESIMC Error Simulation Code
This bit enables error simulation. During error simulation the device
generates error interrupts and error status messages. Nevertheless the
servic e is not affecte d.
0 Normal operation (no error simulation).
1 Simulate one F-bit error/multiframe (106 µsec).
2 Simulate M-bit error in every other multiframe.
3 Simulate FEBE event/multiframe (106 µsec).
4 Simulate P/CP event/multiframe (106 µsec).
5 Simulate Loss of DS3 input (all zeros).
6 Simulate B3ZS code violations.
7 Simulate Loss of Receive Clock
15 420
00000000000FTMR0ESIMC(2:0)
PEB 3456 E
Register Description
Data Sheet 283 05.2001
D3RTUC
DS3 Receive Test Unit Control Register
Access : read/write
Address : 1D0H (PCI), 68H (Local bus)
Reset Value : 0000H
EN Enable Test Unit Receive Clock
This bit enables the receive clock of the test unit. The clock speed is
dependent on the selec ted test mod e.
0 Receive clock disabled.
1 Receive clock enabled.
TUDS2 Test Unit DS2 Group
This bi t field sel ects the D S2 group th e test u nit is atta ched to. Onl y valid
if TURM is 10B, 01B, or 00B.
0..6 Selects DS2 group 0..6.
TUDS1 Test Unit DS1/E1 Tributary
This b it field s elects the DS1/E1 tributary the test uni t is attach ed to. Onl y
valid if TURM is 00B. The DS2 group is selected via TUDS2.
0..3 DS1/E1 tributary
TURM Test Unit Receive Mode
This bit field selects the interface the test unit is attached to.
00BDS 1/E1 tributary (unfra med)
01BDS 2 tributary (unf ramed, bypass M12)
10BDS2 payload (framed)
11BDS3 payload (framed)
15 76 43210
00000000 EN TUDS2(2:0) TUDS1(1:0) TURM
PEB 3456 E
Register Description
Data Sheet 284 05.2001
D3RSTAT
DS3 Receive Status Register
Access : read
Address : 1D4H (PCI), 6AH (Loc al bus)
Reset Value : 0841H (Immediately after reset)
: 084DH (After some clock cycles)
: Depends on time register will be read after reset.
: Status register will change after some clock cycles becaues LOSS
: (loss of signal) and REDS (loss of frame alignment) will be set
: because no signal is available.
Each bit in the DS3 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0 The named status is not or no longer existing.
1 The named status is currently effective.
Except for COFA every bit can be used to generate a DS3 interrupt vector. See also
register D3RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS3 framer interrupts on page “Layer One Interrupts”
on Page 137.
LRX C Loss of Receive DS3 Clock
This bit indicates loss of DS3 receive clock.
LTXC Loss of Transmit DS 3 Clock
This bit indicates loss of DS3 transmit clock.
RSDL Receive Spare Data Link Buffer Full
This bit indicates that the spare data link receive buffer (register
D3RSDL) is full.
TSDL Transmit Spare Data Link Buffer Empty
1514131211109876543210
0 LRXC LTXC RSDL TSDL LPCD SEC Nr
AICC AIC XBIT IDLES AISS REDS LOSS COFA FAS
PEB 3456 E
Register Description
Data Sheet 285 05.2001
This bit indicates that the spare data link transmit buffer (register
D3TSDL) is empty.
LPC D Loopback Code Detected
This bit indicates a changes in register D3RLPCS.
SEC 1 Second Flag
This bit toggles every second synchronously with the one second
interrupt. It can be used by software to synchronize 1 second events
when the ’One second interrupt’ vector is masked.
Nr/AICC Nr-bit Ima ge (C-bit parity format onl y)
This bit contains an image of the DS3 frame overhead bit in block 5 of
subframe 1. It is updated only if its state persists for 3 multiframes and
DS3 f rame is aligned .
AIC-bit changed (M13 asynchronous format)
This bi t indicates a c hange of the AIC-bit (first C-bi t of the first sub frame)
since the last read of this register.
AIC AIC bit Image (DS3 frame overhead bit in block 3 of subframe 1)
This bit contains an image of the DS3 frame overhead bit in block 3 of
subframe 1. It is updated only if its state persists for 3 multiframes and
DS3 f rame is aligned .
XBIT X bit Image (DS3 frame overhead bit in block 1 of subframes 1 and 2)
This bit contains an image of the DS3 frame overhead bit in block 1 of
subframes 1 and 2. It is updated only if both bits in a DS3 multiframe
have the same value, its state persists for at least 3 multiframes and
when the DS3 framer is in synchronous state.
IDLE S Idle State
This bit indica tes that th e idle pa ttern (fram ed ...110 0... with C-bi ts=’0’ in
subframe 3 and X-bits=’1’) was persistent as per alarm timing
parameters defined in register D3RAP. Idle is considered active in a
multif rame when fewer than 15 erro rs are detected. At 10-3 error rates, 5
errors per multiframe are typical. The exact time necessary to change
the flag could be greater if the FAS flag is not constant. The frame
alignm ent s tate is integ rated b y inc remen ting or decrem entin g a co un ter
at the end of each multiframe when the FAS flag is set or cleared
respectively.
AISS AIS Alarm State.
This bit indicates the AIS alarm state. AIS can be a framed ’..1010..’
pattern with C-bits=’0’ and X-bits=’1’ or an unframed all ‘1’ pattern. This
is determined by D3TCFG.AISC. AIS is considered active in a
PEB 3456 E
Register Description
Data Sheet 286 05.2001
multif rame when fewer th an 15 errors ar e detected an d is declare d when
it was persistent as per alarm timing parameters defined in register
D3RAP. At 10-3 erro r rates, 5 errors per multiframe are ty pical. The exac t
time ne ce ss ary to c han ge th e fl ag c ou ld b e gre ate r if th e FAS fl ag i s n ot
constant. The frame alignment state is integrated by incrementing or
decrem enting a cou nter at the end of each multif rame when the F AS flag
is set or cleare d respectively.
REDS Red Alarm State (loss of frame alignment)
This bit indicates that red alarm was persistent as per alarm timing
parameter defined in register D3RAP. The red alarm flag nominally
change s when loss of frame alignment cond ition persis ts for either 32 or
128 multiframes. This is determined by bit D3RCFG.SAIT. The exact
time ne ce ss ary to c han ge th e fl ag c ou ld b e gre ate r if th e FAS fl ag i s n ot
constant. The frame alignment state is integrated by incrementing or
decrem enting a cou nter at the end of each multif rame when the F AS flag
set or cleared re spect ively.
LOSS Loss of DS3 Input Signal
This b it indic ates tha t the received D S3 bit s tream c ontained at least 175
consecutive ‘0’s. It is deasserted when 59 ‘1’ bits are detected in 175
clocks (1/3 densit y). Fol lowin g remova l of LOS , a 10 ms ec gua rd time r
is sta rted. If a new LOS occurs, the r elease c ondition is exten ded so th at
the 1 /3 densit y condit ion must persist fo r at least 1 0 msec. Thi s prevent s
chatter and excessive interrupts.
COFA Change of Frame Alignment.
This bit indicates a change of frame alignment event. It is set when the
DS3 framer found a new frame alignment and when the new frame
position differs from the expected frame position.
FAS DS3 Frame Alignment State
This bit indicates that the DS3 framer is not aligned.
PEB 3456 E
Register Description
Data Sheet 287 05.2001
D3RLPCS
DS3 Receive Loopback Code Status Register
Access : read
Address : 1D8H (PCI), 6CH (Local bus)
Reset Value : 0000H
LPC D Loopback Detected
LPCD(x) indicates that a loopback request was received. A loopback
request for tributary x is indicated by inverting one of the 3 C-bits of the
xth subframe. The C-bit is determined by D3TCFG.LPC. A command
state change must persist for 5 contiguous multiframes before it will be
reported. This function is available in M13 asynchronous mode only.
0 No loopback code being received
1 Loopback code being received
15 6 0
000000000 LPCD(6:0)
PEB 3456 E
Register Description
Data Sheet 288 05.2001
D3RSDL
DS3 Receive Spare Data Link Register
Access : read
Address : 1DCH (PCI), 6EH (Loc al bus)
Reset Value : 01FFH
DL(S)(B) Overhead Bit for Block B of Subframe S
These bits buffer the spare DL bits received in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every multiframe to synchronize reading of this register. The register
must be read within 106 µsec to avoid an overrun.
15 876543210
0000000 DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
PEB 3456 E
Register Description
Data Sheet 289 05.2001
D3RCVE
DS3 Receive B3ZS Code Violation Error Counter
Access : read/write
Address : 1E0H (PCI), 70H (Local bus)
Reset Value : 0000H
CVE(15:0) B3ZS Code Violation Errors
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of B3ZS Code Violation errors. The error counter will not be
increm ented during asy nc hro nou s state.
D3RFEC
DS3 Receive Framing Bit Error Counter
Access : read/write
Address : 1E4H (PCI), 72H (Local bus)
Reset Value : 0000H
FEC(15:0) Framing Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of F-bit and M-bit errors. Errors are not counted in out of frame
state.
15 0
CVE(15:0)
15 0
FEC(15:0)
PEB 3456 E
Register Description
Data Sheet 290 05.2001
D3RPEC
DS3 Receive Parity Error Counter
Access : read/write
Address : 1E8H (PCI), 74H (Local bus)
Reset Value : 0000H
PE(15:0) Parity Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of parity errors (P-bits in DS3 overhead bits). The P-bit is
duplicated in the DS3 frame structure but only one error is counted per
multiframe. Errors are not counted in out of frame state.
D3RCPEC
DS3 Receive Path Parity Error Counter
Access : read/write
Address : 1ECH (PCI), 76H (L ocal bus)
Reset Value : 0000H
CPE(15:0) Path Parity Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Count of path parity errors (CP bits in DS3 C-bit parity overhead bits).
CP-bits are triplicated in the DS3 frame structure but only single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
15 0
PE(15:0)
15 0
CPE(15:0)
PEB 3456 E
Register Description
Data Sheet 291 05.2001
D3RFEBEC
DS3 Receive FEBE Error Counter
Access : read/write
Address : 1F0H (PCI), 78H (Local bus)
Reset Value : 0000H
FEBEC(15:0) FEBE error events
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
This register counts the occurence of a received ‘not all ‘1’s’. FEBE-bits
are triplicated in the DS3 frame structure but only one single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
D3REXZ
DS3 Receive Excessive Zer oe s Counter
Access : read/write
Address : 1F4H (PCI), 7AH (Loc al bus)
Reset Value : 0000H
EXZ(15:0 ) Exz ess iv e Zero es
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Violations are 3 zero strings. The error counter will not be incremented
during asynchronous state.
15 0
FEBE(15:0)
15 0
EXZ(15:0)
PEB 3456 E
Register Description
Data Sheet 292 05.2001
D3RAP
DS3 Alarm Parameters
Access : read/write
Address : 1F8H (PCI), 7CH (Loc al bus)
Reset Value : 0000H
AIS AIS criteria
This bits sets the error rate for AIS det ection. Declaration of AIS depend s
on value defined in bit field CV.
0 AIS is recognized when the alarm indication signal is received
with less than 8 errors per multiframe.
1 AIS is recognized when the alarm indication signal is received
with less than 15 errors per multiframe.
CV Counter Value
This bi t sp ec i fi e s th e nu mb e r o f f ram es w h en t h e TE3 - CH AT T de c la res
AIS, RED or Idle.
0..63 Counter Value.
15 7 5 0
00000000AIS0CV(5:0)
PEB 3456 E
Register Description
Data Sheet 293 05.2001
8.9.2.2 DS2 Control and Status Registers
D2TSEL
DS2 Transmit Gr ou p Select Re gis ter
Access : read/write
Address : 200H (PCI), 80H (Local bus)
Reset Value : 0000H
Note: This register is an indirect access register, which must be programmed before
accessing the register DS2 transmit registers.
GN Group Number
This bit fi eld sel ects the DS2 gr oup, whic h can be acces sed via the D S2
transmit registers.
0..6 Group Number.
15 20
0000000000000 GN(2:0)
PEB 3456 E
Register Description
Data Sheet 294 05.2001
D2TCFG
DS2 Transmit Configuration Register
Access : read/write
Address : 204H (PCI), 82H (Local bus)
Reset Value : 0000H
LPC Loopback Code
This bit selects the C-bit which will be inverted when loopback requests
are transmitted.
00 Invert 1st C-bit.
01 Invert 2nd C-bit.
10 Invert 3rd C-bit.
E1 G.747 Sele ct
This bit selects the operation mode of the low speed multiplexer.
0 Select M12 mode (4 DS1 into DS2).
1 Select ITU-T G.747 mode (3 E1 into DS2).
15 210
0000000000000LPC(1:0)E1
PEB 3456 E
Register Description
Data Sheet 295 05.2001
D2TCOM
DS2 Transmit Command Re gis ter
Access : read/write
Address : 208H (PCI), 84H (Local bus)
Reset Value : 0000H
FINSC Fault Insertion Code
This bit enables transmission of faults for testing purposes.
0 No fault inserti on.
1 Insert F-bit errors at low rate (2 out of 5 F-bits).
2 Insert F-bit errors at high rate (2 out of 4 F-bits).
3 Insert M-bit framing bit error (DS1 mode) or P-bit error (ITU-T
G.747)
SRA Set Remote Alarm
This bit enables transmission of the DS3 remote alarm. In DS1 modes
remote alarm is transmitted in subframe 4, block 1 overhead bit and in
ITU-T G.747 remote alarm is transmitted in bit 2 of “set II”.
0 Normal operation.
1 Enable transmission of remote alarm.
RES ITU-T G.747 Reserved Bit
This bit sets the value to be transmitted in the reserved bit of
ITU-T G.747 format.
0 Transmit reserved bit as ’0’.
1 Transmit reserved bit as ’1’.
15 3210
000000000000 FINSC(1:0) SRA RES
PEB 3456 E
Register Description
Data Sheet 296 05.2001
D2TILPC
DS2 Transmit E1/T1 Remote Loopback/Loopback Code InsertionRegister
Access : read/write
Address : 20CH (PCI), 86H (Local bus)
Reset Value : 0000H
LPC Send Loopback Code for Tributary N
Setting LPC(x) enables tran sm is si on of the l oopback co de in trib utary x.
The loopback code inserted is specified in D2TCFG.LPC.
0 Disable transmission of loopback code.
1 Enable transmission of loopback code.
15 30
000000000000LPC(3:0)
PEB 3456 E
Register Description
Data Sheet 297 05.2001
D2RSEL
DS2 Receive Group Select Register
Access : read/write
Address : 220H (PCI), 90H (Local bus)
Reset Value : 0000H
Note: This register is an indirect access register, which must be programmed before
accessing the register DS2 transmit registers.
GN Group Number
This bit fiel d selects the DS2 gro up num be r, wh ich can be acce ss ed via
the DS2 receive registers.
0..6 Group Number.
15 210
0000000000000 GN(2:0)
PEB 3456 E
Register Description
Data Sheet 298 05.2001
D2RCFG
DS2 Receive Configuration Register
Access : read/write
Address : 224H (PCI), 92H (Local bus)
Reset Value : 0000H
Note: ITU-T G.747 mapping and loopback codes are controlled by bits E1 and LPC in
the DS3 transmit configuration register D2TCFG.
E1/T1 and loo pba ck c od es are con trol led by E1 an d L P C f iel ds of the D 2TCFG regi ster.
ECM Error Counter Mode
DS2 errors are counted in background and copied to foreground (error
counter registers) when condition selected via ECM is met.
0 Counte r valu es are copie d to fore ground when copy comm and i s
execut ed. See als o regi ste r DS3CO M.
1 The counter values are copied to the foreground register in one
second intervals. At the same time the background registers are
reset to zero . This operation is sync hronous with the peri odic one
second interrupt which alerts software to read the register.
MFM Multiframe Framing Mode
This bit se lects the M-bit error co ndition which trig gers the DS2 framer to
start a new frame search. It is valid in DS1 mode only.
0 F-frame search started if 3 contiguous multiframes have M-bit
errors.
1 Inhibit new F-frame search due to M-bit errors.
FFM F-Framing Mode
This bi t sele cts th e F-bit e rror conditi on wh ich trigg ers the DS2 fra mer to
start a new frame search.
0 A new frame search is started when 2 out of 4 contiguous F-bits
are in error.
1 A new frame search is started when 2 out of 5 contiguous F-bits
are in error.
15 310
000000000000ECM0MFMFFM
PEB 3456 E
Register Description
Data Sheet 299 05.2001
D2RCOM
DS2 Receive Command Register
Access : read/write
Address : 228H (PCI), 94H (Local bus)
Reset Value : 0000H
ESIMC Error Simulation Code
This bi t field enable s error sim ulation. Du ring erro r simulat ion the devic e
generates error interrupts and error status messages. Nevertheless the
servic e is not affecte d.
0 Normal operation (no error simulation)
1 Simulate 2 receive F-bit errors/multiframe (186 µsec)
2 Simulate
2 receive M-bit errors/multiframe (186 µsec) (DS-1 mode)
Receive parity error/multiframe (133 µsec) (ITU-T G.747 mode)
3 Simulate remote alarm
4 Simulate loss of frame (RED alarm timer)
5 Simulate AIS (AIS alarm timer)
6 Simulate receive loop command
C2NC Copy DS2 Error Counters
Only v ali d wh en D2 RC F G.E CM is se t to ‘0 ’. V a lu es of DS 2 back gr o und
registers are copied to foreground. Background registers are NOT
cleared. Command is self clearing and completes before next register
access is possible i.e. software can write command and then
immediately read the counters without starting a delay timer.
0 No operation.
1 Copy background counters to foreground.
C2C Copy and Clear DS2 Error Counters
Only v ali d wh en D2 RC F G.E CM is se t to ‘0 ’. V a lu es of DS 2 back gr o und
registers are copied to foreground. Background registers are cleared.
15 6 4 1 0
000000000ESIMC(2:0)00C2NCC2C
PEB 3456 E
Register Description
Data Sheet 300 05.2001
Command is self clearing and completes before next register access is
possi ble i.e. software can w rite com mand a nd then immediate ly read the
counters without starting a delay timer.
0 No operation.
1 Copy background counters to foreground. Clear background
counters.
PEB 3456 E
Register Description
Data Sheet 301 05.2001
D2RIMSK
DS2 Receive Interrupt Mask Register
Access : read/write
Address : 22CH (PCI), 96H (Local bus)
Reset Value : 003FH
This register provides the interrupt mask for DS2 status interrupts and DS2 loopback
code interrupts. Generation of an interrupt vector itself does not necessarily result in
assertion of the interrupt pin. For description of interrupt concept and interrupt vectors
see “Layer One Interrupts” on Page 137.
The following definition applies:
1 The corresponding interrupt vector will not be generated by the device.
0 The corresponding interrupt vector will be generated.
LPCS Mask ’Loopback Code Status’ (flagged in D2RLPCS)
AISS Mask ’AIS State’
REDS Mask ’Red Alarm State’
RES Mask ’Reserved Bit’
RAS Mask ’DS2 Remote Alarm State’
FAS Mask ’DS2 Frame Alignment State’
15 543210
0000000000 LPCS AISS REDS RES RAS FAS
PEB 3456 E
Register Description
Data Sheet 302 05.2001
D2RSTAT
DS2 Receive Status Register
Access : read
Address : 230H (PCI), 98H (Local bus)
Reset Value : 0001H (Immediately after reset)
: 0011H (After so me cloc k cyc le s)
: Depends on time register will be read after reset.
: Status register will change after some clock cycles becaues REDS
: (loss of frame alignment) will be set, because no signal is available.
Each bit in the DS2 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0 The named status is not or no longer existing.
1 The named status is currently effective.
The change of status bit can also be used to generate a DS2 interrupt vector. See also
register D2RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS2 framer interrupts on page “Layer One Interrupts”
on Page 137.
AISS DS2 AIS Alarm State (unframed all ‘1’s pattern)
AIS is considered valid in a multiframe when fewer than 5 zeros are
detected. At 10-3 error rates, 1 zero per multiframe is typica l. A valid DS2
signal without any bit errors has at least 5 zeros.
The AIS flag nominally changes when the AIS condition is persistent as
per alarm timing parameters defined in register D2RAP. The exact time
necessary to change the flag could be greater in extremely high error
rates. The AIS state is integrated by incrementing or decrementing a
counter at the end of each multiframe depending on the AIS condition
being valid or invalid respectively.
REDS DS2 Red Alarm State (loss of frame alignment).
15 543210
0000000000 AISSREDSRES RASCOFAFAS
PEB 3456 E
Register Description
Data Sheet 303 05.2001
The red alarm flag nominally changes when loss of frame alignment
condit ion is p ersistent as per al arm timi ng paramet ers defined in regis ter
D2RAP. The exact ti me nec essar y to chan ge the fla g coul d be greate r if
the FAS flag is not constant because the frame alignment state is
integrat ed by incrementi ng or decrementing a coun ter at the end of each
multiframe when the FAS flag set or cleared respectively. Note that the
framer’s verification algorithm is designed to prevent a bouncing FAS
flag.
RES Reserved Bit
This bit indicates the status of bit 3 in set II of ITU-T G.747 mode. Is it
updated if the state persists for at least 8 multiframes. Reserved Bit
changes are not reported when the DS2 framer is not aligned.
RRA Remote Alarm
This bit indicates that remote alarm is active. Changes are reported
when they persist for at least 8 multiframes. In DS1 mode changes on
Mx bit are reported, in ITU-T G.747 mode changes of bit 1 of set II are
repo rted. Cha nges are not reported whe n the DS2 fra mer is not a ligne d.
COFA Change of Frame Alignment.
This bit indicates a change of frame alignment event. It is set when the
DS2 framer found a new frame alignment and when the new frame
position differs from the expected frame position.
FAS Dem ultiplexer Los s of Frame A lignment
This bit indicates that the DS2 framer is not aligned.
PEB 3456 E
Register Description
Data Sheet 304 05.2001
D2RLPCS
DS2 Receive Loopback Code Status Register
Access : read
Address : 234H (PCI), 9AH (Local bus)
Reset Value : 0000H
LPCD(N) Loopback Command Detected
LPCD(x) indicates that a loopback request was received. A loopback
request for tributary x is indicated by inverting one of the 3 C-bits of the
xth subframe. The C-bit is determined by D2TCFG.LPC. A command
state change must persist for 5 contiguous multiframes before it will be
reported.
0 No loopback code being received.
1 Loopback code being received.
15 30
000000000000 LPCD(3:0)
PEB 3456 E
Register Description
Data Sheet 305 05.2001
D2RFEC
DS2 Receive Framing Bit Error Counters
Access : read/write
Address : 238H (PCI), 9CH (Local bus)
Reset Value : 0000H
FE(15:0) Framing Bit Errors
Error counter mode (Clear on Read or Errored Second) depends on
register D2RCFG.ECM.
For DS1 mode framing bit errors inc lude F-bit an d M-bit errors. For G747
mode, in divid ual bits in the Fram e Alignm ent Signa l (FAS) are counted.
Errors are not counted in out of frame state.
D2RPEC
DS2 Receive Parity Bit Error Counter (ITU-T G.747)
Access : read/write
Address : 23CH (PCI), 9EH (Loc al bus)
Reset Value : 0000H
PE(15:0) Parity Errors in ITU- T G.747 mode
Error counter mode (Clear on Read or Errored Second) depends on
register D2RCFG.ECM. Errors are not counted in out of frame state.
15 0
FE(15:0)
15 0
PE(15:0)
PEB 3456 E
Register Description
Data Sheet 306 05.2001
D2RAP
DS2 Receive Alarm Timer Param ete rs
Access : read/write
Address : 240H (PCI), A0H (Local bus)
Reset Value : 00H
AIS AIS criteria
This bits sets the error rate for AIS detection. Declaration of AIS is
specified by bits CM and CV.
ITU-T G.747:
0 AIS condition is recognized when the alarm indication signal is
received with less than 5 errors in each of 2 consecutive
multiframes.
1 AIS condition is recognized when the alarm indication signal is
received with less than 9 errors in each of 2 consecutive
multiframes.
M12 format:
0 AIS condition is recognized when the alarm indication signal is
received with less than 3 errors in 3156 bits.
1 AIS condition is recognized when the alarm indication signal is
received with less than 9 errors in 3156 bits.
CM Counter Mode
This bit selects the alarm timer mode. If counter mode is set to
multiframes (‘0’) the value in CV determines the number of multiframes
after which the TE3-CHATT declares AIS or RED. When counter mode
is set to ‘½ milliseconds’ (‘1’) the value in CV determines the time in CV
x 0.5 ms after which AIS or RED is declared.
0 Multiframes.
1 ½ Milliseconds.
15 765 0
00000000 AIS CM CV(5:0)
PEB 3456 E
Register Description
Data Sheet 307 05.2001
CV Counter Value
Depe nden t o n bit CM th e co un ter v a lue sp ec if i es t h e n u mb er o f fr am es
or the time in mu ltiples of 0.5 millis econds wh en AIS or RE D is declare d,
i.e. setting CV to 20 and CM to ‘1’ sets the alarm integration time to 10
milliseconds.
0..63 Counter Value.
PEB 3456 E
Register Description
Data Sheet 308 05.2001
8.9.3 Test Unit Registers
TUTCFG
Test Unit Transmit Configuration Register
Access : read/write
Address : 280H (PCI), C0H (Local bus)
Reset Value : 0000H
INV Invert output
This bit enables inversion of the test unit output. Bit inversion is done
after the z ero suppression insertion point.
0 No inversio n
1 Invert pattern generator output
FBT Feedback Tap
This bit field sets the feedback tap in pseudorandom pattern mode.
PRBS shift regis ter in put bi t 0 is XO R of s hif t re gis ter bits LEN and FBT.
LEN Pattern Generator Length
This bit field sets the pattern generator length to 1..32.
ZS Enable Zero Suppression
This bi t enables z ero suppre ssion where a ’1’ bit is inserted at the output
if the next 14 bits in the shift register are ’0’.
0 No zero suppres si on
1 Zero suppression.
MD Generator Mode
This bit selects the generator mode of the test unit to be either PRBS or
fixed pattern mode.
0 Pseudora ndo m Patte rn (PRBS)
1 Fixed Pattern
15 13 12 8 6 2 1 0
00 INV FBT(4:0) 0LEN(4:0)ZSMD
PEB 3456 E
Register Description
Data Sheet 309 05.2001
TUTCOM
Test Unit Transmit Command Register
Access : write
Address : 284H (PCI), C2H (Local bus)
Reset Value : 0000H
Note: All commands are self clearing i.e. user does not have to clear command. The
maximum command rate is limited by clock rate of unit under test and the
associated synchronization process. Write interval should be > 4 transmit clock
periods e.g. 2.6 µs for T1 tributary test or 634 ns for T2 tributary test.
LDE R Load Error Rate Reg ister
This bit loads the value of the error rate register TUTEIR to the test unit
trans mitter. The c omma nd can be given whil e the tr ansmi tter is runnin g.
0 No function.
1 Copy value of register TUTEIR to transmit clock region.
IN1E Insert One Error in Output
This bit enables a single erro r insertion in th e next bit after command was
written.
0 No function
1 Single error insertion.
STOP Stop Pattern Generat ion.
This bit stops the test unit transmitter. When stopped output becomes
all ’1’.
0 No function.
1 Stop pattern generation.
15 3210
000000000000 LDER IN1E STOP STRT
PEB 3456 E
Register Description
Data Sheet 310 05.2001
STRT Load/Start Transmitter.
This bit starts the test unit transmitter with the parameters defined in
register TUTCFG. In fixed pattern mode the pattern needs to be
programmed via register TUTFP0/1 prior to starting the transmitter.
0 No operation.
1 Load/Start test unit.
PEB 3456 E
Register Description
Data Sheet 311 05.2001
TUTEIR
Test Unit Transmit Error Insertion Rate Register
Access : read/write
Address : 288H (PCI), C4H (Local bus)
Reset Value : 0000H
MTST Manufacturing test.
Must be written to ‘0’ for normal operation.
TXER Transmit Error Insertion Rate.
This bit field determines the error insertion rate of the test unit
transmitter.
000 No errors
001 10-1 (1 in 10)
010 10-2 (1 in 100)
011 10-3 (1 in 1 000)
100 10-4 (1 in 10 000)
101 10-5 (1 in 100 000)
110 10-6 (1 in 1 000 000)
111 10-7 (1 in 10 000 000)
15 32 0
000000000000 MTST TXER(2:0)
PEB 3456 E
Register Description
Data Sheet 312 05.2001
TUTFP0
Test Unit Transmit Fixed Pattern Low Word
Access : read/write
Address : 28CH (PCI), C6H (Local bus)
Reset Value : 0000H
FP Fixed Pattern Low Word
See description below.
TUTFP1
Test Unit Transmit Fixed Pattern High Word
Access : read/write
Address : 290H (PCI), C8H (Local bus)
Reset Value : 0000H
FP Fixed pattern High Word
The 32 bit fixed pattern is distributed over two 16 bit registers and
contains the pattern which is transmitted repetitively from bit
FP(TUTCFG.LEN) down to FP(0) when test unit is operated in fixed
pattern generator mode.
15 0
FP(15:0)
15 0
FP(31:15)
PEB 3456 E
Register Description
Data Sheet 313 05.2001
TURCFG
Test Unit Receive Configuration Register
Access : read/write
Address : 2A0H (PCI), D0H (Local b us)
Reset Value : 0000H
AIM Auxili ary Interrup t Mode
This bit field enables the auxiliary interrupt mask AIM of register
TURIMSK. In normal operation and if not masked every status event
generates an interrupt event. In auxiliary interrupt mode an individual
status event generates one interrupt event and further status events of
the same class, i.e. ’Bit Error Detected’, are masked via an internal
mask. This prevents excessive interrupt floods. See register TURIMSK
for further details.
0 Normal Operation
1 Auxiliary Interrupt Mode
DAS Disable Automatic Synchronization
This bit disables automatic resynchronization in case of high bit error
rates. If automatic resynchronization is enables the receiver
automatically tries to resynchronize to the received test pattern.
0 Enable automatic resynchronization.
1 Disable automatic resynchronization.
FBT Feedback Tap
This bi t field sets the fe edback tap of the tes t unit synchroni zer (receiver)
in pseudorandom pattern mode. Next input to PRBS reference shift
register (bit 0) is XOR of shift register bits LEN and FBT.
LEN Reference shift register le ngth
This bit field sets the length of the receiver’s test pattern register.
15 13 12 8 6 2 1 0
AIM 0 DAS FBT(4:0) 0LEN(4:0)ZSMD
PEB 3456 E
Register Description
Data Sheet 314 05.2001
ZS Enable Zero Suppression
This bit enables zero suppression at the test unit receiver. A ’1’ is
expected and inserted at the input if the next 14 bits in the shift register
are set to ’0’.
0 No zero suppres si on.
1 Enable zero suppression.
MD Generator Mode
This bit sets the generator mode of the test unit to either PRBS or fixed
pattern.
0 Pseudora ndo m Patte rn (PRBS)
1 Fixed Pattern
PEB 3456 E
Register Description
Data Sheet 315 05.2001
TURCOM
Test Unit Receive Command Register
Access : write
Address : 2A4H (PCI), D2H (Local b us)
Reset Value : 0000H
Note: All commands are self clearing i.e. user does not have to clear command. The
maximum command rate is limited by clock rate of unit under test and the
associated synchronization process. Write interval should be > 4 transmit clock
periods e.g. 2.6 µs for T1 tributary test or 634 ns for DS2 tributary test.
RDF Copy Receiver’s 32 bit Pattern
This bi t loads th e test uni ts interna l receive r pattern to register TURFP i n
fixed pattern mode. In synchrones state TURFP will be loaded with the
pattern received. In asynchronous state TURFP with a 32-bit sample of
the last received bit stream.
0 No function.
1 Update register TURFP with synchronizer pattern.
RDC Copy bit counter and error counter
This bit loads the test units internal bit counter and error counter to
registers TURBC0,1 and TUREC0,1.
0 No function.
1 Copy cou nte r .
CAIM Clear Auxil iary Interrupt Masks.
This bit resets the internal auxililiary mask. See TURCFG.AIM.
0 no operation
1 clear auxiliary interrupts
STRT Start Receiver.
This bit loads and starts the test unit receiver with the parameters
defined in register TURCFG.
15 43210
00000000000 RDF RDC CAIM STOP STRT
PEB 3456 E
Register Description
Data Sheet 316 05.2001
0 No operation.
1 Load/Start test unit receiver.
PEB 3456 E
Register Description
Data Sheet 317 05.2001
TURERMI
Test Unit Receive Error Measurement Interval Register
Access : read/write
Address : 2A8H (PCI), D4H (Local b us)
Reset Value : 0000H
TST Test Mode
This bit enables measurement interval timer test.
0 Normal operation
1 Auto te st of me asurem ent int erval fu nctio n. End of Meas ureme nt
interrupt should be asserted after approximately 4250 receive
clock cycles (if enabled). The lower three bits of register FPAT
should be “111”.
RXMI Receive Error Rate Measurement Interval
This bit fie ld def ines t he meas uremen t int erval in term s of inp ut bit s for
measurement of receive bit error rate.
At the end of the measurement window, contents of background error
counter are automatically copied to foreground error counter and reset
for nex t measurem en t i nterval. An i nte rrup t can be gene rate d at the en d
of each mea s urem ent in terval.
000BMax measurement interval of 232-1
001B103 bits
010B104 bits
011B105 bits
100B106 bits
101B107 bits
110B108 bits
111B109 bits
15 32 0
000000000000TST RXMI(2:0)
PEB 3456 E
Register Description
Data Sheet 318 05.2001
TURIMSK
Test Unit Receive Interrupt Mask Register
Access : read/write
Address : 2ACH (PCI), D6H (Local bus)
Reset Value : 001FH
This register provides the interrupt masks for the test unit interrupts. Generation of an
interrupt vector itself does not necessarily result in assertion of the interrupt pin. For
description of interrupt concept and interrupt vectors see “Layer One Interrupts” on
Page 137.
The following definition applies:
1 The corresponding interrupt vector will not be generated by the device.
0 The corresponding interrupt vector will be generated.
ERXM Mask ’End of Receive Error Rate Measurement’
BED Mask ’Bit Error Detected’
ALL1 Mask ’All ‘1’ Pattern Received’
LOS Mask ’Loss of Signal’
SYN Mask ’Change in Receiver Synchronization State’
AIM flags have same layout as the above five mask but are internal masks that are set
automat ically follow ing the interrupt in the AIM mo de. This mask prevents exc essive bus
load in error conditions. AIM flags are cleared by the TURCOM.CAIM command. They
are “read only” flags in this register.
15 12 8 43210
000 AIM(4:0) 000 ERXM BED ALL1 LOS SYN
PEB 3456 E
Register Description
Data Sheet 319 05.2001
TURSTAT
Test Unit Receive Status Register
Access : read
Address : 2B0H (PCI), D8H (Local b us)
Reset Value : 0021H
INV Inverted Pattern
This bit indicates that the received PRBS sequence is inverted.
0 Not Inverted.
1 Inverted.
LA1 Latched ’Input all ’1’’
This bit indicates that the condition ’Input all ’1’’ was active since last
status register read.
LA0 Latched ’Input all ’0’’
This bit indicates that the condition ’Input all ’0’’ was active since last
status register read.
LOOS Latched Out of Synchronization
This bit indicates that the receiver was out of synchronization since last
status register read.
EMI End of Measurement Interval
This bi t i ndi cates tha t th e en d of the m eas ure me nt i nternal w as reached
since last read of error counter or that command TURCMD.RDC was
given. The results of the bit error rate test are available in register
TURBC0,1 and TUREC0,1. This flag is cleared when the error counter
is read. Counters will not be overwritten while EMI is ’1’.
LBE Latched Bit Error Detected Flag
This bi t indic ates tha t at leas t ’1’ one bit error occu rred sin ce last read of
this register. It is cleared by status register read.
A1 Input all ‘1’s
This bit indicates that the input contained all ’1’ during the last 32 bits. It
is reset if at least one ’0’ occurs in 32 bits.
15 876543210
0000000INVSLA1LA0LOOSEMILBEA1 A0OOS
PEB 3456 E
Register Description
Data Sheet 320 05.2001
A0 Input all ‘0’s
This bit indicates that the input contained all ’0’ during the last 32 bits. It
is reset if at least one ’1’ occurs in 32 bits.
OOS Receiver Out of Synchronization
This bit indicates the status of the test unit synchronizer.
PEB 3456 E
Register Description
Data Sheet 321 05.2001
TURBC0
Test Unit Receive Bit Counter Low Word
Access : read
Address : 2B4H (PCI), DAH (Local bus)
Reset Value : 0000H
BC(31:0) Bit Counter
See description below.
TURBC1
Test Unit Receive Bit Counter High Word
Access : read
Address : 2B8H (PCI), DCH (Local bus )
Reset Value : 0000H
BC(31:0) Bit Counter
BC is a 32 bit counter which is split between two 16 bits registers. It
counts receive cloc k slots wh en the receiver i s enabled. Bi ts are counte d
in a background register which is not directly readable. The values are
transfer red to th e two 16 bit foreground (readable ) regi sters an d cleare d
in one of the two ways:
1. Assert command TURCOM.RDC.
2. Automatically at end of measurement interval.
The background register is transferred to the foreground register and
cleared in the same way as the bit error counter (s ee previous section).
15 0
BC(15:0)
15 0
BC(31:16)
PEB 3456 E
Register Description
Data Sheet 322 05.2001
When the error registers are read in response to the “End of
Measurement Interval” interrupt vector , reading this register is not
necessary because the measurement interval would be known.
However the user could assert command TURCOM.RDC to terminate
the measurement interval early and transfer the current bit error count
and bit count to the foreground registers (polling mode).
PEB 3456 E
Register Description
Data Sheet 323 05.2001
TUREC0
Test Unit Receive Error Counter Low Word
Access : read
Address : 2BCH (PCI), DEH (Local bus)
Reset Value : 0000H
EC(31:0) Error Counter
See description below.
TUREC1
Test Unit Receive Error Counter High Word
Access : read
Address : 2C0H (PCI), E0H (Local bus)
Reset Value : 0000H
EC(31:0) Error Counter
This 32 bit counter counts receive errors detected when receiver is
enabled and in synchronized state. When the ’Bit Error Detected’
interrupt is enabled, it will be asserted and then automatically masked
when this counter is increm en ted .
Errors are c oun ted in a back gro und regi ste r (not directl y rea dab le) unti l:
1. The user asserts command TURCOM.RDC.
2. The end of measurement interval is reached and the last result was
read.
In both cases the value of the background register is copied to
TUREC.EC and the measured values are accessible. An ’End of
15 0
EC(15:0)
15 0
EC(31:16)
PEB 3456 E
Register Description
Data Sheet 324 05.2001
Receive Error Rate Measurement’ interrupt vector is optionally
generated.
PEB 3456 E
Register Description
Data Sheet 325 05.2001
TURFP0
Test Unit Receive Fixed Pattern Low Word
Access : read
Address : 2C4H (PCI), E2H (Local bus)
Reset Value : 0000H
FP(31:0) Fixed pattern
See description below.
TURFP1
Test Unit Receive Fixed Pattern High Word
Access : read
Address : 2C8H (PCI), E4H (Local bus)
Reset Value : 0000H
FP(31:0) Fixed Pattern
This 32 bi t fiel d is dist ributed ove r two 16 bit reg is ters and is used in the
fixed pattern mode (TURCFG.MD=’1’). The TURCOM.RDF command
will copy the cu rrent state of t he receiver’ s 32 bit patte rn generator to this
register. If the receiver is synchronized, bits FP(TURCFG.LEN:0)
contain the fixed pattern being received. Bit 0 is the most recently
received. If not synchronized, the register contains a 32 bit sample of
input data.
15 0
FP(15:0)
15 0
FP(31:16)
PEB 3456 E
Register Description
Data Sheet 326 05.2001
8.9.4 Transmit Framer Register
TCMDR
T1/E1 Transmit Command Register
Access : read/write
Address : 00H
Reset Value : 0000H
XAP Transmit Auxiliary Pattern
This bit enables transmission of auxiliary pattern in the outgoing bit
stream. The auxiliary pattern is defined as a continuous pattern of ‘01’.
0 Disable transmission of auxiliary pattern.
1 Enable transmission of auxiliary pattern. This function is not
available if bit XAIS is set to ‘1’.
XPRBS Transmit PRBS
This bit enables the transmission of the pseudo-random bit sequence
defined in register TPRBSC.
0 Disable transmission of PRBS.
1 Enable transmission of PRBS.
XAIS Transmit AIS
This bit enables transmission of alarm indication signal towards the
remote end. AIS is an all one unframed signal.
0 Disable transmission of AIS.
1 Enable transmission of AIS.
15 543210
0000000000 XAP XPRBS XAIS XRA XLU XLD
PEB 3456 E
Register Description
Data Sheet 327 05.2001
XRA Transmit Remote Alarm (Yellow Alarm)
This bit enables the transmission of remote alarm in the outgoing bit
stream. Clearing the bit will remove the remote alarm pattern.
T1
0 Disable transmission of remote alarm.
1 Enable transmission of remote alarm. Remote alarm pattern is
selected vi a register FM R.SRAF.
E1
0 Disable transmission of remote alarm.
1 Set A-bit in transmitted service word.
XLU Transmit Line Loopback Actuate (Up) Code
0 Normal operation.
1 A one in this bit position will cause the transmitter to replace
normal transmit data with the line loopback actuate code
continu ously unt il this bit i s reset. The li ne loopbac k actuate cod e
will be optionally overwritten by the framing/DL/CRC bits.
XLD Transmit Line Loopback Deactuate (Down) Code
0 Normal operation.
1 A one in this bit position will cause the transmitter to replace
normal transmit data with the line loopback deactuate code
continuously until this bit is reset. The line loopback deactuate
code will be optionally overwritten by the framing/DL/CRC bits.
PEB 3456 E
Register Description
Data Sheet 328 05.2001
TFMR
T1/E1 Transmit Mode Register
Access : read/write
Address : 01H
Reset Value : 0000H
XAS Automatic Spare Bit Insertion
E1: CRC-4 Multiframe
0 Normal operation. Content of register XSP.XS13 and XSP.XS15
is inserted in the E-Bit of time slot 0 in frame 13 and frame 15
respectively.
1 Submultiframe status will be automatically set in the outgoing
data stream. Each received, errored submultiframe causes bit
one of ti me sl ot 0 o f f rame 13 a nd fr ame 15 t o be ‘ 0’. Othe rwi se
these bits are set to ‘1’.
AXRA Autom at ic Tran sm it Re mo te Alarm
Setting this bit enables automatic transmission of remote alarm.
0 Normal operation.
1 The Remote Alarm (yellow alarm) bit will be automatically set in
the outgoing data stream if the receiver is in asynchronous state
(FRS.LFA bit is set). In synchronous state the remote alarm bit
will be reset.
15 543210
0000000000 XAS AXRA SRAF T1E1 FM(1:0)
PEB 3456 E
Register Description
Data Sheet 329 05.2001
SRAF Select Remote (Yellow) Alarm Format
Setting thi s bit enable s the remote ala rm forma t in T1 mode. This bit has
no function in E1 mode.
T1: F4
1 Bit 2 = 0 in every channel
T1: F12
0 FS bit of frame 12.
1 Bit 2 = 0 in every channel.
T1: ESF
0 Pattern ‘1111 1111 0000 0000…’ in data link channel.
1 Bit 2 = 0 in every channel.
T1E1 T1/E1 mode selection
This bit switches the transmit framer into T1 and E1 mode.
0 Select T1 mode.
1 Select E1 mode.
FM Select Frame Mode
This bit field determines the framing mode of the transmit framer.
T1
00BSelect ESF format.
01BSelect F12 format.
10BSelect F4 format.
Other Reserved
E1
00BSelect Double frame format.
01BSelect CRC-4 multiframe format.
Other Reserved
PEB 3456 E
Register Description
Data Sheet 330 05.2001
TLCR0
T1/E1 Transmit Loop Code Register 0
Access : read/write
Address : 02H
Reset Value : 0000H
FLLB Disable Framed Line Loopback
This bit switches between framed and unframed transmission of line
loopba ck. In unframed transmission the FS/DL bit the line loopback code
overwrites the FS/DL bits, while in framed transmission the FS/DL bits
will not be overwr itt en by the line loop bac k code.
0 Set framed line loopbac k transmission.
1 Set unframed line loopback transmission.
LCS Loop Code Select
This bit sw itch es betwee n line loo pba ck code defi ned in AN SI T1.403 or
a user definable loopback code defined in register TLCR1.
0 Select ANSI codes.
1 Select line loopback code defined in register TLCR1.
LDCL Line Loopback Deactuate Code Length
This bit field determines the length of the line loopback deactuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
LACL Line Loopback Actuate Code Length (5-8 bit)
This bit field determines the length of the line loopback actuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write
001001 to TLCR1 register and define code length of 6 bits.
15 14 9 8 1 0
FLLB LCS 0000 LDCL(1:0) 000000 LACL(1:0)
PEB 3456 E
Register Description
Data Sheet 331 05.2001
TLCR1
T1/E1 Transmit Loop Code Register 1
Access : read/write
Address : 03H
Reset Value : 0000H
LDC Line Loopback Deactuate Code
This bit field is sent in the outgoing bit stream if enabled via bit
TCMDR.XLD and TLCR0.LCS.
Note: Most significan t bit is sent f irst. E.g. TC LR0.LDCL = 01B specifie s
code length to be six bits long. In this case LDC(5) is sent first.
LAC Line Loopback Actuate Code
This bit field is sent in the outgoing bit stream if enabled via bit
TCMDR.XLU and TLCR0.LCS.
Note: Most signi ficant bit is sen t firs t. E.g. TCLR0 .LACL = 0 1B speci fies
code length to be six bits long. In this case LAC(5) is sent first.
15 8 7 0
LDC(7:0) LAC(7:0)
PEB 3456 E
Register Description
Data Sheet 332 05.2001
TPRBSC
T1/E1 Transmit PRBS Control Register
Access : read/write
Address : 04H
Reset Value : 001FH
FPRBS Framed PRBS
This bit field enables framed or unframed transmission of the pseudo-
random bit sequence.
0 Transmit framed PRBS.
1 Transmit unframed PRBS.
IPRBS Invert PRBS
This bit field enables inversion of the pseudo-random bit sequence in
transmit direction.
0 PRBS is not inverted.
1 PRBS is inverted.
PRP Pseudo-Random Pattern
This bit field determines the generator polynomial for the pseudo-
random bit sequence.
00BPRBS is generated according to 215 -1 (ITU-T O. 1 5 1)
01BPRBS is generated according to 220 -1 (ITU-T O. 1 5 1)
1-BFor PRBS the fixed pattern, defined in TFPR0 and TFPR1, is
selected.
FPL Fixed Pattern Length
This bit field sets the length of the fixed pattern FP which is located in
register TFPR0 and TFPR1. E.g.: FPL(4:0) = 10010B means pattern
length is equal to 19, which implies that the bits FP(18)..FP(0) form the
PRBS.
15 12 9 8 4 0
FPRBS 00IPRBS00PRP(1:0)000FPL(4:0)
PEB 3456 E
Register Description
Data Sheet 333 05.2001
TFPR0
T1/E1 Transmit Fixed Pattern Register Low Word
Access : read/write
Address : 05H
Reset Value : 0000H
FP(31:0) Fixed Pattern Low Bytes
See description below.
TFPR1
T1/E1 Transmit Framer Fixed Pattern Register High Word
Access : read/write
Address : 06H
Reset Value : 0000H
FP(31:0) Fixed Pattern High Bytes
This bit field together with bit field TFPR0.FP defines a bit sequence,
whic h c an b e s ent ins te ad of a pse udo-random bi t se quence. F P is se nt
in the order FP(TPRBSC.FPL-1) down to FP(0) and will be repeated until
deactivated.
15 0
FP(15:0)
15 0
FP(31:16)
PEB 3456 E
Register Description
Data Sheet 334 05.2001
TPTSL0
T1/E1 Transmit PRBS Time Slot Number Register Low Word
Access : read/write
Address : 07H
Reset Value : FFFFH
TSL(31:0) Time slot 15..0 Select
See description below.
TPTSL1
T1/E1 Transmit PRBS Time Slot Number Register High Word
Access : read/write
Address : 08H
Reset Value : 00FFH
TSL(31:0) Time slot 31..16 Select
Selected bits in bit field TSL and TPTSL0.TSL determine those time
slots, which are used for PRBS generation. Time slots can be
programmed arbitrarily. E.g. if TPTSL0.TSL(1) and TPTSL0.TSL(2) are
set to ‘ 1’, the PR BS i s s ent c ont inu ous ly o ve r b oth time s lo ts c om bin ed.
15 0
TSL(15:0)
15 0
TSL(31:16)
PEB 3456 E
Register Description
Data Sheet 335 05.2001
XSP
T1/E1 Transmit Spare Bit Register
Access : read/write
Address : 09H
Reset Value : 0000H
XS13, XS15 Transmit Spare Bit
E1: CRC-4 Multiframe
Depen dent o n bit F MR.XAS and frame r mode spare bits of servic e wo rd
in CRC-4 multiframe 13 and 15 are replaced by XS13 and XS15.
15 10
00000000000000 XS13 XS15
PEB 3456 E
Register Description
Data Sheet 336 05.2001
8.9.5 Receive Framer Registers
RCMDR
T1/E1 Recei ve Command Regist er
Access : read/write
Address : 00H
Reset Value : 0000H
SIM Alarm Simulation
This bit field enables alarm simulation in the receive framer. See codes
for specific function.
0000BDisa ble alarm simulation.
0001BSimulate loss of signal
Setting this code:
- Generate ’Loss of Signal Status’ interrupt vector.
- Flag ’Los s of Signal’ via bit FSR.LOS.
- Generate PDEN interrupt vector.
- Flag ’Pul se Density Code Violation Det ected’ via bit FSR.PDEN/
AUX.
Removing this code:
- Generate ’Loss of Signal Status’ interrupt vector.
- Remove signalling of ’Loss of Signal’.
- Generate PDEN interrupt vector.
- Remove signalling of ’Pulse Density Code Violation Detected’.
0010BSimulate Alarm Indication Signal
Setting this code:
- Generate ’Loss of Frame Alignment’ interrupt vector.
- Flag ’Loss of Frame Alignment’ via bit FRS.LFA.
- Generate ’Alarm Indication Signalled’ interrupt vector.
- Flag ’Alarm Indication Signalled’ via bit FRS.AIS.
15 5 4 1 0
00000000000 SIM(3:0) FRS
PEB 3456 E
Register Description
Data Sheet 337 05.2001
Removing this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Generate ’Alarm Indication Signal Status’ interrupt vector.
- Remove signalling of ’Alarm Indication Signalled’.
0011BSimulate auxilia ry patt ern (’...010101 ...’ pat tern )
This seq uence simulates also los s of frame (required for auxil iary
pattern).
Setting this code:
- Generate ’Auxiliary Pattern Status’ interrupt vector.
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Flag ’Los s of Signal’ via bit FRS.LF A.
- Flag ’Auxiliary Pattern detected’ via bit FRS.PDEN/AUX.
- Flag ’Loss of M ultiframe Alignment’ via bit FRS.L MFA (CRC-4
Multiframe mode).
- Increment framing error counter by 3 or 4 depending on
RFMR.SSP
Removing this code:
- Generate ’Auxiliary pattern Status’ interrupt vector.
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Remove signalling of FRS.PDEN/AUX.
- Remove signalling of ’Loss of Multiframe Alignment’.
0100BSimulate loss of frame
Setting this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Flag ’Los s of Signal’ via bit FRS.LF A.
- Flag ’Loss of M ultiframe Alignment’ via bit FRS.L MFA (CRC-4
multiframe mode).
- Increment framing error counter by 2, 3, or 4 (depends on
RFMR.SSP).
- Increment error ed sec on ds (T1 mod e only ).
Removing this code:
- Generate ’Loss of Frame Alignment Status’ interrupt vector.
- Remove signalling of ’Loss of Frame Alignment’.
- Remove signalling of ’Loss of Multiframe Alignment’.
PEB 3456 E
Register Description
Data Sheet 338 05.2001
0101BSimulate remote ala rm
Setting this code:
- Generate ’Remote Alarm Status’ interrupt vector.
- Flag ’Received Remote Alarm’ bit FRS.RRA.
Removing this code:
- Generate ’Remote Alarm Status’ interrupt vector.
- Remove signalling of ’Receive Remote Alarm’.
0110BSimula te CRC error (T1 ESF or E1 CRC-4 multiframe mode)
Setting this code:
- Generate CRC interrupt vector.
- Increment CRC error co unte r.
Removing this code:
- Stop generation of CRC interrupt vect or.
- Stop incremen t of CRC error counte r.
FRS For ce Resynchroni zation
A transition from low to high will force the frame aligner to execute a
resynchronization of the pulse frame. The procedure depends on the
status of bit FMR.SSP.
0 No operation.
1 Change from ’0’ to ’1’ forces resynchronization.
PEB 3456 E
Register Description
Data Sheet 339 05.2001
RFMR
T1/E1 Recei ve Mod e Regi ste r
Access : read/write
Address : 01H
Reset Value : 0000H
LOSR Loss of Signal Recovery
This bit sets the conditions for ’Loss of Signal’ detection.
T1
0 Loss of signal cleared, when pulse density defined by register
PCR is d etec te d du rin g a time in terv al de cla red by regi ster PCD.
1 Loss of signal cleared, when pulse frame density defined by
register PCR is detected during a time interval declared by
register PCD and a pulse density of at least N ‘1’s in every N+1
octets (0 <N<24) during reco ve ry interval defi ned in re gis ter PCD
is de tect ed.
E1
0 Loss of signal cleared, when pulse density defined by register
PCR is d etec te d du rin g a time in terv al de cla red by regi ster PCD.
1 No function.
ALMF Au tomatic Loss of Mul tifra me
This bit selects condition for automatic loss of multiframe.
T1
0 CRC errors do not cause loss of frame alignment.
1 320 or more CRC errors in one second cause loss of frame
alignment.
E1
0 CRC errors do not cause loss of frame alignment.
1 915 or more CRC-4 errors in one second cause loss of frame
alignment.
15 111098765 3210
0000 LOSR ALMF RRAM AIS3 SSP SSC(1:0) 0 SRAF T1E1 FM(1:0)
PEB 3456 E
Register Description
Data Sheet 340 05.2001
RRAM Receive Remo te Alarm Mod e
The conditions for remote (yellow) alarm detection can be selected via
this bit to allow detection even in the presence of BER 10-3. Remote
alarm detection is flagged in register FRS.RRA and can be signalled as
an interrupt.
T1: F4
0 Normal operation
Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no longer
detected.
1 Detection with BER 10-3
Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm will b e res et w he n receiv er do es not de tec t the Bit 2 =
’0’ condition for three consecutive pulseframes.
T1: F12
0 Normal operation
Depending on bit FMR0.SRAF:
0 Detection:
FS-bit of frame 12 is forced to ‘1’.
Release:
The alarm will be reset when above conditions are no
longer detected.
1 Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no
longer detected.
1 Detection with BER 10-3
Remote alarm detection depending on bit FMR0.SRAF:
0 Detection:
FS-bit of frame 12 is forced to ‘1’.
Release:
The alarm w il l be res et whe n rec eiv er do es not det ect the
’Fs-bit’ condition for three consecutive multiframes.
PEB 3456 E
Register Description
Data Sheet 341 05.2001
1 Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm w il l be res et whe n rec eiv er do es not det ect the
Bit 2 = ’0’ condition for three consecutive pulseframes.
T1: ESF
0 Normal operation
Remote alarm detection depending on bit FMR0.SRAF:
0 Detection
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Release:
The alarm will be reset when above conditions are no
longer detected.
1 Detection:
Bit 2 = ‘0’ in every speech channel per frame.
Release:
The alarm will be reset when above conditions are no
longer detected.
1 Detection with BER 10-3
Remote alarm detection depending on bit FMR0.SRAF:
0 Detection
Pattern ‘1111 1111 0000 0000…’ in data link channel.
Release:
The alarm wi ll be re set w he n rec eiv er doe s not de tec t ‘ DL
pattern’ for three times in a row.
1 Detection:
Bit 2 = ‘0’ in 255 consecutive speech channels.
Release:
The alarm w il l be res et whe n rec eiv er do es not det ect the
Bit 2 = ’0’ condition for three consecutive pulseframes.
AIS3 Select AIS Condition
This bit selects the condition which leads to AIS reporting.
T1: F4, F12
0 AIS (blue alarm) is indicated, when two or less zeros in the
received bit stream are detected in a time interval of 12 frames.
1 AIS (blue alarm) detection is only enabled, when framer is in
asynchronous state. The alarm is indicated, when three or less
PEB 3456 E
Register Description
Data Sheet 342 05.2001
zeros within a time interval of 12 frames are detected in the
received bit stream.
T1: ESF
0 AIS (blue alarm) is indicated, when two or less zeros in the
received bit stream are detected in a time interval of 24 frames.
1 AIS (blue alarm) detection is only enabled, when framer is in
asynchronous state. The alarm is indicated, when five or less
zeros within a time interval of 24 frames are detected in the
received bit stream.
SSP Select Synchronization/Resynchronization Procedure
T1: F12
0 Specified number of errors in FT framing or specified number of
errors in FS framing leads to loss of synchronization (FRS.LFA).
In the case of FS bit framing errors, bit FRS.LMFA is set
additionally. A complete new synchronization procedure is
initiated to regain pulseframe alignment and then multiframe
alignment.
1 Spe ci f ied nu mb er of er ro r s in FT fr am in g ha s t he same ef fe ct as
above. Specified number of errors in FS framing only initiates a
new search for multiframe alignment without influencing
pulseframe synchronous state (FRS.LMFA is set).
T1: ESF
0 Synchronization is achieved only on verification of the framing
pattern.
1 Synchronous s tate is reached when framing pa ttern and CRC-6
checksum are correctly found.
SSC Select Synchronization Conditions
T1
Loss of Frame Alignment (F RS.LFA or o pt. FRS.LMFA) is declared if
00B2 out of 4 framing bits
01B2 out of 5 framing bits
10BF12
2 out of 6 framing bits
ESF
2 out of 6 framing bits per multiframe period
11B4 consecutive incorrect multiframe pattern
It depends on the selected multiframe format and optionally on bit
FMR.SSP which framing bits are observed:
PEB 3456 E
Register Description
Data Sheet 343 05.2001
F12 SSP = 0: FT bits → FRS.LFA: FS bits → FRS.LFA and
FRS.LMFA SSP = 1:FT → FRS.LFA
FS → FRS.LMFA
ESF ESF framing bits → FRS.LFA
E1
00B3 out of 4 consecutive FAS or service word errors
01B4 out of 4 consecutive FAS or service word errors
10B3 out of 3 FAS errors
11B4 out of 4 FAS errors
SRAF Select Remote (Yellow) Alarm Format
This bit is valid for T1 mode only.
T1: F4
0/1 Bit 2 = ‘0’ in every channel.
T1: F12
0 FS bit of frame 12.
1 Bit 2 = ‘0’ in every channel.
T1: ESF
0 Pattern ‘1111 1111 0000 0000…’ in data link channel.
1 Bit 2 = ‘0’ in every channel.
T1E1 T1/E1 Mode Selection
This bit switches the receive framer into T1 or E1 mode.
0 Select T1 mode.
1 Select E1 mode.
FM Select Frame Mode
This bit field selects the framing mode of the receive framer.
T1
00BESF-Format
01BF12-Format
10BF4-Format
Other Reserved
E1
00BDoubleframe
01BCRC-4
10BCRC-4 Interworking mode
Other Reserved
PEB 3456 E
Register Description
Data Sheet 344 05.2001
RLCR0
T1/E1 Recei ve Loop Code Register 0
Access : read/write
Address : 02H
Reset Value : 0000H
LCS Loop Code Select
This bit sw itch es betwee n line loo pba ck code defi ned in AN SI T1.403 or
a user definable loopback code defined in register RLCR1.
0 Select ANSI codes.
1 Select line loopback code defined in register RLCR1.
LDCL Line Loopback Deactuate Code Length
This bit field determines the length of the line loopback deactuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
LACL Line Loopback Actuate Code Length (5-8 bit)
This bit field determines the length of the line loopback actuate code
specified in register TLCR1. The length of the loopback code can be
specified in a range of 5 to 8 bits.
00B..11BSpecifies code length in the range of 5 to 8 bits.
Note: Codes of smaller length might be activated by multiple entry, e.g. code 001: write
001001 to LCR1 register and define code length of 6 bits.
15 14 9 8 1 0
0LCS0000 LDCL(1:0) 000000 LACL(1:0)
PEB 3456 E
Register Description
Data Sheet 345 05.2001
RLCR1
T1/E1 Recei ve Loop Code Register 1
Access : read/write
Address : 03H
Reset Value : 0000H
LDC Line Loopback Deactuate Code
This in comi ng bit stre am will be compared against this bit fi eld if enabled
via bit RLCR0.LCS.
Note: Most significan t bit is sent f irst. E.g. TC LR0.LDCL = 01B specifie s
code length to be six bits long. In this case LDC(5) is sent first.
LAC Line Loopback Actuate Code
This in coming bit stre am will be compared against this bit fi eld if ena bled
via bit RLCR0.LCS.
Note: Most signi ficant bit is sen t firs t. E.g. TCLR0 .LACL = 0 1B speci fies
code length to be six bits long. In this case LAC(5) is sent first.
15 8 7 0
LDC(7:0) LAC(7:0)
PEB 3456 E
Register Description
Data Sheet 346 05.2001
RPRBSC
T1/E1 Recei ve PRBS Control R egis ter
Access : read/write
Address : 04H
Reset Value : 001FH
EPRM Enable PRBS Monitor
This bit enables the PRBS monitoring function. When PRBS monitor is
enabled the pseudo-random pattern synchronizer logs onto the
pseudo-random pattern defined in PRB.
0 PRBS monitor is disabled.
1 PRBS monitor is enabled.
PRP Pseudo-Random Pattern
00BThe incoming pattern is compared according to 215 -1 (ITU-T
O.151)
01BThe incoming pattern is compared according to 220 -1 (ITU-T
O.151)
11BThe incomin g pattern is com pared to the fixed pa ttern, defi ned in
RFPR0 and RFPR1. The pattern length is defined in FPL.
Other Reserved
FPL Fix ed Pat tern Length, e.g .: =10 010 means pattern length is equ al to 19,
which implies that the bits RFPR1/0.FP(18)..FP(0) form the PRBS.
15 13 9 8 4 0
00 EPRM 000PRP(1:0)000FPL(4:0)
PEB 3456 E
Register Description
Data Sheet 347 05.2001
RFPR0
T1/E1 Receive Fixed Pattern Register Low Word
Access : read/write
Address : 05H
Reset Value : 0000H
FP Fixed Pattern Low Bytes
See description below.
RFPR1
T1/E1 Receive Fixed Pattern Register High Word
Access : read/write
Address : 06H
Reset Value : 0000H
FP Fixed Pattern High Bytes
This bit field together with RFPR0.FP defines a bit sequence, which will
be monitored in the PRBS synchronous state. FP is compared in the
order FP(RPRBSC.FPL-1) down to FP(0) and comparison will be
repeated until deactivated.
15 0
FP(15:0)
15 0
FP(31:16)
PEB 3456 E
Register Description
Data Sheet 348 05.2001
RPTSL0
T1/E1 Receive PRBS Time Slot Number Register Low Word
Access : read/write
Address : 07H
Reset Value : FFFFH
TSL Time slot 15..0 Select
See description below.
RPTSL1
T1/E1 Receive PRBS Time Slot Number Register High Word
Access : read/write
Address : 08H
Reset Value : 00FFH
TSL Time slot 31..16 Select
Selected bits in bit field TSL and RPTSL0.TSL determine those time
slots, which are used for PRBS monitoring. Time slots can be
program me d arb itrar il y. E. g. if RP TSL0 .TSL( 1) an d RP TSL 0.TSL (2) a re
set to ‘1’, the PRBS is monitored continuously over both time slots
combined.
15 0
TSL(15:0)
15 0
TSL(23:16)
PEB 3456 E
Register Description
Data Sheet 349 05.2001
IMR
T1/E1 Recei ve Interr up t Mask Register
Access : read/write
Address : 09H
Reset Value : 0000H
For each framer interrupt vector an interrupt vector generation mask is provided.
Generation of an interrupt vector itself does not necessarily result in assertion of the
interrupt pin. For description of interrupt concept and interrupt vectors see “Layer One
Interrupts” on Page 137.
The following definition applies:
1 The corresponding interrupt vector is suppressed by the device.
0 The corresponding interrupt vector is generated.
T400 Mask ’400 millisecond Timer’
CRC Mask ’CRC Error’
PDEN/AUX Mask ’Pulse Density / Auxiliary Pattern’
FAS Mask ’Frame Alignment Status’
MFAS Mask ’Multiframe Alignment Status’
AIS Mask ’Alarm Indication Status’
LOSS Mask ’Loss of Signal Status’
RAS Mask ’Remote Alarm Status’
ES Mask ’Errored Second’
SEC Mask ’One Second Tick’
LLBS Mask ’Line Loopback Status’
PRBSS Mask ’PRBS Status’
15 11109876543210
0000T400CRC
PDEN
/AUX FAS MFAS AISS LOSS RAS ES SEC LLBS PRBSS
PEB 3456 E
Register Description
Data Sheet 350 05.2001
RFMR1
T1/E1 Recei ve Mod e Regi ste r 1
Access : read/write
Address : 0AH
Reset Value : 0000H
FRST For ce Resynchronization Timer
This bit field defines the time after which the framer automatically starts
resynchronization if Emulator Automatic Check Mode is enabled.
0..7 Automatic resynchronization after (FRST+1)*8 milliseconds.
EACM Enable Emulator Automatic Check Mode
This bit enables automatic resynchronization mode. After loss of frame
the receive framer starts resynchronization after (FRST+1)*8ms when
frame search is not started by system software. If EACM is disabled
system software has to force resynchronization by setting bit
RCMDR.FRS.
ECM Error Counter Mode
0 Unbuffered error counter mode. Counters are updated when
respective error occurs. Counter registers are directly readable
and cleared automatically at the end of a read cycle.
1 Buffered error counter mode. Actua l error counts are hidden fro m
user and updated in backgrou nd. The counter is copied to the bus
register at one second intervals and reset automatically. This
operation is synchronous with the periodic one second interrupt
which alerts software to read the register.
15 4 210
00000000000 FRST(2:0) EACM ECM
PEB 3456 E
Register Description
Data Sheet 351 05.2001
PCD
T1/E1 Receive Pulse Count Detection Register
Access : read/write
Address : 0BH
Reset Value : 0015H
PCD Pulse Count Detection
A ’Loss of Signal ’ alarm wi ll be dete cted, if t he incom ing data stream ha s
zero octets for a programmable number T of consecutive octets. The
number T is programmable via the PCD register and can be calculated
as follows:
T = 8*(PCD+1), 1 ≤ PCD ≤ 63.
E.g. PCD = 21 sets loss of signal threshold to 176 (=(21+1)*8) zeros.
Note: For T1 mode time detection interval has cumulative uncertainty
of 1 per 193 clocks.
15 5 0
0000000000 PCD(5:0)
PEB 3456 E
Register Description
Data Sheet 352 05.2001
PCR
T1/E1 Receive Pulse Count Recovery Register
Access : read/write
Address : 0CH
Reset Value : 0015H
PCR Pulse Count Rec overy
’Loss of Signal’ alarm will be cleared, when a programmable pulse
density is detected in the received bit stream. A pulse is a logical ’1’ in
the received bit stream. The number of pulses M which must occur in a
certain time interval, which is programmable via register PCR, can be
calculated as follows:
M = PCR, 1 ≤ PCR ≤ 63.
Additional ’Loss of Signal’ recovery condition may be selected by using
RFMR.LOSR.
15 5 0
0000000000 PCR(5:0)
PEB 3456 E
Register Description
Data Sheet 353 05.2001
FRS
T1/E1 Recei ve Status Register
Access : read/write
Address : 40H
Reset Value : 0000H
Each bit in th e framer rec eive status re gister de clare s a spec ific condi tion dep en dent on
the selected modes. The following convention applies to the individual bits:
0 The named status is not or no longer existing.
1 The named status is currently effective.
The chang e of status bit (exc ep t FS RF) can also be us ed to gen erat e a fram er in terru pt
vector. See also register IMR which describes how to enable/disable interrupt vector
generation and refer to the description of framer interrupt vector on page “Layer One
Interrupts” on Page 137.
NMF No Mu ltiframe Found
E1: CRC-4 Interworking
This bit is set, if no multiframe is found after 400 milliseconds.
LOS Loss of Signal (Red Alarm)
This bit is set, when the ’Loss of Signal’ condition has been detected.
T1
Detection
An alarm w ill be gen erat ed if the in com in g d ata stream rem ain at l ogi ca l
zero for 168 cycles.
Recovery
The recov ery procedure starts af ter detecting a lo gical 1. The LOS alar m
is cleared if 21 one’s are detected within 168 bits (12.5%).
E1
see T1 and “Erro r Performance Monitori ng and Alar m Handlin g” on
Page 98.
15141312111098 3210
0 NMF LOS AIS LFA RRA LMFA FSRF 0 0 0 0 PDEN
AUX LLBDD LLBAD PRBS
PEB 3456 E
Register Description
Data Sheet 354 05.2001
AIS Alarm Indication Signal (AIS)
This bit is set, when the alarm indication condition defined by bit
RFMR.AIS3 has been detected. The flag stays active for at least one
multiframe. It will be reset with the beginning of the next following
multiframe, if no alarm condition is detected.
LFA Loss of Fram e Alignment
T1
This bit is set, when the ’Loss of Frame Alignment’ co ndit ion defined by
bits RFMR .SSP and RFMR .SSC has been d etected. The flag is cleared,
when synchronization has been regained.
E1
This bit is set, when the ’Loss of Frame Alignment’ co ndit ion defined by
bit RFMR.SSC has been detected. The flag is cleared, when
synchronization has been regained.
RRA Received Remote Alarm (Yellow Alarm)
Condition for receive remote alarm is defined by bit FMR.RRAM. The
flag is set after detecting remote alarm (yellow alarm).
LMFA Loss of Multiframe Alignment
T1: F12
This bit is set, when the condition for ’Loss of Multiframe Alignment’
defin ed by bit RFMR.SSC has been de tected . The flag is clear ed after
multiframe synchronization has been regained.
E1: CRC-4 Multiframe, CRC-4 Interworking
This bit is set in CRC-4 multiframe or CRC-4 inte rworking mode, when
double frame alignment is lost. This bit is reset, when the multiframe
pattern is acquired or after 400 milliseconds in CRC-4 interworking
mode, when N MF is asserted.
FSRF Frame Search Restart Flag
This bit toggles on each new pulse frame search started. This function
can be used to recognize multiple candidates. If FSRF does not toggle,
but LFA and LMFA remain active, the synchronizer has multiple
candidates and cannot determine which one is correct.
Note: This flag can not be used to generate an interrupt vector.
PEB 3456 E
Register Description
Data Sheet 355 05.2001
PDEN/AUX T1
Pulse Density Code Violation Detected
This bit is set, when the pulse density of the received data stream is
below the requirement defined by ANSI T1.403.
E1
Auxili ary Patte rn Detec ted
This bit is set, when the pattern ’...010101...’ has been detected
concurrent with loss of frame.
LLBDD Line Loop-Back Deactuation Signal Detected
This b it is s et, w hen l ine lo opback dea ctuate s ign al is d ete cte d and the n
received over a period of more than 33,16ms with a bit error rate less
than 1/100. The bit remains set as long as the bit error rate does not
exce ed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation. If frame alignment state is not
synchronized, all received data bits are searched for the LLBD pattern.
LLBAD Line Loop-Back Actuation Signal Detected
This bit is set to one in case the LLB actuate signal is detected and then
received over a period of more than 33,16ms with a bit error rate less
than 1/100. The bit remains set as long as the bit error rate does not
exce ed 1/100.
If framing is aligned, the first bit position of any frame is not taken into
account for the error rate calculation. If frame alignment state is not
synch ron iz ed, all receive dat a bits are searc hed for the LLBA pattern.
PRBS PRBS status
This bit is set, when the PRBS receiver is in the synchronous state. It is
set high if the synchronous state is reached even in the presence of a
BER 1/10. A data stream containing all zeros with / without framing bits
is also a valid pseudo-random bit sequence.
PEB 3456 E
Register Description
Data Sheet 356 05.2001
FEC
T1/E1 Recei ve Frami ng Error Counter
Access : read/write
Address : 41H
Reset Value : 0000H
FE Framing Error Counter
The counter will not be incremented during asynchronous state. Error
count er mode (Cl ear on Rea d or Errore d Second ) depen ds on regi ster
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1: F12
The counter will be incremented when incorrect FT and FS bits are
received.
T1: ESF
The c ount er will be incremented when incorrect FAS bits are received.
E1
The counter will be incremented when incorrect FAS words are received.
15 0
FE(15:0)
PEB 3456 E
Register Description
Data Sheet 357 05.2001
CEC
T1/E1 Recei ve CRC Erro r Counter
Access : read/write
Address : 42H
Reset Value : 0000H
CR CRC Errors
The counter will not be incremented during asynchronous state. Error
count er mode (Cl ear on Rea d or Errore d Second ) depen ds on regi ster
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1: F12
No function.
T1: ESF
The counter will be incremented when a multiframe has been received
with a CRC error.
E1: Doubleframe
No function.
E1: CRC-4 Multiframe
In CRC-4 multiframe mode the counter will be incremented when a
submultiframe has been received with a CRC error.
15 0
CR(15:0)
PEB 3456 E
Register Description
Data Sheet 358 05.2001
EBC
T1/E1 Recei ve Erro red Blo ck Counter
Access : read/write
Address : 43H
Reset Value : 0000H
EB E-Bit or Errored Block counter
The counter will not be incremented during asynchronous state. Error
count er mode (Cl ear on Rea d or Errore d Second ) depen ds on regi ster
RFMR1.ECM. In errored second mode the counter is 10 bit wide,
otherwise 16 bit.
T1
The counter will be incremented once per multiframe if a submultiframe
has been received with a CRC error or an errored frame alignment has
been detected.
E1: Doubleframe
No function.
E1: CRC-4 Multiframe
The counter will be incremented each time the framer receives a CRC-4
multiframe with Si bit in frame 13 or frame 15 set to zero.
15 0
EB(15:0)
PEB 3456 E
Register Description
Data Sheet 359 05.2001
BEC
T1/E1 Recei ve Bit Error Coun ter
Access : read/write
Address : 44H
Reset Value : 0000H
BE Bit Error Counter
Error counter mode (Clear on Read or Errored Second) depends on
register RFMR1.ECM. In errored second mode the counter is 10 bit
wide, otherwise 16 bit.
T1
This bit counter will be incremented with every received PRBS bit error
in the PRBS synchronous state.
15 0
BE(15:0)
PEB 3456 E
Register Description
Data Sheet 360 05.2001
8.9.6 Facility Data Link Registers
Facility data link registers control the signalling channels of T1, E1 as well as the
signal lin g ch ann els of the DS3 C- bit p arity form at (Pa th M ain tena nc e D ata Link and Far
End Alarm and Control Channel).
RCR1
Receive Channel Configuration Register 1
Access : read/write
Address : 00H
Reset Value : 0000H
RAH2 Receive Address High Byte 2 Valid
This bit enables byte RAH.RAH2 for address comparison.
0Disable
1 Enable
RAH1 Receive Address High Byte 1 Valid
This bit enables byte RAH.RAH1 for address comparison.
0Disable
1 Enable
RTF RFIFO Threshold Level
This b it field s ets the threshold of the rec eive FIF O and is a pplied to both
pages of the receive FIFO. A ’Receive Pool Full’ interrupt vector will be
generated, when the programmed threshold is reached. The threshold
value is given as follows:
00B32 byte threshold
01B16 byte threshold
10B4 by te th reshold
11B2 by te th reshold
1514131211109876543210
0 RAH2 RAH1 RTF(1:0) INV RIFTF BFE BRM BRAC RAL2 RAL1 XCRC CRC
DIS RON HDLC
PEB 3456 E
Register Description
Data Sheet 361 05.2001
INV Invert data input from Receive Framer
This bit enables data inversion between receive framer and receive
signalling controller.
0 Disable data Inversion.
1 Enable data inversion.
RIFTF Report Interframe Time-fill Change
This bit selects, that interframe time-fill changes should be reported.
0 Disable IFF status messages.
1 Enable IFF status messages.
BFE Ena ble BOM Filter Mode
This bit selects, that byte oriented messages have to be filtered. The
BOM is reporte d only if 7 out 10 data is receiv ed. This bit is valid in BOM
mode only.
0 Disable BOM filter mode.
1 Enable BOM filter mode.
BRM BOM Receive Mode
This b it sw itche s cont inuou s and 10 by te pac ket re cepti on of t he rec eive
signalling controller. This bit is valid in BOM mode only.
0 Enable continuous reception.
1 Enable 10 bytes packets.
BRAC BOM Receiver Active
T1: ESF
This bit switches the BOM receiver to operational state (on) or
inoperational state (off). When BOM Receiver is switched on, an
automa tic sw itch ing be tween HDLC m ode and BOM m ode is enabl ed. If
eight or more consecutive ’1’s are detected, the BOM mode is entered.
Upon detection of a flag in the data stream, the signalling controller
switches back to HDLC mode.
0 Switch BOM receiver off.
1 Switch BOM r eceiver on.
RAL2 Receive Address Low Byte 2 Valid
This bit enables byte RAL.RAL2 for address comparison.
0Disable
1 Enable
PEB 3456 E
Register Description
Data Sheet 362 05.2001
RAL1 Receive Address Low Byte 1 Valid
This bit enables byte RAL.RAL1 for address comparison.
0Disable
1 Enable
XCRC Transfer CRC to RFIFO
This bit defines, that CRC of incoming data packets shall be transferred
to the receive FIFO or not.
0 No transfe r of CRC to RFIFO.
1 Transfer of CRC to RFIFO.
CRCDIS CRC Check Disable
This bit enables or disa bles the CRC check of incomi ng data packets.
0 Enable CRC check.
1 Disable CRC check.
RON Receiver On/Off
This bit switches the receiver of the facility data link channel to
operational (on) or inoperational state (off).
0 Switch receiver off.
1 Switch receiver on.
HLDC HDLC Mode
This bit identifies the protocol mode of the facility data link receiver.
0 Set protocol mode to transparent.
1 Set protocol mode to HDLC.
PEB 3456 E
Register Description
Data Sheet 363 05.2001
RCR2
Receive Channel Configuration Register 2
Access : read/write
Address : 01H
Reset Value : 0000H
PAS Pattern Select for SSM and CRC Count Function
This bit selects the default pattern for synchronization status messages
and bit error indication.
0 Use pattern defined in ETS 300233.
1 Use patterns specified in registers VSSM and VCRC.
SAUM Sa-bit Update Mode
This bit selects the update mode for the Sa-bits located in register
RSAW1..RSAW3.
E1: Doubleframe
0S
a-bits are updated after eight frames.
1S
a-bits are updated only, if Sa data chang es. Update is do ne after
eight frames.
E1: CRC-4 Multiframe
0S
a-bits are updated after every multiframe.
1S
a-bits are updated only, if Sa data chang es. Upda te is do ne on
a multiframe start.
SAUP Sa-Bit Update
This bit enables the Sa-bit update function.
0 Disable update of Sa-bits.
1 Enable update of Sa-bit s using R SAW1.. RSAW3 registers.
15141312 109 76543210
PAS SAUM SAUP SACRC(2:0) SASSM(2:0) SA8E SA7E SA6E SA5E SA4E SMF T1E1
PEB 3456 E
Register Description
Data Sheet 364 05.2001
SACRC Sa-bit Select for CRC Function
This bit field enables the CRC count function of the selected Sa-bit.
0 Disable CRC count function.
1..5 Enable CRC count function for bit Sa4..Sa8, e.g. SACRC = 2
selects bit Sa8 for CRC count function.
Other Reserved
SASSM Sa-bit Select for SSM Function
This b it fie ld en abl es the sync hroniz ation status mes sage funct ion o f the
selected Sa-bit. The SSM function checks incoming messages and
reports any change if a synchronization status message has been
received three times in a row.
0 Disable SSM function.
1..5 Enable SSM function for bit Sa4..Sa8, e.g. SASSM = 2 selects
bit Sa8 for SSM function.
Other Reserved
SA8E..SA4E Sa-bit Signalling Enable
Setting one of the bits switches between Sa-bit access or protocol
access of the selected bits.
0 Enable Sa-bit access via register RSAW1-3.
1 Enable protocol access (HDLC, transparent). Selected bits will
be combined to receive protocol data.
SMF Select Multiframe Format
This bit switches between doubleframe and CRC-4 multifra me format.
0 Select doubleframe format.
1 Select CRC-4 multiframe format.
T1E1 T1/E1 Mode Selection
This bit switches the receive signalling controller into T1 or E1 mode.
0 Select T1 mode.
1 Select E1 mode.
PEB 3456 E
Register Description
Data Sheet 365 05.2001
RFF
Receive FIFO Register
Access : read
Address : 02H
Reset Value : 0000H
RFIFO Receive FIFO Data
This bit field contains the first 16 bit word of the receive FIFO of the
signalling controller. The receive FIFO itself consists of two pages with
32 bytes, thus 16 words can be stored inside the receive FIFO at a time.
Port status and FIFO operations can be accessed via register PSR and
register HND.
The first bit received is stored in bit 0.
15 0
RFIFO(15:0)
PEB 3456 E
Register Description
Data Sheet 366 05.2001
XCR1
Transmit Channel Configuration Register 1
Access : read/write
Address : 03H
Reset Value : 0000H
PBYTE Preamble Byte
This bit field selects the preamble byte to be sent after interframe time-
fill transmission is stopped.
PCNT Preamble Count
This bit field selects the amount of preamble repetitions.
INV Invert Data
This bit enables data inversion between transmit signalling controller
and transmit framer.
0 Disable data Inversion.
1 Enable data inversion.
XON Transmitter On/Off
This b it switch es the transm itter of t he facility d ata link to operational (on)
or inoperational state (off).
0 Switch transmitter off.
1 Switch transmitter on.
DISCRC Disable CRC
This bit enables CRC generation and transmission on transmission of
HDLC packets.
0 Enable CRC generation.
1 Disable CRC generation.
15 87 43210
PBYTE(7:0) PCNT(3:0) INV XON DIS
CRC SF
PEB 3456 E
Register Description
Data Sheet 367 05.2001
SF Shared Flags
This bit enables transmission of protocol data with shared flags.
0 Disable shared flags.
1 Enable shared flags.
PEB 3456 E
Register Description
Data Sheet 368 05.2001
XCR2
Transmit Channel Configuration Register 2
Access : read/write
Address : 04H
Reset Value : 0000H
IFTF Interframe Time Fill
This bit determines the interframe time of the transmit signalling
controller.
0 Interframe time fill is 7EH.
1 Interframe time fill is FFH.
SA8E..SA4E Sa-bit Signalling Enable
Setting one of the bits switches between normal Sa-bit access or prot ocol
access of the selected bits.
0 Enable Sa-bit access via register XSAW1-3.
1 Enable protocol access (HDLC, transparent). Selected bits will
be combined for protocol data transmission.
SMF Select CRC-4 Multiframe Forma t
This bit switches between doubleframe and multiframe format.
E1
0 Select doubleframe format.
1 Select CRC-4 multiframe format.
T1E1 T1/E1 Mode Selection
This bit switches the receive signalling controller into T1 or E1 mode.
0 Select T1 mode.
1 Select E1 mode.
15 876543210
00000000 IFTF SA8E SA7E SA6E SA5E SA4E SMF T1E1
PEB 3456 E
Register Description
Data Sheet 369 05.2001
XFF
Transmit FIFO Register
Access : write
Address : 05H
Reset Value : 0000H
XFIFO Transmit FIFO Data
This bit field writes a 16 bit word to the transmit FIFO of the signalling
controller. The transmit FIFO itself consists of two pages with 32 bytes,
thus 16 words can be written to the transmit FIFO at a time. Port status
and FIFO operations can be accessed via register PSR and register
HND.
Data written to the transmit FIFO is sent starting with bit 0 up to bit 15.
15 0
XFIFO(15:0)
PEB 3456 E
Register Description
Data Sheet 370 05.2001
PSR
Port Status register
Access : read
Address : 06H
Reset Value : 0000H
XRA Transmit Repeat Active
This bit indicates that the transmit signalling controller is operating in
repeat mode.
0 Normal operation
1 Repeat operation
XFW Transmit FIFO Write Enable
This bit indicates that data can be written to XFF.XFIFO. This bit is for
polling use with the same meaning as the ’Transmit Pool Ready’
interrupt vector.
RBC Receive B y te Count
This bit field indicates the amount of data stored in the receive FIFO.
Valid after a ’Receive Message End’ interrupt vector is generated.
Receive byte count will be cleared, when a ’Receive Message Clear’
command is executed via register HND. A zero byte count in
combination with a ‘Receive Pool Full’ or ’Receive Message End’
interrupt vector means that 32 bytes are available in the receive FIFO.
SMOD E Receiver Statu s Mode
This bit indicates the status of the receive signalling controller. If BOM
mode is se lec ted vi a bi t RCR1 .BRM th e rec ei ve r switches a utom at ica ll y
between HDLC mode and B OM mode.
10BHDLC mode
01BBOM mode
Other Reserved
15141312 87654 0
XRA XFW RBC(4:0) SMODE(1:0) BRFO STAT(4:0)
PEB 3456 E
Register Description
Data Sheet 371 05.2001
BRFO BOM Receive FIFO Overflow
0 No overflow
1 RFF overflow
The status word will be cleared after a ’Receive Message Clear’
command is issued.
STAT Receive FIFO Status
This bit field reports the status of the data stored in the receive FIFO.
HDLC mode
00000BValid HDLC Frame
00001BReceive Data Overflow
00010BReceive Abort
00011BNot Octet
00100BCRC Error
00101BChannel Off
BOM MODE
00000BBOM Filtere d data decla red
00001BBOM data avai lab le
00010BBOM End
00011BBOM filtered data undeclared
00100BBOM header error (ISF, incorrect sy nc hron iz ati on form at)
PEB 3456 E
Register Description
Data Sheet 372 05.2001
HND
Handshake Register
Access : write
Address : 07H
Reset Value : 0000H
Note: Receive command (bit 8) and transmit commands (bit 5 down to bit 0) can not be
issued at the same time. Doing so will cause the facility data link to omit the
tran smit co mmands .
RMC Receive Mess age Complete
This bit is a confirma tion from C PU that a data bloc k has been re ad from
RFIFO following a ’Receive Pool Full’ or ’Receive Message End’
interrupt vector and that the occupied page can now be released.
0 No function
1 Release page of receive FIFO.
Note: If this bit is set, the low byte (transmit commands) of the register
HND is ignored.
ABORT Abort Frame
Setting this bit aborts HDLC frames which are transmitted.
0 Normal operation
1 Abort HDLC frame.
XRES Transmitter Reset
This bit resets the signalling controller transmit. However, the contents
of the control register will not be reset.
0 Normal operation
1 Transmitter reset
XREP Transmission Repeat
Setting th is bit tog ether with bit XTF ind icates tha t the cont ents st ored in
XFF.XFIFO shall be repeatedly transmitted by the TE3-CHATT.
0 No cycl ic transm is sion.
15 8 543210
0000000RMC0ABORTXRES XREP OBI XHF XTF XME
PEB 3456 E
Register Description
Data Sheet 373 05.2001
1 Enable cyclic transmission.
OBI Odd Byte Count Indicator
Setting this bit together with bit XME indicates the number of bytes
writte n to XFF.XF IFO is od d. Th is means the lowe r byte of the last write
trans fer to the transm it FIFO is valid on ly. In HDLC mod e the status byte
written to transmit FIFO must be included in calculation.
0 Even number of bytes stored in XFF.XFIFO.
1 Odd number of bytes stored in XFF.XFIFO.
XHF Transmit HDLC frame
Setting th is bit in dic ate s th at th e co ntents written to XFF.X FIFO sh all be
transmitted as HDLC frame. If data written to XFF.XFIFO completes a
HDLC frame, bit XME must be set together with XHF in order to generate
CRC and flag.
0 No function
1 Transmit data stored in XFF.XFIFO in HDLC format.
XTF Transmit transparent frame
Setting th is bit in dic ate s th at th e co ntents written to XFF.X FIFO sh all be
transmitted in transparent mode.
0 No function
1 Transmit data stored in XFF.XFIFO fully transparent, i.e. without
bit stuffing and CRC.
XME Transmit Message End
Setting this bit indicates that the last data block written to XFF.XFIFO
completes the current frame. The la st byte of the data block written to the
transmit FIFO is a status word indicating the message status. The
signalling controller terminates the transmission properly by appending
CRC and the closing f lag to the da ta seque nce i f the status word writte n
as the last entry to the transmit FIFO does not contain an abort
indication.
•
PEB 3456 E
Register Description
Data Sheet 374 05.2001
Table 8-26 Signalling Controller Transmit Commands
XRES XREP OBI XHF XTF XME Function
1-----Reset Port
000100Transmit HDLC Frames
Send FIFO content as HDLC frame.
000/1101End Transmit HDLC
Send FIFO content as HDLC frame.
Add CRC (if enabled) and flag after last
byte stored in FIFO.
010/1100Repeat HDLC Frame
Send FIFO content as HDLC frame.
Add CRC (if enabled) and flag after last
byte stored in FIFO. Then repeat
transmission of FIFO content.
010/1101Stop Repeat HDLC Frame
Stop transmission after last byte stored
in FIFO. This command is issued when
repetitive transmission started by
comma nd ’Repe at HDLC Fra me’ s hall
be stopped.
000010Transmit Transparent
Send FIFO content in transparent
mode.
000/1011End Transmit Transparent
Send FIFO content in transparent
mode. End tra nsmission after las t byte
stored in FIFO.
010/1010Repeat Transmit Transparent
Send FIFO content in transparent
mode. Repeat transmission of FIFO
content after last byte was sent.
010/1011Stop Repeat Transmit Transparent
Stop transparent transmission after
last byte stored in FIFO. This
command is issued when repetitive
transmission started by command
’Repeat transmit transparent’ shall be
stopped.
PEB 3456 E
Register Description
Data Sheet 375 05.2001
MSK
Interrupt Mask Register
Access : read/write
Address : 08H
Reset Value : 0000H
For each facility data link inter rupt vector an interrupt vector generation mask is provided.
Generation of an interrupt vector itself does not necessarily result in assertion of the
interrupt pin. For description of interrupt concept and interrupt vectors see “Layer One
Interrupts” on Page 137.
The following definition applies:
1 The corresponding interrupt vector will not be generated by the device.
0 The corresponding interrupt vector will be generated.
Facility Data Link Interrupt Vector Transmit
TXSA Mask ’Transmit Sa Data’
ALLS Mask ’All Sent’
XDU Mask ’’Transmit Data Underrun’
XPR Mask ’Transmit Pool Ready’
Facility Data Link Interrupt Vector Receive
RSA Mask ’Receive Sa Data Valid’
SSM Ma sk ’Synchronization Status Message Received’
RPF Mask ’Receive Pool Full’
RME Mask ’Receive Message End’
ISF Ma sk ’Inc orrect Synchronization Form at’
15 111098 43210
0000 TXSA ALLS XDU XPR 000 RSA SSM RPF RME ISF
PEB 3456 E
Register Description
Data Sheet 376 05.2001
RAL
Receive Addr ess Lo w
Access : read/write
Address : 09H
Reset Value : 0000H
RAL2 Receive Address Low Byte
This bit field defines the low byte of the second receive address.
RAL1 Receive Address Low Byte
This bit field defines the low byte of the first receive address.
15 8 7 0
RAL2(7:0) RAL1(7:0)
PEB 3456 E
Register Description
Data Sheet 377 05.2001
RAH
Receive Addr ess High
Access : read/write
Address : 0AH
Reset Value : 0000H
RAH2 Receive Address High Byte
This bit field defines the high byte of the second receive address.
RAH1 Receive Address High Byte
This bit field defines the high byte of the first receive address.
15 8 7 0
RAH2(7:0) RAH1(7:0)
PEB 3456 E
Register Description
Data Sheet 378 05.2001
RSAW1
Receive Sa Word 1
Access : read
Address : 0BH
Reset Value : 0000H
SA5 Received Sa5 Data Byte
This bi t field conta ins data rece ived in Sa5 of an E1 dou bleframe or an E1
CRC-4 multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA5(0) is the
data bit receive in frame one, while SA5(7) is the data byte received in
frame 15 of a multiframe.
SA4 Received Sa4 Data Byte
This bi t field conta ins data rece ived in Sa4 of an E1 dou bleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA4(0) is the
data bit receive in frame one, while SA4(7) is the data byte received in
frame 15 of a multiframe.
15 8 7 0
SA5(7:0) SA4(7:0)
PEB 3456 E
Register Description
Data Sheet 379 05.2001
RSAW2
Receive Sa Word 2
Access : read
Address : 0CH
Reset Value : 0000H
SA7 Received Sa7 Data Byte
This bi t field conta ins data rece ived in Sa7 of an E1 dou bleframe or an E1
CRC-4 multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA7(0) is the
data bit receive in frame one, while SA7(7) is the data byte received in
frame 15 of a multiframe.
SA6 Received Sa6 Data Byte
This bi t field conta ins data rece ived in Sa6 of an E1 dou bleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA6(0) is the
data bit receive in frame one, while SA6(7) is the data byte received in
frame 15 of a multiframe.
15 8 7 0
SA7(7:0) SA6(7:0)
PEB 3456 E
Register Description
Data Sheet 380 05.2001
RSAW3
Receive Sa Word 3
Access : read
Address : 0DH
Reset Value : 0000H
SADV Received Sa4..Sa8 Data Valid
This bit indicates that new Sa data in register RSAW1..RSAW3 is
availa ble. The s ignallin g controll er will not u pdate Sa da ta while thi s bit is
set. SADV will be cleared on reads to this register.
0No S
a data availab le.
1S
a data available in register RSAW1..RSAW3.
SA8 Received Sa8 Data Byte
This bi t field conta ins data rece ived in Sa8 of an E1 dou bleframe or an E1
multiframe.
E1: CRC-4 Multiframe
Received data byte is aligned to a multiframe boundary. SA8(0) is the
data bit receive in frame one, while SA8(7) is the data byte received in
frame 15 of a multiframe.
15 8 7 0
0000000 SADV SA8(7:0)
PEB 3456 E
Register Description
Data Sheet 381 05.2001
RSAW4
Receive Sa Word 4
Access : read
Address : 0EH
Reset Value : 0000H
SSMD SSM Data Pattern
This bit field co ntains the re ceived sync hronizati on status m essage. Th e
synchronization status message reported depends on bit RCR2.PAS
and, i f selected, on pattern ena bled in regis ter VSSM. Only va lid if SSMV
is set.
SSMV Synchronization Status Message Valid
This bit indicates that a new synchronization status message has been
received. A new SSM is reported every time a message has been
received three time in a row on the Sa-bit selected via register
RCR2.SASSM. This bit is reset after the user performs a read on this
register.
0 No new SSM data available.
1 New SSM data available.
15 7 4 3 1 0
00000000 SSMD(3:0) 000 SSMV
PEB 3456 E
Register Description
Data Sheet 382 05.2001
CRC1
CRC Status Counter 1
Access : read
Address : 0FH
Reset Value : 0000H
CRC1 CRC1 counter
The Sa-bit error indication counter CRC1 (16 bits) counts either the
received bit sequences 0001B and 001 1B or user programmable values
specified in register VCRC in every submultiframe on a selectable Sa-bit.
In the primary rate access digital section CRC errors ar e reported from
the TE via Sa6. Incrementing is only possible in the multiframe
synchronous stat e.
The counter is increased with every received bit error indication if
enabled in register RCR2. The counter will not be incremented once it
reaches FFFFH. A read will clear this counter.
15 0
CRCS1(15:0)
PEB 3456 E
Register Description
Data Sheet 383 05.2001
CRC2
CRC Status Counter 2
Access : read
Address : 10H
Reset Value : 0000H
CRC2 CRC2 counter
The Sa-bit error indication counter CRC2 (16 bits) counts either the
received bit sequences 0010B and 001 1B or user programmable values
specified in register VCRC in every submultiframe on a selectable Sa-bit.
In the primary rate access digital section CRC errors detected at T-
reference points are r eported via Sa6. Incrementin g is only possible in the
multiframe synchronou s stat e.
The counter is increased with every received bit error indication if
enabled in register RCR2. The counter will not be incremented once it
reaches FFFFH. A read will clear this counter.
15 0
CRCS(15:0)2
PEB 3456 E
Register Description
Data Sheet 384 05.2001
XSAW1
Transmit Sa Word 1
Access : read/write
Address : 11H
Reset Value : 0000H
SA5 Transmit Sa5 Data Byte
This bit field contains data to be transmitted in Sa5 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA5 will be inserted into the data stream, if
selected via bit XCR2.SA5E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA5(0) is the
data bi t transm itte d i n f ram e o ne w hi le SA5(7 ) is t he data bit tran sm itte d
in frame 15 of a multiframe.
SA4 Transmit Sa4 Data Byte
This bit field contains data to be transmitted in Sa4 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA4 will be inserted into the data stream, if
selected via bit XCR2.SA4E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA4(0) is the
data bi t transm itte d i n f ram e o ne w hi le SA4(7 ) is t he data bit tran sm itte d
in frame 15 of a multiframe.
15 8 7 0
SA5(7:0) SA4(7:0)
PEB 3456 E
Register Description
Data Sheet 385 05.2001
XSAW2
Transmit Sa Word 2
Access : read/write
Address : 12H
Reset Value : 0000H
SA7 Transmit Sa7 Data Byte
This bit field contains data to be transmitted in Sa7 of an E1 doubleframe
or an E1 multifram e. SA7 will be in serted into t he data stream , if selecte d
via bit XCR2.SA7E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA7(0) is the
data bi t transm itte d i n f ram e o ne w hi le SA7(7 ) is t he data bit tran sm itte d
in frame 15 of a multiframe.
SA6 Transmit Sa6 Data Byte
This bit field contains data to be transmitted in Sa6 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA6 will be inserted into the data stream, if
selected via bit XCR2.SA6E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA6(0) is the
data bi t transm itte d i n f ram e o ne w hi le SA6(7 ) is t he data bit tran sm itte d
in frame 15 of a multiframe.
15 8 7 0
SA7(7:0) SA6(7:0)
PEB 3456 E
Register Description
Data Sheet 386 05.2001
XSAW3
Transmit Sa Word 3
Access : read/write
Address : 13H
Reset Value : 0000H
XSAV Sa Data Valid
This bit indicates that new Sa data has been written to register
XSAW1..XSAW3 from system processor.
0 No new Sa data available.
1New S
a data available.
XSAR Sa Data Repetitions
This bit field defines the number of repetitions of the Sa data bytes. A
’Tra nsmit Sa Data’ interrupt vector will be generated after programmed
number of repetitions.
SA8 Transmit Sa8 Data Byte
This bit field contains data to be transmitted in Sa8 of an E1 doubleframe
or an E1 CRC-4 multiframe. SA8 will be inserted into the data stream, if
selected via bit XCR2.SA8E.
E1: CRC-4 Multiframe
Transmit data will be aligned to a multiframe boundary. SA8(0) is the
data bi t transm itte d i n f ram e o ne w hi le SA8(7 ) is t he data bit tran sm itte d
in frame 15 of a multiframe.
15 14 13 8 7 0
0 XSAV XSAR(5:0) SA8(7:0)
PEB 3456 E
Register Description
Data Sheet 387 05.2001
VSSM
Valid SSM Pattern
Access : read/write
Address : 14H
Reset Value : 0000H
PA Pattern 15..0
Setting one or more of the bits enables the selected pattern for SSM
comparison. E.g. setting PA(3) and PA(1) enables pattern 0010B and
0001B for SSM comparison. Identified SSM pattern are reported via
reg ister RSAW4.
Only valid if RCR2.PAS is set to ’1’.
15 0
PA(15:0)
PEB 3456 E
Register Description
Data Sheet 388 05.2001
VCRC
Valid CRC Count Pattern
Access : read/write
Address : 15H
Reset Value : 0000H
CRC22
CRC21 CRC2 Pattern Definition
The bit fields CRC21 and CRC22 determine the Sa-bit error indication
pattern to be reported in register CRC2.
Only valid if RCR2.PAS is set to ’1’.
CRC12
CRC11 CRC1 Pattern Definition
The bit fields CRC11 and CRC12 determine the Sa-bit error indication
pattern to be reported in register CRC1.
Only valid if RCR2.PAS is set to ’1’.
15 12 11 8 7 4 3 0
CRC22(3:0 CRC21(3:0) CRC12(3:0) CRC11(3:0)
PEB 3456 E
Electrical Characteristics
Data Sheet 389 05.2001
9 Electrical Characteristics
9.1 Important Electrical Requirements
Both VDD3 and VDD25 can take on any power-on sequence. Within 50 milliseconds of
power-up the voltages must be within their respective absolute voltage limits. At power-
down, within 50 milliseconds of either voltage going outside its operational range, both
voltages must be returned below 0.1V.
9.2 Absolute Maximum Ratings
Table 9-1 Absolute Maximum Ratings
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
9.3 DC Characteristics
a) Power Supply Pins
Table 9-2 DC Characteristics
Parameter Symbol Limit Values Unit
min max
Ambient tem per ature under bia s
PEB 3456 E
TA0
-40 70
85
°C
Junction temperature under bias TJ125 °C
Storage temperature Tstg -65 125 °C
Voltage on any pin with resp ect to ground VS-0.5 VDD3+0.5 V
Parameter Symbol Limit Values Unit Test
Condition
min. max.
Core Supply Voltage VDD25 2.25 2.75 V
I/O Supply Voltage VDD3 3.0 3.6 V
PEB 3456 E
Electrical Characteristics
Data Sheet 390 05.2001
b) Non-PCI Interface Pins
Table 9-3 DC Characteristics (Non-PCI Interface Pins)
TA = -40 to 85°C, VDD3 = 3.3 V ±=0.3 V, VDD25 = 2.5 V ±=0.25 V, VSS = 0 V
Core
supply
current
VDD25
operationa
lICC25 < 400 mA
power
down
(no clocks)
ICCPD25 < 2 mA
I/O su ppl y
current
VDD3
operationa
lICC3 < 200 mA Inputs at
VSS/VDD3
No output
loads.
power
down
(no clocks)
ICCPD3 < 2 mA
Sum of Input leakage
current and
Output leakage current
(Outputs Hi-z)
ILI
ILO
< 10 µA
Power Dissipation P<3 W
Parameter Symbol Limit Values Unit Test Condition
min. max.
L-input voltage VIL -0.4 0.8 V
H-input voltage VIH 2.0 VDD3+0.4 V
L-outp ut vol tag e VOL 0.45 V IQL = 2 mA
H-output voltage VOH 2.4 V IQH = -400 µA
Parameter Symbol Limit Values Unit Test
Condition
min. max.
PEB 3456 E
Electrical Characteristics
Data Sheet 391 05.2001
c) PCI Interface Pins
Table 9-4 DC Characteristics (PCI Interface Pins)
TA = -40 to 85°C, VDD3 = 3.3 V ±=0.3 V, VDD25 = 2.5 V ±=0.25 V, VSS = 0 V
9.4 AC Characteristics
a) Non-PCI interface pins
TA = -40 to 85°C, VDD3 = 3.3 V ±=0.3 V, VDD25 = 2.5 V ±=0.25 V, VSS = 0 V
Inputs are driven to 2.4 V for a logical ‘1’ and to 0.4 V for a logical ‘0’. Timing
measurements are made at 2.0 V for a logical ‘1’ and at 0.8 V for a logical ‘0’.
The AC testing input/output waveforms are shown below.
•
Figure 9-1 Input/Output Waveform for AC Tests
b) PCI interface pins
PCI interface pins are measured as pins compliant to the 3.3V signalling environment
according to the PCI Specification Rev. 2.1.
Parameter Symbol Limit Values Unit Test Condition
min. max.
L-input voltage VIL -0.5 0.3VDD3 -
80mV V
H-input voltage VIH 0.5VDD3 VDD3+0.5 V
L-outp ut vol tag e VOL 0.1VDD3 VIQL = 1500 µA
H-output voltage VOH 0.9VDD3 VIQH = -500 µA
Device
Under
Test
2.0
0.80.8
2.0 test points
0.45
2.4
Cload = 50pF
PEB 3456 E
Electrical Characteristics
Data Sheet 392 05.2001
9.4.1 PCI Bus Interface Timing
•
Figure 9-2 PCI Clock Cycle Timing
Table 9-5 PC I Clock Ch aracteristics
Note: Rise and fall tim es are specifi ed in term s of the edge rate me as ured in V/ns. Thi s
slew rate must be met across the minimum peak-to-peak portion of the clock
waveform shown in Figure 9-3.
•
Figure 9-3 PCI Input Timing Measurement Conditions
Parameter Symbol Limit Values Unit
min. max.
CLK cycle time tcyc 15 ns
CLK high time thigh 6ns
CLK low time tlow 7ns
CLK slew rate (see note) 1.5 4 V/ns
0.2 V
DD3
0.6 V
DD3
0.5 V
DD3
0.4 V
DD3
0.3 V
DD3
t
high
t
low
t
cyc
0.4 V
DD3
, p-to-p
(minimum)
t
h
Input delay
Clock V
test
V
test
V
tl
V
th
t
su
V
tl
V
th
V
test
Inputs valid V
max
PEB 3456 E
Electrical Characteristics
Data Sheet 393 05.2001
•
Figure 9-4 PCI Output Timing Measurement Conditions
Table 9-6 PCI Interface Signal Characteristics
Note:
1. Minimum times are mea sured fo r 3.3V signalli ng envi ronmen t acco rding to th e PCI
Specification Rev. 2.1.
2. REQ and GNT are point-to-point signals. All other signals are bussed.
Parameter Symbol Limit Values Unit Notes
min. max.
CLK to signal valid - bussed
signals tval 28ns1, 2
CLK to REQ valid tval 27ns1, 2
Float to active delay ton 2ns
Active to float delay toff 14
Input set up time to CLK - b ussed
signals tsu 42
Input setup time to CLK - GNT tsu 52
Input hold time from CLK th0.5
t
off
t
on
t
val
Tri-state output
Output delay
Clock V
test
V
test
V
test
V
test
V
tl
V
th
PEB 3456 E
Electrical Characteristics
Data Sheet 394 05.2001
9.4.2 SPI Interface Timing
•
Figure 9-5 SPI Interface Timing
Table 9-7 SPI Interface Timing
•
Note:
1 SPI clock is related to PCI clock where the SPI frequency is 1/78 of the PCI
frequency . All timings fo r SPI interface are calc ulated with a PC I clock running at 33
MHz.
No. Parameter Limit Values Unit Notes
min. max.
1 SPCS low to SPCLK delay 500 ns 1
2 SPCLK to SPCS delay 500 ns
3 SPCLK high time 500 n s
4 SPCLK low time 500 n s
5 SPCS to SPSO delay 100 ns
6 SPCLK to SPSO delay 100 ns
7 SPSI to SPCLK setup time 100 ns
8 SPSI to SPCLK hold time 100 ns
5
4
6
3
7
8
1 2
SPCS
SPCLK
SPSO
SPSI
PEB 3456 E
Electrical Characteristics
Data Sheet 395 05.2001
9.4.3 Local Micro pro ces sor In terf ace Timing
9.4.3.1 Intel Bus Interface Timing (Slave Mode)
•
Figure 9- 6 Intel Read Cycle Timing (Slave Mode)
•
Figure 9-7 Intel Write Cycle Timing (Slave Mode)
22
LA
LCS0
LRD
LRDY
LD
20
24 25
27 28
26
23
21
29
32
22
20
24 25
30
31
26
23
21
32
LA
LCS0
LWR
LRDY
LD
PEB 3456 E
Electrical Characteristics
Data Sheet 396 05.2001
Table 9-8 Intel Bus Interface Timing
No. Parameter Limit Values Unit
min. max.
20 LA to LRD, LWR setup time 20 ns
21 LA to LRD, LWR hold time 0 n s
22 LCS0 to LRD, LWR setup time 20 ns
23 LCS0 to LRD, LWR hold time 0 ns
24 LCS0 low to LRDY active delay 20 ns
25 LRD, LWR high to LRDY high delay 20 ns
26 LCS0 high to LRDY float delay 20 ns
27 LRD low to LD active delay 20 ns
28 LRD high to LD float delay 20 ns
29 LRDY low to LD valid delay 20 ns
30 LD to LWR setup time 20 ns
31 LD to LWR hold time 0 ns
32 LRD, LWR minimum high time 20 n s
PEB 3456 E
Electrical Characteristics
Data Sheet 397 05.2001
9.4.3.2 Intel Bus Interface Timing (Master Mode)
•
Figure 9-8 Intel Read Cycle Timing (Mast er Mode, L RDY controlled)
•
Figure 9-9 Intel Write Cycle Timing (Master Mode, LRDY controlled)
LA
LCS2,1
LRD
LRDY
LBHE
62b
65
60b
61b
60a
61a
62a
63a 63b
LCLK
66
LD
67a
67b
LA
LCS2,1
LWR
LRDY
LD
LBHE
62b
65
69a 69b
60b
61b
60a
61a
62a
63a 63b
LCLK
66
PEB 3456 E
Electrical Characteristics
Data Sheet 398 05.2001
•
Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled)
•
Figure 9-11 Intel Write Cycle Timing (Master Mode, Wait state controlled)
LA
LCS2,1
LRD
LBHE
62b
60b
61b
60a
61a
62a
63a 63b
LCLK
LD
68a 68b
WS*t
CYC
LA
LCS2,1
LWR
LD
LBHE
62b
69a 69b
60b
61b
60a
61a
62a
63a 63b
LCLK
WS*t
CYC
PEB 3456 E
Electrical Characteristics
Data Sheet 399 05.2001
•
Figure 9-12 Intel Bus Arbitration Timing
Table 9-9 Intel Bus Interface Timing (Master Mode)
Note: tCYC is the clock period of the PCI clock.
No. Parameter Limit Values Unit
min. max.
60a LCLK to LA active delay 0 10 ns
60b LCLK to LA float delay 0 10 ns
61a LCLK to LCS2,1 active delay 0 10 ns
61b LCLK to LCS2,1 float delay 0 10 ns
62a LCLK to LBHE active delay 0 10 ns
62b LCLK to LBHE float delay 0 10 ns
63a LCLK to LRD, LWR active delay 0 10 ns
63b LCLK to LRD, LWR float delay 0 10 ns
65 LRDY low to LRD, LWR high delay 2 tCYC
66 LRDY to LRD, LWR hold time 0 ns
67a LD to LRD setup time 0 ns
67b LD to LRD hold time 0 ns
68a LD to LCLK setup time 10 ns
68b LD to LCLK hold time 0 ns
69a LCLK to LD delay 0 10 ns
69b LCLK to LD float delay 0 10 ns
70 LCLK to LHOLD delay 0 10 ns
71 LHLDA asserted to Read/Write Cycle start 1 tCYC
72 LHLDA minimum pulse width 2 tCYC
LHOLD
LHLDA
70
LCLK
Read/
Write
71
72
PEB 3456 E
Electrical Characteristics
Data Sheet 400 05.2001
9.4.3.3 Motorola Bus Interface Timing (Slave Mode)
•
Figure 9-13 Motorola Read Cycle Timing (Slave Mode)
•
Figure 9-14 Motorola Write Cycle Timing (Slave Mode )
44
40
46 47
49 50
48
45
41
54 4342
51
LA
LCS0
LRDWR
LDTACK
LD
LDS
44
LA
LCS0
LRDWR
LDTACK
LD
40
46 47
52
53
54
48
43
41
LDS
42
45
PEB 3456 E
Electrical Characteristics
Data Sheet 401 05.2001
Table 9-10 Motorola Bus Interface Timing
No. Parameter Limit Values Unit
min. max.
40 LA to LDS setup time 20 ns
41 LA to LDS hold time 0 ns
42 LCS0 to LDS setup time 20 ns
43 LCS0 to LDS hold time 0 ns
44 LRDWR to LDS setup time 20 ns
45 LRDWR to LDS hold time 0 ns
46 LCS0 low to LDTACK active delay 20 ns
47 LDS high to LDTACK high delay 20 n s
48 LCS0 high to LDTACK float delay 20 ns
49 LDS low to LD active delay 20 ns
50 LDS high to LD float delay 20 ns
51 LDTACK low to LD valid delay 20 ns
52 LD to LDS set up tim e 20 ns
53 LD to LDS hol d time 0 ns
54 LDS minimum high time 20 ns
PEB 3456 E
Electrical Characteristics
Data Sheet 402 05.2001
9.4.3.4 Motorola Bus Interface Timing (Master Mode)
•
Figure 9-15 Motorola Read Cycle Timing (Master Mode, LDTACK controlled)
•
Figure 9-16 Motorola Write Cycle Timing (Master Mode, LDTACK controlled)
LA
LCS2,1
LDS
LDTACK
LD
LSIZE0
82b
85
86
87a 87b
80b
81b
LRDWR
83b
80a
81a
82a
83a
84a 84b
LCLK
LA
LCS2,1
LDS
LDTACK
LD
LSIZE0
82b
85
89a 89b
80b
81b
LRDWR
83b
80a
81a
82a
83a
84a 84b
LCLK
86
PEB 3456 E
Electrical Characteristics
Data Sheet 403 05.2001
•
Figure 9-17 Motorola Read Cycle Timing (Master Mode, Wait state controlled)
•
Figure 9-18 Motorola Write Cycle Timing (Master Mode, Wait state controlled)
LA
LCS2,1
LDS
LSIZE0
82b
80b
81b
LRDWR
83b
80a
81a
82a
83a
84a 84b
LCLK
LD
88a 88b
WS*t
CYC
LA
LCS2,1
LDS
LD
LSIZE0
82b
89a 89b
80b
81b
LRDWR
83b
80a
81a
82a
83a
84a 84b
LCLK
WS*t
CYC
PEB 3456 E
Electrical Characteristics
Data Sheet 404 05.2001
•
Figure 9-19 Motorola Bus Arbitration Timing
Table 9-11 Motorola Bus Interface Timing (Master Mode)
No. Parameter Limit Values Unit
min. max.
80a LCLK to LA active delay 0 10 ns
80b LCLK to LA float delay 0 10 ns
81a LCLK to LCS2,1 active delay 0 10 ns
81b LCLK to LCS2,1 float delay 0 10 ns
82a LCLK to LSIZE0 active delay 0 10 ns
82b LCLK to LSIZE0 float delay 0 10 ns
83a LCLK to LRDWR active delay 0 10 ns
83b LCLK to LRDWR float delay 0 10 ns
84a LCLK to LDS active delay 0 10 ns
84b LCLK to LDS float delay 0 10 ns
85 LDTACK low to LDS high delay 2 tCYC
86 LDTACK to LDS hold time 0 ns
87a LD to LDTACK setup time 0 ns
87b LD to LDTACK hold time 0 ns
88a LD to LCLK setup time 10 ns
88b LD to LCLK hold time 0 ns
89a LCLK to LD delay 0 10 ns
LBR
LBG
LBGACK
93
90
92
LCLK
94
Read/
Write
91
PEB 3456 E
Electrical Characteristics
Data Sheet 405 05.2001
89b LCLK to LD float delay 0 10 ns
90 LCLK to LBR delay 0 10 ns
91 LBGACK to LBR delay 1 tCYC
92 LBG to LBGACK hold time 0 ns
93 LBG to LBGACK delay 1 tCYC
94 LCLK to LBGACK delay 0 10 ns
No. Parameter Limit Values Unit
min. max.
PEB 3456 E
Electrical Characteristics
Data Sheet 406 05.2001
9.4.4 tCYC is the clock period of the PCI clock.Serial Interface Timing
9.4.4.1 DS3 Serial Interface Timing
Note: The clo ck in put tim ings are ca lcula ted assu ming a PCI clo ck fre quenc y of 33 MHz
or more.
•
Figure 9-20 Clock Input Timing
Table 9-12 Clock Input Timing
No. Parameter Limit Values Unit
min. max.
100 Clock frequency nom. 44.736 MHz
101 Clock high timing 7.5 ns
102 Clock low timing 7.5 ns
103 Clock fall time 2 ns
104 Clock rise time 2 ns
TC44
RC44
100
101 102
103 104
PEB 3456 E
Electrical Characteristics
Data Sheet 407 05.2001
•
Figure 9-21 DS3 Transmit Cycle Timing
Note:
1. Actual clock reference depends on selected clock mode:
•
Figure 9-22 DS3 Transmit Data Timing
Note:
2. Timing for transmit data which is updated on the rising edge of TC44O.
3. Timing for transmit data which is updated on the falling edge of TC44O.
Table 9-13 DS3 Transmit Cycle Timing
No. Parameter Limit Values Unit
min. max.
110 RC44, TC44 to TC44O delay 2 15 ns
111 TC44O to TD44, TD44P/TD44N delay 0 5 ns
110 110
TC44
RC44
(Note 1)
TC44O
111
TD44, TD44P/N
TC44O
(Note 2)
TC44O
(Note 3)
PEB 3456 E
Electrical Characteristics
Data Sheet 408 05.2001
•
Figure 9-23 DS3 Receive Cycle Timing
Note:
1. Timing for data which is sampled on the rising edge of the receive clock.
2. Timing for data which is sampled on the falling edge of the receive clock.
Table 9-14 DS3 Receive Cycle Timing
No. Parameter Limit Values Unit
min. max.
130 RD44, RD44P/RD44N to RC44 setup time 5 ns
131 RD44, RD44P/RD44N to RC44 hold time 5 ns
130 131
RC44
(Note 1)
RD44, RD44P/N
RC44
(Note 2)
PEB 3456 E
Electrical Characteristics
Data Sheet 409 05.2001
•
Note: DS3 Status Signal Timing
Note: Status signals are generated synchronous to the PCI clock.
Table 9-15 DS3 Status Signal Timing
No. Parameter Limit Values Unit
min. max.
132 CLK to RLOS/RLOF/RAIS/RRED delay 2 10 ns
132
RLOS
CLK
132
RLOF
132
RAIS
132
RRED
PEB 3456 E
Electrical Characteristics
Data Sheet 410 05.2001
9.4.4.2 Overhead Bit Timing
•
Figure 9-24 DS3 Transmit Overhead Timing
•
Figure 9-25 DS3 Transmit Overhead Synchronization Timing
Table 9-16 DS3 Transmit Overhead Timing
No. Parameter Limit Values Unit
min. max.
150 TOVHCK to TOVHSYN delay 75 ns
151 TOVHSYN to TCLKO44 setup time 5 ns
152 TOVHSYN to TCLKO44 hold time 5 ns
153 TOVD to TOVHCK setup time 25 ns
154 TOVD to TOVHCK hold time 5 ns
155 TOVHEN to TOVHCK setup time 25 ns
156 TOVHEN to TOVHCK hold time 5 ns
TOVHSYN
(Output Mode)
TOVHD
TOVHCK
155 156
TOVHEN
153 154
150
151 152
TC44O
TOVHSYN
(Input Mode))
PEB 3456 E
Electrical Characteristics
Data Sheet 411 05.2001
•
Figure 9-26 DS3 Receive Overhead Timing
Table 9-17 DS3 Receive Overhead Timing
No. Parameter Limit Values Unit
min. max.
157 ROVHCK to ROVHSYN delay 75 ns
158 ROVHCK to ROVHD delay 75 ns
157
ROVHSYN
ROVHD
ROVHCK
158
PEB 3456 E
Electrical Characteristics
Data Sheet 412 05.2001
9.4.4.3 Stuff Bit Timing
•
Figure 9-27 DS3 Transmit Stuff Bit Timing
Table 9-18 DS3 Transmit Stuff Timing
•
Figure 9-28 DS3 Receive Stuff Bit Timing
Table 9-19 DS3 Receive Stuff Bit Timing
No. Parameter Limit Values Unit
min. max.
160 TSBD to TSBCK setup time 25 ns
161 TSBD to TSBCK hold time 5 ns
No. Parameter Limit Values Unit
min. max.
162 RSBCK to RSBD delay 75 ns
TSBCK
160 161
TSBD
162
RSBD
RSBCK
PEB 3456 E
Electrical Characteristics
Data Sheet 413 05.2001
9.4.4.4 T1/E1 Tributary Timing
•
Figure 9-29 T1/E1 Tributary Clock Input Timing
Table 9-20 T1/E1 Tributary Clock Input Timing
No. Parameter Limit Values Unit
min. typ max.
Tributaries operated in E1 Mode
105 Clock frequency 2.048 MHz ± 50 ppm
106 Clock high timing 40 ns
107 Clock low timing 40 ns
108 Clock fall time 10 ns
109 Clock rise time 10 ns
Tributaries operated in T1 Mode
105 Clock frequency 1.544 MHz ± 130 ppm
106 Clock high timing 40 ns
107 Clock low timing 40 ns
108 Clock fall time 10 ns
109 Clock rise time 10 ns
CTCLK
105
106 107
108 109
PEB 3456 E
Electrical Characteristics
Data Sheet 414 05.2001
•
Figure 9-30 T1/E1 Tributary Synchronization Timing
Table 9-21 T1/E1 Tributary Synchronization Timing
No. Parameter Limit Values Unit
min. max.
120 CTFS to CTCLK setup time 5 ns
121 CTFS to CTCLK hold time 5 ns
CTCLK
CTFS
120 121
CTCLK
PEB 3456 E
Electrical Characteristics
Data Sheet 415 05.2001
9.4.4.5 Test Port Timing
•
Figure 9-31 T1/E1 Test Transmit Clock Timing
Table 9-22 T1/E1 Test Transmit Clock Timing
No. Parameter Limit Values Unit
min. typ max.
Test port operated in E1 Mode
170 Clock period 2.048 MHz ± 50 ppm
171 Clock high timing 100 ns
172 Clock low timing 100 ns
173 Clock fall time 10 ns
174 Clock rise time 10 ns
Test port operated in T1 Mode
170 Clock period 1.544 MHz ± 130 ppm
171 Clock high timing 100 ns
172 Clock low timing 100 ns
173 Clock fall time 10 ns
174 Clock rise time 10 ns
TTCLK
170
171 172
173 174
PEB 3456 E
Electrical Characteristics
Data Sheet 416 05.2001
•
Figure 9-32 T1/E1 Test Transmit Data Timing
Table 9-23 T1/E1 Test Transmit Data Timing
•
Figure 9-33 T1/E1 Test Receive Clock Timing
Table 9-24 T1/E1 Test Receive Clock Timing
No. Parameter Limit Values Unit
min. max.
175 TTD(x) to TTC(x) setup time 25 ns
176 TTD(x) to TTC(x) hold time 75 ns
No. Parameter Limit Values Unit
min. typ max.
Test port operated in E1 Mode
180 Clock period 469 2056 ns
181 Clock high timing 156 335 ns
182 Clock low timing 312 1900 ns
Test Port operated in T1 Mode
180 Clock period 625 1587 ns
181 Clock high timing 310 495 ns
182 Clock low timing 310 1275 ns
175 176
TTCLK
TTD
TRCLK
180
181 182
PEB 3456 E
Electrical Characteristics
Data Sheet 417 05.2001
•
Figure 9-34 T1/E1 Test Receive Data Timing
Table 9-25 Test T1/E1 Receive Data Timing
No. Parameter Limit Values Unit
min. max.
185 RTC(x) to RTD(x) delay -5 25 ns
TRD
185
TRCLK
PEB 3456 E
Electrical Characteristics
Data Sheet 418 05.2001
9.4.5 JTAG Interface Timing
•
Figure 9-35 JTAG Interface Timing
Table 9-26 JTAG Interface Timing
No. Parameter Limit Values Unit
min. max.
200 T CK period 120 ns
201 TCK high time 60 ns
202 TCK low time 60 ns
203 TMS setup time 20 ns
204 TMS hold time 20 ns
205 TDI setup time 20 ns
206 TDI hold time 20 ns
207 TDO valid time 50 ns
TRST
TCK
TMS
TDI
TDO
202201 200
203 204
205 206
207
PEB 3456 E
Electrical Characteristics
Data Sheet 419 05.2001
9.4.6 Reset Timing
•
Figure 9-36 Reset Timing
Table 9-27 Reset Timing
No. Parameter Limit Values Unit
min. max.
220 RST pulse width 120 ns
221 Number of CLK cycles during RST act iv e 2 CLK
cycles
V
DD3
CLK
220
RST
power-on
221
((420))
10 Package Outline
PEB 3456 E
List of Abbreviations
Data Sheet 421 05.2001
11 List of Abbreviations
Abbreviation Definition
A/C Analogue to Digital
ADC Analogue to Digital C onv erte r
AIS Alarm indication signal (blue alarm)
AGC Automatic gain control
ALOS Analog loss of signa
AMI Alternate mark inversion
ANSI American National Standards Institute
ATM Asynchronous transfer mode
SDH Synchornous Digital Hierarchy
SONET Synchronous Optical Network
ESF Extended Superframe
SF Super Frame
HDLC High Level Data Link Control
SDLC Synchronous Level Data Link Control
PCI Peripheral Component Interconnect.
DS3 Digital Signal Level 3
PLL Phase Locked Loop
FDL Facility Data link
SPI Serial Peripheral Interface
BOM Bit Oriented Massage
FIFO First in First out
AUXP Auxiliary pattern Line 0
B8ZS Line coding to avoid too long strings of consecutive 0
BER Bit error rate
BFA Basic frame alignment
BOM Bit orientated message
Bellcore Bell Communications Research
BPV Bipolar violation
PEB 3456 E
List of Abbreviations
Data Sheet 422 05.2001
BSN Backward sequence number
CAS Channel associated signaling
CAS-BR Channel associated signaling - bit robbing
CAS-CC Channel associated signaling - common channel
CCS Common channel signaling
CMI coded mark inversion (also known as 1T2B code)
CR Command/Response (special bit in PPR)
CRC Cycli c redu nda nc y che ck
CSU Channel service unit
CVC Code violation counter
DCO Digitally controlled oscillator
DL Digital loop
DPLL Digitally controlled phase locked loop
DS1 Digital signal level 1
EA Extended address (special bit in PPR)
PRBS Pseudo Random Binary Sequence
LOS Loss of Sign al
LOF L oss of Frame
WAN Wide Area Network
DMA Direct Memory Access
ACCM Asynchronous Control Character Map
FCM Frame Che ck Sum
DWORD Double Word ( 4 bytes )
DMU Data Management Unit
Abbreviation Definition
A/C Analogue to Digital
PEB 3456 E
List of Abbreviations
Data Sheet 423 05.2001
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