$< XILINX XC4000 Series Field Programmable Gate Arrays July 30, 1996 (Version 1.03) Product Specification XC4000-Series Features Note: XC4000-Series devices described in this data sheet include the XC4000E, XC4000EX, XC4000L, and XC4000XL. This information does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D or XC4000H. For information on these devices, see the Xilinx WEBLINX at http:/Avww.xilinx.com. Third Generation Field-Programmable Gate Arrays - Select-RAM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Fully PCI compliant (speed grades -3 and faster) - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global tow-skew clock or signal distribution networks System Performance to 66 MHz e Flexible Array Architecture Systems-Oriented Features - {EEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output (4 mA per XC4000L output) * Configured by Loading Binary File - Unlimited reprogrammability * Readback Capability * Backward Compatible with XC4000 Devices * XACTstep Development System runs on '386/'486/ Pentium-type PC, Sun-4, and Hewlett-Packard 700 series - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization - RAM/ROM compiler Low-Voltage Versions Available Low-Voltage Devices Function at 3.0 - 3.6 Voits * XC4000L: Low-Voltage Versions of XC4000E devices * XC4000XL: Low-Voltage Versions of XC4000EX devices Additional XC4000EX/XL Features Highest Capacity Over 130,000 Usable Gates Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Configurable Logic Blocks * Improved VersaRing |/O Interconnect for Better Fixed Pinout Flexibility Flexible New High-Speed Clock Network - 8 additional Early Buffers for shorter clock delays - 4 additional FastCLK buffers for fastest clock input - Virtually unlimited number of clock signals * Optional Multiplexer or 2-input Function Generator on Device Outputs * High-Speed Parallel Express Configuration Mode Improved I/O Setup and Clock-to-Output with FastCLkK and Global Early Buffers 4 Additional Address Bits in Master Parallel Configuration Mode Introduction XC4000-Series high-performance, high-capacity Field Pro- grammable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of eleven years of FPGA design experience and feedback from thousands of customers, these FPGAs com- bine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated soft- ware to achieve fully automated implementation of com- plex, high-density, high-performance designs. The XC4000 Series currently has 19 members, as shown in Table 1. July 30, 1996 (Version 1.03) 4-5XC4000 Series Field Programmable Gate Arrays Table 1: XC4000-Series Field Programmable Gate Arrays | | Max. Max Logic | Max. RAM Typical | Total | Number Decode | Gates Bits Gate Range CLB Logic of Inputs Max. Device (No RAM) (No Logic)|(Logic and RAM)*| Matrix Blocks Flip-Flops; per side | User I/O XC4003E 3,000 3,200 2,000 - 5,000 10 x 10 100 360 30 80 XC4005E/L | 5,000 6,272 3,000 - 9,000 14x 14 196 616 42 112 XC4006E 6,000 8,192 4,000- 12,000 | 16x16 256 768 48 128 XC4008E 8,000 10,368 6,000 - 15,000 18x 18 324 936=| =O 144 XC4010E/L 10,000 12,800 7,000 - 20,000 20x20 | 400 1,120 60 160 XC4013E/L 13,000 18,432 | 10,000-30,000 | 24x24 | 576 1,536 72 192 XC4020E=.20,000 25,088 | 13,000-40,000 28x28 | 784 | 2,016. 84 224 XC4025E 25,000 32,768 | 15,000-45.000 32x32 | 1,024 2,560 96 256 | XC4028EX/XL 28,000 32,768 | 18,000-50,000 32x32 | 1,024 2,560 96 256 | | XC4036EX/XL | 36,000 41,472 ' 22,000-65,000 36x36 1,296 3,168 108 288 | XC4044EX/XL | 44,000 51,200 27,000-80,000 | 40x40 ~*+1,600 3,840 420 320 XC4052XL 52,000 61,952 33,000-100,000| 44x44 1936 4,576 132 352 XC4062XL_| 62,000 73,728 | 40,000- 130.000 48x48 2,304 _| 5,376 144 384 Larger Devices Available in the First Half of 1997 Note: Throughout the functional descriptions in this docu- ment, references to the XC4000E device family include the XC4000L, and references to the XC4000EX device family include the XC4000XL, unless explicitly stated otherwise. References to the XC4000 Series include the XC4000E, XC4000EX, XC4000L, and XC4000XL families. All func- tionality in low-voltage families is the same as in the corre- sponding 5-Volt family, except where numerical references are made to timing, power, or current-sinking capability. Description XC4000-Series devices are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading configuration data into internal memory cells. The FPGA can either actively read its configuration data from an external serial or byte- parallel PROM (master modes), or the configuration data * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. can be written into the FPGA from an external device (slave, peripheral and Express modes). XC4000-Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, floorplanning, simula- tion, automatic block placement and routing of intercon- nects, to the creation, downloading, and readback of the configuration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hard- ware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for produc- tion rates well beyond 5,000 systems per month. For lowest high-volume unit cost, a design can first be implemented in the XC4000E or XC4000EX, then migrated to one of Xilinx compatible HardWire mask-programmed devices. Tabie 2 shows density and performance for a few common circuit functions that can be implemented in XC4000-Series devices. 4-6 July 30, 1996 (Version 1.03)$< XILINX Table 2: Density and Performance for Several Common Circuit Functions in XC4000E! | Design Class Function | CLBs Used | XC4000E-3 | XC4000E-2 | Units 256 x 8 Single Port (read/modify/write) | 72 6 80 _ | Mhz - | Memory | 32x 16 bit FIFO | simultaneous read/write 48 63 80 MHz | MUXed read/write 32 63 80 MHz | | 9 bit Shift Register (with enable) OS 170 200. | MHz 16 bit Pre-Scaled Counter a 142 170 MHz 16 bit Loadable Counter 8 65 76 | MHz 16 bit Accumulator 9 6 | 76 | MHz 8 bit, 16 tap FIR Filter sample rate as Logic parallel 400 55 65 MHz | serial 68 8.1 10 MHz 8x8 Parallel Multiplier ; | single stage, register to register _ 8 37 30 | ons | 16 bit Address Decoder {internal decode) 3 AT ' 3.9 | _ns | 9 bit Parity Checker 1 43 27 | ns Note: 1. Most functions are faster in XC4000EX due to faster carry logic, direct connects, and other additional interconnect. Taking Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system. This capability gives the sys- tem designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modifications are easy, and can be made to products already in the field. An FPGA can even be recon- figured dynamically to perform different functions at differ- ent times. Reconfigurable logic can be used to implement system self-diagnostics, create systems capable of being reconfig- ured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benefit, using reconfigurable FPGA devices simpli- fies hardware design and debugging and shortens product time-to-market. July 30, 1996 (Version 1.03) 4-7XC4000 Series Field Programmable Gate Arrays XC4000E and XC4000EX Families Compared to the XC4000 For readers already familiar with the XC4000 family of Xil- inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000-Series devices are listed in this section. The biggest advantages of XC4000E and XC4000EX devices are significantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000EX devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. Most XC4000EX devices have no corresponding XC4000 devices, because of the larger CLB arrays. The XC4028EX has the same array size as the XC4025 and XC4025E, but is not bitstream-compatible. However, the XC4025, XC4025E, and XC4028EX are all pinout-compatibie. improvements in XC4000E and XC4000EX Increased System Speed Delays in FPGA-based designs are layout dependent. There is a rule of thumb designers can considerthe sys- tem clock rate should not exceed one third to one haif of the specified toggle rate. Critical portions of a design, such as shift registers and simple counters, can run fasterapprox- imately two thirds of the specified toggle rate. XC4000E and XC4000EX devices can run at synchronous system clock rates of up to 66 MHz, and internal perfor- mance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000- Series devices use a sub-micron triple-layer metal process. In addition, many architectural improvements have been made, as described below. PCi Compliance XC4000-Series -3 and faster speed grades are fully PCI compliant. XC4000E and XC4000EX devices can be used to implement a one-chip PCI solution. Carry Logic The speed of the carry logic chain has increased dramati- cally. Some parameters, such as the delay on the carry chain through a single CLB (Teyp), have improved by as much as 50% from XC4000 values. See Fast Carry Logic on page 21 for more information. Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes The RAM in any CLB can be configured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write. Dual-Port RAM A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be configured as either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-trig- gered (synchronous) dual-port RAM, or as combinatorial logic. Configurable RAM Content The RAM content can now be loaded at configuration time, so that the RAM starts up with user-defined data. H Function Generator In XC4000-Series devices, the H function generator is more versatile than in the XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function gen- erator can thus be totally or partially independent of the other two function generators, increasing the maximum capacity of the device. 10B Clock Enable The two flip-flops in each IOB have a common clock enable input, which through configuration can be activated individ- ually for the input or output flip-flop or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the lOBs more versatile, and avoids the need for clock gating. Output Drivers The output pull-up structure defaults to a TTL-like totem- pole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 outputs. Alternatively, XC4000-Series devices can be globally configured with CMOS outputs, with p-channel puil-up transistors pulling to Vcc. Also, the configurable pull- up resistor in the XC4000 Series is a p-channel transistor that pulls to Vec, whereas in the XC4000 it is an n-channel transistor that pulls to a voltage one transistor threshold below Vcc. Input Thresholds The input thresholds can be globaily configured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two global adjustments of input threshold and output level are independent of each other. 4-8 July 30, 1996 (Version 1.03)$< XILINX Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Configuration Pin Pull-Up Resistors During configuration, the three mode pins, MO, M1, and M2, have weak pull-up resistors. For the most popular con- figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually configured with or without weak pull-up or pull-down resistors after configu- ration. The PROGRAM input pin has a permanent weak pull-up. Soft Start-up Like the XC3000A, XC4000-Series devices have Soft Start-up. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. This feature avoids poten- tial ground bounce when all outputs are turned on simulta- neously. immediately after start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual configuration option. XC4000 and XC4000A Compatibility Existing XC4000 bitstreams can be used to configure an XC4000E device. XC4000A bitstreams must be recom- piled for use with the XC4000E due to improved routing resources, although the devices are pin-for-pin compatible. Additional Improvements in XC4000EX Only Increased Routing New interconnect in the XC4000EX includes twenty-two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs. The twelve Quad Lines in each CLB row and column include optional repowering buffers for maximum speed. Additional high- performance routing near the |OBs enhances pin flexibility. Faster Input and Output A fast, dedicated early clock sourced by global clock buffers is available for the |OBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the early clock is available. The input data can be initially loaded into the Fast Capture latch with the early clock, then transferred to the input flip-flop or latch with the low-skew globai clock. A programmable delay on the input can be used to avoid hold-time requirements. See IOB Input Sig- nats on page 24 for more information. Latch Capability in CLBs Storage elements in the XC4000EX CLB can be configured as either flip-flops or latches. This capability makes the FPGA highly synthesis-compatible. 1OB Output MUX From Output Clock A multiplexer in the {OB allows the output clock to select either the output data or the [OB clock enable as the output to the pad. Thus, two different data signals can share a sin- gle output pad, effectively doubling the number of device outputs without requiring a larger, more expensive pack- age. This multiplexer can also be configured as an AND- gate to implement a very fast pin-to-pin path. See IOB Output Signals on page 27 for more information. Express Configuration Mode A new slave configuration mode accepts parallel data input. Data is processed in parallel, rather than serialized inter- nally. Therefore, the data rate is eight times that of the six conventional configuration modes. Additional Address Bits Larger devices require more bits of configuration data. A daisy chain of several large XC4000EX devices may require a PROM that cannot be addressed by the eighteen address bits supported in the XC4000E. The XC4000EX family therefore extends the addressing in Master Parailel configuration mode to 22 bits. July 30, 1996 (Version 1.03) 4-9XC4000 Series Field Programmable Gate Arrays Table 3: CLB Count of Selected XC4000-Series Soft Macros | 7400 Equivalents ~ CLBs Muitiplexers 138 5 brishft4 | 4 m2-le 1, 139 2 |brishfts | 13. |m4-te 1 | 1147 5 . _ m8-1e | 3 "148 | 6 4-Bit Counters mi6-1e 5 | , 150 5 jed4cd 3 |Registers | 151 | 3 i cd4cle i 5 rd4r [ 92 \'152 3 icddrle | 6 |rder | 4 | 153 2 |cb4ce | 3 |rdt6r 8 | 154 | 16 |eb4cle i 6 | 157 2 \cb4re 5 4 58 | 2 "- and 16-Bit Counters Shift Registers ; ie a eb8ce ~~ | 6 sr8ce : [4 | , icb8re ; 10 |sri6re a | 8B | M63 | p cotee G [Decoders 464 4 cc16cle 9 |q2-4e 2 465s 9 cclcied 21 | g3-8e 4 | | 466 | 5 identity Comparators d4-16e | 16 | 168 7 |comp4 1 | 474 3 |comps 2 | 194 5 |comp16 5 | 195 3 | Magnitude Comparators Explanation of counter nomenciature 280 3 jcompm4 ar cb = binary counter 283 | 8 |compms 9 cd = BCD counter 298 | 2 compmi6 20 cc = cascadable binary counter (352 ; 2 d = bidirectional +390 | 3 | = loadable 518 3 | | e =clock enable | 521 | 3 r = synchronous reset | Explanation of RAM nomenciature |RAMs _ 7 = asynchronous clear | | $=single-port edge-triggered [ram1ex4 2 | d = dual-port edge-triggered ram16x4s 2 | no extension = level-sensitive ram16x4d 4 | | 4-10 July 30, 1996 (Version 1.03)$< XILINX Detailed Functional Description XC4000-Series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. The XC4000E and XC4000EX support system clock rates of up to 66 MHz and internal performance in excess of 150 MHz. Compared to older Xilinx FPGA fami- lies, XC4000-Series devices are more powerful. They offer on-chip edge-triggered and dual-port RAM, clock enables on VO flip-flops, and wide-input decoders. They are more versatile in many applications, especially those involving RAM. Design cycles are faster due to a combination of increased routing resources and more sophisticated soft- ware. Basic Building Blocks Xilinx user-programmable gate arrays include two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). CLBs provide the functional elements for constructing the user's logic. IOBs provide the interface between the package pins and internal signal lines. Three other types of circuits are also available: 3-State buffers (TBUFs) driving horizontal longlines are associated with each CLB. * Wide edge decoders are available around the periphery of each device. Anon-chip oscillator is provided. Programmable interconnect resources provide routing paths to connect the inputs and outputs of these config- urable elements to the appropriate networks. The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections impiemented in the FPGA. Each of these available circuits is described in this section. Configurable Logic Blocks (CLBs) Configurable Logic Blocks implement most of the logic in an FPGA. The principal CLB elements are shown in Figure 1. The number of CLBs needed to implement selected soft macros is shown in Table 3. Two 4-input function generators (F and G) offer unrestricted versatility. Most combinatorial logic functions need four or fewer inputs. However, a third function generator (H) is pro- vided. The H function generator has three inputs. Either zero, one, or both of these inputs can be the outputs of F and G; the other input(s) are from outside the CLB. The CLB can, therefore, implement certain functions of up to nine variables, like parity check or expandable-identity comparison of two sets of four inputs. Each CLB contains two storage elements that can be used to store the function generator outputs. However, the stor- age elements and function generators can also be used independently. These storage elements can be configured as flip-flops in both XC4000E and XC4000EX devices; in the XC4000EX they can optionally be configured as latches. DIN can be used as a direct input to either of the two storage elements. H1 can drive the other through the H function generator. Function generator outputs can also drive two outputs independent of the storage element out- puts. This versatility increases logic capacity and simplifies routing. Thirteen CLB inputs and four CLB outputs provide access to the function generators and storage elements. These inputs and outputs connect to the programmable intercon- nect resources outside the block. Function Generators Four independent inputs are provided to each of two func- tion generators (F1 - F4 and G1 - G4). These function gen- erators, with outputs labeled F and G, are each capable of implementing any arbitrarily defined Boolean function of four inputs. The function generators are implemented as memory look-up tables. The propagation delay is therefore independent of the function implemented. A third function generator, labeled H, can implement any Boolean function of its three inputs. Two of these inputs can optionally be the F and G functional generator out- puts. Alternatively, one or both of these inputs can come from outside the CLB (H2, HO). The third input must come from outside the block (H1). Signals from the function generators can exit the CLB on two outputs. F or H can be connected to the X output. G or H can be connected to the Y output. A CLB can be used to implement any of the following func- tions: * any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables! any single function of five variables * any function of four variables together with some functions of six variables * some functions of up to nine variables. 1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Ginly two unregistered function generator outputs are available from the CLB. July 30, 1996 (Version 1.03)XC4000 Series Field Programmable Gate Arrays Cyeee 4 Din/Ha SR/Hg Ga S/R CONTROL Bypass YQ G3 LOGIC FUNCTION OF G1-G4 G2 Gy Lagic FUNCTION OF : H P.G AND Hi Fa Bypass S/R CONTROL LOGIC xa FUNCTION f: OF F3 Fg Ft-F4 Fy K (CLOCK) Multiplexer Controfled by Configuration Program x6692 Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown) Implementing wide functions in a single block reduces both ; the number of blocks required and the delay in the signal Table 4: CLB Storage Element Functionality path, achieving both increased capacity and speed. {active rising edge is shown) The versatility of the CLB function generators significantly Mode K EC SR D Q improves system speed. In addition, the design-software Power-Up or tools can deal with each function generator independently. GSR Xx x Xx SR This flexibility improves cell usage. x 1 X SR Flip-Flops Flip-Flop | __/ 1 0" N The CLB can pass the combinatorial output(s) to the inter- 0 x o connect network, but can also store the combinatorial Latch 1 mo x Q results or other incoming data in one or two flip-flops, and 0 1* 0* D D connect their outputs to the interconnect network as well. Both Xx 0 o* x Q The two edge-triggered D-type flip-flops have common Legend: , : . X on't care clock (K) and clock enable (EC) inputs. Either or both clock fT ising edge inputs can also be permanently enabled. Storage element SR ator Reset value. Reset is default. functionality is described in Table 4. a Input is Low or unconnected (default value) 1 Input is High or unconnected (default value) Latches (XC4000EX only) The CLB storage elements can also be configured as Clock input latches. The two latches have common clock (K) and clock _ Each flip-flop can be triggered on either the rising or falling enable (EC) inputs. Storage element functionality is clock edge. The clock pin is shared by both storage ele- described in Table 4. ments. However, the clock is individually invertible for each storage element. Any inverter placed on the clock input is automatically absorbed into the CLB. 4-12 July 30, 1996 (Version 1.03)Clock Enable The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. if left unconnected for either, the clock enable for that storage element defaults to the active state. EC is not invertible within the CLB. Set/Reset An asynchronous storage element input (SR) can be con- figured as either set or reset. This configuration option determines the state in which each flip-flop becomes oper- ational after configuration. It also determines the effect of a Global Set/Reset pulse during normal operation, and the effect of a pulse on the SR pin of the CLB. All three set/ reset functions for any single flip-flop are controlled by the same configuration data bit. The set/reset state can be independently specified for each flip-flop. This input can also be independently disabled for either flip-fiop. The set/reset state is specified by using the INIT attribute, or by placing the appropriate set or reset flip-flop library symbol. SR is active High. It is not invertible within the CLB. Global Set/Reset A separate Global Set/Reset line (not shown in Figure 1) sets or clears each storage element during power-up, reconfiguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. Therefore, if a flip-flop is set by SR, it is also set by GSR. Similarly, a reset flip-flop is reset by both SR and GSR. GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 2.) A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-pro- grammabie pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Set/ Reset signal. Alternatively, GSR can be driven from any internal node. STARTUP <PAD > > GSR 2} IBUE GTS a3 f aias } 5 CLK DONEIN | X5260 Figure 2: Schematic Symbols for Global Set/Reset $< XILINX Data Inputs and Outputs The source of a storage element data input is programma- ble. It is driven by any of the functions F, G, and H, or by the Direct In (DIN) block input. The flip-flops or latches drive the XQ and YQ CLB outputs. Two fast feed-through paths are available, as shown in Figure 1. A two-to-one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs. This bypass is sometimes used by the automated router to repower internal signals. Control Signals Multiplexers in the CLB map the four controi inputs (C1 - C4 in Figure 1) into the four internal control signals (H1, DIN/ H2, SR/HO, and EC). Any of these inputs can drive any of the four internal control signals. When the logic function is enabled, the four inputs are: * EC Enable Clock * SR/HO Asynchronous Set/Reset or H function generator Input 0 * DIN/H2 Direct In or H function generator Input 2 * H1H function generator input 1. When the memory function is enabled, the four inputs are: EC Enable Clock WE Write Enable * DO Data Input to F and/or G function generator D1 Data input to G function generator (16x1 and 16x2 modes) or 5th Address bit (32x1 mode). Using FPGA Flip-Flops and Latches The abundance of flip-flops in the XC4000 Series invites pipelined designs. This is a powerful way of increasing per- formance by breaking the function into smailer subfunc- tions and executing them in parallel, passing on the results through pipeline flip-flops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB flip-flop, place the appropriate library symbol. For example, FDCE is a D-type flip-flop with clock enable and asynchronous clear. The corresponding latch symbol (for the XC4000EX only) is called LDCE. In XC4000-Series devices, the flip flops can be used as registers or shift registers without blocking the function gen- erators from performing a different, perhaps unrelated task. This ability increases the functional capacity of the devices. The CLB setup time is specified between the function gen- erator inputs and the clock input K. Therefore, the specified CLB flip-flop setup time includes the delay through the function generator. July 30, 1996 (Version 1.03) 4-13XC4000 Series Field Programmable Gate Arrays Using Function Generators as RAM Optional modes for each CLB make the memory look-up tables in the F and G function generators usable as an array of Read/Write memory celis. Available modes are level-sensitive (similar to the XC4000/A/H families), edge- triggered, and dual-port edge-triggered. Depending on the selected mode, a single CLB can be configured as either a 16x2, 32x1, or 16x1 bit array. Supported CLB memory configurations and timing modes for single- and duai-port modes are shown in Table 5. XC4000-Series devices are the first programmabie logic devices with edge-triggered (synchronous) and dual-port RAM accessible to the user. Edge-triggered RAM simpli- fies system timing. Dual-port RAM doubles the effective throughput of FIFO applications. These features can be individually programmed in any XC4000-Series CLB. Advantages of On-Chip and Edge-Triggered RAM The on-chip RAM is extremely fast. The read access time is the same as the logic delay. The write access time is slightly slower. Both access times are much faster than any off-chip solution, because they avoid I/O delays. Edge-triggered RAM, also called synchronous RAM, is a feature never before available in a Field Programmable Gate Array. The simplicity of designing with edge-triggered RAM, and the markedly higher achievable performance, add up to a significant improvement over existing devices with on-chip RAM. Three application notes are available from Xilinx that dis- cuss edge-triggered RAM: XC4000E Edge-Triggered and Dual-Port RAM Capability Implementing FIFOs in XC4000E RAM? and Synchronous and Asynchronous FIFO Designs. All three application notes apply to both XC4000E and XC4000EX RAM. Table 5: Supported RAM Modes 16, 16, 32 Edge- Level- | x x | x | Triggered Sensitive. 1 2; 1 | Timing Timing Singie-Port | Vj voi Vv | v v Duai-Port Vv jou [eee RAM Configuration Options The function generators in any CLB can be configured as RAM arrays in the following sizes: * Two 16x1 RAMs: two data inputs and two data outputs with identical or, if preferred, different addressing for each RAM * One 32x1 RAM: one data input and one data output. One F or G function generator can be configured as a 16x1 RAM while the other function generators are used to imple- ment any function of up to 5 inputs. Additionally, the XC4000-Series RAM may have either of two timing modes: Edge-Triggered (Synchronous): data written by the designated edge of the CLB clock. WE acts as a true clock enable. * Level-Sensitive (Asynchronous): an external WE signal acts as the write strobe. The selected timing mode applies to both function genera- tors within a CLB when both are configured as RAM. The number of read ports is also programmable: * Single Port: each function generator has a common read and write port * Dual Port: both function generators are configured together as a single 16x1 dual-port RAM with one write port and two read ports. Simultaneous read and write operations to the same or different addresses are supported. RAM configuration options are selected by placing the appropriate library symbol. Choosing a RAM Configuration Mode The appropriate choice of RAM mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design pro- cess. Recommended usage is shown in Table 6. The difference between level-sensitive, edge-triggered, and dual-port RAM is only in the write operation. Read operation and timing is identical for all modes of operation. Table 6: RAM Mode Selection | ~ Dual-Port | | | Level- Edge- Edge | | Sensitive Triggered | Triggered | | Use for New | No Yes | Yes | | Designs? | _ to Size (16x1, 2CLB. 1/2CLB. = 1CLB CC Registered) : Simultaneous No : No Yes 1 _ Read/Write _ oe Relative | | 2X (4X Performance | x ex effective) July 30, 1996 (Version 1.03)$< XILINX Cyene ty Do a DIN WRITE DECODER 16-LATCH ARRAY Greer Ga 1 of 16 READ WRITE PULSE ADDRESS Din WRITE DECODER 16-LATCH ARRAY 4 __ FreneFa 10116 kK (CLOCK) WRITE PULSE xB752 Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM 4 Cy ee9 Cy < + | | | a L/ \/ \E WE DyiAg Do EC tT) DIN L_/ WRITE 46-LATCH [| DECODER ARRAY + Gys9"Gq 4, | Freesky v tof 16 | [) a READ | WRITE PULSE _ ADORESS A iH {] = ) DIN WRITE 16-LATCH | DECODER ARRAY 4 7 | 1 of 16 LATCH ! a K ENABLE| ; - ______.. { } Cr}! READ (CLOCK) : WRITE PULSE ADDRESS X6754 Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical) July 30, 1996 (Version 1.03) 4-15XC4000 Series Field Programmable Gate Arrays RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes when the function generators are configured as RAM. The DIN/ H2, H1, and SR/HO lines become the two data inputs (DO, D1) and the Write Enable (WE) input for the 16x2 memory. When the 32x1 configuration is selected, D1 acts as the fifth address bit and DO is the data input. The contents of the memory cell(s) being addressed are available at the F and G function-generator outputs. They can exit the CLB through its X and Y outputs, or can be cap- tured in the CLB flip-flop(s). Configuring the CLB function generators as Read/Write memory does not affect the functionality of the other por- tions of the CLB, with the exception of the redefinition of the control signals. In 16x2 and 16x1 modes, the H function generator can be used to implement Boolean functions of F, G, and D1, and the D flip-flops can latch the F, G, H, or DO signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) RAM _ simplifies timing requirements. XC4000-Series edge-triggered RAM timing operates like writing to a data register. Data and address are presented. The register is enabled for writing by a logic High on the write enable input, WE. Then a rising or falling clock edge loads the data into the register. as shown in Figure 5. Complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. The active edge of WCLK latches the address, input data, and WE sig- nals. An internal write pulse is generated that performs the write. See Figure 3 and Figure 4 for block diagrams of a CLB configured as 16x2 and 32x1 edge-triggered, single- port RAM. The relationships between CLB pins and RAM inputs and outputs for single-port, edge-triggered mode are shown in Table 7. The Write Clock input (WCLK) can be configured as active on either the rising edge (default) or the falling edge. It uses the same CLB pin (K) used to clock the CLB flip-flops, but it can be independently inverted. Consequently, the RAM output can optionally be registered within the same DATA IN ADDRESS | DATA OUT $e X6461 Figure 5: Edge-Triggered RAM Write Timing CLB either by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to both function generators in the CLB when both are config- ured as RAM. The WE pin is active-High and is not invertible within the CLB. Note: The pulse following the active edge of WCLK (Twps in Figure 5) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive: however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are con- figured as edge-triggered RAM. Table 7: Single-Port Edge-Triggered RAM Signals RAM Signal CLB Pin Function D DO or D1 Data In (18x2, 16x1) DO (32x1) A[3:0] _ Fi-F4or+~Addresst~S '@1-G4 Al) D1 (2x1) Address WE WE Write Enable WCLKOKt~<CO!OCCIOCKCO~* SPO. ~=ForG@ ~~ SinglePortOut (Data Out) __ (Data Out) 4-16 July 30, 1996 (Version 1.03)Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously at two independent addresses. Simultaneous read and write operations at the same address are also supported. Dual-port mode always has edge-triggered write timing, as shown in Figure 5. Figure 6 shows a simple model of an XC4000-Series CLB configured as dual-port RAM. One address port, labeled A[3:0], supplies both the read and write address for the F function generator. This function generator behaves the same as a 16x1 single-port edge-triggered RAM array. The RAM output, Single Port Out (SPO), appears at the F func- tion generator output. SPO, therefore, reflects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the G function generator. The write address for the G function generator, however, comes from the address A[3:0]. The output from this 16x1 RAM array, Dual Port Out (DPO), appears at the G function generator output. DPO, therefore, reflects the data at address DPRA[3:0]. RAM16X10 Primitive Co BPO (Qual Port Out) Registered DPO WE 0 DPRAIS:0} ARIS:Of Function Generator | 1 SPO (Single Port Out} D Registered SPO A530] ARIS:0] F Function Generator } WCLK x675s Figure 6: XC4000-Series Dual-Port RAM, Simpie Model $2 XILINX Therefore, by using A[3:0] for the write address and DPRA|3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effec- tive throughput of the FIFO. The relationships between CLB pins and RAM inputs and outputs for dual-port, edge-triggered mode are shown in Table 8. See Figure 7 for a block diagram of a CLB config- ured in this mode. Note: The pulse following the active edge of WCLK (Twps in Figure 5) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are con- figured as edge-triggered RAM. Table 8: Dual-Port Edge-Triggered RAM Signals RAM Signal | CLB Pin | Function D DBO | Data In A{3:0] F1-F4 Read Address for F, Write Address for F and G DPRA[3:0} G1-G4 ' Read Address for G WE WE Write Enable WCLK K Clock SPO FP Single Port Out (addressed by A[3:0]) DPO G Dual Port Out (addressed by _DPRA[3:0)) July 30, 1996 (Version 1.03) 4-17XC4000 Series Field Programmable Gate Arrays G10 J TW WwW Oo WE [P Do EC | Din | WRITE 16-LATCH oEcoDER ["-} anRay fo 4 <= 7 | 1 of 16 : LATCH TI | ENABLE ; nde : L or READ Gy+**Gy 4 4 WRITE PULSE ADDRESS ho | Ow WRITE @-LATCH DECODER ARRAY 4 4 FreecF4 a 1 of 16 | =n LATCH | Po K HENABLE | : | | SE READ (CLOCK) * WRITE PULSE ADDRESS _ X6748 Figure 7: 16x1 Edge-Triggered Dual-Port RAM 4-18 July 30, 1996 (Version 1.03)$< XILINX Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000-Series backward-com- patibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be complicated in execution. Data and address signals are presented, then a positive pulse on the write enable pin (WE) performs a write into the RAM at the designated address. As indicated by the level-sensitive label, this RAM acts like a latch. During the WE High pulse, changing the data lines results in new data written to the old address. Changing the address lines while WE is High results in spu- rious data written to the new addressand possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. The user must generate a carefully timed WE signal. The delay on the WE signal and the address lines must be care- fully verified to ensure that WE does not become active until after the address lines have settled, and that WE goes inac- tive before the address lines change again. The data must be stable before and after the falling edge of WE. In practical terms, WE is usually generated by a 2X clock. If a 2X clock is not available, the falling edge of the system clock can be used. However, there are inherent risks in this approach, since the WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several older application notes are available from Xilinx that dis- cuss the design of levei-sensitive RAMs. These application notes include XAPP031, Using the XC4000 RAM Capabil- ity and XAPP042, High-Speed RAM Design in XC4000: at ae mene However, the edge-triggered RAM available in the XC4000 Series is superior to level-sensitive RAM for almost every application. Figure 8 shows the write timing for level-sensitive, single- port RAM. The relationships between CLB pins and RAM inputs and outputs for single-port level-sensitive mode are shown in Table 9. Figure 9 and Figure 10 show block diagrams of a CLB con- figured as 16x2 and 32x1 level-sensitive, single-port RAM. Initializing RAM at Configuration Both RAM and ROM implementations of the XC4000- Series devices are initialized during configuration. The ini- tial contents are defined via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. lf not defined, all RAM contents are initialized to all zeros, by default. RAM initialization occurs only during configuration. The RAM content is not affected by Global Set/Reset. Table 9: Single-Port Level-Sensitive RAM Signals ADDRESS x ~- Tas | RAMSignal | CLBPin | Function 'D DO or D1 : Data In _ /Al3:0] Fi-F4or Address G1-G4 . | WE WE Write Enable 0 For G Data Out _ oe Ty Twe Tan WRITE ENABLE / twe-T pg a je-TpH DATA IN REQUIRED Figure 8: Level-Sensitive RAM Write Timing X6462 July 30, 1996 (Version 1.03) 4-19XC4000 Series Field Programmable Gate Arrays 4, Cy 989g bos | WE 'Dy Do EC I | | Din Enable WRITE DECODER 16-LATCH ARRAY Gyee8G, 4 tof 16 READ ADDRESS Enable DIN 16-LATCH DECODER ARRAY ~ F Fy seers 1 of 16 READ ADDRESS Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM Cy e064 DIN Enable 16-LATCH ARRAY WRITE DECODER GyeeeGyq Freesky 1 of 16 READ ADDRESS DIN Enable 16-LATCH ARRAY WRITE DECODER 1 of 16 READ ADDRESS X6749 Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical) 4-20 July 30, 1996 (Version 1.03)Fast Carry Logic Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function gen- erator in the adjacent CLB. The carry chain is independent of normal routing resources. Dedicated fast carry logic greatly increases the efficiency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addi- tion in digital signal processing are two typical applications. The two 4-input function generators can be configured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efficient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benefit at the 32-bit level. This fast carry logic is one of the more significant features of the XC4000 Series, speeding up arithmetic and counting into the 70 MHz range. The carry chain in XC4000E devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right. (See Figure 11.) In order to improve speed in the high-capacity XC4000EX devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in Figure 12. This restriction should have lit- tie impact, because the smallest XC4000EX device, the XC4028EX, can accommodate a 64-bit carry chain in a sin- gle column. Additionally, standard interconnect can be used to route a carry signal in the downward direction. Figure 13 on page 22 shows an XC4000E CLB with dedi- cated fast carry logic. The carry logic in the XC4000EX is similar, except that COUT exits at the top only, and the sig- nal CINDOWN does not exist. As shown in Figure 13, the carry logic shares operand and control inputs with the func- tion generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 14 and Figure 15 on page 23 show the details of the carry logic for the XC4000E and the XC4000EX respec- tively. These diagrams show the contents of the box labeled CARRY LOGIC in Figure 13. As shown, the XC4000EX carry logic eliminated a multiplexer to reduce delay on the pass-through carry chain. Additionally, the multiplexer on the G4 path now has a memory-programma- ble input, which permits G4 to directly connect to COUT. G4 thus becomes an additional high-speed initialization path for carry-in. $< XILINX The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: Using the Dedicated Carry Logic in XC4000? This discussion also applies to XC4000E devices, and to XC4000EX devices when the minor logic changes are taken into account. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Mac- ros (RPMs) that already include these symbols. CLB }|-+ CLB ->+ CLB |+/ CLB ie ee ee CLB CLB CLB CLB & f zt - fh J f + F + + : FF y * CLB CLB CLB CLB -| >] ; ft at 4 CLB | CLB |%s+ CLB +| CLB X6687 Figure 11: Available XC4000E Carry Propagation Paths CLB |-.-+ CLB |---+| CLB |---+| CLB CLB | :-+| CLB | :-+| CLB | :-+| CLB CLB | -+ CLB | }-+| CLB | >| CLB X6610 beweeeee ' Figure 12: Available XC4000EX Carry Propagation Paths (dotted lines use general interconnect) July 30, 1996 (Version 1.03) 4-21XC4000 Series Field Programmable Gate Arrays K S/R EC CinuP CoutT X6699 Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX) 4-22 July 30, 1996 (Version 1.03)Cour mt fr_o\ | x2000 Ciwur i Cin DowN Figure 14: Detail of XC4000E Dedicated Carry Logic Cout A Couto FA F3 $< XILINX p FUNCTION | GENERATORS i | | G24 -_> a h G@3-+ |______ TO FUNCTION GENERATORS X6701 Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic) July 30, 1996 (Version 1.03) 4-23XC4000 Series Field Programmable Gate Arrays Input/Output Blocks (IOBs) User-configurable input/output blocks (1OBs) provide the interface between external package pins and the internal logic. Each {OB controls one package pin and can be con- figured for input, output, or bidirectional signals. Figure 16 shows a simplified block diagram of the XC4000E iOB. A more complete diagram of the XC4000E 1OB can be found in Figure 42 on page 51, in the Boundary Scan section. Figure 42 includes the boundary scan logic in the IOB. Figure 17 shows a simplified block diagram of the XC4000EX IOB. The XC4000EX IOB contains some spe- cial features not included in the XC4000E IOB. These fea- tures are highlighted in Figure 17, and discussed throughout this section. When XC4000EX special! features are discussed, they are clearly identified in the text. Any feature not so identified is present in both XC4000E and XC4000EX devices. 1OB Input Signals Two paths, labeled 11 and |2 in Figure 16 and Figure 17, bring input signals into the array. Inputs also connect to an input register that can be programmed as either an edge- triggered flip-flop or a level-sensitive latch. The choice is made by placing the appropriate library sym- bol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transpar- ent-High). Variations with inverted clocks are available, and some combinations of latches and flip-flops can be imple- mented in a single IOB, as described in the XACT Libraries Guide. The inputs can be globally configured for either TTL (1.2V, default) or CMOS thresholds, using an option in the Make- Bits program. There is a slight hysteresis of about 300mV. The output levels are also configurable; the two global adjustments of input threshold and output level are inde- pendent. Inputs of the low-voitage devices must be configured as CMOS at all times. They can be driven by the outputs of all 5-Volt XC4000-Series devices, provided that the 5-Volt out- puts are in TTL mode. They can also be driven by any TTL output that does not exceed 3.7 V. 5-Volt XC3000-family device outputs, for example, are TTL-compatible, but since the output voltage can exceed 3.7 V, they cannot be used to drive an XC4000L or XC4000XL input. The inputs of XC4000-Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC4000-Series device inputs are shown in Table 10. Table 10: Supported Sources for XC4000-Series Device Inputs ' _XC4000-Series Inputs | 3.3 V, | 5V, 5V, S | ouree _CMOS , TTL | CMOS Any device, Vec = 3.3 V, CMOS outputs | XC4000-Series, Vcc = 5 V, TTL outputs | Any device, Vcc = 5 Vy 'TTL outputs (Voh < 3.7 V) Any device, Vcc = 5 V, aa CMOS outputs 1. Acceptable for XC4000XL if the designated 5-Volt supply pad (V7) is tied to 5V. VEY Registered Inputs The 11 and l2 signals that exit the block can each carry either the direct or registered input signal. The input and output storage elements in each IOB have a common clock enable input, which, through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC pin on the XC4000-Series CLB. It cannot be inverted within the 1OB. The storage element behavior is shown in Table 11. Table 11: Input Register Functionality (active rising edge is shown) f | Clock | Mode Clock | Enable D Q Power-Up or x | x x SR i GSR _ | _ ; Flip-Flop Sf Di DD. 0 Xx x Q Latch 1 1 Xx Q | 0 1* dD D | | Both xX 0 | xX Q- Legend X Don't care _f Rising edge SR Set or Reset value. Reset is default. o* Input is Low or unconnected (default value) i* Input is High or unconnected (default value) 4-24 July 30, 1996 (Version 1.03)$< XILINX 1 1 I . 1 Passive ! SContiol | | Pulse) | ' Pull-Down \ nud Le! T T J a ; Flip-Flop ! DQ ' Out c Output 1 CE Buffer Pea | Output ; 1 Clock | yy Clock Enable CE 7 Input LPT Clock | 1 I 1 | ! 1 ho | i 7] Flip- Input E ! 1 Flop/ Buffer ' \ Latch ' lp | 2 ao ! | 1 t ' 1 ' ' ; ' 1 1 1 1 x6704 Figure 16: Simplified Block Diagram of XC4000E IOB Be me mee 1 ' Siew Rate Palugy | Control Pull-Down ' i \ Output MUX i \ er | ! | ME Flip-Flop | Out dQ Output ' Output Ciock ly | i : Flip-Flop/ I : : Latch 2 + Qo Clock Enabie ; J | Input Clock + } Figure 17: Simplified Block Diagram of XC4000EX iOB (shaded areas indicate differences from XC4000E) July 30, 1996 (Version 1.03) 4-25XC4000 Series Field Programmable Gate Arrays Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input flip-flop is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input flip-flop setup time is defined between the data measured at the device I/O pin and the clock input at the 1OB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the {OB must, there- fore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufficient delay eliminates the possibility of a data hold-time requirement at the external pin. The maxi- mum delay is therefore inserted as the default. The XC4000E IOB has a one-tap delay element: either the delay is inserted (default), or itis not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC4000E global clock buffers. (See Global Nets and Buffers (XC4000E only) on page 41 for a description of the global clock buffers in the XC4000E.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the flip-flop. The XC4000EX [OB has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The attributes or properties used to select the desired delay are shown in Table 12. The choices are no added attribute, MEDDELAY, and NODELAY. The default setting, with no added attribute, ensures no hold time with respect to any of the XC4000EX clock buffers, including the Global Low- Skew buffers. MEDDELAY ensures no hold time with respect to the Global Early and FastCLK buffers. Inputs with NODELAY may have a positive hold time with respect to all clock buffers, including the FastCLK buffers. For a description of each of these buffers, see Global Nets and Buffers (XC4000EX only) on page 43. Table 12: XC4000EX [OB Input Delay Element Value When to Use ' full delay Zero Hold with respect to Global Low- | (default, no | Skew Buffer, Global Early Buffer, or | | attribute added) | FastCLK Buffer MEDDELAY Zero Hold with respect to Global Early ; Buffer or FastCLK Buffer | NODELAY "Short Setup, positive Hold time Additional Input Latch for Fast Capture (XC4000EX only) The XC4000EX 1OB has an additional optional latch on the input. This latch, as shown in Figure 17, is clocked by the output clock the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the [OB flip-flop or latch. To use this Fast Capture technique, drive the output clock pin (the Fast Capture latching signal) from the output of one of the Global Early or FastCLK buffers supplied in the XC4000EX. The second storage element should be clocked by a Global Low-Skew buffer, to synchronize the incoming data to the internal logic. (See Figure 18.) These special buffers are described in Global Nets and Buffers (XC4000EX only) on page 43. The Fast Capture latch is designed primarily for use with a Global Early buffer. For Fast Capture, a single clock signal is routed through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) The Fast Capture latch is clocked by the Global Early buffer, and the standard IOB flip-flop or latch is clocked by the Global Low-Skew buffer. This mode is the safest way to use the Fast Capture latch, because the clock buffers on both storage elements are driven by the same pad. There is no external skew between clock pads to create potential problems. Alternatively, a FastCLK buffer can be used to minimize the setup time of device inputs, if a positive hold time is accept- able. Use the FastCLK buffer to clock the Fast Capture latch, and a slower clock buffer to clock the standard |OB flip-flop or latch. Either the Global Early buffer or the Global Low-Skew buffer can be used for the second storage ele- ILDFFDX {iPad >_-_---- D t-~-} Qk internal | jogic a ~ GF 4 BUFGE CE Q [ead >+-{>_ S$ BUFGLS ILDFFDX {eap>H~ D J a to internal __ | logic GF ia BUFFCLK | _CE TZ) p G : [PAD> > NODELAY BUFGLS Figure 18: Examples Using XC4000EX Fast Capture Latch 6705 4-26 July 30, 1996 (Version 1.03)ment, but whichever one is used should be the same clock as the related internal logic. Since the FastCLK pads are different from the Global Early and Global Low-Skew pads, care must be taken to ensure that skew external to the device does not create internal timing difficulties. To place the Fast Capture latch in a design, use one of the special library symbols, ILDFFDX or ILDFLDX. ILDFFDX is a transparent-Low Fast Capture latch followed by an active-High input flip-flop. ILDFLDX is a transparent-Low Fast Capture latch followed by a transparent-High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the 1OB. If a single BUFG output is used to drive both clock inputs, the software automatically runs the clock through both a Global Low-Skew buffer and a Global Early buffer, and clocks the Fast Capture latch appropriately. Figure 17 on page 25 also shows a two-tap delay on the input. By default, if the Fast Capture latch is used, the Xilinx software assumes a Global Early buffer is driving the clock, and selects MEDDELAY to ensure a zero hold time. This default can be overridden to remove the delay, if FastClk is used, by attaching a NODELAY attribute or property to the ILDFFD or ILDFLD latch. Select the desired delay based on the discussion in the previous subsection. 10B Output Signals Output signals can be optionally inverted within the IOB, and can pass directly to the pad or be stored in an edge- triggered flip-flop. The functionality of this flip-flop is shown in Table 13. An active-High 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB. The 4-mA maximum output current specification of many FPGAs often forces the user to add external buffers, which are especially cumbersome on bidirectional I/O lines. The XC4000E and XC4000EX devices solve many of these problems by providing a guaranteed output sink current of 12 mA. Two adjacent outputs can be interconnected exter- nally to sink up to 24 mA. (XC4000L and XC4000XL out- puts can sink up to 4 mA, and two adjacent XC4000L and XC4000XL outputs can sink up to 8 mA.) The XC4000E and XC4000EX FPGAs can thus directly drive buses on a printed circuit board. $= XILINX Table 13: Output Flip-Flop Functionality (active rising edge is shown) , | Clock | |__Mode | Clock | Enable | T | D | @ iPower-Up | = X x 0* Xx SR Lor GSR | X 0 0* x Q | Flip-Flop ! r oC D | x x 1 xX Zz : x o* X Q Legend: X Don't care _/ Rising edge SR Set or Reset value. Reset is default. o* Input is Low or unconnected (default value) 1* input is High or unconnected (default value) Zz 3-state By default, the output pull-up structure is configured as a TTL-like totem-pole. The High driver is an n-channel pull- up transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally con- figured as CMOS drivers, with p-channel pull-up transistors pulling to Vec. This MakeBits option applies to all outputs on the device. It is not individually programmable. Outputs of low-voltage devices must be configured as CMOS at all times. They can drive the inputs of any 5-Volt . device with TTL-compatible thresholds. Any XC4000-Series 5-Volt device with its outputs config- ured in TTL mode can drive the inputs of any typical 3.3- Volt device. (For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products sec- tion of The Programmable Logic Data Book.) Supported destinations for XC4000-Series device outputs are shown in Table 14. Table 14: Supported Destinations for XC4000-Series Outputs T xC4000-Series Outputs | Destination 33V, 5V, | 5V, | CMOS; TTL | CMOS Any typical device, Vec=3.3V) Vv | Vv. [ some! CMOS-threshold inputs | Anydevice, Vec=5V, = =3| Vo i voi vv } TTL-threshold inputs Any device, Vec = 5 V, _CMOS-threshold inputs | 1. Only if destination device has 5-V tolerant inputs July 30, 1996 (Version 1.03) 4-27XC4000 Series Field Programmable Gate Arrays OPAD OBUFT X6702 Figure 19: Open-Drain Output An output can be configured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (1) to Ground. (See Figure 19.) Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground pin pair. For XC4000EX devices, additional internal Power/ Ground pin pairs are connected ta special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000EX devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns dura- tion. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000-Series devices have a feature called Soft Start- up, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter- mined by the individual configuration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 16 or Figure 17) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not com- pete with other routing resources; it uses a dedicated distri- bution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specific pin loca- tion can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to GSR. See Figure 2 on page 13 for details. Alternatively, GTS can be driven from any internal node. Output Multiplexer/2-input Function Generator (XC4000EX only) As shown in Figure 17 on page 25, the output path in the XC4000EX 1OB contains an additional multiplexer not avail- able in the XC4000E IOB. The multiplexer can also be con- figured as a 2-input function generator, implementing a pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 inverted inputs. The logic used to implement these func- tions is shown in the upper gray area of Figure 17. When configured as a multiplexer, this feature allows two output signals to time-share the same output pad; effec- tively doubling the number of device outputs without requir- ing a larger, more expensive package. When the MUX is configured as a 2-input function genera- tor, logic can be implemented within the |OB itself. Com- bined with either a FastCLK or Global Early buffer, this arrangement allows very high-speed gating of a single sig- naj. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a FastCLK buffer, as shown in Figure 20. The critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. (This value may not be achievable in XC4000XL devices.) As shown in Figure 17, the |OB input pins Out, Output Clock, and Clock Enable have different delays and different flexibilities regarding polarity. Additionally, Output Clock sources are more limited than the other inputs. Therefore, the Xilinx software does not move logic into the 1OB func- tion generators unless explicitly directed to do so. BUFFCLK from internal logic X6698 Figure 20: Fast Pin-to-Pin Path in XC4000E 4-28 July 30, 1996 (Version 1.03)bo F 2 a D1 OAND2 so, X6598 oo Figure 21: Output AND and MUX Symbols in XC4000EX 1OB The user can specify that the [OB function generator be used, by placing special library symbols beginning with the letter O. For example, a 2-input AND-gate in the lIOB func- tion generator is called OAND2. Use the symbol input pin labelled F for the signai on the critical path. This signal is placed on the OK pin the [OB input with the shortest delay to the function generator. Two examples are shown in Figure 21. Other IOB Options There are a number of other programmable options in the XC4000-Series 1OB. Pull-up and Pull-down Resistors Programmable pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to Vcc. The configurable pull-down resistor is an n-channel transis- tor that pulls to Ground. The value of these resistors is 50 kQ 100 kQ. This high value makes them unsuitable as wired-AND pull-up resis- tors. The pull-up resistors for most user-programmable IOBs are active during the configuration process. See Table 24 on page 78 for a list of pins with pull-ups active before and dur- ing configuration. After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resis- tor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull- up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Independent Clocks Separate clock signals are provided for the input and output flip-flops. The clock can be independently inverted for each flip-flop within the |OB, generating either falling-edge or ris- ing-edge triggered flip-flops. The clock inputs for each |OB $= XILINX are independent, except that in the XC4000EX, the Fast Capture latch shares an IOB input with the output clock pin. Early Clock for 1OBs (XC4000EX only) Special early clocks are available for IOBs. These clocks are sourced by the same sources as the Global Low-Skew buffers, but are separately buffered. They have fewer loads and therefore less delay. The early clock can drive either the [OB output clock or the IOB input clock, or both. The early clock allows fast capture of input data, and fast clock- to-output on output data. The Global Early buffers that drive these clocks are described in Global Nets and Buff- ers (XC4000EX only) on page 43. Fast Clock for lIOBs (XC4000EX only) Very fast clocks driven by FastCLK buffers are also avail- able for IOBs. These clocks are sourced by semi-dedicated padsthe pads can be used as general I/O if not used to drive FastCLK buffers. There are two FastCLK buffers on the left edge, and two on the right edge of the device. They provide the fastest method of reaching the iOB clock pins. The FastCLK buffer can drive either the IOB output clock or the IOB input clock, or both. These buffers allow the fastest possible setup times and clock-to-output times. The Fast- CLK buffers are described in Global Nets and Buffers (XC4000EX only) on page 43. Global Set/Reset As with the CLB registers, the Global Set/Reset signal (GSR) can be used to set or clear the input and output reg- isters, depending on the value of the INIT attribute or prop- erty. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-controlled set/reset signal is avail- able to the 1/O flip-flops. The choice of set or clear applies to both the initial state of the flip-flop and the response to the Global Set/Reset pulse. See Giobal Set/Reset on page 13 for a description of how to use GSR. JTAG Support Embedded logic attached to the |OBs contains test struc- tures compatible with IEEE Standard 1149.1 for boundary scan testing, permitting easy chip and board-levei testing. More information is provided in Boundary Scan on page 50. Three-State Buffers A pair of 3-state buffers is associated with each CLB in the array. (See Figure 27 on page 34.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programma- ble pull-up resistors attached to these longlines help to implement a wide wired-AND function. July 30, 1996 (Version 1.03) 4-29XC4000 Series Field Programmable Gate Arrays The buffer enable is an active-High 3-state {i.e. an active- Low enable), as shown in Table 15. Another 3-state buffer with similar access is located near each 1/O block along the right and left edges of the array. (See Figure 33 on page 39.) The horizontal longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. Special longlines running along the perimeter of the array can be used to wire-AND signals coming from nearby |OBs or from internal longlines. These fonglines form the wide edge decoders discussed in Wide Edge Decoders on page 31. Three-State Buffer Modes The 3-state buffers can be configured in three modes: * Standard 3-state buffer * Wired-AND with input on the | pin Wired OR-AND Standard 3-State Buffer All three pins are used. Place the library element BUFT. Connect the input to the | pin and the output to the O pin. The T pin is an active-High 3-state (i.e. an active-Low enable). Tie the T pin to Ground to implement a standard buffer. Wired-AND with Input on the ! Pin The buffer can be used as a Wired-AND. Use the WAND1 library symbol, which is essentially an open-drain buffer. Z=D,@D, @(D,+D,) #(D,+D,) e OD o, | Q c ~ : e Oy %5 Oo, =o WAND1 WORZAND Dy [27 WANDI WAND4, WAND8, and WAND16 are also available. See the XACT Libraries Guide for further information. The T pin is internally tied to the | pin. Connect the input to the | pin and the output to the O pin. Connect the outputs of all the WAND1s together and attach a PULLUP symbol. Wired OR-AND The buffer can be configured as a Wired OR-AND. A High level on either input turns off the output. Use the WORZAND library symbol, which is essentially an open- drain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the 10 and 11 pins and tie the output to the O pin. Tie the outputs of ail the WORZANDs together and attach a PULLUP symbol. Three-State Buffer Examples Figure 22 shows how to use the 3-state buffers to imple- ment a wired-AND function. When all the buffer inputs are High, the pull-up resistor(s) provide the High output. Figure 23 shows how to use the 3-state buffers to imple- ment a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 15. Table 15: Three-State Buffer Functionality [IN TT | OUT WORZAND xeaas Figure 22: Open-Drain Buffers implement a Wired-AND Function Z=D,ytA+Dg*B+0gC+ Dy oN Weak Keeper" Figure 23: 3-State Buffers Implement a Multiplexer * oe | Dg pb Dg Dy | BuFT BUFT BUFT a c xn esse 4-30 July 30, 1996 (Version 1.03)Wide Edge Decoders Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data field is wider than the function generator inputs. FPGAs need multi-level decoding and are thus slower than PALs. XC4000-Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000-Series FPGA has four programmable decod- ers located on each edge of the device. The inputs to each decoder are any of the [OB 11 signals on that edge plus one local interconnect per CLB row or column. Each row or col- umn of CLBs provides up to three variables or their compii- ments., as shown in Figure 24. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to a product term in typical PAL devices. Each of these wired-AND gates is capable of accepting up to 42 inputs on the XC4005E and 72 on the XC4013E. There are up to 96 inputs for each decoder on the XC4028EX and 132 on the XC4052EX. The decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. The decoder outputs can drive CLB inputs, so they can be combined with other logic to form a PAL-like AND/OR struc- ture. The decoder outputs can also be routed directly to the chip outputs. For fastest speed, the output should be on the same chip edge as the decoder. Very large PALs can be emulated by ORing the decoder outputs in a CLB. This decoding feature covers what has tong been considered a weakness of older FPGAs. Users often resorted to exter- nal PALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000-Series device can implement these functions fast and efficiently. To use the wide edge decoders, place one or more of the WAND library symbols (WAND1, WAND4, WAND8, WAND16). Attach a DECODE attribute or property to each WAND symbol. Tie the outputs together and attach a PUL- LUP symbol. Location attributes or properties such as L (left edge) or TR (right half of top edge) should also be used to ensure the correct placement of the decoder inputs. $< XILINX INTERCONNECT C).... C)... Bec)... *C).. X2627 Figure 24: XC4000-Series Edge Decoding Example On-Chip Oscillator XC4000-Series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for config- uration memory clearing, and as the source of CCLK in Master configuration modes. The oscillator runs at a nom- inal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 and 10 MHz. (The oscillator operates more slowly at Jower volt- ages. The output frequency may be reduced by as much as 10% for low-voltage devices.) The oscillator output is optionally available after configura- tion. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. There- fore, if the primary oscillator output is running at the nomi- nal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%, These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code (see Figure 25). The oscillator is automatically disabled after configuration if the OSC4 symbol is not used in the design. OSC4 F8M |} F500K |- FAGK jf F490 | F15 | xa708 Figure 25: XC4000-Series Oscillator Symboi July 30, 1996 (Version 1.03) 4-31XC4000 Series Field Programmable Gate Arrays Programmable Interconnect All internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efficient automated routing. The XC4000E and XC4000EX share a basic interconnect structure. XC4Q00EX devices, however, have additional routing not available in the XC4000E. The extra routing resources allow high utilization in high-capacity devices. All XC4000EX-specific routing resources are clearly identi- fied throughout this section. Any resources not identified as XC4000EX-specific are present in all XC4000-Series devices. This section describes the varied routing resources avail- able in XC4000-Series devices. The implementation soft- ware automatically assigns the appropriate resources based on the density and timing requirements of the design. Interconnect Overview There are several types of interconnect. * CLB routing is associated with each row and column of the CLB array. {OB routing forms a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the internal logic blocks. Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals. Five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (XC4000EX only), and longlines. In the XC4000EX, direct connects allow fast data flow between adjacent CLBs, and between IOBs and CLBs. Extra routing is included in the 1OB pad ring. The XC4000EX also includes a ring of octal interconnect lines near the IOBs to improve pin-swapping and routing to locked pins. XC4000E devices include two types of global buffers, while XC4000EX devices have three different types. These glo- bal buffers have different properties, and are intended for different purposes. They are discussed in detail later in this section. CLB Routing Connections A high-level diagram of the routing resources associated with one CLB is shown in Figure 26. The shaded arrows represent routing present only in XC4000EX devices. Table 16 shows how much routing of each type is available in XC40Q0E and XC4000EX CLB arrays. Clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the XC4000EX. Smaller XC4000E designs, typically requiring significantly less interconnect, do not require the additional routing. Figure 27 on page 34 is a detailed diagram of both the XC4000E and the XC4000EX CLB, with associated rout- ing. The shaded square is the programmable switch matrix, present in both the XC4000E and the XC4000EX. The L-shaped shaded area is present only in XC4000EX devices. As shown in the figure, the XC4000EX block is essentially an XC4000E block with additional routing. CLB inputs and outputs are distributed on all four sides, providing maximum routing flexibility. In generat, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, out- puts, and function generators can freely swap positions within a CLB to avoid routing congestion during the place- ment and routing operation. Table 16: Routing per CLB in XC4000-Series Devices [ XC4000E XC4000EX | Vertical Horizontal Vertical | Horizontal | Singles 8 8 8 8 Doubles 4 4 a Quads o- Re 120 iLongiines | 6 610 6 (Direct 0 0 : 2 2 | (Connects fo Globals 4 0 8 | Oo | Canylogic] 2 =, OF | 1 | 0 | Total | 4 188 4-32 July 30, 1996 (Version 1.03)$= XILINX co Q 5 Qa | a a : Direct Connect > Long a . 4 6 4 8 4 VW VY VY VY Quad Long Global Long Double Single Global Carry Direct Clock Clock Chain Connect x5994 Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only) July 30, 1996 (Version 1.03) 4-33XC4000 Series Field Programmable Gate Arrays QUAD DOUBLE SINGLE DOUBLE LONG DIRECT FEEDBACK #20262 LONG + OY 9% ~~ 4 % % %, % % %@ % @% G % % % Q % =] Common to XC4000E and XC4000EX 2 XC4000EX only BB Programmable Switch Matrix Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB 4-34 July 30, 1996 (Version 1.03)$= XILINX o Bs x & > . Rw 3 9 S 9 | Double poceetes Teen Singles | Six Pass Transistors Per Switch Matrix Double Interconnect Point X6600 Figure 28: Programmable Switch Matrix (PSM) Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to establish connections between the lines (see Figure 28). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou- ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix. CLB CLB Single-Length Lines Single-length lines provide the greatest interconnect flexi- bility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switch- ing matrices that are located in every row and a column of CLBs. Single-length tines are connected by way of the program- mable switch matrices, as shown in Figure 29. Routing connectivity is shown in Figure 27. Single-length lines incur a delay whenever they go through a switching matrix. Therefore, they are not suitable for rout- ing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one. Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a switch matrix. Double-length lines are grouped in pairs with the switch matrices stag- gered, so that each line goes through a switch matrix at every other row or column of CLBs (see Figure 29). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Double-iength lines are connected by way of the programmable switch matrices. Routing connectivity is shown in Figure 27. CLB . CLB CLB CLB Lt Doubles PSM = Singles MT Doubles m4 CLB lh TM xX PSM cry | CLB X6601 Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs) July 30, 1996 (Version 1.03) 4-35XC4000 Series Field Programmable Gate Arrays Quad Lines (XC4000EX only) XC4000EX devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected via buffered switch matrices (shown as dia- monds in Figure 27 on page 34). Quad lines run past four CLBs before entering a buffered switch matrix. They are grouped in fours, with the buffered switch matrices stag- gered, so that each line goes through a buffered switch matrix at every fourth CLB location in that row or column. (See Figure 30.) The buffered switch matrixes have four pins, one on each edge. All of the pins are bidirectional. Any pin can drive any or all of the other pins. Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch matrix shown in Figure 28, with the addition of a program- mable buffer. There can be up to two independent inputs and up to two independent outputs. Only one of the inde- pendent inputs can be buffered. The place and route software automatically uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. A heavily loaded sig- nal is typically buffered, while a tightly loaded one is not. One scenario is to alternate buffers and pass transistors. This allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. Due to the buffered switch matrices, quad lines are very fast. They provide the fastest available method of routing heavily loaded signals for long distances across the device. ti Figure 30: Quad Lines (XC4000EX only) X6602 4-36 July 30, 1996 (Version 1.03)Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000EX devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fan- out nets. Two horizontal longlines per CLB can be driven by 3-state or open-drain drivers (TBUFs). They can therefore imple- ment unidirectional or bidirectional buses, wide multiplex- ers, or wired-AND functions. (See Three-State Buffers on page 29 for more details.) Each horizontal longline driven by TBUFs has either two (XC4000E) or eight (XC4000EX) pull-up resistors. To acti- vate these resistors, attach a PULLUP symbol to the long- line net. The software automatically activates the appropri- ate number of pull-ups. There is also a weak keeper at each end of these two horizontal longlines. This circuit pre- vents undefined floating levels. However, it is overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmable splitter switch at its center, as does each XC4000EX longline driven by TBUFs. This switch can separate the line into two indepen- dent routing channels, each running half the width or height of the array. Each XC4000EX fongline not driven by TBUFs has a buff- ered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. Due to the buffering, XC4000EX ton- gline performance does not deteriorate with the larger array sizes. If the longline is split, the resulting partial longlines are independent. Routing connectivity of the longlines is shown in Figure 27 on page 34. = XILINX Direct Interconnect (XC4000EX only) The XC4000EX offers two direct, efficient and fast connec- tions between adjacent CLBs. These nets facilitate a data flow from the left to the right side of the device, or from the top to the bottom, as shown in Figure 31. Signals routed on the direct interconnect exhibit minimum interconnect prop- agation delay and use no general routing resources. The direct interconnect is also present between CLBs and adjacent IOBs. Each !OB on the left and top device edges has a direct path to the nearest CLB. Each CLB on the right and bottom edges of the array has a direct path to the nearest two |OBs, since there are two IOBs for each row or column of CLBs. The place and route software uses direct interconnect whenever possible, to maximize routing resources and min- imize interconnect delays. 5} |S 5] |5 5] 15 DD a Oo oO am ao 108 } ttm] }[_108 CLB CLB CLB 108 [Ab t>{_108 J Lod Lok a od Tr gy gd 108 _}| Lai rT op |->{" 108 | CLB CLB (0B tt by }->[108_] ; | | | ee S| |S S| |o 3; |S E a a ;| G x6603 Figure 31: XC4000EX Direct Interconnect July 30, 1996 (Version 1.03) 4-37XC4000 Series Field Programmable Gate Arrays VO Routing XC4000-Series devices have additional routing around the 1OB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines spanning two CLBs (four fOBs), and four longlines. Global lines and Wide Edge Decoder lines are provided. XC4000EX devices also include eight octal lines. A high-level diagram of the VersaRing is shown in Figure 32. The shaded arrows represent routing present only in XC4000EX devices. | Direct Connect 4 4 VW VY Decode 4 Vv Figure 33 is a detailed diagram of the XC4000E and XC4000EX VersaRing. The area shown includes two IOBs. There are two [{OBs per CLB row or column, therefore this diagram corresponds to the CLB routing diagram shown in Figure 27 on page 34. The shaded areas represent routing and routing connections present only in XC4000EX devices. Quad Single Double Long Direct Connect Long Edge Double Long Giobal Octal Clock X5995 Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000EX only) 4-38 July 30, 1996 (Version 1.03)$= XILINX QUAD DOUBLE SINGLE DOUBLE LONG <rPpvuUDvr ora oa DECODER DIRECT DECODER LONG LJ Common to XC4000E and XC4000EX XC4000EX only Figure 33: Detail of Programmable interconnect Associated with XC4000-Series IOB (Left Edge) July 30, 1996 (Version 1.03) 4-39XC4000 Series Field Programmable Gate Arrays Octal I/O Routing (XC4000EX only) Between the XC4000EX CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and fixed pinout flexibility. (See Figure 34.) These routing tracks are called octals, because they can be broken every eight CLBs (sixteen IOBs) by a programma- ble buffer that also functions as a splitter switch. The buff- ers are staggered, so each line goes through a buffer at every eighth CLB location around the device edge. The octal lines bend around the corners of the device. The lines cross at the corners in such a way that the segment most recently buffered before the turn has the farthest dis- tance to travel before the next buffer, as shown in Figure 34. JOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and dou- ble-length lines, quads, and longlines within the CLB array. Segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device. iOB / 7 LO 108 / I Segment with nearest buffer iv : connects to segment with furthest buffer Figure 34: XC4000EX Octal I/O Routing 4-40 July 30, 1996 (Version 1.03)$< XILINX Global Nets and Buffers Both the XC4000E and the XC4000EX have dedicated glo- bal networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in detail in the following sections. The text descriptions and diagrams are summarized in Table 17. The table shows which CLB and IOB clock pins can be sourced by which global buffers. In both XC4000E and XC4000EX devices, placement of a library symbol called BUFG results in the software choos- ing the appropriate clock buffer, based on the timing requirements of the design. The detailed information in these sections is included only for reference. Global Nets and Buffers (XC4000E only) Four vertical fonglines in each CLB column are driven exclusively by special global buffers. These jonglines are in addition to the vertical longlines used for standard inter- connect. The four global lines can be driven by either of two types of global buffers. The clock pins of every CLB and IOB can also be sourced from local interconnect. Two different types of clock buffers are available in the XC4000E: * Primary Global Buffers (BUFGP) * Secondary Global Buffers (BUFGS) Table 17: Clock Pin Access Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to poten- tially heavier loading, but offer greater flexibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semi- dedicated pads. The Secondary Global buffers can be sourced by either semi-dedicated pads or internal nets. Each CLB column has four dedicated vertical Global lines. Each of these lines can be accessed by one particular Pri- mary Global buffer, or by any of the Secondary Global buff- ers, as shown in Figure 35. Each corner of the device has one Primary buffer and one Secondary buffer. IOBs along the left and right edges have four vertical global longlines. Top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. A global buffer should be specified for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=L attribute or property to a BUFGS symbol to direct that a buffer be placed in one of the two Secondary Global buffers on the left edge of the device, or a LOC=BL to indicate the Secondary Global buffer on the bottom edge of the device, on the left. XC4000E XC4000EX Local en en -c| L&R T&B BUFFCL __siinter- BUFGP | BUFGS | BUFGLS BUFGE | BUFGE K connect All CLBs in Quadrant vo v v v Vv v All CLBs in Device Yo oN v V IOBs on Adjacent Vertical rn aa v v v \ Half Edge fl coe IOBs on Adjacent Vertical yy Voy V Full Edge . /1OBs on Adjacent Horizontal v a - V Half Edge (Direct) ea oe IOBs on Adjacent Horizontal vO v v vy y V Half Edge (through CLB globals) IOBs on Adjacent Horizontal vo V ma ee bo fo v Full Edge (through CLB globals) ae : L = Left, R = Right, T = Top, B = Bottom July 30, 1996 (Version 1.03) 4-41XC4000 Series Field Programmable Gate Arrays 108 108 2] I a: BUFGS a s i 8| 3 : PGCKI Ci SGCK1 Toe 4 BUFGP : I 4 ocals pe 10B | i | [ . =] Any BUFGS | a Lae : One BUFGP - | 108 per Global Line }. wal) Pcu5| 108 Figure 35: XC4000E Global Net Distribution BUFGLS 1OB 108 +> Al os GCKi GCKB | : Lp p--_--+. wa BUFGE | | 7 | (Ro. BUFGLS v BUFGE \ | rl | 2| | | 348 L + t \ __ BUFFCLK ,. - BUFGLS 8 aoe at FOLK! (BUFGLS 8 | locals 7 ais 8 fogals 7 | al. a CLB CLOCKS t L a4 4 \ os [4 - hy : (PER COLUMN) | : (oe clocks * u ' : j locals ' : locals | i : lop CUB CLOCKS | 108 | P CLOCKS (PER COLUMN) | at BL f early locais locals. ay 1 ELS 8 . BUFGLS 8.1 | FCLK2 j : XB}_---4 ee BUFFCLK ~ i i I t + t | BUFGLS. ES BUFGE to BUFGE T Q col a | ~ 1 ete +b . 4 wae BUFGLS 10B Figure 36: XC4000EX Global Net Distribution 108 108 2 2 | I$ | 3 BUFGP i - 7 $1 SGCK4 tne PGCKA 4y | T | BUFGS | 4 i locals a ' 10B : . + jocals . . L. . Any BUFGS t | One BUFGP | locals : i per Global Line i - | j08 EI-L Pans + : | BUFGP a SGCK3 , PGCK3 2 BUFGS |OB XB60S BUFGLS GCKB cup clocks (PER COLUMN} 108 | CLOCKS | CLB CLOCKS (PER COLUMN} 3} g roi 8 lj. | 8 ES | 3 g JOB 10B BUFGLS. X6694 4-42 July 30, 1996 (Version 1.03)Global Nets and Buffers (XC4000EX only) Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The global lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. Each half-column global line has its own buffered multiplexer, as shown in Figure 36. The top and bottom glo- bal lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. The top and bottom halves of the global lines must be separately driven although they can be driven by the same global buffer. The eight global lines in each CLB column can be driven by either of two types of global buffers. They can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. Consequently, the number of different clocks that can be used simultaneously in an XC4000EX device is very large. There are four global lines feeding the lOBs at the left edge of the device. IOBs along the right edge have eight global lines. There is a single global line along the top and bottom edges with access to the IOBs. All 1OB global lines are bro- ken at the center. They cannot be connected across the center of the device, as this connection might introduce unacceptable skew. 1OB global lines can be driven from any of three types of global buffers, or from local interconnect. Alternatively, top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. Three different types of clock buffers are available in the XC4000EX: Global Low-Skew Buffers (BUFGLS) e Global Early Buffers (BUFGE) FastCLK Buffers (BUFFCLK) Giobal Low-Skew Buffers are the standard clock buffers. They should be used for most internat clocking, whenever a large portion of the device must be driven. Global Early Buffers are designed to provide a faster clock access, but CLB access is limited to one-fourth of the device. They also facilitate a faster I/O interface. FastCLK buffers are specifically designed to provide the fastest possible I/O clock. They have only the standard input access to CLBs, through local interconnect. Figure 36 is a conceptual diagram of the global net struc- ture in the XC4000EX. Global Early buffers and Giobal Low-Skew buffers share a single pad. Therefore, the same IPAD symbol can drive one buffer of each type, in parallel. This configuration is particularly useful when using the Fast Capture latches, as described in 1OB Input Signals on page 24. Paired Global $< XILINX Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals. Choosing an XC4000EX Clock Buffer The clocking structure of the XC4000EX provides a large variety of features. However, it can be simple to use, with- out understanding all the details. The software automati- cally handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. In fact, if a buffer symbol called BUFG is placed, rather than a specific type of buffer, the software even chooses the buffer most appropriate for the design. The detailed information in this section is provided for those users who want a finer level of control over their designs. If fine control is desired, use the following summary and Table 17 on page 41 to choose an appropriate clock buffer. * The simplest thing to do is to use a Global Low-Skew buffer. Ifa faster clock path is needed, try a BUFG. The software will first try to use a Global Low-Skew Buffer. If timing requirements are not met, a faster buffer will automatically be used. lfasingle quadrant of the chip is sufficient for the clocked logic, and the timing requires a faster clock than the Global Low-Skew buffer, use a Global Early buffer. In special cases, where both external and internal timing have been carefully studied, a FastCLK buffer can be used, for the fastest possible I/O clock path. Global Low-Skew Buffers Each corner of the XC4000EX device has two Global Low- Skew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any of the four vertical lines accessing the IOBs on the left edge of the device, and any of the eight vertical lines accessing the 1OBs on the right edge of the device. (See Figure 37 on page 44.) IOBs at the top and bottom edges of the device are accessed through the vertical Global lines in the CLB array, as in the XC4000E. Any Global Low-Skew buffer can, therefore, access every |OB and CLB in the device. The Gicbai Low-Skew buffers can be driven by either semi- dedicated pads or internal logic. To use a Global Low-Skew buffer, place a BUFGLS ele- ment in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the desig- nated location. For example, attach a LOC=T attribute or property to direct that a BUFGLS be placed in one of the two Global Low-Skew buffers on the top edge of the device, or a LOC=TR to indicate the Global Low-Skew buffer on the top edge of the device, on the right. July 30, 1996 (Version 1.03) 4-43XC4000 Series Field Programmable Gate Arrays > 3 X6753 Figure 37: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Global Early Buffers Each corner of the XC4000EX device has two Global Early buffers. The primary purpose of the Global Early buffers is to provide an earlier clock access than the potentially heavily-loaded Global Low-Skew buffers. A clock source applied to both buffers will result in the Global Early clock edge occurring several nanoseconds earlier than the Gio- bal Low-Skew buffer clock edge, due to the lighter loading. Global Early buffers also facilitate the fast capture of device inputs, using the Fast Capture latches described in IOB input Signals on page 24. For Fast Capture, take a single clock signal, and route it through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) Use the Globai Early buffer to clock the Fast Capture latch, and the Global Low-Skew buffer to clock the normal input flip-flop or lJatch, as shown in Figure 18 on page 26. The Global Early buffers can also be used to provide a fast Clock-to-Out on device output pins. However, an early clock in the output flip-flop |OB must be taken into consid- eration when calculating the internal clock speed for the design. The Global Early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. Refer to Figure 38, Figure 39, and Figure 36 on page 42 while reading the following explana- tion. Each Global Early buffer can access the eight vertical Glo- bal lines for all CLBs in the quadrant. Therefore, only one- fourth of the CLB clock pins can be accessed. This restric- tion is in large part responsible for the faster speed of the buffers, relative to ine Global Low-Skew buffers. A ! CLB B I CLB CLB oO B a 2 al 10B i 10B }<J 8 3 4 X6751 Figure 38: Left and Right BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant or Edge (GCK1 is shown. GCK2, GCK5 and GCKG6 are similar.) The left-side Global Early buffers can each drive two of the four vertical lines accessing the |OBs on the entire left edge of the device. The right-side Global Early buffers can each drive two of the eight vertical lines accessing the IOBs on the entire right edge of the device. (See Figure 38.) Each left and right Global Early buffer can also drive half of the IOBs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the Global Early buffers. The top and bottom Global Early buffers can drive haif of the IOBs along either the left or right edge of the device, as shown in Figure 39. They can only access the top and bot- tom IOBs via the CLB global lines. 7 [ion <<) v6 | CLB 9 B | , | CLB CLB o B | | ran a 2 DI 108 | | 108 I<] 5 3 4 xera7 Figure 39: Top and Bottom BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant (GCK8 is shown. GCK3, GCK4 and GCK7 are similar.) 4-44 July 30, 1996 (Version 1.03)$< XILINX The Global Early buffers can be driven by either semi-ded- icated pads or internal logic. They share pads with the Glo- bal Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOCST attribute or prop- erty to direct that a BUFGE be placed in one of the two Glo- bal Early buffers on the top edge of the device, or a LOC=TR to indicate the Giobal Early buffer on the top edge of the device, on the right. FastCLk Buffers The fastest way to bring a clock into the XC4000EX device is through a FastCLK buffer. Two FastCLK buffers are present on the left edge, and two on the right edge, of the XC4000EX die. There are no FastCLk buffers on the top or bottom edges. One purpose of the FastCLK buffers is to create a very fast pin-to-pin path by using the 1OB 2-input function generator in conjunction with the FastCLK. Drive the F input of the JOB function generator with the FastCLK buffer output, as described in IOB Output Signals on page 27. Alternatively, a FastCLK buffer can be used to minimize the setup time of device inputs, if a positive hold time is accept- able. Use the FastCLK buffer to clock the Fast Capture latch, and a slower clock buffer to clock the standard |OB flip-flop or latch. Either the Global Early buffer or the Global Low-Skew buffer can be used for the second storage ele- ment, but whichever one is used should be the same clock as the related internal logic. Since the FastCLK pads are different from the Global Early and Global Low-Skew pads, care must be taken to ensure that skew external to the device does not create internal timing difficulties. The FastCLK buffers can also be used to provide a fast Clock-to-Out on device output pins. However, a fast clock in the output flip-flop IOB must be taken into consideration when calculating the internal clock speed for the design. 108 | | 10B CLB CLB <4 2b CLB CLB 3 | 10B | f 1OB | X6745, Figure 40: Each BUFFCLK Can Drive Any or All Clock Inputs in Same Half-Edge (FCLK1 is shown. FCLK2, FCLK3 and FCLK4 are similar.) The FastCLK buffers are limited to accessing |OBs on one- half of the die edge only, as shown in Figure 40 and Figure 36 on page 42. They can each drive two of the four vertical lines accessing the IOBs on the left edge of the device, or two of the eight vertical lines accessing the |OBs on the right edge of the device. They can only access the CLB array through single- and double-length lines. The FastCLK buffers must be driven by the semi-dedicatec 1OBs. They are not accessible from internal nets. Other than the FastCLK feature, these IOBs are identical to all other IOBs. To use a FastCLK buffer, place a BUFFCLK element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=LB attribute or prop- erty to direct that a BUFFCLK be placed on the left edge of the device at the bottom, or use LOC=L to indicate either of the buffers on the left edge. The input to the BUFFCLK symbol! must be driven by a input pad symbol, such as IPAD, or by an input flip-flop or latch, such as INFF, ILD, ILDFFDX, or ILDFLDX. July 30, 1996 (Version 1.03) 4-45XC4000 Series Field Programmable Gate Arrays Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring sur- rounding the logic array provides power to the i/O drivers, as shown in Figure 41. An independent matrix of Vee and Ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 F capacitor connected near the Vcc and Ground pins of the package will provide adequate decou- pling. Output buffers capable of driving/sinking the specified 12 mA (XC4000E) or 24 mA (XC4000EX) loads under speci- fied worst-case conditions may be capable of driving/sink- ing up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical. GND $ _-- Ground and pp pee pee eee bee tee be Vee Ring for r r r qT r t t r VO Drivers mfan ben foo $o- $e $e- t= - I 1 i 1 1 1 { t 1 Vec [S ] Voc LC soi Power Grid X5422 Figure 41: XC4000-Series Power Distribution Pin Descriptions There are three types of pins in the XC4000-Series devices: Permanently dedicated pins User I/O pins that can have special functions e Unrestricted user-programmable I/O pins. Before and during configuration, all outputs not used for the configuration process are 3-stated with a 50 kQ - 100 kQ pull-up resistor. After configuration, if an IOB is unused it is configured as an input with a 50 kQ - 100 kQ pull-up resistor. XC4000-Series devices have no dedicated Reset input. Any user I/O can be configured to drive the Global Set/ Reset net, GSR. See Global Set/Reset on page 13 for more information on GSR. XC4000-Series devices have no Powerdown control input, as the XC3000 and XC2000 families do. The XC3000/ XC2000 Powerdown control also 3-stated all of the device I/ O pins. For XC4000-Series devices, use the global 3-state net, GTS, instead. This net 3-states all outputs, but does not place the device in low-power mode. See IOB Output Signals on page 27 for more information on GTS. Device pins for XC4000-Series devices are described in Table 18. Pin functions during configuration for each of the seven configuration modes are summarized in Tabie 24 on page 78, in the Configuration Timing section. 4-46 July 30, 1996 (Version 1.03)$= XILINX Table 18: Pin Descriptions Pin Name vO : During | Contig. vO After | Config. Pin Description Permanently Dedicated Pins vcc Eight or more (depending on package) connections to the nominal +5 V supply voltage I '(+3.3 V for low-voltage devices). All must be connected, and each must be decoupled -with a 0.01 - 0.1 uF capacitor to Ground. GND :Eight or more (depending on package type) connections to Ground. All must be con- nected. CCLK lorO During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn- chronous Peripheral mode, but is an input in Stave mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and I can be selected as the Readback Clock. There is no CCLK High time restriction on XC4000-Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 65 for an explanation of this exception. DONE vO DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on 0 DONE can be configured to delay the global logic initialization and the enabling of out- puts. The optional pull-up resistor is selected as an option in MakeBits, the XACTstep pro- gram that creates the configuration bitstream. The resistor is included by default. _ PROGRAM PROGRAM is an active Low input that forces the FPGA to clear its configuration mem- ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. User I/O Pins That Can Have Special Functions RDY/BUSY During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in Asyn- VO _ |chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable |/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the AO-A17 outputs (AO - A21 for XC4000EX) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is useful for clocked PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. vO MO, M1, M2 As Mode inputs, these pins are sampled after INIT goes High to determine the configu- ration mode to be used. After configuration, MO and M2 can be used as inputs, and M1 can be used as a 3-state output. These three pins have no associated input or output registers. (MO), | During configuration, these pins have weak pull-up resistors. For the most popular con- 1), |figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three 2) |mode inputs can be individually configured with or without weak pull-up or pull-down re- sistors. A pull-down resistor value of 4.7 kQ is recommended. These pins can only be used as inputs or outputs when calied out by special schematic definitions. To use these pins, place the library components MDO, MD1, and MD2 in- stead of the usual pad symbols. Input or output buffers must still be used. July 30, 1996 (Version 1.03) 4-47XC4000 Series Field Programmable Gate Arrays Table 18: Pin Descriptions (Continued) i vo | vO TN During | After Pin Name _ | Config. | Config. Pin Description If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. TDO . Oo O This pin can be user output only when called out by special schematic definitions. To | use this pin, place the library component TDO instead of the usual pad symbol. An out: put buffer must still be used. lf boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select | ' inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. | | TDI, TCK, | ue if the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-. TMS ited once configuration is completed, and these pins become user-programmable 1/O. | (STAG) In this case, they must be cailed out by special schematic definitions. To use these pins, , place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-| put or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. Itis available as HDC 0 VO acontrol output indicating that configuration is not yet completed. After configuration, | HDC is a user-programmable 1/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. Itis available as a LDC QO | WO jcontrol output indicating that configuration is not yet completed. After configuration, | |LDC is a user-programmable V/O pin. | | | Before and during configuration, INIT is a : bidirectional sic signal. . A1kQ- 10 kQ external ; pull-up resistor is recommended. | As an active-Low open-drain output, INIT is held Low during the power stabilization and , | INIT | vO V0 internal clearing of the configuration memory. As an active-Low input, it can be used | | i to hold the FPGA in the internal WAIT state before the start of configuration. Master . | mode devices stay in a WAIT state an additional 30 to 300 ps after INIT has gone High. | During configuration, a Low on this output indicates that a configuration data error has | i occurred. After the I/O go active, INIT isa user-programmabte I/O pin. + _ | | {Four Primary Global inputs each drive a dedicated internal global net with short delay | PGCK1- | jand minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-| | | PGCK4 Weak lor VO grammable I/O. (XC4000E | Pull-up | The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol only) : connected directly to the input of a BUFGP symbol is automatically placed on one of : these pins. _ Four Secondary Global inputs each drive a dedicated internal global net with short i delay | SGCKt1 - and minimal skew. These internal global nets can also be driven from internal logic. If | | SGCK4 | Weak bor iO not used to drive a global net, any of these pins is a user-programmablie I/O pin. | (XC4000E = Pull-up The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff- | only) lers. Any input pad symboi connected directly to the input of a BUFGS symbol is auto- | : | matically placed on one of these pins. | | Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-| GCK1 - 'bal Early buffer. Each pair of global buffers can also be driven from internal logic, but | GCK8 Weak Lor lO must share an input signal. If not used to drive a global buffer, any of these pins is a | (XC4000EX ; Pull-up user-programmabie i/O. Ty Four FCLK inputs ca can each drive a FastCLK buffer. The FastCLK buffers cannot be | driven from internal logic. If not used to drive a global buffer, any of these pins is a user- | lor /O jprogrammable /O. |Any input pad symbol connected rectly to the input of a BUFFCLK symbol is automat- FCLK1 - FCLK4 | Weak (XC4000EX | Pull-up | only) | | | only) | | Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol | | | | 4-48 July 30, 1996 (Version 1.03)$= XILINX Table 18: Pin Descriptions (Continued) Pin Name vo During Config. vO After Config. Pin Description CSO, CS1, WS, RS vO These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe - (WS) loads the data present on the DO - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy and drives DO - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. AQ - A17 vO During Master Parallel configuration, these 18 output pins address the configuration EPROM. After configuration, they are user-programmable I/O pins. A18 - A21 (XC4000EX only) | VO During Master Parallel configuration with an XC4000EX master, these 4 output pins add 4 more bits to address the configuration EPROM. After configuration, they are user-pro- grammable I/O pins. DO - D7 vO During Master Parallel and Peripheral configuration, these eight input pins receive con- figuration data. After configuratio;, they are user-programmable I/O pins. DIN vO During Slave Serial or Master Serial configuration, DIN is the serial configuration data input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the DO input. After configuration, DIN is a user-programmable 1/O pin. DOUT VO During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DIN input. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Prog rammable I/O Pins Vo Weak Pull-up vO These pins can be configured to be input and/or output after configuration is completed. | Before configuration is completed, these pins have an internal high-value pull-up resis-. tor (50 kQ - 100 kQ) that defines the logic level as High. July 30, 1996 (Version 1.03) 4-49XC4000 Series Field Programmable Gate Arrays Boundary Scan The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Stan- dard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for \/O and internat logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compati- ble devices may be serial daisy-chained together, con- nected in parailel, or a combination of the two. The XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan configuration option is selected, three normal user I/O pins become ded- icated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this sec- tion. By exercising these input signals, the user can serially ioad commands and data into these devices to control the driv- ing of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also discussed in the Xilinx application note XAPP 017: Boundary Scan in XC4000 Devices." Figure 42 shows a_ simplified block diagram of the XC4000E Input/Output Block with boundary scan imple- mented. XC4Q0Q0EX boundary scan logic is identical. Figure 43 on page 52 is a diagram of the XC4000-Series boundary scan logic. It includes three bits of Data Register per IOB, the [EEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. XC4000-Series devices can also be configured through the boundary scan logic. See Configuration Through the Boundary Scan Pins on page 64. Data Registers The primary data register is the boundary scan register. For each |OB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-lOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures ail In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three bound- ary scan bits are special-purpose Xilinx test signals. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instruc- tions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to imple- ment with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE). Instruction Set The XC4000-Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 19. Table 19: Boundary Scan Instructions ' Instruction | Test : | VO Data 2 1 10 Selected TOO SOUCE coitce 0 OO | EXTEST DR DR Oo 0 1 | SAMPLE/ DR Pin/Logic PRELOAD o!/ 1/0 USER 1 BSCAN. | User Logic TDO1 o 1/4 USER 2 BSCAN. | User Logic TDOZ P4560! 0 READBACK | Readback | Pir/Logic Data 1 0 | 1 CONFIGURE, DOUT Disabled 1; 1 0 Reserved _ 1 1 71 | BYPASS Bypass . Register ; 4-50 July 30, 1996 (Version 1.03)$= XILINX EXTEST TSINV |M TSOE Boundary " - capture 3-State TS Scan TS - update OUTPUT INVERT OUTPUT M Quput Data O M | INVERT Quput Clock OK Q - capture Boundary | Q - capture Scan Clock Enable 0 - update c | 1+ capture Boundary d Scan } ' input Data 111 L1- update sd bo @ EC input Data 2 12 M | INVERT Q FLIP-FLOP/LATCH input Clock JK INPUT GLOBAL S/R x5792 Figure 42: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown). XC4000EX Boundary Scan Logic is Identical. July 30, 1996 (Version 1.03) 4-51XC4000 Series Field Programmable Gate Arrays DATA IN | | | { ! _ tOB.Q ~e ee Sp 1 + i | 1OB.T TERT ae need coo ooo! | ) + J] | Gog | 7 ! Ty -| 108 | 108 | 108 | 108 | 108 r | | t > TH tos oe HO (CH 1cB 106 Hi] CH ice woe HOD is 4 108.1 ee i {10s oe HT] | tee p oo : i f \ oD 68 o aby | - me ! J |... 7 | CH) toa Ji. . i io : : : C+ '08 fr - p| LE [ : jo : ee ee | : \ > _ _ [> Lo CH ws BYPASS _ oe HI |} 08.0 ' toe REGISTER | : | a i LC . 108.T * - : - | Te) oS ~-l 5 INSTRUCTION REGISTER [7 vu 1 itp a Lo # af . 4 | ee t | mn *| p LE | ;[M ro | | u INSTRUCTION REGISTER ge BL peed wal T ~-fSe==-/|--------- | L BYPASS | : ! oof i CH top REGISTER op KY : 4D Q +~]D Q 7 i , oo i : { . f : a PD eT LeE 1 | OH tcp 0B 13 m : | | | CH op con Ey | i CH 108 op FO cH 108 op HLT TH 108 1oB {7 : a eee : i neta pe ee | SH 108 op Fy | 108.0 ; | | ' | i : DATAOUT UPDATE EXTEST ' __| 108 | 108 | 108 | io8 | top 4 | oe CLOCK DATA i ( oo fo 5 Figure 43: XC4000-Series Boundary Scan Logic 4-52 July 30, 1996 (Version 1.03)Bit Sequence The bit sequence within each OB is: In, Out, 3-State. The input-only MO and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the output- only M1 pin contributes all three bits. The first two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal sig- nals. The final bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 44. The device-specific pinout tables for the XC4000 Series include the boundary scan locations for each IOB pin. BSDL (Boundary Scan Description Language) files for XC4000-Series devices are available on the Xilinx BBS. Including Boundary Scan in a Schematic If boundary scan is only to be used during configuration, no special schematic elements need be included in the sche- matic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user func- tions after configuration. To indicate that boundary scan remain enabled after config- uration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 45. Bit 0 ( TDO end) TDO.T Bit 4 TbOo.a Bit 2 Top-edge IOBs (Right to Left) Left-edge |OBs (Top to Bottom) ae ee MD1.T MD1.0 MD1.1 MDO.t MD2.) | Bottom-edge IOBs (Left to Right) | Right-edge |OBs (Bottom to Top) (TDI end) B SCANT.UPD X6075 Figure 44: Boundary Scan Bit Sequence $= XILINX Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TD! can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDi and TCK. Avoiding Inadvertent Boundary Scan Activation lf TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant dur- ing configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process. To prevent activation of boundary scan during configura- tion, do either of the following: * TMS: Tie High to put the Test Access Port controller in a benign RESET state * TCK: Tie High or Lowdon't toggle this clock input. For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017.001, Boundary Scan in XC4000E Devices. Optional To User Logic IBUF BSCAN TDI TO! TOO TDO [1MS>_ s DRCK }~ [TcK>T tc {DLE } To User From To01 SELt f- Logic User Logic I to02 SEL2 kK X2678 Figure 45: Boundary Scan Schematic Example July 30, 1996 (Version 1.03) 4-53XC4000 Series Field Programmable Gate Arrays Configuration Configuration is the process of loading design-specific pro- gramming data into one or more FPGAs to define the func- tional operation of the internal blocks and _ their interconnections. This is somewhat like loading the com- mand registers of a programmable peripheral chip. XC4000-Series devices use several hundred bits of config- uration data per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multi- plexer input, or an interconnect pass transistor. The XACT- step development system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format. Special Purpose Pins Three configuration mode pins (M2, M1, MO) are sampled prior to configuration to determine the configuration mode. After configuration, these pins can be used as auxiliary connections. M2 and MO can be used as inputs, and M1 can be used as an output. The XACTsfep development system does not use these resources unless they are explicitly specified in the design entry. This is done by plac- ing a special pad symbol called MD2, MD1, or MDO instead of the input or output pad symbol. In XC4000-Series devices, the mode pins have weak pull- up resistors during configuration. With ail three mode pins High, Slave Serial mode is selected, which is the most pop- ular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left uncon- nected. (Note, however, that the internal pull-up resistor value can be as high as 100 kQ.) After configuration, these pins can individually have weak pull-up or pull-down resis- tors, as specified in the design. A pull-down resistor value of 4.7 kQ is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of MO/RT, M1/RD is desired. Configuration Modes XC4000E devices have six configuration modes. XC4000EX devices have the same six modes, plus an additional configuration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and MO inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisy-chained devices. The seventh mode, called Express mode, is an additional slave mode that allows high-speed parallel configuration of the high-capacity XC4000EX devices. The coding for mode selection is shown in Table 20. Table 20: Configuration Modes Mode | M2] M1 MO| CCLK | Data Master Serial 0 | 0 0 | output | Bit-Serial Slave Serial 1/1 4 | input | Bit-Serial Master ~=s1~<0~~<0- output. Byte-Wide, | iParallet Up increment | ot from 00000 | Master 1 | 4 | 0 output | Byte-Wide, | Parallel Down | decrement |! from 3FFFF : Peripheral =O 1 1 input | Byte-Wide (Synchronous* | [Peripheral 1. O 1 | output | Byte-Wide | | Asynchronous Pt | Express | 0 1 0 input | Byte-Wide \(XC4000EX | | oy) _ | _ Reserved Oo oO | 1 = ne sn ee en re Note: * Peripheral Synchronous can be considered byte- wide Slave Parallel A detailed description of each configuration mode, with tim- ing information, is included later in this data sheet. During configuration, some of the I/O pins are used temporarily for the configuration process. All pins used during configura- tion are shown in Table 24 on page 78. Master Modes The three Master modes use an internal oscillator to gener- ate a Configuration Clock (CCLK) for driving potential slave devices. They also generate address and timing for exter- nal PROM(s) containing the configuration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, for compatibility with dif- ferent microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the configura- tion data in serial form from a Xilinx serial-configuration PROM. CCLK speed is selectable as either 1 MHz (default) or 8 MHz {up to 10% lower for low-voltage devices). Configura- tion always starts at the default slow frequency, then can switch to the higher frequency during the first frame. Fre- quency tolerance is -50% to +25%. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake sig- nal. In Asynchronous Peripheral mode, the internal oscilla- tor generates a CCLK burst signal that serializes the byte- wide data. CCLK can also drive slave devices. In the syn- 4-54 July 30, 1996 (Version 1.03)chronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode In Slave Serial mode, the FPGA receives serial configura- tion data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously. Serial Daisy Chain Multiple devices with different configurations can be con- nected together in a daisy chain, and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 55 on page 68. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the tength count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycies after the last configura- tion bit is received. Figure 49 on page 61 shows the start- up timing for an XC4000-Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The MakePROM program must be used to combine the bitstreams for a daisy- chained configuration. Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, and XC4000 Series use a compatible bitstream format and can, there- fore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. The lead device must belong to the highest family in the chain. If the chain contains XC4000-Series devices, the master nor- mally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 49 on page 61. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 49. The master device then generates additional $2 XILINX CCLK pulses until it reaches its finish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really finish its configuration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC4000- Series device, not reaching F means that readback cannot be initiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the finish point F is reached. Timing is con- trolled using MakeBits options. XC3000 Master with an XC4000-Series Slave Some designers want to use an inexpensive lead device in peripheral mode and have the more precious I/O pins of the XC-4000-Series devices all available for user I/O. Figure 46 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be config- ured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC4000-Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse. Express Mode (XC4000EX only) Express mode is similar to Slave Serial mode, except the data is presented in parallel format, and is clocked into the target device a byte at a time rather than a bit at a time. The data is loaded in parallel into eight different columns: it is not internally serialized. Eight bits of configuration data are loaded with every CCLK cycle, therefore this configuration sr Output Connected Reset to CCLK 0 0 Active Low Qutout 1 Active High Output 1 1 + O00 etc | x5223 Figure 46: CCLK Generation for XC3000 Master Driving an XC4000-Series Slave July 30, 1996 (Version 1.03) 4-55XC4000 Series Field Programmable Gate Arrays mode runs at eight times the data rate of the other six modes. A length count is not used in Express mode. Express mode must be specified as an option to the Make- Bits program, which generates the bitstream. The Express mode bitstream is not compatible with the other six config- uration modes. Multiple slave devices with identical configurations can be wired with parallel DO-D7 inputs. in this way, multiple devices can be configured simultaneously. Pseudo Daisy Chain Muitiple devices with different configurations can be con- nected together in a pseudo daisy chain, provided that all of the devices are in Express mode. A single combined bit- stream is used to configure the chain of Express mode devices, but the input data bus must drive D0O-D7 of each device. Tie High the CS1 pin of the first device to be con- figured. Connect the DOUT pin of each FPGA to the CS1 pin of the next device in the chain. The DO-D7 inputs are wired to each device in parallel. The DONE pins are wired together, with one or more internal DONE pull-ups acti- vated. Alternatively, a 4.7 kQ external resistor can be used, if desired. (See Figure 63 on page 76.) The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All XC4000EX devices in Express mode are synchronized to the DONE pin. User I/O for each device become active after the DONE pin for that device goes High. (The exact timing is determined by MakeBits options.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together prevents all devices in the chain from going High until the last device in the chain has completed its configuration cycle. Because only XC4000EX and XC5200 devices support Express mode, only these devices can be used to form an Express mode daisy chain. XC5200 devices used in a combined daisy chain with XC4000EX devices should be configured as synchronized to DONE (MakeBits option CCLK_SYNC or UCLK_SYNC), and their DONE pins wired together with those of the XC4000EX devices. Setting CCLK Frequency For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges trom 0.5 MHz to 1.25 MHz (up to 10% lower for low- voltage devices). In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz (up to 10% lower for low-voltage devices). The frequency is selected by an option when run- ning MakeBits, the bitstream generation software tool. If an XC4000-Series Master is driving an XC3000- or XC2000- family slave, slow CCLK mode must be used. Slow mode is the default. Data Stream Format The data stream (bitstream) format is identical for all con- figuration modes, with the exception of Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Addition- ally, CRC error checking is not supported in Express mode. The data stream formats are shown in Table 21. Express mode data is shown with DO at the left and D7 at the right. For all other modes, bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bit in each byte assigned to DO. The configuration data stream begins with a siring of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones (or 24 fill bits, in Express mode). This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 22 and Table 23). Each frame begins with a start field and ends with an error check. In all modes except Express mode, a postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to pro- vide four clocks for the startup sequence at the end of con- figuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bit- streams created by the Xilinx software. Table 21: XC4000-Series Data Stream Formats Data Type Express Mode All Other (D0-D7) Modes (D0...) [Fill Byte 11111711b 41111111b Preamble Code 11110010b 0010b Length Count FFFFFFh COUNT(23:0) Fill Bits ~ 1141b | Start Field 11010010b Ob Data Frame DATA(n-1:0) DATA(n-1:0) CRC or Constant 11010010b xxxx (CRC) Fieid Check or 0110b [Extend Write Cycle [FFFFFFFFFFh | -Up Bytes LEGEND: Unshaded Once per bitstream Light Once per data frame 4-56 July 30, 1996 (Version 1.03)Table 22: XC4000E Program Data $= XILINX [ Device XC4003E |XC4005E/L; XC4006E | XC4008E | XC4010E/L|XC4013E/L: XC4020E | XC4025E | Max Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000 CLBs 100 196 256 324 400 576 784 1,024 (Row x Col.) (10 x10) (14x 14) (16 x 16) (18 x 18) (20 x 20) (24 x 24) (28 x 28) (32 x 32) 1OBs 80 112 128 144 160 192 224 256 Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560 Horizontal 20 28 32 36 40 48 56 64 Longlines TBUFs per 12 16 18 20 22 26 30 34 Longline Bits per Frame 126 166 186 206 226 266 306 346 Frames 428 572 644 716 788 932 1,076 1,220 Program Data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128 PROM Size 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 i(bits) Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header. The MakeBits software creates the configuration bitstream. in Express mode, only non-CRC error checking is sup- ported. In all other modes, MakeBits allows a selection of CRC or non-CRC error checking. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, MakeBits calculates a run- ning CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data load- ing and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vcc. Cyclic Redundancy Check (CRC) for Configuration and Readback The Cyclic Redundancy Check is a method of error detec- tion in data transmission applications. Generally, the trans- mitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical caiculation on the bitstream and com- pares the result with the received checksum. Each data frame of the configuration bitstream has four error bits at the end, as shown in Table 21. If a frame data error is detected during the loading of the FPGA, the con- figuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 47. The checksum consists of the 11 most signif- icant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A compari- son to a previous checksum is meaningful only if the read- back data is independent of the current device state. CLB outputs should not be included (Read Capture MakeBits option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. July 30, 1996 (Version 1.03)XC4000 Series Field Programmable Gate Arrays Table 23: XC4000EX Program Data Device XC402BEWXL | XC4036EX/KL - XC4044EX/XL | XC4052XL XC4062XL Max Logic Gates 28,000 36,000 44,000 52,000 62,000 CLBs 1,024 1,296 1,600 1,936 2,304 (Row x Col.) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) IOBs 256 288 320 352 384 Flip-Flops 2,560 3,168 3,840 4576 5,376 Horizontal Longlines 192 216 240 264 288 TBUFs per Longline 34 ~ 38 42 46 50 Bits per Frame 421 469 517 565 613 Frames 1587 1775 ~ 1963 2151 2,339 Program Data 668,127 | 832,483 1,014,879 1,215,323 1,433,807 PROM Size (bits) 668,167 832,523 1,014,919 1,215,363 1,433,847 Notes: 1. Bits per Frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits Number of Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header. 3. Express mode bitfiles are slightly larger (see Table 21). X2 ora] ) Has ester sls roa X15 | | { SERIAL DATAIN 1 | I Polynomial: X16 + X15 + X24 1 t -tifatis 15/14/13[12/11] 10/9 [8] 7] 6] 5 LAST DATA FRAME +| START BIT | ~ CRC - CHECKSUM > Readback Data Stream x1788 Figure 47: Circuit for Generating CRC-16 4-58 July 30, 1996 (Version 1.03)$= XILINX Configuration Sequence There are four major steps in the XC4000-Series power-up configuration sequence. * Configuration Memory Clear * Initialization * Configuration Start-Up The full process is illustrated in Figure 48. Configuration Memory Clear When power is first applied or is reapplied to an FPGA, an internal circuit forces initialization of the configuration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of configu- ration bits, a time delay is started. This time delay is nomi- nally 16 ms, and up to 10% longer in the low-voltage devices. The delay is four times as long when in Master Modes (MO Low), to allow ampie time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as rec- ommended, the longest delay takes precedence. There- fore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconfiguring an FPGA by pulsing the PROGRAM pin Low. During this time delay, or as long as the PROGRAM input is asserted, the configuration logic is held in a Config- uration Memory Clear state. The configuration-memory frames are consecutively initialized, using the internal oscil- lator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the configuration frames and then tests the INIT input. Initialization During initialization and configuration, user pins HDC, LDC, INIT and DONE provide status outputs for the system inter- face. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the final initializa- tion pass through the frame addresses. There is a deliber- ate delay of 50 to 250 us (up to 10% longer for low-voltage devices) before a Master-made device recognizes an inac- tive INIT. Two internal clocks after the INIT pin is recognized as High, the FPGA samples the three mode lines to deter- mine the configuration mode. The appropriate interface lines become active and the configuration preamble and data can be loaded. Boundary Scan Instructions Availabie: Yes rt | Tast MO Generate es | One Time-Out Pulse PROGRAM i of 16 or 64 ms = Low | | | Keep Clearing | Configuration Memory | ' | | EXTEST ! SAMPLE/PRELOAD Completely Clear | BYPASS Configuration Memory ~1.3 ps per Frame CONFIGURE" Once More (* if PROGRAM = High) Master Waits 50 to 250 us i Before Sampling Mode Lines | Sample Mode Lines Master CCLK Goes Active H rere Load One Configuration Oata Frame LDE Output = L, HDC Output SAMPLE/PRELOAD BYPASS Pass Configuration Data to DOUT CCLK Count Equals Length Count Stan-Up Sequence ' BE + g EXTEST Operational 3 SAMPLE PRELOAD Q BYPASS 7 USER 1 H Boundary Scan USER 2 is Selected CONFIGURE | READBACK X8076 Figure 48: Power-up Configuration Sequence July 30, 1996 (Version 1.03) 4-59XC4000 Series Field Programmable Gate Arrays Configuration The 0010 preamble code, included for all modes except Express mode, indicates that the following 24 bits repre- sent the length count. The length count is the total number of configuration clocks needed to load the complete config- uration data. (Four additional configuration clocks are required to complete the configuration process, as dis- cussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. In Express mode, the length count bits are ignored, and DOUT is held Low, to disable the next device in the pseudo daisy chain. A specific configuration bit, early in the first frame of a mas- ter device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configu- ration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configu- ration data bits and a frame error field. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all configura- tion frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. in Express mode, when the first device is fully programmed, DOUT goes High to enable the next device in the chain. Delaying Configuration After Power-Up There are two methods of delaying configuration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 48 on page 59.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply tise time is excessive or poorly defined. As long as PRO- GRAM is Low, the FPGA keeps clearing its configuration memory. When PROGRAM goes High, the configuration memory is cleared one more time, followed by the begin- ning of configuration, provided the INIT input is not exter- nally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The XC4000-Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration causes the FPGA to wait after completing the configuration memory clear operation. When INIT is no longer held Low exter- nally, the device determines its configuration mode by cap- turing its mode pins, and is ready to start the configuration process. A master device waits up to an additional 250 us to make sure that any slaves in the optional daisy chain have seen that INIT is High. Start-Up Start-up is the transition from the configuration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial configuration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the configuration sig- nals, and that the internal flip-flops are released from the global Reset or Set at the right time. Figure 49 describes start-up timing for the three Xilinx fam- ilies in detail. Express mode configuration always uses either CCLK_SYNC or UCLK_SYNC timing, the other con- figuration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a fixed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some flexibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the /O become active. The XC4000 Series offers additional flexibility. The three events DONE going High, the internal Set/Reset being de-activated, and the user I/O going active can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of soft- ware options in MakeBits, the bitstream generation soft- ware. The default option, and the most practical one, is for DONE to go High first, disconnecting the configuration data source and avoiding any contention when the /Os become active one clock lat2r. Reset/Set is then released another clock period later .. make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 49, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. 4-60 July 30, 1996 (Version 1.03)$2 XILINX Mi , Length Count Match CCLK Period CCLK XC2000 F = Finished, no more configuration clocks needed Daisy-chain lead device XC3000 must have latest F Heavy lines describe default timing XC4000E/EX CCLK_NOSYNC XC4000E/EX CCLK_SYNC XC4000E/EX UCLK_NOSYNC XC4000E/EX UCLK_SYNC Di Diet Synchronization * ; Uncertainty -<_| UCLK Period X6700 Figure 49: Start-up Timing July 30, 1996 (Version 1.03) 4-61XC4000 Series Field Programmable Gate Arrays The XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a configuration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a com- mon user clock, or to guarantee that all devices are suc- cessfully configured before any I/Os go active. If either of these two options is selected, and no user clock is specified in the design or attached to the device, the chip could reach a point where the configuration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bit- stream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the configuration memory is full, and the total number of configuration clocks received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a flip-flop QO, shown in Figure 50. QO is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. * The release of the open-drain DONE output The change of configuration-reiated pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called Start-up Timing Synchronous to Done In and is selected by the CCLK_SYNC and UCLK_SYNC MakeBits options. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by the CCLK_NOSYNC and UCLK_NOSYNC MakeBits options. As a configuration option, the start-up control register beyond QO can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK If CCLK is used to drive the start-up, QO through Q3 pro- vide the timing. Heavy lines in Figure 49 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options. Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relation- ship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence. DONE Goes High to Signal End of Configuration In all configuration modes except Express mode, XC4000- Series devices read the expected length count from the bit- stream and store it in an internal register. The length count varies according to the number of devices and the compo- sition of the daisy chain. Each device also counts the num- ber of CCLKs during configuration. Two conditions have to be met in order for the DONE pin to go high: e the chip's internal memory must be full, and * the configuration length count must be met, exactly. This is important because the counter that determines when the length count is met begins with the very first CCLK, not the first one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the first CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of configuration, the configuration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] which is sometimes interpreted as the device not configur- ing at all. If it is not possible to have the data ready at the time of the first CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. The XACT User Guide includes detailed information about man- ually altering the fength count. In Express mode, there is no length count. The DONE pin for each device goes High when the device has received its quota of configuration data. Wiring the DONE pins of sev- eral devices together delays start-up of all devices until ail are fully configured. 4-62 July 30, 1996 (Version 1.03)$2 XILINX aa ayaa STARTUP ae DONE iN * iOBs OPERATIONAL PER CONFIGURATION * f>e> GLOBAL SET/RESET OF ! ALL CL ANDO 108 FLIP-FLOP i GSR ENABLE GSA INVERT STARTUP. GSR CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC SEE STARTUP.GTS_-_LIBRARIES GUIDE) | GTS INVERT r GTS ENABLE 0 tds {} GLOBAL 3-STATE OF ALL 108s aos <4 = | * > @ DONE FINISHED " Lf? | T__ ENABLES BOUNDARY 0 __ 0 SCAN, READBACK AND CONTROLS THE OSCILLATOR Q0 Ot Ge a3 a4 | FULL | LENGTH COUNT =D-~ s 9 5 8 5 a da dD | pool > 1 posi > 1K pod SK pemd > dS K | | 7 , ! CLEAR MEMORY e L I e i CCLK STARTUP.CLK USEA NET E *ER-eN 9 Figure 50: Start-up Logic Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by MakeBits, the bitstream generation software. Release of User I/O After DONE Goes High By default, the user 1/O are released one CCLK cycie after the DONE pin goes High. if CCLK is not clocked after DONE goes High, the outputs remain in their initial state 3-stated, with a 50 kQ - 100 kQ pull-up. The delay from DONE High to active user 1/O is controlled by a MakeBits option. % ~CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS" X1828 Release of Global Set/Reset After DONE Goes High By default, Global Set/Reset (GSR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all flip-flops are held in their initial set or reset state. The delay from DONE High to GSR inactive is controlled by a MakeBits option. Configuration Complete After DONE Goes High Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 49 on page 61. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used. July 30, 1996 (Version 1.03) 4-63XC4000 Series Field Programmable Gate Arrays Configuration Through the Boundary Scan Pins XC4000-Series devices can be configured through the boundary scan pins. The basic procedure is as follows: * Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Hoiding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after configuration if a resistor is used to hoid INIT Low. * Issue the CONFIG command to the TMS input * Wait for INIT to go High Sequence the boundary scan Test Access Port to the SHIFT-DR state * Toggle TCK to clock data into TDI pin. The user must account for all TCK clock cycles after INIT goes High, as ail of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note XAPP017, Boundary Scan in XC4000 Devices This application note also applies to XC4000E and XC4000EX devices. IF UNCONNECTED, DEFAULT IS CCLK Readback The user can read back the content of configuration mem- ory and the level of certain internal nodes without intertfer- ing with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs and IOBs, as weil as the content of function genera- tors used as RAMs. Note that in XC4000-Series devices, configuration data is not inverted with respect to configuration as it is in XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble the original bitstream, because the bit- stream format differs from other modes. XC4000-Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback signals, place the READ- BACK library symbol and attach the appropriate pad sym- bois, as shown in Figure 51. After Readback has been initiated by a Low-to-High transi- tion on ROBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preambie, but starts with five dummy bits (all High) followed by the Start bit (Low) of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the fast frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low. CLK READ_TRIGGER NM,___TRIG MDO READ_DATA DATA > [MDI> READBACK OBUF IP IBUF Figure 51: Readback Schematic Example X1786, 4-64 July 30, 1996 (Version 1.03)Readback Options Readback options are: Read Capture, Read Abort, and Clock Select. They are set with MakeBits, the bitstream generation software. Read Capture When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB sig- nals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output flip-flops and the input signals 11 and 2. Note that while the bits describ- ing configuration (interconnect, function generators, and RAM content) are notinverted, the CLB and !OB output sig- nals are inverted. When the Read Capture option is not selected, the values of the capture bits reflect the configuration data originally written to those memory locations. lf the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table configuration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 52. Read Abort When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback opera- tion and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. The status of readback is indi- cated by the output control net RDBK.RIP RDBK.RIP is High whenever a readback is in progress. Clock Select CCLK is the default clock. However, the user can insert another clock on RDOBK.CLK. Readback contro! and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback contro! nets are simply not connected. RDBK.CLK is located in the lower right chip corner, as shown in Figure 52. $< XILINX vO vO PROGRAMMABLE 7 INTERCONNECT [ edo] | Os x1787 Figure 52: READBACK Symbol in Graphical Editor Violating the Maximum High and Low Time Specification for the Readback Clock The readback clock has a maximum High and Low time specification. In some cases, this specification cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mech- anism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the follow- ing frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the read- back data relative to the frame. The system must keep track of the position within a data frame, and disable inter- rupts before frame boundaries. Frame lengths and data formats are listed in Table 21, Table 22 and Table 23. Readback with the XChecker Cable The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verifi- cation. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-cir- cuit emulator. July 30, 1996 (Version 1.03) 4-65XC4000 Series Field Programmabie Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Master Serial Mode In Master Seriai made, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. NOTE: M2, M1, MO can be shorted to Ground if not used as //O In MakeBits, the user can specify Fast ConfigRate, which, starting several bits into the first frame, increases the CCLK frequency by a factor of eight. The value increases from between 0.5 and 1.25 MHz, to a value between 4 and 10 MHz. (For low-voltage devices, the frequency can be up to 10% lower.) Be sure that the serial PROM and slaves are fast enough to support this data rate. XC2000, XC3000/A, and XC3100A devices do not support the Fast ConfigRate option. The SPROM CE input can be driven from either [DC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-l/O, but CDC is then restricted to be a permanently High user output after con- figuration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Master Serial mode is selected by a <00Q> on the mode pins (M2, M1, MO). NOTE: M2, M1, MO can be shorted to Vcc if not used as /O (Low Reset Option Used} CT ty | Veco < = NIC g 47 KQ 47KQ 28. _ ark S 4? pene oe S 47 KR | wa Mi MO ii MO. va PWRDN, " Nic M2 " DouT >| oIN DOUT _ DIN DouT F XC4000E/EX Veo it onus MASTER i XC1700D_ as v XCAD00E/EX, XC3100A SERIAL | Ar ke Tv xcs5200 SLAVE coLK CLK vpp }-~ SLAVE DIN pat DATA | PROGRAM LBC cE CEO }- | PROGRAM de| RESET | DONE int > AESET/OE | [| Poe NT <> pe NT <> PROGRAM | Figure 53: Master Serial Mode Circuit Diagram 4-66 July 30, 1996 (Version 1.03)$< XILINX CCLK (Output) Serial Data in Serial DOUT n-3 x a \ ~ 1X x (Output) X3223 " Description Symbol Min Max Units | i DIN setu 1 T 20 ns | CCLK Po DSCK | i DIN hold 2 Toxps 0 ns | Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode. Figure 54: Master Serial Mode Programming Switching Characteristics July 30, 1996 (Version 1.03) 4-67XC4000 Series Field Programmable Gate Arrays Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal delay of 0.56 CCLK periods, which NOTE: M2, M1, MO can be shorted to Ground if not used as /O means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the sub- sequent rising CCLK edge. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, MO). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resis- tors during configuration. NOTE: M2, M1, MO can be shorted to Vcc if not used as /O J Vee om 47KQ = NC owe 4.7 Ker 47K 47K yg | cl 10 MO Mt MO M1 PWRDN ] u me ' NIC | M2 +] M2 PRON DOUT 2] DIN BOUT I | DIN DOUT F- XC4000E/EX vec wm] CCLK 9 cok MASTER ak XC1700D 45V XC4000E/EX, XC3100A SERIAL $ 7 Ke 7 xc5200 SLAVE couK wlcix VPP |_| SLAVE DIN DATA PROGRAM rot 3m CE CEO;/_ >| PROGRAM RESET RESETIOE [| DONE int ><> iNT iLow Reset Option Used) 4 | | fee | PROGRAM X6608 Figure 55: Slave Serial Mode Circuit Diagram 4-68 July 30, 1996 (Version 1.03)$< XILINX DIN Bit n Bitn+1 <~G) Toco > 2) Teen (5) Toor CCLK x \ + (4) Tec >'@ Teco (Output) Bitn-4 Bit n X5379 | Description _____ Symbo! Min Max Units DIN setup 1 | Too 20 ns DIN hold 2 Teep 0 i ns CCLK DIN to DOUT 3 Teco _ 30 ns High time 4 Tocu 45 ns Low time 5 Toor 45 ns Frequency Foc | 10 MHz Note: Configuration must be delayed untit the INIT pins of all daisy-chained FPGAs are High. Figure 56: Slave Serial Mode Programming Switching Characteristics July 30, 1996 (Version 1.03) 4-69XC4000 Series Field Programmable Gate Arrays Master Parallel Modes In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decre- menting the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble dataand all cata that over- flows the lead deviceon its DOUT pin. There is an inter- nal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (DO) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. HIGH TO DIN OF OPTIONAL or t 47KQ iow NIC DAISY-CHAINED FPGAS The PROM address pins can be incremented or decre- mented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (ail zeros) while oth- ers must boot from the top. The FPGA is flexible and can load its configuration bitstream from either end of the mem- ory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, MO). The EPROM addresses start at 00000 and increment. Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement. NC a an I i i t Mo M1 Me TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS ur CCLK > | | | NOTE:MO can be shorted bo to Ground if not used AITO Mo M1 M2 as 1/0. vec AIG DIN pout /} Aisp EPROM (8K x 8) CCLK 4.7KQ Al4 + TF (OR LARGER} __ USER CONTROL OF HIGHER init A13 - ORDER PROM ADDRESS BITS XC4000E/EX : . ate CAN BE USED TO SELECT BETWEEN SLAVE Ale 1 ALTERNATIVE CONFIGURATIONS AN AW ____ ' PROGRAM Ato A10 PROGRAM Ag Ag DONE mi 407 Ag AB | | |] 06 A7 Ay D7 | , [apes AG | AS D6 | Loa AS AS Ds | |] 03 A4 Ad D4 : [/] D2 A3 A3 D3 ~ : 77] 21 A2[- a2 pap i i /| BO At At oir! | | AO AO Do | DONE OE = | DATABUS 8 | | < PROGRAM Figure 57: Master Paraliel Mode Circuit Diagram X6697 4-70 July 30, 1996 (Version 1.03)$< XILINX A0-A17 (output) Address for Byte n a moor XXXXXXXXXXXKKK Address for Byte n+ 1 @ Trac Byte Xx @)tpae > __/ RCLK (output) | 7 CCLKs @)Taeo CCLK CCLK (output) DOUT (output) D6 07 Byte n-1 X6078 Description Symbol Min Max Units | Delay to Address valid 1 Trac 0 200 ns | RCLK Data setup time 2 Tore 60 ns | Data hold time 3 Tacp 0 ns Notes: 1. At power-up, Vcc must rise from 2.0 V to Vec min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. The first Data byte is ioaded and CCLK starts at the end of the first RCLK active cycle (rising edge). This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 58: Master Parallel Mode Programming Switching Characteristics July 30, 1996 (Version 1.03) 4-71XC4000 Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- tion data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth con- secutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance puillup prior to INIT going High. NOTE: The lead FPGA serializes the data and presents the pre- amble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK peri- ods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisy- chained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, MQ). M2 can be shorted to Ground if not used as I/O NIC 4.7 KO NIC |_| L | | | MO M1 M2 Mo M1 M2 CLOCK CCLK CCLK OPTIONAL 8 DAISY-CHAINED DATA BUS 2__+ Do.7 FPGAS DOUT DIN pout HK voc XC4000E/EX XC4000E/EX SYNCHRO- SLAVE Nous 4.7kO PERIPHERAL CONTROL T RDY/BUSY _ SIGNALS INIT DONE INIT DONE 4.7 kQ z PROGRAM+ PROGRAM PROGRAM Figure 59: Synchronous Peripheral Mode Circuit Diagram X5996 4-72 July 30, 1996 (Version 1.03)$< XILINX CCLK ; I 1 1 { | INIT - r BYTE ) F" )_ } ! ; BYTE 0 OUT: BYTE 1 OUT ' ON DOUT KoXtX2X3X4+Xs X86 XK? o xX 1 I | RDY/BUSY / \ / \ x6096 Description Symbol Min Max Units INIT (High) setup time Tic 5 us DO - D7 setup time Toc 60 ns DO - D7 hold time Top 0 ns CCLK c CCLK High time TocH 50 ns CCLK Low time Teer 60 ns CCLK Frequency Fee 8 MHz Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal. 4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded. Figure 60: Synchronous Peripheral Mode Programming Switching Characteristics July 30, 1996 (Version 1.03) 4-73XC4000 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CSO being Low and RS and CS1 being High to accept byte-wide data from a micro- processor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preambie data (and all data that overflows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake sig- nal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pull- up prior to INIT going High. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered. The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaran- teed to be longer than 10 CCLK periods. Status Read The logic AND condition of the CS0, CStand RS inputs puts the device status on the Data bus. D7 High indicates Ready * D7 Low indicates Busy * DO through D6 go unconditionally High It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the final byte transfer. If this transfer does not occur, the start-up sequence is not com- pleted ail the way to the finish (point F in Figure 49 on page 61). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by MakeBits and MakePROM, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data Sines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, MO). Mo M1 DATA a BUS +~. <4 DO-7 CCLK OPTIONAL DAISY-CHAINED PGAs DOUT DIN DOUT |- vec ADDRESS hs ADDRESS , | DECODE XC4000E/EX | sus) | Losic ASYNCHRO- XC4000E/EX ~ NOUS SLAVE PERIPHERAL 47 KR 4.7kQ | csi AS Ws ROY/BUSY SIGNALS iNT | CONTROL | DONE BEPROGRAM | ' PROGRAM INIT DONE PROGRAM 47kQ | I X6596 Figure 61: Asynchronous Peripheral Mode Circuit Diagram 4-74 July 30, 1996 (Version 1.03)$= XILINX Write ta LCA Read Status WS/CSO RS, cS1 CcLK ADY/BUSY BOUT x Previous Byte D6 x D7 x bo x or X ba X6097 Description Symbol Min Max Units Effective Write time 1 Toa 100 ns . (CSO, WS=Low; RS, CS1=High) Write DIN setup time 2 Toc 60 ns | DIN hold time 3 Tep 0 ns | RDY/BUSY delay after end of 4 Twrre 60 ns Write or Read RDY /RDY/BUSY active after beginning 7 60 ns : of Read | RDY/BUSY Low output (Note 4) 6 Tausy 2 9 CCLK | periods Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. Tausy indicates that the double-buffered paraliel-to-serial converter is not yet ready to receive new data. The shortest Taysy occurs when a byte is loaded into an empty parallel-to-serial converter. The longest Tgysy occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated unti! RDY/BUSY has been High for one CCLK period. Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics July 30, 1996 (Version 1.03) 4-75XC4000 Series Field Programmable Gate Arrays Express Mode (XC4000EX only) Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the con- figuration data shift registers. A CCLK frequency of 1 MHz is equivalent to a 8 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not support CRC error checking, but does sup- port constant-field error checking. In Express mode, an external signal drives the CCLK input of the FPGA device. The first byte of parailel configuration data must be available at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subse- quent data bytes are clocked in on each consecutive rising CCLK edge. Express mode is only supported by the XC4Q00EX and XC5200 families. It may not be used, therefore, when an XC4000EX or XC5200 device is daisy-chained with devices from other Xilinx families. If the first device is configured in Express mode, additional devices may be daisy-chained only if every device in the chain is also configured in Express mode. CCLK pins are tied together and DO-D7 pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or float- ing, since there is an internal pullup). Frame data is accepted only when CS1 is High and the devices configu- ration memory is not already full. The status pin DOUT is pulled Low two internal-oscillator cycles after INIT is recog- nized as High, and remains Low until the devices configu- ration memory is full. DOUT is then pulled High to signal the next device in the chain to accept the configuration data on the DO-D7 bus. The DONE pins of all devices in the chain should be tied together, with one or more active internal pull-ups. If a large number of devices are included in the chain, deacti- vate some of the internal pull-ups, since the Low-driving DONE pin of the last device in the chain must sink the cur- rent from ail pull-ups in the chain. The DONE pull-up is activated by default. It can be deactivated using a Make- Bits option. XC4000EX devices in Express mode are always synchro- nized to DONE. The device becomes active after DONE goes High. DONE is an open-drain output. With the DONE pins tied together, therefore, the external DONE signal stays low until all devices are configured, then all devices in the daisy chain become active simultaneously. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been configured. XC5200 devices in the chain should be configured as syn- chronized to DONE (MakeBits option CCLK_SYNC or UCLK_SYNC), and their DONE pins wired together with those of the XC4000EX devices. Express mode must be specified as an option to the Make- Bits program, which generates the bitstream. The Express mode bitstream is not compatible with the other six config- uration modes. Express mode is selected by a <010> on the mode pins (M2, M1, MO}. i i | | | MO M1 M2 | wT CS! BOUT patagus 2_4-_-_| pe-07 Vec T 4.7KQ S XC4000EX/ XC5200 INT | - es NIT DONE |) CCLK xee1! Figure 63: Express Mode Circuit Diagram NOTE: 1 M2, M1, MO car be shorted | b to Ground if not used as VO 4TKQ = 4 5 ae To Additional MO M1 M2 Optional i Daisy-Chaineo | Devices cst DOUT ,-______- | J | 8. x9! po-07 Optional Daisy-Chained XC4000EX/ XC5200 ate PROGRAM ~~ INIT DONE }-, i ! { i ' ccLK | i | | en we _ \ To Additional Optional J Daisy-Chained Devices 4-76 July 30, 1996 (Version 1.03)$< XILINX [ Description Symbol Min Max Units INIT (High) setup time Tic - us DO-D7setuptime Toc ns D0 - D7 hold time Top 0 ~ ns | CCLK - ! CCLK High time Tocu ns CCLK Low time Tec. | CCLK Frequency Foc CCLK Te _ 31 INIT o < Too @ @ Too "| DOUT -__ FPGA Filled Internal INIT ADY/BUSY csi Note: If not driven by the preceding DOUT, CS1 must remain High until the device is fully configured. Figure 64: Express Mode Programming Switching Characteristics X6710 July 30, 1996 (Version 1.03) 4-77XC4000 Series Field Programmabie Gate Arrays Table 24: Pin Functions During Configuration CONFIGURATION MODE <M2:M1:M0> SYNCH. ASYNCH. MASTER MASTER MASTER PERIPH- PERIPH- PARALLEL SERIAL ERAL ERAL DOWN PARALLEL UP; EXPRESS USER <0:0:0> <0:1:1> <1:0:1> <1:1:0> <1:0:0> <0:1:0> OPERATION DONE DONE CCLK (0 CCLK (0 RDY; oO 0 DOUT SGCK4-GCK5-VO TDI-VO TCK-/0 TMS-O TDO-(0) VO PGCK4-GCK6-I/O vO A10 Alt __ANa Ata Al4 AS = =) SQGCK1-GCK7-1/0 Al6 16 PGCK1-GCK8-l/O Ai7 Ata Atg* A20* A21* a Oe ALLOTHERS * XC4000EX only Notes 1. A shaded table cell represents a 50 kQ - 100 {2 pull-up before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration. 4-78 July 30, 1996 (Version 1.03)$= XILINX Configuration Switching Characteristics Veo Kn Teor > _S RE-PROGRAM @#- >300ns PROGRAM aereereneraee men T PI p- INIT ~e| Ticck - Tocik CCLK OUTPUT or INPUT / }? 300 ns MO, M1, M2 (Requited) x vaio X DONE RESPONSE X1532 300 ns 0) Master Modes Description Symbol Min ~ Max Units MO = High Tpor 10 40 Power-On Reset MO = Low Teor 40 130 Program Latency Tpy 30 200 i Us per / _ CLB column 'CCLK (output) Delay Ticck 40 250 us CCLK (output) Period, slow Teck 640 2000 ns 'CCLK (output) Period, fast Teck 80 250 ns Slave and Peripheral Modes Description Symbol Min Max Units Power-On Reset _ Teor 10 33 ms Program Latency Tp 30 200 US per en ___|_ SLB column CCLK (input) Delay (required) Tieck 4 us 'CCLK (input) Period (required) Toot 100 ns July 30, 1996 (Version 1.03) 4-79XC4000 Series Field Programmable Gate Arrays XC4000E Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identitied as either Advance or Preliminary are to be considered Final. XC4000E Operating Conditions Symbol Description Min Max Units Voc Supply voltage relative to GND, T, = -0 C to +85C Commercial 4.75 5.25 Vv Supply voltage relative to GND, T, = -40C to +100C | Industrial 4.5 5.5 Vv Supply voltage relative to GND, Te = -55C to +125C_ |Military 4.5 5.5 Vv Vin High-level input voltage TTL inputs 2.0 Vec Vv CMOS inputs 70% 100% Vec Vir Low-level input voltage TTL inputs 0 0.8 V CMOS inputs 0 20% Vec Tin Input signal transition time (Note 2) 250 ns Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Typical value only. Not tested or characterized. Note 3: Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V. XC4000E DC Characteristics Over Operating Conditions Symbol Description Min Max Units Vou High-level output voltage @ Iqy = -4.0MA, Veg min TTL outputs 2.4 V High-level output voltage @ Igy = -1.0MA, Voc min CMOS outputs Voec-0.5 Vv Voi Low-level output voltage @ lo, = 12.0MA, Voc min TTL outputs 0.4 V (Note 1) CMOS outputs 0.4 V leco Quiescent FPGA supply current (Note 2) TTL input levels 10 mA CMOS input levels 1 mA I Input or output leakage current -10 +10 pA Cin Input capacitance (sample tested) PQFP and MQFP 10 pF packages Other packages 16 pF IRIN Pad pull-up (when selected) @ Vj = OV (sample tested) 0.02 0.25 mA IRE Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with a MakeBits Tie option. 1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. 4-80 July 30, 1996 (Version 1.03)$< XILINX XC4000E Absolute Maximum Ratings Symbol Description Units Vec Supply voltage relative to GND -0.5 to +7.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to Voc +0.5 Vv Vrs Voltage applied to 3-state output (Note 1) -0.5 to Voc +0.5 Vv Tste Storage temperature (ambient) -65 to +150 C Tsor Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C Ty Junction temperature Ceramic packages +150 C Plastic packages +125 C Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is nat implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC4000E Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. Ail devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reflect worst-case values over the recommended operating conditions. Finished / ad a4 Internal Net a & re? ? a7 fdbk. TRIG ji | L, 4 it [<TRCRT} _ , (1 \ TRTRC 2) op SS lee a Mo (4) Trot TrcH | 5) 4 {ft } 2 OF - rdbk. RIP if > \ ~ TRCRA ~~ rdbk. DATA Aowmnk DUMMY X vaio X VALID / \ > TRCRD /> 1790 Description Symbol Min Max Units tdbk. TRIG rdbk. TRIG setup 1 Tatre 200 - ns rdbk. TRIG hold 2 Trort 50 - ns rdok. TRIG Low to abort Readback 3 Tate 100 - ns rdelk.1 tdbk.DATA delay 7 Trerp - 250 ns tdbk.RIP delay 6 Trcrr - 250 ns High time 5 TRH 250 500 ns Low time 4 Trace 250 500 ns Note 1: Timing parameters apply to all speed grades. Note 2: If rdbk. TRIG is High prior to Finished, Finished will trigger the first Readback. July 30, 1996 (Version 1.03) 4-81XC4000 Series Field Programmable Gate Arrays XC4000E Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The foliowing guidelines reflect worst-case values over the recommended operating conditions. Speed Grade -4 -3 2 | Description Symbol Device Max Max Max Units | |From pad through Teg XC4003E 7.0 4.7 [Primary buffer, XC4005E 7.0 4,7 'to any clock K | XC4006E 7.5 5.3 ' XC4008E 8.0 6.1 XC4010E 11.0 6.3 XC4013E 11.5 6.8 XC4020E 12.0 7.0 : XC4025E 12.5 7.2 |From pad through | Ts XC4003E 75 5.2 Secondary buffer, XC4005E 7.5 5.2 to any clock K XC4006E 8.0 5.8 | XC4008E 8.5 6.6 | XC4010E 11.5 6.8 _ XC4013E 12.0 7.3 | XC4020E 12.5 7.5 XC4025E 13.0 7.7 4-82 July 30, 1996 (Version 1.03)$= XILINX XC4000E Wide Decoder Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. Speed Grade -4 -3 -2 Description Symbol Device Max Max Max Units Full length, both pull-ups, TWarF XC4003E 9.2 5.0 4.3 ns inputs from IOB I-pins XC4005E 9.5 6.0 5.1 ns : XC4006E 12.0 7.0 6.2 ns | : XC4008E 12.5 8.0 7.0 ns XC4010E 15.0 9.0 8.1 ns XC4013E 16.0 11.0 9.9 ns XC4020E 17.0 13.9 12.5 ns XC4025E 18.0 16.9 15.2 ns | Full length, both pull-ups, TWAFL XC4003E 12.0 7.0 6.0 ns | inputs from internal logic XC4005E 12.5 8.0 68 ns, XC4006E 14.0 9.0 7.9 ns | XC4008E 16.0 10.0 8.8 ns | XC4010E 18.0 11.0 9.7 ns XC4013E 19.0 13.0 11.7 ns XC4020E 20.0 15.5 14.0 ns XC4025E 21.0 18.9 17.0 ns Half length, one pull-up, Twao XC4003E 10.5 6.0 5.1 ns inputs from IOB !-pins XC4005E 10.5 7.0 6.0 ns XC4006E 13.5 8.0 6.8 ns XC4008E 14.0 9.0 7.9 ns XC4010E 16.0 10.0 8.8 ns XC4013E 17.0 12.0 10.8 ns | XC4020E 18.0 15.0 13.5 ns | XC4025E 19.0 17.6 15.8 ns Half length, one pull-up, TWAOL XC4003E 12.0 8.0 6.8 ns inputs from internal logic XC4005E 12.5 9.0 7.7 ns | XC4006E 14.0 10.0 8.5 ns | XC4008E 16.0 11.0 9.4 ns | XC4010E 18.0 12.0 10.2 ns / XC4013E 19.0 14.0 11.9 ns XC4020E 20.0 16.8 14.3 ns XC4025E 21.0 19.6 16.7 ns oe Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. Note 2: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (Tpyp) and output delay (Topr or Tops), as listed under IOB Switching Characteristic Guidelines. July 30, 1996 (Version 1.03) 4-83XC4000 Series Field Programmable Gate Arrays XC4000E Horizontal Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Interna! timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. Speed Grade 4 3 -2 ~ | Description | Symbol | Device Max Max Max Units . TBUF driving a Horizontal Longline Tio1 XC4003E 5.0 4.2 3.4 ns (LL): XC4005E 5.0 5.0 4.0 ns : . . . XC4006E 6.0 59 47 ns | going High or Low to LL going High or | xCaco8E 70 63 50 ns Low, while T is Low. XC4010E 8.0 6.4 5 ns Buffer is constantly active. XC4013E 9.0 7.2 5.7 ns N XC4020E 10.0 8.2 66 ns (Note1) ___| XC4025e 11.0 9.1 7.3 ns || going Low to LL going from resistive Tiog =| XC4003E 5.0 42 3.6 | ons pull-up High to active Low. Cave 6 a3 ts | ns TBUF configured as open-drain. XC4008E 84 68 58 ns | XC4010E 10.5 6.9 59 | ons (Note1) : XC4013E 11.0 7.7 6.5 | ns XC4020 12.0 87 74 | ons XC4025E 12.0 9.6 8.2 i ons T going Low to LL going from resistive Ton XC4003E 5.5 4.6 3.9 ns pull-up or floating High to active Low. XC4005E 70 6.0 5.4 | ons 'TBUF configured as open-drain or active XC4006E 75 6.7 5.7 ; ons 9 Pp XC4008E 8.0 7.1 6.0 ; ns buffer with | = Low. XC4010E 8.5 7.3 6.2 | ns XC4013E 8.7 7.5 6.4 i ons t XC4020E 11.0 8.4 7.1 ns (Note1) XC4025E 11.0 8.4 7.4 / ons T going High to TBUF going inactive, Torr | All devices 1.8 1.5 1.3 ; ns not driving LL T going High to LL going from Low to Tpus | XC4003E 20.0 14.0 11.9 | ns High, pulled u ingle resistor. XC4005E 23.0 16.0 13.6 ns igh, pulled up by a single re XC4006E 25.0 18.0 15.3 ions XC4008E 27.0 20.0 17.0 | ons (Note 2) | XC4010E 29.0 22.0 18.7 | ns XC4013E 32.0 26.0 22.1 ns XC4020E 35.0 32.5 27.6 ns XC4025E 42.0 39.1 33.2 | ns | T going High to LL going from Low to Tpur | XC4003E 9.0 7.0 6.0 ns i i XC4005E 10.0 8.0 6.8 ns rs. High, pulled up by two resistors XC4006E 15 90 77 ne XC4008E 12.5 10.0 8.5 , ns (Note1) XC4010E 13.5 11.0 9.4 | ons XC4013E 15.0 13.0 11.0 ' ons XC4020E 16.0 14.8 ; ons XC4025E 18.0 16.5 ns Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. Note 2: This value includes a minimum load. The value reported by LCA2XNF -S is increased to allow for potentially heavy loading, therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination. 4-84 July 30, 1996 (Version 1.03)$< XILINX XC4000E CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade -4 -3 -2 Description ' Symbol | Min | Max | Min | Max | Min | Max Combinatorial Delays F/G inputs to X/Y outputs Tito 2.7 2.0 1.6 F/G inputs via H to X/Y outputs Tino 4.7 4.3 2.7 C inputs via SR through H to X/Y outputs TuHeo 41 3.3 2.4 C inputs via H to X/Y outputs THH10 3.7 3.6 2.2 C inputs via DIN through H to X/ outputs = THH20 4.5 3.6 2.6 CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Topcey 3.2 2.6 21 Add/Subtract input (F3) to COUT Tascy 55 4.4 3.7 Initialization inputs (F1, F3) to COUT Tincy 1.7 1.7 1.4 CIN through function generators to Tsum 3.8 3.3 2.6 X/Y outputs CIN to COUT, bypass function generators . Tpyp 1.0 0.7 0.6 Sequential Delays Clock K to outputs Q Toxo 3.7 2.8 2.8 Setup Time before Clock K F/G inputs Tick 4.0 3.0 2.4 FIG inputs via H TiHcK 6.1 4.6 3.9 C inputs via HO through H THHocK 45 3.6 3.5 C inputs via H1 through H | THeick 5.0 41 3.3 C inputs via H2 through H TyHeck 4.8 3.8 3.7 Cc inputs via DIN Toick 3.0 2.4 2.0 C inputs via EC ! Tecck 4.0 3.0 2.6 C inputs via S/R, going Low (inactive) Trek 4.2 4.0 4.0 Cin input via F/G | Teck Cin input via F/G and H | Touck {to July 30, 1996 (Version 1.03) 4-85XC4000 Series Field Programmable Gate Arrays XC4000E CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. | Speed Grade 4 3 -2 | Description Symbol | Min | Max | Min | Max | Min | Max |Hold Time after Clock K | F/G inputs Texi 0) 0 0 | | |F/G inputs via H Tekin 0 0 0 | : |C inputs via HO through H ToxHHo 0 0 0 iC inputs via H1 through H Text 0 0 Q iC inputs via H2 through H ToxHHe 0 0 0 |C inputs via DIN Toko 0 0 0 | |C inputs via EC ToxEc 0 0 o C inputs via SR, going Low (inactive) Toxr 0 0 (cn : Clock | jClock High time Tou 45 4.0 40 | Clock Low time Tet 45 4.0 40 | Set/Reset Direct | Width (High) Trew | 5.5 4.0 4.0 Delay from C inputs via S/R, Trio 6.5 4.0 4.0 i__going High to Q | fo iMaster Set/Reset (Note 1) Width (High or Low) Tyraw | 13.0 11.5 11.5 Delay from Global Set/Reset nettoQ Tyra 23.0 18.7 | 17.4 Global Set/Reset inactive to first Tak active clock K edge Toggle Frequency? (MHz) (Note 2) Frog 114 125 | 125 | Note 1: Timing is based on the XC4005E. For other devices see the XACT timing calculator. Note 2: Export Control Max. flip-flop toggle rate. 4-86 July 30, 1996 (Version 1.03)$< XILINX XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing caiculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade -4 3 -2 Description Size | Symbol Min Max Min Max Min Max Write Operation Address write cycle time | 16x2 Twes 15.0 14.4 11.6 (clock K period) 32x1 | Twets 15.0 14.4 11.6 Clock K puise width 16x2 Twes 7.5 ims 7.2 ims 5.8 ims (active edge) 32x14 Twets 7.5 ims 7.2 ims 5.8 ims Address setup time 16x2 Tass 2.8 2.4 2.0 before clock K 32x1 Tasts 2.8 2.4 2.0 Address hold time 16x2 TaHs 0 0 0 after clock K 32x1 Tauts 0 0 0 DIN setup time 16x2 Toss 3.5 3.2 2.7 before clock K 32xt Tosts 2.5 1.9 1.7 DIN hold time 16x2 Tous 0 0 0 atter clock K 32x1 TouTs 0 0 0 WE setup time 16x2 Twss 2.2 2.0 1.6 before clock K 32x1 | Twsts 2.2 2.0 1.6 WE hold time 16x2 TwHs 0 0 0 after clock K 32x1 | Twuts 0 0 0 Data valid 16x2 | Twos 10.3 8.8 6.3 after clock K 32x1 Twots 11.6 10.3 7A Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing. T Tous oss Tass Tans ADDRESS DATA OUT X6461 July 30, 1996 (Version 1.03) 4-87XC4000 Series Field Programmable Gate Arrays XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade -4 3 -2 Description Size Symbol} Min Max Min Max [| Min | Max | Write Operation Address write cycle time 16x1 | Tweps | 15.0 14.4 11.6 | | (clock K period) | Clock K pulse width (active edge) = 16x17 | Tweps | 7-5 ims } 7.2 tims] 5.8 ims i Address setup time before clock K | 16x1 | Tasps | 2.8 2.5 2.4 | Address hold time after clock K 16x11 | TaHDs 0 0 0 DIN setup time before clack K 16x1 | Tosps | 2.2 1.9 1.6 DIN hold time after clock K 16x1 | Tpxps Q 0 o- |WE setup time before clock K 16x1 | Twsos | 2.2 2.0 1.6 WE hold time after clock K 16x1) Twups | 0.3 0 0 : (Data valid after clock K | 16x1 Twops 10.0 7.8 - 6.2 Note: Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing. DATA IN ADDRESS DATA OUT X6474 4-88 July 30, 1996 (Version 1.03)$< XILINX XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade -4 -3 -2 Description i Size | Symbol | Min Max Min Max Min Max Write Operation Address write cycle time 16x2 Two 8.0 8.0 8.0 32x1 Twer 8.0 8.0 8.0 Write Enable pulse width 16x2 Twp 4.0 4.0 4.0 Address setup time 16x2 Tas 2.0 2.0 2.0 before WE 32x1 Tast 2.0 2.0 2.0 Address hold time 16x2 Tay 25 2.0 2.0 after end of WE 32x1 TaHT 2.0 2.0 2.0 DIN setup time 16x2 Tos 4.0 2.2 0.8 before end of WE 32x1 Tost 5.0 2.2 0.8 DIN hold time 16x2 Too 2.0 2.0 2.0 after end of WE 32x1 Tout 2.0 2.0 2.0 Read Operation Address read cycle time 16x2 Tro 4.5 3.1 2.6 32x1 Tact 6.5 5.5 3.8 Data valid after address 16x2 TiLo 2.7 2.0 1.6 change (no Write Enable) | 32x1 Tino 4.7 4.3 2.7 Read Operation, Clocking Data into Flip-Flop Address setup time 16x2 Tick 4.0 3.0 2.4 before clock K 32x1 TineK 6.1 4.6 3.9 Read During Write Data valid after WE goes 16x2 Two 10.0 6.0 4.9 active (DIN stable 32x1 . Twort 12.0 7.3 56 before WE) | Data valid after DIN 16x2 | Typo 9.0 6.6 5.8 (DIN changes during WE); 32x1 Toor 11.0 7.6 6.2 Read During Write, Clock- ing Data into Flip-Flop WE setup time 16x2 Twek 8.0 6.0 5.1 before clock K 32x1 Twekt 9.6 6.8 5.8 Data setup time 16x2 | Tock 7.0 5.2 4.4 before clack K | S2x1 Tpext 8.0 6.2 5.3 | Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. July 30, 1996 (Version 1.03) 4-89XC4000 Series Field Programmable Gate Arrays XC4000E CLB Level-Sensitive RAM Timing Characteristics Ain re meres merece TWO mn SEIT aietieammeietame al | ADDRESS x x WRITE i int TAS <9 telat - mecca TYR sere cee TAH oo er \ | | WRITE ENABLE | y \ ef ! DATA iN REQUIRED READ WITHOUT WRITE X.Y OUTPUTS VALID VALID meee THICK > moc teat TH mH CLOCK VALID {OLD XQ, YQ OUTPUTS READ DURING WRITE WRITE ENABLE DATA IN (stable during WE} X, OUTPUTS VAUD VALID (changing during WE) OLo NEW DATA IN { | 1 VALID X, Y OUTPUTS (PREVIOUS) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP t Yate amare nr we ete cee TYR ec nen re sae WRITE ENABLE DATA IN CLOCK | le--TeKo -> 1 | i XQ, YQ OUTPUTS x2640 4-90 July 30, 1996 (Version 1.03)$2 XILINX XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL t/O) All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy between the two methods, the values listed below should be used, and the derived values must be ignored. All values are expressed in units of nanoseconds. Speed Grade -4 : -3 -2 Description ' Symbol | Device Mtaon Clock to Output Tickor KCdoeE Wa ioe ef (fast) using OFF i XC4006E 145 | 10.7 a4 ' XC4008E 15.0 : 10.8 9.2 es or | (Max) XC4010E 16.0 10.9 9.3 Lf > | XC4013E 16.5 11.0 9.4 / Global Clock-to-Output Deiay : XC4020E 17.0 i 41.0 9.4 wate | XC4025E 17.0 12.6 10.7 [Global Clock to Output Ticko XCa003e 16.5 14.0 115 limi i | XC4005 18.0 14.7 12.0 (slow limited) using OFF | XC4006E 18.5 14.7 12.0 ; : XC4008E 19.0 14.8 12.4 Tre ofr > (Max) | xc4010F 20.0 14.9 12.2 i XC4013E 20.5 15.0 12.8 Global Ciock-to-Output Delay : XC4020E 21.0 15.1 12.8 a XC4025E 21.0 15.3 13.0 input Setup Time, using IFF | Tpsur XC4003E 25 : 23 23 (no delay) | XC4005E 2.0 : 1.2 1.2 ' | XC4006E 19 1.0 1.0 | lp i ; XC4008E 14 0.6 0.6 Inout * ; (Min) XC4010E 1.0 0.2 02 See Te ry XC4013E 0.5 | 0 0 Tee Def | XC4020E 0 0 0 : to XC4025E 0 0 0 Input Hold Time, using IFF Tey XC4003E 4.0 4.0 4.0 (no delay) XC4005E 4.6 45 4.5 | XC4006E 5.0 47 47 ew ee seed D / XC4008E 6.0 5.4 54 Input * (Min) | xc4010E 6.0 55 5.5 Set-Up te rr - xC40136 7.0 65 5.5 we Bd ' XC4020E 7.5 6.7 57 | XC4025E 8.0 7.0 5.9 bee . . . L ee en Input Setup Time, using IFF Tesy : XC4003E 8.5 | 7.0 6.0 (with delay) i XC4005E 8.5 7.0 6.0 a XC4006E 8.5 7.0 6.0 einen eB XC4008E 8.5 7.0 6.0 ing * (Min) XC4010E 8.5 7.0 6.0 Set-Up t re XC4013E 8.5 7.0 6.0 a ae XC4020E 9.5 7.0 6.0 | XC4025E 9.5 7.6 6.5 Input Hold Time, using IFF Tey XC4003E Q 0 0 wi XC4005E 0 0 0 (with delay) XC4006E 0 0 0 ole | XC4008E 0 0 0 input | {Min} | xc4o10E 0 0 0 Set-Up | iFF : XC4013E 0 0 0 Hoe RS P - XC4020E 0 0 0 XC4025E 0 0 0 OFF = Output Flip-Flop \FF = Input Flip-Flop or Latch ADVANGE. July 30, 1996 (Version 1.03) 4-91XC4000 Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade -4 -3 -2 Description Symbol Device Min Max | Min Max | Min Max Propagation Delays | (TTL Inputs) : i Pad to 11, 12 Trip All devices 3.0 25 2.0 | Pad to 11, I2 via transparent latch, no delay Tei All devices 4.8 3.6 3.6 with delay Tpou XC4003E 10.4 9.3 7.0 XC4005E 10.8 9.6 7.3 | XC4006E 10.8 10.2 7.8 | XC4008E 10.8 10.6 8.1 | | XC4010E 11.0 10.8 8.2 | XC4013E 11.4 11.2 8.5 | | XC4020E 13.8 12.4 9.5 | XC4025E 13.8 13.7 9.5 | (CMOS Inputs) Pad to 11, 12 Tpipc | All devices 5.5 44 | 37 | | |Pad to 11, 12 via transparent | : latch, no delay Tec |All devices 8.8 6.8 | 6.2 | | with delay Tppiic | XC4003E 16.5 12.4 _ 11.0 XC4005E 16.5 13.2 | 11.9 XC4006E 16.8 13.4 | 12.1 | XC4008E 17.3 13.8 | 124 XC4010E 17.5 14.0 | 12.6 XC4013E 18.0 14.4 | 13.0 XC4020E 20.8 15.6 | 14.0 XC4025E 20.8 15.6 | 14.0 | (TTL or CMOS) T Tt Clock (IK) to 1, 12 (flip-flop) Tir All devices 5.6 2.8 | 28 Clock (IK) to 11, l2 (latch enable, active Low) Tu |All devices 6.2 4.0 3.9 Hold Times (Note 1) |Pad to Clock (IK), nodelay Tixp, All devices} 0 0 0 ! with delay | Txpip Alldevices) 0 0 0 |Clock Enable (EC) to Clock (IK)| | no delay Tec |Alidevices) 1.5 15 09 | with delay | Teco Alldevices| 0 QO Oo | P| Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be vaiid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 4-92 July 30, 1996 (Version 1.03)$= XILINX XC4G00E IOB Input Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to ail XC4000E devices unless otherwise noted. Speed Grade 4 -3 2 : Description Symbol | Device Min Max Min Max Min Max |Setup Times (TTL Inputs) Pad to Clock (IK), nodelay = Tick jAll devices | 4.0 2.6 17 : with delay Tpickp iXC4003E 10.9 8.2 5.5 : IXC4005E | 10.9 8.7 5.5 iXC4006E 10.9 9.2 6.6 iXC4008E | 11.1 9.6 6.9 \XC4010E 11.3 9.8 7.0 / |XC4013E 11.8 10.2 7.3 XC4020E 14.0 11.4 8.2 iXC4025E 14.0 11.4 8.2 (CMOS Inputs) Pad to Clock (IK), nodelay Tpicxc All devices| 6.0 3.3 2.4 with delay Tpicxpg +XC4003E | 12.0 8.8 6.2 XC4005E | 12.0 9.7 6.2 XC4006E | 12.3 9.9 7.3 : XC4008E | 12.8 10.3 7.6 i | XC4010E | 13.0 10.5 7.7 | XC4013E | 13.5 10.9 8.0 | XC4020E | 16.0 12.1 8.9 / | XC4025E | 16.0 12.1 8.9 : i \(TTL or CMOS) |Clock Enable (EC) to Clock (IK), no delay Teck Alldevices; 3.5 2.5 2.0 | with delay TecKp | XC4003E | 10.4 8.1 5.6 ; XC4005E | 10.4 8.5 5.6 XC4006E | 10.4 9.1 6.9 XC4008E | 10.4 9.5 7.2 XC4010E | 10.7 9.7 7.3 XC4013E | 11.1 10.1 7.6 | XC4020E | 14.0 11.3 8.5 - XC4025E | 14.0 11.3 8.5 Global Set/Reset (Note 3) Delay from GSR net ' Tar 12.0 7.8 6.8 through QtoH, 12 GSR width Tuaw 13.0 11.5 11.5 GSR inactive to first active = TyrR | Clock (IK) edge Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator. July 30, 1996 (Version 1.03) 4-93XC4000 Series Field Programmable Gate Arrays XC4000E IOB Output Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the vaiues provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade 4 3 ~2 Description Symbol Min Max Min Max Min Max Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast ToKpor 7.5 6.5 4.5 slew-rate limited| Toxpog 11.5 9.5 7.0 Output (O) to Pad, fast Tope 8.0 5.5 4.8 slew-rate limited; Tops 12.0 8.5 7.3 3-state to Pad hi-Z TrsHz 5.0 4.2 3.8 i (slew-rate independent) 3-state to Pad active | and valid, fast TTsoNF 97 8.1 7.3 slew-rate limited| Trgons 13.7 11.1 9.8 Propagation Delays (CMOS Output Levels) Clock (OK) to Pad, fast ToKPoFC 9.5 7.8 7.0 i : slew-rate limited Toxposc 13.5 11.6 10.4 Output (O) to Pad, fast Toprc 10.0 9.7 8.7 slew-rate limited. Topsc 14.0 13.4 12.1 3-state to Pad hi-Z | Trsuze 5.2 4.3 3.9 (slew-rate independent) | '3-state to Pad active and valid, fast TTSoNFC 9.1 7.6 | slew-rate limited) Trsonsc 13.1 11.4 Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. 4-94 July 30, 1996 (Version 1.03)$= XILINX XC4000E IOB Output Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are not measured directly. They are derived fram benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing caiculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade 4 -3 -2 Description | Symbol | Min Max Min Max Min | Max Setup and Hold Output (O) to clock (OK) Took 5.0 4.6 3.8 | setup time i Output (O) to clock (OK) | Toxo 0 0 o | hold time | Clock Enable (EC) to Tecok 4.8 3.5 25 | clock (OK) setup | Clock Enable (EC) to Toxec 1.2 1.2 05 | clock (OK) hold | iClock Clock High Tou 4.5 4.0 4.0 Clock Low Tet 45 4.0 4.0 Global Set/Reset (Note 3) Delay from GSR net to Pad Treo 15.0 11.8 | 87 GSR width Taw 13.0 11.5 114.5 GSR inactive to first active Tauro : clock (OK) edge Note 1: Output timing is measured at pin threshold, with SOpF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator. July 30, 1996 (Version 1.03) 4-95XC4000 Series Field Programmable Gate Arrays XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to- date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade 4 3 -2 Description | Symbol | Min Max Min Max Min Max Setup and Hold ! Input (TDI) to clock (TCK) TrprTcK setup time Input (TDI) to clock (TCK) Trextp! ; hold time \Input (TMS) to clock (TCK) TIMsTCK setup time Input (TMS) to clock (TCK) TrcKTMs hold time Propagation Delay Clock (TCK) to Pad (TDO) TrcKPa Clock Clock (TCK) High TICKH Clock (TCK) Low TroKe | Power-On Reset JTAG operation after valid TRutaG Vec Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Nate 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. XC4000L Switching Characteristics XC4000L timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http:/Awww.xilinx.com for the latest available information. XC4000EX Switching Characteristics XC4000EX timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http:/Awww.xilinx.com for the latest available information. XC4000XL Switching Characteristics XC4000XL timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at http://www.xilinx.com for the latest available information. 4-96 July 30, 1996 (Version 1.03)$< XILINX Device-Specific Pinout Tables Pin Locations for XC4003E Devices XC4003E PC | Pa ' va | PG | Bndry XC4003E PC Pa | va PG Bndry Pad Name 84 100 | 100 120 Scan Pad Name 84 100 | 100 | 120 Scan vO P47 | P47 | P44 | Ki3 | 172 Tce po pap Pag 1 G3 : 70 p4p | P48 P45 | Ji2 175 V/O {A8) P3 P93 POO G1 32 1/0 P49 P49 P46 L13 178 VO (A9) P4 Pod Pot Fl 35 VO P50 P50 P47 M13 181 10 ~1 B95} pan ET ae | Ss (WO SGCKS P51_| P51 | P48 | Lid 184 vO ; Poe | P93 | 2 AT GND P52 [| P52 | P49 | K11 - 70 (A10) Ps | Po7 | P94] 3 44 DONE Pos | Pos | Pso_| Li : 0 (A11) Pe | P98 | P95 | D1 47 VCC Po4 | P54 | Pst 110 : 70 (A12) By | pea p96 a so ,SCSCCW PROGRAM P65 | P55 | P52 M12 - VO (A13) Pe | Pi00 | P97. D2 53 vO (D7) P56 | P56 {| P53 M11 187 70 (At4) pg PT Pas 36 70, PGCK3 Po7 | P57 | P54 Nis | 190 VO, SGCKi (A15)| P10 | P2 | P99 03 59 vO (D6) P5B_ PSB | P55 M10 | 193 VCC P11 P3 P100 G3 ~ [vO . P59 P56 Ni1 196 GND pial pa tt Pt tea - 70 (D5) P59, P60 | P57 | M9 199 VO, PGCK1 (A16)| P13 P5 | P2 | B2 62 VO (ESO) Peo | P61 | PsB | N10 202 VO (A17) P14, P6 | P38 | B3 65 vO -_| Pez | P59 | 18 205 (VO, TDI pis P7 | P4 | CS. 68 vO _ -__| P63 | P6O | NO 208 (VO, TCK Pie | Pa | P5 | B4 7i [ls (D4) Per | P4 | Pel | M8 a iV, TMS Pi7|_P9 | Pe | BS 74 vO Pez | P65 P62 | NB 214 vO Pie | P10 | P7 | Ad 7 ~~ Wee Pes | P66 P63 | M7 - WO : - eect ap, GND Pea | P67 Ped | L7 : vO 1 pq Ba AB 8 70 (03) P65 | Pes | P65 | _N7 217 vO Pig | P12 P9 BE 56 VO (RS) Pee | Pg | P66 | NG 220 vO P20 | Pia. P10 | A 89 vO ~_ 1 P7o | Pe7 | NS 223 GND P21 | P14. Pit | B7 : vO : : -__| M6 226 VOC poo BIE tpi 1 GF - (VO (62) Pe7 | P7i | Pes | 16 229 0 pag Bie 1 Pia TAP go WO Pes | P72 | P6o | 232 WO Boa PIF 1 Pid TAS 35 0 (D1) Peo | P73 | P70 MB 235 1 S181 pis TAS op COCK, P70 | P74 | P71 NB 238 ve 5 ; ; 88 ior 70 (00, DIN PH P78 | P72 | _NO 241 70 Peet Pao | PIT aio | iar HO,SGCK# I) Pre p76 | Pra Ma | 88 ie Pe7 Qe ee 0 CCLK P73. P77 | P74 | LA : eo trette te ate) eye ee VO, SCGK2 p29 | P24 | P21 Ai2 119 GND B76 PaO PIF TKS - O (M1) P30 | P25 | Pee | Bit 122 | 1/0 (A0, WS) P77_| Pal | P78 | 12 2 {GND P31 | P26 | Pes | C10 -__| IO, PGCK4 (At) || P78 | P82 | P79 | NI 5 | (MO) p32, Pe7 | Ped | Cit 125 1/0 (CSI, A2) P79 | Pa3 | Peo | k2 8 ia po poo | Poe Bia ae SAS pao | ped Pet | ut at vO, PGCK2 P35_P30_ | P27 | C12 127 0 (a5) P82 | P86 P83) Ki 17 VO (HDC) P36 P31 | P28) Ai3 130 se 1-97 pad 13 30 VO - | P32] P29 | D12 133 hie pes 53 (LDC) a re no os 136 70 (A6) P83 | Pag P86 | H2 26 vO Pag | Pas | P32 | D138 142 ema = oe ne x 28 Ts} - | P36) P33_| Fit 145 ange 10 ~~) P37_| Pas) Et3 148 vO P40 | P38 : P35 Fi2 151 Additional No Connect (N.C.) Connections on PG120 Package 1/0 (INIT) P4t_| P39 P36 | F13 154 ; vec P42 | P40 Pav | Gi2.- GND P43, P4i| P38 | Git : i 0 Pa4 | P42 P3Q| Gia 157 v0 P45 | P43 P40 | H13 | 160 vO - | Pag Pat | 313 163 vO - P45 | P42 | H12 166 vO Pag P46 | P43] Hii [tes | 2898 July 30, 1996 (Version 1.03) 4-97XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4005E/L Devices | ! x PC PQ/TQ = PG| PQ. PQ Bndry ; Caos pc|pa|ta|pa| pa PQ |Bndry| Pad Namel 4 | 100 144/156 | 160 208 | Scan Pad Name|| 84 | 100 144] 186 | 160 208 | Scan; GND - | - | P27|Ct1| P29) P37] VOC pp | Poa tPidal Ha [Pig Pieal V0 P27 | P21 P28 | B12 | Pa2 | P42 | 152 VO (A8) {| P3 | P93 |P129| Hi |P143/P1e4) 44 a : ee As rs F s 188 0 (as) || Pa [Poa |Pis0| Gi [Pid44/pte5| 47) ~~ ar tors pact Bas aan vO - | P95 |P131) G2 /P145/P186) 50 oe 6 196 tP1aal Ga [piaelpiay) 53 v0 P28 | P23 | P32 B13 P36 | P46 164 VO (A10)_|| P5 | P97 |P133| F1_/P147/P190. 56 seam. fe Ba P87 | Paz 167 aN) P | Pos = ao 2 O(m1) _|/P30 P25 | P34 A1S | P38 Pda) 170 70 - Bias) E2 [Pisolpieg/ @s~SCGND P31 P26 | P35 C13 P39 | Pag) - GND _ D137 3 Piet P1904 | (MO) P32 | P27 | P36 A16 | P40 | P50| 173 > oe es VCC P33 | P28 | P37 Ci4/ P41 P55, - vO (A12) |[ P7 P99 |P138) E3 |P154/P199| 68 i (MD) Bai P20 | P38 BIS Baa PEST 7a = (A183) || P8_|P100 oa = a ee a |vO, P35 | P30) P39 B16 P43 P57) 175 - - : PGCK2 s aia aa py seu = a seer a iO (HDC) | P36 | P31 | P40) D14/ Pad P5e! 178 /0 - | - | Pat C15! P45 | P59} 181 O. P10] P2 |P143' B2 |P159 P204/ 83 0 > pag ig Pas R60 | 184 (AIS) V0 - | P32 P43 E14 P47 | P61 | 187 veG ii P3 (P14d GaP igo pa0st TT ~SC*OVLDCT)) || P7_ P33_Paa Cie Pas P62) 190 GND Pi2|P4 | P1 | C4) Pl Pp2) - GNP ~ j= PAS | FIG PBT P67 |e V0 P13| PS P2| 83 P2| P4 | 66 vo ~_| + PAB F15 | P52 | P68 | 193 PGCK1 [vO - | - P47: E16 | P53/ P69 | 196 (ate) v0 P38 P34 Pas F16 | P54/ P70 199 VO(A17) |[P14| P6 P3 > Al P3: P5 | 89. VO P39 | P35 | P49 G14] P55} P71 202 V0 |.) pat a2 Pa Pe 92 vO - | P36) P50 G15 | P56 P74 205 V0 TT ps5 G5 PSs DP?) 95 vO - P37 P51 G16 | P57 P75 208 vO.Tbl ||pPis| P7 PS B4. Pe. pa 9g (|vO P40. P38; P52 H16 | P58/ P76 211 VvO,1TCK |!pie6| Pa | P7 | AS. P7. PQ. 101 VO (INIT) || P41 P39 | P53 H15 | P59/ P77 214 GND | . | pal G?Piolpia SCS P42 P40! P54 H14 P60 | P78 - VO - - P9 B5 P11 P15 104 GND P43 P41 P55 : J14 P61 P79 - VO . . P10! B6 |P12/|P16. 107 VO P44 P42 | P56: J15 , P62 | P80: 217 VO, TMS |[P17| P9 | Pit | AS | P13| P17 110 VO P45 Pas | P57 J16 | P63 P81 | 220 v0 P18 | P10! P12) C7 | P14) P18 113 vO -__ P44 | P58 K16 | P64 P82 223 0 T+ 1pi31 By 1 P15] 21 116 V0 - | P45/P59 K15| P65 P83) 226 | V0 pit) P14 AS | P16 1 P23 119 v0 P46 | P46 | P60 K14 | P66 P86 229 V0 P19 P12/P15/| A7 |P17/ P23 122 WO P47 | P47 P61 L1i6 | P67 P87 232 V0 P20/ P13 | P16) A8 | P18 | P24| 125 VO 7 4 7 | P62 M16 | Pee PBS | 205 GND P21, P14/Pi7/ Ca |Pi9/ P25; - WO i = | P63 115 | Peo P89 238 Vere P22/P15/Pi8 Be | P20|/ P26) - [GND 7 j= | P64 114 P70 P90 - v0 P23|Pi6|/Pi9 C9 |P21/P27, 128 8VO_ | P48 | P4B | PES PIG | P73 PIS eat VO P24|P17/P20 BS | P22! P28; 131 @) P49 P49; P66 M14; P74. P96: 244 vO - | P18|P21 AQ | P23| P29. 134 vO 7 P67 NTS P75 POT | 247 vO - | - | P22, B10} P24 P30! 137 vO i 7 | P6B PIS | P76 P98 250 i) P25 | P19 | P23 C10 / P25 P33! 140 vO P50 | P50 | PEO N14 | P77 POO | 253 | /0 P26 | P20 | P24 A10 | P26 P34) 143 | Ko P51 P51 P70 RIG P78 P100 256 V0 - | - | P25/A11 | P27 P35) 146 KS _ 0 |->T pee Bin Poa B36 148 GND P52 | P52 P71 P14 P79 P101 4-98 July 30, 1996 (Version 1.03)$< XILINX XC Il pc | PQ) Ta) PG | PA PQ |Bndry xee || PC | P| Ta PG | Pa | PQ Bndry. Pad Name|| 84 | 100 | 144 | 156 | 160 208 Scan Pad Name|| 24 | 100) 144 156 | 160 | 208 | Scan DONE P53 | P53 | P72] R15| P80 /P103)_- vO, P78 | P82 |P112| P2 |P124/P162| 5 Vcc P54 | P54 P731P13/ P81 /Pios|- PGCK4 PRO- P55 | P55 | P74 /A14!/ Ps2/Pi08]- (A1) GRAM 70 - - |P113] N2 'P125/P163/ 8 VO (D7) || P56 | P56 | P75/T16 | Pas /P109 259 | {VO - - |P114) M3 | P126;P164| 14 /0, P57 | P57 | P76 | 715 | P84 P1100. 262 vO P79 | Pa3 [P115| Pi Pi27/P165| 14, PGCK3 \(CS1, A2) VO - - P77 | R13.) P85 |P111) 265 V/O (A3) P80 P84 /P116 N1 |P128/P166: 17 vO - - | P78| P12) P86 |P112| 268 GND - - |P118' L3 |P131/P171; - vO (D6) |[ P58) P58 | P79 | T14 | Pe7 P1131 271 vO - - |P119 L2 [P132/P172) 20 vO - | P59] P80 T13 | P88 P114] 274 vO - - |P120) L1 |P133 P173a] 23 GND i - | Pai Pi1| P91 -Pti9) - VO (A4) || P81 | P85 |P121) K3 |P134 P174) 26 0 - - | Pe2) R11 | P92 P120) 277 VO (A5) || P82 | Pee [P122; K2 |P135/P175| 29 0 : > | ps3] tii | P93 /Pi2t) 280. =O -_ | P87 /P123/ Ki |P137|P178| 32 VO(D5) || P59 | Peo | P84 | Tio | P94 |P122) 283. /0 - | P88 P124| J1 P138/P179/ 35 | 1/0 (CSO) || P60 | P61 | P85 | P10 | P95 |P123) 286 I/O (A6) P83 | P89 P125| J2 P139/P180; 38 V0 - | P62! P86 | RiO| P96 |/P126) 289 VO (A7)_ ||P84| P90 P126) J3 P140/P187 41 VO - P63 . P87) T9 | P97 | P127| 292 GND P1 | P91 |}P127| H2 .P141|P182: - /O (D4) ||/P61! P64 Pas] RQ P98 |P128] 295 4/2/96 VO P62 | P65 | P89] Pg P99 |P129! 298 =e a es oa a oT ey I Additional No Connect (N.C.) Connections on TQ144, 4 PG156, PQ160 & PQ208 Packages vO (D3) _|[ P65 | P68 | P92! Ts |Pi02/P132 301 VO (RS) |[Pe6 | Peg | P93/ T7 [P103/P133) 304 TQ144 PG156 PQ160 PQ208 0 - | P70] P94] T |P104/P134) 307 | P17 A4 PB PA V0 -- | P95) Av /P105/P135| 310 | Al2 Pg P3 VO (D2) || P67 P71 | P96) P7 |P106/P138) 313 D1 PIO-P13 70 P68 | P72 | P97 TS |P107/P139! 316 | 02 nee vO - -_| P98 R6 |P108/P140; 319 Baa Pa1 vO - - | P99! T4 |P109 P141/ 322 P51.PS4 GND - - |P100] P6 |P110/P142/) - Pe3-P66 vO (D1) |/Peg | P73 [P101| T3 |P113 P147/ 325 P7D.P73 i/O (RCLK,|| P70 | P74 |P102| P5 |P114/P148) 328 PBd4-PB5 RDY/ P91-P94 BUSY) P102 0 - - ('P103] R4 |P115/P149) 331 P104-P105 VO : - -P104) R3 [P116/P150, 334 P107 V0 P71 | P75 |P105| P4 P117/P151, 337 P115-P118 (DO, DIN) P124-P125 VO, P72 | P76 |P106| T2 P118/P152 340 P136-P137 SGCK4 P143-P146 (DOUT) ier Pt70 CCLK P73 | P77 |P107| R2 |P119/P153 STP 177 VCC P74. P78 /P108| P3 |P120/P154_- P188-P1a9 0,TDO |/P75- P79 [P109| T1 |P121:/P159: 0 195-P198 GND P76 P80 |P110/ N3 |P122/P160 - P2068. P28 vO P77 P81 |P111; R1 |P123|P161 (Ao, WS) 3/12/96 July 30, 1996 (Version 1.03) 4-99XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4006E Devices XC4006E = PC | TQ. PG PQ: PQ | Bndry | Kens [PC )Ya [PG Fa [Pa apay (Nome teak ean Pad Name 84 | 144 | 156 | 160 | 208 | Scan vo - moa Taig 1 P33 1 Pad 176 VCC pP2 | P1287 H3 [P142/Pi83.- /0 (A8) P3P129| Hi P143/Pi84 50 pes | i | ne me | 18 1/0 (AS) Pa Pi90| Gi Pi4a/ Pia | 53 ra Soe pas" Bi se =e = vo ~ PIs | G2 Pras | Piss) 56 iO, SCGK2 p29 P33 | Bia. Pav | PA? 191 vo ~_| P1892] GS _| P146 | F187 | 59 0 (Mi) P30 | P34| A15 | P3e | Pas | 194 | [VO (A10) P5 |P133| Fi |P147/Pi90; 62 END B51 | PSE G18 Pao | Pas Sa VO (Att) P6 |P134| Fo |PtaslPie1[ 65 MO) Bap) baa Vie + Pao b Psa 1 a7 we Pigs | E1 | Pi4o| Pig) 68 "VCC pag Pay | cia) Pa | PSE ~~ vo ~_{P136 | E2 | Piso | Pigs) 7 1 (M2) pa4.| p38) B15 P42 P56 198 GND P137) F3 | P151/ Pig4 a \ ! e Pyare mere | WSO TP Be "0 - ~_,_ D2 | PISS F198 | 77 ie - | Pat | C15 = Pep 208 4 VO (A12) P7 |P138. E3 |P154/Pi99| 80 ny ~<a Big Pde BBO) BOB 0 (A13) Pa |P139 C1 | P155/P200| 83 L ie) - | P43 | 14 P47) P61] 214 vo __-_| P1402 | P186 | P201 | 86 1/0 (LOG) P37 | P44 | C16) Pag P62) 214 vO rT. |pi41! D3 | P157|P202]) 89 0 : we Bae peg BT 0 (A14) pg |P142| B1 | Pi58/P203/ 92 6 - ae peo Peg BB 0, SGCK1 (A15)| P10 | P143/ B2_| P159|P204| 95 GND ts eg per) B67 VCC Pit |P144; C3 | P160/P205)- I GND sit ost pr Be vO - P46) F15 P52 | PEs 223 vO - P47 1 16 P53! Peg: 226 0, PGCK1 (A186)! P13 | P2 | B3 P2 | P4 98 | VO (A17) Pia. Pa | AY. P3 | P5104 WO P3B PAS FIG Pod | P70 229 vO P39 P49) Gi4. P55 | P71 | 232 vO - Pd | A2 P4 |! PB, 104 L i : io pe es pet er bie? [vo ~| P50 | Gis P56 | P74 235 VO, TDI P15. P | B4: P6 | PB | 110 vO -_; P51 | G16 | Poy | P75 | 288 VO, TCK Pie) P7 | AS.) P7 | PO) 113 WO Pao | Pe | H16 | P56 | P76 | ett (0 1+ a tata Toe 0 (INIT) pat [P53 | Hid P59 | P77 244 WO - - 59-t Bt 6 VCC P42 | P54 | H14 P60 | P78 - GND pa bes 1 bis P14 - GND Pag | P55. J14 | Pet | P79 - 70 po Bet Par TPIS Tae VO P44} P56. J15 Pe2 P80] 247 0 TSi5 Bet pia PRET ADE VO P45 | P57 J16 | P63 P81 | 250 VO, TMS P17) Pit | AS | P13 Pi7!~ 128 vO a 0 P18) P12) C7 | P14 P18 | 134 eo -__| P59 KIS | PES Pes | 286 vO Pag | P60 Kid , Pes Pas! 259 Veo vj PIS B7 PIS Pet | 184 yO P47 | P61 L16 P67 P87 | 262 og ee rere ar a TO P20 | P16 Aa | PIs P24] 143 [Wo -_j P63, LIS | Peo Peo | 268 GND - | P64 L14) P70 PIO. - (GND p21 | P17: C8 | P19 | P25 - eo - eet ieq pag tI VCC p22! pis) Bs | P20 | P26 - Wa loys B72 Pad 274 MO Pes | P19 | C9 | Pat | P27 146 VO P48 P65 P16 | P73. P95; 277 Wo Ped | P20 | Bo | Pee | Fee | 188 v0 P49. P66 | M14 P74. POS. 280 | we Pet | AS | P28 | P29 | ie 7 P67 N15 | P75 PO? 283 aie ~_| Pee | Bio | Ped | Poo | 185 Te) ". | P8 | PIs | P76 P98 286 | vO P26 | P23 | C10 | P26 | P33 | _ 158 VO / P50 P69 Ni4 P77 PSO 280 lo P26 | Ped | Ato | P26 | Fad | 161 170, SGCK3 P51 P70 | A16 | P78 P100) 292 _ MO 7 | P25 | AN | Pe7 | P36 | 164 GND P52 P71 | P14 P79 | PtOt : uO ~__ P26 | Bit | P26 | Pae | 167 DONE P53. P72 A15 | PeO Pi03' - iGND ~__ P27, O11 | Peo | PO? - VCC p54 P73 P13) PB Pic6)- vO : 7 AT | P30 PAO 170 PROGRAM P55 P74. R14 P82 P108, re) - - - + P31 | P41 = 173 4-100 July 30, 1996 (Version 1.03)$2 XILINX XC4006E | PC | TQ] PG) PQ|PQ|Bndry { XC4006E | PC | TQ) PG| PQ! PQ | Bndry | Pad Name 84 | 144 | 156 | 160 | 208 | Scan | Pad Name 84 | 144 | 156 | 160 208 | Scan VO (D7) P56 | P75 | Tie | Pea |P109) 295 vO - |P120) 1 |P133/P173| 29 VO, PGCK3 P57 | P76 | 715 Pa4 |P110, 298 |VO (Aa) Pst |P121| K3 |P134)P174] 32 0 - | P77 | RI3 | Pas | P111] 301 VO (A5) Pg2P122) Ko |P135|P175| 35 V0 > | p7e | Pi2 | Pa |P112| 304 10 - |P123| Ki [P137/P178. 38 VO (D6) psa | P79 | Ti4 | Pav | P113| 307 VO - |Pizal Jt |Pias8/Pi79) 41 V0 - | Pso | 113] Pas |P114| 310 /0 (A6) Pg3 |Pi25| J2 |Pia9|Pigo| 44 vO - - | RZ] Peg P15] 313 ~ VO (A7) Ps4 | Pi26| J3 |Pi40|Pi81> 47 | VO : - T12 | P90 | P116| 316 GNO Pi |Pi27 H2 |Pi4i/Pie2l GND - | Pat | Pit | P91 | P1149 - 4/2/96 V0 - | Pe2 | Ait | Po2 | Pi20/ 319 V0 - | pas] T11 | Pea [P121] 322 VO (D5) P59 | Pea | T10 | Poa | Pi22| 325 VO (C80) P6o P85 | P10, P95 | P123 328 Additional No Connect (N.C.) Connections on PQ160 & /0 - P86 | RIO. P96 | P126, 331 PQ208 Packages (vO - P87 | Ta | P97 |P127; 334 [1/0 (D4) P61 Pas. RO | P98 |P128) 337 PQ160 PQ208 0 P62 Peg | Pe | P99 | P1290; 340 P136 PI VGC pea | Pao | As |P100lPi30/ - P3 (GND Pea | P91 | Ps | Pt01| P131 : P12-P13 VO (D3) P65 | P92 | Ta |P102 P132/ 343 | P19-20 VO (AS) Pe6 | P93, T? | P103 P133/ 346 | P31-P32 ie) - | P94 T |P104 Pi34| 349 P38-P39 v0 ": | P95. AZ | P105/P135| 352 P51-P54 vO (D2) pe7 | Pas | P7 | P106|Pi38| 355 P65-P66 vO pes | P97 | TS | P107/P139/ 358 P72-P73 V0 - | P98] R6 |P108)P140) 361 P84-P85 vO - | P99 | 74 |P109/P141 364 Po1-P92 GND > P100) P6 PI10 | P142 P102 0 - = | RS P11 P145 367 P104-P105 v0 - = | = | Pt12/P146) 370 P107 V0 (D1) P69 P101, 13 |P113_P147, 373 Pui7-P118 VO (RCLK, P70 |P102) PS |P114) P148| 376 Pred P 12s RDY/BUSY) P136-P137 vO - |P103} R4 |} P115|P149; 379 P143-P144 v0 ~TPi04! A3 |P116|P150) 382 P155-P158 VO (BO, DIN) P71} P105. P4 |P117'P151| 385 P169-P170 /0, SGCK4 P72 |Piog T2 |P118 P1s2) 388 P176-P177 (DOUT) : Ge. P188-P189 CCLK P73 |P107! R2 | P119 P153 - P195-P196 vec P74 |P108| P3 | P120; P154 - P206-P208 6, TDO P75 |Pi09| T1 | Pi21|P159| 0 TT GND p76 |Piio) N3 |Pi22;Pieo| - 2/28/96 VO (AO, WS) P77 | P1i1, Rt |P123/Pi6e1) 2 VO, PGCK4 (A1) | P78 P112! P2 | Pi24;Pie2) 5 vO > P1413) N2 P125|/Pi63. 8 10 > pit4| M3 P126; P1641 0 (CS1, A2) P79 P115| P1 Pie7|Pi65. 14 VO (A3) Peo /P1i6) N1 P128|/P166. 17 VO - |Pii7| M2 |P129/P167_ 20 yO te Tm |P130/P168] 23 iGND - | Pti8) L3 | P131! P1717 : WO - | P19! (2 |P132/P172| 26 July 30, 1996 (Version 1.03) 4-101XC4000 Series Field Programmable Gate Arrays fo Pin Locations for XC4008E Devices xC4008E Pad Name PG | PQ | Bndry | 191 | 208 | Scan wee eens | PC PQ) PG PQ Bndry | VW 84 | 160 191 208 Scan | i Ale | Pod | 185 VGC Pi42! J4 P183 + 4 vO | XC4008E Pad Name VO (A8) [P1433 18456 eee eet GND WO (AQ) P4 P144 J2 P185559C*S: Wo vO - P145 Jt P186 62 ~~ . L VO a oo a -{ | Pp ~ : 0 = P16 Ht P1B7, 658 a aa Bye Ba jn jes VO Pay P 4 vO : - H2 |Pt88! 68 ~~ Per 82 Bia hae 200 - - VO P33. A16 =P43 203 vO _ HS [Pie | 7 vo - | P34 BIS | P44 206 | MO(A10) P5 (P147, G1 | P190! 74 0 o = "P35 G14 Pas | 200 VO (A11) P6 PI! 77 - - oo 40 - - pigs egn tC __|[ P28 | P36 A17 Pas t2 ee oe nedf EEE UE ON vO, SCGK2 P37 P47) 215 ee nee eee fee eer GND 2 PAST | G8 PAG GND pat | pao ae teat Te) -.P152: C1 'P197| 86 ee ~ pa = (MO P32.) P40 A18 | PS 221 (vO | | - Pisa 2 Pigg] 89 vee oT Bag PAO ATG P80 oT VO {A12) P7 ,P154 F3 | Pi99]) 92 wo oe -~ a (M2) P34. P42 C16 P56 | 222 VO (AI P8 Pi55. D2 P - a = 9) o mise ay 200 = 0, PACK2 || P35 | P43 B17 | P57 223 Woo Eg peop agin O(HDC) P36 P44. E16 P58 226 : | a 6 E16 PSB 226 le _ iP to UO - P45 C17 P59 229 V0 (A14) Po Pisa. C2 203 104 - ~~ 10, SGCK1(A15)*|[ P10 Pisa. ~B2__P204 107 aes - : he D7 Pe 235 ai fet Pico Be P28. i@B6) | Par aber Pea 238 (WO. PGGKI(A1) (| Pia PCS aA itotC(iti PHO P16 P68 241 VO (A17) Pia. P3.) C4. PS | 113 vo - P80 C18 ; Pet 244 - GND ~ pst Gi. Per) V0 pa | B38 | PS a1 fe vO - | P52 E18 | Pes! 247 ~- | PS] C P7 ) 119 we . ae ah a 10. Tol PIs | Pe ro Pe i22 FO [| = PSS 18 ESS 20 wo Penn em : P38 | P54. G17 P70. 253 VO, TCK Pis | P7 | B4 wo. ST pa ce VO oT P9 ) AB GND - | P10! C7 VO : > Pit] a4 vO - | P12) AB VO, TMS - Pi7 | Pig | 87 P41 P59. J16. P77 | 274 vO P18 P14 AG a {| P42 P6O J15 . P7a! - - - I : ee oa -| GND Pag P61 K15 PT ee papas HO || P4a P62 K16 | PRO 77 ; ot aren VO P45 P63 K17_ P81 280 EO AO Pee - Ped K18. P82 283 Pi9 P17. B9 P23 158 po0 Pid ca Poa vO - P65. L18 P83. 286 Pea | 289 | P20 9 Pea 161 iO oo or || P21 Pte 9 P26 VO TG PBB DOD Pee P20 B10 P26 VO P46 P66 M18 | P86 295 P23 Pei C10 P27 164. io P47, P67 M17. P87 298 Ped Pee B10 Pee 1h SSS Sd PN PBB 301 P23. AGOP2 i et YO ; - P24 AIO PB P39 | P55 G18: P71 256 - i = H1! P72 | 259 | oS aa? | p73] 262 - | P56 H18 , P74 | 265 - | ps7 sia | P75 | 268 Pao | P58. 17. | ~PV6 | 271 io. - P69 P18 pee oe 2 GND . - P70 Mi | PIO); vO ce : AMY Pt 176 i/ , > P71 Tie |) P93 307 vO ot GT P82 N79 vO |). p72 P17 Pea 310 vo P25 | P26 | BIN P38 18 WO P48 P73. N16 P95 313 4-102 July 30, 1996 (Version 1.03)P74 wv $< XILINX XC4008E Pad Name || FC | GO | AG | Fo enary XC4008E Pad Name || F | PO | ra fon | Breny vo P49 P74] Ti7 | P96 | 316 0, TDO P75 Pi21. U2 Pi59. 0 | VO - | p75 | R17 | P97 | 319 GND P76 |P122| RA3 | P160 | vO - | P76 | P16 | Pos | 322 | i/0 (AO, WS) P77 |Pi23/ T3 |P1e1 2 | vO P50. P77 |: U18 | P9g | 325 5 VO, PGCK4 (Al) P78 |Pt24/ Ut |Pig2 5 V0, SGCK3 P51 | P78. 116 P100 328 | vO - [P125| P3 Pies, 8 | GND P52 | P79 | R16 | P101 - 1 (om - |P126) R2 |Pie4, 11 | DONE ps3 | Pao | u17 [P103|_- =| = VO (CST, A2) P79 |Pi27| 72 |Pie5| 74 VCC P54 | Pai | Ris |Pi06; - = vO(A3) ~~ |P Paso |Pi28] N3 [Pi66; 17 | PROGRAM pss | Pa2 | vig |Pica) - | vO_ - | Pt2a! p2 (P1671 20 VO (D7) Ps6 | Pa3 | T15 | P109| 331 | vO} Pi30. Ti Pi68 23 | [/O, PGCK3 P57 | P84! U16 |P110) 334 GND (PP pig] M3 Piz - | VO - | P85 | T14|P111! 337 vO - - |Pis2| P1 i P172] 26 vO + | P86 | U1s | P112/ 340 vo. -)p1a3) Nt) P173)29 VO (D6) P58 | P87 | Vi7P113. 343 VO (A4) Pai |P134! M2 jPi74! 32 | Ie | Pee vie P14 346 OAS) Pe2 |Pias/ M1 | P175) 35 vO - | P89. TI3 PI15, 349 = = - - L3 |PI76 38 V0 Pea | U14 | P1te) 35200 - | P1836) 12 |P177, 41 _ GND - | Pot | T12 | Pris - vO - |P137) L4 )P178) 44 0 - | Pg2 | U13 |P120] 355, VO - |Pizsag! Ki [P179! 47 0 - P93 | vi3 | P121! 358 WO(AG) ~*|| P83. P1389. ~K2 P180~50 VO (D5) P59 | Poa | u12 |P122) 361 | ~~ (0 (A7) ay 1/0 (G50) Peo | P95 | Vi2 |P123/ 364 (GND P1 P14t Ka P182 | 0 : - | TH | P1241 367 4/2/96 ~ Me) - - | uit [P1256 |" 370 WO - POG | Vit | P26 | 373 Additional No Connect (N.C.) Connections on PG191 & Vo - | p97 | vio |P127| 376 PO208 Packages VO (D4) P1 | P98 | U0 | P128| 379 9 vO P62 P99 T10 P129. 382 [ PG@t191 PQ208 PQ208 VCC P63 P100 R10 ; P130 - [L Ai4 PA P107 GND P64 | P101) RO | P131 : B5 P3 P117 VO (D3) P65 |Pi02/ T9 |P132/) 385 ~ B6 P12 P118 ' 1/0 (RS) P66 |P103| U9 |P133! 388 Big.t=<<isiaSCOC*SSC SO vO - |Pi04{ v9 [P1334 391 Dt P38 Pi44 | vO - |P105; V8 | P135 394 [ D138 P39 P155 7 vO : ~ | Us |P136 397 F2 P51 P156 re) - - Ta |P137 400 F17 P52 P157 VO (D2) P67 |P106| V7 |P138 403 CO N2 P53 P158 4 VO P68 | P107| U7 | P139; 406 N17 P54 P169 ie) - [P108| v6 |Pi40; 409, | Aq P65 P7170 Te) - | Pto9| U6 | P141| 412 | f R18 P66 | Pi95 GND - Pio! T7 P1420 v4 P91 oe Pigg v0 Pit US Pi45 415 | [ V5 P92 P206 v0 P12 16 P46 418 | vi4 . P1020 P207 ; vO (D1) P69 | P113! V3 P147, 421 | ~ P104 WO P70 |P114; v2 | Pt48) 424 | P105 (RCLK, RDY/BUSY) ; vO - |P115| U4 | P149| 427 | = 2/28/96 vO - | P116| TS /P150; 430 | VO (DO, DIN) P71 |P117| U3 | P151| 433 VO, SGCK4 (DOUT) P72 [P1i18| 14 | Pis2) 436 -CCLK P73 | P119; V1 | P153 - 4 vec Pi20; R4 | Pisa; - July 30, 1996 (Version 1.03) 4-103XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4010E/L Devices 7 PQ/ _ | | | XC4010E/L|/ PC PQ) TQ | PG 4.9 | BG [Bndry XC4010E/L|| Pc | Pa Ta | PG | Par BG Bnary) | PadName)) 84 | 160 176 191 39g | 225 Scan Pad Name|| 84 160/176 191 59, 225 Scan 70 P19| P17 P19! BO | P23 G5 | 176 yoC 55 p140\Pi66| Ja (Pia3> De tT 0 P20 | P18| P20) C9 P24. H3 | 179 V0 (a8) _|| P3_P143/P156| J3 [P184| Ea | 62 | GND Pet | Pig | Pet | D9 | P25) He |e VO (a9) || Pa |P144/P157| J2 |P185) B7 | 65 vee P22 | P20 | P22 D10/ P26 | Hi | - 0 - [Pi45/P158/ Ji [P186 A7 | 68 vo P23 | Pai | P23 C10) P27 | H4 | 182 0 pida Pisel Hi tPia7 GF PFA V0 P24 P22| P24 B10| P28) H5 | 185 0 + ->Bg0 He Teiaa DTT 7a 0 - |P23[P25 | AQ | P29; J2 188 WO Bisi Ha Pigs EF PF 0 |[-- [P24 P26 aio P30[ Ji 194 0 (A10) || PS P147 P162/ G1 P190 AB 60 VO |p: 7 | P27) Alt P31) J3 | 194 VO (A11) || P6 Pi48P163| G2 Pi91 Be | a3) | VO + | P28 C11 PS2| 4 | 197 0 - P149/Pie4 F1 [P192) AS | 86 VO ___|| P25 | P25 | P29 Bit P33) k2 | 200 io Bigolpres ET IP19a) BE 1 a9 vO || P26 | P26 | P30 Ai2 P34 K3 | 203 GND - Pi51/P166 G3 [P194/GND* - WO || - | Pe7 | P31 B12 P35 J6 | 206 io - " . Fo P1985 De go VO - | P28 P32. A13, P36. L1 | 209 HO "Bie7 BT Pisel CB 88 GND - | P29 P33) C12 P37 GND") vo - _P152|P168, C1 P197| Ad 98 HO cts | B13 P38 | L822 vO - Pisa Pie9| 2 pide) ce 101 7 jt fs AI | P89] MI 215 0 (A12)_ || P7 P154/P170| F3 P199) B4 104 vO ~_{ P80 | P34 | A15 | P40 | KS | 218 VO (A13)_|| P8_P155/P171, D2 P200) D5 | 107 VO ~_| PST | P85 C13 | Pat | M2 | 221 | io ~BigeP172BiPs01 BB tio WO P27 P32/P36 Bi4| P42 14 224 0 > P157/P173, 3 P202 F | 113 vO ~__ P33) P37 AIG | P43 ONT 227 V0 (A14) || P9 P158.P174, C2 P203. A2/ 116 WO ~_| P34 | P38 | B15 | P44) M3 230 VO, SGCKi||P10 P159/P175) B2 P204 C3) 119 WO -_| P95 | P39 | Cid PAB! N2 293 (A15) ! vO P28 P36 /P40/A17 P46 K6 236 VGC Pia P16 Piyl ba pa0e Aa TT 'VO, SCGK2|| P29 | P37 | P41 | B16 P47, P1239 GND P12 P1 Pt D4 P2 Al - O (Mt) P30 , P38 | P42/C15 P48) N3 242 VO, PGCK1|/P13_ P2 P2|C3 | P4 D4 | 122 GND P31 P39 P43) D15 P49 |GND* - (A16) po | (MO) P32 P40/P44/ Ata P50; P2245 VO (A17) ||P14. P3. P3|C4 P5 Bi 125 VCC P33 P41 /P45|/D16 P55) Al - lO - P4 P4|B3 P6 C2 128 i(M2) ||P34_ P42| P46) C16 P56) M4 246 iO - ps pS 65 Pp? ES tat VO, PGCKa|[P35 P43 /P47/B17 P57| R2 247 VO,7Dl [P15 P6 P A2 P8 D3 134 | VO(HDC) ||P36 P4a4| Pas E16 P58 P3250 (VO, TCK |[P16 P7 P7 ' B4 |} P9: C1. 137. VO - | P45; P49,/C17;/ P59 L5 | 253 0 - P PB C6) PI0 D2 140. VO - | P46 P50 D17/ P60 N4 256 VO - P9 = PQ A3/PI1;: G6 743 1/0 - | P47,P51 B18) P61. RB 259 iO : DTI BS pia) Ea 146 VO (LDC) |[P37, P48 P52) E17/ P62 P4 262 VO TP Be pis) Dt ia9StsCO - /P49 P53 F16| P63 K7 265 ~~ GND - P10) P10: C7 P1i4/GND* - | VO - | P50 P54,C18,/P64 M5 268 VO pit Pit, A4 P15) FS 152 v0 - += B18 P65 RA | 271 | ie) - P12) P12} A5 P16: E1 155 0 - - .F17) P66: NS. 274 VO,TMS |[P17 P13: P13/ B7 P17 Fa 158 GND - _, P51 P55.G16 | P67 GND* - vO P18 P14P14. AG P18! F3. 161 - VO - P52 P56 E18 P68 RS 277 vO - - ' P15: C8 P19: G4 | 164 ie) - | P53 P57 FIt8 P69 M6 = 280 0 : pig Ay P20. G3. 167 0 ~~ 1/P38/P54 P58 G17;P70 N6 > 283 VO - P15 P17. B8 P21. G2! 170, vO P39! P55 P59/G18 P71 P6 | 286 . om - P16 P18 A& P22 Gt | 173 0 : - P6O H1I6 P72 R6 289 4-104 July 30, 1996 (Version 1.03)$< XILINX XC4010E/L|| PC PQ TQ) PG no BG Bndry| |xc4010E|| Pc | Pa. Ta PG AO BG |Bndry Pad Name|| 84 | 160} 176 | 191 | 50, | 225 | Scan Pad Name|| 84 | 160/176 191/49, | 225 | Scan, vO - | - Pei|Hi7/P73| M7 | 292 70 (C50) ||P60 P95 |P103/Vi2 P123, J12 406. vO - | P56 | P62|H18/ P74] R7 | 295 | vO - + |p104| T11 /P124 J13 | 409 | v0 - |P57/P63'J18/P75/ L7 | 298; 3831/0. - | - [P105)u11 [P125 314 | 412 vO P40/P58|P64 J17/P76| NB 301 | ~~ [1/0 - | P96 P106! Vit |P126, J15 | 415 _ vO (INT) ||P47)P59/Pe5 | J16/P77/ Pa 304 vO ~~ | P97 P107| Vi0 |P127] Jit | 418 VCC P42 | P60 | P66 | J15 P78] RB - /0 (D4) P1 | P98 (P108! U10 |P128/ H13 | 421 GND P43 P61 | P67 | K15 P79| M8 | - vO Pee | P99 [P109 T10 [P129| H14 | 424 VO P44 P62 | P68/ K16/P80/ L8 | 307 vec P63 [P100/P110| R10 |P130, Hi5 = Te) P45 P63 | P69 | K17| P81. P9 | 310 GND P64 [P101/P111| RQ 'P131/'GND*) - [vO - | P64! P70!/k18| P82) RO | 313 /O (D3) P65 P102/P112| T9 P132 H12| 427 /O - | P65 P71/L18/ P83; NO | 316 VO (RS) P66 P103/P113] U9 |P133._H11 | 430 | vO - | = /p721L17/ P84) M9 | 319 =~ - |P104)/P114' v9 [P1384 G14) 433 vO - | - | P73'L16) P85] Lg | 322 vO - [P105 P15) V8 P135 G15 436_ vo P46 | P66 | P74 M18 P86| N10 | 325 v0 | - | - (P116] Us P136| G13) 439 vO P47 | P67 [ P75. M17/ P87| KO . 328 vO : - [P117, Ts 'P137| G12 442 vO - | P68/ P76. N18 P88 R11 | 331 1/0 (D2) P67 [Pios|Pi1a. V7 (P1381 G11 445 vO - | P69/P77/ P18 Pag) P11 | 334 VO P68 (P107/P119, U7 P139) F15 448 . GND - P70!/P78;Mi6 P90/GND*; - | 10 ~T/ -1p408/P120| V6 P140 F14 451 vO - - - |N17| P91. R12 | 337 v0 - 'P109/P121| U6 P141) F13 454 vO -- | - [R18/P92 Lio | 340 =839GND || - =P110Pi22; T7 P142'GND*) - vO - | P71! P79/T18/ P93 P12 | 343 vO - + | + | V5 /P143 13 457 ie) - | P72 P80| P17 P94 Mii) 346 | = j/0 - - > V4 |P144 D15 | 460 vO P48 P73 P81/N16/P95 | R19 | 349 vO - [P111.P123, Us [P145 Fit | 463 vO P49| P74 Pe2|T17; P96) Ni2| 352 vO - |P112P124, T [P146,D14 | 466 0 - |P75/| P83 A17 P97; P13 355 | 1/0 (D1) P69 |P113/P125| V3 |P147' E12) 469 V0 - |P76| P84 P16| P98) K10 358 V/O (RCLK, ||P70 |P114/P126 V2 P148 C15 472 VO P50/ P77 P85 U18/P99 R14 361, ADY/ 0, SGCK3||P51 P78 P86 | T16 P100! N13 | 364 BUSY) _ GND P52 | P79 | P87) R16 P101/GND| - vO -_{P1iS)P127, U4 (P149| Dis 475 DONE P53 P80 | Pss|Ui7 P103| P14) - ie) -_|P116 P128, TS P150 C14 478 VEG P54 Pel P89 Ris Pi0e Ris; vO P71 'P117/P129 U3 P151 F10 481 PHOGRAM||P55 P82 P90 vig Pica Miz; - (20, DIN) _. os 70 (D7) |/P56| P83 P91 | T15 P109 Pi5 367 (OOUT) P72 P118/P130, T4 P152. BIS | 484 | vo POCKG Pe POF PHD ie PION WO cou ralPraa WT Fee ow ; nen VCC P74 |P120/P132! R4 P154 Bl4, - vO P86, POF | UTS |PTI2| M13 | 376 (0, TDO || P75 |P121/P133 U2 (P159 AIS; O /O (D6) P58 P87 P95 VI7 P113 J10 | 379 GND p76 Piad pial RB Pi60 Die TS vo ~_, PaB | POG VIG PIG L12 | 382 |v P77 |P123 P135| T3 Pi61 Ai4| 2 vO - Pag) Po7 T13 P115 M15 385 | (sy We) vO -_ P90 P98 Ui4 P116 113 388 jG PaCKal| P78 Pi24 P136| Ui P162) Bid. 5 vO : - - | V15.P117) L149 391 (At) vO st 14 118] K11 394 VO - |Pi25/P1a7| Pa [Pi63a) E118 GND - P91, P99 | T12 P119/GND* - 0 - |P126/P138 R2 [P164/ C1211 vO -__ P92 P100, U13 'P120/ K13 | 397 V0 P79 /P127/P139 T2 P165 A13. 14 | Te) - | P93 /P101|/ V13 |P121| K14 | 400 i(CS1, A2) W/O (D5) P59 | P94 P102 U12|P122' K15 | 403 VO (A3) |[P80 |P128)P140 N3 |P166 B12 17 | July 30, 1996 (Version 1.03) 4-105XC4000 Series Field Programmable Gate Arrays xc4010E/L|| Pc | Pa | Ta | PG EG | 8G |Bnary Pad Name|| 84 160 | 176/191 | 545 | 225 | Scan V0 - 'p129/Pi41| P2 [P167| A12| 20 | vO - |P130/P142| T1 |P168| C11| 23 /0 - | - | - | RT [Pte9 B11 | 26 V0 - |. = Tne [P1701 E10 | 29 GND - |Pi31P143) M3 |P171/GND*) /0 - |P132/P144) P1 [P172| A11 | 32 0 - |P133/P145| Ni [P173! Di0 | 35 0 (Aa) ||P8i |P134|P146) M2 |Pi74| Ato | 36 | VO (AS) P82 [P135|P147. Mt |P175| DO 41 V0 - | - |P148, L3 |P176) C9 44 i) - |P136|P149\ L2 |P177/ BO. 47 vO - |P137|P150| L1 |P178/ AQ . 50 ie) - |P138/P151| K1 P179| E9 53 /O (A6) P83 |P139)/P152| K2 .P180; C8 56 /O (A7) P84 'P140)P153) K3 -P181| B& 59 GND P1 'P141/P154, K4 |P182| A8 - 4/2/96 * Pads labelled GND* are internally bonded to a Ground plane within the BG225 package. They have no direct con- nection to any package pin. Additional Ground (GND) Connections on BG225 Package GND F8 G7 GB G9 H6 H7 H8 H3 H10 J7 J8 J9 Qa K8 be 2/28/96 Note: The package pins in this table are bonded to an internal Ground plane within the BG225 package. They should all be externally connected to Ground. Additional No Connect (N.C.) Connections on PQ/ HQ208 & BG225 Packages PQ/HQ208 BG225 PI A3 P3 B10 C4 C6 3/12/96 4-106 July 30, 1996 (Version 1.03)Pin Locations for XC4013E/L Devices $= XILINX ] XC4013E/L|| PQ ia PG | BG ia Bnary XC4013E/L|| Pa ie PG | BG fe Bndry Pad Name || 160 208 223 | 225 240 Scan | Pad Name || 160 208 223 | 225 240 Scan vO - - D7 F2 P20 194 | VCC Pi42| P1683 J4.| DB | P2t2| - os _, oe a mal soe 10 (AB) P143 | Pis4| v3 | 8 | P2i3| 74 70 prota es} Bar as VO (AQ) Pi44| P15 | J2 | By | P2i4| 77 6 BigP par tome hae pas a0 vO P145 | P1e6e | Ji A7 | P2165 | 80 iio Bie) Pop aa G1 1 Be { 309 v0 Pi46 | Pie7 | H1 | C7 | P2ie|] 83 70 pay) pps tag tas} per vo =| P16 | He | b7 Pet? | 86 V0 Pigs | P24 | Co | HS | P28 | 215. V0 - [Piso] 3 | E7 P2ta| a9 | GND pig | Pas} pe tH} Bee . VO (A10) Pi47 | Pi90/ Gi | Ae P220/ 92 WOO B50 1 Peet DIO THT P80 : VO (A11) Pi48 | P191 | G2 | Be P221| 95 VeC - ~ ~Tyee= > paa t v0 Pai Fa C10 H4 | P31 | 218 Wo - - Ha | C6 Pees 98 vO P23 x > 5 sa Wo - G4 | F7 Peed 101 V0 P24} P30 | Alo | v1 | P34 | 207 | uO Piag) Pi92 | Fi | AS | P225 | 104 70 a te Bae 0 10 Piso | P193| 1 | BS | P226/ 107 6 See ea teh Be ba GND Pi51 | Pi94 | G3 | GND | P227 | - 0 - st} jg pag Sas Re) - |Pi95| F2 | De | P228/] 110 1 - Bap Per Bae tase vO - | Pig OF | CS | P229| 113 Wee - Eee pa =. VO Pise2 | P197| C1 | Aa | P230] 116 0 P25] P33] B11 | K2 | P41 | 242 V0 pis3 | Pt93 | E2 | Ee | P231 |] 119 "VO (A12) Pis4.|Pig9| Fa Ba | P2932] 122 vo P26 | Pad | Al2 | KS | Pa | 245 VO (A13) Piss | P200| D2 8 | Peas ize Cf Pe7 | P85 | Bi2 | Y6 | Pas | 248 0 - - Sa AS Pega | De 10 pas | pss | A131 | P44 | 254 10 - - a ea Bags baat Co p29 | P37 | Ct2 | GND*! P45 - 0 Pis56 | P201 | Bi B3 P236 | 134 vo - O19 | 2 P46 | 264 V0 Pis7 | P202 | 63 | F P237| 137 "0 - ~_| Bis | Ka PAT | 287 1/0 (A14) Pisa | P203 C2 | A2 | P238] 140 vo 7 | P38 | B13 | 1S | PAB 260 VO, SGCK1 || P159 | P20a| B2 | C3 | P239 143 vo | P39 | AIG M1 PAG | 263 (A18) VO P30 | pao | Ais | K5 | P50. 266 VOC Pie0 | P205 ba | Be Paso vO P31) Pai | cia | M2 | P51: 269 GND PI pa | pa | At Pi - vO p32 | P42 | B14 | L4 | P52 272 vO,PGCKi || P2 | P4 | C3 | Da | P2 | 146 vO Psa) P43 | AI6 | NI | P53 275 (A16) V0 P34) p44 | B15 | M3 | P54. 278 VO (A17) Pa. P5 | c4 | BY | P3 | 149 [VO P35. P45. C14. | N2 | P55 281 v0 Pa. P6 | B3 | c2 | Pa | 152 vO P36 | P46 | A17 | K6 | P56. 284 vO Ps | py. cs | 8 | Ps | 155 vO, 8CGK2 || P37 | pa7 [ Bi | P1 | Ps?) 287 0, TDI Pe | Ps a2 | D3 | Pe | 158 (M1) Pas | P48. C15 | N3 | P58 | 290 V0, TCK pP7 | Po Ba | cr | P7 | 161 GND P3@ | P49 D15 | GNO*| P59 - V0 Pe | Pio | c | D2 | P8 | 164 | (MO) P40 | P50. Aa | P2 | Peo | 293 0 Po | Pi1 | as | Ge | Po | 167 | VCC P41 | P55. Di6 | Al | Pet : VO - | Pi2 | BS | E4 | P10 | 470 1 (M2) pa2 | P56 Ci6 | M4 | Pe2 | 294 VO - P13) Be. Di | Plt | 173 VO, PGCK2 || P43 | P57. B17 | A2 | Pes | 295 V0 - DS 3 | Pi2 | 176 /O (HDC) pa4 | P58. Ete | P38 | Pea | 298 vO : - D. E2 | P13 | 179 /0 PaS | P59. Ci7 | L5 | P65 | 301 GND PIO.) P14 | C7 GND! P14 : vO P46 | P60 Di? N4 | P66 | 304 VO Pit | Pis | a4 FS | Pis | 182 V0 p47 | P61 B18 | R38 | P67 . 307 V0 Pi2 | Pie | AS Et | Pie | 185 V0 (CDC) pags | Pe2 17 | P4 | Pes | 310 /0, TMS Pig | Pi7 | By. F4 | P17 | 188 V0 pag | P63 FIG | ~K7 | P69 | 313 vO Pi4.) Pig) AB | FS Pia | 191 V0 P50 | P64 C18 M5 | P70 | 316 VCC : : - | vec* Pig | vO - P65. D184 | P71 319 July 30, 1996 (Version 1.03) 4-107XC4000 Series Field Programmable Gate Arrays XC4013E/L|| PQ ia PG BG oa Bndry XC4013E/L}} PQ AO PG BG a Bndry Pad Name || 160 208 223 | 225 240 Scan Pad Name || 160 208 223 | 225 240 Scan vO - | Pee | Fi7 | NS. p72 | 322 VO,PGCK3 || pa4 | Pi10 Ute | Ni4 | Pi2a | 442 i) - - | 15 | PS | P73 | 325 v0 Pas | Pitt | Ti4 | Lit | P125 | 445 V0 : - | Fis | te | P74 | 328 v0 pes | P1i2 | U15 | M13 | P126| 448 GND P51| Pe? | Gie |GND*| P75... | ~ =o : - | Ri4 | Ni5 | Pi27 |) 451 V0 P52, pes | 18 | 5 | P76 331 V0 : - | Ata | Mia | Pize | 454 vO ps3 | Peg | Fi8 | M6 | P77 | 334 1/0 (D6) pe7 | P113| Vi7 | J10, Pi29 | 457 0 P54 | P70 | Gi7 | Ne | P78 | 33a7.| [VO Pes | Pii4| vie | Li2 | Pig0 | 460 (VO P55 | P71 | Gie | Pe | P79 | 340 vO P89 | P1i5 | Ti3 | Mi5 | P131 463 VCC - : - |veer} ps0 [> OO P90 | P1i| Ul4 | L13 | P132, 466 VO - | P72 Hie | R6 | P81 | 343 vO - | Pti7| Vi5| Li4 | Pi33 | 469 VO - | P73. Hi7 | M7 | P82 | 346 i) - | Pita! via | Kit | P1384) 472 vO : - | Gis N7 | Pea | 349] [GND poi | P119) 112 /GND*| P1356 - 70 : - | HI5 P7 | P85 | 352 VO : - | Ri2 115 | P1386) 475 0 Pse | P74 | H1i8.| A? | Pee | 355 V0 : > | Ri. Ki2 | P137 | 478 0 P57 | P75 | J18 | L7 | P87 | 358 vO p92 | Pi20 | Ui3.) Ki3 | P138| 481 V0 P58) P76 | J17 | N8. P88 | 361 [vO pa3 | Pi21 | via | Ki4 | Pisa | 4a4 VO (INIT) Peg | P77 | Jie | P8 P89 | 364 vec - : - [voce Pi4ol - vec P60 | P78 | Ji5 | RB | P9;O.| 1/0 (D5) Poa | P122| U12 | Kis P141 | 487 GND Pet | P79 | Kis | Me | Pot - | [vO (GSO) P95 | P123| vi2 | Ji2 | P142 | 490 V0 P62 | Paso | Kie | L8 | P92. 367 Te) - | Pi2aa | Ti | sia | Pi4a 493 0 Pes. Pai | Ki7 | P98 | P93. 370 v0 - | P1258] ull | dia | P145 496 vO Pe4. a2 | Kis | RO | PO4 | 373 v0 P96 P126| Vii | J15 | P46 499 v0 Pes pa3 | Lig | No | POS | 376 V0 Pa?) Pi27| Vio | Jit | P147| 502 ie) - | pea | Li7 | m9 | Poe | 379 0 (D4) Pea | P128) U10 | Hi3 | P148) 505 V0 - | Pes | Lie | t9 | P97 | a2 V0 Peg | Pi29 Tio | Hi4 | P149 | 508 fo) . - | 415 | Rio | P99 385 VCC Pi00 | P1390. R10 H15 | Pis0) - 10 : - Mis | P10 | Pi00. 388 ~=3 (GND Pio | Pi31.. AQ ~~ GND*| Pisi | VCC : - ~~) veer] Pind /0 (D3) Pio2| Pi32. 79 ~Hi2 | Pis2| 511 v0 Pes | P86 Mi8 | NiO | P102. 301. ~/0 (RS) Pi03 | P1338) U9 Hii | Pisa, 514 vO P67 | P87 | M17) K9 | P103 394 V0 Pi04 | P134| V9 Gi4 | Pi54. 517 vO Pes | pas | N18 | R11 | P104 397 V0 P105 | P1385) V8. Gi5 | P1i55 | 520 To) Peo | P89 | P18 | P11 | P105 400 vO - |P136! U8 Gi3 | Pi56| 523 GND P70 | P90 | Mi | GND" Pide - ~=([0 - | P137| 18 G12 Pi57 | 526 0 : - | Nis | MIO. P107. 403. ~*|VO (D2) Pio6 | Pi38| V7 Git P159| 529 v0 : - [Pts | N11 Pida | 406 V0 Pio7 | Pi39| U7 | Fi5 P160| 532 vO ~~) pai | Ni7 | R12) Pios| 409. ~=(Voo : : 7 Tyee") Piet | vO | pga [Ate | L10 | Pio) 412 = V0 Pios | Piao | ve | Fi4 | Pie2 | 536 vO P71 | pos | 116 | P12) Pili 415. [V0 Pio9 | Pi41| Us | F13 | P163| 538 ie) P72.| po4 | Pi7 | Mit | Pi12 418 vO : : RB | Gio | Pied | 541 VO P73. P95 | N16 | A13 | P13. 421 vO - fe R7 | E18 | Pies 544 v0 P74. pgs | T17.| Ni2 | Plia 424 GND Pi10. -Pi42| 17 |GNO| Pies - v0 P75, P97 | RI7 | P13] P115. 427 v0 _ Re | E14 | Pie? 547 0 P76 | Poa | Pi6 | Ki0 | P116 430 v0 TT R5 | Fi2 | Pi68 550 0 P77 | Pog Ula | Ald | Pti7| 433. ~={ 0 > pqaa | v5 | 13 | P169 553 VO, 8GCK3 || P78 | Pi00. Tie | N13 | P118) 436 [V0 pia | v4 | DI5 | P170 556 GND P79 | P101. R16 |GND*| Pii9, - v0 Pii1 | P145|| US | Fil | P171 559 DONE Pao | Pio3. Ui7 | P14 |Pi20,.- ~*(O Pii2|Pi46) 76 | b14 | Pi72 562 VCC Pai | P106 RIS | RIS |PI2i; - (WOW) P1i3 | Pi47 | V3 | E12 | P73 565 PROGRAM || Pa2 | Pi08 vie | Mi2 | Piz2, - | VO (RCLK, |fP114 | Pi4a| v2 | cis | Piva. 568 [VO (D7) Pa3 | P109| Tis P15 | Pi23) 439 .| | RDY/BUSY) ' 0 Pii5 | P149. U4 | DIS | PI75 571 4-108 July 30, 1996 (Version 1.03)$= XILINX T , | 4 xc4013E//| Pa | fi pa | BG | PO lBndry Pad Name || 160 208 223 | 225 240 Scan vO Piis | Pts0| TS | Ci4 | Pi76| 574 vO P1417 | Pi51 | U3 F10 | P177 | 577 (DO, DIN) vO, sGcK4 || Pite | Pi52| T4 | B15 | Pi78 | 580 (DOUT) CCLK Pii9 | Pisa) vi | C13; PI79 : VCC Pi20 | P154| R4 | B14 | P180 : 0, TDO Pi21 | Pi59 | u2 | Ais | P1841 0 GND Pi2z2 | Pie60| R3 | D12 | Pia2 - vO Pi23 Piet | 13 | A14 | Piss] 2 (Ao, WS) : VO, PGCK4 {{Pi24; Pie2 | U1 { B13 | Pis4| 5 (At) fe) P125 | Pies! P3 | E11 | Pies! 28 VO P126 | P1642 | C12 | Pies | 11 vO Pi27|P16e5| T2 Ai3 | PI87 | 14 (CS1, A2) WO (A3) Pi28 | Pi66| NS B12 | Pig8) 17 vO - - P4 F9 | Pis9 20 | vO - - N4 | Dit Pi90/; 23 | ie) Pi29 | Pie7| P2 | Ai2 Pi91 26 VO Pi30 | Pies | Ti | C11, Pi92' 29 vO - | Pie9| Ai | B11 | P1938. 32 vO - | Pi70; N2 | E10 ) Pi94. 35 GND P131 | P171| M3 | GND* | P196 : vO Pi32 | Pi72| P1 | Alt | Pi97. 38 | vO P133 | P173 | N1 DIO | P198; 41 vO : - M4 | C10 | P199) 44 vO : : 4 | B10 | P200 |) 47 | ivec - - - | vec* | P21 - 1/0 (A4) P134|P174. M2 | Alo | P2021 50 VO (A5) P135 | P175 M1 Da | P203 | 53 VO - | Pi7) L3 | C9 | P205| 56 V0 P136 | P177 | L2 B9 | P206| 59 | VO P137 | P17@ | Li Ag | P20o7 | 62 vO Pisa | P179 | Ki E9 | P208] 65 VO (AB) Pi39 | P1860 | K2 . CB | P209/ 68 VO (A?) Pi40 [Piet | K3 ; B8 | P20; 71 | GND Pi41 | P12; K4 | AB Pot; - | 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the BG225 package. They have no direct con- nection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the BG225 package. They have no direct connection to any package pin. Additional Ground (GND) Connections on BG225 Packages j BG225 BG225 K8 H9 " J7 H10 ~ a8 fF G7 J9 | G8 H6 6 ~t<CSt | H7 " | F8 3/11/96 The BG225 package pins in this table are bonded to an in- ternal Ground plane on the XC4013E/L die. They must all be externally connected to Ground. Additional No Connect (N.C.) Connections on PQ/ HQ208 & PQ/HQ240 Packages PQ/HQ208 PQ/HQ240 ] Pi P22 + | P3 P37 t | | P51 i. P83 " P52 | P98 + | P53 _| P1434 r P54 PiIsst F P102 P195 P104 P204 $ P105 | P219 [ P107 ~ [OP \ P156 | P157 |. P15B : _ P206 - P207 P2008. 3/20/96 $ Pins marked with this symbol are reserved for Ground connections on future revisions of the device. These pins do not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible. July 30, 1996 (Version 1.03) 4-109XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4020E Devices H PG H | | XC4020E Pad Name in sou | oan ana y XC4020E Pad Name bid mn Ws gery 1/0, TMS Pi7_ | B7 Pi7 | 218 VCC Pigg J4.SsP2T - ora aes a = VO (A8) Pi84.J3.|sP213 86 oO - 5 P20 a VO (A9) Pi85 J2. =| P214 89 hia : ba Pot 57 vO P186 | Jt P215 92 70 - tS - 550 VO _[[_Pt87 | H1 | Pate 95 iO - - - 533 V0 Piss | H2 | P217 8 349 oa 323 536 vo Pis9 | H3 P218 101 i io B30 a B54 530 VO (A10) Pi90 | Gi | P220 | 104 yo" B34 Ba PIE 34D VO (A11) P191 G2. | ~P224 107 i on - = 170 vO P22 A8 P26 245 6 - - 43 vO P23 | B9 P27 248 | VOC 4} - Baap (vo P24 ca P28 251 - - GND P25 Dg P29 - vO : H4 223 | 116 voc P26) DIO | P30 : v0 ~ G4 Peed | 119 vO P27 | C10 | P3t 254 "wo Pre | Fi 226 | 122 0 Pas | Bio | P32 | 257 VO P1i93.OEY =| P226 | (125 HO a5 tag 33a 560 | GND P194 G3.s|sP227 - a - a4 VO P30. AiO | P34 263 ie) P1095 F2 | p228 | 128 - : VO P31. OAT P35 266 ie) Pi96 =i Ss|sP229 | (131 10 Baa Cid 1 Pe 369 VO P197.C1_~| P2390) 134 10 = - - O70 vO P198 | E2 =| P2at 137 70 . - - O75 TOTatS) P2007 be Pass tas) on | P8278 VO - Di2 | P39 281 : ee oa HO - cat page 6p VvO_ P33. Bit | P41 284 WO - Ea boas ise vO P34 | At2 | P42 287 0 P201 BI P236 158 vo P35 | Bi2 | Pas 290 V0 P202 E3 P237 161 vo P36 AY Pad 293 VO (A14) P203 | C2 P238 | 164 GND Pa7_| C12 | Pas - vO - DiS P46 296 VO, SGCK1 (A15) P204.B2)SsP2BQ | 167 re - Dia BaF 396 VCC P205 | D3 | P240 - em P38 B13. P48 302 GND Pe D4 Pt ee VO P39 A14 | -P49 305 VO, PGCK1 (A16) [| P4 c3 | P2 | 170 ~ WO Bag TAS 1 B50 308 WO (air oe pat Gis Pst att vO : - 314 vO P7 C5 P5 179 V0 - a7 VO, TDI | P8 A2 P6 182 10 Sap Bia BED 320 vO, TCK re 84 al 185 vo P43 AIG P53 323 vO - - - 188 vO P44 | BI5 P54 326 vO - - - to vO p45 | C14 | P55 329 vO Pro 8S 198 vO P46 | A17 | P56 332 vO Pt AS Po 19? VO, SCGK2 P47 | Bi6 P57 335 | v0 Pre BS P10 200 0 (M1) P4g | Ci5 | P58 338 vO P13 B6 P11 203 GND 3417 p1s | ps9 I vO - D5 Pte 206 + (MO) P50 | Ais | P60 341 v0 - 06 pis 209 vec P55 | O16 | P61 (GND P14) G7 Pia : 1 (Ma) P56. | Cie | Pe2 | 342 vO PIs Aa pis 212 VO, PGCK2 P57, Bi7 | P63 | 343 | vO P16 AS P16 215 0 (HDC) P58. | E16 | P64 346 4-110 July 30, 1996 (Version 1.03)$= XILINX XC4020E Pad Name i a rs enay XC4020E Pad Name toe on ia eaary vO P59 | C17 | P65 349 | vO - a - 487 0 P60 | Di7 | P66 352 | vO - : : 490 0 P61 | Bis | P67 355 vO P95 | Nie | P1139} 493 vO (LDC) P62 E17 P68 358 vo P96 T17 | P1t4 496 vo : - 361 vO Pov | Ri7 | P11s | 499 VO - : - 364 vO Pos | Pig | P116 502 vO P63. F16 | P69 367 vO P99 | U18 | Pi17) 505 | VO P64 ' Cis | P70 370 | VO, SGCK3 Pi00 | Ti | P118 | 508 (vO P5 | Die | P71 373 GND Piot | R16 | P119 - vO Pes | Fi7 | P72 376 | DONE P103.; U17 | P120 - vO : E15 | P73 379 VCC P106 -RI5 | P121 - | [/O - Fi5 | P74 382 "PROGRAM P108 | Vig | Pi22 - | GND P67 | Gi6 | P75 7 VO (D7) P109 | 115 | P123 | 511 ie) Pes | E18 | P76 385 VO, PGCK3 Pii0 | U16 | P124 | 514 re) Peg | F18 | P77 388 | vO Pit1 | 714 | Pi25 | 517 | ne) P70 | Gi7 | P78 391 vO Pii2 | Ui5 | P126 | 520 vO P71 | Gia | P79 304 | VO - Ri4 | P127 | 523 VCC : : P80 - vO Ris | Pi2z8 | 526 | VO. P72 | Hi6 | Pel 397 vO : - - 529 | 170 P73. | H17 | P82 400 vO - - - 532 vO - : - 4030 (D8) P1143. VI7_| Pi29 | 535 vO : : 406 V0 Pi14 Vie | P130 | 538 VO - Gi5 | Ped 4og9.. 60S P1159 713 | P13. 541 (vO - Hi5 > P8s 412, =O Pit.. Ui4 | Pi32. 544 vO P74 | Hi8 . P86 415 VO Pii7. Vi5 | P1833. 547 0 P75 | J18 P87 418 | vO P118) V14._ | P134.~<550 VO P76. J17..~*P88 421 GND P19. 112. P135 - VO (INIT) P77..J16|SC~P8D 424 | vO : Ri2. P136| 553 VCC P78. J15~~=sPQO I VO - Rit P1387, 556 GND P79. ~SK15.sPQ : 0 P120.- U13.. P138 | 559 VO. Pso Ki6 | P92 427 VO P1211. V13. P139 | 562 VO P81. -Ki7 | P93 430 | Vcc - . P140 - vO P82 Ki8_ | P94 433 VO (D5) P122 ' U12. P141 | 565 VO P8318 | P95 436 | VO (G80) P1238. (V12_~sCP142 ~| 568 vO Pe4 | L17 . P96 439 VO - - 571 vO P85 | L16 | P97 442 vO : - 574 vO : : - 445 ie) Pi24.| Tit | Pi44 | 577 vO - - : 448 vO P125 | Util P145 | 580 vO : Lis P99 | 451 | vO P126| Vil. Pi46 | 583 vO : Mi5. P100| 454 | vO Pi27 | Vi0.. P147 | 586 VCC - - P1041 _ VO (D4) Pi28 | U10 | Pi48 | 589 vO P86 M18 , P102 | 457 vO Pi29 | T10 | P149 | 592 vO P87 | M17 P103 | 460 VCC P130 | R10 | P150 : vO Pes | N18 P104 | 463 | GND Pi31 | RQ.) P151 - Te) Pag | P18 P105 | 466 | VO (D3) P1i32 | T9 | P152 | 595 |GND P90 | Mi6 P106 _ VO (RS) P133 | U9 P153 | 598 VO : N15. P107 | 469 vO P134.| V9 | P154 | 601 vO - Pid P108~472 VO Piss | ve P155 | 604 VO P91 | Ni7 . P109. 475 | Te) Pi36 | U8 . P156 | 607 O_ P92) Ri8 = ~P110.. +478 Te) P137_| 18 | P157 | 610 v0 P93. 718 Pill 481 V0 - - 613 0 P94: P17. P12 484 | vO - : - 616 July 30, 1996 (Version 1.03) 4-111XC4000 Series Field Programmable Gate Arrays as 1 XC4020E Pad Name || 12 in ne | Bray | XC4020E Pad Name x rea oe Bndry VO (D2) Pi38 | v7 | Pi59 | 619 V0 Pi7a | 11 | P207 74 le) Pi39 | U7 | Pieo | 622 VO PI79.K1.sP208 {77 VCC : : Piet | - [VO (A6) P180.. K2 | P209 80 VO Pi40 | V6 | P162 625 0 (A7) Pigi | K3 | P210 83 vO. Pi41 ue | P163 628 IGND Pis2 | K4 | Pati); ie) | - Re | Pies 631 ap 196 vO - R7 . Pies | 634 GND P142 | 17 | P166 - VO - RE | P167 | 637 Additional No Connect (N.C.) Connections on HQ208 & vo - | RS | P168 | 640 HQ240 Packages vO Pi43 | vs | Pigg | 643 V0 Pia4a.| V4 | Pi70 | 646 | HQ208 HQ240 vO Pi45 | U5 | Pi71 | 649 Pt P22 t re) (Pia | Te ! pi72 | 652 P3 P37 t 70 (D1) P147 | V3. Pi73 | 655 Pol P83 t VO (RCLK, RDY/BUSY) Pi4g.| V2 | Pi74) 658 P38 + VO - - . 661 P143 10 - > fe 664 P158 + 0 Pi49 | U4 9 P175 | 667 | P195 VO Pi50 | 75 P176 670 | P204 $ "VO (DO, DIN) Pi5t | U3 | Pi77 | 673 __ P2i9 + VO, SGCK4 (DOUT) P1522: T4 P178 676 : CCLK Piss. V1_=|:s#P179 - VCC P1544 | ~P180 : 0, TBO | Piso U2 | Piet} oOo | GND P160 R3 P182 - 4 vO (AQ, WS) Pi1 | 13 | P183 2 W/O, PGCK4 (A1) Pi62, U1 P184 5 vO , Pies. P38) | P18s.| OB v0 Pisa | R2 | P1s6 11 3/20/96 VO (CS1, A2) Pies | T2 | P1987 14 VO (A3) Pi66 ' NS P188 17 + Pins marked with this symbol are reserved for Ground iO . _ : ~ 20. connections on future revisions of the device. These pins TO 7 7 23 do not physically connect to anything on the current device ie) P4 P180 26 revision. However, they should be externally connected to To 7 Na) P1900 39 Ground, if possible. VO P67. P2. P1913 vO P1681 Pi92 35 VO Pieg AY SO|sP193 38 vo Pi70-N2 | Pig4 | 41 GND Pi71 | M3 | Pi96 vO Pi72| Pi | Pigy | 44 vO P173 - NI Pigs, 47 V0 - M4 | P199 50 VO - 4 | P200 | 53 VCC - - P201 te 0 - - : 56 vO - : : 59 VO (Ad) Pi74., M2 | P202 62 70 (A5) Pi75. M1 | P2003. 65 VO Pi7) (3 P205 68 ie) P1772 p2o6 | 71 4-112 July 30, 1996 (Version 1.03)$< XILINX Pin Locations for XC4025E, XC4028EX, & XC4025E, |[ ug | pa HO 7 XC4028XL Devices PRBEXIKL. || 708 | 303 | 240 209 304 352 Sean Pad Name ; can | ORI HQ | PG | HQ PG | HQ | BG | Bndry ca 5 j= oe Pes oe 8 Pad Nama || 208 | 223} 240 299 | 304 | 352 Scan Iv te - GND - : : - {@ND*)- P1g3/ J4 |P2i2| Ki | P38 [VCC | V0 Pio | c | P8 | E7 P205| D26 218 (A8) 184) U3 | P213) Ke | P37 | O14 | 98 v0 Pii | A3 | PO | Ba P204! Goa | 224 VO (A9) Pi85| J2. P214| K3 | P36| C14 | 101 0 pia t Be pio | cs 1 pae3) Fes | baa vO (A19)_|[Piae| Ji P2i5| KS | P36. A15 | 104 0 Pig} Be | Pit Ad | Pog2 F26 | 27 vo (aia) _|[P187| Hi |P2ie) K4 | P34 BIS | 107. Gg pe] P12 By P27 Hed | 2907 io Pie H2 |P2i7, Jt | P33 | cis | 110 70 [pe T Pia | Ge | P90) Hea 233 189 H3 )P2ie| v2 | P32] Dis 113 70 - - =e + pag | GE O36 vo (aio) _|[P190/ Gi [P220/ Hi | Pat | Ate] 116 | 6 - -="}- Be pons Daze 339 VO(At1) ||Pi91| G2 }P231/ v3 P30 | B16 | 119 GND pia Do? | Pia | as 1 Poa7 TGND*) GND wif ts tf = GNDT 'VO,FCLK1 [P15 | a4 P15 | Be | P286| J23 | 242 vO ~ | 7 + | 34 | P29 | C16 | 122 (vO Pi | AS | Pi | D8 |P285 Jo4 | 245 vo : ~ | 35 | P28 | B17 | 125 V0, TMS Pi7 | B7 | Pi7 | C7 | P24) Has | 248 vO op | He | Per C17 | 128 | io Pig | as | Pi8 B7 | P2831 K23 | 251 vO - | - -_| Gi | P26 Bie | 151 Wee - ~ [pia as Tpaa2tvee Woe ~ [| = (Peep Et | P26 ivCC = io - D7 | P20 | CB |P280| K24a 254 \VO - H4 |P223| H3 | P23 | C18! 134 | vO > De | P21) E9 P2791 Ups | 357 0 - | G4 |P224| G2 | P22 | Di7| 137 6 }-asBza iba 1 BBO 10 P192| Fi |p225| H4 | P27 | A20 | 140 10 - }-p9 | pa77 | Kes | pes vo Pi93| 1 |P226| F2 | P20 BI9| 143 GNDE - Peat) = NDF GND P1941 G3_/P227| Fi] Pi9 GND) - 0 - > pe | Pave Las 1386 vO : : -_[ Hs [Pie cis | 146 6 + ~ ~aa | P275| 26 | 269 vo : : 7 GS | PIF | O18 | 149 0 P19] C8 | P23 09 | P274| M23. 272 5 P195 | Fe (P2268) 1 | P16 a :_ 152 v0 P20 | A7 | P24 | B9 | P273| M24 275 ts oo a 5 = | aS =o 3 vO P21) BB | P25 | 10 P272) M25 278 I) P22 | AB | P26 | AQ P271| M26) 281 vO P198| E2 [Peat] Fo Pra | B21 | 161 vO P23 | B9 P27 B10 | P270| Nes | 284 yo (Ai2)_||p199| F3 |P2a2! Gs | P12 | B22 | 164 v0 pa | Co P28 | Gio | Paes NS B87 vO (A13) |[P200! b2 P233| C1 | Pio | C21 | 167 END a55 1 pet ps9 Pato TBoea Ghat GND op | pf GND" veC P26 | Dio | P30 | Ait | P267, VCC" vec cp tf OC | iio P27 | C10 | Pat B10 | 266, N26 | 290 vO ji | = Fa {| P98 | p20) 170 vO P28 | B10 | P32 B11 | P265, P25 | 293 vo : . 7, ES | PB | Aes 173 v0 P29! Ag | P33 | C11 | P264) P23 296 VO 7 Fa | Pesa| 02 | P7 | Det | 176 te) P30 A10 | P34 | E11 P263) P24 , 299 vo -_, E4 | P2365) C2 | Pe | C22) 179 0 P31 | Alt | P35 | Di1 262) R26 | 302 vo P20t, Bt |P2a6) FS | PS | B24 | 182 /0 p32 |cii P36 | Al2 | P26t| R25 | 305 Te) P202| ES |P2a7| E4 | P4 | C23/ 18 he - - [Bie | Pae0| Fee | 608 vo (Ata) _|[P203| c2_Pea8| bs | Pa | 022/188 70 - - } xia [pose Raa tain VO, SGCK1,||P204| Ba |P239| C3 | P2 | C24| 191 - - - - yo GCKE (A15) a : : a Ci2 | P258 se 314 vec P205| D3 |P240) A2 | Pi ivcc) - | | ed GND P2 | b4 | Pi Bi |P30a;Gnp"|-t~CS ~_ | 12 | Pes?) T26 | 317 vO, PGCKI,|| PA. C3 | P2 | b4 |P303| 023 194 vO ~__ B11 | P36 E12 | Pe66 | T23 | 320 GCK1 (A16) v0 7 pi2 | P39) B13 | P2565] V26. 323 V0 (At7) Ps | c4 | P3 | B2 |Pa02| C25 | 197 vec ~_ | P40 | AIG | P253/VCC" Ve) P6 B3 P4 B3 P301| D24 200 VO P33 | B11 | P41 | A14 | P252| U24 326 vO P7 C5 | PS E6 | P300| E23 203 : Vo P34 | Ail2 | P42 | C13 P251! V25 329 | VO, TDI P38 A2 P6 D5 |P299| C26 206 vO P35 | B12 | P43 | B14 P250/ V24 332 VO, TCK Pg B4 P7 ca |P298! E24 | 209 /O, FCLK2 P36 | A13 ; P44 | DI3 | P2a9 U23 335 | iO - | | AG | P27, Fea | 212 | = GND _ P37 | C12 | PAS | AIS | P24BGNO"| = July 30, 1996 (Version 1.03) 4-113XC4000 Series Field Programmable Gate Arrays T T ee i ow. To es rs oer | Ha | PG HO PG | HQ BG | Bndry reese || wa) PG | HQ) PG | HO | BG | Bndry | pad Name || 208 | 223 240 | 299 | 304 | 352 | Sean PadName || 208 | 223 , 240 299 | 304 | 352 | Scan ey - - | + | BIS | R247) 26 | 338 vO - - ~ S17 | P201 | AEI7; 457 vO - |e - | E13 | Peas | w25 | Ko) - - - | H19 P200| AE16| 460 vO - | DI3 | P46 C14 | P245| Wea GND - - | P83; - , - |GND| - VO - | D14 | P47 | AIT | P244} v23 _ vw ode ds - | Heo | P199 | AF16| 463 | VO |) P38 B13 P48 | D14 | P243 AA26 350! =O : - >. J18 | P198 AC15| 466 | (vO P39 Ald P49 | B16 P242 Y25 353 ie) - | Gi5 | P84 349 | P197)AD15{ 469 | vO ~ |} P40 1S | P50 | C15 | P241! Y24 366 | Vo - H15/ Pas Kite |Pig6|AE15| 472 vO. __|[ P41 | C13.) P51 | E14 | P240 AAZ5 360 - tio Ba Hi8 | Pas J20 | P195/ AFIS 475 __ GND - - -) oe [vo P75 | J18 | P87 K17 |P194/AD14 478 vee ff. 7 - - ) ef vo P76 J17 | P88 K18 'P193{/AE14 481 VO - | - . - | Atg | P239)AB25' 362 vO (INIT) {[ P77 Ji6 | P89. Ki9_-PIs2;AFI4 484 | VO. - | - | DIS | P2368! AA24 365 VCC P78 Ji5 | P90 | L20 | Pigt|/vcce vO. P42 | B14 | P52 C16 | P237' 23 368 GND P79 | K15 P91 K20 | P190 _GND* Lo vo. P43 | A16 P53 B17 |P2s6/AC26, 371 VO Peo | Ki6 P92. L19 | P189,AE13) 487 [vo P44 | B15 | P54 B18 | P235 as 374 v0 __|[ P81 k17_ P93 L1e | P188 | AC13| 490 vO [P45 C14 | Pb5 | E15 F234 AB24| 377, \vO __|] Pe2 [kia | Poa Lie | P187|ADI3| 493 | (vO P46 Al? | P56 D16 P233/AD25 380 0 P83 18 | P95 Li7 | Pi86|AFi2! 496 | (VO, SGCK2,|[ P47 B16 P57 C17 P232 | AC24 383 ie) [Pea L17 | P96 M20. P185|AE12 499 1GCK2 | oe OY P85 6 | P97. M19 | P184FAD12. 502 0 (M1) P4g | C15 - P58 A20 | P231 AB23; 386 iO nan NB0_ P1839 GND P49 | Di5 P59} Ai9 | P230 GND! - WO Ne Pee 1 (M0) || P50 | Ate P60 | Cie | P229 AD24| 389 GNDt > Ppa VCC P&5 D16 P61 | B20 | P228, VCC" - vO oss M17 181 lr (M2)|[ P56, C16 P62 017 | P227 AC23 390 ig oh Toon te | P1890 VO, PGCK2,|| P57 B17 | P63 B19 | P226 AE24 391 iG - | 118 Pa9 | N19 P179 0 HBO P58 | E16 | ed Cig |P205/ana3) aoa "| M5 F100] P vO. || Pag C17 Pes F16 'P224)acea) gory SCS : ~_, Prot 0 Parr vO || P60 Div P6 | E17 P2235) AF24) 400 | oo mes aes aos a5 a vo Pet B18 | P67 O18 P222/AD22 408 a pas T N18 1 Piod NGF | P1737. WO(LDC) || Pe2_ E17 | P68 | C20 P221 AEZS 406 = G Pag | Pig .P105 Ala Pi72| AF? 532 vo cop 17 | P220 AE22) 409 GND P90 | M16 P106. AZ0 P171 GND, - vO Ppt G16 P2198 AF23| 412 ig TY Ne | P170) AEB 535 CC fp NEO ig B18 Pte9) ADB | 538 is Pea a 69 | bi ware t aoa HE vo ~__ NIB | P107 U20 P68 Ace 84 | i | vO - P15 |)P108! P17 .P167) AFB, 544 VO Ped C18 | P70 | E18 | Pet7 | AE21| 418 10 Ppt N17 |/P109| 119 P166. AE7 | 547_ VO Pes | D168 | Pri | O20 | Pete | ARZt 421 VO Po2 | R18 P110! R18 | P165. AD7 | 550 | ee Le poh vo P94) P17 P112| V20 |Pi63. AES | 556 vO. > FI P74 Hi6 213 AEZ0) 4300 Gain ST ENDS vO po EN R212 AF20) 493 0 oe VIG vo co FI P21 ACIS) 486 2 TRI | Pi62 AD6 | 559 | |GND P67 | | G16 P75 E20 P210| GND* . . vO. - . . | = | 118 | P1614. AC7 | 562 Me) P68 | 18 P76 HI7 P209'ADI8 439 : ~ th. vO peg | Fi P77 | Gis |P208 AE19 442 | Ne aa ne ee ae aes - ran WO P70 GI7 P78 Gt9 Peo? ACIZ 445 QS~*SY P97 | RIT | P15 Ale | P1s8 ADS 571 WO |p P71 | G18 P79 W168 | P206 ADI7 448 0 P98 | P16 | P116 T17 | P187 AES 574 __ Noe - ~_, P80 | F20 | F204 OCT vO p99 | U18 | P117. Uig Pi56. AD4 577 VO P72 | Hi6 | PB1 | J16 | P203 AEI | 451 WO, SGCK3,|P100/ Ti6 | P1i8 x20 "F155" ACS 580 vO P73 | Hi7 | P82 G20 | P202/AF18 454 Gcka | ae 4-114 July 30, 1996 (Version 1.03)$< XILINX XC4025E, | iq | pa | Ha PG | HQ BG Bndy | ee || HQ PG HQ | PG HQ | BG | Bndry. Pad Name || 208 223 | 240 | 299 | 304 | 382 | Scan Padi Name || 208 | 223 240 | 299 304 | 352 | Scan | GND P1o1 AI6 | P119/ W20 P154/GND*| - v0 [= - | x8 |P107. M4 | 697 DONE P103, U17 | P120/ vi8 -P153] AD3 | - vO . - - | v9 }P106 Lt | 700 VCC P106) A15 |P121/ xi9 | Pis2[vcc*} - GNDt - - | P158 > GNDT- PROGRAM |[P108| via Pi22| U17 | P151! AC4 | vo : - U9 }P105} Le | 703 VO (07) Pi09! T15 P123/ W19/}P150 AD2/ 583 | V0 - - -. 19 |P104' 13 706 |VO, PGCK3,|[P110 U16 . P124| Wis |P149 AC3 | 586 | VO (D2} P138, V7 )P159/ W8/P103; Ji 709 |GCKS _ _ HO P139 U7 | P160, X7 | P102) K3 712 VO P111| T14 | P125! T15 | P148| AB4 589 VCC . ~~ P1614 ' X5 Ptot vec" | _ vO Pit2| U15 |P126. Ute |P147| ADI 592 | rs) Pi40. V6 P1621 va pool Jo 718 vo 7_ | R14 | P127_Vi7 | P146| AAS 595 VO, FCLK4 [[P141, Ue P1638) W7 | P98) U3 718 | VO - RIS |P128. X18 | P145 AAS 598 0 - "Ra piea) Ua 1 pay Ka at vO : 7 UNIS | P144) ABZ 601 ig - | RV P165| We! P96 Gi. 724 vO : : 7 | Tia (P1438) ACT | 604 = GND P142/ 17 P166! X6 | P95 GNDX - | VCC To CCT - vO - | - | - | 18 | P94) H2 | 727 GND : : : : 7 GND" vO - : - W7 | P93 HS 730 0 (D6) P113; VI7 | P129/ WI7_P142, 3 0 ope | Pie7 X41) Pao jaa" [VO Pi14) V1i6 | P130/ Vi6 | P141) AA2 1o >) RS [Pies U7 P91. Fi 736 vO PIS | T13 | P1391 | X17 | P140 "AAI v0 ~ |[P143) V5 /Pie9- ws | P90; G2 739 vo PIG | U14 P1g2) U14 | Pisa Wa v0 Pi44; V4 P170. V6) P89) G3: 742 | vO P1I7) VIS P1338 V15 | P138 W3 vO P145. US |PI71) 17 | Pea, Fe: 745 vO P118; Vid P134 T13 | P1s7. Ye vO Pi46 16 P172| X83 P87| E2 | 748 vO - - > wie | P1386 Y4 GND - ee - eno v0 - - - wis | P1365] v4 Vee : To wee'y |GND PII9| 112 | P1365 X16 | P134 | GND" VO (D1) P147_ V3 /P173) U6 P86] FS | 751 | vo 7 Rte | P1396 UI3 | P133| V3 VO (RCLK, |/Pi48 v2 [P174/ v5 Pas] G4 | 754 V0 - | RW | P1387 -Vi4 | P1382) W2 -RDY/BUSY) VO, FCLK3 |/P120/ U13 | P138 w14 | P131, U4 VO y= ~~ | Wa | P84! D2 | 757 VO Pi21| V1i3 |}P139 Vi3 | P130! U3 VO |p: - - | W3 | P83 F4 760 ere : - |Pi40 X15 [P1291 vcc*, - | V0 Pi49! U4 P175 Te P82 3 , 763. 170 (D5) Pi22/ U12 )P141, T12 |P127| v2 | 643 | vO P150; T5 P176) US. P81 C2, 766 | VO (C80) |/P123/ vi2 |P142) x14 [P1261 v1 | 646 | vO ~|[Pist: U3 P177' V4. P80. D3: 769 : 'GNDt OT pag) - | {B0. DIN) i 0 : ~ |b uid Piss! ua | 649 vO, SACk4,||P152) T4 P1768) X1 | P79. Ee | 772 VO - | = |) = | W183 P1244, T2 | 652 | (OUT) | GND So GNOT = fei Pisa) Vi Pi79. V3) P7Be. C3 | vO Lt X13 P1231 | 655 VCC Pis4| R4 |Pts0. Wi P77lvcc) vO To viz Pi22 Aa 658 6 TOO StfPts9/ U2 Piet U4 ' P76) D4 | Oo VO P124. Ti | P144/ W12 P1214 561 GND P1601 Ra 1Pia2d x | P75 GND") vO Pi25 Utt | P145 7 711 120) R2 664 | io (ao, WS) |/Pi1 73 /P183. W2/ P74, BB | 2 vo Pi26 Vit | P146) X12 P119| AI 667 VO, PGCKA, |/P162) Ui [P184, V2 P73 C4 | 5 V0 P127. V10 | P147/ U11 P118| P3 | 670 GCK7 (A1) VO (D4) Pi28 U10 |P148| Vit P117' P2 |) 673 vO Pi63! P3 P18. RS P72 DS 8 V0 Pi29| Tio |P149) wit | P1168) P1 | 676 V0 Pied! R2 piss T4/! P71) AS 14 VCG P130 R10 |P150, X10 }P115/vCC*| - | vO |/Pie5| T2 'Pie7 U3 P70. DB 14 GND P1i31, RQ | P151. X11 | P114/GND*; - (CSI, A2) | So . 0 (D3) Pi32; T9 | P152, Wi0/P113| N2 | 679 __ 70 (A3) P16; No (P188 Vi P6o C67 V0 (RS) P133, U9 |P153) VIO [P112, N4 | 682_ vO : : 7 4 PB, BS 20 VO P1384. V9 (P1564) 710 |P111, N3 | 685 = WO : 72 PS | Pe7 AS 23 VO P135; V8 P1s5) U10 |Pi10. Mi | 688 = {YOO ft ee : 7 OCT V0 P136! UB P156. x9 |Pi09 M2 | 691. = |GND - - ee GND VO Pi37, T8 P157 Wo |Pi08 M3) 6940 VOL PA PIBS Ue POS CF 6 July 30, 1996 (Version 1.03) 4-115XC4000 Series Field Programmable Gate Arrays . | _ Oban || H@.| PG | HQ | PG | HQ BG | Bndry | Pad Name 208 | 223 240 | 299 | 304 352 | Sean [vO - Na |P190| T3 | P65) B6 29 vO Pie7| P2 /Pi91 Ui | Pea! AG | 32 WO Pi6g! T1 |}P192. P4 |] P63; D8 35 (VO Pi9' R1 /P193) A3 | P62) B7 38 ie) P170 N2|Pi94] N5 | P61, A7 44 vO _- | + [P195] T2 ; P6o| Do | 44 VO : - | - | R2] P59] co | 47 GND Pi71! M3 .Pi96} Ti | P58 GND*) - \VO Pi72, Pt Pi97, N4/ P57) BB | 50 ie P173/ N1 |P198) P3 | P66|D10 | 53 vO =, M4 |P199' P2 | P55| C10 56 ie) . L4 |P200 N3 | P54 | BO 59 VCC : - |P201. At | P52ivoc., - | VO - - - MS P51) AS 62 | VO . - - Pt P50 Dit! 65 vO - - - | M4 P49] B11 68 vO -. - | - | N2' Pas lA 71 GND - - - | - |GNO" - VO (Aa) Pi74[ M2 P202) Ni | P47 012. 74 VO (A5) P175| M1 -P203| M3: P46. C12. 77 | ie) P176) L3 P205} M2/| P45| B12. 80. vO P177| L2 |P206, LS | P44/ A12> 83 VO (A21) Pi78) Li |P207. M1 | P43| C13. 86 WO (A20) P179, Ki |P208 14 | Paz! B13 a9 vo (Ae) |[P180; K2 |P209. L3 | P41) A13. 92 | W/O(A7) |[P181| K3 ;}P210, L2 | P4aol B14] 95 [GND P182. K4 | P211| Lt | P39/GND*| - 4/2/96 Pads labelled GND are internally bonded to a Ground plane within the BG352 package. They have no direct con- nection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the BG352 package. They have no direct connection to any package pin. Pads labelled GND should be connected to Ground if pos- sible; however, they can be left unconnected if necessary for compatibility with other devices. Additional No Connect (N.C.) Connections on HQ208 Package N.C. | NC. | : PI P107 fo P3 - P155 P51 a P156 | P52. P157 | P53 P158 | P54 ___ P206 7 | P102 P207 B04 , P208 ~~ P105 a : 3/15/96 Additional Ground (GND) Connections on HQ240 Package ed 3/21/96 The Ground (GND) package pins in the above table should be externally connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices. Additional No Connect (N.C.) Connections on HQ304 Package 3/21/96 Note: In XC4025 (no extension) devices in the HQ304 package, P101 is a No Connect (N.C.) pin. P101 is Vec in XC4025E/L and XC4028EX/XL devices. Where necessary for compatibility, this pin can be left unconnected. 4-116 July 30, 1996 (Version 1.03)Additional No Connect, Vcc & Ground Connections on BG352 Package N.C. A18 A24 B4 B10 B23 C1 cs ca D1 3/21/96 vce A10 Al7 B2 B25 D7 D13 p19 G23 H4 KI GND Al A2 AS A8& $= XILINX July 30, 1996 (Version 1.03) 4-117XC4000 Series Field Programmable Gate Arrays ~ I Pin Locations for XOMSSEMT Devices XCA036EXML Hoses | Paai4 | Basse | Bndry | XCA036EXXL Il aso4 paaii | Bss2| BMY) 7G P266 | F20 | 130 + 326 Pad Name Scan 70, GCKi (Ai6)_|| P303.| He Ded 218 vO P264 | C21 | ust | 332 iO (A17) p302' Fe cao. 227. 0 P263 | B22, U30 | 335 V0 P30tB4 | E28 | 224) VO Paez | E21 28 | 338 VO P300. D4 | E29.) 2a7 ~~ VO P261 | D22 U29 St vO, TDI P299 | B2 | B30 | 230 vo F260 AS | V80 | 344 VO, TCK Poca <G9) bai | 233 WO Peso | B24 | Veo | 347 | 1/0 - | Fe | E30 | 236 vec - | veo* | vec | - /0 - C5 | E31 | 239 GND ~__| GND" | GND" | - 0 Bay 1 Ay apa | Bae 0 P258 | A25 | W30 | 350 0 B06 | AB TGS Bas 0 P257 | De4 | W290 | 353 VCC . VCC* . VCC* . vo . - B26 Y30 356 v0 P2905, BS | H28 | 248 WO P256 C27 28 362 v0 p204. C9) H29 | WO P2s5 Fad | AASO | 365 v0 P2093. ES | ~G30 | 254 VCC pess VCC" | VCC" | v0 p2o2 | Fi2 , H30 | 257 v0 Pease | Fes | AAzo | 368 0 P8917 Dio Be eo St*WO Pest | E27 | ABST | 371 0 5290 tT BIg tbe 1 38S V0 P2560 | B28 | AB3O | 374 70 Boag} E10 agit 366 VO, FCLK2 p249 C29 | AB2O | S77 V0 P2868 Fid_~J30.~| 269 GND P248 | GND* GND | GND paa7 | GND GNDT v0 Poa7 | 26 AB2B 380 0, FCLKI P286 | Cii K28 272 Vo P2ag | 026 | ACO | 383 70 Boas | BiB Ko OTE v0 Po45 | B30 AC29 386 V0, TMS P2e4. E11 Ka0 | 278 vo Pada | E29 | AC28 389 v0 P283. E15 = K31 | 281 vO P243 | Fee Ad29 392 VeG Baa Veer veer tT v0 P242 F380 AD28 395 vO P20. FI6 | L209 | 284 vO P24 C31 AE3O | 398 WO pe7d GIs Lao ter p240 E31 | AE29 | 401 10 | pia | maa | 290 (GND ~__| GND | GND" VO - E17 | M31 | 293 WoC 7 NGG" | CC v0 P278 | E13 | N31 | 206, WO. Pe) | B82 | Arai | 408 vO P277 | Ai5 | N28 | 299 vO p238 | ASS | AE2B 407 GND ass bene vO ps7 ASS AGST__410 VOC veartyeer to i p2s6.FS2~AF28 413 V0 P276 | B16 | P30 | 302 ve 035 | AGBO | _ 416 V0 P275.| Di6 | P28 | 305 v0 -___ B38 | AG29 | 419 0 pava | Die) Pa S08 vO P235 E33 | AHS1 422 70 BVT AIT LRT Tat 0 P234.G3i | AG28 425 0 P272 | E19 | R30 314 vo Poss 482 | AH30 | 428 6 Baya Bia ta 0, GCK2 P232 B36 AJSO. 431 0 P270. Civ R29 320 (Mt) pest | Ase | AH29 | 434 v0 p269. Cig 131 ae3_ = GND P230 GND" GNDT | = GND p268. GND" GND - y a ooo | Gant ! ao 87 Wee pes? NCCT NOC 9) P27. G33. AJB 438 4-118 July 30, 1996 (Version 1.03)$< XILINX XC4036EX/XL i Bndry | XC4036EX/XL 1 Pad Name ||H9904 PG411_ BG432 Seat Pad Name ||H@304/ PGa11 | Baas2 | Bncry VO, GCK3 P226, D36 | AK29 | 439 70 P1i86 | AD36 | AJ14 556 VO (HDC) P225 | C37 | AH27 | 442 | /O P185 AA35 AH14 ; 559 VO p224 | F34 [| AK28 | 445_ /O P184 | AE37 | AKi4 | 562 V0 P223 | J33 | AJ27 | 448 1/0 P183 | AB36 | AL13 | 565 0 P222 | D3a8 | AL28 | 451 | vO P182 | AD38 | AKi3 | 568 1/0 (LDC) P221 | G35 | AH26 | 454 | VCC -~ vec* | vec" - VO : E39 | AL27 | 457 GND - GND* | GND* - iVO - K34 | AH25 460 VO P181 | AB34 | AJI3 | 571 | 0 P220 | F388 AK26 463 VO P180 AE39 | AH13 574 | 0 P219 | G37 AL26 | 466 VO - AM36 AL12. 577 VCC - VCC* | VCC* : yO - AC35. AK12 580 GND - GND* | GND* - VO. _ P179 , AG39 | AH12 583 | ie) P218 , H38 | AH24 | 469 | vo P178 | AG37 | AN1 586 0 P217 | J37 | AJ25 | 472 vcc. P177 | VCC* | VCC* - vO P216 | G39 | AK25 | 475 vO P175 | AD34 | AL1O | 589 vO p2i5 | M34 | AJ24 | 478 0 P174 ; AN39 | AK10 | 592 0 P214 | N35 | AL24 | 481 vO P173. | AE35 | AJ10 | 595 vO P213 | P34 | AH22) 484 1/0 P172 | AH38 | AKO | 598 vo P2i2 | J35 | AJ23 | 487 GND P171.' GND* | GND* - V0 P211 | L37 | AK23 | 490 #0 " P170 AJ37_| ALB 601 "GND P210 | GND* | GND* : VO P169. AG35 | AH10 | 604 VO P209 | M38 | AJ22 | 493 VO P168 | AF34. Au 607 0 P208 | A385 | AK22 496 0 P167| AH36. AKB 610 V0 P207 [| H36 | AL22 499 V0 P166 AK36AK7613 vO P206 | 134 AJ21 502 | vO P165 AM34. AL6 616 VCG P204 | vCC* VCC" - vo P164. AH34..AU7 619 Te) P203 | N37. AH20 | 505 vO P163. AJ35 AH8 | 622 vO P202. N39 AK21 | 508 GND -_ GND* | GND* | - 0 - U35. AK20 | 511: IVvCC - vcec* | VCC" : vO R39 AJI9 || 514 VO P162 AL37 | AK6 | 625 vO P201 M36 | AL20 | 517 0 Pi61 AT38 | ALS 628 VO P200 | v34 | AH18 | 520 | 0 Pi60 AM38 > AH7 | 631 GND - GND* | GND* - | Wo P159 AN37 AJG 634 VCC - voc | VCC* - | Te) - AK34.. AK5 | 637 vO Pi99 | R37 | AK19 | 523. vO - . AR389. AL4 640 vO Pi9s | T38 | AJia | 526 | VO P158 AN35 | AK4 643 vO P197 | T36 | AL19 | 529 vO P157. AL33.. AHS | 646 vO Pi96 | V36 | AKi8 532 ie) P156.. AV38 | AK3 | 649 VO P195 | U37 | AH17 | 535 __ VO, GCK4 P155 . AT36.. AJ4 652 [vO Pi94 | U39 | AJI7 | 538 GND P154 GND* | GND" - V0 Pi93 | v3s | AJi6 | 541 DONE P1538. AR35 | AH4 : W/O (INIT) Pig2 | wa7 | AKi6 | 544 VCC Pi52.. VCC VCC* - 'VCG P191 | vcc* | vCC* - PROGRAM P1511 AN33 | AH3 - GND P190 | GND* | GND* - | V/O (D7) P150 AM32) AJ2 655 vO Pigg | Y34 | ALi6 | 547 | 1/0, GCKS P149 AP34. AG4 =| 658 ie) P188 | AC37 | AH15 | 550 vo P148 | AW39 AG3 | 661 (0 P187 | AB38 | AKi5 | 553 vO P147. AN31.. AH2 | 664 4-119 July 30, 1996 (Version 1.03)XC4000 Series Field Programmable Gate Arrays XC4036EX/XL ! | Bndr (~ XC4036EX/XKL | |) PadName ||H@304' PGa11_ BG432 Scan, PadName ||H@304, PG411 BGa32 aay | vO A AV36 | AH 667 vO P106 | AP18 . P4 784 (vO- - AR33 | AF4 | 670 VCC - | veoc* | VCC* - VO Pi46 | AP32 | AF3 | 673 | GND - GND* | GND | - VO P145 | AU35 | AG2 | 676 vO Pi05 | ARI7 | N3 787 | 0 P144 | AW33) AES | 679 3 =/0 Pi04 | ATi6 | NA 790 VO P143 | AUS3 | AF2 682 {V0 - | Avia | Mt 793 Vcc - | vec* veo | - vO - | AW13- M2796 GND - | GND* GND* : vO (D2) P1i03. ARIS L2 799 /O (D6) P142 . AV32 | AF1 685 VO" Pi02.. AP16 | L3 802 Ke) Pi41 | AU31 | AD4 | 688 | [vcc P101 | vcc* | vCC* - vO Pi40 | AR31 | AD3 | 691 vO Pog AVI2 | OKI 805 | vO Pi39 | AP28 | AE2 | 694 | /I/O, FCLK4 Pos ARIS | K2 808 vO Pi38 | AT32 | AC3 | 697 [VO P97 | AU11 K3 811 VO P137 | AV30 | AD1 700 0 P96 | ATI2 K4 814 1/0 Pi3z6 | AR29 | AC2 | 703. iGND P95 | GND* | GND* - VO P135 | AP26 | AB4 706 VO Po4 | AP14 J2 817 GND P134 | GND* | GND* - VO P93 | ARI J3 820 VO P133 | AU29 AB3 | 709 ie) P92 AVIO | U4 823 | vO P132 | AV28 | AB2 | 712 vO Poi | AT8 | H1 826 iVO, FCLK3 P131 AT28 | ABI 715 VO Pso | ATIO | H2 829 | 0 Pi30 | AR25 | AAS | 718, VO Psg | AP10 | H3 832 | VCC Pi29 | vcc* | vCc* : vo Ps8 | AP12 | H4 835 1/0 (D5) Pi27 | AP24 | AA2 | 721 vO P87 | ARQ G2 | 838 | VO (CSO) Pi26 | AU27 | Y2 724 GND - GND* | GND* ) - VO - AR27 | Y4 727 | IVCC. - vcc* | VCC" - 7/0 - | AW27 | 3 730 WO (D1) P86 | AU7 | G4 841 0 Pi25 | AT24 | W4 733 VO (RCLK, P85 | AW7 F2 844 VO P124 | AR23 | W3 736 RDY/BUSY) GND - GND* | GND* - VO - AWS5 F3 847 VCC voce |) VCC" - | {lo - AVE E1 850 0 Pi23 | AP22.V4.~~=i739~=*~S*CC'WO P84. | ART 3 853 VO P122 | AV24 V3 742 |vO P83 AV4 D1 856 _ VO P121 | AU23. U1 745 = {VO _ P82 ANS E4 859 Ye) P120. AT22.sU2 748 | vO Pai AW D2 862 vO P119 AR21 | U4 751 vO (DO, DIN) Peo | AP6 C2 865 Ve) P118 | AV22 U3 754 | YO, GCK6 (DOUT) P79 AU3 D3 868 vO (D4) P1i7 | AP20 | T1 757 | ~|CCLK P78 | ARS D4 7 vO P116 | AU21 T2 760 vcc P77 | vec* | vCC* - VCC Pris | vCC* | vece >; )O, TDO P76 | AN7 | C4 oF 'GND Pi14 | GND* | GND* _ GND P75 | GND" | GND* - VO (D3) P113 | AUI9 | T3 763 (vO (AO, WS) P74 | AT4 B3 2 1/0 (RS) Pi12 ) Av20 | Ri 766 WO, GCK7 (A1) P73 | AV2 DS 5 vO Pitt | AV18 | R2 769 vO P72 | AM8 B4 8 VO : P110 | AR19) Ad 72 | WO P71 | AL? C5 Wo VO Pio9 | ATI8 | R3 775 vO - AR3 |__BS 14 vO P10s | AW17 | P2 778 | =O -__| ARI C6 7 | 0 P107 | AVi6 | P3 781 WO (CS1, A2) _ P70 | AK6 AS 20 4-120 July 30, 1996 (Version 1.03)$< XILINX XC4036EX/XL Bnd XC4036EX/XL Dad Nene ||Haso4 | PGat1 | BGaa2 | Enery Pad Name ||H@304: PG4i1 | BG432 eney : 1/0 (A3) Peg | ANS D7 23 vO P29 U5 Dig 134 0 Pes | AMG | B6 | 26 = VO Pes | 14 | A20 | 137 vO P67 | AM2 A6 29 0 - P2 B20 140 VCC : vec" | VCC* - VO - Ni C20 | 143 | GND - GND* | GND* - vO P27 R5 C21 146 | vO P66 | ALS Ds 32 vO p26 | M2 A22 149 vO P65 | AH6 C7 35 VCC P25 " VCC* | VCC* - VO P64 | AP2 B7 38 vO P23 13 B22 152 vO P6a | AKA De 4 vO P22 | T C22 155 vO P62 | AGS | D10 44 0 P21 N5 | B23 158 0 P61 AF6 ca 47 vO P20 M4 A24 161 vO Peo | ALS BS 50 GND Pi9 | GND* | GND* - | vO P59 [| AU3 | C10 53 VO P18 K2 p22 164 GND P58 | GNO* | GND* - Ie) P17 K4 C23 | 167 0 P57 | AH2 | BtO 56 /0 P16 P6 B24 170 0 P56 | AES | A10 59 0 P15 M6 C24 173 VO P55 | AM4 | C41 62 VO P14 J3 A26 176 vO P54 | AD6 D112 65 vO P13 | H2 C25 179 VCC P52 | VCC* | VCC* - | VO (A12) Pi2 . H4 D24 182 vO P51 | AG3 | B11 68 VO (A13) P10 GB B26 185 vO P50 > AGI | C12 71 GND - GND* | GND* : vO - ACS | C13 74 VeG - vcc* | vCc* - | VO - AE1 | Ai2 77 vO Pg K6 A27 188 vO P49 | AH4 | D14 80 vO Ps Gi D25 191 vO p4g | ABE | B13 83 vo - Et C26 194 GND : GND* | GND* - vO - E3 B27 197 VCC - vcc* | vcc* - | vO P7 U7 C27 | 200 V/O (A4) P47 | AD2 | Ci4 86 1/0 P6 H6 B28 | 203 VO (A5) P46 | AB4 | Ai13 89 vO P5 C3 b27 | 206 vO P45 | AES | B14 92 vO P4 D2 B29 | 209 VO P44 [ AGI D15 95 | VO(A14) P3 5 cag | 212 VO (A21) P43. | AD4 | C15 98 VO, GCKB (A15) P2 G7 D28 | 215 VO (A20) p42 [| AAS | B15 101 VGG Pi | vccr | vcc* - VO (A6) P4i | AA3 | Bi6 | 104 4/2/96 : VO (A7) P40 Y6 Al6 107 GND P39. | GND* | GND* ~ Pads labelled GND* are internally bonded to a Ground VCC P38 vec | voc* ~ plane within the associated package. They have no direct connection to any package pin. VO (A8) P37 W3 017 110 VO (A9) P36 Y2 Al7 113 Pads labelled VCC* are internally bonded to a Vcc plane VO (A19) P35 V4 C18 116 within the associated package. They have no direct con- VO (A18) P34 T2 018 119 nection to any package pin. vO P33 U4 B18 122 vO P32 V6 A19 125 1/0 (A10) P31 U3 B19 128 | VO (A11) P30 Ri. C19 131 Vcc - vect - vcc* tr GND - GND* GND* | - 7 July 30, 1996 (Version 1.03) 4-121XC4000 Series Field Programmable Gate Arrays Additional No Connect (N.C.) Connections on HQ304 Additional No Connect, Vcc & Ground Connections on Package BG432 Package N.C. N.C. N.C. NC. vec GND P11 P176 A4 AGI Al A2 P24 P205 A8 AH6 Ali A3 P53 P254 AHS A21 P100 P281 AH19 A31 P128 AH23 C3 . ASS C29 3/22/96 AJ8 D11 AJ12 D21 Additional No Connect, Vcc & Ground Connections on ANS PG411 Package AJ20 AJ26 | ONC, Nc. | vcc GND AK11 | AI AA37 A3 AQ AK17 B6 [ AB2 Alt A19 AK24 B34 AC3 A21 A29 AK27 67, SSCAC 39 ABI A37 AL15 Cis AF2 C39 Gt ALI7 C23 AF38 D D14 C25 AJ5 F36 D20 C33 AK2 J D26 D8 AK38 L39 D34 D12 AL35 wt FA. p30 ANI AA39 J39 D32 ANS AJt u E7 AP8 AL39 P4 23. ~AP30 AP4 P36 E37 AP38 AT34 W39 F2 AR37 AU 4 FB AT2 AW9 Y36 F22 AT30 AW19 AAI G5 AUS AW29 AF4 H34 AUg AW37 AF36 y2 J5 AU13 AJ39 | \ K36 AU15 ALI w1 K38 AU17 AP36sCS w2 LS AU25 a \ w26 [135 AU37 ATI4 wst NS AV8 _AT20 ai P88 AV26 _AT26 ACA RS AV'S4 __AUS9 AD2 V2 AW15 AW3 AD30 W5 AW23 ~ AW11 AD31 "W35 AW25 ~ AW24 AE4 Y38 AW35 ~ AW31 AF29 se a AF30 3/26/96 3/22/96 4-122 July 30, 1996 (Version 1.03)$< XILINX Pin Locations for XC4044EX/XL Devices [XC404ME XXL PG4tt BG432 | Bndry Scan| ext PGati BG432 | BndryScan| _/O B20 T29 365 se oe a 0, GCKT (At6) H8 p29 242 Te) E24 U28 374 VO (A17) F6 C30 246 0 p22 u29 377 vO B4 E28 248 7) A23 v30 380 vO D4 E29 251 70 B24 v29 383 vO, TDI Be D30 254 v0 C23 v28 386 V0, TCK G9 D3i 257 0 F22 wat 389 vO F8 E30 260 VEG veC vec = VO C5 E31 263 [GND GND* GND* - vO AT G26 266 V0 A25 W390 392 V0 AS G29 269 vO D24 w29 395 VCC vCC* VCC" - v0 B26 30 398 GND GND* GND" . 0 A27 29 401 0 C7 F30 272 H0 c7 en oe 0 C27 28 404 uo oe a oe /0 Fad AA30 407 VeC vec" vec* : v0 c9 H29 281 uo - aaa a V0 E25 AA29 410 0 e 6s 7 VO E27 AB31 413 VO D10 J28|~s290 vo Be A680 ae ue a a = VO, FCLK2 C29 AB29 419 70 F10 H31 296 GND GND Ho re et a 0 F26 AB28 422 - - ii p28 AC30 425 GND GND GND 10 B30 AC29 428 VO, FCLK1 Ci K28 302 We) E29 AC28 431 vO B12 K29 305 0 D30 AD31 434 v0. TMS et se aes 0 D32 AD30 437 : - 70 F28 AD29 440 vec VCC vec : 0 F30 AD28 44a. v0 F16 L2o 34 10 C3t AE30 446 vO C13 30008 i) E31 AE29 449 f a a V0 E13 N31 326 Vee vee we - V0 B32 AF31 452 vO ANS | N28 | 329 v0 A33 AE28 465 GND GND* GND" : 0 A35 AG31 458 vec vec vec : 0 F32 AF28 461 VO F18 N29 332 VO C35 AG30 464 vO C15 N30 335 0 338 AGDS 467 vO Bi6 P30 338 Te) E33 AH31 470 vO D16 P28 344 0 Gai AG28 473 v0 D18 P29 344 0 Ha2 AH30 476 vO AIT Ast 347 V0, GCK2 B36 AJ30 479 vO E19 R30 350 O (Mt) A39 AH29 482 0 B18 R28 353 ND GND* GND* ' VO C17 R29 356 (MO) E35 AH28 485 VO C1 o 731 - 359 VCC VCC* VCC" - GND GND" GND" : (Ma) G33 AJ28 486 VOC VCC vec - VO, GCK3 D36 AK29 487 ivO F20 730 362 70 (HDC) C37 AH27 480 July 30, 1996 (Version 1.03) 4-123XC4000 Series Field Programmable Gate Arrays ped Nera PG4t11 peas2 | Bndry Scan xe Patt BG432 | Bndry Scan vO F34 AK28 493 vO AA35 AH14 625 1/0 J33 AJ27 496 0 AE37 AK14 628 WO p38 AL28 499 VO AB36 AL13 631 :VO (LBC) G35 AH26 502 vo AD38 AK13 634 VO E39. | Alay | 505 vec voc" vec - VO K34 AH25 508s GND GND* GND* : WO F338 AK26 511 yO AB34 AJ13 637 VO G37 AL26 514 re) AE39 AH13 640 VCC : veC* vocc |e vO AM36AL12 643 GND GND* GND* - Te) AC35 AK12 646. VO H38 AH24 517 vO AG39 AH12 649 vO J37 AJ25 5200 | 0 AG37 | ATI 652 VO G39 AK25 523 VCC vecc* , VCC" - VO M34 Al24 526 iO AD34 AL10 655 VO K36 AH23 529 vO 7 AN39 AK10 658 0 K38 AK24 532 vO AE35 AJ10 661 vO N35 AL24 535 vO AH38 AK 664 VO P34 AH22 538 GND GND* GND* 0 J35 AJ23 64. VO AUS? *ACLS 667 VO L37 AK23 544 vO AG35. ss AH10 670 GND GND* GND Oe 0 AF34. AWS 673 VO M38 AJ22 547 em - AH36 AK8 676 VO. R35 AK22 550 vO AK38 AJB 679 vO _ H36 AL22 553 VO AP38 AH9 682. vO T34 Al2t 556 20 AK36 AK7 685 VCC TE veer Tees = VOD AM34. | ALG 688 0 N37 | AH20.|~559 vO AH34 AJ? 691 om N39 AK21 562 vO AJ35 AH8 694 (vo U35 AK20 565 GND GND* GND* - vO A39 AJ19 568 vec VCC" VCC" 0 M36 AL20 a7 v0 AL37 AKG 697 Me) V34 AH18 574 v0 AT38 ALS 700 i|GND GND" GND* . [VO AM38 AH7 703 vec vcc* vcc" - VO AN37 AJ6 706 VO- _ Ra7, | AKA 577 oe AK34 AK5 | 709 vO T38~Ct*t(<C CSB 580 0 7 AR39 AL4 | s712 vO T36 ALI9 583 iO AN35 AK4 715 VO V36 AK18 586 VO AL33 AH5 718 vO U37 AH17 589 VO TT AV38 AK3S 7221 vO. u39 AJ17 592 VO, GCK4 AT36. | OA 724 vO W3s AKI7 S595 GND GND* | GND* - vO AC39 ALI7 | 598 | DONE _ AR35 AH4 - vO v3a AW6 | 601 WCC VCC* vec - VO (INIT) w37 | AK 16 604 PROGRAM AN33_ AHS - vCG veo | VCC oe 1/0 (D7) AM32..; Ad2 727 |GND- GND* GND" VO, GCKS AP34 AGS 730 vO" Y34 AL16 607 vo AW39 AG3 733 vO [Lace AH15 610 (vo ANS1 AH2 736 vO Y38 AL15 613 VO AV36 AHI 739 vO- AA37 AJ15 616 ie AR33 AF4 742 0 AB38 AKIS 619 iO ~ AP32 AF3 745 VO AD36 AJ14 622 (VO. AU35 AG2 748 4-124 July 30, 1996 (Version 1.03)$2 XILINX . oe __ xe XL PG411 BG432 | Bndry Scan eno PG411 | BG432_| Bndry Scan | vO AW33 AES 751 0 ARI7 N3 877 vO AU33 AF2 754. vO ATI6 N4 880 VCC Vcc voc* | - | vO i AVIA Mi 883 GND || GND* GND* - | ie) AW13 M2 886 VO (D6) Av32 AFI 757.~SsS WO (DY AR15 12 889 vO AU31 AD 760 vO AP16 L3 892 vO AR31. | = AD3 763 VCC vcec* VCC" eo Ie AP28 AE2 760 ~C*~<XHHO AV12 Ki 895 vO AP30 AD2 769 1/0, FCLK4 ARi3_ K2 898 v0 AT30 AC4 772 | AUI1 ~ K3 901 vO AT32 AC3 75 ~|~SsWO AT12 K4 904 Te) AV30. | AD1 778 CO GND GND* GND* vO AR29 AC2 731 0 ~ AP14 J2 907 vO ~ AP26 AB4 7384. VO ARI1 J3 910 GND GND* GND* : vO AV10 J4 913 Me) AU29 | ABS 787 | VO ATS at 6 vO Av28. | AB2 790 vO ATI0 H2 919 VO, FCLK3 AT28 ABI 7933 vO AP10 H3 922 VO AR25 AA3 796 re) AP12. H4 925. vec VCC* vGC* - VO || AR G2 928 O (D5) AP24 AA2 799 vO AU "G3 931 1/0 (C50) AU27 Y2 802. AV8 FA 934 VO AR27 Ya 805. GND GND* GND* - 70 AW27 3 808 VCC 7 VCC" vcc* : vO AT24 W4 ett VO (D1) AUT a4 937 ie) AR23 Ws 814 ~0. (REL, AW7 Fo) 940 GND GND* GND* - RDY/BUSY) _ ___ VCC vcc* vec" : vO AWS FS (WO AW25 We aly vO AVE El V0 AW23 V2 820 VO ART Es Te) AP22 Va so3is vO _ AVA ot v0 av24 v3 a6 VO AN9 EA re) au2s. ~*~ StSCS:t<CS~S vo AW! b2 VO AT22 uD 832. = YO (00, DIN) APG co) 0 AR21 U4 gap. Ss:<t xO CK AU3 D3 | (DOUT} VO AV22 US 8 OK ARE oa - VO (D4) AP20 T1 eat | VCC vcGc* vec" vO Au2t.~=STD B44 6700 AN? eq ae oN SNe oe on GND GND* GND* - GND* ND* - ee aa 0 Oa AU19 ~~ T3 847 NO (A0, WS) ATs BS 2 0 (RS) AV20 Ri 850 HO, GOK? (At) AV 0s vO AV18 R2 853 vO. AMS Bt 8 vO AR19 R4 856 VO. A cs i 70 ATI8 Rotts (itii ARS BS 8 V0 AW17 po gset(<t NO AR ce v v0 AVIE patti OCSN A) ae * oo v0 AP18 pa pep OAS ANS _o7 23 0 AUI7 Ni E71, AME 66 vO AW15 N2..|-874 _ AM? AG 79 VCC vec. veer 7 Veo" | __ VOC" - a GNDY | GND* - GND | _GNO* GNDX July 30, 1996 (Version 1.03) 4-125XC4000 Series Field Programmable Gate Arrays : abate || peat BG432 | Bndry sean| | ah thian PGa11 BG432 | Bndry Scan V0 AL3 D8 32 =| R5 C21 164 0 AH C7 35. ~~ M2 A22 17 vo AP2 B7 38 +~=S; = lvece.~Ct;t~C~C~CCO TCC vcc* OO vO if AKA Do 4. vO 13 B22 170 vo sd sant | BB i) _ Te | C22 173 ~ 0 AK2 AB 47 vO NS 623 |Ct76C vO AGS DIO | a OT _ M4. | A24 TP 179 VO AF6 cs 53 GND ~ GND* GND - VO ALS B9 56. ) OO K2 D22 182.S vO A C10 sos Ka C23 185 GND GND* GND* | - vO Pe | BAA | 188 vO AH2 Bio 62. vo M6 ca4Ctia Cd yO AES A10 6 |vo is D23 194 | VO AM4 cn 6 |voO | ; 5 B25 197. VO TT ADE D12 7A }.COO - J3 A26 200 voo Vee veo to a a vO AG3 Bit | 74 1/0 (A12) H4.si<iASt*~SCtO VO AGI C12 7 1/0 (A13) G3} s 26 209 on | Acs C13 80 | jGND- GND* GND" - vO ~ AEi At2 83. SswCG vec) COCO | VO AH4 D14 sOt<it~O K6A 212. | WO ABE B13 a9 i<iO Gi D2} iGND GND* GND" | OO Al C26 218C vec veo | veo |- | IO 3 B27 221 VO (A4) AD2 C14 9 | VO | 7 C27 224. VO (AS) AB4 A13 oS VO H6 B28 227. 0 AES B14 9 vO C3 D27 230 ie ACI D15 11 | CO D2 B29] 233i, WO (A21) AD4 C15 404 MO (A14) | " ES C280 02C~:tCi8 VO (A20) AAS B15 107. | '/O, GCK8(A15)s({| Ss G7. p28 239 om | AB2 | AIS 10 | vec eos | vce vO ACB C16 113 aypi96 _ : 1/0 (A6) AA3 B16 116 0 (A7) Y6 AIG 119 Pads labelled GND are internally bonded to a Ground GND GND* GND* >" plane within the associated package. They have no direct VCC ~~ VCC" VCC - | connection to any package pin. | VO (A8) w3 DI7 1220 1/0 (A8) 2 ATT 125. Pads labelled voc" are internally bonded to a Voc plane vo V2 Sy joe within the associated package. They have no direct con- 0 Ws BIT 31 nection to any package pin. 1/0 (A19) V4 C18 134. 1/0 (A18) TF pige.:taS vO Ut Bis 140. vO V6 At9 143. 170 (A10) U3 BI9. | 146 VO (A141) Ri ci9..<OS! VCC vCC* VCC" OO GND GND* GND* - VO U5 Di9. | )152 io, T4 A20..*155 VO. P2 B20. | 158 vO NI c20 et 4-126 July 30, 1996 (Version 1.03)$< XILINX Additional No Connect, Vcc & Ground Connections on Additional No Connect, Vcc & Ground Connections on PG411 Package BG432 Package N.C. vec GND A13 A3 Ag B6 Alt A19 B34 A21 A29 C25 A31 A37 C33 C39 C1 Di2 D6 Di4 E7 F36 D20 E23 Jt D26 E37 L39 D34 F2 W1 RA G5 AA39 H34 Adt L35 AL39 N.C. vec GND A4 A2 A28 All B12 B21 C8 D6 N3 AP4 P38 AT34 R3 AU1 AF2 AWS AF38 AW19 AJ5 AWe29 AL35 AW37 ANS : : AP8 AR37 AT2 AUS AU13 AUI5 AU25 AU37 AV26 AV34 AW35 3/22/96 3/26/96 July 30, 1996 (Version 1.03) 4-127XC4000 Series Field Programmable Gate Arrays Pin Locations for XC4052XL Devices | XC4052XL Pad Name BG432_ | Bndry Scan GND GNDX - WO, GCK1 (A16) p29 2660 VOI) "C30 269.~C*: (vO 8 272 | \vo Ee | PS (vO, TOI D300 278 iVO, TCK D31 et "GND GND* : VO Feest=<t*i SSS VO : F290 | 87 vo E30 290, VO E31 293 vO oO G28 2906 pe _ vo G29 299 ; IVCC VCC - GND GND* vO ~ Fad ~~ 302 | VO F31 305 i /0 H28 308 WO H29 ai 10 G30 314 vO H30 317 IGNOttst<Ctsts~S GND* eo | vO : 28 320 vO J29 323 YO H31 326 | vO J30 329 GND GND | vO, FCLK1 K28 332 | vO K29 "335 VO, TMS K30 (338 vO K31 341 vec VCC" | ie) L29 344 ve) L30 347 ;GND GND* - (vO M30 350 [vO M28 353 vO M29 356s vO Mat] 359.SCS iO ee TNSTOSC vO ~~ N28 365 GND GND* Ivo vcc* oo VO Neo0t~i SSCS VO N30 371 sd! VO P30. 2~C~*x SSCS vO : pe, ie) P29 380 | vO - R31 . 383 GND | XC4052XL PadName [| BG432_ | Bndry Scan | HO 80886 vO R28 389 vO - R29 392 vO Tat | 805 GND ~ [[- ano* os VCC _ veces vO ) AFS1 494 vo a AE28 497. iO || AF30 500 yO. ~ ~ AF29 "593 [vO | AG31 506 July 30, 1996 (Version 1.03)$< XILINX XC4052XL Pad Name BG432 Bndry Scan XC4052XL Pad Name BG432 Bndry Scan VO AF28 509 VO AL20 631 GND GND* - vO AH18 634 0 AG30 512 GND GND* - Me) AG29 515 vec voc" - VO AH31 518 vO AK19 637 VO AG28 521 vO AJ18 640s vO AH30 524. CCS! vO AL19 643 VO, GCK2 AJ30 527 VO AK18 646 O (M1) AH29 530 vO AH17 649s GND GND* : VO AJ17 652 i (MO) AH28 533 GND GND* VCC VCC" - 0 AKI7 655 ! 1 (M2) AJ28 534 re) ALI7 658 VO, GCK3 AK29 535 VO AJ16 661 VO (HDC) AH27 538 vO (INTT) AK16 664 vO AK28 544 voc VGC* - vO AS27 544. | GND GND* - vO AL28 547 vO AL16 667 VO (COC) AH26 550 ie) AH15 670, GND GND* - vO AL15 673 uO AK27 553 Te) AJ15 676 vO Ad26 556 GND GND* - ] VO AL27 559s vO AK15 679 VO AH25 562 0 Ad14 682 re) AK26 565. vO AH14 685 ie) AL26 568. COFC AKI4 688 VCC vCC* vO ALI3 691 GND GND* a vO AK13 694 re) AH24 571 voc voce : vO AJ25 574 GND GND* 697 vO AK25 577 vO AJ13 700 vO AJ24 580 | vO AH13 703 vO AH23 583 vO AL12 706 vO AK24 586 vO AK12 709 GND GND* _ | vO AJ12 712 vO AL24 589 vO AK11 715 vO AH22 592 GND GND* vO AU23 595 Te) AH12 718 vO AK23 598 vO AJtt 724 GND GND* - vcc Vcc" - vO AJ22 601 vO AL10 724 0 AK22 604, ~| VO AK10 727 vO AL22 607 v0 AJ10 730 vO AJ24 610 vO AK 733 VCC vcc* - | GND GND* ie) AH20 613 ye) AL8 736 VO AK21 616 vO AH10 739 GND GND" | ie) Alo 742 VO AJ20 619 re) AK8 745 0 AH19 622. +|GND GND* . V0 AK20 625 : VO AJB 748 ~CS VO AJ19 628 VO AHS 751 July 30, 1996 (Version 1.03) 4-129XC4000 Series Field Programmable Gate Arrays | XC4052XL Pad Name BG432 | Bndry Scan [| _XC4052XL Pad Name BG432_ | _Bndry Scan | VO AK7 : 754 WO, FCLK3 ABI | 874 vO ALG 757 lO AAS | B77 ie) Ad7 760 : YE vCC* - | VO AHS 763. ~~; WO (D8) AA2 880 | GND - GND* [vO (CSO) v2 863 VCC Viorel - (GND GND* | vO AK6|SsC766 vO 4 386. VO AL5 769 0 Y3 889 ie) ~ AH te V0 v1 892 | vO AJB 775 0 wi 895 vO AKS 7 C~UFsi wC~~~C~@CYSCSC gg [vO AL4 781 ! vO w3 901 GND GND* - GND GND* vO AH6 784. ~C*<~xWzW vCC* - VO _ AJ5 787) HO we 904 a AK4 790 eee) v2 907 vO AHS 793. = =| 30 v4 910 VO AK 796 vO V3 913 VO, GCK4 Ada 79 ~CliCS'WOSOS~SOSS ut 916 {aN eno ee 019 DONE AH4 GND GND* - vcc vcc* os wo U4 922 PROGRAM AH3 - vO U3 925 (70 (D7) AS2 : 802 VO (D4) Tr ~=0O):tiitt**S /WO, GCK5 AG4 805 vO T2 931 vO AG3 808 voc vcc* : : vO AH2 ea GND* - | V0 ~ AH1 B14 HO (D3) T3 934 Vo AF4 B17 Vo (RS) ~ RT 87 GND GND* - iO R2 940 ie) AF3 820 VO ~ R4 943 VO AG2 823 GND GND* : vO AGI 826 vO R3 946 vO AE4 829 vO P2 949 vO . AE3 8320O re) _ P38 952 vO AF2 835 t<zxLO P4 955 VCC ~ VCC* - vO NI 958 GND GNO* ol N2 961 VO (D6) AFI 838 [vec VCC* : VO AD4 841 GND GND* - vO AD3 844 WO NS 964 | vo AE2 B47 VO N4 967 0 AD2 850 vO M4 970 10 ACA. s ey M2 973 GND ~~ GND* : tO M3 976 vO ACS, 856 WO M4 979 vO 7 ADI 859 "GND GND* - VO Ace, 862 VO (D2) \2 982 vO AB4 865 VO | L3 985 GND GND* : VCC vcc* - | vO AB3 868 VO Ki 988 v0 AB2 | 871 VO, FCLKA K2 | 991 4-130 July 30, 1996 (Version 1.03)$= XILINX XC4052XL Pad Name BG432 Bndry Scan | XC4052XL Pad Name BG432 Bndry Scan | vO K3 994 vO B8 50 vO K4 997, vO AS 53 GND GND* - GND GND* | vO a) 1000. -C*Y| vO Di0 5.OC*S iO J3 1003 VO C9 59 VO J4 1006 vO BO 62 ' VO ~H1 1009. =Y Ve) C10 65 GND GND* - GND GND* - | VO H2 1012 VO B10 68 vO H3 1015 VO AiO 71 | vO H4 1018 Me) Ci 74 vo G2 1021 VO p12 77 vO G3 1024 ere) vcc* vO FI 1027. vO B11 80 GND GND* - 7 vO C12 83 VCC vcC* . GND GND* - VO (D1) G4 1030 re) D13 86 VO (RCLK, RDY/BUSY) F2 1033 vO B12 89 vO F3 1036 0 C13 92 vO _ E1 1039 0 A12 95 vO F4 1042 vO p14 98 vO E2 1045S vO B13 101 GND GND* - GND GND* - re) E3 1048 VCC vcct - VO D1 1051 1/0 (A4) C14 104 VO E4 1054 1/0 (AS) A13 107 WO D2 1057 VO B14 110 1/0 (DO, DIN) C2 1060 0 D15 113 VO, GCK6 (DOUT) D3 1063. Ci, VO (A21) C15 116 CCLK D4 - | VO (A20) B15 119 voc VCG* GND GND* : 6, TDO C4 0 | vO AS 122 GND GND* - vO C16 125 VO (AO, WS) B3 2 VO (A6) Bi6 128 VO, GCK7 (A1) D5 5 VO (A7) A16 131 Te) B4 a) 'GND GND* vO C5 1 VCC Vcc" vO A4 14 VO (A8) Di7 134 vO D 7 0 (A9) Al7 137 GND GND* : - vO C17 140 vO BS 20 /0 B17 143 vO C 23 - GND GND* - VO (CS1, A2) AS 26 VO (A19) C18 146 V0 (A3) D7 29 7 VO (A18) Di8 149 vO B6 32 vO Bis 152 VO AB 35 - vO A19 155 VCC vCC* ae VO (A10) B19 158 GND GND* : VO (A11) C19 161 vO D8 38 ~ vcc Wereu - VO C7 Ai GND GND* : vo B7 Aa vO D19 164 vO Dg 47 vO A20 167 July 30, 1996 (Version 1.03) 4-131XC4000 Series Field Programmabie Gate Arrays | XC4052XL Pad Name BG432 Bndry Scan | Additional No Connect, Vcc & Ground Connections on VO B20 170 BG432 Package vO c20 173 N.C. vec GND V0 B21 176 Ca Al AD vO D20 179 rer 13 GND GND* : ei Ay vO C21 182 Aa AO vO A22 185 63 voc vcc* - Ai8 vO B22 188 vO C22 191 70 B23 194 VO A2d 197 "GND GND* - VO p22 200 | vO C23 203 ie) B24 206 vO C24 209 GND GND* - VO D23 212 vO B25 215 VO A26 218 VO C25 221 VO (A12) p24 224 "VO (A13) B26 227 | GND GND* - | VCC vCC* vO A27 230 re) D25 233 VO C26 236 vO 827 239 vO A28 242 vO D26 245 GND GND* vO C27 248 vO B28 251 VO D27 254 vO B29 257 (VO (A14) C28 260 VO, GCKB (A15) p28 263 [vec VCC" - 4/2/96 Pads labelled GND* are internally bonded to a Ground plane within the associated package. They have no direct connection to any package pin. Pads labelled VCC* are internally bonded to a Vcc plane within the associated package. They have no direct con- nection to any package pin. 3/22/96 4-132 July 30, 1996 (Version 1.03)Package-Specific Pinout Tables 2. XILINX PC84 Package Pinouts : | xcan0se | XC4010E Pin || XC4003E | ycaggs | XC4006E | XC4008E YC aoyor Pin |] xcao03e | YCAOO8E | xcaoose | xca008e Captor P45|| vO v0 v0 10 70 5711 -GND SND ND SND SND P46|| 0 vO vO 0 Me) 52 ll -veo VGC VEG WEG VOC P47|| v0 vO vO Me) vO _| P4ag|l i I P3 || 0 (Aa) | /O(A8) | VO(A8) | VO(A8) | 0 (a8) P49 " 5 > = P4 || vO (A9) | VO (Ag) | VWO(A9) | VO (Ad) | VO (AS) ps0! 110 70 6 70 0 P5 || 0 (A10) | VO(A10) | VO (ATO) | VO (A10) | 10 (ATO) | BEI) 10 10 0 10 0 P6 || VO (A11) | 0 (A11) | VO (ATT) | WO (ATI) | VO (ATI) SGCK3 | SGCK3 | SGCK3 | SGCK3 | SGCK3 P7 |} 70 (A12) | 1/0 (A12) 70 (A12) | 70 (A12) | VO (A12) Peel GND GND GND GND GND P8 || 1/0 (A13) | VO (A13) _ VO (AT3) | VO (A13) 0 (A13) Pal) DONE | DONE DONE | DONE | DONE Pg |[V/O (A14) | VO (A14) 0 (A14) | VO (A14) VO (A14) Psall voc VCC VCC VOC VGC P1ol! 1/0, V0, VO, VO, vO, P5s||_ PRO: PRO: BRO: PRO: PAG: SGCK1 | SGCK1 | SGCK1 | SGCK1 SGCK1 GRAM GRAM | GRAM pai GRAM (A15) (A15) (A15) (A15) (A15) all vee Vee VeG vee VoG P56/1 VO (D7) | /O(D7) | VO(D7) | /O(D7) | VO (07) L P57|| 0, VO, vO, VO, VO, LPt2]| GND GND GND GND GND PGCK3 | PGCK3 | PGCK3 | PGCK3 | PGCK3 | P13 Pant p ook p eek peck pact _P58|| VO (D8) | vO (D6) | VO (D6) | VO (D6) | 1/0 (06) (A16) (A16) (a6) (A16) (at) Ps9/| 0 (Ds) | /O(D5) | /O (D5) | VO (DS) | VO (DS) P14]| VO (A17) | VO (A17) | VO (A17) | VO(A17) | VO(AI7) P60 || VO (CSO) | VO (CSO) | VO (CSO) | VO (CSO) | VO (CSO) P15|| vO, TDI | O,TDI | VO,TDI ; VO, TDI | VO, TDI P61|} VO (D4) | VO(D4) | VO(D4) | VO (D4) | VO (D4) P16|| 70, TCK | 16, TCK | 0, TCK | VO, TCK | 10, TCK Pe2|| VO | vO vo WO vO P17|| O, TMS | VO, TMS 1/0, TMS | 1/0, TMS | 1/0, TMS Pes|| Voc VCC vec vec vec Pia|| vo v0 VO 0 vO P64; GND GND GND GND GND pial v0 vO 73) iO 0 P6s || 70 (03) | O(D3) | O(D3) | VO (D3) | 1/0 (D3) paoll vo 0 0 1) 0 P66 || 0 (RS) | VO(RS) | VO(RS) | vO (AS) | 0 (RS) pa1|| GND GND GND GND GND P67 || VO (D2) ; VO (D2) | vO (D2) | 0 (D2) | VO (D2) ~paall vee VOC VOC VEG VEG pes|| vO 0 0 0 vO paall 0 vO 7) 7) 0 Peg|} YO (D1) | VO (D1) | VO(D1) | VO(D1) | VO (D1) b P70 ||/O (RCLK, |/O (RCLK, |/0 (RCLK, |1/0 (RGLK, | /O (RCLK, Peay] vO VO vO vO vO RDY/ RDY/ RDY/ RDY/ RDY/ posi] 70 vO ie) vO vO Busy) | BUSY) | BUSY) | BUSY) | BUSY) P26 vO | VO vO vo vO P71 Te) vO vO vO vO Pa7|f 0 vO vO vO ie (DO, DIN) | (D0, DIN) | (D0, DIN) | (D0, DIN) | (DO, DIN) p2s|| 1/0 v0 v0 vO vO P72|| VO, VO, vO, VO, /0, P29 VO, vO, V0, VO, vO, SGCK4 SGCK4 SGCK4 SGCK4 | SGCK4 SCGK2 | SCGK2 | SCGK2 | SCGK2 | SCGK2 (DOUT) | (DOUT) | (DOUT) | (DOUT) = (DOUT) | P30 O (M1) O (M1) O (M1) O (M1) O (M1) P73 CCLK CCLK CCLK CCLK CCLK P3t|| GND GND GND GND GND P74|| VCC vec veG vec vec P32 | (MO) 1 (MO) 1 (MO) | (MO) 1 (MO) P75i! O, TOO O, TOO 0, TDO 0, TDO O, TDO P33 VCC VCC VCC VCC VCC P76 GND GND GND |, GND GND | P34 {Tt (M2 1 (M2) 1 (M2) 1 (M2) (M2) P77|| vO vO vO v0 vO = io * x oo (Ao, WS) | (A0, WS) | (AO, WS) | (A0, WS) | (AO, WS) PGCK2 | PGCK2 PGCK2 | PGCK2 | PGCK2 P78}| _ vO, vO, VO, vO, V0, P36 [1/0 (HDC) | VO (HDC) | VO (HDC) | 1/0 (HDC) | 1/0 (HDC) ay a ray ay ay P37 |] 70 (CBG) 1/0 (LDG) | 1/0 (CDC) | 1/0 (LBS) | v0 (LOG) Byall VO 0 v0 70 0 P3s{| v0 VO 0 vO vO (CS1, A2) | (CS1, A2) | (CS1, A2) - (CS1, A2) | (CS1, A2) P39/| 0 vO vO vO Te) P8o|| WO(A3) | O(A3) VO(A3) | VO(A3) | VO(A3) | P40|| VO vO v0 vO vO Pai|| vO(A4a) | VO(A4) VO(A4) | VWO(Aa) | VO (AS) P41 || VO (INIT) | 1/0 (INIT) | VO (INIT) | 1/0 (INIT) | 1/0 (INIT) Pa2|] 0 (A5) | VO(A5) | VO(A5) | VO(A5) | 1/0 (A5) P42|| Vcc vec VCC VCC vec | Pa3|l vO (A6) | VO(A6) VO(A6) VO (A6) | VO (AB) P43|| GND | GND GND GND GND Pa4|| /O(A7) | VO(A7). VO(A7) | WO(A?) | VO(A7) P44|[ 0 /0 vO re) V0 3/28/96 July 30, 1996 (Version 1.03) 4-133XC4000 Series Field Programmable Gate Arrays PQ100 Package Pinouts PQ100 Pin XC4003E XC4005E PQ100 Pin XC4003E XC4005E ne <. Ne nee PI VO (Ata) VO (A14) 554 VOC VEC | P2 VO, SGCK1 (A15) VO, SGCK1 (A415) 355 OGRA BROGHAN . a < | P56 1/0 (D7) vO(07) P57 VO, PGCK3 VO, PGCK3 P5 VO, PGCK1 (A16) VO, PGCK1 (A16) Bea 70 (D8) 70 (06) PG VO (A17) VO (A17) = 16 10 eee pt 1005 P61 VO (C80) VO (G86) PQ vO, TMS vO, TMS I pas 10 10 P10 vO vO Baa 10 10 ~ a O te 64 VO(D4) VO (D4) P13 VO vO Fes vO "0 P14 GND GND P66 vec vee P15 VCC VCC Pe7 GND GND ote 6 5 P68 VO (D3) vO (D3) a7 70 0 P69 VO (RS) VO (RS) P70 Te) vO P18 vO vO [Pr VO (D2) iO (D2) Prg "0 4 vo ' P72 vO ~ vO ~ / 5 P73 0 (D1) VO (D1) P74 /0 (RCLK, VO (RCLK, P22 vO vO RDY/BUSY) RDY/BUSY) p23 vO vO P75 VO (DO, DIN) 1/0 (DO, DIN} P24 VO, SCGK2 VO, SCGK2 P76 VO, SGCK4 (DOUT) | VO, SGCK4 (DOUT) P25 O (M1) 0 (M1) P77 CCLK CCLK P26 GND GND P78 Were) ~~ vcc ~ P27 i (MO) | (MO) P79 0, TDO | 0,100. | P28 VCC Vcc { P80 GND. GND P29 | (M2) | (M2) : P81 VO (AO, WS) /O (AO, WS) L P30 VO, PGCK2 VO, PGCK2 P82 VO, PGCK4 (A1) VO, PGCK4(A1) | P31 VO (HDC) VO (HDC) P83 0 (C81, A2) /0 (CS1, A2) P32 vo vO P84 VO (A3) VO (A3) P33 VO (LDC) VO (LDC) P85 1/0 (Aa) VO (Ad) P34 vO vO P86 1/0 (A5) W/O (AS) P35 VO VO P87 VO VO P36 VO VO P88 VO vO P37 VO vo P8e VO(A6) VO (A6) _ P38 vO vO | P90 VO (A7) VO (A7) P39 \/O (INIT) vO (INIT) P94 GND GND P40 VCC vec p92 vce VCC pat GND GND P93 W/O (AB) 1/0 (AB) P42 vO vO P94 V/O (A9) /O (A9) P43 vO VO P95 VO Vo P44 0 VO P96 vO Vo P45 vO he) P97 VO (A10) VO (A10) P46 vO vO P98 VO (A11) VO (A11) P47 vo vO P99 VO (A12) VO (A12) P48 vO vO P100 1/0 (A13) VO (A13) P4g vO vO P50 vO vO 2/28/96 | PSI VO, SGCK3 VO, SGCK3 4-134 July 30, 1996 (Version 1.03)$= XILINX VQ100 Package Pinouts VQ100 Pin XC4003E VQ100 Pin XC4003E P52 PROGRAM Pi GND P53 VO (D7) P2 0, PGCK? (A16) P54 VO, PGCK3 7 P3 0 (A17) PSS VO (D6) P4 VO, TDI - ; i 5 7 PS VO, TCK P6 0, TMS P58 0 (C80) P7 10 P59 To) PB 0 P60 ie) P9 re) P61 VO (D4) P62 vO P10 vO Pt GND P6S vcC | P12 VCC P64 GND P13 VO P6S 1/0 (D3) P14 V0 P66 VO (RS) P15 vO P67 VO P16 vO P68 VO (D2) P17 VO P69 vO P18 vO P70 0 (D1) P19 vO P74 VO (RELK, RDY/BUSY) P20 vO P72 1/0 (DO, BIN) P21 VO, SCGK2 P73 VO, SGCK4 (DOUT) P74 CCLK P22 O (M1) P75 vcc i ahs P76 O, TDO P24 1 (MO) oF au = wai P78 i/O (AO, WS) P27 VO, PGCK2 P79 VO, PGCK4 (At) P80 VO (CS1, A2) 2 VO (H = ie a P81 70 (A3) P82 VO (A4) P30 VO (CBC) P3i VO P83 i/O (A5) P32 V0 P84 VO P33 vO P85 vo P34 vO P86 VO (A6) P35 VO P87 0 (A7) P36 VO (INIT Pas GND P37 oo P89 voc P38 GND P90 W/O (A8) | P39 VO P91 VO (AQ) P40 vO P92 /0 Pat vO P93 0 P42 vO P94 VO (A10) P43 vO P95 vO (A11) P44 VO P96 VO (A12) P45 v0 P97 VO (A13) P46 vO P98 VO (A14) : P47 70 Pg VO, SGCK1 (A15) P100 vec P48 0, SGCK3 P49 GND 2/28/96 P50 DONE | P51 vec July 30, 1996 (Version 1.03) 4-135XC4000 Series Field Programmable Gate Arrays PG120 Package Pinouts PG120 Pin XC4003E PG120 Pin XC4003E 12 vO Ni3 0, PGCK3 J N.C. Ni2 N.C. J3 N.C. NYT 70 2 /0 (Ad) N10 V0 (680) i vO NS 0 H13 10 Na 70 H12 0 N7 0 (D3) AM vO NG 0 (RS) HS vO NE 16 He VO (A6) Na 70 At 0 (A7) N3 V0 (RGLK, RDY/BUSY) G13 vO N2 V0 (DO, DIN) Gite VCC Ni VO, PGCK4 (Aj) Git GND Mi3 V0 Ga VCC Mi2 PROGRAM G2 GND Mt 70 (D7) G1 YO (A8) Mid 70 (66) F13 VO (INIT) M9 V0 (DS) Fl2 VO MB VO (D4) FY vO 7 WEG F3 70 (A10) Ms 7 F2 0 ME TeXGH A 70 (A9) via ce E13 10 M3 0, SGCK4 (DOUT) E12 vO MD -1D0 E11 N.C. Ma Ne E3 NG. Lia 0 Ee N.C. L12 0, SGCK3 EI vO Li DONE 13 vO 30 WEG Di2 0 5 Se D1 VGG 3 1G D3 VO, SGCK1 (A15) = SND D2 0 (A13) L6 70 (D2) pt VO (A11) rs Te C13 0 (CDC) 3 SCL C12 0, PGCK2 5 vee Cn (Mo) [2 1/0 (AO, WS) C10 GND Li VO (A3) cs vO Ki3 V0 cs vO aa NE C7 VCC Kit GND C6 vO a GND C5 0, Tol Ko 0 (C81, A2) cA GND Ki V0 (AS) ca VOC 3 76 C2 i/0 (A14) Ct 0 (Ai2) 4-136 July 30, 1996 (Version 1.03)$= XILINX PG120 Pin XC4003E PG120 Pin XC4003E B13 N.C. . A10 V/O Bi2 1 (M2) Fg vO B1i O (M1) rn: v0 B10 N.C. {| A7 vO BO vO A6 vos B8 Te) A5 - VO B7 | GND A4 ie) | B ie) A3 N.C. B5 vO, TMS A2 N.C. B4 vO, TCK Ad N.C. B3 VO (A17) 3/13/96 B2 VO, PGCK1 (A16) Bi N.C. | Note: Viewed from the bottom side, the package pins start A13 /O (HDC) at the top row and go from the left edge to the right edge. Al2 VO,SCGK2..ssdsx Viewed from the top side, the pins start at the top row and a Att 10 go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-137XC4000 Series Field Programmable Gate Arrays TQ144 Package Pinouts TQ144 Pin XC4005E XC4006E TQ144 Pin XC4005E | _XC4006E Pay vO vO or SND SND P48 vO 0 P2 VO, PGCKi (A16)_|_/0, PGCKi (A16) Pag vO vO PS 70 (A17) 0 (Ai7) |___PS0 vO vO 34 10 10 P5t v0 0 P5 v0 v0 P92 vO _ VO D 10, TDI iti P53 VO (INIT) 70 (INIT) P7 V0, TCK 0, TCK Pod VoC VCC = SND GND P55 GND GND 59 0 70 P56 V0 0 P10 vO v0 PS? vO YO Pit V0, TMS V0, TMS P58 vO vO Pi2 v0 vO P59 vO vO P13 V0 V0 P60 vO vO P14 vO v0 Pot vO vO P15 70 V0 P62 vO vO P16 V0 V0 P63 vo vO Pi7 GND GND Ped GND GND Pis vcG voc P65 vo vO Pi9 v0 70 P66 vo vO P20 v0 70 P67 vO vO Pat vO 70 P68 vO vO P22 0 v0 P69 vO v0 555 70 70 P70 VO, SGCK3 0, SGCK3 P24 0 V0 prt GND GND BOB 0 70 P72 DONE DONE P26 V0 0 P73 VGC VOC P07 GND GND P74 PROGRAM PROGRAM = 70 0 P75 1/0 (D7) VO (D7) 359 70 10 P76 V0, PGCK3 0, PGCK3 P30 70 V0 P77 vO vO Pat 0 VO P78 vO vO a 70 10 P79 70 (D6) 0 (06) P33 0, SCGK2 V0, SCGK2 P80 vO vO Baa Sa) SMI P81 GND GND P35 GND GND P82 vO v0 P36 (MO) (MO) P83 vO vO 357 VEC VEC Pad 70 (D5) VO (08) = a a P85 70 (C50) 0 (CSO) P39 0, PGCK2 0, PGCK2 P86 vO vO P40 VO (HDC) 70 (HDC) P87 v0 vO Pal 0 0 P8s 70 (04) 70 (04) P42 70 0 P89 vO vo P43 V0 V0 P90 VOC VCC P44 V0 (CDC) 0 (LDC) Pot GND GND P45 GND GND P92 VO (D3) vO (DS) on 6 0 P93 0 (RS) 70 (RS) Poa 0 V0 4-138 July 30, 1996 (Version 1.03)$< XILINX | 7Q144 Pin XC4005E XC4006E TQ144 Pin XC4005E XC4006E "POS vO vO P142 0 (A14) VO (A14) P96 VO (D2) VO (D2) P143 VO, SGCK1 (A15) | 1/0, SGCK1 (A15) P97 VO vO P144 VCC VCC P98 vO V0 2/98/96 P99 V0 V0 P100 GND GND Note: Shaded pins should be taken into account when P101 VO (D1) VO (D1) designing PC boards, in case of future replacement by dif- P102 VO (RCLK, VO (RCLK, ferent devices. RDY/BUSY) RDY/BUSY) P103 vO VO | P104 VO vO ' P4105 /O (DO, DIN) /O (DO, DIN) P106 _||I/0, SGCK4 (DOUT) | 1/0, SGCK4 (DOUT) | | P107 CCLK CCLK P108 VCC VCC | P109 0, TDO 0,1DO P110 GND GND P111 /O (AO, WS) VO (A0,WS) P12 0, PGCK4 (A1) | 0, PGCK4 (At) | Pi13 0 V0 | P114 Te) VO P115 0 (C81, A2) 0 (CS1, A2) P116 VO (A3) VO (A3) | P118 GND GND P119 vO V0 | P120 vO V0 Pi21 VO (A4) 1/0 (A4) P122 1/0 (A5) VO (AS) P123 vO vO P124 vO VO P125 /0 (A6) VO(A6) P126 /0 (A7) VO (A7) P127 GND GND P128 VCC VCC P129 VO (A8) VO(A8) P130 VO (A9) VO(A9) P131 vO ie) P132 VO vO P133 VO (A10) /0 (A10) / ~P134 VO (A11) VO (A11) | P1835 Vo VO P136 VO VO P137 GND GND P138 VO (A12) VO (A12) P139 VO (A13) 70 (A13) | / P4140 0 vO ; P41 vO VO | July 30, 1996 (Version 1.03) 4-139XC4000 Series Field Programmable Gate Arrays PG156 Package Pinouts PG156 Pin XC4005E_ | ~=XC4006E PG156 Pin XC4005E XC4006E_ Pia GNO GND Ti 0, TDO 0, TDO P15 vO fe) T2 0, SGCK4 (DOUT)|1/0, SGCK4 (DOUT) P16 vO vo q3 VO (D1) VO (D1) N1 VO (A3) 0 (A3) Ta 10 70 N2 V0 v0 TS 70 70 N3 GND GND 76 76 0 N14 V0 /0 7 v0 (FB) V0 (RS) NS OO T8 1/0 (D3) VO (D3) lee ne ; T9 10 v0 ab 8 T10 10 (D5) /0 (D5) Ce ee ee 0 0 M3 v0 | v0 ~ M14 v0 v0 vO vO ae ov T14 1/0 (D8) 1/0 (D6) M16 vO vO T15 0, PGCKS V0, PGCK3 | ul vO vO T16 vO (D7) voy | vO vO Ai /0 (AO, WS) 70 (AO, WS) is GND GND Re CCLK CCLK L14 GND GND a3 10 i0 L15 V0 | 0 Ra 70 iio Li6 10 0 Kj 0 10 a6 10 6 : K2 10 (AS) 170 (AS) a7 v0 6 3 K3 70 (Ad) 10 (Ad) a VEC VOC K14 16 0 Ro 1/0 (D4) 0 (64) KIS vo vo RIO vO vO K16 vO vO Att V0 vO 4 vO vO J2 / (A6) i/0 (A6) o 0 J3 0 (A7) 70 (A7) R14 PROGRAM PROGRAM 14 GND GND Ais DONE | DONE | J18 VO _ V0 R16 0, SGCK3 0, SGCK3 J16 vO vO Pi 10 (CSI, A2) /0 (CST, A2) Ht VO (A8) VO (A8) P2 0, PGCK4 (Al) W/O, PGCK4 (Al) He GND GND 53 VOC VoG Ha vec vc P4 i/O (DO, DIN) /0 (DO, DIN) H14 VCC | VCC | BE 70 (ROLE 70 (HCE, His VO (INIT) VO (INIT) RDY/BUSY) RDY/BUSY) H16 vO vO 6 GND GND a 1/0 (A9) 1/0 (A) P7 /0 (D2) /0 (02) |_ G2 VO VO P8 GND GND G3 VO VO P9 vO VO G14 VO 0 P10 V/0 (CSO) /0 (C50) Gis VO vO P11 GND GND G16 VO vO ! P12 VO Ve) F1 VO (A10) /O (A10) P13 vec vec F2 1/0 (A11) /O (A11) F3 GND GND 4-140 July 30, 1996 (Version 1.03)$= XILINX | PG156 Pin XC4005E XC4006E F14 GND GND | FAS 0 vO Fi6 vO vO E1 VO vO E2 vO V0 E3 VO (A12) VO (A12) ! E14 iO vO VO 0 VO (HDC) VO (HDC) VO vO VO (A13) V/O (A13) vO vO VGC VCG GND GND vO 0 GND GND vO vO GND GND 0 vO C10 0 0 Cit GND GND C12 vO vO C13 GND GND C14 VCC Were | 15 vO 0 | =6C16 VO (EDC) /0 (LBC) Bi i/O (A14) VO{A14) B2 1/0, SGCK1 (A15) | 1/0, SGCK1 (A15) B3 0, PGCK1 (A16) VO, PGCK1 (A16) | / B4 vO, TOI 1/0, TDI [BS ie) 0 B6 0 /0 BT vO vO | BS VCC VCC / Bg vO V0 i: - BIO i) vO Bit V0 vO B12 vO vO B13 VO vO B14 VO, SCGK2 VO, SCGK2 B15 + (M2) 1 (M2) B16 vO, PGCK2 vO, PGCK2 Al VO (A17) 10 (A17) PG156 Pin A2 A3 A5 AG A7 A8 AQ Ai0 Ail Al3 Al4 A15 A16 2/28/96 XC4005E VO VO, TCK /O, TMS VO VO VO VO vO ie) ie) 0 0 (M1) | (MO) XC4006E vO VO, TCK VO, TMS 8) vO vO vo vo vO vO VO O (M1) 1 (MO) Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by dif- ferent devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-144XC4000 Series Field Programmable Gate Arrays PQ160 Package Pinouts PQ a 160 XC4008E | XC4006E | xC4008E | xc4010E | xC4013E ! 160 XC4005E | XC4006E | xC4008E | XC4010E | xC4013E Paz Il vo v0 0 3) 70] Pr oR | Roane) BEDE 10 vo Te Toe P2 VO, V0, vO, V0, VO, : a ie PGCKi | PGCK1 | PGCK1 | PGCKi | PGCK1 e ee (A16) (A186) (A16) (A16) (A16) P51 || GND GND GND GND GND P3 [fv (A17) | WO (A17) | VO (AT7) | 10 (A17) | 0 (A17) P52 {| 0 vO vO v0 vO Pa To) 0 0 /0 V0 P53 || 0 vO vO v0 VO PS 10 V0 VO V0 V0 p54 [| v0 V0 vO vO vO P || vo, To! | vO, TDI | VO, TDI | vO, TDI | WO, TDI P55 || VO 0 /0 VO VO P7 |[vO, TCK | 0, TCK | 0, TCK | 0, TCK | 1/0, TCK P56 || vO V0 V0 VO vO 6 | NG So Me P57 Te) vo ie) VO vO ea 7 28 aay ae Psa || 0 vO 0 V0 0 P10 || GND GND GND GND | GND P59 |[1/0 (INIT) | VO (INT) | /O (INTT) | 1/0 (INTT) | 1/0 (INIT) Pit vO vo WO vO | vO P60 || vcc vc Were) VCC vec Pi2 (| vO VO vO V0 VO Pet || GND GND GND GND GND P13 ||/O, TMS | 1/0, TMS | VO, TMS | VO, TMS VO, TMS P2 || vO vO vO vO V0 Pi4 (| vO 0 VO Ke) vO Pe3 || vo 0 10 v0 V0 P1S || v0 v0 vO yO v0 Pea || VO v0 0 vO VO P16 || v0 v0 v0 vO VO Pes || vo vO vO vO vO P17 || Wo vO vO v0 vO Pee || vo /0 v0 0 /0 P18 || 1/0 vO V0 /0 v0 P67 || 0 10 v0 vO V0 Pi9 || GND GND GND GND GND Pes || 1/0 v0 me) vO /0 P20 || vec vec vec vec VCC Peo || 0 /0 v0 TK) 0 P21 10 vO vO v0 Te) P70 || GND GND GND GND GND P22 VO ie) vO vO vO : CG p23 |! vO /0 v0 vO vo | p24 ll 0 /0 10 V0 Te) P73 || Vo vO V0 vO vO pas |] V0 /0 V0 0 V0 P74 || vo v0 70 0 VO P26 || 0 0 V0 70 V0 P75 || v0 vO vO 0 v0 P27 || v0 V0 0 v0 V0 P76 || 1/0 vO v0 v0 V0 P28 vO /0 V0 V0 0 P77 || Vo vO vO vO vO P29 || GND GND GND GND GND P7s || VO, vO, vO, 0, V0, leer =e ers a SGCK3 | SGCK3 | SGCK3 | SGCK3 | SGCK3 ae | P79 || GND GND GND GND GND p32 if vo 1 vo | vo | wo | vo | _P80|| DONE | DONE | DONE | DONE | DONE P33 |{ vo vO V0 vO vO _ Pet = = = oe = Pe2 : PAO- : PRO- PRO- ee * . 5 a o GRAM | GRAM | GRAM | GRAM | GAAM B36 0 0 70 7" 0 pas || vO (D7) | VO(D7) | vO(Dy) | VO(7) | 0 7) pea || 0, v0, V0, V0, 0, P37 seek seeke steno seek 5 eke PGCK3 | PGCK3 | PGCK3 | PGCK3 | PGCK3 past o (iy OW) Oo Mi) OW) OM P85 0 0 VO v0 VO >39 tt GND SND SND an GND Pas || VO /0 JO Te) VO pao tty (way Tawa) my oy) Pa7 || VO (De) | VO (D6) | VO (De) | 1/0 (D6) | 10 (D6) Pas || VO 0 vO HO vO Pat || vec vec Vcc vec VCC ERs Paz || (m2). 1(M2)*<$(M2)~1 (M2) | +1 (M2) mt ras pack Pack packs packs packs P91 || GND GND GND GND GND P44 ||/O (HDC) VO (HDC) 1/0 (HDG) | 1/0 (HDC) | 1/0 (HDC) P92 || vO vO vo vo vo pas Il 0 10 0 0 0 P93 | v0 V0 V0 10 v0 pae Il vo 0. vO 0 0 Pgq || 1/0 (bs) | WO(D5) | VO(Ds) | VO(DS) | 0 (D5) P96 |//0 (So) | VO (C80) | 0 (C80) | 0 (CS0) | 0 (CSO) 4-142 July 30, 1996 (Version 1.03)$= XILINX PQ P | : 180 XC4005E | XC4006E | XC4008E | XC4010E | XC4013E ES XC4005E | XC4006E | xca008E | XC4010E xcaorae | in ! In P96 vO vO 7) vO vO P140l] VO (A7) | VO(A7) | VO(A7) | VO(A7) | VO (A7) P97 vO VO vO vO vO Pi41/[ GND GND GND GND GND ; Pgs || 0 (D4) | YO (D4) | O(D4) | 0 (D4) | VO (D4) P142|[ VCC VGC VCC Vcc VCC P99 vO vO vO vO vO P143]| /O (aa) | O(a) | VO (a8) | 1/0 (Aa) | 1/0 (A8) Pioo|| vec VCC vec vcc voc P144|| VO (Ad) | WO(A9) | OAS) | VO(A9) | 1/0 (a9) Pio1|| GND GND GNO GND GND P145|| 0 vO vO vo. WO P102|| 0 (D3) | vO (D3) | vO (D3) | 10 (D3) vO (D3) | Pi46|| vO vO VO vO vO P103|| vO (RS) | VO (RS) | /O (AS) | VO(RS) VO (RS) P1471] /O (A10) | 1/0 (A10) | 1/0 (A10) | /O (A10) | 1/0 (A10) P104|| 0 vO VO vO: WO P148// VO (A11) | VO (A11) | VO (A11) | VO (Att) | 70 (A117) Pi05|| vO vO vO vO. | VO (P14g|[ VO vO ie) VO vO P106|| 0 (D2) | /O (D2) | VO (D2) | VO (D2) | VO (D2) ;Piso0|/ vo ie) vO VO vO Pi07|| vo re) vO vO vo | P151|[ GND GND GND GND GND | Pios|[" vo "0 vo 0 vo | Aibe ae if Pi09/} VO vo. vo | Ww vO PIs a a P110|| GND GND | GND GND GND P154|| 1/0 (A12) | 1/0 (A12) | 1/0 (A12) | YO (A12) | 1/0 (A12) | P155[] 1/0 (A13) | VO (A13) | 70 (A13) | 1/0 (A13) | VO (A13) . | |Pisel| v0 vO vO 0 v0 vO (D1) | VO(D1) | vO(D1) | vO(D1) | VO (D1) P157|| VO VO vO vw | VO P14 /ORCTK, VO (ACLK, |VO (ACLK, vO(RCTK, VO (RCLK, P158 (| 1/0 (A14) | VO (A14) | 1/0 (A14) | 170 (14) | 70 (014) ADY ADY/ ADY/ ADY/ DY/ |_| susy) | susy) | susy) | susy) | Busy) Tl) cack | sack: | sack: | sack | sacks P115|| VO vO vO vO vO (At5) (A15) (A15) (A15) (A15) Pii6|{ v0 vO VO vO vO [Piso]] vec | vec | vec | vec | vec P117|| vO vO vo" vO vO 9/28/96 (D0, DIN) . (DO, DIN) ; (DO, DIN) | (DO, DIN) | (DO, DIN) | T pus sucks sacks sucka sack sucka Note: Shaded pins should be taken into account when (DOUT) | (DOUT) | (DOUT) | (DOUT) | (DOUT) designing PC boards, in case of future replacement by dif- P119}| CCLK CCLK CCLK CCLK CCLK ferent devices. Pi20|| voc VCC VCC vcc VCC P121|| 0, TDO | O,TDO | O,TDO | O,TDO | O,TDO Pi22|| GND GND GND GND GND P123]| vO Te) vo vO vO (AO, WS) | (Ao, WS) | (AO, WS) | (AO, WS) | (AO, WS) Pi24|| 1/0, VO, 0, vo, | WO, PGCK4 | PGCK4 | PGCK4 | PGCK4 | PGCK4 | (At) = (At) (At) (Al) | (Al) P125 vo |; WO vo vO vO /P126|] 0 vO vO vO vO Pi27|| oO vO vO vO vO (CS1, A2) | (CS1, A2) | (CS1, A2) | (CS1, Az) | (CS1, A2) vO (A3) | VO (A3) | VO (a3) | 10 (A3) | 1/0 (a3) GND GND GND GND GND vO vO vO vO vO vO vO VO vO vO | VO (A4) | VO (Aa) | WO (AA) | V0 (AA) | VO(AA) | VO (A5) VO (A5) VO(A5) 0. (A5) | 1/0 (AS) P1361 NC 3 O iO. . P137|| vo vO vO vO vO Tpizel] oO vO vO vO iO P139|[ vO (a6) | VO(A6) | VO(A6) | VO(A6) | VO (AG) July 30, 1996 (Version 1.03) 4-143XC4000 Series Field Programmable Gate Arrays TQ176 Package Pinouts TQ176 Pin XC4010L TQ176 Pin XC4010L pay uO, PGCK2 > SND P48 0 (HDC) Pa 0, PGCK1 (A16) pag vO P3 V0 (A17) P50 VO Pa V0 PS! VO = 0 P52 0 (LDC) P6 VO, TDI P53 VO P7 V0, TCK P54 vO PE 70 P55 GND 56 70 P56 0 P10 SND P57 v0 1 O P58 v0 a 70 P59 : 0 P13 V0, TMS P60 vO Pid 0 P61 0 P15 v0 P62 vO P16 V0 Pes vO P17 vo P64 vO Bia 10 P65 1/0 (INIT) P19 v0 P66 2 vec P20 vO P67 GND P2i GND Pes vO P22 vec P69 vO P23 0 P70 vO P24 0 Pr vO | P25 vO P72 vO 306 10 P73 70 P27 0 p74 vO P28 vO P75 vo P29 0 P76 vO P30 V0 P77 vO P31 VO P78 GND P32 VO P79 _ vO = ND P80 - vO = 6 Pai v0 D3E iio Pa2 v0 P36 0 P83 0 337 70 PB4 70 533 6 P85 v0 P30 70 P86 0, SGCK3 P87 GND Pao vo Pas DONE Pai 0, SCGK2 ae vo P42 O (M1) . 545 GND P90 PROGRAM oad (M0) P91 VO (D7) P45 voc nes a P46 (M2) a a 4-144 July 30, 1996 (Version 1.03)$< XILINX TQ176 Pin XC4010L TQ176 Pin XC4010L P95 VO (D6) P143 GND P96 VO P144 VO P97 vO P145 0 P98 vO P146 VO (A4) P99 GND P147 1/0 (A5) P100 vO P148 vO | P1014 vO po P149 Te) P1402 VO (D5) _ P1450 vo | P103 0 (CSO) P151 vO a] P104 vO | P152 vO(As)tst~~=isY P105 vO - | P153 VO (A7) P106 vO P154 GND P107 vO P155 VCG P108 VO (D4) P156 VO (A8) P109 vO P157 1/0 (A9) P110 vec P158 VO Pi11 GND | P159 vO P112 YO (D3) [ P160 a) P113 vO (RS) P161 vO P114 vO P162 VO (A10) | P115 vO P163 VO (A11) ] P116 vo P164 vO P117 vO P165 VO [ P118 VO (D2) P166 GND P119 ie) P167 0 [ P120 vO - P168 vO P121 0 P7169 vO P122 GND P170 VO (A12) P123 VO Pi71 VO (A13) Pi24 vO | P172 vo | P125 0 (D1) P173 vO Pi26 VO (RACLK, RDY/BUSY) P4174 VO (A14) P127 0 P175 VO, SGCK1 (A15) P128 vo P176 VCC P129 1/0 (DO, DIN) 3/15/96 P130 0, SGCK4 (DOUT) P1341 CCLK P132 VCC P133 O, TDO P134 GND __ PG191 Package Pinouts (see PG223) = \ o oka in 1) The PGt 91 package pinout has been combined with the : PG223 in a single table, because of their physical compat- P1397 VO ibility. The PG191 has the same dimensions as the PG223, P138 vO but has 32 fewer pins on the inner ring. P139 VO (CS1, A2) P140 VO (A3) i P141 vO P142 vO July 30, 1996 (Version 1.03) 4-145XC4000 Series Field Programmable Gate Arrays PQ208, HQ208 Package Pinouts PQ Pin PI P2 P3 P4 P5 P6 P7 P8 Pg xc 4005 | xc 4006 xc 4008 xc 4010 E/L N.C. GND xc xc 4013 | 4020 E/L E N.C. | NC. GND | GND N.C. | N.C. | N.C. | NC. | NC. vo, | VO, | vo, | vO, | WO, 1]PGCK1 PGCK1| PGCK1|PGCK1|PGCK1 (A16) | (A16) > (A16) | (A16)| (A16) | (A168) vo | WoO vo | Wo | WO | Ww (A17) | (A17) | (A17) | (A17) | (A17) | (A17) vO VO OQ VO vO Vo vo vO vO @) VO vO vO vO , TDIHVO, TORO, TDL /O, TIVO, TDI}O, TDIVO, TDI vo, vO, vO, VO, VO, vO, VO, TCK | TCK | TCK ; TCK | TCK | TCK | TCK XC 4028 EX/XL NLC. GND N.C. V0, GCK1 (A16) VO (At7) E/L E E N.C. GND N.C. VO, N.C. GND N.C. GND GND | GND | GND vO vO vO GND ; GND | GND ie) VO Vo, FCLK1 vO | vO, : TMS VO vO VO, TMS VO vO VO, TS vO vO VO, TMS vo vO vO, TS vo vO VO, TMS VO vo vo vO vO vO vO vO vO VO vO GND | GND | GND vec ; vec | vcc VO vO vO vO vo vO vO vo vO vO vO vO vO vO ie) vO vO vO GND VCC vO vo vO vO vO vO VO VO GND vec vO vO vO vO VO vO VO VO GND voc vO vO vO vO V0 V0 VO VO GND vec VO VO VO V0 vo vO vo vO vo vo vo vO vO vO ie) vO vO vO vO vO vO VO vO vO vO vO VO 0, | FCLK2 GND | GND | GND vO GND | GND | GND | GND IPQ xc | xc xc | xc XC: xc | xc | 208 || 4005 | 4006 | 4008 | 4010 4013 | 4020 | 4028 Pin || E/L E E E/L BEML E EXKL P45 || /O | WO 0 vO 0 ie) ie) P46 || oO | VO vO VO ie) vO vO P47 |] vo, | VO, | vo, | vo, | vO, | vO, | VO, ISGCK2| SGCK2| SGCK2| SGCK2/ SGCK2/SGCK2| GCK2 P48 |/O (M1) (M1) | (M1) | (M1)] (M1)! O (M1) | 0 (M1) P49 || GND | GND | GND | GND | GND | GND | GND P50 || 1 (Mo) | 1(Mo) | 1 (Moy | 1 (Moy | 1 (Mo) | 1 (MO) | 1 (Mo) Psi |[ NC ONC. | NC. NC. | NC. | NC. | NC. P52 || N.C. NC. | NC. | NC. [ NC. | NC. | NG. | P53 [[ N.C. NC. > NC. NC. | NC. | NC | NG. P54 ][Nnc. [Nc NC NC. | NC. | NC. | NC. P55 || vec | VCC. vCC. vcc . vcc | vcc | vec P56 | # (M2) | 1 (M2). 1(M2). 1(M2) | 1 (M2) | 1 (M2) | + (M2) P57 [| vo, | VO, | VO, vO, VO, | VO, | 1, PGCK2 | PGCK2|PGCK2' PGCK2 PGCK2'PGCK2| GCK3 p58 i] VO vO vO | VO VO vo | Vo (HDC) | (HDC) | (HDC) | (HDC) | (HDC) | (HDC) | (HDC) P59 || VO vO vO vO | VO vo | VO P60 || VO vO vO vO VO vO VO P61 || vO re) 1/0 vO vO VO |! VO P62 |} VO |; VO | WO, WO, WO VO VO : (CBC) | (CBG) | (Hc) | (CBC) | (CG) | (BC). (DC) p67 || GND | GND GND | GND GND Pes || 0 vO v0 vO VO Peg || 0 vO vO vO ie) P70 || VO vO vO ie) VO P71 P72 Pz | P74 P75 || W/O vO vO vO vO vO VO P76 || vo 0 vO vO vO vO VO P77 || WO; WO | WO WO | WO | WO) VO (INT) | (NFT) | GINFT) NTT) | (NIT) | (NTT) | NTT) P7g || vcc | vec [| vec VCC | vcc | vcc vcC P79 |[GND | GND | GND) GND | GND | GND. GND - Peo || vO vO vO vO Ve) VO iO Psi || v0 vO vO: vO vO vO ie) Ps2 || VO vO vO: vO vO vO vO P83 || vO vO re) vO vO vO WO pea NO ea } . p86 || 1/0 vO vO vO vO vO | WO P87 || 0 vO vO vO ie) vO vO pss || 0 VO vO vO re) VO vO peg || 0 vO vO VO VO 0 vO P90 || GND | GND | GND. GND | GND | GND | GND Poi [We [NG TNC [vO | Wo vo | vo | 4-146 July 30, 1996 (Version 1.03)$< XILINX Pa || xc | xc | xc | xc | xc | xc | xe PQ || xc | xc | xc | xc xc xe | xc | 208 || 4005 | 4006 | 4008 | 4010 | 4013 | 4020 | 4028 208 || 4005 | 4006 | 4008 | 4010 4013 | 4020 4028 Pin || BL | E | BL | EL E | EXXL Pin || EAL E E | = a ioe Ne P138]}/O (D2)|I/O (D2)|VO (D2)/1/0 (D2)]/O (D2)II/O (D2)/1/0 (D2) a Pi3zq/} vO vo | vo | vo | vo | wo | VO Pe Ne) 7 ee Pi4o|/ vo | vO WoO Vo | vO}; VO | P95 || vo vO vO vo vO ie) VO P141|| VO vO ie) vO vo | vo | vO, | Pgs || vo | vo | vo | vo | vo | wo; WoO _ | FCLK4 P97 VO VO vO VO VO vO Te) P1421] GND | GND GND | GND | GND | GND ND pga || WO | vO | vO | WO | vO | VO | Wo | Peg || vo | vo | WO | Ww | vO | vO | Piog|/ vO, v0, | vO, | vO, | vO, | WO, | VO, : ISGCK3|SGCK3:_ SGCK3' SGCK3| SGCK3|SGCK3! GCK4 i4el| NE : Pioi|[ GND | GND | GND GND | GND | GND | GND P147/|/O (D1)|/O (D1)'VO (D1)|VO (D1)|VO (D1)IVO (D1)|/0 (D1) Pozi N.C. | NC. | NC > NG. NC NC. | NC. P148 aloe vo | WO, VO lo | vO | vO P103||DONE | DONE | DONE | DONE | DONE , DONE DONE Roy) | apYy | Roy) | ROY, oyr Ap | RBY) Prodl| NC. | NC. | NC. | NC ONC | NG NC. BUSY) | BUSY) | BUSY) | BUSY) | BUSY) | BUSY) BUSY) Pr06l| Vo | VoC | VOC | VCO | VCC | VCC | VCC | Piso] VO | vO | VO | 1 | WO |) WO [Vo | Prov} NC. | NC | NC. | NC) NC UNC | NC | ptsill vo | vo | vo | vO) vO T vO | vO P108|| PRO- | PRO- | PRO- | PRO- | PRO- | PRO- | PRO- (DO, | (DO, | (DO, | (Do, ; (BO, | (Do (DO, GRAM GRAM GRAM | GRAM | GRAM | GRAM | GRAM DIN) DIN) | DIN) | DIN) | DIN) | DIN) | DIN) P109|1/0 (D7),1/0 (D7).1/0 (D7)}:0 (D7)//0 (D7)|/0 (D7)\/O (D7), ~s(P1s2|[ 0, | vO, Wo, | WO, | VO, | vo, | V0, P110|| 1/0, VO, vO, Vo, vO, vO, VO, SGCK |SGCK4/|SGCK4:SGCK4 SGCK4|SGCK4| GCK6 PGCK3/PGCK3|PGCK3/PGCK3 PGCK3 PGCK3! GCK5 DOUT} | (DOUT)|(DOUT) (BOUT), (DOUT) (DOUT) (DOUT)| Pitil| vo VO vO vO Ne) vO VO | P153]| CCLK | CCLK | CCLK | CCLK | CCLK . CCLK | CCLK Pit2i| vo | vo vo | vO vo; vO VO. Pis4i| VCC | vec | vec | voc | vec | vec | voc P113]1/0 (D6) /i/0 (D6)| I/O (D6)|I/0 (D6)|/0 (D6)|1/O (D6)|/0 (D6) PISS] N.C. | NC. | NC. | NC. | NC. | NC. NC. P114/| vO vO vO vO VO Tre) ie) jPIS6)] N.C. NC. | NC. | NC. | NC. | NC | NC pre a Pis7]] N.C. | NC. NC. | NC. | NC. | ONC. | ONC. [P18 NC.) NC. NC. | NC, NC.) NC. NC. [P159|0, TOO:0, TDO.0, TDO/O, TDO/O, TDO!O, TDO/O, TDO Tyo Tv | lo 'P 160 GND GND GND GND | GND | GND | GND GN GND | GND | GND iP161|1 i/O vO vO vO vo vo vO WO WO WO WO 0, | | Ws) WS) | WS) WS) WS) WS) WS) ne we i era TOTO) TOIT ee eee ce -P122)/O (D5)/1/0 (D5))1/0 (D5)/1/O (D5)iVO (D5))1/O (D5) 1/0 (DS) (A1) | (A1) | (At) | (AN) | (AT) (AI) (At) iPi23|| vO | vO | vO | WO | WO! WO tO Piel] vO | VO | VO WO vO. vO VO, ___|| (C80) | (CSO) | (CSO) | (CSO) | (CSO) | (CSO) | (CS0)| pigalio O O~CO OO Plea | vO 4 WO | WO = Ptes|| WO | vO WO) WO | vO) Ol MO. P15 || Bs Bt WO | We | Wo (CS1, | (CS1, | (CS1, | (CS1, | (CS1, | (CS1, | (CSI, Piz6|| vO vO | vO | WO | vO | vO | vO Az) A2) A2) | A2) AZ) | AQ) AQ) P127|| vo vO vO vO vO VO vo. P166] I/O (A3):/O (A3):/O (A3)IVO (A3))1/0 (A3)| I/O (A3)//O (A3) 'P128|}/0 (D4)]i/O (D4))V/O (D4) VO (D4) VO (D4) VO (D4)|V/0 (D4) 87, Pyo9{| vo | vo | vo | WO vO vo | VO Pi3o|[ vec | vCC | vcc | VCC) vcC VCC VCC . P131|| GND | GNO | GND | GND | GND. GND GND x Gel vo 7WOoy WO P132|/O (D3)|1/O (D3)|I/O (D3)|I/O (D3)|1/O (D3).1/0 (D3)\1/O (D3) P171|| GND | GND | GND | GND. GND) GND GND Pi3all 0 vO Vo vO vO vo vO P172)) W/O vO VO vO VO VO VO (RS) | (RS) | (RS) | (RS) | (RS). (RS) | (RS) Pi73|| vo | VO | vO WO | WO. WO 0 _ Piza|[ vO | vO | vO | WO | WO | VO | WO | P174|l/O (A4):I/0 (A4)|/0 (Aa) I/O (A4)|I/0 (A4) 1/0 (AA) VO (A4) Pizsi|| vO WO | vO | WO} WO | WO. VO | 70 (A5)|VO (A5}|I/0 (A5)' I/O (A5)//O (A5)|VO (A5)-/0 (AS) mE DE We Pie ae NET NC | V0 | vo | vo [vo To No. | NC | vw | vo | w 7 July 30, 1996 (Version 1.03) 4-147XC4000 Series Fieid Programmable Gate Arrays PQ xc xc xe xc xc xc xc 4005 | 4006 4008 | 4010 | 4013 | 4020 | 4028 Pin E/L E E E/L E/L E EX/XL P180 VO (A6):1/0 (A6)!1/O (A6}/1/0 (A6)/I/0 vO P1814 (A7)| 1/0 (A7)I/O (A7)) 1/0 (A7)/1/0 (A7)/I/0 (A7)1/0 (A P182|} GND | GND : GND | GND | GND | GND | GND P1 vec | vec |, vec | vec | voc | vec | vec P41 1/0 (A8)/1/0 (A8)|1/O0 (A8)/ 1/0 VO (A8)| I/O P41 VO VO (A9) 70 (A8)//0 VO (Ag) I/O Pi vO vO vO vO vO VO VO (A10) | (A10) | (A10) | (A10) | (A10) | (A10) | (A10) P19t|} VO vO vO vO . Wo VO Vo (A11) | (At1) | (A1t) | (Att) (A114) | (A11) | (A114) P4 VO vO VO vO vO vO vO Pt vO vO vO ie) vO VO vO PI GND | GND | GND | GND; GND | GND | GND xc xc 4010 | 4013 E/L E/L xc XC i 4020 4028 | E EXXL P199 (A12) ; (A12) | (A12) | (A12) | (A12) | (A12) (A12) P200}| VO vO vO VO vO vO vO (A13) | (A13) | (A13) | (A13) | (A13) | (A13) | (A13) P2o1|] vO WO | vO | wo | wo | Ww | VO P202|| vO | WO vo | WO | Ww | WO | Ww P203|| VO VO vO vo vo vO vo (A14) | (A14) | (A14) | (A14) | (A14) | (A14) | (At4) P204|| vO, | VO, | VO, | VO, | vO, | VO, | VO, IS@CK1|SGCK1|SGCK1 SGCK1|SGCK1|SGCK1| GCK8 (A15) | (A15) | (A15) | (A15) | (A15) | (A15) | (A15) P205|| vcc | vec | vcc . vec |; vec | vec | vec P206]| N.C. | N.C.) NC. NC. N.C. | N.C. | NC. P207]| N.C. | N.C. | NC. | N.C. NC. | NC. | NLC. P208]| N.C. | N.C. | NC. | NC. NC. | NC. | NC | 3/13/96 Note: Shaded pins should be taken into account when de- signing PC boards, in case of future replacement by differ- ent devices. 4-148 July 30, 1996 (Version 1.03)$< XILINX PG223 and PG191 Package Pinouts fs _ FR | kcaoose xc40108 | xc4013E xc4020E | xC4025E These two packages have been combined into a single ta- | Pin | pin || PG@191 | PG191 | PG223 | PG223 PG223 | ble because of their physical compatibility. The PG191 has T3173 VO VO 10 70 70 the same dimensions as the PG223, but has 32 fewer pins | (AO, WS) | (AO, WS) | (AO, WS) | (AO, WS) | (AO, WS) on the inner ring. T4 ) 74 VO, VO, VO, VO, VO, i _ / SGCK4 | SGCK4 | SGCK4 | SGCK4 | SGCK4 | 8 | PS |kcaoose xcao10E |xca4o13e|xc40206/xcao2sE| | (DOUT) | (DOUT) | (DOUT) | (DOUT) | (DOUT) Pin | pin || PG191 | PG191 | PG223 | PG223 | PG223 (ws | 7sif vo | Wo | vo | WO | Ww. vi | vill ccuk | cclK | CcLKCcLK | CCLK | T6 16 |! V0 vo vO vO vO ve | v2 {lo 0 vO 0 vo =? 7 | GND GND | GND | GND GND ||) |L(RCER, | (RCL, | (ACER, | CTR, | CLK, = Te | Ta lf vo vo | vo vO | | RDY/ RDY/ RDY/ RDY/ RDY/ Ta | T9 || vO (D3) | YO (D3) | 0 (D3) VO (D3) | VO (D3) | | BUSY) | BUSY) BUSY) | BUSY) | BUSY) Tio| Tol] vo | Vo iO vO vO v3 "V3 || VO (01) | VO (01) VO (04) | VOI) VO O4) | Ti )t|| vo) V0 oT ne te v4 | vo WO "WO | Tig} t2|[ END | GND GND, GND | GND V5 5. : : vo | vw | w fats fio ao eo ve | v6 || Vo vo | vo vO Tia Tall vo | vo iO 0 Tron _W7 | V7 {[ VO (b2) | VO (D2) | WO (D2) VO (D2) | VO(D2) | Fs T4811 V0 (D7) VO (D7) | VO (D7) | VO(O7)_ :VO(D7) V8 | V8 |] VO vo vO YO {| VO | te ttel| vo, vo, | vo, | wo, | Wo, va | v9 vO vo vO vo vO SGCK3 | SGCK3 | SGCK3 - SGCK3 | SGCK3 Miojviolf vo | vo | vo | vw vo, (tiztti7 vo 7 WOT 0 Te) ovat} vq VO Vo YO vo vO | T18! 718 TO VO vO VO "vi2' Vi2 [I/O (ESO) VO (CSO) | VO (CSO) | 1/0 (CSO) V0 (CSO) Rl LAIN vO vO io ivi3 vi3{| vo v0 vo | WO. WO | | Re) Rel] v0 ) 0 via / | We [vo | vw R3 | RS GND | GND | GND V15 vO vO vO | R4 R4 vec | VGC vec | VIE vO | Vo vo ! Wo I R5 ~ vo | vO vO Vi7 vi7 |} vO (D6) | 70 (D6) | VO (D8) , VO (D6) | VO(06) RE vo vO WO | vig V18|| PRO- | PRO- | PRO- PRO- | PRO- AZ 0 yo | wl | GRAM | GRAM GRAM GRAM GRAM = ag Vo vo WO, ee 4 we Pack Pack Pace pack Packs | _R9 | A || GND | GND GND | GND GND | {An (At) | (At) (AN) (AN) R10; RI0}} VOC | VCC | VCC : vec ve U2 || 0, TDO | 0, TDO | 0,TDO | 0, TDO 0, TOO | AW Wo vo ~u3 ust) vo yO vO vo WO) | R12 Wo, WOT WO (DO, DIN) (DO, DIN) | (DO, DIN) (DO, DIN)|(D0, DIN); = R13 | ; vO iO | WO U4 tual] vo vo | vo vO vo | Ria WO vO vO ' Us | Us|! WO oc) vO vO | Ris A15|| VCC vec |} vec VCC vec | Us| uel; vo | vo | vo WO | vO R16 Ai|| GND | GND | GND | GND GND | u7 | u7|f vo v0 v0 WO; WO. Ri7 Ri7|[ VO | vO wo | WO WO , us us|! i/o vO v0 vO iO Be Ke vO | U9 | Ug |] 1/0 (RS) | VO (RS) - 1/0 (RS) | 0 (RS) | VO (RS) WO U10 | U10]| 1/0 (D4) | VO (D4) . VO (D4) | 1/0 (D4) | vO (D4) vO Utt: utt}] VO vO vO vO vO vO -U12.U12|| 70 (D5) | VO (D5) | VO (D5) | 70 (D5) _ VO (D5) vO 013, U13]/ vO vO i) vO vO} | Pts vo WO | VO U14 | U14 vO. Vo ie) vO vO} ' P16 | P16 vo [| Wo vo vo | Ww uis/uisi| vo) vO | WO v0 vo | Pi pif vo | wo vo | vo | WO ute; Utell vo, | VO, | WO, vO, V0, (P18 Pis|| vo vO vO | vO VO | PGCK3 | PGCK3 | PGCK3 PGCK3 | PGCK3_ MOUNT TL vo VO VO. WO vo. | _UI7/U17|| DONE DONE | DONE | DONE | DONE Wim Ne Coe, Vo )6UlOClUVO _Uia | Ural] vo WO WO | WO VO FNS TNs [fo (a3) 0 (A3) | V0 (A3) | VO (A3) VO (A3) iT | 71 vO ie yo vo we Nat WP WO. | VO io | 12) T2 vo vO VO vo ' VO NS | T6800 | (CS1.A2} (CS1A2) | (CS1.A2) (CST AZ) (CST,A2) Ni | Niel! V0 fF vo7 WO vO VO July 30, 1996 (Version 1.03) 4-149XC4000 Series Field Programmable Gate Arrays pea tg, |RC4008E | xXC4010E xXC4013E xC4020E |xcao2se| PS | PS lixcqooae /xc4o10E|xca013E |xC4020E |XC4025E Pin. Pin || PG191 | PG191 | PG223 | PG@223 | PG223 PGi91 | PG191 | PG223 | PG223 | PG223 N17 | Nt7]) NC. WO | VO vo vO /Fe it. a vO vO vO Nig NiBl} vO vO vO vO Me) F3 | F3 ||O (A12) | 1/0 (A12) | 0 (A12), 1/0 (A12) | 1/0 (A12) M1 M1 || 1/0 (AS) | 1/0 (A5) | VO (AS) | 1/0 (A5) = 1/0 (A5)_ Fa ie) vO VO M2 > M2 || 1/0 (A4) | 1/0 (A4) | 1/0 (A4) | 1/0 (A4) | 1/0 (A4) F415 VO vO vO M3 | M3{! GND GND GND GND GND Fi| Fiel| vo vO vO vO vO Ma 0 vO Oo + ee) VO vO v0 M15 V0 V0 iO Fis|Fis|| vo vo vo | Wo v0 Mi| M16] GND GND GND GND GND E1 | 1 vO ie) vO VO vO M17) M17[| lO vO vO re) VO | 2 | E2 vo! Vo vo | vo | Mi8/Mi8{/ 1/0 Te) vO vO ron E3 | E3 vO vO VO re) iO it} ui VO vO vO VO vO E4 vO vO re) i2 | l2 ie) vO V0 O- ie) E15 vO vO vO i3 | 13 VO VO vO ie) re) E16 | E16||/O (HDC)| VO (HDC}/ 1/0 (HDC)| 1/0 (HDC)| 1/0 (HDC) L4 vO vO VO E17 | E17||V/O (LDC)|I/0 (CDG) 1/0 (LDC) | 1/0 (LOG) |1/0 (LDC) L15 vO VO vO E18|E1e|{ vo ie) VO 0 vO Lis | Li6|| vO VO vO vO VO oy VO vo WO Li7)Li7]} vo vO vO ie) Vo VO (A13) | VO (A13) | 70 (A13) Lig | Lis|| vo vO VO vO vO D3 VCC VCC voc) vcc vcc Ki | Ki {[ vo vO 0 vO vo | 04 GNO | GND | GND | GND GND K2 | K2 || VO(A6) 1/0 (A6) | 1/0 (AB) | 1/0 (AG) | 1/0 (AB) D5 vO VO vO K3 | K3 || #0 (A7) WO (A7) | VO (A7) | 1/0 (47) | VO (A7) D re) VO vO K4 | K4 || GND GND | GND GND GND D7 v0 vO. vo K15 | K15|| GND GND GND | GND GND DB vO Vo VO Ki6 | Ki6|| VO vo | WO ie) 10 bg Dg|f GND | GND | GND | GND GND K17|K1i7|| VO vO vO VO vO Dio Bio|| vec vec | vcc Voc VCC K18|Kis|/ W/O v0 vo vo | vO D11 vO VO vO Jy) a vo vO 70 vO iO | D12- 0 0 Ne) ~J2 | d2 |) 1/0 (A9) | VO (a9) | 1/0 (AQ) | 0 (AQ) | 1/0 (AQ) Di3 vO vo" VO J3 | J3 || 0 (Aa) | 1/0 (a8) | 70 (A8) 1/0 (8) | 1/0 (A8) Di4 WO | WO: vO | J4 1 J4{[ voc | vec | voc | voc | vec Dis D15|/| GND | GND | GND | GND | GND Jt5 | Jis|] vec VCC vcG VCC VCC pis biel; voc VCC VCC VCC VCC 316 | J16//I/0 (INIT)! 1/0 GINIT) | 1/0 (INIT) | 1/0 (NTT) [1/0 (INIT) Di7 Di7 vO vO vO V0 siz} ui7{f vo vO iO WO 0 Di8 Bis]: [vo 0 VO v0 Jia] siel| vo vO re) vo | vo c1 C1 vO vo. VO. WO H1 | H1 VO VO vO vO vO | 2 G2 TiO (A14) | 70 (A14) | 1/0 (A14) | 1/0 (A14). HO (A14) Se eee ee - H3 |] vO vO " " (ate) | (A16) (Ate) | (A16) ~~ (A16) ae ii6 io (0 Ca C4 |]I/0 (A17) | VO (A17) | VO (A17) [0 (A17)_ VO (A17) a nae jenn fee earner cs. csi} vo VO vO vO VO H16 | Hie|! oO vO VO vO vO Ge cet 16 WOO 0 10 H17/HI7|} VO vO vO vO i) apart exp en GND GND 1 GND H18}Hiall VO vO vO V0 vO ca Gath ie ib ie 0 10 G1 | Gt [1/0 (A10) | 1/0 (A10) | 0 (A10) | 1/0 (A10) | 1/0 (A10) ce ee lh 10 6 6 Ta 6 G2 | G2 {I/O (A11) | VO (A11) | VO (A11) | VO (A11) | 1/0 (AT1) G10 Gill 10 (0 V0 iO io GS || GND GND a a ci} ci) v0 vO vO vO VO | Sie" 0 10 (0 C12] C12|| GND GND GND GND GND aie Gisll GND GND GND 1 GND GND c13/c13|| vo vO vO ie) ie) G17!G17|| vO V0 vo | vo | vo C14 | C14 |} VO vO" vo "vO vO Gis} Gi8l[| vo VO vO VO VO C15 | C15}} O (M1) | _O (M1) | O (Mt) | OMY) OM) Fi [Fill vo) vO | WO. 10 0 C16 | Ct1e|| 1(ma) | 1(M2) i(Ma) | 1(M2) 1 (M2) 4-150 July 30, 1996 (Version 1.03)i | aa in XC4008E | XC4010E | xXC4013E /xc40206| xc4025E | | ~ || PG191 | PG191 | PG223 | PG223 | PG223 : Pin | Pin ci7/ci7|| vo vO | WO VO vO | [cig ciall vo VO vO Ne) VO | Bi Bi 0 vO vO 0 vO | B2 | B2 VO, uO, vO, VO, 10, SGCK1 | SGCK1 | SGCK1 | SGCK1 | SGCK1 | (ats) | (A15) | (At5) , (A158) | (ATS) | _ BS | BS vO vo | Vo vO vO iE B4 | B4 |[V/O, TCK | VO, TCK | VO, TCK | VO, TCK| VO, TCK | | BS | BS c > | Vo vo | Ww | [ 86 Ww | VO vo | | 87 _B7 |[VvO, TMS | 1/0, TMS | 1/0, TMS | 0, TMS_/O, TMS | Bs | Bs || 1/0 vO vO | WO vO | Bg! B9]/ VO vO vO vO | oO | ,Bi0 |} Biol; VO vO 0 io | vO Bit | B11 0 vo | VO | VO vO | tM | B12) B12|] vo | vo | Vo vO V0 B13 vo | vO vO | | v0 [s) v0 io | vO | (Bis Bis|| Ovo i) 0 io | / B16 | B16] W/O, 0, vO, vO, vO, | L SCGK2 _ SCGK2 | SCGK2 | SCGK2 | SCGK2 | 'B17!B17|{ VO, | WO, vO, vo, | vo, | PGCK2 | PGCK2 | PGCK2 PGCK2 | PGCK2 | Big} Bisi| vO | VO vO, vO vO AQ | A2 |] VO, TDI | VO, TDI | VO, TDI | VO, TDI | VO, TDI (a3 A3 || vO 10 vo vO | VO, Ad Ad VO WO vO | WW vO [AS . AS vw | vo | WO: vO | fa a an fer rn | AG | AG vo vo, VO | WO Ww a7 | a7ll wo. vo | WO vO vO, + - co nner er ee AB | AB vo +O vO vO | WwW | AS | AS vO vw | Ww vo | Ww! A1o| A1o|| Vo 0 vo | Wo | Wo AIt Ait([ vO vo) vO | WO | VO Al7|Ai7|| WO | vO NO | VO A18 | Atal] 1(MO) | 1 (MO) 2/28/96 $< XILINX Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by dif- ferent devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-151XC4000 Series Field Programmable Gate Arrays BG225 Package Pinouts BG225 Pin Rl R2 R3 R4 RAS R6 R7 R8 Rg R11 R12 R13 R14 R15 PA P2 P3 P4 P6 P8 P9 XC4010E vec VO, PGCK2 VO VO vo VO VO vcc VO vO VO VO VO vcc VQ, SCGK2 | VO vO VO VO vO vO vO vO DONE VO VO vO O (M1 VO VO VO vO VO VO vO VO, SGCK3 VO, PGCK3 vO VO vO | vO vO VO GND VO VO VO XC4013E/L vcc VO, PGCK2 vO vO vO vO vO vcc VO vO vO vO VO voc VO, SCGK2 I vO VO vO vO vO VO, SGCK3 VO, PGCK3 BG225 Pin M15 Li L3 L4 LS L7 LB Lg XC4010E vO vO vO vO vO vO vO VO vo vo vO vO vO vo XC4013E/L vO vO vo vo vO vO vO VO 4-152 July 30, 1996 (Version 1.03)$= XILINX BG225 Pin XC4010E H14 vO H15 voc Gi VO G2 vO G3 vO G4 YO GS vO G6 VO G7 GND G8 GND G9 GND G11 vO Gl2 G13 G14 G15 F3 F4 FS F6 F8 vO vO vO VO vO vO vO VO (D1 VO vO vO VO, TDI VO, PGCK1 (At VO (At vO vO vec vO vO XC4013E/L VO vcc vO vO vo vO vo vo GND GND GND vo vO VO vO vo vO VO, TMS vO vO GND vo , DI Vo vo vO VO vO vO vo vO vO VO VO VO VO VO (D1 VO vo vo VO, TDI VO, PGCK1 (At VO (A1 vO VO VCC vo vO GND vO BG225 Pin XC4010E D14 VO D15 vO C1 VO, TCK C2 vo C3 VO, SGCK1 (A1 es} VO C7 VO C8 vO cg vO vO vO CCLK vO vo RDY, VO (A1 VCC VO VO (At vO VO (Alt vo vO VO vO vo VO, PGCK4 voc VO, SGCK4 GND VO (A14 VO YO VO (A10 vO GND vO vO vo VO vO : W/O (AO, 0, TDO 2/28/96 XC4013E/L vO vO VO, TCK vO VO, SGCK1 (A1 vO vO VO vO Vo VO CCLK vO vo ARDY, VO (At vec vO VO (Al vO VO (A11 vo VO(A vO vO vO VO, PGCK4 vcc VO, SGCK4 GND VO (A14 vO vo VO (Al VO GND vo vo VO VO vo 1, A2 VO (AO, 0, TDO Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by dif- ferent devices. Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-153XC4000 Series Field Programmable Gate Arrays PQ240, HQ240 Package Pinouts Hazan Pin||xeao1a.. XC4020E| xc4o2se Yraneeek PQ240/ |[XC4013E| a sooe xoaonse| XC4028EX a GRO = H@240 Pin||xc4013L XC4028XL > GND GND GND GND P46 V0 v0 V0 0 aS 6, 0, 0. 0, P47 vO V0 VO 0 PGCK1 | PGCK1 | PGCK1 | GCK1 P48 vO VO ie VO (A16) (A16) (A168) (A16) P49 VO vO vO VO P3 [I/O (A17)|VO (A17) UO (A17)| VO (A17) | P50 /0 0 V0 0 P4 V0 ) 0 10 P51 0 V0 0 0 PR /0 VO VO VO P52 vO vO VO ie) P6 0, TDi | VO, TDI | VO, TDI | VO, TOI P53 V0 V0 V0 0 P7 {1/0, TCK| V0, TCK 1/0, TCK| VO. TCK | P54 vo | vo VO 0 Pa 0 0 0 VO P55 vO Me) V0 V0 P9 VO 0 Vo VO P56 1/0 VO 1/0 /O P10 0 0 0 V0 P57 v0, i/0, 0, i/0, P11 VO VO 0 VO SGCK2 | SGCK2 | SGCK2 GCK2 P12 VO VO i/0 VO P58 O (M1) O (M1) O (M1) O (M1) P13 V0 VO VO VO P59 GND GND GND GND P14 GND GND GND GND | P60 | (MO) 1 (MQ) | (MO) | (MO) P15 VO vO VO VO, FCLK1 P61 VCC VGC vec vec 16 0 1) 1 6 P62 r(m2y) | (M2) 1(M2) | 1 (M2) P17 VO, TMS VO, TMS | VO, TMS 1/0, TMS P63 WO, VO, VO, 40, Die 70 0 0 oT PGCK2 | PGCK2 | PGCK2 | GCK3 DI9 Vee Veet VEE vee P64 [I/O (HDC) |I/0 (HDG) I/O (HDG)! 1/0 (HDC) P20 v0 v0 0 VO | POS vo vo vO vo P21 v0 vO v0 0 P66 vO vO vO vO = P67 0 0 v0 0 boa a 0 iO 0 P68 || (LDC) VO (LDG)| 1/0 (CDG) | 1/0 (LBC) P24 vO 0 V0 iO | P69 vO vO VO vO P25 V0 V0 V0 vO. | P70 vO v0 VO vO P26 V0 0 io) iO p71 vO ie) VO Vo P27 0 0 0 iO | Pre v0 vO VO vo P28 0 0 V0 10 P78 vO vo vO vO P29 |; GND | GND | GND GND P74 vo vO vo vO P30 vec. vcc | vcc Were) P75 GND_ | GND | GND GND Pai 10 0 To} 0 P76 VO vO vO vO P32 V0 10 v0 V0 P77 vO vO VO V0 P33 v0 0 0 0 P78 vO vO vO vO Pad 0 0 v0 iO P79 VO vo vO vO Bas 0 0 0 io P80 se bie vee Pai if if re ve vo ve vo Pee 0 vO 0 v0 Pad 0 v0 0 v0 Pas 0 0 0 v0 Pa6 0 v0 vO V0 PAD 10 70 10 P87 v0 vO 0 v0 P43 V0 0 V0 V0 P88 vo, WO | vo | Ww | Baa 0 V0 io 8 FEL Pag {I/O (INIT) 1/0 (INIT) VO (INIT) | 1/0 (INIT) | 4-154 July 30, 1996 (Version 1.03)$< XILINX PQ240/ |[xC4013E XC4028EX XC4013E | Ha240 Pin||xcao1aL | ~C4020E/ XC4025E | yc soogxt XC4013L | *C4020E | XC4025E xCA028KL | P90 vec. | vec | Vcc VCC 0 VO 0 | P91 GND GND GND GND GND GND GND ~ | P92 vO vO vO VO vO Te) /0 P93 vO vO vO vO | vo V0 0 | P94 vO vO vO vO | vO vO VO |/0, FCLK3| P95 vO VO vO V0 Te) 0 vO P96 vO vO VO vO vcC vcc VCC P97 /0 VO 0 ie) /0 (D5) | VO (D5) | 1/0 (D5) | VO (05) | VO (CSO) |VO (CSO) 70 (ESO) | 0 (ESO) P99 vO vO VO ie) (Re | NES K BNDE P100 Te) vO VO vO VO vO VO P101 VCC VCC VCC VCC VO 7) VO P102 vO 0 ie) /0 vO 0 vO | P103 Te) VO /O vO vO 0 vO P104 0 vO vO ie) VO (D4) | /O (D4) | 1/0 (D4) | 1/0 (D4) P105 0 ie) VO VO ie) 0 VO P106 GND GND GND GND VCC VCC vec P107 0 vO /0 vO GND GND GND P108 VO vO vO vO VO (D3) | VO (D3) | /O (D3) | 1/0 (D3) P109 vO vO vO 0 0 (RS) | 70 (RS) | 1/0 (RS) | 0 (RS) P110 vO vO /0 vO v0 vO VO Pit VO ie) VO vO /0 vO | VO ~ P112 vO re) vO /0 VO 0 vO P113 Te) VO ie) V0 VO 0 vO P114 ie) VO ie) VO 2 P115 ie) vO vO /0 VO (D2) | VO (D2) | 0 (D2) | 0 (02) P116 0 vO 0 V0 ie) vO | VO P117 re) VO VO /0 vec VCC vec P118 VO, VO, vO, /0, vO iO VO SGCK3 | SGCK3 | SGCK3 | GCK4 VO VO WO (VO, FCLK4 P119 GND GND GND GND VO iO. WO P120 DONE | DONE | DONE DONE | vO 0 /0 P121 VCC vcc vec VCC GND GND GND. GND P122 PRO- | PRO- | PRO- PRO- vO vO vO GRAM GRAM GRAM GRAM vO VO VO P123 || O (D7) | YO (D7) | VO (D7) | 0 (07) /0 0 0 P124 0, vO, /0, VO, V0 0 VO PGCK3 | PGCKS | PGCKS GCK5 0 70 0 P125 VO /0 ie) VO vO 70 0 P126 vO vO vo vO | VO (D1) | VO(O1) | VOI) | VO) P127 vO re) 0 vO 10 io 0 P128 vO vO VO vO (ACLK, | (RCLK, | (RCLK, | (RCLK, P129 || 1/0 (D6) | /O (D6) | 1/0 (D6) | 1/0 (D6) RDY/ | RDY/ = RDY/ P130 0 vO /0 vO BUSY) | BUSY) BUSY) BUSY) P131 0 vO /O ie) vO vO vO P132 vO vO iO | WO vO vO vO P133 VO ie) V0 vO July 30, 1996 (Version 1.03) 4-155XC4000 Series Field Programmable Gate Arrays PQ240/ ||XC4013E XC4028EX PQ240/ ||XC4013E X EX! HQ240 Pin ||XC4013L XC4020E | XC4025E XC4028XL HQ240 Pin||XC4013L XC4020E | XC4025E xC4D28XL P177 VO vO VO VO P218 vO VO vo VO (DO, DIN) | (DO, DIN)| (D0, DIN)| (DO, DIN) ag. a zi Zz P178 VO, VO, VO, VO, P220 [/I/O (A10) | /O (A10) | I/O (A10)| 1/0 (A10). SGCK4 | SGCK4 | SGCK4 | GCK6 P221 |/VO(A11) 1/0 (A11) | 1/0 (A11) | 0 (Att) (DOUT) | (DOUT) | (DOUT) | (DOUT) Papa VCG VOC VCC VCC P179 CCLK CCLK CCLK CCLK P2093 VO VO 10 VO P180 vcc vcc vcc vcc Poa4 V0 VO VO V0 P181 0, TDO | 0, TDO | 0, TDO | O, TDO Peas VO V0 VO 0 a as ~ ~ ae ~ P226 0 v0 vO V0 (Ao, WS)| (Ao, WS) | (AO, WS)| (AO, WS) P227 GND GND GND GND Pied v0, /0, 0, V/0, P226 vo vo vo vO PGCK4 | PGCK4 | PGCK4 | GCK7 P229 vO vO vO vO (A1) (A1) (A1) (Al) P230 vO ie) VO vO P185 vO vO v0 VO P231 vO vo vO vO P186 VO VO re) VO P232 1/0 (A12) | I/O (A12) 0 (A12)| 1/0 (A12) | P187 1/0 (CS1, | VO (CS1, | VO(CS1,| /O (CS), P233 _|/1/0 (A13) | VO (A13) YO (A13) | 1/0 (A13) A2) A2) A2) A2) P234 VO vO VO ie) P188 || /O (A3) | 1/0 (A3) | WO (A3) | 1/0 (A3) P235 vO V0 vO ie) P189 vo VO V0 Vo P236 VO /O Vo VO P190 VO vO VO VO P237 VO VO VO VO P191 vo VO VO Vo P238 VO (A14) | /O (A14) | 1/0 (A14)| VO (A14) P192 VO VO 1) vo P239 VO, V/O, /O, VO, P193 VO VO V0 VO SGCK1 | SGCK1 | SGCK1 GCK8 P194 0 vO 0 VO (A15) | (A15)_ | (A15)_ | (A15) 5 P240 vcc Vcc vcc vec P196 GND | GND | GND | GND 3/11/96 P197 vO vO VO YO + Pins labelled GND should be connected to Ground if P198 vO vO VO. YO ___ possible; however, they can be left unconnected if neces- P199 VO VO vO YO |; sary for compatibility with other devices. Pins labelled P200 VO 1) VO VO N.C. are reserved for Ground connections on future revi- P201 VCC VCC Vcc vcc sions of the device. These pins do not physically connect P202 VO (A4) VO (A4) | VO(A4) 1/0 (AA) to anything on the current device revision. However, they P203 70 (AS) WO (AS) | VO (AS) |_/O (AS) should be externally connected to Ground if possible. P209 VO (A6) | I/O (AB) P210 || #0 (A7) | VO (A7) | 0 (A7) | 1/0 (A7) Pati GND GND | GND GND P22 VCC VCC VCC VCC P213 || VO (A8) | VO (A8) | 0 (A8) | 1/0 (A8) P24 || 1/0 (A9) /O (A9) VO (A9) | VO (AS Note: Shaded pins should be taken into account when de- signing PC boards, in case of future replacement by differ- ent devices. 4-156 July 30, 1996 (Version 1.03)$= XILINX PG299 Package Pinouts PG299 Pin XC4025E XC4028EX/KL vi V0 (D4) VO (D4) PG299 Pin XC4025E [ xGaozsexxL v4 0 a Xi 70, SGCK4 (DOUT) | _ VO, GCK6 (DOUT) vis 7a 7 Xe GND GND | via vO v0 x3 vO vo | V15 vO | vO x4 vo vO V16 vO vO : x6 VCC voc _ Vi7 vO V0 x6 GND GND vig DONE DONE x7 vO vO vi9 v0 vO x8 VO vO 20 Te) vO x8 vO vO U1 vO vO x10 vo voc UB 0 4 2 |__mM GND GNO us VO (C81, A2) VO(CS1,A2) | |___ X12 vO vO | U4 0, TDO 0, TDO | __X18 vO vO U5 vO ie) X14 0 (G50) VO (CSO) Ue iO DD : io 6 Zl X15 VGC VCC 5s 70 0 X16 GND GND ta O 6 | __ Xi V0 V0 55 16 10 4 L__X18 vO vO Ut0 v0 v0 X19 voc vec Un v0 V0 X20 0, SGCK3 V0, GCK4_ aa 7 0 4 wi vec VOC U13 v0 0 w2 70 (AO, WS) VO (AO, WS) Gia 0 a WS vO vo UI5 10 10 |__W4 vO - vO + U6 vO vO |__W5 vo "wo WF PROGRAM PROGRAM | __W6 vo VO [ute v0 Te) W7 v0 0, FCLK4 aH 70 70 | we 1/0 (D2) V0 (D2) G20 0 0 wo vO vO TH GND GND wio 1/0 (D3) 0 (D3) 5 16 70 wit 0 vO = 10 70 |__ Wwi2 vo vO T4 vO V0 wi3 vO V0 he GND ano wi4 0 VO, FCLK3 -= 1G 76 Wi5 v0 To) | 5 0 0 W16 VO vo T8 70 0 Wwi7 1/0 (D6) 70 (D6) --- 0 10 wis 0, PGCK3 1/0, GCKS 0 a 0 wi9 0 (07) V0 (D7) =e 7a 70 w20 GND GND T72 VO (05) 70 (D8) Wi 1/0 (A3) V0 (A3) Ha 76 10 v2 VO, PGCK4 (At) VO. GCK7 (At) aa 0 70 V3 CCLK CCLK wi 0 10 v4 /0 (DO, DIN) V0 (00, DIN) _ a ADYIBUSY) ADY/BUSY) m7 v0 v0 ve _ T19 v0 0 ve v0 v0 |___720 vec voc + 7 10 4 Ri voc vec | V10 0 (RS) 0 (RS) R2 V0 vO July 30, 1996 (Version 1.03) 4-157XC4000 Series Field Programmable Gate Arrays PG299 Pin XC4025E XC4028EX/XL XC4025E XC4028EX/XL R3 10 vO ao E R4 re) VO K16 0 VO | AS vO vo Ki7 VO vO R16 VO vO - Ki8 vO vO R17 v0 40 | Ki9 VO (INIT) VO (INIT) R18 0 VO K20 GND GND R19 VO vO J vO vO R20 GND GND J2 vO vO PA vO 0 J3 VO (A11) VO (A11) P2 yO VO J4 vO vO P3 0 VO J5 vO re) P4 1/0 vO J16 vO vO PS 0 vO S17 vO VO P16 0 ie) J18 vO VO P17 ie) vO | J19 vO ie) P18 V0 Te) J20 VO vO P19 vO 0 H1 VO {A10) VO (A10) P20 VO VO H2 VO vO NI VO (Aa) 1/0 (Ad) H3 VO vo N2 VO VO H4 vO vO N3 0 vO HS vO vO N4 vO vO H16 vO vO N5 vO vO H17 vO vo N16 VO vO H18 vO vO N17 VO vO Hi9 vO vO N18 vO vO H20 vO vO N19 vo VO Gl vO vO N20 0 VO G2 vO VO oN D. A21) G3 vO vO M2 0 VO G4 vO vO M3 VO (AS) VO (AS) G5 1/0 (A12) VO (A12) M4 vO ie) Gi6 vO vO M5 vO vO Gi7 vO 0 Mi6 vO vO | GiB vO vO M17 re) vO G19 0 0 M18 vO vO G20 vO VO M19 ie) VO FA GND GND M20 /0 vO F2 VO vO u GND GND F3 VO vO L2 W/O (A?) VO (A7) F4 vO vO L3 VO (A6) VO (A6) F5 vO vO vO 2 WO (20) F16 VO i) vO Te) FI7 VO vO L16 vO vO F18 vO vO Liz re) vO F19 vO vO L18 vO vO F20 VCC VCC L19 yO VO Fl VCC VCC L20 vcc Vcc E2 vO re) Ki VCC vec E3 vO vO K2 VO (A8) 1/0 (A8) E4 VO vO K3 10 (AQ) 1/0 {(A9) E5 VCC VCC + E6 vO vO 4-158 July 30, 1996 (Version 1.03)$= XILINX PG299 Pin XC4025E XC4028EX/XL PG299 Pin XC4025E XC4028EX/XL E7 10 vO C19 VO (HDC) VO (HDC) 8 vO vO | C20 vO (EDC) vO (LDC) E9 vO vO | |B GND GND E10 v0 vO B2 1/0 (A17) VO (A17) E11 vO vO B3 vO vO E12 vO 0 | B4 vo vo.C~S E13 vO vO B5 0 re) E14 VO [ vO 7 B6 0 VO, FCLK1 E15 ie) ie) B7 vO vO | E16 GND GND BS VO VO E17 vO vO | Bo vO vO E18 vO vO B10 0 vO 7 E19 vO VO | B11 ie) vO E20 GND GND ~ Bt2 VO vO D1 vO vO B13 vO vO | D2 vO vO B14 ie) vO D3 vO (A14) VO (A14) B15 vO vO D4 VO, PGCK1 (A16) VO, GCK1(A16) | B16 vO VO DS VO, TOI VO, TDI | B17 vO 0 D6 vO VO B18 ie) VO D7 0 vO B19 VO, PGCK2 VO, GCK3 D8 ie) vO B20 VCC Were) Dg vO vO Ae VCC VCC | D10 V0 V0 yo. A3 vO VO D1 vO vO | A4 vO VO Di2 Me) vO a AS GND GND D13 vO VO, FCLK2 AG VCC VCC p14 vO VO A? vO vO Dis vO vO | AB vO vO D6 vO vO Ag vO VO DI7 1 (M2) 1 (M2) A10 GND GND D18 vO vO Alt vcc vcc D19 vO vO A12 vO vO D20 vO | vO Ai3 vO vO Ci VO (A13) VO (A13) Ai4 vO 0 C2 vO vO A15 GND GND C3 VO, SGCK1 (A15) VO, GGK8 (A15) Ai6 voc vec C4 VO, TCK VO, TCK A17 vo vO C5 VO vO A18 vO vO C6 ie) vO A193 GND GND C7 VO, TMS 0, TMS A20 O (M1) O (M1) C8 vO vO | 3/18/96 co VO vO c10 vO vO | Note: Shaded pins should be taken into account when de- Cit vO vO 7 signing PC boards, in case of future replacement by differ- Cia 0 VO | ent devices. C13 VO VO Note: Viewed from the bottom side, the package pins start C14 vO vO at the top row and go from the left edge to the right edge. C15 vO vo Viewed from the top side, the pins start at the top row and C16 vO vo go from the right edge to the left edge. C17 vO, SGCK2 VO, GCK2 C18 1 (MO) | 1 (MO) July 30, 1996 (Version 1.03) 4-159XC4000 Series Field Programmable Gate Arrays HQ304 Package Pinouts HQ304][ y cagose XC4028EX XC4036EX Pin XC4028XL XC4036XL Ha3o4 XC4025E XC4028EX XC4036EX Pat 10 70 TO in XC4028XL XC4036XL b Bap Vee VOC vee Pi vec VCC vec Beg NG NG ws P2 ||/O, SGCK1(A15)| 1/0, GCK8 0, GCKB Bea 70 70 o (A15) (A15) P3 /0 (A14) VO (A14) VO(A14) PSS vO ie) vO P4 Vo vO Ve) ~~ P56 VO VO vO BS 0 V0 0 P57 vO VO v0 B iO 0 0 P58 GND GND GND pF V0 0 VO Ps9 vO VO vO P8 VO vo VO P60 VO 1/0 vO pg VO ! vo vO P61 vO vO vO P10 /O (A13) VO (A13) VO (A13) P62 VO vO Le) Pit NC N.C. NG. P63 VO vO V0 P12 1/0 (A12) 70 (A12) VO (A12) Ped vO vO vo P13 0 0 0 P65 V0 0 vO P14 0 0 10 P66 VO vO vO Bis VO WO i P67 VO vO VO B16 v0 v0 Te) P68 vO vO ie) Bi7 0 v0 v0 P69 VO (A3) 0 (A3) VO (A3) Fis 70 0 vO | P70 || VO(CSt,A2) | VO(CS1,A2) | V0 (CS1, A2) P19 GND GND GND P71 vO VO vO P20 v0 0 VO Pre vO vo vO Pay 0 ! 16 0 _ P73 ||/0, PGCK4 (At) | VO, GCK7 (At) | 1/0, GCK7 (Al) pa2 10 v0 vO P74 || vO (a0, WS) VO (AO, WS) VO (AO. WS) P23 0 v0 0 P75 GND GND GND P24 NC. NG. NG. P76 0, TDO 0, TDO 0, TDO P25 VCC vcG VCC P77 voc vec vec P26 v0 VO 0 P78 CCLK CCLK CCLK P27 0 /0 V0 P79 y) Dour) u oun C Con. P28 vO vO vo P80 || 1/0 (D0, DIN) /O (DO, DIN) 0 (DO, DIN) P29 V0 V0 V0 oT 16 0 10 P30 VO (A11) VO (A11) VO (Alt) Bap (0 iO 16 P31 VO (A10) VO (A10) O (A10) Bas 0 io iO | P32 VO vO vO BBA 10 16 70 vo vo vO P85 VO (ACLK, VO (RCLK, /0 (RCLK, RDY/BUSY) RDY/BUSY) RDY/BUSY) oe bsbaa : mo ew PB6 VO (D1) VO (D1) VO (D1) P36 VO (A9) VO(A9) | VO (AQ) Pay V0 0 V0 P37 VO (A8) VO (A8) / VO (A8) Pes vO vO VO P38 VCC VCC vec : Pg9 vO VO VO P39 GND GND GND P90 v0 v0 v0 P40 VO (A7) VO (A7) VO (A7) | P91 vO vO VO P41 VO (A6) VO (A6) I/O (AB) P92 vO VO VO Wd uO (A: P93 V0 iO vO ae a (he P94 vo V0 VO P44 /O VO VO P95 GND GND GND P45 VO VO VO / P96 vO vO vO P46 VO (AS) VO (A5) VO (A5) / P97 vO vO vO P47 VO (Aa) 0 (A4) /0 (Aa) P98 v0 VO, FCLK4 VO, FCLK4 P48 vO vO vO P99 vO vO vO ,_Pa9 vo vo VO : P100 N.C. N.C. NC. |_P50 vO vo vO P4101 vCG VCC vec 4-160 July 30, 1996 (Version 1.03)$2 XILINX "Si sowme | Xetdat | Sete SBI vcwme | Feu | ESR P102 Tre) vO 0 P155 || VO, SGCK3 VO, GCK4 VO, GCK4 P103 VO (D2) VO (D2) VO (D2) , P156 vO vO vO P104 VO vO io | P157 vO 0 vO P105 VO vO vO P158 vO VO vO P106 vO vO vO P159 0 vO re) P107 vO vO vo | P160 ie) vO 0 P108 vO vO vO P161 0 vO vO P109 vO v0 vO P162 vO vO VO P110 vO vO re) P163 VO 0 vO | Pq vO vO vO | P164 vO ie) vO , P1t2 VO (RS) VO (RS) VO (RS) P165 vO vO ie) PIH13 VO (D3) VO (D3) VO (D3) P166 VO vO vO P114 GND GND GND P167 VO vO vO P115 VCC vec vcc P168 vO 0 vO P116 vO 0 0 P169 vO vO vO P4117 VO (D4) VO (D4} VO (D4) P170 vO vO re) P118 0 vO vO Pq71 GND GND GND | P1149 vO vO 0 P172 vO 0 vO P120 VO vO 0 P173 vO V0 VO 7 | P121 VO vO 0 P174 vO 0 vO P122 VO vO VO P175 Tr) 0 vO P123 ie) vO VO P176 NC. NC. NC. P124 vO vO VO P177 VCC VCC vec P125 VO vO vO P178 Te) ie) 0 P126 VO (C50) VO (C50) VO (C50) P179 vO vO i) P127 VO (D5) V/0 (D5) VO (D5) P180 vO vO vO ~ P128 NC. N.C. N.C. P181 vO vO vo | p129 VCC Vcc VCC P182 0 Te) vO | P130 vO ie) vO P183 VO 0 0 P131 vO VO, FCLK3 VO,FCLK3 | P14 VO vO 0 P132 vO 0 vO P185 ie) vO 0 P133 re) 70 1/0 P186 re) V0 VO P134 GND GND GND P187 vO vO VO P135 vO VO vO | | 188 0 vO VO P136 vO 0 re) P189 vO vO V0 - P137 vO VO io P190 GND GND GND P1338 vO VO vo | P191 VCC VCC VCC P139 v0 VO re) 7 P192 VO (INIT) W/O (INIT) 1/0 (INIT) P140 v0 0 vO P193 vO vO vO P141 vO VO vO P194 vO vO vO | P142 VO (D6) 0 (D6) /O (D6) P195 VO vO vO P143 vO vO vO P196 vO vo ~~ YO P144 ie) VO vO 7 P197 v0 vO vO P145 vO ie) vO .:~PI98 vO ~ VO vO P146 vO vO vO | Pigg Te) vO vO P147 vO vO vO - P200 vo vO vO P148 vO vO 0 P201 vO 70 vO P149 VO, PGCK3 VO, GCKS vO,GCKS P202 re) Te) vO P150 VO (D7) VO (D7) 1/0 (D7) P203 vO vO Te) P151 PROGRAM PROGRAM PROGRAM | P204 VCC Were) VCC P152 vec VCC vec. P205 N.C. NC. N.C. P153 DONE DONE DONE P206 vO HO vo - | P154 GND GND GND | P207 v0 vO vO July 30, 1996 (Version 1.03) 4-161XC4000 Series Field Programmable Gate Arrays H 4 | Xe Pin |[ 4025 | Xcaozexe | xceosext. pin || XC4025E XCaooexr | xcanaexe P208 0 VO vO | [P61 | vO VO vO | P209 || vo vO vO | [262 vO vO vO P210 GND | GND GND ' P263 vO vO vO P211 0 vO 0 P264 vO vO vO | P212 vO vO ron P265 vO Te) re) P213 || vO ~ Oo, vO | _P266 vO _ vO Vo P2t4 vO vO re) | P267 ee! Vcc VCC P215 VO vO VO | P268 GND if GND GND P2146 ve) vO vO P269 Ke) re) vo P217 vO 1/0 | vO P270 vO vO v0 P218 vO VO vO P271 VO vO 0 P219 vO vO 1/0 P272 VO vO vO P220 vO VO VO P273 vO vO vO | P221 vO (CDC) vO (LDC) VO (LDC) P274 vO vO vO P2220 || vO 0 vO P275 VO 0 VO P223 Te) vO vO P276 vO vO iO | P224 vO ie) vO- P277 vO vO yO | P225 VO (HDC) VO (HDC) VO (HDC) P278 re) ie) vO TT] P226 VO, PGCK2 VO, GCK3 O, GCK3 P279 vO vO re) | P227 1 (M2) 1 (M2) 1 (M2) P280 VO VO vO | | P228 vec _ VCC vec _ P2681 NC. NG. N.C. ~~ P22g 1 (MO) | (MO) 7 1 (MO) P282 vec VCC vec ~ P230 GND GND GND P283 vO vO vo | P231 O (M1) O (M1) 0 (Mi) P284 VO, TMS VO, TMS vO,TS P232 VO, SGCK2 VO, GCK2 VO, GCK2 P285 vO vo vO ~ p233 {| ie) re) vO P286 vO VO, FCLK1 iO, FCLK1 ' P234 vO 0 vO P2987 GND GND GND 7 P235 VO 0 vo P2838 vO vO VO P236 me) vO Te) ~ P2g9 0 vO VO P237 vO vO - vO P290 ie) vO vO ~ P23e || VO vO vO P2901 ie) v0 V0 P239 vO Oo. vo . 292 VO vO ie) P240 vO vO vO ~P293 vO tO | Wo P2441 vO vo vO P2094 vO Vo | VO P242 VO vo vO P295 vO vO vO P243 ie) VO vO P296 vO vO 7) P244 iO V0 io || P297 vO Ke) io P245 VO vO vO P298 VO, TCK VO, TCK VO, TCK P246 vO vO VO P299 VO, TDI VO, TDI VO, TDI P247 vo vO | vO P300 vO VO vO P248 GND GND GND ~P301 vO 0 re) P249 VO VO, FCLK2 V/O, FCLK2 P302 VO (A17) VO (A17) VO (A17) P250 V0 vO vO P303 || V0, PGCK1 VO, GCK1 VO,GCK1 | P251 VO vO VO (A16) (A16) (A16) P252 vO vO V0 | _P304 GND GND GND : P253 VGC VCC VCC 3/20/96 P254 N.C. N.C. NC. 255 Tr) vO re) Note: Shaded pins should be taken into account when de- Po66 VO iO iO signing PC boards, in case of future replacement by differ- P257 vO V0 jo ~~-ent devices. P258 vO v0 vO P259 VO vO yo. p260 || sO vO vO 4-162 July 30, 1996 (Version 1.03)$< XILINX BG352 Package Pinouts BG352 Pin XC4028EX/XL __ [_ AFI GND | AF2 GND | AF3 vO - AF4 vO AF5 GND AF6 vO AF7 0 | AF GND a AF 0 | AF10 VCC | AF11 vO _ AF12 vO - AF13 GND - AF14 0 (INIT) | | AFI5 vO AFI6 vO ; AFI7 VCC | AF18 vO 4 ; AF19 GND __ _ AF20 vO 4 AF21 vO AF22 GND _ | AF23 VO _ AF24 VO | AF25 GND | AF26 GND AEI GND | AE Wee | AES iO | AE4 N.C. 7 AES vO AE6 vO : AE7 /0 _ AE8 vO AES vO - AE10 N.C. _ AE11 vO 7 AEI2 yO S| AE13 VO | AEI4 vO AEI5 yO _ AEI6 ie) AE17 yO AE18 iO AE19 vO - AE20 v0 AE21 vO AE22 vO | AE23 VO (LBC) | AE24 VO, GCK3 ~ AE25 VCC _| AE26 GND ADI v0 | AD2 0 (D7) AD3 DONE 7 AD4 0 : ADS vO | ADE vO | BG352 Pin XC4028EX/XL | AD7 vO [ AD8 vO AD9 vO _ C AD10 vO | __ADII __ vo - AD12 vO | AD13 VO _ - | __AD14 a) AD15 0 | AD16 NC. AD17 _ vO AD18 vO _ a AD19 vO AD20 ; VO - AD21 N.C. AD22 _ VO AD23 VO (HDC) ~ AD24 1 (MO) | AD25 0 AD26 N.C. ACI j vO AC2 _ N.C. AC3 VO,GCKS AC4 PROGRAM _ _ AC5 WO, GCK4 AC6 NC. AC7 vO 7 ACB VCC ACS vO AC10 vO _ ACI NC. ' AC12 0 AC13 _ Ke) AC14 __ VCC | AC15 [ v0 | ACIE N.C. ACI7 vO AC18 vO _ ACI9 vO | AC20 vec AC21 NGC, _! 7 AC22 vO AC23 AM) AC24 VO, GCK2 a AC25 NE. AC26 VO ABI GND AB2 0 | ABS N.C. AB4 __ vO AB23 : O (M1) AB24 vO AB25 V0 AB26 GND __ AAI vO AA2 vO AA vO AA4 __ vO : | AA23 vo _ ' AA24 vO July 30, 1996 (Version 1.03) 4-163XC4000 Series Field Programmabie Gate Arrays BG352 Pin XC4028EX/XL BG352 Pin XC4028EX/XL AA25 vO N3 vO AA26 vO N4 VO (RS) Y1 Ts) N23 vec Y2 vO N24 vO Y3 VO (D6) N25 0 Y4 VGC N26 vO . Y23 vO M1 vO Y24 vO M2 vo Y25 vo M3 vO Y26 V0 M4 vO wi GND M23 vo we vo M24 vO W3 VO M25 0 w4 vO M26 vO w23 VGC L1 vO we4 vO L2 vO W25 vO L3 VO i W26 GND L4 N.C. 7 V1 vO (CSO) L23 N.C. v2 VO (D5) L24 ie) V3 vO _ L25 vO V4 vO L26 vO V23 vO Ki VCC V24 vo __ K2 NC. V25 0 : K3 vO 26 VO K4 vO ul vcc K23 vO [. U2 ie) K24 vO U3 VO K25 0 U4 VO, FCLK3 K26 voc U23 VO, FCLK2 Jt VO (D2) U24 vO J2 vO U25 NC. J3 /O, FCLK4 U26 VCC J4 VO TI vO J23 VO, FCLK1 T2 vO J24 VO Ce T3 NC. J25 VO T4 NC. J26 NC. T23 vO Hi GND T24 NC. H2 VO T25 vO H3 ie T26 vO H4 VGC Ri vO H23 vO r A2 0 H24 0 R3 vO H25 VO, TMS R4 is) H26 GND R23 vO ey vO R24 vO G2 vO ~ R25 vO G3 vO R26 vO G4 VO (RCOLK, RDY/BUSY) P1 vO G23 VCC P2 VO (D4) G24 vO P3 0 G25 VO 4 P4 vec G26 vO P23 vO Fi vO P24 vO F2 Te) P25 vO F3 VO (D1) P26 GND F4 vO NI GND F23 N.C. N2 1 (D3) F24 vO 4-164 July 30, 1996 (Version 1.03)$= XILINX BG352 Pin XC4028EX/XL BG352 Pin XC4028EX/XL F25 vO C25 VO (A17) F26 vO C26 VO, TDI E1 GND Bi GND E2 vO B2 VCC E3 vO B3 VO (AG, WS) &4 VO, GCK6 (DOUT) B4 N.C. E23 vO B5 i) E24 VO, TCK B6 vO E25 vo B7 vO E26 GND B8 vO D1 N.C. B9 vO D2 vO B10 N.C. D3 1/0 (DO, DIN) Bit vO D4 0 (TODO) Bi2 vO D5 vo B13 VO (A20) D VO (C81, A2) B14 /O (A7) D7 VCC B15 VO (A18) D8 vO a B16 VO (A11) D9 vo B17 vO D10 vO B18 vO Dit vO B19 vO Di2 VO (A4) B20 ie) D13 VCC | B2t vO D14 VO (A8) B22 VO (A12) D15 vO B23 NC. D16 N.C. | B24 VO DI7 vO B25 VCC Di8 VO B26 GND D19 vec Al GND D20 vO | A2 GND D21 vO A3 Ms) 022 VO (A14) Ad vO D23 VO, GCK1 (A16) AS GND p24 vO | AG vO D25 N.C. A7 vO D26 vO A8 GND ci N.C. AQ vO C2 vO - A10 VCC C3 CCLK - Ail VO C4 O, GCK7 (A1) A12 0 C5 N.C. - A13 V/O (A6) C6 VO (A3) A14 GND C7 vO A15 VO (A19) cB N.C. ~~ A16 VO (A10) _ cs vO AI? vec d C10 vo A18 NC. Cit N.C. _ A19 GND C12 VO (A5) | A20 vO C13 VO (A21} - A21 0 C14 VQ (AQ) A22 GND C15 vO A23 vO C16 vO A24 N.C. i C17 vO 7 A25 GND Ci8 vO 5 A26 GND C19 vO | 2/28/96 | C20 V0 4 ; . . C21 0 (A13) | Note: Viewed from the bottom side, the package pins start C22 vO | at the top row and go from the left edge to the right edge. C23 vO - Viewed from the top side, the pins start at the top row and C24 VO, GCK8 (A15) a go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-165XC4000 Series Field Programmable Gate Arrays PG411 Package Pinouts PG411 Pin |= XC4036EX/XL XC4044EX/XL AU25 NC. NC. PG411 Pin XC4036EX/KL XC4044EXXL AUD? 70 (C50 6 1080) AW! vo vO [ AU29 vO vO AWS GND GND AU31 re) vO AWS vo 0 AU33 vO vO AW7 /0 (ACLK, vO RDY/BUSY) RDY/BUSY) AUS5 vO vO AW voG vec AUS? a NC. AW11 GND GND AUSS GND GND AE 0 iO | ATR NC. NC. AT4 0 (AO, WS) 1/0 (AO, WS) AWI7 10 VO | _AT6 GND GND AW19 vec vec AT vO vO Await GND GND AT10 vO vo ATi2 v0 0 AT14 GND GND 10 iO AT16 0 10 Vee VEG ATI8 vO vO GND GND AT20 GND GND 16 i | AT22 V0 me) NG Ne ~AT24 V0 i) vec VEC AT26 GND GND 10 0 AT28 VO, FCLK3 VO, FOLK3 VO, GCK? (At) 0, GCK7 (AN) ATS 7 10 " AT32 V0 /0 10 0 _AT34 vec vec AT36 V0, GCK4 V0, GCKa 10 0 | AT38 Ww 0 10 iio ART 0 0 10 0 ARS 10 I) 70 ii ARS CCLK GCLK 10 0 ___ ART vO V0 ii 6 ARQ 0 v0 710 10 ARTI re) V0 v0 ii ___ARTS /0, FCLK4 VO, FCLK4 NG. Ne ___ARIS vO (D2) /0 (D2) io 70 |__ARI7 0 v0 10 6 "ARQ V0 vO 1/0 (D8) 70 (D6) AR21 vO vO NG Ne "ARS V0 0 10 16 AR25 vO v0 10 10 AR27 VO v0 Wee vee "_AR2g 0 vO 0, GCK6 (DOUT) 1/0, GCK6 (DOUT) ___ARS1 vo vo NG. Ne ___AR33 v0 0 | 9 OD 70 (1) ___ARSS DONE DONE "ART NC. NC. 0 7 L AR39 VO vO N.C. N.C. _____APe VO. vo Nc. NG. AP4 vec vec APG VO (D0, DIN) VO (DO, DIN) 1/0 (D3) 1/0 (D3) APS NC. N.C. 70 6 AP10 e) 0 | 10 76 | API2 V0 | v0 | 4-166 July 30, 1996 (Version 1.03)$< XILINX PG411 Pin XC4036EX/XL XC4044EX/KL PG411 Pin XC4036EX/XL XC4044EX/XL AP14 vO vO AH6 vO vO AP16 vO vO AH34 vO vO AP18 7) vO AH36 vo vo AP20 VO (D4) VO (D4) AH38 VO vO AP22 vO vO AGI vO vO AP24 VO (D5) VO (DS) AG3 vO vO AP26 vO vO AGS VO 7) AP28 vO ie) AG35 vO vO AG37 vO vO ie) VO AG39 vO vO VO, GCKS VO, GCK5 AF2 N.C. N.C. GND GND AF4 GNO GND i AF6 vO vO AF34 V0 vO VO (A3) VO (A3) AF36 GND GND N.C. NC. AF38 N.C. N.C. 0, TDO 0, TDO AE1 vO V0 vO vO AES vO vO vO vO AES V0 VO AN33 PROGRAM PROGRAM AE35 vO vO AN35 v0 10 AE37 vO vO AN37 vO vO AE39 i) vO AN39 vO VO AD2 VO (Aa) VO (A4) AM2 vO vO AD4 VO (A21) VO (A214) AM4 vO vO AD6 vO ie) AM6 vO vO AD34 vO vO AM8 vO is) AD36 vO vO AM32 VO (D7) VO (D7) AD38 VO vO AM34 vO VO ACI vO vO AM36 vO ie) ae V6. AM38 VO vO ACS vO | Te) AL1 GND GND AC35 vO vO AL3 vO vO AC37 vO vO AL5 vO vO AL7 vO vO AL33 vO vO AL35 N.C. N.C. AB6 vO AL37 vO vO AB34 vo | AL39 vcC ee AB36 vO [ AB38 0 AK4 vO vO AAI GND GND AK6 VO (C81, A2) VO (C81, A2) AA3 VO (A6) VO (A6) AK34 vO vO AAS VO (A20) VO (A20) AK36 vO vO AA35 vO vO NC. | AA39 vcc VCC AS vO vO Y2 VO (AQ) VO (A9) AJS N.C. N.C. 4 GND GND AJ35 vO is) Y6 VO (A7) VO (Av) Al37 | vO vO Y34 vO vO AJ39 GND GND Y36 GND GND AH2 vO ie) Se Woo. AH4 vO vO July 30, 1996 (Version 1.03) 4-167XC4000 Series Field Programmable Gate Arrays PG411 Pin XC4036EX/XL XC4044EX/XL | W3 Bia Sak \/O {A8) Ee es vO(NIT) | VO (A8) v34 VO VO v36 VO v0 38 VO 0 Ut vO vO U3 0 (A10) 1/0 (A10) | US vO 0 U35 VO vO | U3? vO yO U39 vO vO T2 | V0 (A18) VO (A18) [74 vO VO | 6 VO VO 134 vO vO T36 vO V0 T38 vO VO AY VO (A11) VO (A11) R3 N.C. N.C. RS vO vO R35 0 0 R37 VO VO R39 vO vO P2 vO 0 P4 GND GND | P 0 VO [P34 vO vO P36CS GND GND P38 N.C. N.C. Ni vO vO r NB NC. N.C. NS vO VO | N35 ie) vO N37 vO vO N39 vO vO M2 vO VO M4 vo VO M6 vO vO M34 vO vO M36 vO vO M38 vO VO U1 GND GND vO vo vcc vec PG411 Pin K2 K4 K6 XC4036EX/XL vO ie) vO vO vcc vO vO vO vO vO GND vO VO (A12) vO VO, GCK1 (A16) vO N.C. vO vO vO 0 (A13) N.C. VO, GCK8 (A15) VO, TCK VO 1 (M2) vO vO ie) N.C. GND VO (A17) V0 VO Te) vO vO vo vO XC4044EX/XL vO vO vO vO vec vO vO vO Me) vO GND vO VO (A12) VO VO, GCKT (A16) V0 NC. vO vO vO VO (A13) N.C. 0, GCK8 (A15) VO, TCK V0 1 (M2) Ke Te) VO N.C. GND /O (A17) vO vO V0 vO vO vO he) VO July 30, 1996 (Version 1.03)$= XILINX PG411 Pin XC4036EX/XL XC4044EX/XL PG411 Pin XC4036EX/XL XC4044EX/KL E5 VO (A14) VO (A14) C33 N.C. : N.C. E7 N.C. N.C. C35 vO : vO E9 VO vO C37 I/O (HDC) ; VO (HDC) VO, TMS VO, TMS C39 vcc vcc VO VO : B2 VO, TDI : I/O, TDI vO VO : B4 vO vo vo VO B6 N.C. N.C. vO vO B8 /O VO VO VO B10 VO vO N.C. N.C. B12 VO VO VO vo Bi4 vO vO VO B16 VO vO VO 17,0) Bi8 vO VO VO B20 vO VO VO B22 vO vO | (MO) B24 \ vo vO N.C. .C. B26 VO vO Vo B28 VO vo vO B30 vO VO vO B32 WO VO vcc B34 N.C. N.C. B36 VO, GCK2 1/0, GCK2 i vo B38 vO vO N.C. CC, A3 vec VCC GND AS VO vO vO A7 vo vO vO Ag GND GND GND Atl vcc VCC vO A13 N.C, N.C. 0 A15 vO vO GND A17 vO VO 1/@) A1g GND GND A2i Vcc vcc A23 vO VO GND GND A25 VO vO VO, GCK3 VO, GCK3 A27 VO VO vO VO A2g9 GND GND GND GND [At vec VCC VO VO A33 VO VO fe) VO A35 VO Vo A37 GND GND vo vO | A3g O (M1) O (M1) VO, FCLK1 VO, FCLK1 3/26/96 VO VO Note: Shaded pins should be taken into account when de- VO v0 signing PC boards, in case of future replacement by differ- VO vO ent devices. vo yO Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. N.C. N.C, Viewed from the top side, the pins start at the top row and vO vO go from the right edge to the left edge. VO, FCLK2 VO, FCLK2 vO vO July 30, 1996 (Version 1.03) 4-169XC4000 Series Field Programmable Gate Arrays BG432 Package Pinouts BG432 Pin XC4036EX XC4036XL XC4044EX XC4044XL XC4052XL 8G432 Pin| XC4036EX XC4044EX XC4082XL XC4036XL xC4044XL 10 Ta a ALI vec VGC VEG 10 10 iO AL2 GND GND GND ALS GND GND GND i0 1G 1D ALA vo vo vO 0, GCK3 0, GCK3 V0, GCK3 ALS /0 vO vO GND ND GND ALG v0 V0 v0 GND GND ND AL? GND GND GND GND GND END ALS vO vO vO /0 (07) 1/0 (D7) 70 (D ALS GND GND GND voG VOC WCE AL10 vO uo vO 0, GCK4 0, GCKA 70, GCKA ALi voc vec vec AL12 0 10 vO WO iO 7 ALIS vO V0 v0 10 6 0 ALI4 GND GND GND : nae vO V0 V0 0 V0 re) 0 V0 vO AL19 i) 0 ie) iO iG 1 AL20 10 /0 10 10 70 0 ~AL2A voc VCC VCC , AL22 0 10 vO To 10 10 AL23 GND GND GND 0 0 0 AL24 V0 vO V0 76 0 70 AL25 GND GND GND 10 v0 6 AL26 10 vO v0 AL27 10 vO VO TO WG 10 | AL28 vO vO vO 0 vO 6 / AL29 GND GND GND v0 vO 10 AL30 GND GND GND 10 6 0 AL31 VCC ete! VGC 70 76 10 AKI GND GND GND AK2 GND GND GND v0 10 70 AK3 vO vO V0 , , AKA /0 0 v0 VOC Vee vee AKS vo VO WO VO,GCK2 | VO,GCK2 | VO, GCK2 AK6 V0 V0 vO GND GND GND AK? v0 10 10 10 10 70 AKB v0 vO 0 10 (0 0 AKO v0 vO JO DONE v0 AK12 V0 VO yO ~_AKIS v0 0 0 10 AKi4 0 0 V0 iO AK15 | vO vO vO | AK16 | VO (INIT) VO (INIT) Vo (NIT) vO mi ee : VGC AKi8 0 0 vO 10 ~~ AKT9 v0 vO 70 0 | AK20 vO vO vO 0 / AKaq vO vO vO 10 AK22 vO vO Ke) GND AK23 10 vO vO 70 4-170 July 30, 1996 (Version 1.03)$= XILINX BG432 Pin) XC4036EX XC4044EX XC4052XL_ | BG432 Pin); XC4036EX XC4044EX XC4052XL XC4036XL XC4044XL : XC4036XL | XC4044XL AH18 vO vO vO AB3 VO VO vO AB4 vO VO vO AH20 vO vO vO AB28 VO vO VO AH21 Vcc voc voc AB29 VO, FCLK2 VO, FCLK2 VO, FCLK2 AH22 vO vO vO : AB30 vO VO vO : AB31 vO VO /O AH24 vO vO : vO AAI vcc vcc vcc AH25 vO vO vO AA2 VO (D5) /O (D5) /O (D5) AH26 vO vO vO AAS VO vO vO AH27 vO VO (HDC) VO (HDC) AA4 VCC VCC VCC AH28 1 (MO) | 1 (MO) AA28 VCC vec VCC AH29 (M1) O (M1) O (M1) AA29 Me) ie) VO AH30 VO ie) vO AA30 vO vO /0 AH31 ie) vO vO AAS1 VCC VCC VCC AG2 VO vO vO Y2 VO vO vO AG3 VO vO vO Y3 AG4 VO, GCK5 VO, GCKS5 VO, GCKS Y4 AG28 vo vO vo AG29 vO vO VO AG30 vO vO VO AG31 vo vo vO AF1 1/0 (D6) VO (D6) \/O (D6) AF2 vO vO VO AF3 vO vO vO vo AF4 vO vO vO AF28 vO vO 0 vO GND VO vO vO vO GND vO vO vO VO vO VO VO vo vO vo vO vO GND GND VO (D4) VO (D4) VO (D4) vO vO vO ie) VO VO VO vO VO (D3) VO (D3) VO (D3) GND GND GND VO VO vO GND GND GND vo vO vO vO vo vo VO vO VO vO vo vO GND GND GND VO VO vO VO, FCLK3 VO, FCLK3 . VO, FCLK3 VO vo VO VO VO vO vO vO July 30, 1996 (Version 1.03) 4-171XC4000 Series Field Programmable Gate Arrays BG432 Pin| XC4036EX XC4036XL R3 vO R4 vO vO vo vo vO GND vO vO vO vO vO vO GND vO VO vcc VO (D2) vO Vcc VCC vO VO VCC VO vO, FCLK4 vo vO VO, FCLK1 vO VO, TMS vO GND vO vO vO vO vO VO GND vO VO XC4044EX XC4044XL vO vO vO vO vO vO GND vO vO vO vO VO vO GND vO vO vec VO (D2) vO voc vcc VO vO vcc VO VO, FCLK4 vO VO VO, FCLK1 vO VO, TMS vO GND VO VO VO VO vO vO GND vO vO XC4052XL vO vO vO vO vO vO GND vO VO vO vO VO VO GND vO VO vec 1/0 (D2) VO Vcc vcc vO vO VCC vO VO, FCLK4 vO vO VO, FCLK1 VO VO, TMS VO GND vO vO vO vO vO vo GND VO vo BG432 Pin H3 H4 XC4036EX XC4036XL vO vO vO vO vO vO GND vO VO VO VO vO GND vO RDY, VO vO vO VO vO vO vO vO vO vO VO, GCK6 (DOUT) CCLK VO, GCK7 (A1 vO vO vO vO VCC vO vO ie) GND VO (A8) VO (A18) vO vcc vO VO (A12) XC4044EX XC4044XL /0 vO vO /0 /0 /0 GND VO VO vO Vo vO GND VO RDY. vO vO vO vO vO VO vO VO Vo VO, GCK6 CCLK VO, GCK7 VO vO vO vO VCC vO vO vO GND 0 (A8) W/O (A18) vO voc vO VO (At i XC4052XL vO vO vO VO vo vO GND VO VO (D1) vO vO VO GND vO RDY; VO vo VO VO VO vO vo vo VO vO VO, GCKE CGLK VO, GCK7 (Al) VO (A3) vO vO vO vcc vo vO vO GND vO VO (A18) vO vcc vO VO (A12) 4-172 July 30, 1996 (Version 1.03)$< XILINX BG432 Pin) XC4036EX xC4044EX XC4052XL BG432 Pin| XC4036EX XC4044EX XC4052XL XC4036XL XC4044XL XC4036XL XC4044XL D25 VO vO vO Bi9 VO (A10) VO (A10) VO (A10) a6 NCE GC iC. B20 vO vO vO D27 VO vO 0 ! D28 WO, GCK8 (A15) | /0, GCK8 (A15)| 0, GCK8 (A15) | B22 vO vO vO D290, GCK1 (A16)| 1/0, GCK1 (A16)| 1/0, GCK1 (A16) B23 vO vO VO D30 VO, TDI VO, TDI VO, TDI B24 vO vO vO D31 VO, TCK VO, TCK VO, TCK Z oO Ct GND GND GND | B26 VO (A13) VO (A13) VO (A13) c2 VO (DO, DIN) | VO (D0, DIN) | 1/0 (DO, DIN) B27 vO VO VO C3 VCC vcc vcc B28 vO vO vO C4 0, TDO 0, TDO 0, TOO B29 V0 VO vO C5 vO vO re) B30 GND GND GND C6 vO vO vo | B31 GND GND GND C7 vO VO vO Al VCC vec VCC cB N.C. NC. NC. A2 GND GND GND ce vO VO vO | A3 GND GND GND C10 vO vO vO Ne v ct ie) vO vO AS vO (CS1, A2) | VO(CS1,A2) | VO (CS1, A2) C12 vO vo vO | AG vO vO vO , C13 vO Te) V0 | AT GND GND GND | C14 0 (A4) VO (A4) VO (A4) ic oO Vo VO (A21) VO (A21) VO (A21) AQ GND GND GND A10 VO vO vO t Ail VveG VCC VCC C18 VO (A19) VO (A19) VO (A19) Ai2 vO 0 ie) C19 VO (A114) 0 (A11) VO(AI1) | Ai3 VO (A5) VO (A5) VO (AS) C20 vO 0 vO Ai4 GND GND GND cat ie) vO vO c C22 vO vO vO Ai6e | VO(A7) VO (A7) VO (A7) C23 vO | VO vO AI7 | VO (A9) VO (A9) 1/0 (A9) C24 ie) VO vO Ais. | GND GND GND C25 vO vO vO 7 Aig VO vO VO C26 VO 0 vo A20 vO 0 vO C27 vO vO vO A24 VGC vcc vcc C28 10 (A14) VO (A14) VO (A14) A22 vO re) vO C29 VCC VCC VCC A23 GND GND GND C30 VO (A17) VO (A17) VO(A17) A24 VO v0 vO C31 GND GND GND, A25 GND GND GND | Bt GND GND | ~~ GND A26 V0 vO [fe B2 GND GND GND ; A27 vO vO VO B3 VO (AO, WS) | 1/0 (AO, WS) | 1/0 (AO, WS) B4 VO 0 VO | BS 0 VO vO : A30 GND GND GND BE VO vO vo AST VCC VCC vec a7 vO vO VO | gp e/96 Note: Shaded pins should be taken into account when de- B10 vO vO vO signing PC boards, in case of future replacement by differ- B11 vo vO vO ent devices. vO vO (A6) B18 VO B13 re) ie) B14 vO VO Te) Bi5 VO (A20) VO (A20) VO (A20) | Bi i/O (A6) 0 (A6) vO. es VO vO 1 Note: Viewed from the bottom side, the package pins start at the top row and go from the left edge to the right edge. Viewed from the top side, the pins start at the top row and go from the right edge to the left edge. July 30, 1996 (Version 1.03) 4-173XC4000 Series Field Programmable Gate Arrays Product Availability Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at hitp://www.xilinx.com for the latest revision of the specifications. Table 25: Component Availability Chart for XC4000E FPGAs PC PQ, VQ:PG TQ PG| PQ/CB| PG| CB PQ/HQ! PG|BG:CB PQ HQ|PG|HQ 84 | 100/100 120 144 156) 160 | 164 | 191 | 196 | 208 | 208 | 223 | 225 | 228 240 | 240 | 299 | 304 cl, ct;cl: cl clicl;ct. cl ce; cic C XC 4025E Cc = Commercial, T = 0 to +85 C | = Industrial, T; = -40 to +100 C M = Mil Temp, Tg = -55 to +125 C B = MIL-STD-883C Class B, Te = -55 to +125 C Shaded device/package combinations are not supported. 4-174 July 30, 1996 (Version 1.03)$= XILINX Table 26: Component Availability Chart for XC4000EX FPGAs Speed |! 40208 HaQ240 PG299 HQ304 BG352 PG411 BG432 Grade -4 Cl Ci Cl Cl Cc! XC4028EX 3 Cc Cc C Cc Cc XC4036EX [3 XC4044EX | -3 C = Commercial, T; = 0 to +85 C | = Industrial, Ty = -40 to +100 C M = Mil Temp, Tc, = -55 to +125 C B = MIL-STD-883C Class B, Tc = -55 to +125 Shaded device/package combinations are not supported. Table 27: Component Availability Chart for XC4000L and XC4000XL FPGAs PC TQ PQ HQ = BG PQ HQ PG HQ PG BG PG 84 176 | 208 | 208 225 | 240 | 240 | 299 | 304 411 | 432 | 475 Cc Cc XC4005L Cc Cc XC4010L XC4013L XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL C = Commercial, T, = 0 to +85 C | = Industrial, Ty = -40 to +100 C M = Mil Temp, To = -55 to +125 C B = MIL-STD-883C Class B, Tc = -55 to +125 C Shaded device/package combinations are not supported. Speed grades for the XC4000XL have not yet been determined. July 30, 1996 (Version 1.03) 4-175XC4000 Series Field Programmable Gate Arrays User I/O Per Package Maximum available user |/O for each device/package combination is shown in Table 28 - Table 30. Pinout tables for XC4000-Series devices follow. Pinout data is offered in two forms, as device-specific and package-specific tables. Device-specific tables include all packages for each XC4000-Series device. They follow the pad locations around the die, and include boundary scan register locations. Package-specific tables include all XC4000-Series devices available in a given package. These tables are especially useful in determining which pads should be avoided, in case of a future transition to a different device in the same package. Ail pinouts defined at the time of publication are included in these tables. Additional information may be available. Call your local sales office or see the Xilinx WEBLINX at http:/Avww.xilinx.com for the latest information. Table 28: Maximum User I/O for XC4000E Device/Package Combinations No.of Package || xc4o03E | XC4005E | XC4006E | XC4008E XC4010E XC4013E | XC4020E | XC4025E_ Pins Code 84 PLCC (PC) 61 61 61 61 61 100 PQFP (PQ) 77 77 VQFP (VQ) 77 oe 120. PGA(PG) 80 144. TQFP (TQ) 156. PGA(PG) 160 | PQFP (PQ) 164 | CBFP (CB) 191 | PGA(PG) 196 | CBFP (CB) 208 | PQFP (PQ) HOFP (HQ) 223. | PGA(PG) 192 225 | BGA (BG) 228 | CBFP (CB) a 192 240 | PQFP (PQ) HQFP (HQ) 193 299 | PGA (PG) ; 256 304 | HOFP (HQ) 256 Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the MO and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) 4-176 July 30, 1996 (Version 1.03)$< XILINX Table 29: Maximum User I/O for XC4000EX Device/Package Combinations No. of Pins XC4028EX XC4036EX XC4044EX 208 HQFP (HQ) 160 240 HOFP (HQ) 193 299 PGA (PG) 256 304 HOFP (HQ) 256 256 352 BGA (BG) 256 ait PGA (PG) 288 320 432 BGA (BG) 288 320 Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this tabie, the MO and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) Table 30: Maximum User 1/O for XC4000L and XC4000XL Device/Package Combinations No.of Package Pins XC4005L | XC4010L XC4013L | XC4028XL | XC4036XL | XC4044XL | XC4052XL | XC4062XL 84 | PLCC(PC)|| 61 61 TQFP (TQ) PQFP (PQ) HQFP (HQ) BGA (BG) PQEFP (PQ) HOQFP (HQ) PGA (PG) HQFP (HQ) 256 BGA (BG) PGA (PG) 288 320 352 BGA (BG) 288 320 352 PGA (PG) 384 Note: This table includes standard user-programmable I/O. {t also includes the TDI, TCK, and TMS pins, which can function as user-programmable i/O if not used for boundary scan. In addition to the V/O listed in this table, the MO and M2 pins can be used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special library symbols. The XACT software does not use them by default. (See Table 18 on page 47.) July 30, 1996 (Version 1.03) 4-177XC4000 Series Field Programmable Gate Arrays Ordering Information Example: XC4013E-3HQ240C Device Type -_-___ Temperature Range Speed Grade __ C = Commercial (Tj = 0 to +85C) 6 | = Industrial (Tj = -40 to +100C) 5 M = Military (Te = -55 to+125C) -4 3 Number of Pins Package Type PC = Plastic Lead Chip Carrier BG = Ball Grid Array PQ = Plastic Quad Flat Pack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flat Pack HQ = High Heat Dissipation Quad Flat Pack TQ = Thin Quad Flat Pack MQ = Metal! Quad Flat Pack CB = Top Brazed Ceramic Quad Flat Pack X6750 4-178 July 30, 1996 (Version 1.03)