2002 Microchip Technology Inc. DS21713A-page 1
M24AA32A/24LC32A
Device Selection Table
Features
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 1 µA standby current (max.) (I-temp)
• Organized as 4 blocks of 8K bits (32K bit)
• 2-wire serial interface bus, I2C™ compatible
• Cascadable for up to eight devices
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA32A) and 400 kHz (24LC32A)
compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 32 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, and MSOP package
• Available temperature ranges:
Description
The Microchip Technology Inc. 24AA32A/24LC32A
(24XX32A*) is a 32 Kbit Electrically Erasable PROM.
The device is organized as four blocks of 8K x 8-bit
memory with a 2-wire serial interface. Low voltage
design permits operation down to 1.8V with standby
and active currents of only 1 µA and 1 mA respectively.
It has been developed for advanced, low power appli-
cations such as personal communications or data
acquisition. The 24XX32A also has a page-write capa-
bility for up to 32 bytes of data. Functional address lines
allow up to eight devices on the same bus, for up to
256 Kbits address space. The 24XX32A is available in
the standard 8-pin PDIP, surface mount SOIC, TSSOP
and MSOP packages.
Package Types
Block Diagram
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
24AA32A 1.8-5.5 400 kHz(1) I
24LC32A 2.5-5.5 400 kHz I, E
Note 1: 100 kHz for VCC <2.5V
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
24XX32A
A0
A1
A2
Vss
1
2
3
4
8
7
6
5
Vcc
WP
SCL
SDA
PDIP/SOIC/TSSOP/MSOP
24XX32X
WP
Vcc
A0
A1
SCL
SDA
Vss
A2
1
2
3
4
8
7
6
5
ROTATED TSSOP
(24AA32AX/24LC32AX)
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
I/O
CONTROL
LOGIC
I/O
MEMORY
CONTROL
LOGIC
A0 A1 WPA2
SCL
SDA
VCC
VSS
32K I2C™ Serial EEPROM
*24XX32A is used in this document as a generic part number for the 24AA32A/24LC32A devices.
24AA32A/24LC32A
DS21713A-page 2 2002 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temp. with power applied ..........................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
1.1 DC Characteristics
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
DC CHARACTERISTICS
VCC = +1.8V to +5.5V
Industrial (I): TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Param.
No. Sym Characteristic Min Typ Max Units Conditions
D1 VIH WP, SCL and SDA pins —————
D2 — High level input voltage 0.7 VCC ——V—
D3 VIL Low level input voltage — — 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt
trigger inputs
0.05 VCC ——V(Note 1)
D5 VOL Low level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V
D6 ILI Input leakage current ——±10µAV
IN =.1V to VCC
D7 ILO Output leakage current ——±10µAV
OUT =.1V to VCC
D8 CIN,
COUT
Pin capacitance
(all inputs/outputs)
— — 10 pF VCC = 5.0V (Note 1)
T
AMB = 25°C, FCLK = 1 MHz
D9 ICC write Operating current —0.1 3mAVCC = 5.5V, SCL = 400 kHz
D10 ICC read — 0.05 1 mA —
D11 ICCS Standby current —
—
0.01
—
1
5
µA
µA
Industrial
Automotive
SDA = SCL = VCC
WP = VSS
Note 1: This parameter is periodically sampled and not 100% tested.
2: Typical measurements taken at room temperature.
2002 Microchip Technology Inc. DS21713A-page 3
24AA32A/24LC32A
1.2 AC Characteristics
AC CHARACTERISTICS
VCC = +1.8V to +5.5V
Industrial (I): TAMB = -40°C to +85°C
Automotive (E): TAMB = -40°C to +125°C
Param.
No. Sym Characteristic Min Max Units Conditions
1F
CLK Clock frequency —
—
400
100
kHz 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
2THIGH Clock high time 600
4000
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
3T
LOW Clock low time 1300
4700
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
4T
RSDA and SCL rise time
(Note 1)
—
—
300
1000
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
5T
FSDA and SCL fall time — 300 ns (Note 1)
6T
HD:STA START condition hold time 600
4000
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
7T
SU:STA START condition setup time 600
4700
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
8T
HD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 100
250
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
10 TSU:STO STOP condition setup time 600
4000
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
11 TAA Output valid from clock
(Note 2)
—
—
900
3500
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
12 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
1300
4700
—
—
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA32A)
13 TOF Output fall time from VIH min-
imum to VIL maximum
20+0.1CB
—
250
250
ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.5V (24AA32A)
14 TSP Input filter spike suppression
(SDA and SCL pins)
—50ns(Notes 1 and 3)
15 TWC Write cycle time (byte or
page)
—5ms—
16 — Endurance 1M — cycles 25°C, VCC = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on Microchip’s website:
www.microchip.com.
24AA32A/24LC32A
DS21713A-page 4 2002 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
FIGURE 1-2: BUS TIMING START/STOP
7
524
8910
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
76
D4
10
START STOP
SCL
SDA
2002 Microchip Technology Inc. DS21713A-page 5
24AA32A/24LC32A
2.0 FUNCTIONAL DESCRIPTION
The 24XX32A supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
START and STOP conditions, while the 24XX32A
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter-
mines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first-in
first-out (FIFO) fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX32A) will leave the data
line HIGH to enable the master to generate the STOP
condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
24AA32A/24LC32A
DS21713A-page 6 2002 Microchip Technology Inc.
3.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device (Figure 3-2). The
control byte consists of a four bit control code; for the
24XX32A this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX32A devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 3-3). Because
only A11...A0 are used, the upper four address bits are
don’t care bits. The upper address bits are transferred
first, followed by the less significant bits.
Following the start condition, the 24XX32A monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX32A will select a read or
write operation.
FIGURE 3-2: CONTROL BYTE FORMAT
3.7 Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 256K bits by
adding up to eight 24XX32A's on the same bus. In this
case, software can use A0 of the control byte as
address bit A12, A1 as address bit A13, and A2 as
address bit A14. It is not possible to sequentially read
across device boundaries.
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
1 0 1 0 A2 A1 A0SACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1010A
2
A
1A
0R/W XXXXA
11
A
10 A
9
A
7
A
0
A
8••••••
CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE
CONTROL
CODE
CHIP
SELECT
BITS
X = Don’t Care Bit
2002 Microchip Technology Inc. DS21713A-page 7
24AA32A/24LC32A
4.0 WRITE OPERATIONS
4.1 Byte Write
Following the start condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the address pointer of
the 24XX32A. The next byte is the least significant
address byte. After receiving another acknowledge sig-
nal from the 24XX32A the master device will transmit
the data word to be written into the addressed memory
location. The 24XX32A acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and during this time the 24XX32A
will not generate acknowledge signals (Figure 4-1). If
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte write command, the internal address
counter will point to the address location following the
one that was just written.
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX32A in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 31 additional bytes
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a stop condition. After receipt of each word,
the five lower address pointer bits are internally incre-
mented by one. If the master should transmit more than
32 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an inter-
nal write cycle will begin (Figure 4-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
4.3 Write Protection
The WP pin allows the user to write protect the entire
array (000-FFF) when the pin is tied to VCC. If tied to
VSS or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write com-
mand (Figure 3-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write
cycle.
Note: Page write operations are limited to writ-
ing bytes within a single physical page,
regardless of the number of bytes actu-
ally being written. Physical page bound-
aries start at addresses that are integer
multiples of the page buffer size (or
‘page size’) and end at addresses that
are integer multiples of [page size - 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to
the beginning of the current page (over-
writing data previously stored there),
instead of being written to the next page
as might be expected. It is therefore
necessary for the application software to
prevent page write operations that
would attempt to cross a page boundary.
24AA32A/24LC32A
DS21713A-page 8 2002 Microchip Technology Inc.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: PAGE WRITE
XXX
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
S1010 0
A
2A
1A
0P
X
XXX
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA BYTE 31
A
C
K
X = don’t care bit
S101 0 0
A
2A
1A
0PX
2002 Microchip Technology Inc. DS21713A-page 9
24AA32A/24LC32A
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 5-1 for
flow diagram.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
24AA32A/24LC32A
DS21713A-page 10 2002 Microchip Technology Inc.
6.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.1 Current Address Read
The 24XX32A contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX32A issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24XX32A discontinues transmission (Figure 6-1).
6.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX32A as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the
control byte again but with the R/W bit set to a one. The
24XX32A will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24XX32A to discontinue transmission
(Figure 6-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
6.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24XX32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24XX32A to transmit the
next sequentially addressed 8-bit word (Figure 6-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition. To provide sequential reads the
24XX32A contains an internal address pointer which is
incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address FFF to address 000 if the master acknowl-
edges the byte received from the array address FFF.
FIGURE 6-1: CURRENT ADDRESS READ
SP
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE DATA (n)
A
C
K
N
O
A
C
K
S
T
A
R
T
2002 Microchip Technology Inc. DS21713A-page 11
24AA32A/24LC32A
FIGURE 6-2: RANDOM READ
FIGURE 6-3: SEQUENTIAL READ
XXX
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
CONTROL
BYTE
DATA
BYTE
S
T
A
R
T
X = Don’t Care Bit
S1010AAA0
210 S1 0 10 AAA
1
210 P
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
24AA32A/24LC32A
DS21713A-page 12 2002 Microchip Technology Inc.
7.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 7-1.
TABLE 7-1: PIN FUNCTION TABLE
7.1 A0, A1, A2 Chip Address Inputs
The A0,A1,A2 inputs are used by the 24XX32A for mul-
tiple device operation. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. These
inputs must be connected to either VCC or VSS.
7.2 Serial Data (SDA)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pullup
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
7.3 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
7.4 Write Protect (WP)
This pin can be connected to either VSS, VCC or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to VSS or left floating, normal memory operation
is enabled (read/write the entire memory 000-FFF).
If tied to VCC, WRITE operations are inhibited. Read
operations are not affected.
Name PDIP SOIC TSSOP MSOP ROTATED
TSSOP Description
A0 1 1 1 1 3 Chip Address Input
A1 2 2 2 2 4 Chip Address Input
A2 3 3 3 3 5 Chip Address Input
VSS 4 4 4 4 6 Ground
SDA 5 5 5 5 7 Serial Address/Data I/O
SCL 6 6 6 6 8 Serial Clock
WP 7 7 7 7 1 Write Protect Input
VCC 8 8 8 8 2 +1.8V to 5.5V Power Supply
2002 Microchip Technology Inc. DS21713A-page 13
24AA32A/24LC32A
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
8-Lead TSSOP Example:
24LC32A
I/PNNN
YYWW
24LC32A
I/SNYYWW
NNN
XXXX
YYWW
NNN
4LA
IYWW
NNN
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
8-Lead MSOP Example:
XXXXXX
YWWNNN
4L32AI
YWWNNN
8-Lead SOIC (208 mil) Example:
XXXXXXXX
XXXXXXXX
YYWWNNN
24LC32A
I/SM
YYWWNNN
Rotated TSSOP
marking will be
“4AA”
24AA32A/24LC32A
DS21713A-page 14 2002 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
2002 Microchip Technology Inc. DS21713A-page 15
24AA32A/24LC32A
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle f048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45×
f
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
24AA32A/24LC32A
DS21713A-page 16 2002 Microchip Technology Inc.
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.430.36.020.017.014BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.640.51.030.025.020LFoot Length
5.335.215.13.210.205.202DOverall Length
5.385.285.11.212.208.201E1Molded Package Width
8.267.957.62.325.313.300EOverall Width
0.250.130.05.010.005.002A1Standoff §
1.98.078A2Molded Package Thickness
2.03.080AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
α
A2
A
A1
L
c
β
φ
2
1
D
n
p
B
E
E1
.070 .075
.069 .074
1.78
1.75
1.97
1.88
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
§ Significant Characteristic
2002 Microchip Technology Inc. DS21713A-page 17
24AA32A/24LC32A
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
3.103.002.90.122.118.114DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033A2Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
α
A2
A
A1
L
c
β
f
1
2
D
n
p
B
E
E1
Foot Angle f048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
24AA32A/24LC32A
DS21713A-page 18 2002 Microchip Technology Inc.
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
p
A
A1
A2
D
L
c
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037.035FFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
7
7
.004
.010
0
.006
.012
(F)
β
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff §
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016
.114
.114
.022
.118
.118
.002
.030
.193
.034
MIN
p
n
Units
.026
NOM
8
INCHES
1.000.950.90.039
0.15
0.30
.008
.016
6
0.10
0.25
0
7
7
0.20
0.40
6
MILLIMETERS*
0.65
0.86
3.00
3.00
0.55
4.90
.044
.122
.028
.122
.038
.006
0.40
2.90
2.90
0.05
0.76
MINMAX NOM
1.18
0.70
3.10
3.10
0.15
0.97
MAX
8
α
E1
E
B
n 1
2
φ
§ Significant Characteristic
.184 .200 4.67 .5.08
2002 Microchip Technology Inc. DS21713A-page 19
24AA32A/24LC32A
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
013001
24AA32A/24LC32A
DS21713A-page 20 2002 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
To : Technical Publications Manager
RE: Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21713A
24AA32A/24LC32A
2002 Microchip Technology Inc. DS21713A-page21
24AA32A/24LC32A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA32A: 1.8V, 32 Kbit I2C Serial EEPROM
24AA32AT: 1.8V, 32 Kbit I2C Serial EEPROM
(Tape and Reel)
24AA32AX 1.8V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
24AA32AXT 1.8V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
24LC32A: 2.5V, 32 Kbit I2C Serial EEPROM
24LC32AT: 2.5V, 32 Kbit I2C Serial EEPROM
(Tape and Reel)
24LC32AX 2.5V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
24LC32AXT 2.5V, 32 Kbit I2C Serial EEPROM in
alternate pinout (ST only)
Temperature
Range:
I = -40°C to +85°C
E = -40°C to +125°C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
SM = Plastic SOIC (208 mil body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
Examples:
a) 24AA32A-I/P: Industrial Temperature,
PDIP package
b) 24AA32A-I/SN: Industrial Temperature,
SOIC package
c) 24AA32A-I/SM: Industrial Temperature,
SOIC (208 mil) package
d) 24AA32AX-I/ST : Industrial Temperature,
Rotated TSSOP package
a) 24LC32A-I/P: Industrial Temperature,
PDIP package
b) 24LC32A-E/SN: Extended Temperature,
SOIC package
c) 24LC32A-E/SM: Extended Temperature,
SOIC (208 mil) package
d) 24LC32AX - E/ST: Extended Temperature,
Rotated TSSOP package
24AA32A/24LC32A
DS21713A-page 22 2002 Microchip Technology Inc.
NOTES:
2002 Microchip Technology Inc. DS21713A - page 23
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS21713A-page 24 2002 Microchip Technology Inc.
M
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01/18/02
*DS21713A*
WORLDWIDE SALES AND SERVICE
