74VHC74MX_NL - Fairchild Semiconductor

October 1992

Revised February 2005

74VHC74 Dual D-Type Flip-Flop with Preset and Clear

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

General Descript ion

The VHC74 is an advanced high speed CMOS Dual D-

Type Flip-Flop fabricated with silicon gate CMOS technol-

ogy. It achieves the high speed operation similar to equiva-

lent Bipolar Schottky TTL while maintaining the CMOS low

power diss ipat ion. T he signa l le vel ap pli ed to the D input i s

transferre d to th e Q o utp ut d ur i ng t he p ositi ve go ing tra nsi-

tion of the CK pulse. CLR a nd PR ar e independent of the

CK and are accomplished by setting the appropriate input

LOW.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regar d to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery backup. This cir-

cuit preven ts device destruc tion du e to mismatch ed supply

and input voltages.

Features

■High Speed: fMAX

170 MHz (typ) at TA

■High noise immunity: VNIH

VNIL

28% VCC (min)

■Power down protection is provided on all inputs

■Low power dissipation: ICC

A (max) at TA

■Pin and function compatible with 74HC74

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and Reel. Specify by ap pending th e s uffix let t er “X” to the o rdering c ode.

Pb-Free package per JEDED J-STD-020B.

Note 1: “_NL” indicat es Pb-Free package (per JED EC J -STD-0 20B). Devic e availa ble in Tape and Reel only.

Order Number Package Package Description

Number

74VHC74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC74MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC74SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC74MTC MTC14 14-Lead Thin S hrink Small Outline Package (TSSOP), JE DEC MO-153, 4.4mm Wide

74VHC74MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHC74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74VHC74

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions Truth Table

Note 2: This co nfigu ratio n is nons table ; that is, it will not pers ist w hen p re-

set and clear inputs return to their inactive (HIGH) state.

Pin Names Description

D1, D2Data Inputs

CK1, CK2Clock Pulse Inputs

CLR1, CLR2Direct Clear Inputs

PR1, PR2Direct Preset Inputs

Q1, Q1, Q2, Q2Output

Inputs Outputs Function

CLR PR DCK Q Q

L H X X L H Clear

HLXX H L Preset

L L X X H (Note 2) H (Note 2)

HHL



HHH



HHX



QnQnNo Change

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74VHC74

Absolute Maximum Ratings(Note 3) Recommended Operating

Conditions (Note 4)

Note 3: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading varai-

bles. F airchil d does not r ecom mend operatio n outside databo ok sp ecifica-

tions.

Note 4: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



0.5V to



7.0V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

20 mA

DC Output Current (IOUT)

25 mA

DC VCC/GND Current (ICC)

50 mA

Storage Temperature (TSTG)



C to



150

Lead Temperature (TL)

Soldering (10 seconds) 260

Supply Voltage (VCC) 2.0V to 5.5V

Input Voltage (VIN)0V to



5.5V

Output Voltage (VOUT)0V to V

Operating Temperature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

3.3V

0.3V 0

100 ns/V

VCC

5.0V

0.5V 0

20 ns/V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level Input 2.0 1.50 1.50 V

Voltage 3.0



5.5 0.7 VCC 0.7 VCC

VIL LOW Level Input 2.0 0.50 0.50 V

Voltage 3.0



5.5 0.3 VCC 0.3 VCC

VOH HIGH Level Output 2.0 1.9 2.0 1.9 VIN

VIH IOH



Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH



4 mA

4.5 3.94 3.80 IOH



8 mA

VOL LOW Level Output 2.0 0.0 0.1 0.1 VIN

VIH IOL

Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL

4 mA

4.5 0.36 0.44 IOL

8 mA

IIN Input Leakage Current 0



5.5

0.1

1.0

5.5V or GND

ICC Quiescent Supply Current 5.5 2.0 20.0

VCC or GND

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74VHC74

AC Electrical Characteristi cs

Note 5: CPD is defined as t he value of t he internal equivalent ca pac itan c e w hich is c alculate d f rom the o perating c urrent consum pt ion without load. Average

operat ing cur rent can be obta ined from th e equation: ICC (opr.)

CPD * VCC * fIN



ICC/2 (per F/F).

AC Operating Requirements

Note 6: VCC is 3.3

0.3V or 5.0

0.5V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

fMAX Maximum Clock 3.3

0.3 80 125 70 MHz CL

15 pF

Frequency 50 75 45 CL

50 pF

5.0

0.5 130 170 110 MHz CL

15 pF

90 115 75 CL

50 pF

tPLH Propagation Delay 3.3

0.3 6.7 11.9 1.0 14.0 ns CL

15 pF

tPHL Time (CK-Q, Q) 9.2 15.4 1.0 17.5 CL

50 pF

5.0

0.5 4.6 7.3 1.0 8.5 ns CL

15 pF

6.1 9.3 1.0 10.5 CL

50 pF

tPLH Propagation Delay Time 3.3

0.3 7.6 12.3 1.0 14.5 ns CL

15 pF

tPHL (CLR, PR -Q, Q) 10.1 15.8 1.0 18.0 CL

50 pF

5.0

0.5 4.8 7.7 1.0 9.0 ns CL

15 pF

6.3 9.7 1.0 11.0 CL

50 pF

CIN Input Capacitance 4 10 10 pF VCC

Open

CPD Power Dissipation 25 pF (Note 5)

Capacitance

Symbol Parameter VCC

(V)

(Note 6)



C to



CUnits

Typ Guaranteed Minimum

tW(L) Minimum Pulse Width (CK) 3.3 6.0 7.0 ns

tW(H) 5.0 5.0 5.0

tW(L) Minimum Pulse Width (CLR,PR) 3.3 6.0 7.0 ns

5.0 5.0 5.0

tSMinimum Setup Time 3.3 6.0 7.0 ns

5.0 5.0 5.0

tHMinimum Hold Time 3.3 0.5 0.5 ns

5.0 0.5 0.5

tREC Minim um Recovery Time (CLR,PR) 3.3 5.0 5.0 ns

5.0 3.0 3.0

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74VHC74

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

www.fairchildsemi.com 6

74VHC74

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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74VHC74

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

www.fairchildsemi.com 8

74VHC74 Dual D-Type Flip-Flop with Preset and Clear

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.