1
®
FN7384.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL5150, EL5151, EL5250, EL5251, EL5451
200MHz Amplifiers
The EL5150, EL5151, EL5250, EL5251, and EL5451 are
200MHz bandwidth -3dB vol t age mode fee dback amplifiers
with DC accuracy of 0.01%, 1mV offset s and 10kV/V ope n
loop gains. These ampli fiers are id eally suited for appli cations
ranging from precision measurement instrumentation to high
speed video and monitor applicatio ns. Capable of operating
with as little as 1.4mA of current from a single supply ranging
from 5V to 12V, dual supplies ranging from ±2.5V to ±5.0V,
these amplifiers are also well suited for handheld , port ab le
and battery-powered equipment.
Single amplifiers are of fered in SOT -23 p ackages and duals in
a 10 Ld MSOP package for applications where board sp ace is
critical. Quad amplifiers are available in a 14 Ld SOIC
package. Addi ti onally, singles and duals are avail able in th e
industry-stand ard 8 Ld SOIC p ackage. All p art s ope rate over
the industrial temperature range of -40°C to +85°C.
Features
• 200MHz -3dB bandwidth
• 67V/µs slew rate
• Very high open loop gains 50kV/V
• Low supply current = 1.4mA
• Single supplies from 5V to 12V
• Dual supplies from ±2.5V to ±5V
• Fast disable on the EL5150 and EL5250
•Low cost
• Pb-free available (RoHS co mpliant)
Applications
•Imaging
• Instrumentation
•Video
• Communications devices
Pinouts EL5150
(8 LD SOIC)
TOP VIEW
EL5150
(6 LD SOT-23)
TOP VIEW
EL5151
(5 LD SOT-23)
TOP VIEW
EL5250
(10 LD MSOP)
TOP VIEW
EL5251
(8 LD MSOP)
TOP VIEW
EL5451
(14 LD SOIC)
TOP VIEW
1
2
3
4
8
7
6
5
-
+
NC
IN-
IN+
VS-
CE
VS+
OUT
NC
1
2
3
6
4
5
-+
OUT
VS-
IN+
VS+
IN-
CE
1
2
3
5
4
-+
OUT
VS-
IN+
VS+
IN-
1
2
3
4
10
9
8
7
5 6
-
+
-
+
INA+
CEA
VS-
CEB
INA-
OUTA
VS+
OUTB
INB+ INB-
1
2
3
4
8
7
6
5
-
+
-
+
OUTA
INA-
INA+
VS-
VS+
OUTB
INB-
INB+
OUTA
INA-
INA+
VS+
OUTD
IND-
IND+
VS-
INB+ INC+
1
2
3
4
14
13
12
11
5
6
7
10
9
8
INC-
OUTC
INB-
OUTB
-+ -+
-+ -+
Data Sheet January 16, 2008
2FN7384.7
January 16, 2008
Ordering Information
PART NUMBER PART
MARKING PACKAGE PKG. DWG. #
EL5150IS 5150IS 8 Ld SOIC MDP0027
EL5150IS-T7* 5150IS 8 Ld SOIC (Tape and Reel) MDP0027
EL5150IS-T13* 5150IS 8 Ld SOIC (Tape and Reel) MDP0027
EL5150ISZ (Note) 5150ISZ 8 Ld SOIC (Pb-free) MDP0027
EL5150ISZ-T7* (Note) 5150ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
EL5150ISZ-T13* (Note) 5150ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
EL5150IW-T7* BEAA 6 Ld SOT-23 (Tape and Reel) MDP0038
EL5150IW-T7A* BEAA 6 Ld SOT-23 (Tape and Reel) MDP0038
EL5150IWZ-T7* (Note) BAAJ 6 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038
EL5150IWZ-T7A* (Note) BAAJ 6 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038
EL5151IW-T7* BFAA 5 Ld SOT-23 (Tape and Reel) MDP0038
EL5151IW-T7A* BFAA 5 Ld SOT-23 (Tape and Reel) MDP0038
EL5151IWZ-T7* (Note) BAAK 5 Ld SOT-23 (Tape and Reel) (Pb-free) MDP0038
EL5151IWZ-T7A* (Note) BAAK 5 Ld SOT- 23 (Tape and Reel) (Pb-free) MDP0038
EL5250IY BAEAA 10 Ld MSOP MDP0043
EL5250IY-T7* BAEAA 10 Ld MSOP (Tape and Reel) MDP0043
EL5250IY-T13* BAEAA 10 Ld MSOP (Tape and Reel) MDP0043
EL5251IS 5251IS 8 Ld SOIC MDP0027
EL5251IS-T7* 5251IS 8 Ld SOIC (Tape and Reel) MDP0027
EL5251IS-T13* 5251IS 8 Ld SOIC (Tape and Reel) MDP0027
EL5251ISZ (Note) 5251ISZ 8 Ld SOIC (Pb-free) MDP0027
EL5251ISZ-T13* (Note) 5251ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
EL5251ISZ-T7* (Note) 5251ISZ 8 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
EL5251IY BAFAA 8 Ld MSOP MDP0043
EL5251IY-T7* BAFAA 8 Ld MSOP (Tape and Reel) MDP0043
EL5251IY-T13* BAFAA 8 Ld MSOP (Tape and Reel) MDP0043
EL5251IYZ (Note) BBBHA 8 Ld MSOP (Pb-free) MDP0043
EL5251IYZ-T13* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pb-free) MDP0043
EL5251IYZ-T7* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pb-free) MDP0043
EL5451IS 5451IS 14 Ld SOIC MDP0027
EL5451IS-T7* 5451IS 14 Ld SOIC (Tape and Reel) MDP0027
EL5451IS-T13* 5451IS 14 Ld SOIC (Tape and Reel) MDP0027
EL5451ISZ (Note) 5451ISZ 14 Ld SOIC (Pb-free) MDP0027
EL5451ISZ-T7* (Note) 5451ISZ 14 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
EL5451ISZ-T13* (Note) 5451ISZ 14 Ld SOIC (Tape and Reel) (Pb-free) MDP0027
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
EL5150, EL5151, EL5250, EL5251, EL5451
3FN7384.7
January 16, 2008
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage between VS and VS- . . . . . . . . . . . . . . . . . . . . 13.2V
Slewrate of Voltage between VS and VS- . . . . . . . . . . . . . . . . 1V/µs
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA
Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to VS + 0.5V
Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
BW -3dB Bandwidth AV = +1, RL = 500Ω200 MHz
AV = +2, RL = 150Ω40 MHz
GBWP Gain Bandwidth Product AV = 500 40 MHz
BW1 0.1dB Bandwidth AV = +1, RL = 500Ω10 MHz
SR Slew Rate VO = ±2.5V, AV = +2 50 67 V/µs
VO = ±3.0V, AV = 1, RL = 500Ω100 V/µs
tS0.1% Settling Time VOUT = -1V to +1V, AV = -2 80 ns
dG Differential Gain Error (Note 1) AV = +2, RL = 150Ω0.04 %
dP Differential Phase Error (Note 1) AV = +2, RL = 150Ω0.9 °
VNInput Referred Voltage Noise 12 nV/√Hz
INInput Referred Current Noise 1.0 pA/√Hz
DC PERFORMANCE
VOS Offset Voltage -1 0.5 1 mV
TCVOS Input Offset Voltage Temperature
Coefficient Measured from TMIN to TMAX -2 µV/°C
AVOL Open Loop Gain 15 56 kV/V
INPUT CHARACTERISTICS
CMIR Common Mode Input Range Guaranteed by CMRR test -3.5 +3.5 V
CMRR Common Mode Rejection Ratio 85 100 dB
IBInput Bias Current -100 20 +100 nA
IOS Input Offset Current -30 6 30 nA
RIN Input Resistance 80 170 MΩ
CIN Input Capacitance 1pF
OUTPUT CHARACTERISTICS
VOUT Output Voltage Swing Low RL = 150Ω to GND ±2.5 ±2.8 V
RL = 500Ω to GND ±3.1 ±3.4 V
IOUT Output Current RL = 10Ω to GND ±40 ±70 mA
EL5150, EL5151, EL5250, EL5251, EL5451
4FN7384.7
January 16, 2008
ENABLE (SELECTED PACKAGES ONLY)
tEN Enable Time EL5150 210 ns
tDIS Disable Time EL5150 620 ns
IIHCE CE Pin Input High Current CE = VS+1525µA
IILCE CE Pin Input Low Current CE = VS+ - 5V -1 0 +1 µA
VIHCE CE Input High Voltage for Powerdown Disable VS+ - 1 V
VILCE CE Input Low Voltage for Powerdown Enable VS+ - 3 V
SUPPLY
ISON Supply Current - Enabled (per amplifier) No load, VIN = 0V, CE = +5V 1.12 1.35 1.6 mA
ISOFF+ Supply Current - Disabled (per amplifier) -10 -1 +5 µA
ISOFF- Supply Current - Disabled (per amplifier) No load, VIN = 0V -25 -14 0 µA
PSRR Power Supply Rejection Ratio DC, VS = ±3.0V to ±6.0V 80 110 dB
NOTE:
1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz, VOUT is swept from 0.8V to 3.4V, R L is DC-coupled.
Electrical Specifications VS+ = +5V, VS- = -5V, RL = 150Ω, TA = +25°C, unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Typical Performance Curves
FIGURE 1. EL5150 FREQUENCY vs OPEN LOOP
GAIN/PHASE FIGURE 2. PHASE vs FREQUENCY FOR VARIOUS GAINS
1k 1G10k 100k 1M 10M 100M
100
80
60
40
20
0 180
135
0
-45
90
45
GAIN (dB)
FREQUENCY (Hz)
PHASE (°)
100k 1G1M 10M 100M
180
90
0
-90
-180
-270
PHASE (°)
FREQUENCY (Hz)
AV = +1
RL= 500Ω
RF = 0Ω
AV = +2
RL = 150Ω
RF = 400ΩAV = +5
RL = 500Ω
RF = 1.5kΩ
EL5150, EL5151, EL5250, EL5251, EL5451
5FN7384.7
January 16, 2008
FIGURE 3. EL5150 GAIN vs FREQUENCY FOR VARIOUS RLFIGURE 4. EL5150 GAIN vs FREQUENCY FOR VARIOUS RL
FIGURE 5. EL5150 GAIN vs FREQUENCY FOR VARIOUS RLFIGURE 6. EL5150 GAIN vs FREQUENCY FOR VARIOUS CL
FIGURE 7. EL5150 GAIN vs FREQUENCY FOR VARIOUS CLFIGURE 8. EL5150 GAIN vs FREQUENCY FOR VARIOUS CL
Typical Performance Curves (Continued)
100k 1G1M 10M 100M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +1
CL= 5pF
RL = 100Ω
RL = 500Ω
RL = 300Ω
RL = 200Ω
0.1 100110
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±5V
AV = +2
RF = RG = 402Ω
RL = 1kΩ
RL = 100Ω
RL = 150Ω
RL = 500Ω
100k 1M 10M 100M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +5
RF = 1.5kΩ
CL = 5pF
RL = 500Ω
RL = 100Ω
RL = 200Ω
RL = 400Ω
100k 1M 10M 100M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +1
RL = 500Ω
300M
CL = 15pF
CL = 0pF
CL = 3.9pF
CL = 8.2pF
100k 100M1M 10M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +2
RL = 500Ω
RF = RG = 400Ω
CL = 68pF
CL = 0pF
CL = 47pF
CL = 22pF
100k 30M1M 10M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +5
RF = 1.5kΩ
RL = 500ΩCL = 82pF
CL = 0pF
CL = 15pF
CL = 47pF
CL = 68pF
EL5150, EL5151, EL5250, EL5251, EL5451
6FN7384.7
January 16, 2008
FIGURE 9. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN- FIGURE 10. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN
FIGURE 11. EL5150 GAIN vs FREQUENCY FOR VARIOUS CIN- FIGURE 12. EL5250 GAIN vs FREQUENCY FOR VARIOUS RL
FIGURE 13. EL5150 GAIN vs FREQUENCY FOR V ARIOUS
RF/RG
FIGURE 14. EL5250 GAIN vs FREQUENCY FOR V ARIOUS
GAINS
Typical Performance Curves (Continued)
100k 400M1M 10M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +1
RL = 500Ω
CL = 5pF
100M
CIN- = 12pF
CIN- = 8.2pF
CIN- = 4.7pF
CIN- = 3.3pF
CIN- = 1pF
CIN- = 0pF
CIN- = 18pF
100k 100M1M 10M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +2
RL = 500Ω
CL = 5pF
RF = RG = 400Ω
CIN = 12pF
CIN = 0pF
CIN = 8.2pF
CIN = 3.9pF
100k 40M1M 10M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +5
RF = 1.5kΩ
RL = 500Ω
CL = 5pF CIN- = 68pF
CIN- = 33pF
CIN- = 0pF
CIN- = 8.2pF
CIN- = 3.3pF
CIN- = 8pF
CIN- = 100pF
100k 30M1M 10M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
RL = 50Ω
RL = 500Ω
AV = +5
RF = 1.5kΩ
RL = 500Ω
CL = 5pF
RL = 300Ω
RL = 200Ω
RL = 100Ω
100k 100M1M 10M
5
3
1
-1
-3
-5
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
AV = +2
RL = 500Ω
CL = 5pF
RF = RG = 1kΩ
RF = RG = 500Ω
RF = RG = 100Ω
RF = RG = 3kΩ
RF = RG = 2kΩ
100k 300M1M 10M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
100M
RL = 500Ω
CL = 5pF
AV = +2
AV = +1
AV = +3
EL5150, EL5151, EL5250, EL5251, EL5451
7FN7384.7
January 16, 2008
FIGURE 15. EL5250 GAIN vs FREQUENCY FOR V ARIOUS
GAINS FIGURE 16. PSRR vs FREQUENCY
FIGURE 17. PSRR vs FREQUENCY FIGURE 18. EL5250 CROSSTA LK vs FREQUENCY
FIGURE 19. EL5250 CROSSTALK vs FREQUENCY FIGURE 20. OUTPUT IMPEDANCE
Typical Performance Curves (Continued)
100k 1M 10M
4
2
0
-2
-4
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
100M
RL = 500Ω
CL = 5pF BOTH CHANNELS SHOWN
AV = +2
AV = +3
AV = +1
1k 100M10k 100k
0
20
40
60
80
100
PSRR (dB)
FREQUENCY RESPONSE (Hz)
1M 10M
AV = +1
POSITIVE SUPPLY
1k 100M10k 100k
0
20
40
60
80
100
PSRR (dB)
FREQUEN CY R E SP O N SE (Hz)
1M 10M
AV = +1
NEGATIVE SUPPLY
100k 100M1M 10M
-40
-50
-60
-70
-80
-90
CROSSTALK (dB)
FREQUENCY (Hz)
AV = +2
RL = 500Ω
CL = 5pF
IN CHANNEL A
OUT CHANNEL B
100k 100M1M 10M
40
50
60
70
80
90
CROSSTALK (dB)
FREQUENCY (Hz)
AV = +2
RL = 500Ω
CL = 5pF
IN CHANNEL B
OUT CHANNEL A
1k 100M10k 1M
1.000k
100.000
10.000
1.000
0.001
IMPEDANCE (Ω)
FREQUENCY (Hz)
0.100
100k 10M
AV = +2
EL5150, EL5151, EL5250, EL5251, EL5451
8FN7384.7
January 16, 2008
FIGURE 21. CMRR FIGURE 22. GROUP DELAY
FIGURE 23. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 24. VOLTAGE + CURRENT NOISE vs FREQUENCY
FIGURE 25. DISTORTION vs OUTPUT AMPLITUDE FIGURE 26. SLEW RATE vs POWER SUPPLY
Typical Performance Curves (Continued)
100 100M1k 1M
0
20
40
60
100
CMRR (dB)
FREQUENCY (Hz)
80
100k 10M
AV = +2
10k 1M 600M100M
2500
1500
500
-500
-2500
NORMALIZED GROUP DELAY
(500ps/DIV)
FREQUENCY (Hz)
-1500
AV = +1
RL = 500Ω
CL = 5pF
10M
AV = +1
RL = 500Ω
CL = 5pF
1.0 5.01.5 4.0
3.0
2.5
2.0
1.0
0
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
0.5
3.0 4.52.0 3.52.5
1.5
100 100k10k
100.0
10.0
1.0
0.1
VOLTAGE NOISE (nV/√Hz)
CURRENT NOISE (pA/√Hz)
FREQUENCY (Hz)
1k
AV = +1
RL = 500Ω
CL = 2.2pF
FREQ = 1.9MHz
0916
90
70
30
0
DISTORTION (dBc)
OUTPUT SWING (VP-P)
10
47253
50
8
80
60
20
40
2ND HD
3RD HD
2.2 6.22.7 4.7
105
85
70
SLEW RATE (V/µs)
SPLIT POWER SUPPLY (V)
75
3.7 5.24.23.2
95
5.7
100
80
90
EL5150, EL5151, EL5250, EL5251, EL5451
9FN7384.7
January 16, 2008
FIGURE 27. TOTAL HARMONIC DISTORTION vs OUTPUT
VOLTAGE FIGURE 28. HARMONIC DISTORTION vs FREQUENCY
FIGURE 29. SMALL SIGNAL STEP RESPONSE FIGURE 30. LARGE SIGNAL STEP RESPONSE
FIGURE 31. SMALL SIGNAL STEP RESPONSE FIGURE 32. LARGE SIGNAL STEP RESPONSE
Typical Performance Curves (Continued)
AV = +5
VS = ±5V
RL = 500Ω
RF = 402Ω
0817
-30
-40
-70
THD (dBc)
OUTPUT VOLTAGE (VP-P)
-60
4253
-50
THD_Fin = 2MHz
THD_Fin = 500kHz
AV = +5
VS = ±5V
RL = 500Ω
RF = 402Ω
VOUT = 2VP-P
0.5 10.01.0
-20
-30
-70
HARMONIC DISTORTION (dBc)
FUNDAMENTAL FREQUENCY (MHz)
-60
-40
-50
2ND HD
THD
3RD HD
VOLTAGE (50mV/DIV)
TIME (40ns/DIV)
AV = +1
RL = 500Ω
CL = 2.2pF
20%-80%
CH3 RISE
1.874ns
80%-20%
CH3 FALL
3.106ns
VOLTAGE (500mV/DIV)
TIME (40ns/DIV)
AV = +1
RL = 500Ω
CL = 2.2pF
20%-80%
CH3 RISE
11.72ns
80%-20%
CH3 FALL
15.28ns
VOLTAGE (50mV/DIV)
TIME (40ns/DIV)
AV = +2
RL =150Ω
CL = 2.2pF
20%-80%
CH3 RISE
4.337ns
80%-20%
CH3 FALL
6.229ns
VOLTAGE (500mV/DIV)
TIME (40ns/DIV)
AV = +2
RL = 150Ω
CL = 2.2pF
20%-80%
CH3 RISE
12.87ns
80%-20%
CH3 FALL
15.67ns
EL5150, EL5151, EL5250, EL5251, EL5451
10 FN7384.7
January 16, 2008
FIGURE 33. EL5150 ENABLE/DISABLE FIGURE 34. EL5250 ENABLE/DISABLE
FIGURE 35. DIFFERENTIAL GAIN FIGURE 36. DIFFERENTIAL PHASE
FIGURE 37. SMALL SIGNAL FREQUENCY vs SUPPLY FIGURE 38. INPUT-TO-OUTPUT ISOL ATION WITH PART
DISABLED
Typical Performance Curves (Continued)
TIME (400ns/DIV)
CH 1
CH 4
210ns
ENABLE 620ns
DISABLE
AV = +1
RL = 500ΩRL = 500Ω
SUPPLY = ±5.0V, ±2.7mA
800ns
ENABLE 520ns
DISABLE
TIME (1µs/DIV)
CH 2
0 10010 80
-0.04
DIFFERENTIAL
GAIN (%)
-0.02
4020 5030
0
60 70
0.02
0.04
0.06
90
IRE
010010 80
-1.0
DIFFERENTIAL
PHASE (°)
IRE
-0.5
4020 5030
0
60 70
0.5
1.0
1.5
90
AV = +1
RL = 500Ω
CL = 5pF
100k 300M10M
4
2
-2
-6
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-4
100M1M
0±2.0V
±6.0V
AV = +1
RL = 500Ω
CL = 2.7pF
100k 300M10M
-50
-70
-110
-150
ISOSLATION (dB)
FREQUENCY (Hz)
-130
100M1M
-90
EL5150, EL5151, EL5250, EL5251, EL5451
11 FN7384.7
January 16, 2008
Product Description
The EL5150, EL5151, EL5250, EL5251 and EL5451 are
wide bandwidth, low power, low offset voltage feedback
operational amplifiers capable of operating from a single or
dual power supplies. This family of operational amplifiers are
internally compensated for closed loop gain of +1 or greater .
Connected in voltage follower mode, driving a 500Ω load
members of this amplifier family demonstrate a -3dB
bandwidth of about 200MHz. With the loading set to
accommodate typical video application, 150Ω load and gain
set to +2, bandwidth reduces to about 40MHz with a 67V/µs
slew rate. Power down pins on the EL5151 and EL5251
reduce the already low power demands of this amplifier
family to 12µA typical while the amplifier is disabled.
Input, Output and Supply Voltage Range
The EL5150 and family members have been designed to
operate with supply voltage ranging from 5V to 12V. Supply
voltages range from ±2.5V to ±5V for split supply operati on.
And of course split supply operation can easily be achieved
using single supplies with by splitting off half of the single
supply with a simple voltage divider as illustrated in the
application circuit section.
Input Common Mode Range
These amplifiers have an input common mode voltage
ranging from 3.5V above the negative supply (VS- pin) to
3.5V below the positive supply (VS+ pin). If the input signal is
driven beyond this range the output signal will exhibit
distortion.
Maximum Output Swing & Load Resistance
The outputs of the EL5150 and family members exhibit
maximum output swing ranges from -4V to 4V for VS = ±5V
with a load resistance of 500Ω. Naturally, as the load
resistance becomes lower, the output swing lowers
accordingly; for instance, if the load resistor is 150Ω, the
output swing ranges from -3.5V to 3.5V. This response is a
simple application of Ohms law indicating a lower value
resistance results in greater current demands of the
amplifier. Addi tionally, the load resistance affects the
frequency response of this family as well as all operational
amplifiers; as clearly indicated by the Gain vs Frequency For
Various RL curves clearly indicate. In the case of the
frequency response reduced bandwidth with decreasing
load resistance is a function of load resistance in conjunction
with the output zero response of the amplifier.
Choosing A Feedback Resistor
A feedback resistor is require d to achieve unity gain; simply
short the output pin to the inverting input pin. Gains greater
than +1 require a feedback and gain resistor to set the
desired gain. This gets interesting because the feedback
resistor forms a pole with the parasitic capacitance at the
inverting input; as the feedback resistance increases the
position of the pole shifts in the frequency domain, the
amplifier's phase margin is reduced and the amplifier
becomes less stable. Peaking in the frequency domain and
ringing in the time domain are symptomatic of this shift in
pole location. So we want to keep the feedback resistor as
small as possible. You may want to use a large feedback
resistor for some reason; in this case to compensate the shift
of the pole and maintain stability a small capacitor in the few
Pico farad range in parallel with the feedback resistor is
recommended.
For the gains greater than unity it has been determined a
feedback resistance ranging from 500Ω to 750Ω provides
optimal response.
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.136W
909mW
870mW
435mW
0 15050
1.4
1.2
0.4
0
POWER DISSPIATION (W)
AMBIENT TEMPERATURE (°C)
0.2
12525
0.8
10075 85
1.0
0.6
θJA = 88°C/W
SO14
θJA = 230°C/W
SOT23-5/6
θJA = 110°C/W
SO8
θJA = 115°C/W
MSOP8/10
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0 15050
1
0.9
0.2
0
POWER DISSPIATION (W)
AMBIENT TEMPERATURE (°C)
0.1
12525
0.5
10075 85
0.7
0.3
0.8
0.4
0.6
833mW
625mW
486mW
391mW
θJA = 265°C/W
SOT23-5/6
θJA = 206°C/W
MSOP8/10
θJA = 120°C/W
SO14
θJA = 160°C/W
SO8
EL5150, EL5151, EL5250, EL5251, EL5451
12 FN7384.7
January 16, 2008
Gain Bandwidth Product
The EL5150 and family members have a gain ban dwidth
product of 40MHz for a gain of +5. Bandwidth can be
predicted by the following equation:
(Gain) x (BW) = GainBandwidthProduct
Video Performance
For good video performance, an amplifi er is required to
maintain the same output impedance and same frequency
response as DC levels are changed at the output; this
characteristic is widely referred to as “diffgain-diffphase”.
Many amplifiers have a difficult time with this especially while
driving standard video loads of 150Ω, as the output current
has a natural tendency to change with DC level. The dG and
dP for these families is a respectable 0.04% and 0.9°, while
driving 150Ω at a gain of 2. Driving high impedance loads
would give a similar or better dG and dP performance as the
current output demands placed on the amplifier lessen with
increased load.
Driving Capacitive Loads
These devices can easily drive capacitive loads as
demanding as 27pF in parallel with 500Ω while holding
peaking to within 5dB of peaking at unity gain. Of course if
less peaking is desired, a small series resistor (usually
between 5Ω to 50Ω) can be placed in series with the output
to eliminate most peaking; however, there will be a small
sacrifice of gain which can be recovered by simply adjusting
the value of the gain resistor.
Driving Cables
Both ends of all cables must always be properly terminated;
double termination is absolutely necessary for reflection-free
performance. Additionally, a back-termination series resistor
at the amplifier's output will isolate the amplifier from the
cable and allow extensive capacitive drive. However, other
applications may have high capacitive loads without a
back-termination resistor. Again, a small serie s resistor at
the output can help to reduce peaking.
Disable/Power-Down
Devices with disable can be disabled with their output placed
in a high impedance state. The turn off time is about 330ns
and the turn on time is about 130ns. When disabled, the
amplifier's supply current is reduced to 17µA typically;
essentially eliminating power consumption. The amplifier's
power down is controlled by standard TTL or CMOS signal
levels at the ENABLE pin. The applied logic signal is relative
to VS- pin. Letting the ENABLE pin float or the application of
a signal that is less than 0.8V above VS- enables the
amplifier. The amplifier is disabled when the signal at
ENABLE pin is above VS+ - 1.5V.
Output Drive Capability
Members of the EL5150 family do not have internal short
circuit protection circuitry. Typically, short circuit currents
ranging from 70mA and 95mA can be expected and
naturally, if the output is shorted indefinitely the part can
easily be damaged from overheating; or excessive curren t
density may eventually compromise metal integrity.
Maximum reliability is maintained if the output current is
always held below ±40mA. This limit is set and limited by the
design of the internal metal interconnect. Note that in
transient applications, the pa rt is extremely robust.
Power Dissipation
With the high output drive capabil ity of these devices, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating ar ea.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
For sourcing:
For sinking:
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
N = number of amplifiers (Max = 2)
By setting the two PDMAX equations equal to each other , we
can solve the output current and RLOAD to avoid the device
overheat.
PDMAX TJMAX TAMAX
–
ΘJA
---------------------------------------------
=(EQ. 1)
PDMAX VSISMAX VSVOUTi
–()
i1=
n
∑VOUTi
RLi
-----------------
×+×=(EQ. 2)
PDMAX VSISMAX VOUTi VS
–()
i1=
n
∑ILOADi
×+×=(EQ. 3)
EL5150, EL5151, EL5250, EL5251, EL5451
13 FN7384.7
January 16, 2008
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very im portant. The
feedback resistor should be placed very close to the
inverting input pin. S trip line design techniques are
recommended for the signal traces.
Application Circuits
Sallen Key Low Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the EL5150. A derivation of the transfer function is provided
for convenience (see Figure 41).
Sallen Key High Pass Filter
Again, this useful filter benefits from the characteristics of the
EL5150. The transfer function is very similar to the low pass
so only the results are presented (see Figure 42).
FIGURE 41. SALLEN KEY LOW PASS FILTER
K3 1
Q
RC
1
wo
KHolp
CR CR
CR CR
CR CR
)K1(
1
Q
CRCR 1
wo
KHolp )CRCRCR)K1((jwCRCRw1 1
)jw(H
1s)CRCRCR)K1((sCRCR K
)s(H
0
sC1ViVo
RVKVo
1
RViV
V
1sCR 1
KVo
R
R
1K
11 22
12 21
22 11
2211
2221112211
2
2212111
2
2211
1
21
1
1
1
22
A
B
−
=
=
=
++−
=
=
=
++−+−
=
+++−+
=
=
−
+
−
+
−
+
=
+=
Equations simplify if we let all
components be equal R = C
+
-
0.1µF
5V
V2
C1
R1 R2
V1
1k
C2
RA 1k
1k
RB
0.1µF
5V
V3
R7 1k
VOUT
1
3
2
V+
V-
4
U1A
1n
1n
1k
11
EL5150, EL5151, EL5250, EL5251, EL5451
14 FN7384.7
January 16, 2008
Differe ntial Output Instrumentation Amp lifier
The addition of a third amplifier to the conventional three
amplifier Instrumentation Amplifier introduces the benefits of
differential signal realization; specifically the advantage of
using common mode rejection to remove coupled noise and
ground –potential errors inherent in remote transmission.
This configuration also provides enhanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
FIGURE 42. SALLEN KEY HIGH PASS FILTER
K4 2
Q
RC
2
wo
K4K
Holp
CR CR
CR CR
CR CR
)K1(
1
Q
CRCR 1
wo
KHolp
11 22
12 21
22 11
2211
−
=
=
−
=
++−
=
=
=
Equations simplify if we let
all components be equal R = C
+
-
0.1µF
5V
V2
R8
C7 C9
V1
1n
C2
RA 1k
1k
RB
0.1µF
5V
V3
R7 1k
VOUT
1
3
2
V+
V-
4
U1A
1k
1n
1n
11
+
-
-
+
-
+
+
-
eo
eo4
eo3
REF
R3
R3
R3
R3
R3
R3
R2
R2
RG
A2
e2
A4
A3
R3
R3
A1
e1
+
-
eo3 12R
2RG
⁄+()e1e2
–()–= eo4 12R
2RG
⁄+()e1e2
–()=
eo21 2R
2RG
⁄+()e1e2
–()–=
BW 2fC1 2,
ADi
------------------
=ADi 21 2R
2RG
⁄+()–=
EL5150, EL5151, EL5250, EL5251, EL5451
15 FN7384.7
January 16, 2008
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwi dth and hi gh accuracy of the EL5150.
The operation of the circuit is very straight-forward. As the
strain variable component resistor in the balanced bridge is
subjected to increasing strain, its resistance changes
resulting in an imbalance in the bridge. A voltage variation
from the referenced high accuracy source is generated and
translated to the difference amplifier through the buffer
stage. This voltage difference as a function of the strain is
converted into an output voltage.
+
-
0.1µF
5V
V2
22 R17
1k
1k
RF
0.1µF
5V
V4
RL 1k
VOUT (V1+V2+V3+V4)
1
3
2
V+
V-
4
U1A
22
11
R18
1k
1k
R15
V5 1k
0V
VARIABLE SUBJECT TO STRAIN
R15 1k
R14
4
4
EL5150, EL5151, EL5250, EL5251, EL5451
16 FN7384.7
January 16, 2008
EL5150, EL5151, EL5250, EL5251, EL5451
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X 4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
17 FN7384.7
January 16, 2008
EL5150, EL5151, EL5250, EL5251, EL5451
SOT-23 Package Family
e1
N
A
D
E
4
321
E1
0.15 DC
2X 0.20 C
2X
e
B0.20 MDC A-B
b
NX
6
2 3
5
SEATING
PLANE
0.10 C
NX
1 3
C
D
0.15 A-BC
2X
A2
A1
H
c
(L1)
L
0.25
0° +3°
-0°
GAUGE
PLANE
A
MDP0038
SOT-23 PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCESOT23-5 SOT23-6
A 1.45 1.45 MAX
A1 0.10 0.10 ±0.05
A2 1.14 1.14 ±0.15
b 0.40 0.40 ±0.05
c 0.14 0.14 ±0.06
D 2.90 2.90 Basic
E 2.80 2.80 Basic
E1 1.60 1.60 Basic
e 0.95 0.95 Basic
e1 1.90 1.90 Basic
L 0.45 0.45 ±0.10
L1 0.60 0.60 Reference
N 5 6 Reference
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
6. SOT23-5 version has no center lead (shown as a dashed line).
18
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7384.7
January 16, 2008
EL5150, EL5151, EL5250, EL5251, EL5451
Mini SO Package Family (MSOP)
1(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1 L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A1.101.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c0.180.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E4.904.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e0.650.50 Basic -
L0.550.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
