1 of 10
FEATURES
10 years minimu m data r et ent io n in the
absence o f exter na l po w er
Dat a is automatically pro tect ed d uring power
loss
Rep laces 32k x 8 volat ile static RAM,
EEPROM or Flash memory
Unlim ited write c ycles
Low-po wer CMOS
Read and wr it e access times of 100ns
Lit h iu m energy so u r ce is elect ricall y
d iscon nect ed to retain fres hness unt il power is
applied for the first time
Optional indust r ial t e mperat ure r ange of
-40°C to +85°C, des ig nat ed I N D
JEDEC standard 28-pin DIP package
Power Cap Modu le (PCM) packag e
- D ir ect ly sur face-mountable mo dule
- Rep laceab le snap-on Po werCap provides
lit hiu m backup bat ter y
- Standardized pino ut for all non volatile
SRAM products
- Det ach ment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A14 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+3.3V)
GND - Ground
NC - No Connect
DS1230W
3.3V 256k Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
27
740-Mil Extended
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
28
26
25
24
23
22
21
20
19
18
17
15
16
A12
A6
A4
A14
1
NC
2
3
NC
NC
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
GND
VBAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
19-5636; Rev 11/ 10
DS1230W
2 of 10
DESCRIPTION
The DS1230W 3.3V 256k Nonvo latile SRAM is a 262,144-bit, full y st atic, no nvo latile SRAM o rg anized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry, whi ch constan tly monitors VCC fo r an out-of-to lerance cond it ion. When suc h a co nditio n occu r s,
t he lithiu m energ y so urce is auto mat ically sw itc hed o n and wr ite p ro t ect io n is uncondit ionally enabled to
preve nt dat a corrupt ion. DIP-package DS1230W devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP st andard. T he DIP d evice s a lso mat ch t he
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W
devices in the PowerCap Mo dule package are d ir ect ly sur face mou ntable and are normally paired w it h a
DS903 4P C PowerCap to form a comp let e Nonvolat ile SRAM Module. There is no limit o n t he number of
write cycles that can be executed and no additional support circuitry is required for microprocessor
interfacing.
READ MODE
The DS1230W executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Ena ble ) and
OE
(Output Enable) are active (low). The unique address specified by the 15 address inputs
(A0 – A14) defines w hich of the 32,76 8 byt es o f da ta is t o be accessed. Va lid dat a will be availa ble to the
e ig h t dat a o utput driver s w it h in tACC (Acces s T ime) after the last address input signal is stable, pro viding
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
sat isfied, t he n dat a access must be measured fro m t he later -occurring s ig na l (
CE
or
OE
) and t he lim itin g
parameter is either tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1230W executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stab le. The lat er -o ccurring falling edge of
CE
or
WE
w ill det ermine the st art of the writ e cycle .
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
c ycle s t o a void bus co ntent io n. H oweve r, if the out put drivers are enabled (
CE
and
OE
ac tive) t he n
WE
will dis ab le the outp uts i n tODW from it s falling edge.
DATA RETENTION MODE
The DS1230W provides full fu nctional capabilit y fo r VCC great er t han 3.0 vo lt s and wr ite pr ot ect s by 2.8
vo lt s. Dat a is ma inta ined in t he abse nce o f VCC w ithout any add itio nal suppor t circuit ry. The nonvo latile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write p rotect t hemse lves, a l l input s become “do n’t car e,” and a ll output s become h ig h-impedan ce. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM op er ation can resu me a fter VCC exceeds 3.0 volts.
FRESH NESS SEAL
Each DS1230 W device is shipped fro m Maxim w it h its lit h iu m energ y so ur ce disco nn ected , gu ar ant eeing
fu ll e ne r g y c ap acity. Whe n VCC is first app lied at a leve l great er than 3. 0 vo lt s, the lit hium e nerg y s ou rce
is enabled for bat tery back-up o peration.
DS1230W
3 of 10
PACKAGES
The DS1230W is available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230W to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230W module base is reflow soldered, a DS9034PC PowerCap is snapped on top
o f the base t o for m a co mplete N onvo latile SRAM mo du le. T he DS9034 PC is k eyed t o prevent impr oper
attachment. DS1230W module bases and DS9034PC PowerCaps are ordered separately and shipped in
separate cont ainers. S ee t he DS9034 P C data sheet for furt her informat ion.
DS1230W
4 of 10
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0 .3V to +4.6V
Operating Te mperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e Range
EDIP -40°C to +85°C
PowerCap -55° C to +125° C
Lead Temperature ( soldering, 10s) +260°C
Note: E DIP is wa ve or ha nd soldered only.
Soldering Temper ature (reflow, PowerCap) +260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Po wer Supply Voltage VCC 3.0 3.3 3.6 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.4 V
DC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.2V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Current
CE
=2.2V ICCS1 50 250 µA
St andby Current
CE
=VCC-0.2V ICCS2 30 150 µA
Operating Current ICCO1 50 mA
Write Protection Voltage VTP 2.8 2.9 3.0 V
DS1230W
5 of 10
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/O utput C a pacit a nce CI/O 5 10 pF
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL DS1230W-100 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 100 ns
Access Time tACC 100 ns
OE to Out put Valid tOE 50 ns
CE to O utput Va li d tCO 100 ns
OE or CE to Out put Active tCOE 5 ns 5
Out put High-Z from Deselection tOD 35 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 100 ns
Writ e P ulse Width tWP 75 ns 3
A ddress Setup Time tAW 0 ns
Writ e Recover y Ti me tWR1
tWR2
5
20 ns
ns 12
13
Out put High-Z fr om
WE
tODW 35 ns 5
Output Active from
WE
tOEW 5 ns 5
Da ta Setu p Time tDS 40 ns 4
Da ta Hold Time tDH1
tDH2
0
20 ns
ns 12
13
DS1230W
6 of 10
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
DS1230W
7 of 10
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER-DOWN/POWER-UP CONDITION
DS1230W
8 of 10
POWER-DOWN/POWER-UP TIMING (TA: S ee Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC slew from VTP to 0V tF 150 µs
VCC slew from 0V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to End of Write Prot ection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Ret ent io n T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH d uri ng w rite cycle, the outpu t buffers rema in in a hi gh-impeda nce state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDH, tDS are measur ed from the ear lier of
CE
or
WE
go ing h ig h.
5. T hese para met er s ar e samp led w ith a 5 pF load and are not 100% tes ted.
6. I f the
CE
low transitio n occurs simu lta neously wit h o r latter t han the
WE
low t ransit ion, the o utput
buff e rs rema in in a high-impedance stat e during this per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h-impedance state during t his period.
8. If
WE
is low or the
WE
lo w t ra ns ition o cc ur s pr ior t o o r s imult a ne o u s ly w it h t he
CE
lo w t ra ns ition ,
the out put bu f f e rs remain i n a high-impedance state during this period.
9. Each DS1230W has a built-in sw it ch t hat d isco nnect s t he lit hiu m so ur ce u nt il VCC is fir st app lied b y
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
t ime power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For indu strial product s (IND), this range is -40°C t o
+85°C.
11. In a power-dow n c onditio n the volt a ge on a ny p i n may not e xc ee d the volt age on VCC.
12. tWR1 and tDH1 are measur ed fro m
WE
go ing h ig h.
13. tWR2 and tDH2 are measur ed fro m
CE
go ing h ig h.
14. DS1230 modules are reco gnized by Underwrit ers Laborator ies (UL) under file E 99151.
DS1230W
9 of 10
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100pF + 1TTL Gate
Cycle = 200ns for operating current Input P ulse Levels: 0 to 2.7V
All voltages are refer enced to grou nd Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1230W-100+
0°C to +70°C
3.3V ± 0.3V
28 740 EDIP
100
DS1230WP-100+
0°C to +70°C
3.3V ± 0.3V
34 PowerCap*
100
DS1230W-100IND+
-40°C to +85°C
3.3V
±
0.3V
28 740 EDIP
100
DS1230WP-100IND+
-40°C to +85°C
3.3V ± 0.3V
34 PowerCap*
100
+Denotes a lead(Pb)-free/RoHS-compli ant package.
*DS9034PC+ or DS9034PCI+ (Pow erCap) required. Must be order e d s e parately.
PACKAGE INFORMATION
For the latest package outline information a nd land patterns, go to www.maxim-ic.com/packages. N ote that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr awing pertains to t he p ackage re gardless of RoHS sta tus.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
28 EDIP MDT28+3 21-0245 —
34 PCAP PC2+4 21-0246 —
DS1230W
10 of 10
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Ordering Information table; removed th e DIP module
package drawing and dimension t able
8
11/10
Updated the storage informat ion, sold ering temperature, and lead
t emperat ur e info rmatio n in the Absolute Maximum Ratings section;
r emo ved the -150 MIN/MAX informatio n from the AC Electrical
Characteristics table; updated the Ordering Inf ormation table
(removed -150 part s and leaded -100 parts); remo ved the Power Cap
module drawings and updated t he Package Information table
1, 4, 5, 9