74LVT14 3.3 V hex inverter Schmitt trigger Rev. 02 -- 25 April 2008 Product data sheet 1. General description The 74LVT14 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. It is capable of transforming slowly changing input signals into sharply defined, jitter free output signals. In addition, it has a greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive-going and negative-going inputs. The threshold differential (typically 600 mV) is determined internally by resistor ratios and is insensitive to temperature and supply voltage variations. 2. Features n n n n n n n Different positive and negative going input threshold voltages Tolerant of slow input transitions High noise immunity TTL input and output switching levels Output capability: +32 mA/-20 mA Latch-up protection exceeds 500 mA per JESD78 class II level A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT14D -40 C to +85 C SO14 plastic small outline package; 14 leads; body width 7.5 mm SOT108-1 74LVT14DB -40 C to +85 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVT14PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVT14BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 4.5 x 0.85 mm SOT762-1 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 4. Functional diagram 1 3 5 9 11 13 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A 6Y 1 2 3 4 5 6 9 8 11 10 13 12 2 4 6 8 10 12 Y 001aac497 mna204 Fig 1. A Logic symbol Fig 2. mna025 IEC logic symbol Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 1 1A terminal 1 index area 74LVT14 14 VCC 74LVT14 1Y 2 13 6A 1A 1 14 VCC 2A 3 12 6Y 1Y 2 13 6A 2Y 4 11 5A 2A 3 12 6Y 3A 5 2Y 4 11 5A 3A 5 10 5Y 3Y 6 3Y 6 9 4A GND 7 8 4Y GND(1) 10 5Y 7 8 GND 4Y 9 4A 001aah921 Transparent top view 001aah920 (1) The die substrate is attached to this pad using a conductive die attach material. It cannot be used as a supply pin or input. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 2 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 6A 1, 3, 5, 9, 11, 13 data input 1Y to 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) VCC 14 positive supply voltage 6. Functional description Table 3. Function selection Inputs Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values [1] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit -0.5 +4.6 V input voltage [2] -0.5 +7.0 V VO output voltage output in OFF or HIGH state [2] -0.5 +7.0 V IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO < 0 V -50 - mA IO output current output in LOW state - 64 mA output in HIGH state -32 - mA Tstg storage temperature -65 +150 C Tj junction temperature +150 C 500 mW VI total power dissipation Ptot Tamb = -40 C to +85 C [3] [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [3] For SO14 packages: above 70 C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K. 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 3 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V IOH HIGH-level output current -20 - - mA IOL LOW-level output current - - 32 mA Tamb ambient temperature in free air -40 - +85 C t/V input transition rise and fall rate output enabled 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter -40 C to +85 C Conditions Min Typ[1] Unit Max VT+ positive-going threshold voltage VCC = 3.3 V; see Figure 7 1.5 1.7 2.0 V VT- negative-going threshold voltage VCC = 3.3 V; see Figure 7 0.9 1.1 1.3 V VH hysteresis voltage VCC = 3.3 V; see Figure 7 0.4 0.6 - V VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA -1.2 - - V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 VOH HIGH-level output voltage LOW-level output voltage VOL input leakage current II VCC = 2.7 V to 3.6 V; IOH = -100 A VCC - 0.2 - - V VCC = 2.7 V; IOH = -6 mA 2.4 - - V VCC = 3.0 V; IOH = -20 mA 2.0 - - V VCC = 2.7 V; IOL = 100 A - - 0.2 V VCC = 2.7 V; IOL = 24 mA - - 0.5 V VCC = 3.0 V; IOL = 32 mA - - 0.5 V VCC = 0 V or 3.6 V; VI = 5.5 V - - 10 A VCC = 3.6 V; VI = VCC or GND - - 1 A - - 100 A - - 0.02 mA - 1.5 3 mA - - 0.2 mA - 3 - pF IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input = VCC - 0.6 V other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V [2] [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] This is the increase in the supply current for each input at the specified voltage level other than VCC or GND. 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 4 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter LOW to HIGH propagation delay tPLH -40 C to +85 C Conditions VCC = 3.3 V + 0.3 V HIGH to LOW propagation delay Max - - 6.9 ns 1.0 3.8 5.7 ns - - 4.1 ns 1.0 3.2 4.5 ns nA to nY VCC = 2.7 V VCC = 3.3 V + 0.3 V [1] Min nA to nY VCC = 2.7 V tPHL Unit Typ[1] Typical values are measured at Tamb = 25 C and VCC = 3.3 V. 11. Waveforms VI VM nA input VM GND t PHL t PLH VOH VM nY output VM VOL mna344 See Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. nA Input to nY output propagation delays VO VT+ VI VT- VI VH VT- VT+ a. Transfer characteristics Fig 7. VH VO mna208 mna207 b. Voltage levels Definition of VT+, VT- and VH 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 5 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger Table 8. Measurement points VCC 2.7 V to 3.6 V Input Output VM VM 1.5 V 1.5 V VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 9. Load circuitry for switching times Test data Supply Input pulse requirements Load VCC VI Repetition rate tW tr, tf RL CL 2.7 V to 3.3 V 2.7 V 10 MHz 2.5 ns 500 50 pF 500 ns 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 6 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 7 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 10. Package outline SOT337-1 (SSOP14) 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 8 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 9 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 10 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Integrated Bipolar junction transistors and CMOS DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT14_2 20080425 Product data sheet - 74LVT14_1 Modifications: 74LVT14_1 * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. * * * Legal texts have been adapted to the new company name where appropriate. * Section 13 "Abbreviations" added. Quick reference section removed. DHVQFN14 package added to Section 3 "Ordering information" and Section 12 "Package outline". 19960828 Product specification 74LVT14_2 Product data sheet - - (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 11 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT14_2 Product data sheet (c) NXP B.V. 2008. All rights reserved. Rev. 02 -- 25 April 2008 12 of 13 74LVT14 NXP Semiconductors 3.3 V hex inverter Schmitt trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 April 2008 Document identifier: 74LVT14_2