74LVT14BQ,115 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LVT14 is a high-performance BiCMOS product designed for VCC operation at 3.3 V.

It is capable of transforming slowly changing input signals into sharply deﬁned, jitter free

output signals. In addition, it has a greater noise margin than conventional inverters.

Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase

splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to

effectively speed-up slow input transitions, and provide different input threshold voltages

for positive-going and negative-going inputs. The threshold differential (typically 600 mV)

is determined internally by resistor ratios and is insensitive to temperature and supply

voltage variations.

2. Features

nDifferent positive and negative going input threshold voltages

nTolerant of slow input transitions

nHigh noise immunity

nTTL input and output switching levels

nOutput capability: +32 mA/−20 mA

nLatch-up protection exceeds 500 mA per JESD78 class II level A

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

3. Ordering information

74LVT14

3.3 V hex inverter Schmitt trigger

Rev. 02 — 25 April 2008 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVT14D −40 °Cto+85°C SO14 plastic small outline package; 14 leads;

body width 7.5 mm SOT108-1

74LVT14DB −40 °Cto+85°C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm SOT337-1

74LVT14PW −40 °Cto+85°C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74LVT14BQ −40 °Cto+85°C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 ×4.5 ×0.85 mm

SOT762-1

Product data sheet Rev. 02 — 25 April 2008 2 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

4. Functional diagram

5. Pinning information

5.1 Pinning

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

mna204

1A 1Y

2A 2Y

3A 3Y

4A 4Y

5A 5Y

11 10

6A 6Y

13 12

001aac497

mna025

(1) The die substrate is attached to this pad using a

conductive die attach material. It cannot be used as a

supply pin or input.

Fig 4. Pin conﬁguration for SO14 and (T)SSOP14 Fig 5. Pin conﬁguration for DHVQFN14

74LVT14

1A VCC

1Y 6A

2A 6Y

2Y 5A

3A 5Y

3Y 4A

GND 4Y

001aah920

001aah921

74LVT14

GND(1)

Transparent top view

3Y 4A

3A 5Y

2Y 5A

2A 6Y

1Y 6A

GND

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Product data sheet Rev. 02 — 25 April 2008 3 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

5.2 Pin description

6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level.

7. Limiting values

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

[2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.

For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.

Table 2. Pin description

Symbol Pin Description

1A to 6A 1, 3, 5, 9, 11, 13 data input

1Y to 6Y 2, 4, 6, 8, 10, 12 data output

GND 7 ground (0 V)

VCC 14 positive supply voltage

Table 3. Function selection

Inputs Output

nA nY

Table 4. Limiting values [1]

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

VIinput voltage [2] −0.5 +7.0 V

VOoutput voltage output in OFF or HIGH state [2] −0.5 +7.0 V

IIK input clamping current VI < 0 V −50 - mA

IOK output clamping current VO < 0 V −50 - mA

IOoutput current output in LOW state - 64 mA

output in HIGH state −32 - mA

Tstg storage temperature −65 +150 °C

Tjjunction temperature +150 °C

Ptot total power dissipation Tamb = −40 °C to +85 °C[3] 500 mW

Product data sheet Rev. 02 — 25 April 2008 4 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

8. Recommended operating conditions

9. Static characteristics

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.

[2] This is the increase in the supply current for each input at the speciﬁed voltage level other than VCC or GND.

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.7 - 3.6 V

VIinput voltage 0 - 5.5 V

IOH HIGH-level output current −20 - - mA

IOL LOW-level output current - - 32 mA

Tamb ambient temperature in free air −40 - +85 °C

∆t/∆V input transition rise and fall rate output enabled 0 - 10 ns/V

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

VT+ positive-going threshold voltage VCC = 3.3 V; see Figure 7 1.5 1.7 2.0 V

VT−negative-going threshold voltage VCC = 3.3 V; see Figure 7 0.9 1.1 1.3 V

VHhysteresis voltage VCC = 3.3 V; see Figure 7 0.4 0.6 - V

VIK input clamping voltage VCC = 2.7 V; IIK = –18 mA −1.2 - - V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8

VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH =−100 µAV

CC − 0.2 - - V

VCC = 2.7 V; IOH =−6 mA 2.4 - - V

VCC = 3.0 V; IOH =−20 mA 2.0 - - V

VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 µA - - 0.2 V

VCC = 2.7 V; IOL = 24 mA - - 0.5 V

VCC = 3.0 V; IOL = 32 mA - - 0.5 V

IIinput leakage current VCC = 0 V or 3.6 V; VI= 5.5 V - - 10 µA

VCC = 3.6 V; VI=V

CC or GND - - ±1µA

IOFF power-off leakage current VCC = 0 V; VIor VO= 0 V to 4.5 V - - ±100 µA

ICC supply current VCC = 3.6 V; VI= GND or VCC; IO=0A

outputs HIGH - - 0.02 mA

outputs LOW - 1.5 3 mA

∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V;

one input = VCC −0.6 V

other inputs at VCC or GND

[2] - - 0.2 mA

CIinput capacitance VI= 0 V or 3.0 V - 3 - pF

Product data sheet Rev. 02 — 25 April 2008 5 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

10. Dynamic characteristics

[1] Typical values are measured at Tamb =25°C and VCC = 3.3 V.

11. Waveforms

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.

Symbol Parameter Conditions −40 °C to +85 °C Unit

Min Typ[1] Max

tPLH LOW to HIGH propagation delay nA to nY

VCC = 2.7 V - - 6.9 ns

VCC = 3.3 V + 0.3 V 1.0 3.8 5.7 ns

tPHL HIGH to LOW propagation delay nA to nY

VCC = 2.7 V - - 4.1 ns

VCC = 3.3 V + 0.3 V 1.0 3.2 4.5 ns

See Table 8 for measurement points.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 6. nA Input to nY output propagation delays

mna344

tPHL tPLH

nA input

nY output

GND

VOH

VOL

a. Transfer characteristics b. Voltage levels

Fig 7. Deﬁnition of VT+, VT− and VH

mna207

VHVT+

VT−

mna208

VIVH

VT+

VT−

Product data sheet Rev. 02 — 25 April 2008 6 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

Table 8. Measurement points

VCC Input Output

VMVM

2.7 V to 3.6 V 1.5 V 1.5 V

Test data is given in given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 8. Load circuitry for switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aaf615

VCC

VIVO

DUT

RTRL

PULSE

GENERATOR

Table 9. Test data

Supply Input pulse requirements Load

VCC VIRepetition rate tWtr, tfRLCL

2.7 V to 3.3 V 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω50 pF

Product data sheet Rev. 02 — 25 April 2008 7 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

12. Package outline

Fig 9. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 02 — 25 April 2008 8 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

Fig 10. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 02 — 25 April 2008 9 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

Fig 11. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 02 — 25 April 2008 10 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

Fig 12. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 02 — 25 April 2008 11 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

BiCMOS Integrated Bipolar junction transistors and CMOS

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVT14_2 20080425 Product data sheet - 74LVT14_1

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Quick reference section removed.

•DHVQFN14 package added to Section 3 “Ordering information” and Section 12 “Package

outline”.

•Section 13 “Abbreviations” added.

74LVT14_1 19960828 Product speciﬁcation - -

Product data sheet Rev. 02 — 25 April 2008 12 of 13

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LVT14

3.3 V hex inverter Schmitt trigger

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 April 2008

Document identifier: 74LVT14_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 3

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

8 Recommended operating conditions. . . . . . . . 4

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16 Contact information. . . . . . . . . . . . . . . . . . . . . 12

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13