PIC12C5XX Programming Specification - Microchip Technology

 2001 Microchip Technology Inc. DS30557F-page 1

PIC12C5XX

This document includes the progr amming

specifications for the following devices:

1.0 PROGRAMMING THE

PIC12C5XX

The PIC12C5XX can be programmed using a serial

method. Due to this serial programming, the

PIC12C5XX can be programmed while in the user’s

system , i nc reas in g d esi gn flexi bil ity. Thi s pr ogra mm in g

specification applies to PIC12C5XX devices in all

packages.

1.1 Hardware Requirements

The PIC12C5XX requires two programmable power

supplies, one for VDD (2.0V to 6.5V recommended) and

one for VPP (12V to 14V). Both s upplies should have a

minimum resolution of 0.25V.

1.2 Programming Mode

The Programming mode for the PIC12C5XX allows

programming of user program memory, special loca-

tions used for ID, and the configuration word for the

PIC12C5XX.

Pin Diagram

• PIC12C508 • PIC12C508A • PIC12CE518

• PIC12C509 • PIC12C509A • PIC12CE519

PDIP, SOIC, JW

VDD

GP5/OSC1/CLKIN

GP4/OSC2/CLKOUT

GP3/MCLR/VPP

VSS

GP0

GP1

GP2/T0CKI

PIC12C5XX

PIC12C5XXA

PIC12CE5XXA

In-Cir cuit Serial Programm ing

™

for PIC12C5XX OTP MCUs

PIC12C5XX

DS30557F-page 2  2001 Microchip Technology Inc.

2.0 PROGRAM MODE ENTRY

The Program/Verify Test mode is entered by holding

pins D B0 and DB1 low , whil e raisin g MCLR pin from VIL

to VIHH. Once in this Test mode, the user program

memory and the test program memory can be

accessed and programmed in a serial fashion. The first

selec ted memor y locatio n is the f uses. GP0 and GP1

are Schmitt Trigger inputs in this mode.

Incrementing the PC once (using the increment

address command), selects location 0x000 of the reg-

ular program memory. Afterwards, all other memory

locations from 0x001-01FF (PIC12C508/CE518),

0x001-03FF (PIC12C509/CE519) can be addressed

by in crementing the PC.

If the program counter has reached the last user pro-

gram location and is incremented again, the on-chip

specia l EPROM area wi ll be addres sed. (See Figure 2-

2 to determine where the special EPROM area is

located for the various PIC12C5XX devices.)

2.1 Programming Method

The programming technique is described in the follow-

ing section. It is designed to guarantee good program-

ming margins. It does, however, require a variable

power supply for VCC.

2.1.1 PROGRAMMING METHOD DETAILS

Essenti ally, this techni que inc ludes the followi ng st eps :

1. Perform blank check at VDD = VDDMIN. Report

failure. The device may not be properly erased.

2. Program location with pulses and verify after

each pulse at VDD = VDDP:

where VDDP = VDD range required during

programming ( 4.5V - 5.5V) .

a) Programming condition:

VPP = 13.0V to 13.25V

VDD = VDDP = 4.5V to 5.5V

VPP must be ≥ VDD + 7.25V to keep

“Programming mode” active.

b) Verify condition:

VDD = VDDP

VPP ≥ VDD + 7.5V but not to exceed 13.25V

If locati on fa il s to p rogram after “N” pulses (sug-

gested maximum program pulses of 8), then

report error as a programming failure.

3. Once location passes “Step 2", apply 11X over

progra mming, i.e ., apply 11 times the number of

pulses that were required to program the loca-

tion. This will insure a solid programming mar-

gin. The over programming should be made

“software programmable” for easy updates .

4. Progr am all locations.

5. Verify all l oc ati ons (us in g Speed Verify mo de) at

VDD = VDDMIN.

6. Verify all locations at VDD = VDDMAX.

VDDMIN is the minimum operating voltage spec.

for the part. VDDMAX is the maximum operating

voltage spec. for the part.

2.1.2 SYSTEM REQUIREMENTS

Clearly , to implement this technique, the most stringent

requirements will be that of the power supplies:

VPP: VPP can be a fixed 13.0V to 13.25V supply. It must

not exceed 14.0V to avoid damage to the pin and

should be current limited to approxima tely 100m A.

VDD: 2.0V to 6.5V with 0.25V granularity. Since this

method calls for verification at different VDD values, a

programmable VDD power supply is needed.

Current Requirement: 40mA maximum

Microc hip ma y release devices in the fu ture with differ-

ent VDD ranges, which make it necessary to have a

programmable VDD.

It is important to verify an EPROM at the voltages

specified in this method to remain consistent with

Microc hip's test sc reening. For example, a PIC12C5XX

specified for 4.5V to 5.5V should be tested for proper

programm in g from 4.5V to 5.5V.

2.1.3 SOFTWARE REQUIREMENTS

Certain parameters should be programmable (and

therefore, easily modified) for easy upgrade.

a) Pulse width.

b) Maximum number of pulses, present limit 8.

c) Numbe r of ov er-prog rammi ng pulse s: sh ould b e

= (A • N) + B, where N = number of pulses

required in regular programming. In our current

algorithm A = 11, B = 0.

2.2 Programming Pulse Width

Program Memory Cells: When programming one

word of EPROM, a programming pulse width (TPW) of

100µs is reco mmended.

The maximum number of programming attempts

should be lim ite d to 8 per word.

After the first successful verify, the same location should

be over-programmed with 11X over-programming.

Configuration W ord: The configuration word for oscil-

lator selection, WDT (Watchdog Timer) disable and

code protection, and MCLR enable, requires a pro-

gramming pulse width (TPWF) of 10ms. A series of

100µs pulses is preferred over a single 10ms pulse.

Note: Device must be verified at minimum and

maximum specified operating voltages as

specified in the data sheet.

Note: Any programmer not meeting the program-

mable VDD requirement and the verify at

VDDMAX and VDDMIN requirement, may

only be classified as a “prototype” or

“development” programmer, but not a

produ cti on prog ram me r.

 2001 Microchip Technology Inc. DS30557F-page 3

PIC12C5XX

FIGURE 2-1: PROGRAMMING METHOD FLOW CHART

N > 8?

Start

Blank Check

@ VDD = VDDMIN

Pass?

Report Possible Erase Failure

Continue Programming

at user ’s option

Program 1 Location

@ VPP = 13.0V to 13.25V

VDD = VDDP

N = N + 1

(N = # of program pulses)

Report Programming Failure

Incr e ment PC to p o i n t to

next location, N = 0 Apply 11N additional

program pulses

Pass?

All

locations

done?

Verify all locations

@ VDD = VDDMIN

Pass? Report verify failure

@ VDDMIN

VDD = VDD max.

Verif y all locations

@ VDD = VDDMAX

Pass? Report verify failure

@ VDDMAX

Done

Yes

Now program

Configuration Word Verif y Configuration Word

@ VDDMAX & VDDMIN

PIC12C5XX

DS30557F-page 4  2001 Microchip Technology Inc.

FIGURE 2-2: PIC12C5XX SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE

Address

(HEX) 000 Bit Number

11 0

NNN

TTT

TTT + 1

TTT + 2

TTT + 3

TTT + 3F

(FFF)

For Customer Use

(4 x 4 bit usable)

For Factory Use

Configuration Word 5 bits

0 0 ID0

0 0 ID1

0 0 ID2

0 0 ID3

User Program Me mory

(NNN + 1) x 12 bit

NNN Highest normal EPROM memory address. NNN = 0x1FF for PIC12C508/CE518.

NNN = 0x3FF for PIC12C509/CE519.

TTT Start address of special EPROM area and ID locations.

Note that some versions will have an oscillator calibration value programmed at NNN.

 2001 Microchip Technology Inc. DS30557F-page 5

PIC12C5XX

2.3 S pecial Memory Locations

The highest address of program memory space is

reserve d for the intern al RC osci llator cal ibration v alue.

This location should not be overwritten except when

this location is blank, and it should be verified, when

programmed, that it is a MOVLW XX instruction.

The ID L ocations are a is only enabled i f the devic e is in

Programming/Verify mode. Thus, in normal operation

mode, only the memory location 0x000 to 0xNNN will

be acce ssed and the Progr am Count er wil l just rollov er

from address 0xNNN to 0x000 when incremented.

The configuration word can only be accessed immedi -

atel y after M CLR g oing f rom VIL to VHH. The Program

Counter will be set to all ’1’s upon MCLR =VIL. Thus,

it ha s the valu e “0xFFF” when acce ssing th e configu ra-

tion EPROM. Incrementing the Program Counter once

causes the Program Counter to rollover to all '0's.

Incrementing the Program Counter 4K times after

RESET (MCLR = VIL) does not allow access to the

configu r ati on EPROM .

2.3.1 CUSTOMER ID CODE LOCATIONS

Per definition, the first four words (address TTT to

TTT + 3) are reserved for customer use. It is recom-

mended that the customer us e only the four lower order

bits (bits 0 through 3) of each word and filling the eight

higher order bits with '0's.

A user may want to store an identification code (ID) in

the ID locations and still be able to read this code after

the code pr ot ect ion bit wa s programmed.

EXAMPLE 2-1: CUSTOMER CODE 0xD1E2

The Customer ID code “0xD1E2” should be stored in

the ID locations 0x200-0x203 like this (PIC12C508/

508A/CE518):

200: 0000 0000 1101

201: 0000 0000 0001

202: 0000 0000 1110

203: 0000 0000 0010

Reading these four memory locations, even with the

code protection bit programmed, would still output on

GP0 the bit sequence “1101”, “0001”, “1110”, “0010”

which is “0xD1E2”.

2.4 Program/Verify Mode

The Program/Verify mode is entered by holding pins

GP1 and GP0 low, while raising MCLR pin from VIL to

VIHH (high voltage). Once in this mode, the user pro-

gram memory and the configuration memory can be

acces sed and programm ed in serial fashion. The m ode

of operati on is serial. G P0 and GP1 are Schm itt T rigger

inputs in this mode.

The seque nce that en ters the de vice in to the Program -

ming/Verify mode pla ces all o ther log ic into the RESET

state (the MCLR pin was initially at VIL). This means

that all I/O are in the RESET state (High impedance

inputs).

Note: All oth er lo ca t i ons in P ICm ic ro ® MCU con-

figuration memory are reserved and

should not be program me d.

Note: The MC LR pi n should be rais ed from V IL to

VIHH within 9 ms of VDD rise. This is to

ensure that the device does not have the

PC incremented while in valid operation

range.

PIC12C5XX

DS30557F-page 6  2001 Microchip Technology Inc.

2.4. 1 PROGRAM/VERIFY OPERATION

The GP1 pi n is used as a clock input pin, and the GP0

pin is used for entering command bits and data input/

output during serial operation. To input a command, the

clock p in (G P1) is cyc le d si x tim es . Each co mman d bi t

is latc hed on the falling ed ge of the c lock with t he Leas t

Significant bit (LSb) of the command being input first.

The data on pin GP0 is required to have a minimum

setup and hold t ime (see AC/ DC specs), w ith respect to

the fall ing edg e of the c lock. Com mands tha t have da ta

associated with them (read and load) are specified to

have a minimum delay of 1 µs betwee n the co mmand

and the dat a . After th is delay, the cl ock pi n is cycled 16

times w ith the first cycle be ing a START bit and the last

cycle being a STOP bit. Data is also input and output

LSb first. Therefore, during a read operation, the LSb

will be transmitted onto pin GP0 on the rising edge of

the sec on d c y cle , a nd du ring a load operati on , the LSb

will be latched on the falling edge of the second cycle.

A mini mum 1 µs delay is also spec ified between con-

secutive commands.

All command s are transmitted LSb first . Data words are

also transmitted LSb first. The data is transmitted on

the rising edge and latched on the falling edge of the

clock . To allow for de coding of com mands an d reversal

of data pin configuration, a time separation of at least

1 µs is required between a command and a data word

(or another command).

The commands that are available are lis ted in Table 2-1.

TABLE 2-1: COMMAND MAPPING

Command Mapping (MSb ... LSb) Data

Load Data 000010 0, dat a (14 ), 0

Read Data 000100 0, dat a (14 ), 0

Increment Address 000110

Begin programming 001000

End Programming 001110

Note: The clock must be disabled during in-circuit programming.

 2001 Microchip Technology Inc. DS30557F-page 7

PIC12C5XX

2.4.1.1 Load Data

After receiving this command, the chip will load in a

14-bit “data word” when 16 cycles are applied, as

described previously. Because this is a 12-bit core, the

two MSb’s of the data word are ignored. A timing dia-

gram for the load data command is shown in

Figure 5-1.

2.4.1.2 Read Data

After receiving this command, the chip will transmit

data bits out of the memory currentl y accessed, sta rting

with the se cond rising edge of the cl ock input. The GP0

pin will go into output mode on the second rising clock

edge, and it will revert back to input mode (hi-imped-

anc e) after the 16th rising edge. Becaus e this is a 12-

bit core, the two MSb’s of the data are unu sed and read

as ’0’. A timing diagram of this command is shown in

Figure 5-2.

2.4.1.3 Increment Address

The PC is incremented when this command is

received. A timing diagram of this command is shown

in Figure 5-3.

2.4.1.4 Begin Programming

A load data command must be given before every

begin programming command. Programming of the

appropriate memory (test program memory or user pro-

gram memory) will begin after this command is

received and decoded. Programming should be per-

formed with a series of 100µs programming pulses. A

programming pulse is defined as the time between the

begin programming command and the end program-

ming comman d.

2.4.1.5 End Programming

After receiving this command, the chip stops program-

ming the memory (configuration program memory or

user program memory) that it was programming at the

time.

2.5 Programming Algorithm Requires

Variable VDD

The PIC12C5XX uses an intelligent algorithm. The

algorithm calls for program verification at VDDMIN, as

well as VDDMAX. Verification at VDDMIN guarantees

good “erase margin”. Verification at VDDMAX guaran-

tees good “program margin”.

The actual programming must be done with VDD in the

VDDP range (4.75 - 5.25V).

VDDP =VCC range required during programming.

VDDMIN = minimum operating VDD spec for the part.

VDDMAX = maximum ope rati ng VDD spec for the part.

Programmers must verify the PIC12C5XX at its speci-

fied VDDMAX and VDDMIN levels . Since Microchip may

introduce future versions of the PIC12C5XX with a

broader VDD range, it is best that these levels are user

selectable (defaults are ok).

Note: Any programmer not meeting these

requirements may only be classified as a

“prototype” or “development” programmer,

but not a “production” quality programmer.

PIC12C5XX

DS30557F-page 8  2001 Microchip Technology Inc.

3.0 CONFIGURATION WORD

The PIC12C5XX family members have several config-

urati on bit s. Thes e bit s can be prog ramme d (reads ’0’),

or left unprogrammed (reads ’1’), to select various

device conf igu rations . Figu re 3-1 provide s an overview

of configuration bits.

FIGURE 3-1: CONFIGURATION WORD BIT MAP

Bit

Number: 11 10 9 8 7 65 4 3 2 1 0

PIC12C5XX ————— — —MCLRE CP WDTE FOSC1 FOSC0

bit 11-5: Reserved: Write as ’0’ for PIC12C5XX

bit 4: MCLRE: Master Clear Enable bit

1 = MCLR pin enabled

0 = MCLR internally connected to VDD

bit 3: CP: Code Protect Enable bit

1 = Code memory unprotected

0 = Code memory protected

bit 2: WDTE, WDT Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC<1:0>, Oscillator Selection Bit

11 = External RC oscillator

10 = Internal RC oscillator

01 = XT oscillator

00 = LP oscillator

 2001 Microchip Technology Inc. DS30557F-page 9

PIC12C5XX

4.0 CODE PROTECTION

The progra m code writte n into the EPROM ca n be pr o-

tected by writing to the CP bit of the configuration word.

In PIC12C5XX, it is still possible to program and read

locations 0x000 through 0x03F, after code protection.

Once code protection is enabled, all protected seg-

ments read '0's (or “garbage values”) and are pre-

vented from further programming. All unprotected

segments, including ID locations and configuration

word, read normally. These locations can be pro-

grammed.

Once code protection is enabled, all code protected

locations read 0’s. Al l un prot ected segments , inc lu din g

the intern al oscill ator calib ration val ue, ID, and configu-

ration word read as normal.

4.1 Embedding Configurati on Word and ID Information in the HEX File

TABLE 4-1: CODE PROTECTION

PIC12C508

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

PIC12C508A

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

PIC12C509

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

To allow po rtabili ty of code, the pro grammer is requi red to read the conf iguration w ord and ID locati ons from the HEX

file when loading the HEX file. If configura tion word information was not present in the HEX file, then a simpl e warning

message may be is sued . Similar ly, while savi ng a HEX file, configu rati on word and ID info rmatio n must be includ ed.

An option to not include this information may be provided.

Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x40:0x1FF] Read Disabled (all 0’s), Write Disabled Read Enabled, Write Enabled

ID Locations (0x200 : 0x203) Read Enabled, Write Enabled Read Enabled, Write Enabled

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x40:0x1FE] Read Disabled (all 0’s), Write Disabled Read Enabled, Write Enabled

0x1FF Oscillator Calibration Value Read Enabled, Write Enabled Read Enabled, Write Enabled

ID Locations (0x200 : 0x203) Read Enabled, Write Enabled Read Enabled, Write Enabled

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x40:0x3FF] Read Disabled (all 0’s), Write Disabled Read Enabled, Write Enabled

ID Locations (0x400 : 0x403) Read Enabled, Write Enabled Read Enabled, Write Enabled

PIC12C5XX

DS30557F-page 10  2001 Microchip Technology Inc.

PIC12C509A

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

PIC12CE518

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

PIC12CE519

To code protect:

•(CP enable pattern: XXXXXXXX0XXX)

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled

[0x40:0x3FE] Read Disabled (all 0’s), Write Disabled Read Enabled, Write Enabled

0x3FF Oscillator Calibration Value Read Enabled, Write Enabled Read Enabled, Write Enabled