1. General description
The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs,
which select 4 bits of data from two sources and are controlled by a common data select
input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and
the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data
appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.
The 74AHC257; 74AHCT257 is the logic implementation of a 4-pole 2-position switch,
where the position of the switch is determined by the logic levels applied to input S. The
outputs are forced to a high-impedance OFF-state when OE is HIGH.
The logic equations for the outputs are:
1Y = OE ×(1I1 ×S + 1I0 ×S)
2Y = OE ×(2I1 ×S + 2I0 ×S)
3Y = OE ×(3I1 ×S + 3I0 ×S)
4Y = OE ×(4I1 ×S + 4I0 ×S)
The 74AHC257; 74AHCT257 is identical to the 74AHC258; 74AHCT258, but has
non-inverting (true) outputs.
2. Features
nBalanced propagation delays
nAll inputs have Schmitt-trigger actions
nNon-inverting data path
nInputs accept voltages higher than VCC
nInput levels:
uFor 74AHC257: CMOS level
uFor 74AHCT257: TTL level
nESD protection:
uHBM EIA/JESD22-A114E exceeds 2000 V
uMM EIA/JESD22-A115-A exceeds 200 V
uCDM EIA/JESD22-C101C exceeds 1000 V
nMultiple package options
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Rev. 02 — 9 May 2008 Product data sheet
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 2 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC257
74AHC257D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74AHC257PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74AHCT257
74AHCT257D −40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74AHCT257PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Fig 1. Functional diagram
mgr280
S1
1I0
2
1Y
4
1I1
3
SELECTOR
3-STATE MULTIPLEXER OUTPUTS
2I0
5
2Y
7
2I1
63I0
11
3Y
9
3I1
10 4I0
14
4Y
12
4I1
13
OE
15
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 3 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
mga835
S
OE
1Y
2Y
3Y
4Y
2
3
5
6
11
10
14
13
15
1
4
7
9
12
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
001aad467
15
1G1
1MUX
1
4
2
3
7
5
6
9
11
10
12
14
13
EN
Fig 4. Logic diagram
001aad468
1Y
S
OE
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
2Y
3Y
4Y
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 4 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration SO16 and TSSOP16
257
SVCC
1I0 OE
1I1 4I0
1Y 4I1
2I0 4Y
2I1 3I0
2Y 3I1
GND 3Y
001aad499
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
S 1 common data select input
1I0 2 data input from source 0
1I1 3 data input from source 1
1Y 4 multiplexer output
2I0 5 data input from source 0
2I1 6 data input from source 1
2Y 7 multiplexer output
GND 8 ground (0 V)
3Y 9 multiplexer output
3I1 10 data input from source 1
3I0 11 data input from source 0
4Y 12 multiplexer output
4I1 13 data input from source 1
4I0 14 data input from source 0
OE 15 output enable input (active LOW)
VCC 16 supply voltage
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 5 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
Table 3. Function table[1]
Control Input Output
OE S nI0 nI1 nY
HX XX Z
LH XL L
XH H
LLXL
HX H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VIinput voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V [1] −20 - mA
IOK output clamping current VO < −0.5 V or VO>V
CC + 0.5 V [1] −20 +20 mA
IOoutput current VO = −0.5 V to (VCC + 0.5 V) −25 +25 mA
ICC supply current - +75 mA
IGND ground current −75 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[2] - 500 mW
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 6 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74AHC257
VCC supply voltage 2.0 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V
VCC = 4.5 V to 5.5 V - - 20 ns/V
74AHCT257
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 4.5 V to 5.5 V - - 20 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC257
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V
VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V
VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V
VIL LOW-level
input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V
VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V
VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V
VOH HIGH-level
output voltage VI= VIH or VIL
IO=−50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=−50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
IO=−50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=−4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V
IO=−8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL
IO= 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V
IO= 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 7 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
IIinput leakage
current VI= 5.5 Vor GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND;
VCC = 5.5 V
--±0.25 - ±2.5 - ±10.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4- - - - -pF
74AHCT257
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO=−50 µA 4.4 4.5 - 4.4 - 4.4 - V
IO=−8.0 mA 3.94 - - 3.80 - 3.70 - V
VOL LOW-level
output voltage VI= VIH or VIL; VCC = 4.5 V
IO= 50 µA - 0 0.1 - 0.1 - 0.1 V
IO= 8.0 mA - - 0.36 - 0.44 - 0.55 V
IIinput leakage
current VI= 5.5 Vor GND;
VCC =0Vto5.5V - - 0.1 - 1.0 - 2.0 µA
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND per input
pin; other inputs at
VCC or GND; IO=0A;
VCC = 5.5 V
--±0.25 - ±2.5 - ±10.0 µA
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC = 5.5 V - - 4.0 - 40 - 80 µA
∆ICC additional
supply current per input pin;
VI=V
CC −2.1 V;
other pins at VCC or GND;
IO= 0 A; VCC = 4.5 V to 5.5 V
- - 1.35 - 1.5 - 1.5 mA
CIinput
capacitance VI=V
CC or GND - 3 10 - 10 - 10 pF
COoutput
capacitance -4- - - - -pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 8 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
74AHC257
tpd propagation
delay nI0, nI1 to nY; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 4.2 9.3 1.0 11.0 1.0 12.0 ns
CL= 50 pF - 6.0 12.8 1.0 14.5 1.0 16.0 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 2.9 5.9 1.0 7.0 1.0 7.5 ns
CL= 50 pF - 4.2 7.9 1.0 9.0 1.0 11.5 ns
S to nY; see Figure 6 [2]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.2 11.0 1.0 13.0 1.0 14.0 ns
CL= 50 pF - 7.4 14.5 1.0 16.5 1.0 18.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.5 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 5.0 8.8 1.0 10.0 1.0 12.5 ns
ten enable time OE to nY; see Figure 7 [3]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 4.5 10.5 1.0 12.5 1.0 13.5 ns
CL= 50 pF - 6.4 14.0 1.0 16.0 1.0 17.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.2 6.8 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 4.5 8.8 1.0 10.0 1.0 12.5 ns
tdis disable time OE to nY; see Figure 7 [4]
VCC = 3.0 V to 3.6 V
CL= 15 pF - 5.1 9.5 1.0 11.0 1.0 11.5 ns
CL= 50 pF - 7.2 12.0 1.0 13.5 1.0 14.5 ns
VCC = 4.5 V to 5.5 V
CL= 15 pF - 3.4 6.5 1.0 7.0 1.0 8.5 ns
CL= 50 pF - 4.9 7.9 1.0 9.0 1.0 9.5 ns
CPD power
dissipation
capacitance
fi= 1 MHz; VI= GND to VCC [5]
4 outputs switching via
input S -45- - - - -pF
1 output switching via
input I -15- - - - -pF
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 9 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZL and tPZH.
[4] tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of the outputs.
74AHCT257; VCC = 4.5 V to 5.5 V
tpd propagation
delay nI0, nI1 to nY; see Figure 6 [2]
CL= 15 pF - 3.7 6.5 1.0 8.0 1.0 9.0 ns
CL= 50 pF - 4.9 8.5 1.0 10.0 1.0 11.0 ns
S to nY; see Figure 6 [2]
CL= 15 pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns
CL= 50 pF - 6.4 10.5 1.0 12.5 1.0 13.5 ns
ten enable time OE to nY; see Figure 7 [3]
CL= 15 pF - 3.9 8.0 1.0 9.0 1.0 10.0 ns
CL= 50 pF - 5.1 10.0 1.0 11.0 1.0 12.0 ns
tdis disable time OE to nY; see Figure 7 [4]
CL= 15 pF - 4.5 7.5 1.0 8.0 1.0 8.5 ns
CL= 50 pF - 6.5 9.5 1.0 10.5 1.0 11.5 ns
CPD power
dissipation
capacitance
fi= 1 MHz; VI= GND to VCC [5]
4 outputs switching via
input S -51- - - - -pF
1 output switching via
input I -15- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions 25 °C−40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max Min Max
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 10 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Data inputs and common data select input to output propagation delays
mna486
tPHL tPLH
VM
VM
nI0, nI1, S
input
nY output
GND
VI
VOH
VOL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable and disable times
mna813
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VOL
VOH
VCC
VI
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Type Input Output
VMVMVXVY
74AHC257 0.5 ×VCC 0.5 ×VCC VOL + 0.3 V VOH − 0.3 V
74AHCT257 1.5 V 0.5 ×VCC VOL + 0.3 V VOH − 0.3 V
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 11 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
S1 = test selection switch.
Fig 8. Test circuitry for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74AHC257 VCC ≤3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHCT257 3.0 V ≤3.0 ns 15 pF, 50 pF 1 kΩopen GND VCC
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 12 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
12. Package outline
Fig 9. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 13 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
Fig 10. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 14 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AHC_AHCT257_2 20080509 Product data sheet - 74AHC_AHCT257_1
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 6: the conditions for input leakage current have been changed.
74AHC_AHCT257_1 20000403 Product specification - -
74AHC_AHCT257_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 May 2008 15 of 16
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74AHC257; 74AHCT257
Quad 2-input multiplexer; 3-state
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 May 2008
Document identifier: 74AHC_AHCT257_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16 Contact information. . . . . . . . . . . . . . . . . . . . . 15
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
