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FEATURES
10 years minimu m data retent ion in t he
absence o f exter na l power
Dat a is auto mat ically protected during power
loss
D ir ectly replaces 8k x 8 volat ile static RAM
or EEPROM
Unlim ited writ e cycles
Low-power CMOS
JEDEC standard 28-pin DIP packag e
Read and wr ite access times of 70 ns
Lithium energy source is e lect rica ll y
disconn ected to retain f reshness until power
is a pp lied for the first time
Full ±10% VCC o perating range (DS1225AD)
Option al ±5% VCC o perating range
(DS1225AB)
Optional indust r ia l temperature r ange of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
28-Pin E NC APSUL ATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A12 - Address Input s
DQ0-DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
NC - No Conne c t
DESCRIPTION
The DS1225AB a nd DS1225AD are 65,536-bit, fully static, nonvo latile SR AMs or ganized as 8192 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corrupt ion. The NV SRAMs can be used in p lace o f exist ing 8k x 8 SRAMs dir ect ly co nforming to
the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
micro p ro cesso r interfacing.
DS1225AB/AD
64k Nonvolatile SRAM
www.maxim-ic.com
15
13
27
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
WE
NC
1
2
3
4
5
6
7
8
9
10
11
12
14
28
26
25
24
23
22
21
20
19
18
17
16
A12
A6
A4
NC
19-5625; Rev 11/10
DS1225AB/AD
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READ MODE
The DS1225AB and DS1225AD execut e a r ead cycle w hene ver
WE
(Wr ite Enable) is inactive (high) a nd
CE
(Chip Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 13
address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that
CE
and
OE
access times are also satisfied. If
CE
and
OE
access times are not
satisfied, t hen data acces s must be measured fro m t he later-o cc ur ring s ig na l a nd t he lim it in g pa rame t e r is
eith er tCO for
CE
or tOE for
OE
rather tha n address acce ss.
WRITE MODE
The DS1225AB and DS1225AD execute a write cycle whenever the
WE
and
CE
signals are active
(low) after address inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the
st art o f the write cyc le. The writ e cycle is terminated by the ear lier r ising edge of
CE
or
WE
. All addr ess
inputs must be kept valid throughout the write cycle.
WE
must return to the high state for a minimum
reco very t ime (t WR ) befo re anot her c yc le ca n be initiated. The
OE
control signal should be kept inact ive
(high) during write cyc les to avo id bus content ion. However, if the o utput drivers are enabled (
CE
and
OE
act ive) t hen
WE
will d isab le the outputs in tODW fro m it s falling edge.
DATA RETENTION MODE
The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and write
prot ect s by 4.25 volts. Dat a is maint a ined in the a bsence of VCC without any add it ional suppo rt c ircu it ry.
The nonvolat ile static RAMs constantly mo nitor VCC. Should the supply vo ltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedanc e. As V CC falls belo w appro ximately 3.0 vo lt s, t he po wer swit ching circuit connect s the lithiu m
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
No rma l RAM o perat ion can re sume after VCC exceeds 4.75 vo lt s fo r the DS1225AB and 4.5 vo lt s for t he
DS1225AD.
FRESH NESS SEAL
Each DS1225 is shipped from Maxim with the lithium energy source disconnected, guaranteeing full
energy capacity. When VCC is first applied at a level of greater than VTP , the lithium energy source is
enabled for bat tery backup o p er ation.
DS1225AB/AD
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ABSOLUTE MA XIMUM RATINGS
Voltage on Any Pin Relat ive to Ground -0.3V to +6.0 V
Operating T emper ature
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e -40°C to +85°C
Lead Temperat ure ( soldering, 10s) +260°C
Note: E DI P is wave or ha nd so ldered o nly.
This is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated i n the operation
sections of this specification is not i mplied. Exposure to absolute maxi mum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Note 10)
PARAMETER
SYMBOL
MIN
TYP
MAX
DS1225AB Po wer Supply Volt age
VCC
4.75
5.0
5.25
DS1225AD Power Supply Voltage
VCC
4.50
5.0
5.5
Log ic 1
VIH
2.2
VCC
Logic 0
VIL
0.0
+0.8
(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
DC ELECTRICAL CHARACTERIST ICS (VCC =5V ± 10% for DS1225AD)
PARAMETER
SYMBOL
MIN
TYP
MAX
Input Leakage Cu r r ent
I
IL
-1.0 +1.0 µ
I/O Leakage Cu r r ent
CE
> VIH< VCC
IIO -1.0 +1.0 µA
Output Current @ 2.4V
IOH
-1.0
Output Current @ 0.4V
IOL
2.0
St andby Curr ent
CE
=2.2V ICCS1 5.0 10.0 mA
St andby Curr ent
CE
=VCC -0.5V
ICCS2 3.0 5.0 mA
Operating Cur r ent
(Commercial)
ICC01 75 mA
Operating Cur r ent
(Industrial)
ICC01 85 mA
Write Protection Voltage
(DS1225AB)
VTP 4.50 4.62 4.75 V
Write Protection Voltage
(DS1225AD)
VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
Input Capacitance
CIN
5
10
I nput/Output C apac itance
CI/O
5
10
DS1225AB/AD
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(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
AC ELECTRICAL CHARACTERISTICS (VCC =5V ± 10% for DS1225AD)
PARAMETER SYMBOL
DS1225AB-70
DS1225AD-70
UNITS NOTES
MIN
MAX
Re a d C ycle Time
t
RC
70
ns
Access Time
tACC
70
ns
OE
t o O utput Valid
tOE
35
ns
CE
to Output Va li d tCO
70
ns
OE
or
CE
to O utput Active
tCOE
5
ns 5
Outpu t High Z from Des el ection
t
OD
25
ns
5
Output Ho ld fro m Address
Change tOH
5
ns
Write Cycle Time
tWC
70
ns
Write Pu lse Width
tWP
55
ns
3
A ddress Setup Time
t
AW
0
ns
Write Recovery Time
t
WR1
t
WR2
0
10
ns
ns
12
13
Outpu t High Z from
WE
tODW
25
ns 5
Output Active from WE tOEW
5
ns 5
Da ta Setu p Time
tDS
30
ns
4
Da ta Ho ld Time
t
DH1
tDH2
0
10
ns
ns
12
13
DS1225AB/AD
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1225AB/AD
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA : See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC sl ew f rom VTP to 0V tF 300 µs
VCC slew from 0V to VTP tR 300 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid t o E nd of Wr ite Protectio n tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Retention Time
tDR
10
years
WARNING:
Under no c ircumst anc e ar e negative und ers hoots, of a ny amplitude, a llowed when device is in batt ery
backup mode.
DS1225AB/AD
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NOTES:
1.
WE
is hig h for a r ead cyc le.
2.
OE
= VIH or VIL. If
OE
= VIH during write cycle, the output buffers remain in a high-impedance
state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing low to the ear lier o f
CE
or
WE
go ing h ig h.
4. tDS are measured fr om the earlier o f
CE
or
WE
going hig h.
5. T hese para met er s ar e sampled with a 5 pF load and ar e not 100 % t ested.
6. I f the
CE
lo w transit io n o ccurs simultaneously wit h or later than the
WE
low transit io n, the output
buffers re ma in in a high-impeda nce state during t his per iod.
7. If the
CE
hig h transit io n occurs prio r to or simu lta ne o usly wit h t he
WE
high transit io n, the output
buffers re ma in in a high-impeda nce state during t his per iod.
8. If
WE
is low or the
WE
low transitio n occurs prior to or simult aneously wit h the
CE
low transition,
the output buf fer s remain in a high-impeda nce state during this perio d.
9. Each DS1225AB and each DS1225AD has a built -in swit ch t hat disco nnects t he lit hium so urce unt il
VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of
VCC start ing fro m t he t ime power is first applie d by the user. This parameter is guaranteed by design
and is not 100% t est ed.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, t his range is 0°C to 70°C. Fo r industrial products (IND), this range is -40°C to
+85°C.
11. In a p ower down condition the voltag e on a ny pin may not exce ed the voltage o n VCC.
12. tWR1 , tDH1 are measur ed fr om
WE
going high.
13. tWR2 , tDH2 are measur ed fr om
CE
going high.
14. DS1225 mo dule s are reco gnized by Underwriters Labo r ator ies (UL) under file E 99151.
DC TEST CONDITIONS
Output s Open
Cycle = 200ns for Operating Current
All Voltages Are Re ferenc ed t o Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measur ement Reference Le vels
Input: 1.5V
Output : 1.5V
Input Pulse Rise and Fall Time s: 5 ns
DS1225AB/AD
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ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1225AB-70+
0°C t o +70°C
5V
±
5%
28 720 EDIP
70
DS1225AB-70IND+
-40°C to +85°C
5V
±
5%
28 720 EDIP
70
DS1225AD-70+
0°C t o +70°C
5V ± 10%
28 720 EDIP
70
DS1225AD-70IND+
-40°C to +85°C
5V ± 10%
28 720 EDIP
70
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest pa ckage outline informa t ion a nd land patterns , g o to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
chara cter, but t he dra wing pert ains t o the pa c kage regard less of RoHS status.
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
28 EDIP MDT28+2 21-0245 —
DS1225AB/AD
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added packag e infor mat ion tab le; removed the DIP mo dule package
dra wing a nd dimens ion table
9
11/10
Updated the storage info rmat ion, soldering temperature, and lead
t emperat ur e infor mat ion in the Absolute Maximum Ratings section;
r emoved the -85, -150, and -200 MIN/MAX info rmat io n fro m the
AC Electrical Characteristics table; updated the Ordering
Information table (r emoved -85, -150, a nd -200 parts and leaded -70
parts)
1, 3, 4, 8
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Maxim Integrated:
DS1225AB-150IND+ DS1225AB-200IND+ DS1225AB-70+ DS1225AD-200IND+ DS1225AD-70+ DS1225AD-
70IND+ DS1225AB-200+ DS1225AB-70IND+ DS1225AB-85+ DS1225AD-150+ DS1225AD-150IND+ DS1225AD-
200+ DS1225AD-85+ DS1225AB-170+ DS1225AD-170+