24AA65/P - Microchip Technology

 2003 Microchip Technology Inc. DS21073J-page 1

24AA65/24LC65/24C65

Device Selection Table

Features

• Voltage operati ng range: 1.8V to 6.0V

- Peak write current 3 mA at 6.0V

- Maximum read current 150 µA at 6.0V

- Standby current 1 µA typical

• Industry standard two-wire bus protocol I2C™

compatible

• 8-byte page, or byte modes available

• 2 ms typical write cycle time, byte or page

• 64-byte input cache for fast write loads

• Up to 8 devices may be connected to the same

bus for up to 512K bits total memory

• Including 100 kHz (1.8V ≤ Vcc < 4.5V) and 400

kHz (4.5V ≤ VCC ≤ 6.0V) comp ati bil ity

• Programmable block security options

• Programmable endurance options

• Schmitt Trigger, filtered inputs for noise

suppression

• Output slope control to eliminate ground bounce

• Self-timed erase and write cycles

• Power-on/off data protection circuitry

• Endurance:

- 10,000,000 E/W cy cles for a High Endura nce

Block

- 1,000,000 E/W cycles for a Standard

Endurance Block

• Electrostatic discharge protection > 4000V

• Data rete ntio n > 200 years

• 8-pin PDIP/SOIC packages

• Temperature ranges

Description

The Microchip Technology Inc. 24AA65/24LC65/

24C65 (2 4XX6 5)* is a “sm art ” 8K x 8 Seria l Ele ctrica ll y

Erasable PROM. This device has been developed for

advanced, low-power applications such as personal

communications, and provides the systems designer

with flexibility through the use of many new user-pro-

gramm able fea tures. The 24 XX65 offer s a reloca table

4K bit block of ultra-high-endurance memory for data

that chang es fr equ ent ly. The remainder of the array, or

60K bit s, is rated at 1, 000,000 era se/write (E/W) c ycles

ensured. The 24XX65 features an input cache for fast

write loads with a capacity of eight pages, or 64 bytes.

This device also features programmable security

options for E/W protection of critical data and/or code

of up to fifteen 4K blocks. Functional address lines

allow the connection of up to eight 24XX65's on the

same bus for up to 512K bits contiguous EEPROM

memory. Advanced CMOS technology makes this

device ideal for low-power nonvolatile code and data

applications. The 24XX65 is available in the standard

8-pin plastic DIP and 8-pin surface mount SOIC

package.

Package Types

Part Number VCC Range Page Size Temp. Ranges Packages

24AA65 1.8-6.0V 64 Bytes C P, SM

24LC65 2.5-6.0V 64 Bytes C, I P, SM

24C65 4.5 -6.0V 64 By tes C, I, E P, SM

- Commercial (C): 0°C to +70°C

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

24XX65

SCL

SDA

24XX65

SCL

SDA

PDIP

SOIC

64K I2C™ Smart Serial™ EEPROM

*24XX65 is used in this document as a generic part

number for the 24AA65/24LC65/24C65 devices.

24AA65/24LC65/24C65

DS21073J-page 2  2003 Microchip Technology Inc.

Block Diagram Pin Function Table

HV Generator

EEPROM

Array

Page Lat ches

YDEC

XDEC

Sense Amp.

R/W Control

Memory

Control

Logic

I/O

Control

Logic

SDA

SCL

VCC

VSS

I/O

A2A1A0

Cache

Name Function

A0, A1, A2 User Configurable Chip Selects

VSS Ground

SDA Serial Address/D ata/I/O

SCL Serial Clock

VCC +1.8V to 6.0V Power Supply

NC No Internal Connection

 2003 Microchip Technology Inc. DS21073J-page 3

24AA65/24LC65/24C65

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4 kV

TABLE 1-1: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal ope ration o f the device at thos e or any other co nditio ns abov e those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS

VCC = +1.8V to +6.0V

Commercial (C): TA =0°C to +70°C

Industrial (I): TA =-40°C to +85°C

Automotive (E): TA =-40°C to +125°C

Parameter Sym Min Max Units Conditions

A0, A1, A2, SCL and SDA pins:

High-leve l inpu t voltage

Low-level input voltage

Hyster es is of Sc hm itt Trigger inputs

Low-level output voltage

VIH

VIL

VHYS

VOL

.7 VCC

—

.05 VCC

—

.3 VCC

—

.40

V(Note 1)

IOL = 3.0 mA

Input leakage current ILI —±1µAVIN = .1V to VCC

Output lea kage curre nt ILO —±1µAVOUT = .1V to VCC

Pin capacitance

(all inputs/ou tpu t s) CIN, COUT —10pFVCC = 5.0V (Note 1)

TA = 25°C, FCLK = 1 MHz

Operati ng current ICC Writ e

ICC Read —

—3

150 mA

µAVCC = 6.0V, SCL = 400 kHz

VCC = 6.0V, SCL = 400 kHz

Standby current ICCS —5µAVCC = 5.0V, SCL = SDA = VCC

A0, A1, A2 = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

TSU:STA THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA

24AA65/24LC65/24C65

DS21073J-page 4  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol VCC = 1.8V-6.0V

STD. Mode VCC = 4.5-6.0V

FAST Mode Units Remarks

Min Max Min Max

Clock frequency FCLK —100 — 400kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns (Note 1)

SDA and SCL fall time TF— 300 — 300 ns (Note 1)

Start condition setup time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for

repeated Start condition

Data input hold time THD:DAT 0— 0 —ns

Data input setup time TSU:DAT 250 — 100 — ns

Stop condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Time the bus must be

free before a new

transmission can start

Output fall time from VIH min to

VIL max TOF — 250 20 + 0.1

CB250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppression

(SDA and SC L pins) TSP 50 — 50 — ns (Note 3)

Write cycle time TWR — 5 — 5 ms/page (Note 4)

Endurance

High Endurance Block

Rest of Array 10M

1M —

—10M

1M —

—cycles 25°C, (Note 5)

Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combi ne d TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5: This parame ter is not tested but en sure d by characterization. For endur ance estimates in a specific

applic ation, pleas e cons ult th e Tota l Endura nce™ M odel which c an be downloa ded at ww w.microchip. com.

SCL

SDA

OUT

TSU:STA

TSP

TAA

TLOW

THIGH

THD:STA THD:DAT TSU:DAT TSU:STO

TBUF

TAA

 2003 Microchip Technology Inc. DS21073J-page 5

24AA65/24LC65/24C65

2.0 FUNCTIONAL DESCRIPTION

The 24XX65 supports a bidirectional two-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus must be controlled

by a master device which generates the serial clock

(SCL), c ontrol s the bus acce ss and ge nerates the S tart

and Stop conditions , whil e the 24XX65 works as sl ave.

Both master and slave can operate as transmitter or

receive r, but the master device determines which mode

is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SD A line is sta ble low d uring the high pe riod of

the ack nowledge relat ed clock pu lse. Of co urse, setup

and hold times must be taken into account. During

reads, a maste r mus t sign al an e nd of dat a to the sl ave

by NOT gene rating an Acknowl edge bit on the las t byte

that has been cloc ked o ut o f the slave . In th is ca se, th e

slave (24 XX65) mus t leav e the dat a line high to en able

the master to generate the Stop condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX65 does not generate any

Acknowledge bits if an internal program-

ming cycle is in prog res s.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

To Change

Stop

Condition

24AA65/24LC65/24C65

DS21073J-page 6  2003 Microchip Technology Inc.

3.6 Device Addressing

A control byte is the first byte received following the

S tar t condition from the mas ter device . The contro l byte

consists of a four-bit control code, for the 24XX65 this

is set as ‘1010’ binary for read and write operations.

The next three bits of the control byte are the device

select bits (A2, A1, A0). They are used by the master

device to select which of the eight devices are to be

accessed. These bits are in effect the three Most

Significant bits of the word address. The last bit of the

control byte defines the operation to be performed.

When set to a one a read operation is selected, when

set to a z ero a wri te operation is sele cted. The n ext two

bytes received define the address of the first data byte

(Figure 4-1). Because only A12..A0 are used, the

upper three address bits must be zeros. The Most

Signific ant bit of the Most Significan t Byte is trans ferred

first. Following the Start condition, the 24XX65

monitors the SDA bus checking the device type

identifier being transmitted. Upon receiving a ‘1010’

code and appropriate device select bits, the slave

device (24XX65) output s an Acknowledge signal on the

SDA lin e. Dep en din g u pon the state of the R/W bi t, th e

24XX65 will select a read or write operation.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start condition from the master, the con-

trol code (four bits), the device select (three bits ), and

the R/W bit which is a logic low, is placed onto the bus

by the master transmitter. This indicates to the

addressed slave receiver (24XX65) that a byte with a

word address will follow after it has generated an

Acknowledge bit during the ninth clock cycle. There-

fore, the next byte transmitted by the master is the

high-order byte of the word address and will be written

into the address pointer of the 24XX65. The next byte

is the Least Significant Address Byte. After receiving

another Acknowledge signal from the 24XX65, the

master device will transmit the data word to be written

into the addressed memory location. The 24XX65

acknowledges again and the master generates a Stop

condition. This initiates the internal write cycle, and

during this time the 24XX65 will not generate

Acknowledge signals (Figure 4-1).

4.2 Page Write

The write cont rol byte , word address and the first data

byte are transmitted to the 24XX65 in the same way as

in a byte write. But instead of generating a Stop

condition, the master transmits up to eight pages of

eight data bytes each (64 bytes total), which are

temporarily stored in the on-chip page cache of the

24XX65. They will be written from the cache into the

EEPROM array after the master has transmitted a Stop

conditi on. After the receipt of e ach word, the si x lower

order address pointer bits are internally incremented by

one. The higher order seven bits of the word address

remain constant. If the master should transmit more

than eight bytes prior to generating the Stop condition

(writi ng across a page boundary) , the address counter

(lower three bits) will roll over and the pointer will be

incremente d to poi nt to the n ext line in the ca che. Th is

can continue to occur up to eight times or until the cache

is full, at which time a Stop condition should be

generated by the master. If a Stop condition is not

received, t he cache poi nter w ill roll over to the f irst lin e

(byte 0) of the cache, and any further data received will

overwrite pr eviously captured data. The Stop condi tion

can be sent at any t ime dur ing the tran sfe r. As with the

byte write operation, once the Stop condition is received

an internal write cycle will begin. The 64-byte cache will

continue to capture data until a S top condition occurs or

the operation is aborted (Figure 4-2).

Operatio n Control Code Device Select R/W

Read 1010 Device Address 1

Write 1010 Device Address 0

SLAVE ADDRESS

1 0 1 0 A2 A1 A0

R/W A

START READ/WRITE

 2003 Microchip Technology Inc. DS21073J-page 7

24AA65/24LC65/24C65

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2)

FIGURE 4-3: CURRENT ADDRESS READ

000

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS (1) WORD

ADDRESS (0) DATA

BUS

MASTER

SDA LINE

BUS

CONTROL

BYTE WORD

ADDRESS (1) S

ACTIVITY

ACTIVITY:

DATA n DATA n + 7

WORD

ADDRESS (0)

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE DATA n

24AA65/24LC65/24C65

DS21073J-page 8  2003 Microchip Technology Inc.

FIGURE 4-4: RANDOM READ

FIGURE 4-5: SE QUENTIAL READ

DA LINE

BUS

CONTROL

BYTE WORD

ADDRESS (1) S

ACTIVITY A

DATA n

000

WORD

ADDRESS (0)

TCONTROL

BYTE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

 2003 Microchip Technology Inc. DS21073J-page 9

24AA65/24LC65/24C65

5.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There a re three ba sic types

of read operat ions: current address read , rand om rea d

and sequential read.

5.1 Current Address Read

The 24XX65 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a re ad or wri te opera tion) was to addre ss n (n is

any legal address), the next current address read

operatio n wou ld acc ess dat a fr om add ress n + 1. U pon

receipt of the slav e address w ith R/W bit s et to one, the

24XX65 issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the tr ansfer bu t does ge nerate a Stop con dition an d the

24XX65 discontinues transmission (Figure 4-3).

5.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope ration, first the wo rd address mus t

be set. This is done b y sending the word address to the

24XX65 as p art of a write operati on (R/W bit se t to ‘0’).

After the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal address pointer is set. Then the master issues

the control byte again, but with the R/ W bit set to a one.

The 24XX65 will then issue an acknowledge and

transmit the eight-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition which causes the 24XX65 to discontinue

transmission (Figure 4-4).

5.3 Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX65 transmits the

first data byte, the master issues an acknowledge as

opposed to t he Stop co ndition used in a r andom read.

This acknowledge directs the 24XX65 to transmit the

next sequentially addressed 8-bit word (Figure 4-5).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge, but will

generate a S top condition.

To provide sequential reads the 24XX65 contains an

inter nal address poi nter which i s incremented b y one at

the com ple tio n o f ea ch ope rati on. This a ddr ess po in ter

allows the entire memory contents to be serially read

during one operation.

5.4 Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX65's on the same bus.

In this c as e, so ftware c an use A0 of the c on trol b yte as

address bit A13, A1 as address bit A14 and A2 as

address bit A15.

5.5 Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operatio n even o n a nois y bus. Al l I/O li nes inc orpora te

Schmitt T ri ggers for 400 kHz (Fast mo de) compa tibility.

5.6 High Endurance Block

The location of the high endurance block within the

memory map is programmed by setting the leading bit

7 (S/HE) of the con fig uration by te to ‘0’ . Th e up per bits

of the address loaded in this command will determine

which 4K block within the memory map will be set to

high endurance. This block will be capable of

10,000,0 00 eras e/w ri te cy cle s typ ic al (Fig ure 8-1).

The high endurance block will retain its value as the

high endurance block even if it resides within the

security block range. The high endurance setting

always takes precedence to the security setting.

Note: The high endurance block cannot be

changed after the security op tion has been

set with a length greater than zero. If the

H.E. bloc k is not program med by th e user,

the default location is the highest block of

memory which starts at location 0x1E00

and ends at 0x1FFF.

24AA65/24LC65/24C65

DS21073J-page 10  2003 Microchip Technology Inc.

5.7 Security Options

The 24XX65 has a sophisticated mechanism for write

protecting portions of the array. This write-protect

function is programmable and allows the user to protect

0-15 contiguous 4K blocks. The user sets the security

option by sending to the device the starting block

number for the protected region and the number of

blocks to be protected. All parts will come from the

factory in the default configuration with the starting

block number set to 15 and the number of protected

blocks set to zero. THE SECURITY OPTION CAN BE

SET ONLY ONCE WITH A LENGTH GREATER THAN

ZERO.

To invok e th e s ec urit y o pti on, a W r it e c om ma nd is se nt

to the device with the leading bit (bit 7) of the first

address byte set to a ‘1’ (Figure 8-1). Bits 1-4 of the first

address byte define the starting block number for the

protected region.

For exam ple, i f the s tart ing bl ock n umber is to be s et to

5, the first address byte would be 1XX0101X. Bits 0, 5

and 6 of the f irst ad dress by te are d isregar ded by the

device and can be either high or low. The device will

acknowledge after the first address byte. A byte of don’t

care bits is then sent by the master, with the device

acknowledging afterwards. The third byte sent to the

device has bit 7 (S/HE) set high and bit 6 (R) set low.

Bits 4 and 5 are don’t cares and bits 0-3 define the

number of bl ocks to be write-prote cted. For ex ampl e, if

three blo cks are to be protected, the th ird byte would be

10XX0011. After the third byte is sent to the device, it

will acknowledge an d a S top bit is then sent by the mas-

ter to complete the command.

If one of the security blocks coincides with the high

endurance block, the high endurance setting will take

precedence. Also, if the range of the security blocks

enc ompass the hi gh endur ance bl ock wh en the se cu-

rity option is set, the security block range will be set

accordi ng ly, but the high en du ranc e b loc k w i ll c on tinu e

to retain the high endurance setting. As a result, the

memory blocks preceding the high endurance blo ck will

be set as secure sections.

During a normal write sequence, if an attempt is made

to write to a protected address, no data will be written

and the device will not report an error or abort the

command. If a Write command is attempted across a

secure boundary , un protected addresses will be written

and protected addresses will not.

5.8 Security Configuration Read

The st atus o f the secu re portion of memory can be read

by using the same technique as programming this

option except the read bit (bit 6) of the configuration

byte is set to a on e. After the c onfigu ration byte i s sen t,

the device will acknowledge and then send two bytes of

data to the master just as in a normal read sequence.

The master must acknowledge the first byte and not

acknowledge the second, and then send a Stop bit to

end the seque nc e. The upper four bit s of both of thes e

bytes will always be read as ‘1’s. The lower four bits of

the first byte contains the starting secure block. The

lower four bits of the second byte contains the number

of secure blocks. The default starting secure block is

fifteen and the default number of secure blocks is zero

(Figure 8-1).

6.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , th e device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycl e, then no ACK will be returne d.

If the cycle is complete, then the device will return the

ACK and the master can then proceed with the next

Read or Write command. See Figure 6-1 for flow

diagram.

FIGURE 6-1: ACKNOWLEDGE

POLLING FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

 2003 Microchip Technology Inc. DS21073J-page 11

24AA65/24LC65/24C65

7.0 PAGE CACHE AND ARRAY

MAPPING

The cache is a 64-byte (8 pages x 8 bytes) FIFO buffer .

The cache allows the loading of up to 64 bytes of data

before the write cycle is actually begun, effectively

providing a 64-byte burst write at the maximum bus

rate. When ever a Write command is initi ated, the cache

start s load ing and will contin ue to load un til a Stop bit is

received to start the internal write cycle. The total

length of the write cycle will depend on how many

pages are loaded into the cache before the Stop bit is

given. Maximum cycle time for each p age is 5 ms. Even

if a page is only partially loaded, it will still require the

same cy cle time a s a full page. If more than 64 bytes of

data are loaded before the Stop bit is given, the

address pointer will ‘wrap around’ to the beginning of

cache page 0 and existing bytes in the cache will be

overwritten. The device will not respond to any

comm ands while the wri te cycle is in progress.

7.1 Cache Write Starting at a Page

Boundary

If a Write command begins at a page boundary

(address bits A2, A1 and A0 are zero), then all data

loaded into the cache will be written to the array in

sequential addresses. This includes writing across a

4K block boundary. In the example shown below,

(Figure 8-2) a Write command is initiated starting at

byte 0 of page 3 with a fully loaded cache (64 bytes).

The firs t by te in the cach e i s wri tte n to by te 0 o f p a ge 3

(of the array), with the remaining pages in the cache

written to seque ntial p age s in the array. A wri te cycle i s

executed after each page is written. Since the write

begins at page 3 and 8 pages are loaded into the

cache, the last 3 pages of the cache are written to the

next row in the array.

7.2 Cache Write Starting at a

Non-Page Boundary

When a Writ e comm and is in iti ated tha t does not begin

at a page boundary (i.e., address bits A2, A1 and A0

are not all zero), it is important to note how the data is

loaded in to the cache , and how the dat a in the cache is

written to the arra y . When a W rite command begins, th e

first byte loaded into the cache is always loaded into

page 0. The byte within page 0 of the cache where the

load be gins is determined by the three Lea st Significant

Address bits (A2, A1, A0) that were sent as part of the

W rite command . If the Write co mmand does no t start at

byte 0 of a page and the cache i s ful ly lo ade d, the n the

last byte(s) loaded into the cache will roll around to

page 0 o f the ca ch e and fi ll th e rem aining e mp ty by tes .

If more than 64 b ytes of dat a are load ed into the cach e,

data already loaded will be overwr itte n. In the e xam pl e

shown in Figure 8-3, a Write command has been

initiated starting at byte 2 of page 3 in the array with a

fully l oad ed cache of 64 by tes . Si nc e t he cac he s t arted

loading at byte 2, the last two bytes loaded into the

cache will ‘roll over' and be loaded into the first two

bytes of page 0 (of the cache). When the Stop bit is

sent, page 0 of the cache is written to page 3 of the

array. The remaining pages in the cache are then

loaded sequentially to the array. A write cycle is

execute d after each page is wr itten. If a partially lo aded

page in the cache remains when the Stop bit is sent,

only the bytes that have been loaded will be written to

the array.

7.3 Power Management

The design incorporates a power Standby mode when

not in use and au tomatically powers of f after the normal

terminat ion of any operation when a S top bit is received

and all internal functions are complete. This includes

any error conditions (i.e., not receiving an Acknowl-

edge or Stop condition per the two-wire bus specifica-

tion). The device also incorporates VDD monitor

circuitry to prevent inadvertent writes (data corruption)

during l ow voltage conditio ns. The VDD monitor circuitry

is powered off when the device is in Standby mode in

order to f urther reduce power consumption.

8.0 PIN DESCRIPTIONS

8.1 A0, A1, A2 Chip Address Inputs

The A0..A2 in puts are used by the 24XX65 for m ult ipl e

device operation and conform to the two-wire bus

standard. The levels applied to these pins define the

address block occupied by the device in the address

map. A parti cu lar de vi ce is s ele cte d by transmit ting th e

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-2 and Figure 8-1).

8.2 SDA Serial Address/Data Input/

Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typic al 10 KΩ for 100 kHz, 2 KΩ for 400

kHz).

For norma l data trans fer SDA is allowed to change onl y

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

8.3 SCL Serial Clock

This inpu t is used to sy nchronize the data tra nsfer from

and to the device.

24AA65/24LC65/24C65

DS21073J-page 12  2003 Microchip Technology Inc.

FIGURE 8-1: CONTROL SEQUENCE BIT ASSIGNMENTS

Control Byte

0R/W

0101 A

Address Byte 1

11 A

00S A

•••

Address Byte 0

Slave

Address Device

Select

Bits

•••

12 B

Configuration Byte

XR X

Block

Count

S/HE

0101 X

XXX

XX1 X

Starting Block

Number

XXX

XXA

XXX

X11 XA

111 1N

111 1

Number of

Blocks to

Protect

ACK

Data from Device

Acknowledge

from

Master

Data from Device

Acknowledges from Device

0101 B

XX1 B

XXX

XXN

X01 XA

Acknowledges from Device

0101 X

XXX

XX1 X

High Endurance

Block Number

XXX

XXA

XXX

X10 XA

111 1

ACK

Data from Device

Acknowledges from Device

0101 B

XX1 B

XXX

XXA

000

X00 XA

Acknowledges from Device

Starting Block

Number Number of

Blocks to

Protect

S/HE

ecurity Read

ecurity Write

igh Endurance Block Read

igh Endurance Block Write

High Endurance

Block Number

 2003 Microchip Technology Inc. DS21073J-page 13

24AA65/24LC65/24C65

FIGURE 8-2: CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY

FIGURE 8-3: CACHE WRITE T O THE ARRAY STARTING AT A NON-PAGE BOUNDARY

1Write command initiated at byte 0 of page 3 in the array;

First data byte is loaded into the cache byte 0. 2 64 bytes of data are loaded into cache.

3Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written. 4 Remaining pages in cache are written

to sequential pages in array.

cache

byte 0 cache

byte 1 • • • cache

byte 7 cache page 1

bytes 8-15 • • •

page 0

cache page 2

bytes 16-23 cache page 7

bytes 56-63

page 1 page 2 • • • byte 7 • • •

page 4 • • • page 7page 3

cache page 0

Last page in cache written to page 2 in next row.

array row n

array row n + 1

page 0 page 1 page 2 byte 0 byte 1 page 4 page 7

1 Write command initiated; 64 bytes of data

loaded into cache starting at byte 2 of page 0. 2 Last 2 bytes loaded 'roll over'

to beginning.

ast 2 bytes

oaded into

age 0 of cache.

4 Write from cache into array initiated by STOP bit.

Page 0 of cache written to page 3 of array.

Write cycle is executed after every page is written.

cache

byte 1 cache

byte 2 • • • cache

byte 7 cache page 1

bytes 8-15 • • •

page 0

cache page 2

bytes 16-23 cache page 7

bytes 56-63

page 1 page 2 • • • • • •

page 4 • • • page 7page 3

Remaining bytes in cache are

written sequentially to array.

array

row n

array

row

n + 1

cache

byte 0

Last 3 pages in cache written to next row in array.

page 1 page 2 byte 0 byte 2byte 1 page 4 page 7

byte 7byte 3 byte 4

page 0

24AA65/24LC65/24C65

DS21073J-page 14  2003 Microchip Technology Inc.

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (208 mil) Example:

24LC65

0110017

I/SM

24LC65

I/P017

0310

XXXXXXXX

YYWWNNN

T/XXXXXX

Legend: XX...X C ustom er spe ci fic informati on *

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

T Temperature grade (Blank = Commercial, I = Industrial,

E = Automotive)

Note: In the event th e full Mi croch ip pa rt numbe r cannot be marke d on one line, it will

be carried ov er to the ne xt l ine t hus limiting the nu mb er of av ai lable cha rac ters

for customer specific information.

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2003 Microchip Technology Inc. DS21073J-page 15

24AA65/24LC65/24C65

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .11 5 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24AA65/24LC65/24C65

DS21073J-page 16  2003 Microchip Technology Inc.

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.430.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.640.51.030.025.020LFoot Length 5.335.215.13.210.205.202DOverall Length 5.385.285.11.212.208.201E1Molded Pa ckag e Width 8.267.957.62.325.313.300EOverall Width 0.250.130.05.010.005.002A1Standoff § 1.98.078A2Molded Pa ckag e Thick ness 2.03.080AOverall Height 1.27.050

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units

.070 .075

.069 .074 1.78

1.75 1.97

1.88

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

§ Significant Characteristic

 2003 Microchip Technology Inc. DS21073J-page 17

24AA65/24LC65/24C65

APPENDIX A: REVISION HISTORY

Revision J

Corrections to Section 1.0, Electrical Characteristics.

24AA65/24LC65/24C65

DS21073J-page 18  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS21073J-page 19

24AA65/24LC65/24C65

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape® or Microsoft®

Internet Explorer. Files are also available for FTP

download from our FTP site.

Connecting to the Microchip Internet

Web S ite

The Microchip web site is available at the following

URL:

www.microchip.com

The file transfer site is available by using an FTP

service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errat a

• Job Postin gs

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Confere nces for prod ucts, Dev elopment Systems,

technical information and more

• Listing of seminars and events

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive the mo st current upgrade kits. The Hot Line

Numbe rs are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

042003

24AA65/24LC65/24C65

DS21073J-page 20  2003 Microchip Technology Inc.

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21073J24AA65/24LC65/24C65

1. What are the best fe atures of this doc ument ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2003 Microchip Technology Inc. DS21073J-page 21

24AA65/24LC65/24C65

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device 24AA65 - 64K I2C 1.8V Serial EEPROM (100 kHz)

24AA65T - 64K I2C 1.8V Serial EEPROM (100 kHz)

24LC65 - 64K I2C Serial EEPROM (100 kHz/400 kHz)

24LC65T - 64K I2C Serial EEPROM (Tape and Reel)

24C65 - 64K I2C 4.5V Serial EEPROM (400 kHz)

24C65T - 64K I2C 4.5V Serial EEPROM (Tape and Reel)

Temper atu re R ang e Bl ank = 0°C to +70°C

I= -40°C to +85°C

E= -40°C to +125°C

Package P = Plastic DIP (300 mil Body)

SM = Plastic SOIC (207 mil Body, EIAJ standard)

Examples:

a) 24LC65T-I/SM: 64 Kbit Smart Serial,

Tape and Reel, 207 mil SOIC package,

Industrial temperature, 2.5V

b) 24LC65-I/P: 64 Kbit Smart Serial,

Industrial temperature, PDIP package,

2.5V

c) 24AA65T-/SM: 64 Kbit Smart Serial,

Tape and Reel, 207 mil SOIC package,

Commercial temperature, 1.8V

d) 24C65-E/P: 64 Kbit Smart Serial,

Automotive temperature, PDIP, 5V

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microc hip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www. micr ochip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

24AA65/24LC65/24C65

DS21073J-page 22  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS21073J-page 23

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporat ed with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’ s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PIC micro, PICSTART,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PI CMASTER,

SEEVAL and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor , SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorpora ted in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such a c t s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and M ountain View, California i n March 20 02.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micr operipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of developmen t

systems is ISO 9001 certified.

DS21073J-page 24  2003 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792- 72 00

Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://ww w.microchip .com

Atlanta

3780 Mansell Road, Suite 130

Alpharetta, GA 30022

Tel: 770-6 40- 003 4

Fax: 770-640-0307

Boston

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-6 92- 384 8

Fax: 978-692-3821

Chicago

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-2 85- 007 1

Fax: 630-285-0075

Dallas

4570 Westgrove Drive, Suite 160

Addison, TX 7500 1

Tel: 972-8 18- 742 3

Fax: 972-818-2924

Detroit

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-5 38- 225 0

Fax: 248-538-2260

Kokomo

2767 S. Albright Road

Kokomo, IN 46902

Tel: 765-8 64- 836 0

Fax: 765-864-8387

Los A n ge les

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949-2 63- 188 8

Fax: 949-263-1338

Phoenix

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792- 79 66

Fax: 480-792-4338

San Jose

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-4 36- 795 0

Fax: 408-436-7955

Toronto

6285 Northam Drive, Suite 108

Mississ aug a, Ontario L4V 1X5, C ana da

Tel: 905-6 73- 069 9

Fax: 905-673-6509

ASIA/PACIFIC

Australia

Suite 22, 41 Rawson Street

Epping 2121, NSW

Australia

Tel: 61-2- 986 8-6 73 3

Fax: 61-2-9868-6755

China - Beijing

Unit 915

Bei Hai Wa n Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10 -85 282 10 0

Fax: 86-10-85282104

China - Chengdu

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Chengdu 610016, China

Tel: 86-28 -86 766 20 0

Fax: 86-28-86766599

China - Fuzhou

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

Tel: 86-59 1-7 503 50 6

Fax: 86-591-7503521

China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2 401 -12 00

Fax: 852-2401-3431

China - Sh a ngha i

Room 701, Bldg. B

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21 -62 75- 57 00

Fax: 86-21-6275-5060

China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-75 5-8 290 13 80

Fax: 86-755-8295-1393

China - Sh unde

Room 401, Hongjian Building

No. 2 Fengxiangnan Road, Ronggui Town

Shunde City, Guangdong 528303, China

Tel: 86-765-8395507 Fax: 86-765-8395571

China - Qingda o

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Tel: 86-532-5027355 Fax: 86-532-5027205

India

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalo re, 560 025, Indi a

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45 -47 1- 616 6 Fax: 81-4 5-4 71-6122

Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

Singapore

200 Middle Road

#07-02 Prime Centre

Singapore, 188980

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

Min Chuan 2nd Road

Kaohsiung 806, Taiwan

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan

Taiwan Branch

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Austria

Durisolstrasse 2

A-4600 Wels

Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Regus Business Centre

Lautrup hoj 1-3

Balleru p DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

France

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - l er Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

P. A. De Biesbosch 14

NL-5152 SC Drunen, Netherlands

Tel: 31-416-690399

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Winnersh Triangle

Wokingham

Berk shire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

07/28/03

WORLDWIDE SALES AND SERVICE