2004 Microchip Technology Inc. Preliminary DS41239A
PIC10F200/202/204/206
Data Sheet
6-Pin, 8-Bit Flash Microcontrollers
DS41239A-page ii Preliminary 2004 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular M icrochip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrit y of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violat ion of the Digital Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc. Preliminary DS41239A-page 1
PIC10F200/202/204/206
Devices Included In This Data Sheet:
•PIC10F200
•PIC10F202
•PIC10F204
•PIC10F206
High-Performance RISC CPU:
• Only 33 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
• 12-bit wide instructions
• 2-level deep hardware stack
• Direct, Indirect and Relative Addres sing modes
for data and instructions
• 8-bit wide data path
• 8 Special Function Hardware registers
• Operati ng spe ed:
- 4 MHz internal clock
-1µs instruct ion cycle
Special Micr ocontroller Features:
• 4 MHz precision internal oscillator:
- Factory calibrated to ±1%
• In-Circuit Serial Program ming™ (ICSP™)
• In-Circuit Debugging (ICD) support
• Power-on Reset (POR)
• Device Re se t Timer (DRT)
• Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
• Programmable code protection
• Multiplexed MCLR input pin
• Internal weak pull-ups on I/O pins
• Power-s aving Sleep mode
• Wake-up from Sleep on pin change
Low-Power Features/CMOS Technology:
• Operating Current:
- < 350 µA @ 2V, 4 MHz
• Standby Current:
- 100 nA @ 2V, typical
• Low-power, high-speed Flash technology:
- 100,000 Flash endura nce
- > 40 year retention
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Wide temperature range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Peripheral Feat ures (PIC10F200/202):
• 4 I/O pins:
- 3 I/O pins with individual direction control
- 1 input only pin
- High current si nk/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-bit real-time clock/counter (TMR0) with 8-bit
progra mmab le pres caler
Peripheral Feat ures (PIC10F204/206):
• 4 I/O pins:
- 3 I/O pins with individual direction control
- 1 input only pin
- High current si nk/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-bit real-time clock/counter (TMR0) with 8-bit
progra mmab le pres caler
• 1 Compara tor
- Internal absol ute vol t ag e reference
- Both comparator inputs visible ex ternally
- Comparator output visible externally
6-Pin, 8-Bit Flash Microcontrollers
PIC10F200/202/204/206
DS41239A-page 2 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams
TABLE 1-1: PIC10F2XX MEMORY AND FEATURES
Device Program Memo ry Data Memory I/O Timers
8-bit Comparator
Flash (words) SRAM (bytes)
PIC10F200 256 16 4 1 0
PIC10F202 512 24 4 1 0
PIC10F204 256 16 4 1 1
PIC10F206 512 24 4 1 1
PIC10F200/202
1
2
3
6
5
4
GP0/ICSPDAT
VSS
GP1/ICSPCLK
GP3/MCLR/VPP
VDD
GP2/T0CKI/FOSC4
SOT-23
PIC10F204/206
1
2
3
6
5
4
GP0/ICSPDAT/CIN+
VSS
GP1/ICSPCLK/CIN-
GP3/MCLR/VPP
VDD
GP2/T0CKI/COUT/FOSC4
SOT-23
GP2/T0CKI/FOSC4
N/C
N/C
N/C
N/C
GP2/T0CKI/COUT/FOSC4
PDIP PDIP
PIC10F200/202
1
2
3
4
8
7
6
5
VDD
GP3/MCLR/VPP
VSS
GP0/ICSPDAT
GP1/ICSPCLK
PIC10F204/206
1
2
3
4
8
7
6
5
VDD
GP3/MCLR/VPP
VSS
GP0/CIN+
GP1/ICSPCLK/CIN-
2004 Microchip Technology Inc. Preliminary DS41239A-page 3
PIC10F200/202/204/206
Table of Contents
1.0 General Description............... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .. ......... .. .... .. .. .... ................................................................... 5
2.0 PIC10F200/202/204/206 Device Varieties ..................... ....... .. .. .. .... .. .. ....... .... .. .. .. .... ....... .. .. .... .. .. .. .............................................. 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I /O Po r t...................... ................... ................... ................... .................. ...................................................................................... 25
6.0 Timer0 Module and TMR0 Register (PIC10F200/202)............................................................................................................... 29
7.0 Timer0 Module and TMR0 Register (PIC10F204/206)............................................................................................................... 33
8.0 Comparator Module............................ .... .. ......... .... .. .... .... ....... .... .. .... .... ....... .... .... .. .... ....... .......................................................... 37
9.0 Sp e cial Features of the CPU............ .......... ................... ................... ........... ................... ............................................................ 41
10.0 Instruction Set Summary............................................................................................................................................................ 51
11.0 Developm ent Suppor t. ............................................................. ................................................................................................... 59
12.0 Electrical Characteristics............................................................................................................................................................ 65
13.0 DC and AC Characteristics Graphs and Charts................................. ......... .... .... .... ........... .... .... .... ............................................ 75
14.0 Packagin g In fo rmation........................ ........... .................. ................... ................... ..................................................................... 77
Index .................................................................................................................................................................................................... 81
On-Line Support... .... .. ......... .... .. .... .. ......... .... .. .... ......... .. .... .. .... ......... .. .... .... .. ......... .. .... .... .. ................................................................... 83
Systems Information and Upgrade Hot Line........................................................................................................................................ 83
Reader Response................................................................................................................................................................................ 84
Product Identification System .............................................................................................................................................................. 85
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PIC10F200/202/204/206
DS41239A-page 4 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 5
PIC10F200/202/204/206
1.0 GENERAL DESCRIPTION
The PIC10F200/202/204/206 devices from Microchip
Techno logy are low -cost, high-pe rformance, 8-b it, fully-
static, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single
cycle (1 µs) except for program branches, which take
two cycles. The PIC10F200/202/204/206 devices
deliver performance in an order of magnitude higher
than their competitors in the same price category. The
12-bit wide instructions are highly symmetrical, result-
ing in a typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy to use and easy
to remember instruction set reduces development time
significantly.
The PIC10F200/202/204/206 products are equipped
with special features that reduce system cost and
power requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for
external Reset circuitry. INTRC Internal Oscillator
mode is provided, thereby preserving the limited
number of I/O available. Power-saving Sleep mode,
Watchdog Timer and code protection features improve
system cost, power and rel iabilit y.
The PIC10F200/202/204/206 devices are available in
cost-effective Flash, which is suitable for production in
any volume. The customer can take full advantage of
Microchip’s price leadership in Flash programmable
microcontrollers, while benefiting from the Flash
programmable flexibility.
The PIC10F200/202/204/206 products are supported
by a full-featured macro assembler, a software simu la-
tor, an in-circuit debugger, a ‘C’ compiler, a low-cost
development programmer and a full featured program-
mer. All the tools are supported on IBM® PC and
compatible machin es.
1.1 Applications
The PIC10F2 00/202/204/20 6 devic es fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient. The smal l footpri nt p ackag es, for t hrough h ole or
surface mounting, make these microcontrollers well
suited for app li cation s with sp ace lim ita tio ns. Low cos t,
low power, high performance, ease of use and I/O
flexibility make the PIC10F200/202/204/206 devices
very versatile even in areas where no microcontroller
use has been considered before (e.g., timer functions,
logic and PLDs in larger systems and coprocessor
applications).
TABLE 1-1: PIC10F200/202/204/206 DEVICES
PIC10F200 PIC10F202 PIC10F204 PIC10F206
Clock Maximum Frequenc y of Operation (MHz) 4 4 4 4
Memory Flash Program Memory 256 512 256 512
Data Memory (bytes) 16 24 16 24
Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0
Wake-up from Sleep on Pin Change Yes Yes Yes Yes
Comparators 0 0 1 1
Features I/O Pins 3 3 3 3
Input Only Pins 1 1 1 1
Internal Pull-ups Yes Yes Yes Yes
In-Circuit Serial Programming Yes Yes Yes Yes
Number of Instructions 33 33 33 33
Packages 6-pin SOT-23
8-pin PDIP 6-pin SOT-23
8-pin PDIP 6-pin SOT-23
8-pin PDIP 6-pin SOT-23
8-pin PDIP
The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Tim er, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC10F200/202/204/206 device uses serial programming with data pin GP0 and clock pin GP1.
PIC10F200/202/204/206
DS41239A-page 6 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 7
PIC10F200/202/204/206
2.0 PIC10F200/202/204/206 DEVICE
VARIETIES
A variety of packaging options are available. Depend-
ing on application and production requirements, the
proper device option can be selected using the
information in this section . When placing orders, please
use the PIC 1 0F2 00/2 02 /204 /20 6 Prod uc t Ide ntif ic atio n
System at the back of this data sheet to specify the
correct part numbe r.
2.1 Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
cont act your loc al Microchip Technol ogy sales of fice for
more details.
2.2 Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
PIC10F200/202/204/206
DS41239A-page 8 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 9
PIC10F200/202/204/206
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC10F200/202/ 204/206
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC10F200/202/204/206 devices use a
Harvard architecture in which program and data are
accessed on separate buses. This improves band-
width over traditional von Neumann architectures
where program and data are fetched on the same bus.
Separating program and data memory further allows
instructions to be sized differently than the 8-bit wide
data word. Instruction opcodes are 12 bits wide,
making it possible to have all single-word instructions.
A 12-bit wide program memory access bus fetches a
12-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (33) execut e in a single
cycle (1 µs @ 4 MHz) except for program branches.
The t able belo w lists p rogram memo ry (Flash) and data
memory (RAM) for the PIC10F200/202/204/206
devices.
TABLE 3-1: PIC10F2XX MEMORY
The PIC10F200/202/204/206 devices can directly or
indirec tly addres s its register f iles and data m emory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC10F200/202/
204/206 devices have a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation, on any register, using any
addressing mode. This symmetric al nature and lack of
“special optimal situations” make programming with the
PIC10F200/202/204/206 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
The PIC10F200/202/204/206 devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean fu nctions be tween da ta in the w orking regist er
and any register file.
The ALU is 8 bits wide and capable of addition, subtrac-
tion, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one oper-
and is typically the W (working) register. The other
operand is either a file register or an immediate
const ant. I n sing le ope rand in struc tions, the ope rand i s
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the Status register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1 and
Figure 3-2, with the corresponding device pins
describ ed in Table 3-2.
Device Memory
Program Data
PIC10F200 256 x 12 16 x 8
PIC10F202 512 x 12 24 x 8
PIC10F204 256 x 12 16 x 8
PIC10F206 512 x 12 24 x 8
PIC10F200/202/204/206
DS41239A-page 10 Preliminary 2004 Microchip Technology Inc.
FIGURE 3-1: PIC10F20 0/202 BLOCK DIAGRAM
Flash
Program
Memory
9-10 Data Bus 8
12
Program
Bus
Instruction reg
Program Counter
RAM
File
Registers
Direct Addr 5
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
W reg
Device Reset
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR VDD, VSS
Timer0
GPIO
8
8
GP3/MCLR/VPP
GP2/T0CKI/FOSC4
GP1/ICSPCLK
GP0/ICSPDAT
5-7
3
Stack 1
Stack 2 24 or 16
Internal RC
Clock
512 x12 or
bytes
Timer
256 x12
2004 Microchip Technology Inc. Preliminary DS41239A-page 11
PIC10F200/202/204/206
FIGURE 3-2: PIC10F20 4/206 BLOCK DIAGRAM
Flash
Program
Memory
9-10 Data Bus 8
12
Program
Bus
Instruction reg
Program Counter
RAM
File
Registers
Direct Addr 5
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
Status reg
MUX
ALU
W reg
Device Reset
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR VDD, VSS
Timer0
GPIO
8
8
GP3/MCLR/VPP
GP2/T0CKI/FOSC4
GP1/ICSPCLK
GP0/ICSPDAT
5-7
3
Stack 1
Stack 2 24 or 16
Internal RC
Clock
512 x12 or
bytes
Timer
256 x12
Comparator CIN+
CIN-
COUT
PIC10F200/202/204/206
DS41239A-page 12 Preliminary 2004 Microchip Technology Inc.
TABLE 3-2: PIC10F200/202/204/206 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/IC SPDA T/ CIN+ GP0 TTL CMOS Bidirecti onal I/O pin. C an be software programmed for i nternal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin.
CIN+ AN — Comparator input (PIC10F204/206 only).
GP1/ICSPCLK /CIN- GP1 TTL CMOS Bidirecti onal I/O pin. C an be software programmed for i nternal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK ST CMOS In-Circuit Serial Programming clock pin.
CIN- AN — Comparator input (PIC10F204/206 only).
GP2/T0CKI/COUT/
FOSC4 GP2 TTL CMOS Bidirectional I/O pin.
T0CKI ST — Clock input to TMR0.
COUT — CMOS Comparator output (PIC10F204/206 only).
FOSC4 — C MO S Oscillato r/4 outp ut.
GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR ST — Master Clear (Reset). When configured as MCLR, thi s pin is
an act ive-lo w Rese t to the de vice. Volt age on G P3/MCLR/VPP
must not exceed VDD during normal device operation or the
device w ill en ter Programming mod e. W e ak pul l-up always on
if configured as MCLR.
VPP HV — Programming voltage input.
VDD VDD P — Positive supply for logic and I/O pins.
VSS VSS P — Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog input
2004 Microchip Technology Inc. Preliminary DS41239A-page 13
PIC10F200/202/204/206
3.1 Clocking Scheme/Instruction
Cycle
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q 4. In tern al ly, the PC is in cre me nted ev ery Q1
and the instruction is fetched from program memory
and latched into the instruction register in Q4. It is
decode d and exec uted during the follow ing Q1 throug h
Q4. The clocks and instruction execution flow is shown
in Figure 3-3 and Example 3-1.
3.2 Instruction Flow/Pipelining
An instruction cycl e consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to cha nge (e.g., GOTO), then two cyc le s
are req uired to com plete the ins truction (Ex ampl e 3-1).
A fetch cy cle begins with the PC incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q 3 and Q4 c ycles. Data mem ory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC – 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
phase
clock
All instru ctions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 03H Fetch 1 Execute 1
2. MOVWF GPIO Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF GPIO, BIT1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC10F200/202/204/206
DS41239A-page 14 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 15
PIC10F200/202/204/206
4.0 MEMORY ORGANIZATION
The PIC10F200/202/204/206 memories are organized
into program memory and data memory. Data memory
banks are accessed using the File Select Register
(FSR).
4.1 Program Memory Orga nization for
the PIC10F200/204
The PIC10F200/204 devices have a 9-bit Program
Counter (PC) capable of addressing a 512 x 12
program memory space.
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F200/204 are physically implemented (see
Figure 4-1). Accessing a location above these
boundaries will cause a wraparound within the first
256 x 12 space (PIC10F200/204). The effective
Reset vector is at 0000h (see Figure 4-1). Location
00FFh (PIC10F200/204) contains the internal clock
oscillator calibration value. This value should never
be overwrit ten.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F200/204
CALL, RETLW PC<7:0>
S tack Level 1
S tack Level 2
User Memory
Space
9
0000h
01FFh
On-chip Program
Memory
Reset Vector(1)
Note 1: Address 0000h becomes the
effective Reset vector. Location
00FFh contains the MOVLW XX
internal oscillator calibration value.
256 Word 00FFh
0100h
PIC10F200/202/204/206
DS41239A-page 16 Preliminary 2004 Microchip Technology Inc.
4.2 Program Memory Orga nization fo r
the PIC10F202/206
The PIC10F202/206 devices have a 10-bit Program
Counter (PC) capable of addressing a 1024 x 12
program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC10F202/206 are physically implemented (see
Figure 4-2). Accessing a location above these
boundaries will cause a wraparound within the first
512 x 12 space (PIC10F202/206). The effective
Reset vector is at 0000h (see Figure 4-2). Location
01FFh (PIC10F202/206) contains the internal clock
oscillator calibration value. This value should never
be overwrit ten.
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F202/206
4.3 Data Memory Organization
Data memory is composed of registers or bytes of
RAM. T herefore, dat a me mo ry for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
The Specia l Func ti on R egi st ers in clude the TMR0 reg-
ister, the Program Counter (PCL), the Status register,
the I/O register (GPIO) and the File Select Register
(FSR). In addition, Special Functio n Registers are used
to control the I/O port configuration and prescaler
options.
The General Purpose Registers are used for data and
control information und er com ma nd of t he instructions .
For the PIC10F200/204, the register file is composed of
7 Special Function Registers and 16 General Purpose
Registers (see Figure 4-3 and Figure 4-4).
For the PIC10F202/206, the register file is composed of
8 Special Function Registers and 24 General Purpose
Registers (see Figure 4-4).
4.3. 1 GENERAL PURP OSE REGI STER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing:
INDF and FSR Registers”.
CALL, RETLW PC<8:0>
S tack Level 1
S tack Level 2
User Memory
Space
10
0000h
02FFh
Reset Vector(1)
Note 1: Address 0000h becomes the
effective Reset vector. Location
01FFh contains the MOVLW XX
internal oscillator calibration value.
512 Words 01FFh
0200h
On-chip Program
Memory
2004 Microchip Technology Inc. Preliminary DS41239A-page 17
PIC10F200/202/204/206
FIGURE 4-3: PIC10F20 0/2 04 REGISTER
FILE MAP FIGURE 4-4: PIC10F202/206 REGISTER
FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
10h
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
General
Purpose
Registers
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
2: PIC10F204 only. Unimplemented on the
PIC10F200 and reads as 00h.
3: Unimplemented, read as 00h.
08h
CMCON0(2)
0Fh
1Fh
Unimplemented(3)
File Address
00h
01h
02h
03h
04h
05h
06h
07h
18h
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
General
Purpose
Registers
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
2: PIC10F206 only. Unimplemented on the
PIC10F202 and reads as 00h.
08h
CMCON0(2)
PIC10F200/202/204/206
DS41239A-page 18 Preliminary 2004 Microchip Technology Inc.
4.3.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used b y the CPU and periph eral functio ns to cont rol the
operation of the device (Table 4- 1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset(2) Page #
00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 23
01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 29, 33
02h(1) PCL Low-order 8 bits of PC 1111 1111 22
03h STATUS GPWUF CWUF(5) —TOPD ZDCC00-1 1xxx(3) 19
04h FSR Indirect Data Memory Address Pointer 111x xxxx 23
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 21
06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx 25
07h(4) CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 34
N/A TRISGPIO — — — — I/O Control Register ---- 1111 37
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
Legend: — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an
explanation of how to access these bits .
2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change
Reset.
3: See Table 9-1 for other Reset specific values.
4: PIC10F204/206 only.
5: PIC10F204/206 only. On all other devices, this bit is reserved and should not be used.
2004 Microchip Technology Inc. Preliminary DS41239A-page 19
PIC10F200/202/204/206
4.4 Status Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For exam ple, CLRF STATUS, will clear the upper thre e
bits and set th e Z bit. Thi s leaves the Statu s regis ter as
000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructi on s be us ed to alt er the Status register.
These instructions do not af fect the Z, DC or C bit s from
the Status register. For other instructions which do
affect Status bits, see Section 10.0 “Instruction Set
Summary”.
REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF CWUF(1) —TO PD ZDCC
bit 7 bit 0
bit 7 GPWUF: GPIO Rese t bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6 CWUF: Comparator Wake-up on Change Flag Bit(1)
1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset conditions.
bit 5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bi t
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit ca rry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from th e 4th low-order bit of th e result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
Note 1: This bit is used on the PIC10F20 4/206. For code compa tibility do not use this bit on
the PIC10F200 /20 2.
Legend:
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC10F200/202/204/206
DS41239A-page 20 Preliminary 2004 Microchip Technology Inc.
4.5 Option Register
The Option register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W regis ter will be transfe rred to the Option register.
A Reset sets the OPTION<7:0> bits.
REGISTER 4-2: OPTION REGISTER
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU and GPWU).
Note: If the T0CS bit is set to ‘1’, it will override
the TRIS functi on on the T0CKI pin.
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 GPWU: En able Wake-up on Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6 GPPU: Enable Weak Pull -ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Presca ler assigned to the WDT
0 = Presca ler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
2004 Microchip Technology Inc. Preliminary DS41239A-page 21
PIC10F200/202/204/206
4.6 OSCCAL Register
The Oscill ator Calibration (OSCCAL) register is used to
calibrate the internal precision 4 MHz oscillator. It
cont ains seven bits for calibra tio n.
After you move in the calibration constant, do not
change the value. See Section 9.2.2 “Internal 4 MHz
Oscillator”.
REGISTER 4-3: OSCCAL REGISTER (ADDRESS: 05h)
Note: Erasing the device will also eras e the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0
CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4
bit 7 bit 0
bit 7-1 CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0 FOSC4: INTOSC/4 Output Enable bit(1)
1 = INTOSC/4 output onto GP2
0 = GP2/T0CKI/COUT applied to GP2
Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.
Legend:
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC10F200/202/204/206
DS41239A-page 22 Preliminary 2004 Microchip Technology Inc.
4.7 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
(PCL) is mapped to PC<7:0>.
For a CALL instruction, or any instruction where the
PCL is t he destina tion, bit s 7:0 of th e PC again are p ro-
vided by the instruction word. However, PC<8> does
not come from the instruction word, but is always
cleared (Figure 4-5).
Instr uctions where the PCL is th e destinatio n, or modif y
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
FIGURE 4-5: LOADING OF PC
BRANCH INSTRUCTIONS
4.7.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in program memory (i.e.,
the oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 0000h and
begin executing user code.
4.8 Stack
The PIC10 F200/2 04 devi ces ha ve a 2- deep, 8-b it wide
hardware PUSH/POP stack.
The PIC10 F202/2 06 devi ces ha ve a 2- deep, 9-b it wide
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of S tack 1
into Stack 2 and then PUSH the current PC value,
incre me nt ed by o ne , i nt o Stack Level 1. If more than two
sequential CALLs are ex ecuted, o nly the mo st recen t two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specif ied in the inst ruction. This i s particu larly useful f or
the implementation of data look-up tables within the
program me mory.
Note: Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
PC 87 0
PCL
Inst ruction Word
GOTO Ins truction
CALL or Modify PCL Instruction
PC 87 0
PCL
Inst ruction Word
Reset to ‘0’
Note 1: There are no Status bits to indicate stack
overflows or stack underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occ ur from th e exec ution of the CALL
and RETLW instructions.
2004 Microchip Technology Inc. Preliminary DS41239A-page 23
PIC10F200/202/204/206
4.9 Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose add re ss is co ntain ed in the FS R reg ist er (FSR
is a pointer). This is indi re ct addr es sing.
4.10 Indirect Addressing
• Register file 09 contains the value 10h
• Register file 0A contains the value 0Ah
• Load the value 09 into the FSR register
• A read of the INDF register will return the va lue
of 10h
• Increment the value of the FSR register by one
(FSR = 0A)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressi ng is shown in Example 4-1.
EXAMPLE 4-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The FSR is a 5-bit wi de register. It is used in conjunc-
tion with the INDF re gister to indirect ly address the data
memory area .
The FSR<4:0> bits are used to select data memory
addresse s 00h to 1Fh.
FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206)
Note: PIC10F200/202/204/206 – Do not use
banking. FSR <7:5> are unimplemented
and read as ‘1’s.
MOVLW 0x10 ;initializ e pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;cle a r I N D F
;register
INCF FSR,F ;inc pointer
BTFSC FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE : ;YES, continue
:
Note 1: F or register map detail, see Section 4.3 “Data Memory Organization”.
Location Select
Location Select
Indirect Addressing
Direct Addressing
Data
Memory(1) 0Fh
10h
Bank 0
0
4(FSR)
00h
1Fh
(opcode) 04
PIC10F200/202/204/206
DS41239A-page 24 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 25
PIC10F200/202/204/206
5.0 I/O PORT
As with any other register, the I/O register(s) can be
written and read und er program contro l. Howeve r , read
instruc tions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1 GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If GP3/MCLR is config-
ured as MCLR, weak pull-up is always on and wake-up
on change for this pin is not enabled.
5.2 TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS regi ster bit pu ts the corre-
sponding output driver in a High-impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input only and the GP2/T0CKI/
COUT/FO SC4 pin, w hich may be contro lled by variou s
registers. See Table 5-1.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
TABLE 5-1: ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
5.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except GP3 which is input
only, may be us ed for both input and output ope rations.
For input o perations, these ports are non-la tc hin g. An y
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain u nchan ged unt il t he outp ut latch is rewri tten. To
use a port pin as output, the corresponding direction
control bi t in TRIS must be clea red (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1: PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Note: A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driv en hig h,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Priority GP0 GP1 GP2 GP3
1 CIN+ CIN- FOSC4 I/MCLR
2 TRIS GPIO TRIS GPIO COUT —
3——T0CKI—
4——TRIS GPIO—
Data
Bus
Q
D
Q
CK
Q
D
Q
CK P
N
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin
W
Reg
Latch
Latch
Reset
Note 1: See Table 3-2 f or buffer type.
VSS
VDD
(1)
PIC10F200/202/204/206
DS41239A-page 26 Preliminary 2004 Microchip Technology Inc.
TABLE 5-2: SUMMARY OF PORT REGISTERS
5.4 I/O Programming Considerations
5.4.1 BID IREC TION AL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
exampl e, read the entire port into the CPU, execute the
bit operation and rewrite the result. Caution must be
used when these instructions are applied to a port
where one or more pin s are us ed as in put/ outp uts. For
example, a BSF operation on bit 2 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 2 to
be set and the GPIO value to be written to the output
latches . If another b it of GPIO i s used as a bid irectiona l
I/O pin (say bit 0) and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the C PU a nd rewritt en to the d ata latch of thi s
parti cular pin, ov erwriting the previous c ontent. As lon g
as the pin stays in the Input mode, no problem occurs.
Howeve r, if b it 0 i s swit ched into Ou tpu t mo de la ter o n,
the content of the data latch may now be unknown.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The res ulting hig h output curre nts may dam age
the chip.
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.4.2 SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instr uction cycl e, wher eas f or re ading , the d ata mu st be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
caus es that fi le to be read into the CPU. Other wis e, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
access ing this I/O port.
Addr e s s N a m e B i t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi t 0 Value on
Power-On
Reset
Value on
All Other Resets
N/A TRISGPIO — — — — I/O Control Register ---- 1111 ---- 1111
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
03h STATUS GPWUF CWUF —TO PD ZDC C00-1 1xxx qq-q quuu(1, 2)
06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu
Legend: Shaded cells are not used by Port registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
2: If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.
;Initial GPIO Settings
;GPIO<3:2> Inputs
;GPIO<1:0> Outputs
;
; GPIO latch GPIO pins
; ---------- ----------
BCF GPIO, 1 ;---- pp01 ---- pp11
BCF GPIO, 0 ;---- pp10 ---- pp11
MOVLW 007h;
TRIS GPIO ;---- pp10 ---- pp11
;
Note 1: The user may have expected the pin values
to be ---- pp00. The 2nd BCF caused GP1
to be latched as the pin value (High).
2004 Microchip Technology Inc. Preliminary DS41239A-page 27
PIC10F200/202/204/206
FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206)
PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
GP<2:0>
MOVWF GPIO NOP
Port pin
sampled here
NOPMOVF GPIO, W
Instruction
Executed MOVWF GPIO
(Write to GPIO) NOPMOVF GPIO,W
This example shows a write to GPIO followed
by a read from GPIO.
Data s e tu p ti me = (0 .2 5 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
(Read GPIO)
Port pi n
written here
PIC10F200/202/204/206
DS41239A-page 28 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 29
PIC10F200/202/204/206
6.0 TIMER0 MODULE AND TMR0
REGISTER (PIC10F200/202)
The Timer0 module has the following features:
• 8-bit time r/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(Option<5>). In Timer mode, the Timer0 module will
increm ent ev ery ins tru cti on cycle (witho ut p r es ca ler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(Option<5>). In this mode, Timer0 will in crement either
on every rising or falling edge of pin T0CKI. The T0SE
bit (Option<4>) determines the source edge. Clearing
the T0SE bit select s the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.1 “Using Timer0 with an External Clock
(PIC10F200/202)”.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (Option<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. Whe n the prescaler is assi gned to
the Timer0 module, prescale values of 1:2, 1:4, 1:256
are selectable. Section 6.2 “Prescaler” details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the Option register .
2: The prescaler is shared with the Wa tchdo g Timer (Figure 6-5).
0
1
1
0
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks TMR0 reg
PSOUT
(2 TCY delay)
PSOUT
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)
3
Sync
T0SE
GP2/T0CKI
Pin
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
PIC10F200/202/204/206
DS41239A-page 30 Preliminary 2004 Microchip Technology Inc.
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
6.1 Using Timer0 with an External
Clock (PIC10F200/202)
When an external cl ock input i s used for T ime r0, it must
meet ce r tain r equ ir e me nts. The ex t er na l cl oc k r equ ir e-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also , there is a d ela y in the actua l incr ementin g of
Timer0 after synchronization.
6.1.1 EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the pre sc ale r outp ut. The synch r on iza tio n
of T0CKI with the internal phase clocks is accom-
plishe d by sampli ng the prescale r output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 TOSC (and a small RC delay of 2 Tt0H) and low
for at least 2 TOSC (and a small RC delay of 2 Tt0H).
Refer to the electrical specification of the desired
device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
pres caler, so that th e presc aler out put is sy mmetric al.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, i t is nec essa ry for T0CKI to h ave a perio d of
at least 4 TOSC (and a small RC delay of 4 Tt0H) divided
by the presc aler value . The only requi rement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
param ete rs 40, 41 and 42 in the electrical spec if ication
of the desired device.
Addres s Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n
Power-On
Reset
Value on
All Other
Resets
01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A TRISGPIO(1) — — ——I/O Control Register ---- 1111 ---- 1111
Legend: Sh aded cells not us ed by Timer0. — = unimplemented, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 NT0 NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
2004 Microchip Technology Inc. Preliminary DS41239A-page 31
PIC10F200/202/204/206
6.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOC K
6.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 9.6 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
The PSA and PS<2:0> bits (Option<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) wi ll clear the presc aler . Wh en assigne d
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writ able. On a Re set, the prescal er contains all ‘0’s.
6.2.1 SWITCHI NG PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram ex ecution). To avoid an uninten ded device Rese t,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0 → WDT)
Increment Timer0 (Q4)
External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
External Clock/ Pres cale r
Output After Sampling (3)
Prescaler Output (2)
(1)
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
Note: The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa. CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION ;are required only if
;desired
CLRWDT ;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION ;desired WDT rate
PIC10F200/202/204/206
DS41239A-page 32 Preliminary 2004 Microchip Technology Inc.
To change the prescaler from the WDT to the Timer0
module , use the se quence sh own in Exam ple 6-2. This
sequen ce mu st b e used ev en if th e WDT is dis abled . A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT→TIMER0)
FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLRWDT ;Clear WDT and
;prescaler
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
OPTION
TCY (= FOSC/4)
Sync
2
Cycles TMR0 reg
8-bit Prescaler
8-to-1MUX
M
MUX
Watchdog
Timer
PSA(1)
01
0
1
WDT
Time-Out
PS<2:0>(1)
8
PSA(1)
WDT Enable bit
0
10
1
Data Bus
8
PSA(1)
T0CS(1)
M
U
XM
U
X
U
X
T0SE(1)
GP2/T0CKI(2)
Pin
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register.
2: T0CKI is shared with pin GP2 on the PIC10F200/202/204/206.
2004 Microchip Technology Inc. Preliminary DS41239A-page 33
PIC10F200/202/204/206
7.0 TIMER0 MODULE AND TMR0
REGISTER (PIC10F204/206)
The Timer0 module has the following features:
• 8-bit time r/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
- External clock from either the T0CKI pin or
from the output of the com p a rato r
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(Option<5>). In Timer mode, the Timer0 module will
increm ent ev ery ins tru cti on cycle (witho ut p r es ca ler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
There are two types of Counter mode. Th e first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CS bit (Option<5>), setting
the CMPT0CS bit (CMCON0<4>) and setting the
COUTEN bit (CMCON0<6>). In this mode, Timer0 will
increment either on every rising or falling edge of pin
T0CKI. The T0SE bit (Option<4>) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discus sed in det ail in Section 7.1 “Using Timer0 with
an External Clock (PIC10F204/206)”.
The seco nd Counte r mo de use s the out put of the com-
parator to increment Timer0. It can be entered in two
different ways. The first way is selected by setting the
T0CS bit (Option<5>) and clearing the CMPT0CS bit
(CMCON<4>); (COUTEN ([CMCON<6>]) does not
affect this mode of operation. This enables an internal
connection between the comparator and the Timer0.
The second way is selected by setting the T0CS bit
(Option<5>), setting the CMPT0CS bit (CMCON0<4>)
and clearing the COUTEN bit (CMCON0<6>). This
allow s the output of t he comparato r onto the T0 CKI pin,
while keeping the T0CKI input active. Therefore, any
comparator change on the COUT pin is fed back into
the T0CKI i nput. The T0SE bit (Op tion<4> ) determi nes
the source edge. Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input as
discussed in Section 7.1 “Using Timer0 with an
External Clock (PIC10 F204/206)”
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (Option<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. Whe n the prescaler is assi gned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7 .2 “Prescaler” detai ls
the operation of the pres caler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM (PIC10F204/206 )
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the Option register.
2: The prescaler is shared with the Wa tchdo g Timer (Figure 7-5).
3: Bit CMPT0CS is located in the CMCON0 register, C MCON0<4>.
0
1
1
0
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks TMR 0 re g
PSOUT
(2 TCY delay)
PSOUT
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)
3
Sync
T0SE(1)
T0CKI
Pin
CMPT0CS(3)
1
0
Internal
Comparator
Output
PIC10F200/202/204/206
DS41239A-page 34 Preliminary 2004 Microchip Technology Inc.
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
7.1 Using Timer0 with an External
Clock (PIC10F204/206)
When an external cl ock input i s used for T ime r0, it must
meet ce r tain r equ ir e me nts. The ex t er na l cl oc k r equ ir e-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also , there is a d ela y in the actua l incr ementin g of
Timer0 after synchronization.
7.1.1 EX TERN AL CLO CK
SYNCHRONIZATION
When no pr escal er is used, t he ex tern al clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figur e 7-4). Therefore, it is necessary for T0CKI or the
comp a rator output to be h igh for a t l eas t 2 TOSC (and a
small RC delay of 2 Tt0H) and low for at least 2 TOSC
(and a sma ll RC delay of 2 Tt0H ). Refer to the electri cal
specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type
pres caler, so that th e presc aler out put is sy mmetric al.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI or the comparator
outp ut to ha ve a p er i od of at le a st 4 TOSC (and a small
RC delay of 4 Tt0H) divided by the prescaler value. The
only requirement on T0CKI or the comparator output
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
param ete rs 40, 41 and 42 in the electrical spec if ication
of the desired device.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
All Other
Resets
01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu
07h CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuu u
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
N/A TRISGPIO(1) — — — — I/O Control Register ---- 1111 - -- - 111 1
Legend: Shaded cells not used by Timer0. — = unimplemented, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC+5
PC
(Program
Counter)
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 NT0 NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
2004 Microchip Technology Inc. Preliminary DS41239A-page 35
PIC10F200/202/204/206
7.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 7-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOC K
7.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Figure 9-6). For
simplicity, this counter is being referred to as
“presca ler” through out thi s dat a sheet.
The PSA and PS<2:0> bits (Option<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) wi ll clear the presc aler . Wh en assigne d
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writ able. On a Re set, the prescal er contains all ‘0’s.
7.2.1 SWITCHI NG PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram ex ecution). To avoid an uninten ded device Rese t,
the following instruction sequence (Example 7-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0 → WDT)
Increment Timer0 (Q4)
External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
External Clock/ Pres cale r
Output After Sampling (3)
Prescaler Output (2)
(1)
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
Note: The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa. CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION ;are required only if
;desired
CLRWDT ;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION ;desired WDT rate
PIC10F200/202/204/206
DS41239A-page 36 Preliminary 2004 Microchip Technology Inc.
To change the prescaler from the WDT to the Timer0
module , use the se quenc e sho wn i n Exampl e 7.2. Thi s
sequen ce mu st b e used ev en if th e WDT is dis abled . A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT→TIMER0)
FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLRWDT ;Clear WDT and
;prescaler
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
OPTION
TCY (= FOSC/4)
Sync
2
Cycles TMR0 reg
8-bit Prescaler
8-to-1MUX
M
MUX
Watchdog
Timer
PSA(1)
01
0
1
WDT
Time-out
PS<2:0>(1)
8
PSA(1)
WDT Enable bit
0
10
1
Data Bus
8
PSA(1)
T0CS(1)
M
U
XM
U
X
U
X
T0SE(1)
GP2/T0CKI(2)
Pin
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register.
2: T0CKI is shared with pin GP2.
3: Bit CMPT0CS is located in the CMCON0 register.
1
0
Comparator
Output
CMPT0CS(3)
2004 Microchip Technology Inc. Preliminary DS41239A-page 37
PIC10F200/202/204/206
8.0 COMPARATOR MODULE
The Comparator module contains one analog
comparator. The inputs to the comparator are
multiplexed with GP0 and GP1 pins. The output of the
comparator can be placed on GP2.
The CMC ON0 regi ster, show n in Reg ister 8-1, con trols
the comparator operation. A block diagram of the
comparator is shown in Figure 8-1.
REGISTER 8-1: CMCON0 REGISTER (ADDRESS: 07h)
R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU
bit 7 bit 0
bit 7 CMPOUT: Comparator Output bit
1 = VIN+ > VIN-
0 = VIN+ < VIN-
bit 6 COUTEN: Comparator Output Enable bit(1 , 2)
1 = Output of comparator is NOT placed on the COUT pin
0 = Output of comparator is placed in the COUT pin
bit 5 POL: Comparator Output Polarity bit(2)
1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4 CMPT0CS: Comparator TM R0 Clock Source bit(2)
1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3 CMPON: Compar ator Enab le bit
1 = Comparator is on
0 = Comparator is off
bit 2 CNREF: Comparator Negative Reference Select bit(2)
1 = CIN- pin(3)
0 = Internal voltage reference
bit 1 CPREF: Comparator Positive Reference Select bit(2)
1 = CIN+ pin(3)
0 = CIN- pin(3)
bit 0 CWU: Comparator Wake-up on Ch ange Enable bit(2)
1 = Wake-up on comparator change is disabled
0 = Wake-up on comparator change is enabled.
Note 1: Overrides T0CS bit for TRIS control of GP2.
2: When the comparator is turned on, these control bits assert themselves. When the
comparator is off, these bits have no effect on the device operation and the other
control registers have precedence.
3: PIC10F204/206 only.
Legend:
R = Readable bit W = Writable bit U = Unimpl emented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC10F200/202/204/206
DS41239A-page 38 Preliminary 2004 Microchip Technology Inc.
8.1 Comparator Configuration
The on-board comparator inputs, (GP0/CIN+, GP1/
CIN-), as well as the comparator output (GP2/COUT)
are steerable. The CMCON0, OPTION, and TRIS
registers are used to st eer t hes e p ins (see Figure 8-1).
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Table 12-1.
FIGURE 8-1: BLOCK DIAGRAM OF THE COMPARATOR
TABLE 8-1: TMR0 CLOCK SOURCE
FUNCTION MUXING
Note: The comparator can have an inverted
output (see Figure 8-1).
+
-
C+
C-
OSCCAL
Band Gap Buffer
(0.6V)
CMPON POL
T0CKSEL
T0CKI/GP2/COUT
COUTEN
COUT(Register)
T0CKI Pin
T0CKI
QD
S
CWUF READ
CMCON
CWU
CPREF
CNREF
T0CS CMPT0CS COUTEN Source
0x xInternal In stru cti on
Cycle
10 0CMPOUT
10 1CMPOUT
11 0CMPOUT
11 1T0CKI
2004 Microchip Technology Inc. Preliminary DS41239A-page 39
PIC10F200/202/204/206
8.2 Comparator Operation
A single comparator is shown in Figure 8-2 along with
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN-, the output of the comp arator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 8-2 represent
the uncertainty due to input offsets and response time.
See Table 12-1 for Common Mode Voltage.
FIGURE 8-2: SINGLE COMPARATOR
8.3 Comparator Reference
An internal reference signal may be used depending on
the com parato r operat ing mode. T he analo g signal that
is present at VIN- is compared to the signal at VIN+ and
the digital output of the comparator is adjusted
accordingly (Figure 8-2). Please see Table 12-1 for
internal reference specifications.
8.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the com-
parator inputs are changed, a delay must be used to
allow the comparator to settle to its new state. Please
see Table 12-1 for comparator response time
specifications.
8.5 Comparator Output
The comparator output is read through CMCON0
register. This bit is read-only. The comparator output
may also be use d inte rnal ly, see Figure 8-1.
8.6 Comparator Wake-up Flag
The com pa rator w ake-up flag is s et w henever a ll of the
following conditions are met:
•CWU = 0 (CMCON0 <0>)
• CMCON0 has be en re ad to latc h the last k nown
state of th e CMPOUT bit (MOVF CMCON0, W)
• Device is in Sleep
• The output of the comparator has changed state
The wake-up flag may be cleared in software or by
anot her device Reset.
8.7 Comparator Operation During
Sleep
When the c omparato r is active a nd the device is placed
in Sleep mode, the comparator remains active. While
the comparator is powered-up, higher Sleep currents
than sho wn in the powe r-down current s pecification w ill
occur. To minimize power consumption while in Sleep
mode, turn off the comparator before entering Sleep.
8.8 Effects of a Reset
A POR Reset forces the CMCON0 register to its Reset
state. This forces the Comparator module to be in the
comparator Reset mode. This ensures that all potential
inputs are analog inputs. Device current is minimized
when analog inputs are present at Reset time. The
comparator will be powered-down during the Reset
interval.
8.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The an alo g i npu t the r efo re, m us t b e b etween
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
–
+
Vin+
Vin- Result
Result
VIN-
VIN+
Note: Analo g leve ls on an y pi n that is defin ed as
a digit al input may cause the input buffer to
consume more current than is specified.
PIC10F200/202/204/206
DS41239A-page 40 Preliminary 2004 Microchip Technology Inc.
FIGURE 8-3: ANALOG INPUT MODE
TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Addr e s s Na me Bit 7 Bit 6 B it 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on
POR
Value o n
All Other
Resets
03h STATUS GPWUF CWUF —TOPD ZDCC00-1 1xxx qq0q quuu
07h CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu
N/A TRISGPIO — — — — I/O Control Register ---- 1111 ---- 1111
Legend: x = Unknown, u = Unchanged, — = Unimplemented, read as ‘0’, q = Depends on condition.
VA
RS < 10 K
AIN CPIN
5pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current At The Pin
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
2004 Microchip Technology Inc. Preliminary DS41239A-page 41
PIC10F200/202/204/206
9.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors a re special circuits that deal with the nee ds of real-
time applications. The PIC10F200/202/204/206
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Watchdog Timer (WDT)
- Wake-up from Sleep on pin change
- Wake-up from Sleep on comparator change
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
•Clock Out
The PIC10F200/202/204/206 devices have a Watch-
dog Timer, which can be shut off only through configu-
ration bit WDTE. It runs off of its own RC oscillator for
added re liabi lity. When using IN TRC, there is an 18 ms
delay only on VDD power-up. With this timer on-chip,
most applications need no external Reset circuitry.
The Sleep mo de is des igned to of fer a ve ry low current
Power-down mode. The user can wake-up from Sleep
through a change on input pins, wake-up from
comparator change, or through a Watchdog Timer
time-out.
9.1 Configuration Bits
The PIC10F200/202/204/206 Configuration Words
consist of 12 bits. Configuration bits can be
programmed to select various device configurations.
One bit is the Watchdog Timer enable bit, one bit is the
MCLR enable bit and one bit is for code protection (se e
Register 9-1).
REGISTER 9-1: CONFIGURATION WORD FOR PIC10F200/202/20 4/2 06(1, 2)
— — — — — — — MCLRE CP WDTE — —
bit 11 bit 0
bit 11-5 Unimplemented: Read as ‘0’
bit 4 MCLRE: GP3/MCLR Pin Function Select bit
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3 CP: Code Protecti on bit
1 = Code protection off
0 = Code protection on
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enab led
0 = WDT di sabled
bit 1-0 Reserved: Read as ‘0’
Note 1: Refer to the “PIC10F200/202/204/206 Memory Programming Specifications” (DS41228) to
determine how to access the Configuration Word. The Configuration Word is not user
addressable during devi ce operation.
2: INTRC is the only oscillator mode offered on the PIC10F200/202/204/206.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown
PIC10F200/202/204/206
DS41239A-page 42 Preliminary 2004 Microchip Technology Inc.
9.2 Oscillator Configurations
9.2.1 OSCILLATOR TYPES
The PIC10F200/202/204/206 devices are offered with
Internal Os cillator mode only.
• INTOSC: Internal 4 MHz Oscillator
9.2.2 INTERNAL 4 MHz OSCILLATOR
The internal oscillator provides a 4 MHz (nominal) system
clock (see Section 12.0 “Electrical Characteristics” for
information on variation over voltage and temperature).
In addi tion, a ca librat ion in struct ion is progra mmed into
the last ad dress of me mory, which cont ains the ca libra-
tion value for the internal oscillator. This location is
always uncode protected, regardless of the code-pro-
tect settings. This value is programmed as a MOVLW xx
instruction where xx is the calibration value and is
placed at th e Re set v ector. This will load the W regis ter
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user th en h as th e option of writing the v alu e to th e
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” th e internal oscill ator to re move pro cess variatio n
from the oscillator frequency.
9.3 Reset
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR
Reset during Sleep
• WDT time-out Reset during normal operation
• WDT time-out Reset during Sleep
• Wake-up from Sleep on pin change
• Wake-up from Sleep on comparator change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other R eset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumpt ion of n orm al ope rati on. The excepti ons to thi s
are TO, P D, GPWUF and CWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 9-1 for a full description of Reset
state s of all regi sters.
TABLE 9-1: RESET CONDITIONS FOR REGISTERS – PIC10F200/202/204/206
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
Register Address Power-on Reset MCLR Reset, WDT Time-out,
Wake-up On Pin Change, Wake on
Comparator Change
W—qqqq qqqu(1) qqqq qqqu(1)
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PCL 02h 1111 1111 1111 1111
STATUS 03h 00-1 1xxx q00q quuu(2)
STATUS(3) 03h 00-1 1xxx qq0q quuu(2)
FSR 04h 111x xxxx 111u uuuu
OSCCAL 05h 1111 1110 uuuu uuuu
GPIO 06h ---- xxxx ---- uuuu
CMCON(3) 07h 1111 1111 uuuu uuuu
OPTION — 1111 1111 1111 1111
TRISGPIO — ---- 1111 ---- 1111
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to M OVLW XX instruction at top of memory.
2: See Table 9-2 for Reset va lue for specific conditions.
3: PIC10F204/206 only.
2004 Microchip Technology Inc. Preliminary DS41239A-page 43
PIC10F200/202/204/206
TABLE 9-2: RESET CONDITION FOR SPECIAL REGISTERS
9.3.1 MCLR ENABLE
This configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR func tion is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 9-1.
FIGURE 9-1: MCL R SE L ECT
9.4 Power-on Reset (POR)
The PIC10F200/202/204/206 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD, or program the pin as GP3. An internal
weak pull-up resistor is i mplemented us ing a transistor
(refer to Table 12-3 for the pull-up resistor ranges).
This will eliminate external RC components usually
needed to create a Power-on Reset. A maximum rise
time for VDD is specified. See Section 12.0 “Electrical
Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, fre quency, tem pera ture ,...) m ust be met to en su re
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 9-2.
The Power-on Reset circuit and the Device Reset
Timer (see Section 9.5 “Device Reset Timer (DRT)” )
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, whi ch is typic ally 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low i s show n
in Figu re 9-3. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 9-4, the on-chip Power-on Reset feature is
being use d (MCLR a nd V DD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 9-5 depicts a
probl em sit uat ion wh ere VDD rises too slowly. The time
betwee n when the DR T sen se s that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this sit uat ion, when th e st art-u p timer time s
out, VDD has not reached the VDD (min) value and the
chip ma y not fun ction corre ctly. For such situ ations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 9-4).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations”, (DS00522) and
AN607 “Power-up Trouble Shooting”, (DS00607).
STATUS Addr: 03h PCL Addr: 02h
Power-on Reset 00-1 1xxx 1111 1111
MCLR Reset during normal operation 000u uuuu 1111 1111
MCLR Reset during Sleep 0001 0uuu 1111 1111
WDT Reset during Sleep 0000 0uuu 1111 1111
WDT Reset normal operation 0000 uuuu 1111 1111
Wake-up from Sleep on pin change 1001 0uuu 1111 1111
Wake-up from Sleep on comparator change 0101 0uuu 1111 1111
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’.
GP3/MCLR/VPP
MCLRE Int ernal MCLR
GPWU
Note: When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
PIC10F200/202/204/206
DS41239A-page 44 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 9-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 9-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
SQ
RQ
VDD
GP3/MCLR/VPP
Power-up
Detect POR (Pow e r- on Reset)
WDT Reset CHIP Reset
MCLRE
Wake-up on pin change Reset
Start-up Timer
(10 µs or 18 ms)
WDT Time-out
Pin Change
Sleep
MCLR Reset
VDD
MCLR
Internal POR
DRT T ime-out
Internal Reset
TDRT
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
2004 Microchip Technology Inc. Preliminary DS41239A-page 45
PIC10F200/202/204/206
FIGURE 9-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
PIC10F200/202/204/206
DS41239A-page 46 Preliminary 2004 Microchip Technology Inc.
9.5 Device Reset Timer (DRT)
On the PIC10 F200/202/204 /206 devices , the DRT run s
any time the device is powered up.
The DRT operates on an internal oscillator. The
process or is kept in Reset as long as the DR T is active.
The DR T del ay allo w s VDD to rise above VDD min. and
for the oscillator to stabilize.
The on-chip DRT keeps the devices in a Reset
condition for approximately 18 ms after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not require d in
most ca ses. T his allows savi ngs in cost- sensi tiv e and/
or sp ace restric ted ap plic ations , as well as allo wing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 9.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 9-3: DRT (DEVICE RESET TIMER
PERIOD)
9.6 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
internal 4 MHz o sc ill ato r. This means th at the WDT wil l
run even if the main processor cl ock has be en stopped,
for example, by execution of a SLEEP instruction.
During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (Status<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 9.1
“Configuration Bits”). Refer to the PIC10F200/202/
204/206 Programming Spe cifications to determine how
to access the Configuration Word.
9.6.1 WDT PERIOD
The WDT has a nomin al time-out perio d of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the O ption regi ster . T hus, a tim e-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under w orst c ase co ndi tions (V DD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
9.6.2 WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
post scaler , if as signed to the WDT, and prevent s it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake- up Rese t.
Oscillator POR Reset Subsequent
Resets
INTO SC 18 ms (typic al) 10 µs (typical)
2004 Microchip Technology Inc. Preliminary DS41239A-page 47
PIC10F200/202/204/206
FIGURE 9-6: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
All Other
Resets
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Wa tchdog Timer, — = unimplemented, read as ‘0’, u = unchanged.
(Figure 6-5)
Postscaler
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the Option register .
WDT Time-out
Watchdog
Time
From Timer0 Clock Source
WDT Ena ble
Configuration
Bit
PSA
Postscaler
8-to-1 MUX PS<2:0>
(Figure 6-4)
To Timer0
0
1M
U
X
1
0
PSA
MUX
PIC10F200/202/204/206
DS41239A-page 48 Preliminary 2004 Microchip Technology Inc.
9.7 Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF, CWUF)
The TO, PD, GPWUF and CWUF bits in the Status
register can be tested to determine if a Reset condition
has been caused by a Power-up condition, a MCLR,
W atchdog T imer (WDT) Reset, wake-up on comp arator
change or wake-up on pin change.
TABLE 9-5: TO, PD, GPWUF, CWUF STATUS AFTER RESET
9.8 Reset on Brown-out
A Brown-out is a condition where device power (VDD)
dips below it s minimum value, but no t to zero, an d then
recovers. The device should be reset in the event of a
Brown-out.
To reset PIC10F200/202/204/206 devices when a
Brown-out occurs, external Brown-out protection
circuits may be built, as shown in Figure 9-7 and
Figure 9-8.
FIGURE 9-7: BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 9-8: BROWN-OUT
PROTECTION CIRCUIT 2
CWUF GPWUF TO PD Reset Caused By
0000WDT wake-up from Sleep
000uWDT time-out (not from Sleep)
0010MCLR wake-up from Sleep
0011Power-up
00uuMCLR not during Sleep
0110Wake-up from Sleep on pin change
1010Wake-up from Sleep on comparator change
Legend: u = unchanged, x = unknown, — = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: The TO, PD, GPWUF and CWUF bits maintain their status (u) until a Reset occu rs. A low-pulse on the
MCLR input does not change the TO, PD, GPWUF or CWUF status bits.
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be confirmed as MCLR.
33k
10k
40k(1)
VDD
MCLR(2) PIC10F20X
VDD
Q1
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
2: Pin must be confirmed as MCLR.
VDD • R1
R1 + R2 = 0.7V
R2 40k(1)
VDD
MCLR(2) PIC10F20X
R1
Q1
VDD
2004 Microchip Technology Inc. Preliminary DS41239A-page 49
PIC10F200/202/204/206
FIGURE 9-9: BROWN-OUT
PROTECTION CIRCUIT 3
9.9 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
9.9.1 SLEEP
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keep s runnin g, the T O bit (S t atus< 4>) is set, the PD bit
(S ta tus<3>) is cle ared and the os cillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high,
driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI inp ut sh ould be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
9.9.2 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of
the following events:
1. An external Reset input on GP 3/M C LR/VPP pi n,
when configur ed as MCLR.
2. A Watchdog Timer time-out Reset (if WDT was
enabled).
3. A change on input pin GP0, GP1 or GP3 when
wake-up on change is enabled.
4. A comparator outp ut change has occ urred when
wake-up on comparator change is enabled.
These events cause a device Reset. The TO, PD
GPWUF and CWUF bits can be used to determine the
cause of device Reset. The TO bit is cl eared if a WDT
time-out occurred (and caused wake-up). The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The GPWUF bit indicates a change in state
while in Sleep at pins G P0, G P1 or G P3 (s inc e the las t
file or bit operation on GP port). The CWUF bit
indicates a change in the state while in Sleep of the
comp ara tor outp ut.
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Note: This Brown-out Protection circuit em ploys
Microchip Technology’s MCP809 micro-
controller supervisor. There are 7 different
trip point selections to accommodate 5V to
3V systems.
MCLR
PIC10F20X
VDD
VDD
VSS
RST
MCP809
VDD
Bypass
Capacitor
Note: Caution: Right before entering Sleep,
read the input pi ns. When in Sleep, w ak e-
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs an d the pins are not rea d before re-
entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode .
Note: The WDT is cleared when the device
wakes from Sleep, regardle ss of the wake-
up source.
PIC10F200/202/204/206
DS41239A-page 50 Preliminary 2004 Microchip Technology Inc.
9.10 Program Verification/Code
Protection
If the co de protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (Reset
vector) can be read, regardless of the code protection
bit setting.
9.11 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
Use on ly the lower 4 bits o f the ID loc ations an d always
progra m the upper 8 bits as ‘0’s.
9.12 In-Circuit Serial Programming™
The PIC10F200/202/204/206 microcontrollers can be
serially programmed whi le in the end a pplication cir cuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. D epend ing on the c omman d, 16 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
PIC10F200/202/204/206 Programming Spe cificatio ns.
A typical In-Circuit Serial Programming connection is
shown in Figur e 9-10.
FIGURE 9-10: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC10F20X
VDD
VSS
MCLR/VPP
GP1
GP0
+5V
0V
VPP
CLK
Data I/O
VDD
2004 Microchip Technology Inc. Preliminary DS41239A-page 51
PIC10F200/202/204/206
10.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instructi on type and one or
more operands wh ich further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 10-1, while the various opcode
fields are sum m ariz ed in Table 10-1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W reg is ter. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
design ator which sel ects the numb er o f the bit affe cte d
by the operation, while ‘f’ represent s the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
inst ruction ex ecution ti me is 1 µs. If a c onditiona l test is
true or the program count er is changed as a result of an
instruction, the instruction execution time is 2 µs.
Figure 10-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
wher e ‘h’ signifies a hex adecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (a ccumulator)
bBit address wi thin an 8-b i t file regi ster
kLiteral field, constant data or label
xDon’t care locat i on (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
dDestination select;
d = 0 (sto re resu l t in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Progra m Counter
WDT Watchdog Timer counter
TO Time-out bit
PD Power-down bit
dest Destination, either the W register or the specified
register file location
[ ] Options
( ) Contents
→Assigned to
< > Register bit field
∈In the set of
italics User defined term (font is courier)
Byte-orie nted file register operations
11 6 5 4 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operati ons
11 8 7 5 4 0
OP C O DE b (BIT #) f ( F IL E #)
b = 3-bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11 9 8 0
OPCODE k (l i te ra l )
k = 9-bit immediate value
PIC10F200/202/204/206
DS41239A-page 52 Preliminary 2004 Microchip Technology Inc.
TABLE 10-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands Description Cycles 12-Bit Opcode Status
Affected Notes
MSb LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Incr eme nt f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C, DC, Z
None
Z
1, 2, 4
2, 4
4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
1, 2, 4
2, 4
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2, 4
2, 4
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
–
k
–
f
k
AND literal with W
Call Subro uti ne
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load Option register
Return, place Literal in W
Go into Standby mode
Load TRIS register
Exclusive OR literal to W
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
1
3
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.7 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value pres ent on the pi ns thems elves. For ex ample , if the dat a latch is ‘1’ for a pi n co nfig ure d as input an d
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
2004 Microchip Technology Inc. Preliminary DS41239A-page 53
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ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (W) + (f) → (dest)
Status Affected: C, DC, Z
Description: Add the contents of the W register
and regis ter ‘f’. If ‘d’ is ‘0’, the resul t
is stored in the W register. If ‘d’ is
‘1’, the resu lt is sto r ed bac k in
register ‘f ’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W).AND. (k) → (W)
Status Affected: Z
Description: The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (W) .AND. (f) → (dest)
Status Affected: Z
Description: The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register .
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Descr iption : If bit ‘b’ in reg ister ‘ f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, the n the nex t ins truc -
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a 2-cycle instruction.
PIC10F200/202/204/206
DS41239A-page 54 Preliminary 2004 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 ≤ f ≤ 31
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription : If bit ‘b’ i n regis ter ‘f’ is ‘ 1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the nex t ins tru c-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instea d,
making this a 2-cycle instruction.
CALL Subroutine Call
Syntax: [ label ] CALL k
Operands: 0 ≤ k ≤ 255
Operation: (PC) + 1→ Top-of-S tack;
k → PC<7:0>;
(S tatus<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected: None
Description: Subroutine call. First, return
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
Status<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 31
Operation: 00h → (f);
1 → Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] C LRW
Operands: None
Operation: 00h → (W);
1 → Z
Status Affected: Z
Description: The W register is cleared. Zero bi t
(Z) is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
Status Affected: TO, PD
Description: The CLRWDT instruction resets the
WDT. It also reset s the prescal er , if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Description: The co ntents of re gister ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register . If
‘d’ is ‘1’, th e result is stored back in
register ‘f’.
2004 Microchip Technology Inc. Preliminary DS41239A-page 55
PIC10F200/202/204/206
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operati on: (f) – 1 → (dest)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the r esult is
stored back in register ‘f’.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operati on: (f) – 1 → d; skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decr emente d. If ‘d’ is ‘0’, the res ult
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 ≤ k ≤ 511
Operation: k → PC<8:0>;
Status<6:5> → PC<10:9>
Status Affected: None
Description: GOTO is an unconditi onal bran ch .
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
Status<6:5>. GOTO is a two-cycle
instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operati on: (f) + 1 → (dest)
Status Affected: Z
Description: The co ntents of re gister ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operati on: (f) + 1 → (dest), skip if result = 0
Status Affected: None
Description: The co ntents of re gister ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead maki ng it a
two-cycle instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. (k) → (W)
Status Affected: Z
Descripti on: The con ten ts of the W register are
OR’ed with the eight bit literal ‘k’.
The result is placed in the W
register.
PIC10F200/202/204/206
DS41239A-page 56 Preliminary 2004 Microchip Technology Inc.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (W).OR. (f) → (dest)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W re gister. If ‘d’ is ‘1’,
the result is placed back in registe r
‘f’.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
moved to destina tion ‘d’. If ‘d ’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the des tin ati on is fil e
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since status
flag Z is affected.
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight-bit literal ‘k’ is loaded
into the W register . The don’t cares
will assembled as ‘0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 31
Operation: (W) → (f)
Status Affected: None
Description: Move data from the W register to
register ‘f’.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operati on: No operation
Status Affected: None
Descr ipti on : No operation.
OPTION Load Option Register
Syntax: [ label ] Option
Operands: None
Operation: (W) → Option
Status Affected: None
Description: The content of the W register is
loaded into the Option register.
2004 Microchip Technology Inc. Preliminary DS41239A-page 57
PIC10F200/202/204/206
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return ad dress). This
is a two-cycle instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag . If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is stored bac k in reg-
ister ‘f’.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag . If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Cregister ‘f’
Cregister ‘f’
SLEEP Enter SLEEP Mode
Syntax: [ label ]SLEEP
Operands: None
Operation: 00h → WDT;
0 → WDT prescaler;
1 → TO;
0 → PD
Status Affected: TO, PD, RBWUF
Description: Time-out S tatus bit (T O) is set. T he
Power-dow n Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The proce sso r is pu t in to Sleep
mode wit h the osci llato r st op ped .
See Section 9.9 “Power-do wn
Mode (Sleep)” for more detail s .
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operati on: (f) – (W) → (dest)
Status Affected: C, DC, Z
Descr iption : Subtract (2’ s co mplem ent met hod)
the W reg ister fr om regist er ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in regi ste r ‘f’.
PIC10F200/202/204/206
DS41239A-page 58 Preliminary 2004 Microchip Technology Inc.
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operand s: f = 6
Operation: (W) → TRIS register f
Status Affected: None
Description: TRIS register ‘f’ (f = 6 or 7) is
loaded wi th the co nten t s of the W
register
XORLW Exclusive OR literal with W
Syntax: [ label ]XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed w ith the eight- bit lite ral ‘k ’.
The result is placed in the W
register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: (W) .XOR. (f) → (dest)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2004 Microchip Technology Inc. Preliminary DS41239A-page 59
PIC10F200/202/204/206
11.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Sim ulator
- MPLAB dsPIC30 Software Simulator
•Emulators
- MPLAB ICE 2000 In -Circuit Emulator
- MPLAB ICE 4000 In -Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Progra mm ers
-PRO MATE
® II Universal Device Progr a mm er
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM De monstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM L IN Demo nstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
-K
EELOQ®
- P ICDEM MSC
-microID
®
-CAN
- PowerSmart®
-Analog
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to deb ugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Exten si ve on-l in e help
The MPLAB IDE allows you to :
• Edit your sour ce files (either assemb ly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug us ing :
- source files (as sembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve whe n upgrading to tools with increasin g flexibi lity
and power.
11.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, M AP files to detail memory u sage and symbol re f-
erence, a bsolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User de fined m acros to strea mline asse mbly c ode
• Condit ion al as sem bl y for mult i-p urpo se sourc e
files
• Directi ves that allow complete control over the
assembly p rocess
PIC10F200/202/204/206
DS41239A-page 60 Preliminary 2004 Microchip Technology Inc.
11.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
11.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement , deletion and extr action
11.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-
ties and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated an d c on form to the ANSI C li brary standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keepin g and math func tions (trigonome tric, expone ntial
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
11.6 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or lin ked with other relocatable object files and
arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatib ility
11.7 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simulat or allows code deve l-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or use r de fined key p ress, to any pin. The exec u-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
11.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
develop ment in a PC hosted en vironment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler . The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
2004 Microchip Technology Inc. Preliminary DS41239A-page 61
PIC10F200/202/204/206
11.9 MPLAB ICE 2000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which all ows ed iting, b uildin g, do wnlo ading and sourc e
debuggi ng from a singl e envi ronm en t.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easi ly reconfi gured for emula tion of d iffer-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.10 MPLAB ICE 4000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a co mplete micro controller de sign tool se t for high-
end PICm icro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debuggi ng from a singl e envi ronm en t.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol , offe rs cost ef fective i n-circuit Flash debug ging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-tim e. MPLAB ICD 2 also serv es as a devel opme nt
programmer for selected PICmicro devices.
11.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
11.13 MPLAB PM3 Device Program mer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and V DDMAX for maximum reliability . It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket as sembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode, the MPLAB PM3 device programmer can
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. MPLAB PM3 connects to the host PC via an
RS-232 or USB cable. MPLAB PM3 has high-speed
communications and optimized algorithms for quick
programming of large memory devices and incorpo-
rates an SD/MMC card for file storage and secure data
applications.
PIC10F200/202/204/206
DS41239A-page 62 Preliminary 2004 Microchip Technology Inc.
11.14 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
11.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demo nstrat ion boa rd demo nstrate s the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an
be pro gramme d with a PRO MATE II devic e progra m-
mer or a PICSTART Plus development programmer.
The PICDE M 1 demonstrati on board can be conne cted
to the MPLAB ICE in-circuit emulator for testing. A
proto type area extends the ci rcuitry for a dditio nal appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
11.16 PIC DEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by J eremy Ben tham
11.17 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary ha rdware and s oftware is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB I CD 2 and MPLAB ICE in-circuit emul ators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display , a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
11.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and softwa re is included to run
the demonstration programs.
11.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on th e demo board are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display , PCB footprints for H-
Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing are a. Inc lud ed with the kit is a PIC16F627A and
a PIC18F1 320. Tutorial fir mwar e is inc luded along wi th
the User’s Guide.
2004 Microchip Technology Inc. Preliminary DS41239A-page 63
PIC10F200/202/204/206
11.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
gramme d sample i s included. The PR O MA TE I I device
programmer, or the PICSTART Plus development pro-
gramme r , can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous proto typ e area is av ailab le for user hardw are
expansion.
11.21 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
11.22 PICDEM LIN PIC16C43X
Demonstration Board
The pow erfu l LI N hard w are a nd s of tw are kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN b us communication.
11.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for p rogramming, evaluation a nd development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates un der a simple Windows GUI.
The PICkit 1 Starter Kit includes the User’s Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB® IDE
(Integrated Development Environment) software,
software and hardware “Tips 'n Tricks for 8-pin Flash
PIC® Microcontrollers” Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
11.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM U SB Demo ns trati on Board sho w s o f f th e
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
11.25 Evaluati on and
Programming Tools
In additio n to the PICDEM seri es of circuits, Microchip
has a line of evaluation kits and demonstration software
for the se products.
•K
EELOQ evaluation and prog ram mi ng too ls for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerS mart battery charging evaluation/
calibration kits
•IrDA
® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory ev al uat ion an d
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
PIC10F200/202/204/206
DS41239A-page 64 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 65
PIC10F200/202/204/206
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40°C to +125°C
Storage temperature ............................................................................................................................-65°C to +150°C
Volt a ge on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Volt a ge on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power diss ipation(1) ..................................................................................................................................800 mW
Max. current out of VSS pin..................... ...... ..... ............................. ..... ...... ............................ ..... .........................80 mA
Max. current into VDD pin.....................................................................................................................................80 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp cur rent, IOK (VO < 0 or VO > VDD)...........................................................................................................±20 mA
Max. output current sunk by any I/O pin ..............................................................................................................25 mA
Max. output current sourced by any I/O pin.........................................................................................................25 mA
Max. output current sourced by I/O port ..............................................................................................................75 mA
Max. output current sunk by I/O port ...................................................................................................................75 mA
Note 1: Power dis sipation is ca lculated as fol lows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – V OH) x IOH} + ∑(VOL x IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
thos e in di c at e d in t he o pe rat i o n l is tin g s o f t his s pecifi ca t io n is not i mp li e d. Ex po su r e to m ax im um r at i ng c ond it i on s
for extended periods may affect device reliability.
PIC10F200/202/204/206
DS41239A-page 66 Preliminary 2004 Microchip Technology Inc.
FIGURE 12-1: PIC10F200/202/204/206 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
2004 Microchip Technology Inc. Preliminary DS41239A-page 67
PIC10F200/202/204/206
12.1 DC Characteristics: PIC10F200/202/204/206 (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
Param
No. Sym Characteristic Min Typ(1) Max Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 12-1
D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset —Vss— VSee Section 9.4 “DC Character-
istics” for details
D004 SVDD VDD Rise Rate to ensure
Power-on Reset 0.05* — — V/ms See Section 9.4 “DC Character-
istics” for details
D010 IDD Supply Current(3) —
—170
350 TBD
TBD µA
µAFOSC = 4 MHz, VDD = 2.0V
FOSC = 4 M Hz, VDD = 5.0V
D020 IPD Power-down Current(4) —0.1TBDµAVDD = 2.0V
D022 ∆IWDT WDT Current(4) —1.0TBDµAVDD = 2.0V
D023 ∆ICMP Comparator Current(4) —15TBDµAVDD = 2.0V
D024 ∆IVREF Internal Reference Current(4) —TBDTBDµAVDD = 2.0V
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test condit ions for all IDD measurements in active Operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Power-do wn c urre nt is measured wit h th e part in Sle ep mo de, with all I/ O pi ns in high-impedance sta te a nd
tied to VDD or VSS.
PIC10F200/202/204/206
DS41239A-page 68 Preliminary 2004 Microchip Technology Inc.
12.2 DC Characteristics: PIC10F200/202/204/206 (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +125°C (extende d)
Param
No. Sym Characteristic Min Typ(1) Max Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 12-1
D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset —Vss— VSee Section 9.4 “DC Character-
istics” for details
D004 SVDD VDD Rise Rate to ensure
Power-on Reset 0.05* — — V/ms See Section 9.4 “DC Character-
istics” for details
D010 IDD Supply Current(3) —
—170
350 TBD
TBD µA
µAFOSC = 4 MHz, VDD = 2.0V
FOSC = 4 M Hz, VDD = 5.0V
D020 IPD Power-down Current(4) —0.1TBDµAVDD = 2.0V
D022 ∆IWDT WDT Current(4) —1.0TBDµAVDD = 2.0V
D023 ∆ICMP Comparator Current(4) —15TBDµAVDD = 2.0V
D024 ∆IVREF Internal Reference Current(4) —TBDTBDµAVDD = 2.0V
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test condit ions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
4: Power-do wn c urre nt is measured wit h th e part in Sle ep mo de, with all I/ O pi ns in hi gh-impedance st ate and
tied to VDD or VSS.
2004 Microchip Technology Inc. Preliminary DS41239A-page 69
PIC10F200/202/204/206
TABLE 12-1: DC CHARACTERISTICS: PIC10F200/202/204/206 (Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as descr ibed in DC specification
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer Vss — 0.8V V For all 4.5 ≤ VDD ≤ 5.5V
D030A Vss — 0.15 VDD V Otherwise
D031 with Schmitt Trigger
buffer Vss — 0.15 VDD V
D032 MCLR, T0 C K I Vss — 0.1 5 VDD V
VIH Input High Voltage
I/O ports: —
D040 with TTL buffer 2.0 — VDD V4.5 ≤ VDD ≤ 5.5V
D040A 0.25 VDD
+ 0.8 VDD —VDD V Otherwise
D041 with Schmitt Trigger
buffer 0.85 VDD —VDD V F or entire VDD range
D042 MCLR, T0 C K I 0 .8 5 VDD —VDD V
D070 IPUR GPIO weak pull-up current(3) TBD 250 TBD µAVDD = 5V, VPIN = VSS
IIL Input Leakage Current(1, 2)
D060 I/O ports — — ± 1 µA Vss ≤ VPIN ≤ VDD, Pin at high-impedance
D061 GP3/MCLR(4) ——± 30µA Vss ≤ VPIN ≤ VDD
D061A GP3/MCLR(5) ——± 5µA Vss ≤ VPIN ≤ VDD
Output Lo w Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage
D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
Capacitive Loading Specs
on Output Pins
D101 All I/O pins — — 50* pF
Legend: T BD = To Be Determined.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
* These parameters are for design guidance only and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.
3: Does not include GP3. For GP3 see par amet ers D061 and D061A.
4: This specification applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal
pull-up enabled.
5: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the
MCLR circuit is higher than the standard I/O logic.
PIC10F200/202/204/206
DS41239A-page 70 Preliminary 2004 Microchip Technology Inc.
TABLE 12-2: COMPARATOR SPECIFICATIONS
TABLE 12-3: PULL-UP RESISTOR RANGES – PIC10F200/202/204/206
Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125° C , un le ss otherwise stated.
Param
No. Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ±5.0 TBD mV
D301 VICM Input Common Mode Voltage 0 — VDD – 1.5* V
D302 CMRR Common Mode Rejection
Ratio 55* — — db
D303 TRESP Response Ti m e(1) —300 TBD nsVDD = 3.0V to 5.5V, -40° to +85°C
D304 TMC2OV Comparator M ode Change t o
Output Valid —300 TBD ns
D305 VIVRF Internal Reference Voltage TBD 0.6 TBD V TBD
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
Note 1: Response tim e m easured w ith on e comparator in put at (VDD – 1.5)/2 while the other input transitions from VSS
to V DD.
VDD (Volts) Temperature (°C) Min Typ Max Units
GP0/GP1
2.0 -40 TBD TBD TBD Ω
25 TBD TBD TBD Ω
85 TBD TBD TBD Ω
125 TBD TBD TBD Ω
5.5 -40 TBD TBD TBD Ω
25 TBD TBD TBD Ω
85 TBD TBD TBD Ω
125 TBD TBD TBD Ω
GP3
2.0 -40 TBD TBD TBD Ω
25 TBD TBD TBD Ω
85 TBD TBD TBD Ω
125 TBD TBD TBD Ω
5.5 -40 TBD TBD TBD Ω
25 TBD TBD TBD Ω
85 TBD TBD TBD Ω
125 TBD TBD TBD Ω
Legend: TBD = To Be determined.
* These parameters are characterized but not tested.
2004 Microchip Technology Inc. Preliminary DS41239A-page 71
PIC10F200/202/204/206
12.3 Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/206
The timing parameter symbols have been created following one of the following formats:
FIGURE 12-2: LOAD CONDITIONS – PIC10F200/202/204/206
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp2to mcMCLR
ck CLKOUT osc Oscillator
cy Cycle time os OSC1
drt Device Reset Timer t0 T0CKI
io I/O port wdt Watchd og Timer
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
CL
VSS
pin Legend:
CL = 50 pF for all pins
PIC10F200/202/204/206
DS41239A-page 72 Preliminary 2004 Microchip Technology Inc.
TABLE 12-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F200/202/204/206
FIGURE 12-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –
PIC10F200/202/204/206
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise spec ified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section 12.1 “DC Characteristics”.
Param
No. Sym Characteristic Freq
Tolerance Min Typ† Max Units Conditions
F10 FOSC Internal Calibrated
INTOSC Frequency(1) ± 1% TBD 4.00 TBD MHz VDD and Temperature TBD
± 2% TBD 4.00 TBD MHz 2.5V ≤ VDD ≤ 5.5V
Temper atur e TBD
± 5% TBD 4.00 TBD MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (ext ende d)
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) colu mn is a t 5V, 25°C unless ot herwi se st at ed. The se para me ters are for des ign
guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitiv ely decoupled as close to
the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.
VDD
MCLR
Internal
POR
DRT
Timeout(2)
Internal
Reset
Watchdog
Timer
Reset
32
31
34
I/O pin(1)
32 32
34
30
Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.
2: Runs on POR only.
2004 Microchip Technology Inc. Preliminary DS41239A-page 73
PIC10F200/202/204/206
TABLE 12-5: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F200/202/204/206
FIGURE 12-4: TIMER0 CLOCK TIMINGS – PIC10F200/202/204/206
TABLE 12-6: TIMER0 CLOCK REQUIREMENTS – PIC10F200/202/204/206
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Secti on 12.1 “DC
Characteristics”
Param
No. Sym Characteristic Min Typ(1) Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2000* — — ns VDD = 5.0V
31 TWDT Watchd og T im er T i me-out Pe riod
(no prescaler) 9*
9* 18*
18* 30*
40* ms
ms VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
32 TDRT Device Reset Timer Period(2) 9*
9* 18*
18* 30*
40* ms
ms VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
34 TIOZ I/O High-imped ance from MC LR
low — — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in th e Typica l (“Typ”) col umn is at 5V, 25°C unl ess o therwi se st ated . These pa rameter s are for des ign
guidance only and are not tested.
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section 12.1 “DC Characteristics”.
Param
No. Sym Characteristic Min Typ(1) Max Units Conditions
40 Tt0H T0CKI High Pulse
Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse
Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whic hev er is grea ter.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C un less otherwise stated. These parameters are for design
guidance only and are not tested.
T0CKI
40 41
42
PIC10F200/202/204/206
DS41239A-page 74 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 75
PIC10F200/202/204/206
13.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
PIC10F200/202/204/206
DS41239A-page 76 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 77
PIC10F200/202/204/206
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example
10F206-I
0432
/P017
6-Lead SOT-23
X X N N Example
CH17
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanum eri c traceab ility code
Note: In the event the full M icroch ip p art nu mber ca nnot be m arked on one line, it w ill
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
PIC10F200/202/204/206
DS41239A-page 78 Preliminary 2004 Microchip Technology Inc.
6-Lead Plastic Small Outline Transistor (CH or OT) (SOT-23)
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
φ
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059
E1
Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000
A1
Standoff
1.301.100.90.051.043.035
A2
Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
66
n
Number of Pins
MAX
NOM
MINMAX
NOM
MINDimension Limits
MILLIMETERSINCHES*Units
1
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
exceed .005" (0.127mm) per side.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
Notes:
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
*Controlling Parameter
2004 Microchip Technology Inc. Preliminary DS41239A-page 79
PIC10F200/202/204/206
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .3 13 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
PIC10F200/202/204/206
DS41239A-page 80 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41239A-page 81
PIC10F200/202/204/206
INDEX
A
ALU.......................................................................................9
Assembler
MPASM Ass embler.....................................................59
B
Block Diagram
On-Chip Rese t Circuit.................. .......... ........... ..........44
Timer0...................................................................29, 33
TMR0/WDT Pr escaler.....................................32, 36, 38
Watchdog Timer...................... ....... .... .. .... .. .. ......... .. .. ..47
Brown-Out Protection Circuit ..............................................48
C
C Compilers
MPLAB C17................ ...................................... ..........60
MPLAB C18................ ...................................... ..........60
MPLAB C30................ ...................................... ..........60
Carry .....................................................................................9
Clocking Scheme................................................................13
Code Protection ............................................................41, 50
Comparator
Comparator Module......................... .. .. .... .. .. ....... .. .. .. ..37
Configuration...............................................................38
Interrupts.....................................................................39
Operation ....................................................................39
Reference ...................................................................39
Configuration Bits................................................................41
D
DC and AC Characteristics......................................... .... .. ..75
Demonstration Boards
PICDEM 1........ ........... ................... .......... ...................62
PICDEM 17.................................... .......... ...................63
PICDEM 18R ...................... ........... ................... ..........63
PICDEM 2 Plus............................ .......... ................... ..62
PICDEM 3........ ........... ................... .......... ...................62
PICDEM 4........ ........... ................... .......... ...................62
PICDEM LIN ......... .................. ........... ................... ......63
PICDEM USB.............. .......... ................... ........... ........63
PICDEM.net Internet/Ethernet....................................62
Development Support .........................................................59
Digit Carry.............................................................................9
E
Errata ....................................................................................3
Evalu a tio n a nd Pr o g ramming Tools............... ................... ..63
F
Family of Devices
PIC10F200/202/204/206...............................................5
G
GPIO...................................................................................25
I
I/O Int e rfacing............. ................... ..................................... 25
I/O Ports ....................... ................... .......... ................... ...... 25
I/O Prog ramming Consideratio n s.... ................... .......... ...... 26
ID Locations.................................................................. 41, 50
INDF ................................................................................... 23
Indire ct Data Addressing .................................................... 23
Instru ction Cycle................................................................. 13
Instru ction Flow/Pipelining.................................................. 13
Instru ction Set Summary .................................................... 52
L
Loading of PC................................ .... .... .... ......... .. .... .... .... .. 22
M
Memory Organization ......................................................... 15
Data Memor y................................... ................... ........ 1 6
Program Memory (P IC10F200/ 204) ........................... 15
Program Memory (P IC10F202/ 206) ........................... 16
MPLAB ASM30 Assembler, Linker, Librarian............. ........ 6 0
MPLAB ICD 2 In-Circuit Debugger..................................... 61
MPLAB ICE 2000 High-Perf orm ance Univers a l
In-Circuit Emulator.................... .......... ................... .... 61
MPLAB ICE 4000 High-Perf orm ance Univers a l
In-Circuit Emulator.................... .......... ................... .... 61
MPLAB Integrated Development Environment Software.... 59
MPLAB PM3 Device Programmer...................................... 61
MPL IN K Obje ct Link e r / M PLIB Ob j e ct Libra ri a n....... ...... .. ... 60
O
Option Register................................................................... 20
OSCCAL Register................. ................... ........... ................ 21
Oscillator Configurations. .. ......... ......................................... 42
Oscillator Types
HS............................................................................... 42
LP............................................................................... 42
P
PIC10F200/202/204/206 Device Varieties............................ 7
PICkit 1 Fla sh Starter Kit...... ................... ........... ................ 63
PICSTART Plus Development Programmer....................... 62
PORDe v i ce R e s et Timer (D RT) ..... ...... ...... ..... ...... ...... . 41 , 4 6
PD............................................................................... 48
Power-on Reset (POR)............................................... 41
TO............................................................................... 48
Power-down Mode.............................................................. 49
Prescaler ...................................................................... 31, 35
PRO MATE II Univer sal De vice Progr a mm er..... .......... ...... 61
Program Counter................................................................ 22
Q
Q cycles... ................... .......... ................... ................... ........ 13
R
Read-Modify-Write.............................................................. 26
Register File Map
PIC10F200/204 .......................................................... 17
PIC10F202/206 .......................................................... 17
Registers
Special Function......................................................... 18
Reset .................................................................................. 41
Reset on Brown -Out... ................... ................... .......... ........ 48
PIC10F200/202/204/206
DS41239A-page 82 Preliminary 2004 Microchip Technology Inc.
S
Sleep.............................................................................41, 49
Softwa re Simulator (MPLAB SIM )........................ ........... ....60
Softwa re Simulator (MPLAB SIM 3 0 )........................ ...........60
Speci a l Features of the CPU....... ...................................... ..41
Special Function Registers .................................................18
Stack...................................................................................22
Statu s Reg i ster............. ........... ................... .....................9, 19
T
Timer0
Timer0...................................................................29, 33
Timer0 (TMR0) Module.........................................29, 33
TMR0 with External Clock .....................................30, 34
Timing Parameter Symbology and Load Conditions...........71
TRIS Registers............. ................... ........... .................. .......25
W
Wake-up from Sleep ...........................................................49
Watchdog Timer (WDT)...................... .... ......... .. .... .... .. .41, 46
Period..........................................................................46
Programming Consi der a tions .................. ...................46
WWW, On-Line Support ........................................................3
Z
Zero bit....................... ...................................... ................... ..9
2004 Microchip Technology Inc. Preliminary DS41239A-page 83
PIC10F200/202/204/206
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web S ite
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errat a
• Job Postin gs
• Microch ip Consultant Pr ogram Member Listing
• Links to other useful web sites related to
Microchip Products
• Confere nces for prod ucts, Dev elopment Systems,
technical information and more
• Listi ng of seminars and events
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kit s. The Hot Line
Numbe rs are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
PIC10F200/202/204/206
DS41239A-page 84 Preliminary 2004 Microchip Technology Inc.
READER RESPONSE
It is ou r intention to pro vi de you with the b est do cu me nt ation possib le to e ns ure successful u se of y ou r Mic r oc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, su bject m atter, and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the followi ng information, and use this outline to provide us with your comments about this document.
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RE: Reader Response Total Pages Sent ________
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Questions:
FAX: (______) _________ - _________
DS41239APIC10F200/202/204/206
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2004 Microchip Technology Inc. Preliminary DS41239A-page 85
PIC10F200/202/204/206
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC10F200
PIC10F202
PIC10F204
PIC10F206
PIC10F200T (Tape & Reel)
PIC10F202T (Tape & Reel)
PIC10F204T (Tape & Reel)
PIC10F206T (Tape & Reel)
Temperatu re Rang e I = -40°C to +85°C (Industrial)
E= -40°C to +125°C (Extended)
Package PG = 300 mil PDIP (Pb-fr ee)
OTG = SOT-23, 6-LD (Pb-free)
Pattern Special Requirements
Examples:
a) PIC10F200-I/PG = Industrial temp., PDIP
package (Pb-free)
b) PIC10F202T-E/OTG = Extended temp.,
SOT-23 package (Pb-free), Tape and Reel
Note: Tap e and Reel avai la ble for onl y the follow ing packag es: S O T-23.
DS41239A-page 86 Preliminary 2004 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-7 92- 72 00
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: www.microchip.com
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France
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05/28/04
WORLDWIDE SALES AND SERVICE
