MAX8550ETI+T - Maxim Integrated

19-3173; Rev 3; 4/13

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

EVALUATION KIT AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

General Description

The MAX8550/MAX8551 integrate a synchronous-buck

PWM controller to generate VDDQ, a sourcing and sinking

LDO linear regulator to generate VTT, and a 10mA refer-

ence output buffer to generate VTTR. The buck controller

drives two external N-channel MOSFETs to generate out-

put voltages down to 0.7V from a 2V to 28V input with out-

put currents up to 15A. The LDO can sink or source up to

1.5A continuous and 3A peak current. Both the LDO out-

put and the 10mA reference buffer output can be made

to track the REFIN voltage. These features make the

MAX8550/MAX8551 ideally suited for DDR memory appli-

cations in desktops, notebooks, and graphic cards.

The PWM controller in the MAX8550/MAX8551 utilizes

Maxim’s proprietary Quick-PWM™ architecture with pro-

grammable switching frequencies of up to 600kHz. This

control scheme handles wide input/output voltage ratios

with ease and provides 100ns response to load tran-

sients while maintaining high efficiency and a relatively

constant switching frequency. The MAX8550 offers fully

programmable UVP/OVP and skip-mode options ideal in

portable applications. Skip mode allows for improved

efficiency at lighter loads. The MAX8551, which is tar-

geted towards desktop and graphic-card applications,

does not offer the pulse-skip feature.

The VTT and VTTR outputs track to within 1% of VREFIN / 2.

The high bandwidth of this LDO regulator allows excel-

lent transient response without the need for bulk capac-

itors, thus reducing cost and size.

The buck controller and LDO regulators are provided with

independent current limits. Adjustable lossless foldback

current limit for the buck regulator is achieved by monitor-

ing the drain-to-source voltage drop of the low-side MOS-

FET. Additionally, overvoltage and undervoltage

protection mechanisms are built in. Once the overcurrent

condition is removed, the regulator is allowed to enter

soft-start again. This helps minimize power dissipation

during a short-circuit condition. The MAX8550/MAX8551

allow flexible sequencing and standby power manage-

ment using the SHDNA, SHDNB, and STBY inputs.

Both the MAX8550 and MAX8551 are available in a

small 5mm ×5mm, 28-pin thin QFN package.

Applications

DDR I and DDR II Memory Power Supplies

Desktop Computers

Notebooks and Desknotes

Graphic Cards

Game Consoles

RAID

Networking

Features

Buck Controller

oQuick-PWM with 100ns Load-Step Response

oUp to 95% Efficiency

o2V to 28V Input Voltage Range

o1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output

oUp to 600kHz Selectable Switching Frequency

oProgrammable Current Limit with Foldback

Capability

o1.7ms Digital Soft-Start and Independent

Shutdown

oOvervoltage/Undervoltage-Protection Option

oPower-Good Window Comparator

LDO Section

oFully Integrated VTT and VTTR Capability

oVTT has ±3A Sourcing/Sinking Capability

oVTT and VTTR Outputs Track VREFIN / 2

oAll-Ceramic Output-Capacitor Designs

o1.0V to 2.8V Input Voltage Range

oPower-Good Window Comparator

PART TEMP RANGE PIN-PACKAGE

MAX8550ETI -40°C to +85°C 28 5mm × 5mm TQFN

MAX8550ETI+ -40°C to +85°C 28 5mm × 5mm TQFN

MAX8551ETI -40°C to +85°C 28 5mm × 5mm TQFN

MAX8551ETI+ -40°C to +85°C 28 5mm × 5mm TQFN

Ordering Information

MAX8550

MAX8551

5mm x 5mm Thin QFN

TOP VIEW

OVP/UVP

(N.C. FOR

MAX8551)

TON

REF

ILIM

POK1

POK2

STBY

SHDNB

SHDNA

SKIP

(TP1 FOR

MAX8551)

GND

PGND1

BST

VIN

OUT

REFIN

VTTI

VTT

PGND2

VTTR

VTTS

Pin Configuration

Typical Operating Circuit appears at end of data sheet.

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

Denotes a lead(Pb)-free/RoHS-compliant package.

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

2Maxim Integrated

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

MAIN PWM CONTROLLER

VIN 228

Input Voltage Range

VDD, AVDD

4.5 5.5 V

Output Adjust Range VOUT 0.7 5.5 V

FB = OUT

0.693

0.7

0.707

FB = GND

2.47

2.5

2.53

Output Voltage Accuracy

(Note 2)

FB = VDD

1.78

1.8

1.82

Soft-Start Ramp Time tSS Rising edge of SHDNA to full current limit 1.7 ms

TON = GND (600kHz)

170 194

219

TON = REF (450kHz)

213 243

273

TON = OPEN (300kHz) 316 352

389

On-Time tON

VIN = 15V,

VOUT = 1.5V

(Note 3)

TON = AVDD (200kHz) 461 516

571

Minimum Off-Time

tOFF_MIN

(Note 3)

200 300

450 ns

VIN Quiescent Supply Current IIN 25 40 µA

VIN Shutdown Supply Current SHDNA = SHDNB = GND 1 5 µA

All on (PWM, VTT, and VTTR on) 2.5 5

SHDNA = GND (only VTT and VTTR on) 2 4

STBY = AVDD (only VTTR and PWM on) 1 2

AVDD Quiescent Supply Current IAVDD

SHDNB = GND (only PWM on) 0.5 1

AVDD + VDD Shutdown Supply

Current SHDNA = SHDNB = GND 2 10 µA

Rising edge of VIN 4.1

4.25

4.4 V

AVDD Undervoltage-Lockout

Threshold Hysteresis 50 mV

VDD Quiescent Supply Current IVDD Set VFB = 0.8V 1 5 µA

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN = +15V, VDD = AVDD = VSHDNA = VSHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP

= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VIN to GND .............................................................-0.3V to +30V

VDD, AVDD , VTTI to GND .........................................-0.3V to +6V

SHDNA, SHDNB, REFIN to GND..............................-0.3V to +6V

SS, POK1, POK2, SKIP, ILIM, FB to GND ................-0.3V to +6V

STBY, TON, REF, UVP/OVP to GND ........-0.3V to (AVDD + 0.3V)

OUT, VTTR to GND ..................................-0.3V to (AVDD + 0.3V)

DL to PGND1..............................................-0.3V to (VDD + 0.3V)

DH to LX....................................................-0.3V to (VBST + 0.3V)

LX to BST..................................................................-6V to +0.3V

LX to GND .................................................................-2V to +30V

VTT to GND...............................................-0.3V to (VVTTI + 0.3V)

VTTS to GND............................................-0.3V to (AVDD + 0.3V)

PGND1, PGND2 to GND .......................................-0.3V to +0.3V

REF Short Circuit to GND ...........................................Continuous

Continuous Power Dissipation (TA= +70°C)

28-Pin 5mm x 5mm TQFN (derate 35.7mW/°C

above +70°C).................................................................2.86W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10s) .................................+300°C

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

REFERENCE

Reference Voltage VREF AVDD = 4.5V to 5.5V; IREF = 0

1.98

2.02

Reference Load Regulation IREF = 0 to 50µA

0.01

VREF rising

1.93

REF Undervoltage Lockout Hysteresis

300

FAULT DETECTION

OVP Trip Threshold

(Referred to Nominal VOUT)

UVP/OVP = AVDD (Note 4)

112 116

120 %

UVP Trip Threshold

(Referred to Nominal VOUT)65 70 75 %

Lower level, falling edge, 1% hysteresis 87 90 93

POK1 Trip Threshold

(Referred to Nominal VOUT)Upper level, rising edge, 1% hysteresis

107 110

113 %

Lower level, falling edge, 1% hysteresis

87.5

92.5

POK2 Trip Threshold

(Referred to Nominal VVTTS

and VVTTR)Upper level, rising edge, 1% hysteresis

107.5 110 112.5

UVP Blanking Time From rising edge of SHDNA 10 20 40 ms

OVP, UVP, POK_ Propagation

Delay OVP not applicable in MAX8551 10 µs

POK_ Output Low Voltage ISINK = 4mA 0.3 V

POK_ Leakage Current VPOK_ = 5.5V, VFB = 0.8V, VVTTS = 1.3V 1 µA

ILIM Adjustment Range VILIM

0.25 2.00

ILIM Input Leakage Current 0.1 µA

Current-Limit Threshold (Fixed)

PGND1 to LX 45 50 55 mV

Current-Limit Threshold

(Adjustable) PGND1 to LX VILIM = 2V

170 200

235 mV

Current-Limit Threshold (Negative

Direction) PGND1 to LX SKIP = AVDD (Note 4) -75 -60 -45 mV

Current-Limit Threshold (Negative

Direction) PGND1 to LX SKIP = AVDD, VILIM = 2V (Note 4)

-250

Zero-Crossing Detection

Threshold PGND1 to LX 3mV

Thermal-Shutdown Threshold

+160

°C

Thermal-Shutdown Hysteresis 15 °C

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +15V, VDD = AVDD = VSHDNA = VSHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP

= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at TA= +25°C.) (Note 1)

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

4Maxim Integrated

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MOSFET DRIVERS

DH Gate-Driver On-Resistance VBST - VLX = 5V 1 4 Ω

DL Gate-Driver On-Resistance in

High State 14Ω

DL Gate-Driver On-Resistance in

Low State 0.5 3 Ω

DH falling to DL rising 30

Dead Time (Additional to

Adaptive Delay) DL falling to DH rising 30 ns

INPUTS AND OUTPUTS

Rising edge

1.20

1.7

2.20

Logic Input Threshold

(SHDN_, STBY, SKIP (Note 4)) Hysteresis

225

Logic Input Current

(SHDN_, STBY, SKIP (Note 4)) -1 +1 µA

Low (2.5V output)

0.05

Dual-Mode™ Input Logic

Levels (FB) High (1.8V output) 2.1 V

Input Bias Current (FB)

-0.1 +0.1

µA

High AVDD -

0.4

Floating

3.15 3.85

REF

1.65 2.35

Four-Level Input Logic Levels

(TON, OVP/UVP (Note 4))

Low 0.5

Logic Input Current

(TON, OVP/UVP (Note 4)) -3 +3 µA

FB = GND 90

175

350

FB = AVDD 70

135

270OUT Input Resistance

FB adjustable mode

400 800 1600

kΩ

OUT Discharge-Mode

On-Resistance (Note 4) 10 25 Ω

DL Turn-On Level During

Discharge Mode

(Measured at OUT)

(Note 4) 0.3 V

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +15V, VDD = AVDD = VSHDNA = VSHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP

= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at TA= +25°C.) (Note 1)

Dual Mode is a trademark of Maxim Integrated Products, Inc.

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

Note 1: Specifications to -40°C are guaranteed by design, not production tested.

Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-compara-

tor threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the

trip level by approximately 1.5% due to slope compensation.

Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V,

and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.

Note 4: Not applicable to the MAX8551.

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

LINEAR REGULATORS (VTTR AND VTT)

VTTI Input Voltage Range VVTTI 1 2.8 V

VTTI Supply Current IVTTI IVTT = IVTTR = 0

<0.1

1mA

VTTI Shutdown Current SHDNA = SHDNB = GND 10 µA

REFIN Input Impedance VREFIN = 2.5V 12 20 30 kΩ

REFIN Range VREFIN 1

2.8

VREFIN rising 0.7 0.9 V

REFIN Lockout Threshold Hysteresis 75 mV

Soft-Start Charge Current ISS VSS = 0 4 µA

VTT Internal MOSFET High-Side

On-Resistance

IVTT = -100mA, VVTTI = 1.5V,

AVDD = 4.5V 0.3 Ω

VTT Internal MOSFET Low-Side

On-Resistance IVTT = 100mA, AVDD = 4.5V 0.3 Ω

VTT Output Accuracy

(Referred to VREFIN / 2) VREFIN = 1.5V or 2.5V, IVTT = 1mA -1 +1 %

VREFIN = 2.5V, IVTT = 0 to ±1.5A 1

VTT Load Regulation VREFIN = 1.5V, IVTT = 0 to ±1A 1 %

VTT Current Limit VTT = 0 or VTTI ±3 ±5

±6.5

VTTS Input Current IVTTS VVTTS = 1.5V, VTT open

0.1

1µA

VTTR Output Error

(Referred to VREFIN / 2) VREFIN = 1.5V or 2.5V, IVTTR = 0 -1 +1 %

VTTR Current Limit VVTTR = 0 or VVTTI

±23 ±40 ±60

ELECTRICAL CHARACTERISTICS (continued)

(VIN = +15V, VDD = AVDD = VSHDNA = VSHDNB = VBST = VILIM = 5V, VOUT = VREFIN = VVTTI = 2.5V, UVP/OVP = STBY = FB = SKIP

= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, VVTTS = VVTT, TA= -40°C to +85°C, unless otherwise noted. Typical values

are at TA= +25°C.) (Note 1)

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

6Maxim Integrated

Typical Operating Characteristics

(VIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA= +25°C, unless otherwise noted.)

EFFICIENCY vs. LOAD CURRENT

(TON = GND)

MAX8550/51 toc01

ILOAD (A)

EFFICIENCY (%)

1010.1

100

0.01 100

fSW = 600kHz

VOUT = 2.5V

VOUT = 1.8V

VOUT = 1.5V

SKIP = GND

SKIP = AVDD

EFFICIENCY vs. LOAD CURRENT

(TON = OPEN)

MAX8550/51 toc02

ILOAD (A)

EFFICIENCY (%)

1010.1

100

0.01 100

fSW = 300kHz

VOUT = 2.5V

VOUT = 1.8V

VOUT = 1.5V

SKIP = GND

SKIP = AVDD

SWITCHING FREQUENCY vs. LOAD CURRENT

(TON = GND)

MAX8550/51 toc03

ILOAD (A)

FREQUENCY (kHz)

1110892345671

100

150

200

250

300

350

400

450

500

550

600

650

700

012

SKIP = GND

SKIP = AVDD

SWITCHING FREQUENCY vs. INPUT VOLTAGE

(TON = GND)

MAX8550/51 toc04

VIN (V)

FREQUENCY (kHz)

262420 22810 12 14 16 186

420

440

460

480

500

540

520

560

580

600

620

640

660

680

700

400

428

ILOAD = 12A

ILOAD = 0A

SWITCHING FREQUENCY vs. TEMPERATURE

(TON = GND)

MAX8550/51 toc05

TEMPERATURE (°C)

FREQUENCY (kHz)

80655035205-10-25

650

660

670

680

690

700

600

640

630

620

610

-40

ILOAD = 12A

OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX8550/51 toc06

ILOAD (A)

VOUT (V)

12106 842

2.495

2.500

2.505

2.510

2.515

2.520

2.525

2.530

2.535

2.540

2.490

014

VIN = 15V,

TON = GND

SKIP = GND

SKIP = AVDD

VTT VOLTAGE

vs. VTT CURRENT

MAX8550/51 toc07

IVTT (A)

VVTT (V)

21-2 -1 0

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.20

-3 3

VTTR VOLTAGE

vs. VTTR CURRENT

MAX8550/51 toc08

IVTTR (mA)

VVTTR (V)

105-10 -5 0

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.20

-15 15

LINE REGULATION

(VOUT vs. VIN)

MAX8550/51 toc09

VIN (V)

VOUT (V)

262420 228 10 12 14 16 186

2.46

2.47

2.48

2.49

2.50

2.51

2.52

2.53

2.54

2.55

2.45

428

ILOAD = 0A

ILOAD = 12A

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

LOAD TRANSIENT (BUCK)

MAX8550/51 toc10

20µs/div

12A

VOUT

100mV/div

VTT

100mV/div

VTTR

100mV/div

ILOAD

10A/div

0.1A

IVTT = 1.5A, IVTTR = 15mA

LOAD TRANSIENT VTT (-1.5A TO +1.5A)

MAX8550/51 toc11

40µs/div

VOUT

50mV/div

VTT

50mV/div

VTTR

50mV/div

IVTT

2A/div

ILOAD = 12A, IVTTR = 15mA

LOAD TRANSIENT VTT (-3A TO +3A)

MAX8550/51 toc12

40µs/div

VOUT

50mV/div

VTT

50mV/div

VTTR

50mV/div

IVTT

5A/div

ILOAD = 12A, IVTTR = 15mA

POWER-UP WAVEFORMS

MAX8550/51 toc13

200µs/div

OUT

1V/div

VTT

2V/div

VTTR

1V/div

VIN

10V/div

VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA

POWER-DOWN WAVEFORMS

MAX8550/51 toc14

200µs/div

OUT

1V/div

VTT

2V/div

VTTR

1V/div

VIN

10V/div

VDD = 5V, ILOAD = 12A, IVTT = 1.5A, IVTTR = 15mA

VDDQ STARTUP AND SHUTDOWN INTO

HEAVY LOAD, DISCHARGE DISABLED

MAX8550/51 toc15

1ms/div

VOUT

2V/div

VTT

1V/div

VSHDNA + VSHDNB

5V/div

POK1

5V/div

ILOAD = 12A,

IVTT = 1.5A

Typical Operating Characteristics (continued)

(VIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA= +25°C, unless otherwise noted.)

VDDQ STARTUP AND SHUTDOWN INTO

LIGHT LOAD, DISCHARGE ENABLED

MAX8550/51 toc16

2ms/div

VOUT

1V/div

VTT

1V/div

VSHDNA + VSHDNB

5V/div

VPOK1

5V/div

RLOAD = 10Ω,

RVTT = 20Ω

VTT, VTTR STARTUP AND SHUTDOWN

MAX8550/51 toc17

200µs/div

VVTT

1V/div

VVTTR

1V/div

VSHDNB

5V/div

VPOK2

5V/div

IVTT = 1.5A, IVTTR = 15mA

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

8Maxim Integrated

OVERVOLTAGE AND TURN-OFF

OF BUCK OUTPUT

MAX8550/51 toc18

20µs/div

VOUT

2V/div

25A/div

VDL

5V/div

VDH

20V/div

Typical Operating Characteristics (continued)

(VIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA= +25°C, unless otherwise noted.)

SHORT CIRCUIT AND

RECOVERY OF VDDQ

MAX8550/51 toc19

400µs/div

VOUT

2V/div

ILOAD

10A/div

VIN

10V/div

IIN

2A/div

UVP DISABLED, FOLDBACK CURRENT LIMIT

SHORT CIRCUIT AND

RECOVERY OF VDDQ

MAX8550/51 toc20

400µs/div

VOUT

2V/div

ILOAD

10A/div

VIN

10V/div

IIN

2A/div

UVP ENABLED

SHORT CIRCUIT OF VTT

MAX8550/51 toc21

400µs/div

VVTT

1V/div

IVTT

5A/div

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

Pin Description

PIN NAME FUNCTION

1TON

On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect to

GND, REF, AVDD, or leave TON unconnected to select the following nominal switching frequencies:

TON = AVDD (200kHz)

TON = OPEN (300kHz)

TON = REF (450kHz)

TON = GND (600kHz)

OVP/

UVP

(MAX8550)

Overvoltage/Undervoltage-Protection Control Input. This four-level logic input enables or disables the

overvoltage and/or undervoltage protection. The overvoltage limit is 116% of the nominal output

voltage. The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when

OVP is also enabled. Connect the OVP/UVP pin to the following pins for the desired function:

OVP/UVP = AVDD (Enable OVP and discharge mode, enable UVP.)

OVP/UVP = OPEN (Enable OVP and discharge mode, disable UVP.)

OVP/UVP = REF (Disable OVP and discharge mode, enable UVP.)

OVP/UVP = GND (Disable OVP and discharge mode, disable UVP.)

N.C.

(MAX8551) Do not connect; leave open.*

3 REF

+2.0V Reference Voltage Output. Bypass to GND with a 0.1µF (min) capacitor. REF can supply 50µA

for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDNA, SHDNB, and

STBY are low.

4 ILIM

Valley Current-Limit Threshold Adjustment for Buck Regulator. The current-limit threshold across PGND

and LX is 0.1 times the voltage at ILIM. Connect ILIM to a resistive divider, typically from REF to GND,

to set the current-limit threshold between 25mV and 200mV. This corresponds to a 0.25V to 2V range at

ILIM. Connect ILIM to AVDD to select the 50mV default current-limit threshold. See the Setting the

Current Limit section.

5 POK1

Buck Power-Good Open-Drain Output. POK1 is low when the buck output voltage is more than 10%

above or below the normal regulation point or during soft-start. POK1 is high impedance when the

output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown.

6 POK2

LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more

than 10% above or below the normal regulation point, which is typically REFIN / 2. In standby mode,

POK2 responds only to the VTTR input. POK2 is low in shutdown, and when VREFIN is less than 0.8V.

7 STBY

Standby. Connect to high for low-quiescent mode where the VTT output is disabled, but the VTTR

buffer is kept alive if SHDNB is high. POK2 takes input from only VTTR in this mode. PWM output can

be on or off, depending on the state of SHDNA.

8SS

Soft-Start Control for VTT and VTTR. Connect a capacitor (C9 in the Typical Applications Circuit) from

SS to ground (see the Soft-Start Capacitor Selection section). Leave SS open to disable soft-start.

SS discharges to ground when SHDNB is low. See the POR, UVLO, and Soft-Start section.

9 VTTS

Sensing Pin for Termination Supply Output. Normally connected to VTT pin to allow accurate regulation

to half the REFIN voltage. Connected to a resistive divider from VTT to GND to regulate VTT to higher

than half the REFIN voltage.

10 VTTR Termination Reference Voltage. VTTR tracks VREFIN / 2.

The MAX8551 has no OVP or discharge-mode feature. Only UVP is available.

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

10 Maxim Integrated

Pin Description (continued)

PIN NAME FUNCTION

11 PGND2 Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.

12 VTT Termination Power-Supply Output. Connect VTT to VTTS to regulate to VREFIN / 2.

13 VTTI Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator

for DDR application.

14 REFIN External Reference Input. This is used to regulate the VTT and VTTR outputs to VREFIN / 2.

15 FB

Feedback Input for Buck Output. Connect to AVDD for a +1.8V fixed output or to GND for a +2.5V fixed

output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output

voltage. FB regulates to +0.7V.

16 OUT

Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.

OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the

Typical Applications Circuit). OUT also serves as the buck output’s feedback input in fixed-output

modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an

internal 10Ω resistor connected between OUT and GND.

17 VIN Input-Voltage Sense Connection. Connect to input power source. VIN is used only to set the PWM’s on-

time one-shot timer. IN voltage range is from 2V to 28V.

18 DH High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.

19 LX External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current

limit and the return supply of the DH driver.

20 BST Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the

Typical Applications Circuit (Figure 8). See the Boost-Supply Diode and Capacitor Selection section.

21 DL Synchronous-Rectifier Gate-Driver Output. Swings from PGND to VDD.

22 VDD Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to

PGND1 with a 1µF (min) ceramic capacitor.

23 PGND1 Power Ground for Buck Controller. Connect PGND1 externally to the underside of the exposed pad.

24 GND Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.

SKIP

(MAX8550)

Pulse-Skipping Control Input. Connect to AVDD for low-noise, forced-PWM mode. Connect to GND to

enable pulse-skipping operation.

TP1

(MAX8551) In the MAX8551, this pin is a test pin and must be connected to GND (pin 24).

26 AVDD Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage

with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor.

27 SHDNA Shutdown Control Input A. Use to control buck output. A rising edge on SHDNA clears the overvoltage

and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AVDD for normal operation.

28 SHDNB Shutdown Control Input B. Use to control VTT and VTTR outputs. Both VTTR and VTT are high

impedence in shutdown (see Table 2).

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

MAX8550/

MAX8551

ON-TIME

COMPUTE

tON

ONE-SHOT

1.0V

1.16 x INTREF

OVP/UVP

LATCH

QUAD LEVEL

DECODE

20ms

TIMER

0.7 x INTREF

INTREF

DECODE

DISCHARGE

LOGIC N

REFERENCE

INTREF

VOUT = 1.8V

VOUT = 2.5V

INTREF + 10% INTREF - 10%

POWER-DOWN*

*POWER-DOWN

FORCES POK2 LOW

AND VTT, VTTR

HIGH IMPEDANCE.

+0.4V

10kΩ10kΩ

REFIN

2 - 10% REFIN

2 + 10%

REFIN

2 - 10% REFIN

2 + 10%

BST

VDD

PGND

ILIM

VDD - 1V

OUT

AVDD

GND

REF

REFIN

VTT

VDD

PGND2

VTTR

POK2

POK1

OVP/UVP

(N.C. IN MAX8551)

TON

tOFF

TRIG

ONE-SHOT

TRIG

ZERO CROSSING

VTTS

VTTI

CURRENT

LIMITS

VTT ILIM

VTTR ILIM

STBY

SHUTDOWN

DECODER

BUCK ON/OFF

VTT ON/OFF VTTR ON/OFF

BIAS ON/OFF

SHDNA

SHDNB

SKIP

(TP1 IN MAX8551

MUST BE CONNECTED TO GND)

VTTI

PGND2

OUT

Figure 1. Functional Diagram

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

12 Maxim Integrated

Detailed Description

The MAX8550/MAX8551 combine a synchronous-buck

PWM controller, an LDO linear regulator, and a 10mA ref-

erence output buffer. The buck controller drives two exter-

nal N-channel MOSFETs to deliver load currents up to

12A and generate voltages down to 0.7V from a +2V to

+28V input. The LDO linear regulator can sink and source

up to 1.5A continuous and 3A peak current with relatively

fast response. These features make the MAX8550/

MAX8551 ideally suited for DDR memory applications.

The MAX8550/MAX8551 buck regulator is equipped

with a fixed switching frequency of up to 600kHz using

Maxim’s proprietary constant on-time Quick-PWM

architecture. This control scheme handles wide

input/output voltage ratios with ease, and provides

100ns “instant-on” response to load transients, while

maintaining high efficiency with relatively constant

switching frequency.

The buck controller, LDO, and a reference output

buffer are provided with independent current limits.

Lossless foldback current limit in the buck regulator is

achieved by monitoring the drain-to-source voltage

drop of the low-side FET. The ILIM input is used to

adjust this current limit. Overvoltage protection, if

selected, is achieved by latching the low-side synchro-

nous FET on and the high-side FET off when the output

voltage is over 116% of its set output. It also features

an optional undervoltage protection by latching the

MOSFET drivers to the OFF state during an overcurrent

condition, when the output voltage is lower than 70% of

the regulated output. This helps minimize power dissi-

pation during a short-circuit condition.

The current limit in the LDO and buffered reference out-

put buffer is ±5A and ±40mA, respectively, and neither

have the over- or undervoltage protection. When the

current limit in either output is reached, the output no

longer regulates the voltage, but regulates the current

to the value of the current limit.

+5V Bias Supply (VDD and AVDD)

The MAX8550/MAX8551 require an external +5V bias

supply in addition to the input voltage (VIN). Keeping the

bias supply external to the IC improves the efficiency

and eliminates the cost associated with the +5V linear

regulator that would otherwise be needed to supply the

PWM circuit and the gate drivers. If stand-alone capabili-

ty is needed, then the +5V supply can be generated with

an external linear regulator such as the MAX1615. VDD,

AVDD, and IN can be connected together if the input

source is a fixed +4.5V to +5.5V supply.

VDD is the supply input for the buck regulator’s MOSFET

drivers, and AVDD supplies the power for the rest of

the IC. The current from the AVDD and VDD power

supply must supply the current for the IC and the gate

drive for the MOSFETs. This maximum current can be

estimated as:

where IVDD + IAVDD are the quiescent supply currents

into VDD and AVDD, QG1 and QG2 are the total gate

charges of MOSFETs Q1 and Q2 (at VGS = 5V) in the

Typical Applications Circuit

, and fSW is the switching

frequency.

Free-Running Constant-On-Time PWM

The Quick-PWM control architecture is a pseudo-fixed-

frequency, constant on-time, current-mode regulator

with voltage feed-forward (Figure 1). This architecture

relies on the output filter capacitor’s ESR to act as a

current-sense resistor, so the output ripple voltage pro-

vides the PWM ramp signal. The control algorithm is

simple: the high-side switch on-time is determined

solely by a one-shot whose pulse width is inversely pro-

portional to input voltage and directly proportional to

the output voltage. Another one-shot sets a minimum

off-time of 300ns (typ). The on-time one-shot is trig-

gered if the error comparator is low, the low-side switch

current is below the valley current-limit threshold, and

the minimum off-time one-shot has timed out.

On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the

high-side switch on-time. This fast, low-jitter, adjustable

one-shot includes circuitry that varies the on-time in

response to input and output voltages. The high-side

switch on-time is inversely proportional to the input volt-

age (VIN) and is proportional to the output voltage:

where K (the switching period) is set by the TON input

connection (Table 1) and RDS(ON)Q2 is the on-resis-

tance of the synchronous rectifier (Q2) in the

Typical

Applications Circuit

(Figure 8). This algorithm results in

a nearly constant switching frequency despite the lack

of a fixed-frequency clock generator. The benefits of a

constant switching frequency are twofold:

1) The frequency can be selected to avoid noise-sensi-

tive regions such as the 455kHz IF band.

VI R

OUT LOAD DS ON Q

()

=×

+×

()

IIIfQQ

BIAS VDD AVDD SW GG

=+ +×+

()

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

2) The inductor ripple-current operating point remains

relatively constant, resulting in an easy design

methodology and predictable output voltage ripple.

The on-time one-shot has good accuracy at the operat-

ing points specified in the

Electrical Characteristics

table (approximately ±12.5% at 600kHz and 450kHz,

and ±10% at 200kHz and 300kHz). On-times at operat-

ing points far removed from the conditions specified in

the

Electrical Characteristics

table can vary over a

wider range. For example, the 600kHz setting typically

runs approximately 10% slower with inputs much

greater than 5V due to the very short on-times required.

The constant on-time translates only roughly to a con-

stant switching frequency. The on-times guaranteed in

the

Electrical Characteristics

table are influenced by

resistive losses and by switching delays in the high-

side MOSFET. Resistive losses, which include the

inductor, both MOSFETs, the output capacitor’s ESR,

and any PC board copper losses in the output and

ground, tend to raise the switching frequency as the

load increases. The dead-time effect increases the

effective on-time, reducing the switching frequency as

one or both dead times are added to the effective on-

time. The dead time occurs only in PWM mode (SKIP =

VDD) and during dynamic output-voltage transitions

when the inductor current reverses at light or negative

load currents. With reversed inductor current, the induc-

tor’s EMF causes LX to go high earlier than normal,

extending the on-time by a period equal to the DH-rising

dead time. For loads above the critical conduction point,

where the dead-time effect is no longer a factor, the

actual switching frequency is:

where VDROP1 is the sum of the parasitic voltage drops

in the inductor discharge path, including the synchro-

nous rectifier, the inductor, and any PC board resis-

tances; VDROP2 is the sum of the resistances in the

charging path, including the high-side switch (Q1 in the

Typical Applications Circuit

), the inductor, and any PC

board resistances, and tON is the one-shot on-time (see

the

On-Time One-Shot (TON)

section.

Automatic Pulse-Skipping Mode

(

SKIP

= GND)

In skip mode (SKIP = GND), an inherent automatic

switchover to PFM takes place at light loads (Figure 2).

This switchover is affected by a comparator that trun-

cates the low-side switch on-time at the inductor cur-

rent’s zero crossing. The zero-crossing comparator

differentially senses the inductor current across the

synchronous-rectifier MOSFET (Q2 in the

Typical

Applications Circuit

, Figure 8). Once VPGND - VLX

drops below 5% of the current-limit threshold (2.5mV

for the default 50mV current-limit threshold), the com-

parator forces DL low (Figure 1). This mechanism caus-

es the threshold between pulse-skipping PFM and

nonskipping PWM operation to coincide with the

boundary between continuous and discontinuous

inductor-current operation (also known as the critical

conduction point). The load-current level at which

PFM/PWM crossover occurs, ILOAD(SKIP), is equal to

half the peak-to-peak ripple current, which is a function

of the inductor value (Figure 2). This threshold is rela-

tively constant, with only a minor dependence on the

input voltage (VIN):

where K is the on-time scale factor (see Table 1). For

example, in the

Typical Applications Circuit

of Figure 8

(K = 1.7µs, VOUT = 2.5V, VIN = 12V, and L = 1µH), the

pulse-skipping switchover occurs at:

The crossover point occurs at an even lower value if a

swinging (soft-saturation) inductor is used. The switch-

ing waveforms can appear noisy and asynchronous

when light loading causes pulse-skipping operation,

but this is a normal operating condition that results in

high light-load efficiency. Trade-offs in PFM noise vs.

25 17

12 2

12 168

. . .

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟=

- .5V

IVK

LOAD SKIP OUT IN OUT

()

=×

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

fVV

tV V

SW OUT DROP

ON IN DROP

()

Table 1. Approximate K-Factor Errors

TON SETTING

TYPICAL

K-

FACTOR

(µs)

K-FACTOR

ERROR

(%)

MINIMUM VIN AT

VOUT = 2.5V

(h = 1.5, SEE THE

DROPOUT

PERFORMANCE

SECTION)

200

(TON = AVDD)5.0 ±10 3.15

300

(TON = OPEN) 3.3 ±10 3.47

450

(TON = REF) 2.2 ±12.5 4.13

600

(TON = GND) 1.7 ±12.5 5.61

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

14 Maxim Integrated

light-load efficiency are made by varying the inductor

value. Generally, low inductor values produce a broad-

er efficiency vs. load curve, while higher values result in

higher full-load efficiency (assuming that the coil resis-

tance remains fixed) and less output voltage ripple.

Penalties for using higher inductor values include larger

physical size and degraded load-transient response,

especially at low input-voltage levels.

DC output accuracy specifications refer to the thresh-

old of the error comparator. When the inductor is in

continuous conduction, the MAX8550/MAX8551 regu-

late the valley of the output ripple, so the actual DC out-

put voltage is higher than the trip level by 50% of the

output ripple voltage. In discontinuous conduction

(SKIP = GND and ILOAD < ILOAD(SKIP)), the output volt-

age has a DC regulation level higher than the error-

comparator threshold by approximately 1.5% due to

slope compensation.

Forced-PWM Mode (

SKIP

= AVDD in

MAX8550 Only)

The low-noise forced-PWM mode (SKIP = AVDD) dis-

ables the zero-crossing comparator, which controls the

low-side switch on-time. This forces the low-side gate-

drive waveform to constantly be the complement of the

high-side gate-drive waveform, so the inductor current

reverses at light loads while DH maintains a duty factor

of VOUT / VIN. Forced-PWM mode keeps the switching

frequency fairly constant. However, forced-PWM opera-

tion comes at a cost where the no-load VDD bias cur-

rent remains between 2mA and 20mA due to the

external MOSFET’s gate charge and switching frequen-

cy. Forced-PWM mode is most useful for reducing

audio frequency noise, improving load-transient

response, and providing sink-current capability for

dynamic output-voltage adjustment.

Current-Limit Buck Regulator (ILIM)

Valley Current Limit

The current-limit circuit for the buck regulator portion of

the MAX8550/MAX8551 employs a unique “valley” cur-

rent-sensing algorithm that senses the voltage drop

across LX and PGND1 and uses the on-resistance of

the rectifying MOSFET (Q2 in the

Typical Applications

Circuit

, Figure 8) as the current-sensing element. If the

magnitude of the current-sense signal is above the val-

ley current-limit threshold, the PWM controller is not

allowed to initiate a new cycle (Figure 4). With valley

current-limit sensing, the actual peak current is greater

than the valley current-limit threshold by an amount

equal to the inductor current ripple. Therefore, the exact

current-limit characteristic and maximum load capability

are a function of the current-sense resistance, inductor

value, and input voltage. When combined with the

undervoltage-protection circuit, this current-limit method

is effective in almost every circumstance.

In forced-PWM mode, the MAX8550/MAX8551 also

implement a negative current limit to prevent excessive

reverse inductor currents when the buck regulator output

is sinking current. The negative current-limit threshold is

set to approximately 120% of the positive current limit

and tracks the positive current limit when VILIM is adjust-

ed. The current-limit threshold is adjusted with an exter-

nal resistor-divider at ILIM. A 2µA to 20µA divider current

is recommended for accuracy and noise immunity.

The current-limit threshold adjustment range is from

25mV to 200mV. In the adjustable mode, the current-

limit threshold voltage (from PGND1 to LX) is precisely

1/10th the voltage seen at ILIM. The threshold defaults

to 50mV when ILIM is connected to AVDD. The logic

threshold for switchover to the 50mV default value is

approximately AVDD - 1V.

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors do not corrupt the differ-

ential current-sense signals seen between LX and GND.

Figure 2. Pulse-Skipping/Discontinuous Crossover Point

INDUCTOR CURRENT

ON-TIME0 TIME

IPEAK

ILOAD = IPEAK / 2

∆I

∆t

VIN - VOUT

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

POR, UVLO, and Soft-Start

Internal power-on reset (POR) occurs when AVDD rises

above approximately 2V, resetting the fault latch and

the soft-start counter, powering up the reference, and

preparing the buck regulator for operation. Until AVDD

reaches 4.25V (typ), AVDD undervoltage-lockout

(UVLO) circuitry inhibits switching. The controller

inhibits switching by pulling DH low and holding DL low

when OVP and shutdown discharge are disabled

(OVP/UVP = REF or GND) or forcing DL high when OVP

and shutdown discharge are enabled (OVP/UVP =

AVDD or OPEN). See Table 3 for a detailed truth table

for OVP/UVP and shutdown settings. When AVDD rises

above 4.25V, the controller activates the buck regulator

and initializes the internal soft-start.

The buck regulator’s internal soft-start allows a gradual

increase of the current-limit level during startup to

reduce the input surge currents. The MAX8550/

MAX8551 divide the soft-start period into five phases.

During the first phase, the controller limits the current

limit to only 20% of the full current limit. If the output

does not reach regulation within 425µs, soft-start enters

the second phase, and the current limit is increased by

another 20%. This process repeats until the maximum

current limit is reached, after 1.7ms, or when the output

reaches the nominal regulation voltage, whichever

occurs first. Adding a capacitor in parallel with the

external ILIM resistors creates a continuously

adjustable analog soft-start function for the buck regu-

lator’s output.

Soft-start in the LDO section can be realized by con-

necting a capacitor between the SS pin and ground.

When SHDNB is driven low, or during thermal shut-

down of the LDOs, the SS capacitor is discharged.

When SHDNB is driven high or when the thermal limit is

removed, an internal 4µA (typ) current charges the SS

capacitor. The resulting ramp voltage on SS linearly

increases the current-limit comparator thresholds to

both the VTT and VTTR outputs, until full current limit is

Figure 4. Valley Current-Limit Threshold

INDUCTOR CURRENT

ILOAD

ILIMIT

0TIME

IPEAK

ILOAD(MAX)

ILIM(VAL) = 1 - x ILOAD

LIR

()

Figure 3. Adjustable Current-Limit Threshold

ILIM

TO PWM

CONTROLLER

(SEE FIGURE 1)

VDD - 1V

MAX8550/

MAX8551

1.0V

CREF

CILIM

REF

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

16 Maxim Integrated

attained when SS reaches approximately 1.6V. This

lowering of the current limit during startup limits the ini-

tial inrush current peaks, particularly when driving

capacitors. Choose the value of the SS cap appropri-

ately to set the soft-start time window. Leave SS floating

to disable the soft-start feature.

Power-OK (POK1)

POK1 is an open-drain output for a window comparator

that continuously monitors VOUT. POK1 is actively held

low when SHDNA is low and during the buck regulator

output’s soft-start. After the digital soft-start terminates,

POK1 becomes high impedance as long as the output

voltage is within ±10% of the nominal regulation voltage

set by FB. When VOUT drops 10% below or rises 10%

above the nominal regulation voltage, the MAX8550/

MAX8551 pull POK1 low. Any fault condition forces

POK1 low until the fault latch is cleared by toggling

SHDNA or cycling AVDD power below 1V. For logic-level

output voltages, connect an external pullup resistor

between POK1 and AVDD. A 100kΩresistor works well

in most applications. Note that the POK1 window detec-

tor is completely independent of the overvoltage and

undervoltage-protection fault detectors and the state of

VTTS and VTTR.

SHDNA

and Output Discharge

The SHDNA input corresponds to the buck regulator

and places the buck regulator’s portion of the IC in a

low-power mode (see the

Electrical Characteristics

table). SHDNA is also used to reset a fault signal such

as an overvoltage or undervoltage fault.

When output discharge is enabled, (OVP/UVP = AVDD

or open) and SHDNA and SHDNB are pulled low, or if

UVP is enabled (OVP/UVP = AVDD) and VOUT falls to

70% of its regulation set point, the MAX8550 dis-

charges the buck regulator output (through the OUT

input) through an internal 10Ωswitch to ground. While

the output is discharging, DL is forced low and the

PWM controller is disabled but the reference remains

active to provide an accurate threshold. Once the out-

put voltage drops below 0.3V, the MAX8550 shuts

down the reference and pulls DL high, effectively

clamping the buck output and LX to ground.

When output discharge is disabled (OVP/UVP = REF or

GND), the controller does not actively discharge the

buck output and the DL driver remains low. Under these

conditions, the buck output discharge rate is determined

by the load current and its output capacitance. The buck

regulator detects and latches the discharge-mode state

set by the OVP/UVP setting on startup.

For the MAX8551, the OVP/UVP is internally connected

to REF, which permanently enables the output dis-

charge feature (see Table 1).

SHDNB

and STBY

The SHDNB input corresponds to the VTT and VTTR

outputs, and when driven low, places the linear-regula-

tor portion of the IC in a low-power mode (see the

Electrical Characteristics

table). When SHDNB is pulled

low, VTT and VTTR are high impedance.

The STBY input is an active-high input that is used to

shut down only the VTT output. When STBY is high, VTT

is high impedance. The STBY input overrides the

SHDNB input, so even with SHDNB high, if STBY is

high, then the VTT output is inactive.

Power-OK (POK2)

POK2 is the open-drain output for a window compara-

tor that continuously monitors the VTTS input and VTTR

output. POK2 is pulled low when REFIN is less than

0.8V, or when SHDNB is pulled low. POK2 is high

impedance as long as the output voltage is within

±10% of the nominal regulation voltage as set by

REFIN. When VVTTS or VVTTR rises 10% above or 10%

below its nominal regulation voltage, the MAX8550/

MAX8551 pull POK2 low. For logic-level output volt-

ages, connect an external pullup resistor between

POK2 and AVDD. A 100kΩresistor works well in most

applications.

Table 2. Shutdown and Standby Control Logic

STBY SHDNA SHDNB BUCK OUTPUT VTT VTTR

GND AVDD AVDD ON ON ON

GND AVDD GND ON OFF OFF

AVDD AVDD AVDD ON OFF ON

GND GND AVDD OFF ON ON

GND GND GND OFF OFF OFF

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

Current Limit (LDO for VTT

and VTTR Buffer)

The VTT output is a linear regulator that regulates the

input (VTTI) to half the VREFIN voltage. The feedback

point for VTT is at the VTTS input (Figure 1). VTT is

capable of sinking and sourcing at least 1.5A of continu-

ous current and 3A peak current. The current limit for

VTT and VTTR is typically ±5A and ±40mA, respective-

ly. When the current limit for either output is reached,

the outputs regulate the current, not the voltage.

Fault Protection

The MAX8550/MAX8551 provide overvoltage/undervolt-

age fault protection in the buck controller. Select

OVP/UVP to enable and disable fault protection as

shown in Table 3. Once activated, the controller contin-

uously monitors the output for undervoltage and over-

voltage fault conditions.

Overvoltage Protection (OVP)

When the output voltage rises above 116% of the nomi-

nal regulation voltage (MAX8550 only) and OVP is

enabled (OVP/UVP = AVDD or open), the OVP circuit

sets the fault latch, shuts down the PWM controller, and

immediately pulls DH low and forces DL high. This

turns on the synchronous-rectifier MOSFET (Q2 in the

Typical Applications Circuit

of Figure 8) with a 100%

duty cycle, rapidly discharging the output capacitor

and clamping the output to ground. Note that immedi-

ately latching DL high can cause the output voltage to

go slightly negative due to energy stored in the output

LC circuit at the instant the OVP occurs. If the load can-

not tolerate a negative voltage, place a power Schottky

diode across the output to act as a reverse-polarity

clamp. Toggle SHDNA or cycle AVDD below 1V to clear

the fault latch and restart the controller. OVP is dis-

abled when OVP/UVP is connected to REF or GND (see

Table 3). OVP only applies to the buck output. The VTT

and VTTR outputs do not have overvoltage protection.

Undervoltage Protection (UVP)

When the output voltage drops below 70% of its regula-

tion voltage while UVP is enabled, the controller sets

the fault latch and begins the discharge mode (see the

Shutdown and Output Discharge

section). When the

output voltage drops to 0.3V, the synchronous rectifier

(Q2 in the

Typical Applications Circuit

) turns on and

clamps the buck output to GND. UVP is ignored for at

least 10ms (min) after startup or after a rising edge on

SHDNA. Toggle SHDNA or cycle AVDD power below 1V

to clear the fault latch and restart the controller. UVP is

disabled when OVP/UVP is left open or connected to

GND (see Table 3). UVP only applies to the buck out-

put. The VTT and VTTR outputs do not have undervolt-

age protection.

Thermal Fault Protection

The MAX8550/MAX8551 feature two thermal-fault-pro-

tection circuits. One monitors the buck-regulator por-

tion of the IC and the other monitors the linear regulator

(VTT) and the reference buffer output (VTTR). When the

junction temperature of the buck-regulator portion of

the MAX8550/MAX8551 rises above +160°C, a thermal

sensor activates the fault latch, pulls POK1 low, and

shuts down the buck-controller output using discharge

mode regardless of the OVP/UVP setting. Toggle

SHDNA or cycle AVDD below 1V to reactivate the con-

troller after the junction temperature cools by 15°C. If

the VTT and VTTR regulator portion of the IC has its die

temperature rise above +160°C, then VTT and VTTR

Table 3. OVP/UVP Fault Protection

OVP/UVP DISCHARGE UVP PROTECTION OVP PROTECTION

AVDD

Yes.

DL forced high when SHDNA and

SHDNB are low.

Enabled.

Discharge sequence activated. DL

forced high when shut down.

Enabled.

DH pulled low and DL forced high.

OPEN

Yes.

DL forced high when SHDNA and

SHDNB are low.

Disabled. Enabled.

DH pulled low and DL forced high.

REF No.

DL forced low when SHDNA is low.

Enabled.

Discharge sequence activated. DL

forced high when shut down.

Disabled.

GND No.

DL forced low when SHDNA is low. Disabled. Disabled.

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

18 Maxim Integrated

shut off, go high impedance, and restart after the die

portion of the IC cools by 15°C. Both thermal faults are

independent. For example, if the VTT output is over-

loaded to the point that it triggers its thermal fault, the

buck regulator continues to function.

Design Procedure

Firmly establish the input voltage range (VIN) and maxi-

mum load current (ILOAD) in the buck regulator before

choosing a switching frequency and inductor operating

point (ripple current ratio or LIR). The primary design

trade-off lies in choosing a good switching frequency

and inductor operating point, and the following four fac-

tors dictate the rest of the design:

• Input Voltage Range. The maximum value (VIN(MAX))

must accommodate the worst-case voltage. The mini-

mum value (VIN(MIN)) must account for the lowest

voltage after drops due to connectors and fuses. If

there is a choice, lower input voltages result in better

efficiency.

• Maximum Load Current. There are two values to con-

sider. The peak load current (IPEAK) determines the

instantaneous component stresses and filtering

requirements and thus drives output capacitor selec-

tion, inductor saturation rating, and the design of the

current-limit circuit. The continuous load current

(ILOAD) determines the thermal stresses and thus

drives the selection of input capacitors, MOSFETs,

and other critical heat-contributing components.

• Switching Frequency. This choice determines the

basic trade-off between size and efficiency. The opti-

mal frequency is largely a function of maximum input

voltage, due to MOSFET switching losses proportion-

al to frequency and VIN2. The optimum frequency is

also a moving target, due to rapid improvements in

MOSFET technology that are making higher frequen-

cies more practical.

• Inductor Operating Point. This choice provides trade-

offs: size vs. efficiency and transient response vs. out-

put ripple. Low inductor values provide better

transient response and smaller physical size but also

result in lower efficiency and higher output ripple due

to increased ripple currents. The minimum practical

inductor value is one that causes the circuit to operate

at the edge of critical conduction (where the inductor

current just touches zero with every cycle at maximum

load). Inductor values lower than this grant no further

size-reduction benefit. The optimum operating point is

usually found between 20% and 50% ripple current.

When pulse skipping (SKIP = low at light loads), the

inductor value also determines the load-current value

at which PFM/PWM switchover occurs.

Setting the Output Voltage (Buck)

Preset Output Voltages

The MAX8550/MAX8551s’ Dual-Mode operation allows

the selection of common voltages without requiring

external components (Figure 5). Connect FB to GND for

a fixed 2.5V output, to AVDD for a fixed 1.8V output, or

connect FB directly to OUT for a fixed 0.7V output.

Setting the Buck Regulator Output (V

OUT

) with a

Resistive Voltage-Divider at FB

The buck-regulator output voltage can be adjusted from

0.7V to 5.5V using a resistive voltage-divider (Figure 6).

The MAX8550/MAX8551 regulate FB to a fixed refer-

ence voltage (0.7V). The adjusted output voltage is:

where VFB is 0.7V, RCand RDare shown in Figure 6,

and VRIPPLE is:

Setting the VTT and VTTR Voltages (LDO)

The termination power-supply output (VTT) can be set by

two different methods. First, the VTT output can be con-

nected directly to the VTTS input to force VTT to regulate

to VREFIN / 2. Secondly, VTT can be forced to regulate

higher than VREFIN / 2 by connecting a resistive

V LIR I R

RIPPLE LOAD MAX ESR

=× ×

()

VVR

OUT FB C

RIPPLE

⎛

⎝

⎜⎞

⎠

⎟+12

Figure 5. Dual-Mode Feedback Decoder

MAX8550/

MAX8551

0.1V

2.5V

(FIXED)

1.8V

(FIXED)

ERROR

AMPLIFIER

REF (2.0V)

OUT

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

divider from VTT to VTTS. The maximum value for VTT

is VVTTI - VDROPOUT where VDROPOUT = IVTT ×0.3Ω

(max) at TA= +85°C.

The termination reference voltage (VTTR) tracks 1/2

VREFIN.

Inductor Selection (Buck)

The switching frequency and inductor operating point

determine the inductor value as follows:

For example: ILOAD(MAX) = 12A, VIN = 12V, VOUT =

2.5V, fSW = 600kHz, 30% ripple current or LIR = 0.3:

Find a low-loss inductor with the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered

iron is inexpensive and can work well at frequencies up

to 200kHz. The core must be large enough not to satu-

rate at the peak inductor current (IPEAK):

Most inductor manufacturers provide inductors in stan-

dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.

Also look for nonstandard values, which can provide a

better compromise in LIR across the input voltage range.

If using a swinging inductor (where the no-load induc-

tance decreases linearly with increasing current), evalu-

ate the LIR with properly scaled inductance values.

Input Capacitor Selection (Buck)

The input capacitor must meet the ripple current

requirement (IRMS) imposed by the switching currents:

IRMS has a maximum value of ILOAD / 2 when VIN = 2 ×

VOUT. For most applications, nontantalum capacitors

(ceramic, aluminum, POS, or OSCON) are preferred

due to their resistance to power-up surge currents typi-

cal of systems with a mechanical switch or connector in

series with the input. If the MAX8550/MAX8551 are

operated as the second stage of a two-stage power

conversion system, tantalum input capacitors are

acceptable. In either configuration, choose a capacitor

that has less than 10°C temperature rise at the RMS

input current for optimal reliability and lifetime.

Output Capacitor Selection (Buck)

The output filter capacitor must have low enough equiv-

alent series resistance (RESR) to meet output ripple and

load-transient requirements, yet have high enough ESR

to satisfy stability requirements.

For processor core voltage converters and other appli-

cations in which the output is subject to violent load

transients, the output capacitor’s size depends on how

much RESR is needed to prevent the output from dip-

ping too low under a load transient. Ignoring the sag

due to finite capacitance:

In applications without large and fast load transients,

the output capacitor’s size often depends on how much

RESR is needed to maintain an acceptable level of out-

put voltage ripple. The output ripple voltage of a step-

down controller is approximately equal to the total

inductor ripple current multiplied by the output capaci-

tor’s RESR. Therefore, the maximum RESR required to

meet ripple specifications is:

I LIR

ESR RIPPLE

LOAD MAX

()

≤×

ESR STEP

LOAD MAX

()

≤∆

VVV

RMS LOAD

OUT IN OUT

()

II LIR

PEAK LOAD MAX

()

⎛

⎝

⎜⎞

⎠

⎟

LVV

V kHz A H . (

=×××

≈

25 12

12 600 12 0 3 1

- 2.5V) µ

LVVV

V f I LIR

OUT IN OUT

IN SW LOAD MAX

()

×× ×

Figure 6. Setting VOUT with a Resistive Voltage-Divider

MAX8550/

MAX8551 DL

PGND1

GND

COUT

OUT

VOUT

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

20 Maxim Integrated

The actual capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. Thus, the

capacitor is usually selected by ESR and voltage rating

rather than by capacitance value (this is true of tanta-

lums, OSCONs, polymers, and other electrolytics).

When using low-capacity filter capacitors, such as

ceramic capacitors, size is usually determined by the

capacity needed to prevent VSAG and VSOAR from

causing problems during load transients. Generally,

once enough capacitance is added to meet the over-

shoot requirement, undershoot at the rising load edge

is no longer a problem (see the VSAG and VSOAR equa-

tions in the

Transient Response

section). However, low-

capacity filter capacitors typically have high-ESR zeros

that can affect the overall stability (see the

Stability

Requirements

section).

Stability Requirements

For Quick-PWM controllers, stability is determined by

the value of the ESR zero relative to the switching fre-

quency. The boundary of instability is given by the fol-

lowing equation:

If COUT consists of multiple same-value capacitors, as

in the

Typical Applications Circuit

of Figure 8, the fESR

remains the same as that of a single capacitor.

For a typical 600kHz application, the ESR zero frequen-

cy must be well below 190kHz, preferably below

100kHz. Two 150µF/4V Sanyo POS capacitors are used

to provide 12mΩ(max) of RESR. This results in a zero at

42kHz, well within the bounds of stability.

Do not put high-value ceramic capacitors directly

across the feedback sense point without taking precau-

tions to ensure stability. Large ceramic capacitors can

have a high-ESR zero frequency and cause erratic,

unstable operation. However, it is easy to add enough

series resistance by placing the capacitors a couple of

inches downstream from the feedback sense point,

which should be as close as possible to the inductor.

Unstable operation manifests itself in two related but

distinctly different ways: double pulsing and fast-feed-

back loop instability. Double pulsing occurs due to

noise on the output or because the ESR is so low that

there is not enough voltage ramp in the output voltage

signal. This “fools” the error comparator into triggering

a new cycle immediately after the 400ns minimum off-

time period has expired.

Double pulsing is more annoying than harmful, result-

ing in nothing worse than increased output ripple.

However, it can indicate the possible presence of loop

instability due to insufficient ESR. Loop instability can

result in oscillations at the output after line or load

steps. Such perturbations are usually damped but can

cause the output voltage to rise above or fall below the

tolerance limits. The easiest method for checking stabil-

ity is to apply a very fast zero-to-max load transient and

carefully observe the output-voltage-ripple envelope for

overshoot and ringing. It can help to simultaneously

monitor the inductor current with an AC current probe.

Do not allow more than one cycle of ringing after the

initial step-response under/overshoot.

VTT Output Capacitor Selection (LDO)

A minimum value of 60µF is needed to stabilize the VTT

output for load currents up to ±1.5A. This value of capaci-

tance limits the regulator’s unity-gain bandwidth frequen-

cy to about 700kHz (typ) to allow adequate phase margin

for stability. To keep the capacitor acting as a capacitor

within the regulator’s bandwidth, it is important that

ceramic caps with low ESR and ESL be used.

Since the gain bandwidth is also determined by the

transconductance of the output FETs, which increases

with load current, the output capacitor needs to be

greater than 60µF if the load current exceeds 1.5A, but

can be smaller than 60µF if the maximum load current

is less than 1.5A. As a rule, choose the minimum

capacitance and maximum ESR for the output capaci-

tor using the following:

RESR value is measured at the unity-gain-bandwidth

frequency given by approximately:

Once these conditions for stability are met, additional

capacitors including those of electrolytic and tantalum

types can be connected in parallel to the ceramic

capacitor (if desired) to further suppress noise or volt-

age ripple at the output.

GBW OUT

LOAD

=×

OUT MIN LOAD

ESR MAX LOAD

=×

60 15

515

Ω

where

fRC

ESR SW

ESR ESR OUT

≤

=××

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

VTTR Output Capacitor Selection (LDO)

The VTTR buffer is a scaled-down version of the VTT

regulator, with much smaller output transconductance.

Its compensation cap can therefore be smaller, and its

ESR larger, than what is required for its larger counter-

part. For typical applications requiring load current up

to ±20mA, a ceramic cap with a minimum value of 1µF

is recommended (RESR < 0.3Ω). Connect this cap

between VTTR and the analog ground plane.

VTTI Input Capacitor Selection (LDO)

Both the VTT and VTTR output stages are powered

from the same VTTI input. Their output voltages are ref-

erenced to the same REFIN input. The value of the VTTI

bypass capacitor is chosen to limit the amount of rip-

ple/noise at VTTI, or the amount of voltage dip during a

load transient. Typically VTTI is connected to the output

of the buck regulator, which already has a large bulk

capacitor. Nevertheless, a ceramic capacitor of at least

10µF must be used and must be added and placed as

close as possible to the VTTI pin. This value must be

increased with larger load current, or if the trace from

the VTTI pin to the power source is long and has signifi-

cant impedance. Furthermore, to prevent undesirable

VTTI bounce from coupling back to the REFIN input

and possibly causing instability in the loop, the REFIN

pin should ideally tap its signal from a separate low-

impedance DC source rather than directly from the

VTTI input. If the latter is unavoidable, increase the

amount of bypass capacitance at the VTTI input and

add additional bypass at the REFIN pin.

MOSFET Selection (Buck)

The MAX8550/MAX8551 drive external, logic-level, N-

channel MOSFETs as the circuit-switch elements. The

key selection parameters:

On-resistance (RDS(ON)): the lower, the better.

Maximum drain-to-source voltage (VDSS): should be

at least 20% higher than input supply rail at the high-

side MOSFET’s drain.

Gate charges (QG, QGD, QGS): the lower the better.

Choose MOSFETs with rated RDS(ON) at VGS = 4.5V.

For a good compromise between efficiency and cost,

choose the high-side MOSFET that has a conduction

loss equal to its switching loss at nominal input voltage

and maximum output current (see below). For the low-

side MOSFET, make sure that it does not spuriously

turn on because of dV/dt caused by the high-side

MOSFET turning on, as this results in shoot-through

current degrading efficiency. MOSFETs with a lower

QGD to QGS ratio have higher immunity to dV/dt.

For proper thermal-management design, calculate the

power dissipation at the desired maximum operating

junction temperature, maximum output current, and

worst-case input voltage. For the low-side MOSFET, the

worst case is at VIN(MAX). For the high-side MOSFET,

the worst case could be at either VIN(MIN) or VIN(MAX).

The high-side MOSFET and low-side MOSFET have dif-

ferent loss components due to the circuit operation.

The low-side MOSFET operates as a zero-voltage

switch; therefore, major losses are:

• The channel-conduction loss (PLSCC)

• The body-diode conduction loss (PLSDC)

• The gate-drive loss (PLSDR):

Use RDS(ON) at TJ(MAX):

where VFis the body-diode forward-voltage drop, tDT is

the dead time (≈30ns), and fSW is the switching fre-

quency. Because of the zero-voltage switch operation,

the low-side MOSFET gate-drive loss occurs as a result

of charging and discharging the input capacitance,

(CISS). This loss is distributed among the average DL

gate-driver’s pullup and pulldown resistance, RDL

(≈1Ω), and the internal gate resistance (RGATE) of the

MOSFET (≈2Ω). The drive power dissipated is given by:

The high-side MOSFET operates as a duty-cycle control

switch and has the following major losses:

• The channel-conduction loss (PHSCC)

• The VI overlapping switching loss (PHSSW)

• The drive loss (PHSDR)

(The high-side MOSFET does not have body-diode

conduction loss because the diode never conducts

current):

Use RDS(ON) at TJ(MAX):

()

VIR

HSCC OUT

IN LOAD DS ON

=× ×

PCVf R

LSDR ISS GS SW GATE

GATE DL

=× ×× +

PIVtf

LSDC LOAD F DT SW

=×××2

()

VIR

LSCC OUT

IN LOAD DS ON

=⎛

⎝

⎜⎞

⎠

⎟××12

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

22 Maxim Integrated

where IGATE is the average DH-driver output current

determined by:

where RDH is the high-side MOSFET driver’s on-resis-

tance (1Ωtyp) and RGATE is the internal gate resis-

tance of the MOSFET (≈2Ω):

where VGS = VDD = 5V. In addition to the losses above,

allow about 20% more for additional losses because of

MOSFET output capacitances and low-side MOSFET

body-diode reverse-recovery charge dissipated in the

high-side MOSFET that is not well defined in the

MOSFET data sheet. Refer to the MOSFET data sheet

for thermal-resistance specifications to calculate the PC

board area needed to maintain the desired maximum

operating junction temperature with the above-calculat-

ed power dissipations. To reduce EMI caused by

switching noise, add a 0.1µF ceramic capacitor from the

high-side switch drain to the low-side switch source, or

add resistors in series with DH and DL to slow down the

switching transitions. Adding series resistors increases

the power dissipation of the MOSFET, so ensure that

this does not overheat the MOSFET.

MOSFET Snubber Circuit (Buck)

Fast switching transitions cause ringing because of a

resonating circuit formed by the parasitic inductance

and capacitance at the switching nodes. This high-fre-

quency ringing occurs at LX’s rising and falling transi-

tions and can interfere with circuit performance and

generate EMI. To dampen this ringing, an optional

series RC snubber circuit is added across each switch.

Below is a simple procedure for selecting the value of

the series RC of the snubber circuit:

1) Connect a scope probe to measure VLX to PGND1,

and observe the ringing frequency, fR.

2) Estimate the circuit parasitic capacitance (CPAR) at

LX by first finding a capacitor value, which, when

connected from LX to PGND1, reduces the ringing

frequency by half. CPAR can then be calculated as

1/3rd the value of the capacitor value found.

3) Estimate the circuit parasitic capacitance (LPAR)

from the equation:

4) Calculate the resistor for critical dampening (RSNUB)

from the equation: RSNUB = 2π×fRx LPAR. Adjust

the resistor value up or down to tailor the desired

damping and the peak voltage excursion.

5) The capacitor (CSNUB) should be at least 2 to 4

times the value of CPAR to be effective.

The power loss of the snubber circuit (PRSNUB) is dissi-

pated in the resistor and can be calculated as:

where VIN is the input voltage and fSW is the switching

frequency. Choose an RSNUB power rating that meets

the specific application’s derating rule for the power

dissipation calculated.

Setting the Current Limit (Buck)

The current-sense method used in the MAX8550/

MAX8551 makes use of the on-resistance (RDS(ON)) of

the low-side MOSFET (Q2 in the

Typical Applications

Circuit

). When calculating the current limit, use the worst-

case maximum value for RDS(ON) from the MOSFET data

sheet, and add some margin for the rise in RDS(ON) with

temperature. A good general rule is to allow 0.5% addi-

tional resistance for each 1°C of temperature rise.

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

ley of the inductor current occurs at ILOAD(MAX) minus

half the ripple current; therefore:

where ILIM(VAL) equals the minimum valley current-limit

threshold voltage divided by the on-resistance of Q2

(RDS(ON)Q2). For the 50mV default setting, connect ILIM

to AVDD. In adjustable mode, the valley current-limit

threshold is precisely 1/10th* the voltage seen at ILIM.

For an adjustable threshold, connect a resistive divider

from REF to GND with ILIM connected to the center tap.

The external 250mV to 2V adjustment range corresponds

to a 25mV to 200mV valley current-limit threshold. When

adjusting the current limit, use 1% tolerance resistors and

II I LIR

LIM VAL LOAD MAX

LOAD MAX

() ( )

()

>×

⎛

⎝

⎜⎞

⎠

⎟

-2

PCVf

RSNUB SNUB IN SW

=××

PAR

R PAR

()

PQVf R

HSDR G GS SW GATE

GATE DH

=××× +

()

GATE ON DH GATE

PVIf

HSSW IN LOAD SW GS GD

GATE

=× ×× +

In the negative direction, the adjustable current limit is typically

-1/8th the voltage seen at ILIM.

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

a divider current of approximately 10µA to prevent signifi-

cant inaccuracy in the valley current-limit tolerance.

Foldback Current Limit

Alternately, foldback current limit can be implemented

if the UVP latch option is not available. Foldback cur-

rent limit reduces the power dissipation of external

components so they can withstand indefinite overload

and short circuit, with automatic recovery after the over-

load or short circuit is removed. To implement foldback

current limit, connect a resistor from VOUT to ILIM (R6

in Figure 7 and the

Typical Applications Circuit

), in

addition to the resistor-divider network (R4 and R5)

used for setting the adjustable current limit as shown in

Figure 7.

The following is a procedure for calculating the value of

R4, R5, and R6:

1) Calculate the voltage, VILIM(NOM), required at ILIM

when the output voltage is at nominal:

2) Pick a percentage of foldback, PFB, from 15%

to 40%.

3) Calculate the voltage, VILIM(0V), when the output is

shorted (0V):

4) The value for R4 can be calculated as:

5) The parallel combination of R5 and R6, denoted

R56, is calculated as:

6) Then R6 can be calculated as:

7) Then R5 is calculated as:

Boost-Supply Diode and

Capacitor Selection (Buck)

A low-current Schottky diode, such as the CMDSH-3

from Central Semiconductor, works well for most appli-

cations. Do not use large-power diodes, because high-

er junction capacitance can charge up the voltage at

BST to the LX voltage and this exceeds the absolute

maximum rating of 6V. The boost capacitor should be

0.1µF to 4.7µF, depending on the input and output volt-

ages, external components, and PC board layout. The

boost capacitance should be as large as possible to

prevent it from charging to excessive voltage, but small

enough to adequately charge during the minimum low-

side MOSFET conduction time, which happens at maxi-

mum operating duty cycle (this occurs at minimum

input voltage). In addition, ensure that the boost capac-

itor does not discharge to below the minimum gate-to-

source voltage required to keep the high-side MOSFET

RRR

5656

656

=×

RVRR

VV V R

VVR

OUT

OUT ILIM NOM ILIM V

ILIM NOM ILIM V

=××

()

−

()

⎡

⎣

⎢

⎤

⎦

⎥

() ()

4 5

-- 4-

AR56 2

=⎛

⎝

⎜⎞

⎠

⎟

µ- 4

RVV

ILIM V

= ()

VPV

ILIM V FB ILIM NOM() ( )

0=×

LIR

ILIM NOM LOAD MAX

DS ON Q

() ()

()

=× ×

⎛

⎝

⎜⎞

⎠

⎟

10 1

Figure 7. Foldback Current Limit

MAX8550/

MAX8551

REF

ILIM

GND

CREF

VOUT

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

24 Maxim Integrated

fully enhanced for lowest on-resistance. This minimum

gate-to-source voltage (VGS(MIN)) is determined by:

where VDD is 5V, QGis the total gate charge of the

high-side MOSFET, and CBOOST is the boost-capacitor

value where CBOOST is C7 in the

Typical Applications

Circuit

(Figure 8).

Transient Response (Buck)

The inductor ripple current also affects transient-

response performance, especially at low VIN - VOUT dif-

ferentials. Low inductor values allow the inductor

current to slew faster, replenishing charge removed

from the output filter capacitors by a sudden load step.

VVx

GS MIN DD G

BOOST

()

Figure 8. Typical Applications Circuit

MAX8550

REF

ILIM

GND

PGND1

VTTR

VDD

BST

VIN

AVDD

VTTI

VTT

POK

VIN (4.5V TO 28V)

2.5V

12A

VTT

1.25V

±1.5A

BIAS

SUPPLY

POK1

VTTR

1.25V

10mA

PGND2

REFIN

VTTS

OUT STBY

POK2

TON

OVP/UVP

IRF7821

N-CHANNEL

30V, 9mW

TOKO FDA1254-1R0M

1.0µH, 21A, 1.6mΩ

CMOSH-3

C11, C12 (150mF, 4V,

25mW, LOW-ESR POS

CAPACITOR (D2E)

SANYO 4TPE150M

IRF7832

N-CHANNEL

30V,5mW

10µF

60µF

1µF

100kΩ

187kΩ

41.2kΩ

20kΩ

100kΩ

3.9nF

C10

0.22µF

OFF

C11

150µF

C12

150µF

C13

1µF

0.22µF

4.7µF

10Ω

1µF

0.01µF

C14

470µF

(OPTIONAL)

SKIP

SHDNA

SHDNB

2 x 10µF

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

The output sag is also a function of the maximum duty

factor, which can be calculated from the on-time and

minimum off-time:

where tOFF(MIN) is the minimum off-time (see the

Electrical Characteristics

) and K is from Table 1.

The overshoot during a full-load to no-load transient

due to stored inductor energy can be calculated as:

Applications Information

Dropout Performance (Buck)

The output-voltage adjustable range for continuous-

conduction operation is restricted by the nonadjustable

minimum off-time one-shot. For best dropout perfor-

mance, use the slower (200kHz) on-time setting. When

working with low input voltages, the duty-factor limit

must be calculated using worst-case values for on- and

off-times. Manufacturing tolerances and internal propa-

gation delays introduce an error to the TON K-factor.

This error is greater at higher frequencies (see Table

1). Also, keep in mind that transient-response perfor-

mance of buck regulators operated too close to

dropout is poor, and bulk output capacitance must

often be added (see the VSAG equation in the

Design

Procedure

section).

The absolute point of dropout is when the inductor cur-

rent ramps down during the minimum off-time (∆IDOWN)

as much as it ramps up during the on-time (∆IUP). The

ratio h = ∆IUP / ∆IDOWN indicates the controller’s ability

to slew the inductor current higher in response to

increased load, and must always be greater than 1. As

h approaches 1, the absolute minimum dropout point,

the inductor current cannot increase as much during

each switching cycle, and VSAG greatly increases,

unless additional output capacitance is used.

A reasonable minimum value for h is 1.5, but adjusting

this up or down allows trade-offs between VSAG, output

capacitance, and minimum operating voltage. For a

given value of h, the minimum operating voltage can be

calculated as:

where VDROP1 and VDROP2 are the parasitic voltage

drops in the discharge and charge paths (

see the On-

Time One-Shot (TON)

section), tOFF(MIN) is from the

Electrical Characteristics

, and K is taken from Table 1.

The absolute minimum input voltage is calculated with

h = 1.

If the calculated VIN(MIN) is greater than the required

minimum input voltage, then the operating frequency

must be reduced or output capacitance added to

obtain an acceptable VSAG. If operation near dropout is

anticipated, calculate VSAG to be sure of adequate

transient response.

A dropout design example follows:

VOUT = 2.5V

fSW = 600kHz

K = 1.7µs

tOFF(MIN) = 450ns

VDROP1 = VDROP2 = 100mV

h = 1.5

Voltage Positioning (Buck)

In applications where fast-load transients occur, the

output voltage changes instantly by RESR ×COUT ×

∆ILOAD. Voltage positioning allows the use of fewer out-

put capacitors for such applications, and maximizes

the output-voltage AC and DC tolerance window in

tight-tolerance applications.

Figure 9 shows the connection of OUT and FB in a volt-

age-positioned circuit. In nonvoltage-positioned cir-

cuits, the MAX8550/MAX8551 regulate at the output

capacitor. In voltage-positioned circuits, the MAX8550/

MAX8551 regulate on the inductor side of the voltage-

positioning resistor. VOUT is reduced to:

VV RI

OUT VPS OUT NO LOAD POS LOAD() (_ )

=× -

VVV

Vns

VV V

IN MIN()

. .

. . .=+

⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

25 01

11 5 450

01 01 43

VVV

IN MIN OUT DROP

OFF MIN DROP DROP() ()

=×

⎛

⎝

⎜⎞

⎠

⎟

⎡

⎣

⎢

⎤

⎦

⎥

121

VIL

SOAR

LOAD MAX

OUT OUT

=×

××

()

∆2

LI VK

VV K

SAG

LOAD MAX OUT

IN OFF MIN

OUT OUT IN OUT

IN OFF MIN

××+

⎡

⎣

⎢⎤

⎦

⎥

()

×+

⎡

⎣

⎢

⎤

⎦

⎥

() ()

()

∆2

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

26 Maxim Integrated

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board, with their ground terminals flush

against one another. Follow these guidelines for good

PC board layout:

• Keep the high-current paths short, especially at the

ground terminals. This practice is essential for sta-

ble, jitter-free operation.

• Keep the power traces and load connections short.

This practice is essential for high efficiency. Using

thick copper PC boards (2oz vs. 1oz) can enhance

full-load efficiency by 1% or more. Correctly routing

PC board traces is a difficult task that must be

approached in terms of fractions of centimeters,

where a single mΩof excess trace resistance caus-

es a measurable efficiency penalty.

• The LX and PGND1 connections to the low-side

MOSFET for current sensing must be made using

Kelvin-sense connections.

• When trade-offs in trace lengths must be made, it is

preferable to allow the inductor-charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-

side MOSFET or between the inductor and the out-

put filter capacitor.

• Route high-speed switching nodes (BST, LX, DH,

and DL) away from sensitive analog areas (REF, FB,

and ILIM).

• Input ceramic capacitors must be placed as close

as possible to the high-side MOSFET drain and the

low-side MOSFET source. Position the MOSFETs so

the impedance between the input capacitor termi-

nals and the MOSFETs is as low as possible.

Special Layout Considerations for LDO Section

The capacitor (or capacitors) at VTT should be placed

as close to VTT and PGND2 (pins 12 and 11) as possi-

ble to minimize the series resistance/inductance of the

trace. The PGND2 side of the capacitor must be short

with a low-impedance path to the exposed pad under-

neath the IC. The exposed pad must be star-connected

to GND (pin 24), PGND1 (pin 23), and PGND2 (pin 11).

A narrower trace can be used to connect the output

voltage on the VTT side of the capacitor back to VTTS

(pin 9). However, keep this trace well away from poten-

tially noisy signals such as PGND1 or PGND2. This

prevents noise from being injected into the error ampli-

fier’s input. For best performance, the VTTI bypass

capacitor must be placed as close to VTTI (pin 13) as

possible. REFIN (pin 14) should be separately routed

with a clean trace and adequately bypassed to GND.

Refer to the MAX8550 evaluation kit data sheet for PC

board guidelines.

Figure 9. Voltage-Positioned Output

MAX8550/

MAX8551

VIN

RPOS

FB OUT

PGND1

BST

GND

VOLTAGE-

POSITIONED

OUTPUT

VDD

AVDD

+5V BIAS

SUPPLY

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Maxim Integrated

MAX8550/

MAX8551

REF

ILIM

GND

PGND1

VTTR

VDD

BST

VIN

AVDD

VTTI

VTT

POK

VIN (4.5V TO 28V)

1.8V - 2.5V / 12A

VTT

0.9V - 1.25V / 1.5A

BIAS

SUPPLY

POK1

VTTR

0.9V - 1.25V / 10mA

PGND2

REFIN

VTTS

OUT STBY

POK2

TON

OVP/UVP

Q2 L1

C10

OFF

C11

10Ω

1µF

0.01µF

SKIP

SHDNA

SHDNB

Typical Operating Circuit

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

28 Maxim Integrated

Package Information

For the latest package outline information and land patterns (foot-

prints), go to www.maximintegrated.com/packages. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE OUTLINE NO. LAND

PATTERN NO.

28 TQFN-EP T2855-6 21-0140 90-0026

Chip Information

PROCESS: BiCMOS

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent

licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and

max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________

MAX8550/MAX8551

Integrated DDR Power-Supply Solutions for

Desktops, Notebooks, and Graphic Cards

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

3 4/13 Added MAX8551ETI+ to Ordering Information 1

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Maxim Integrated:

MAX8550ETI+ MAX8550ETI+T