$= XILINX Spartan and Spartan-XL Families Field Programmable Gate Arrays November 25, 1997 (Version 0.6) Advance Product Specification introduction The Spartan Series is the first high-volume production FPGA solution to deliver all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, Core Solutions and prices that, in high volume, approach and in many cases are equivalent to mask programmed ASIC devices, The Spartan series is the result of more than thirteen years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan feature set, leveraging advanced hybrid process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan Series currently has 10 members, as shown in Table 1. Spartan Series Features Note: The Spartan series devices described in this data sheet include the Spartan family of devices and the Spartan-XL family of devices. Next generation ASIC replacement technology - First ASIC replacement FPGA for high-volume production with on-chip RAM - Advanced Ultradense 0.35um/0.50um process - Density up to 1862 logic cells or 40,000 system gates - Streamlined feature set based on XC4000 architecture - System performance beyond 80 MHz - Broad set of AllianceCORE and LogiCORE solutions available - Unlimited reprogrammability System level features - Available in both 5.0 Volt and 3.3 Volt versions - On-chip Select-RAM memory - Fully PCI compliant - Low power segmented routing architecture - Full readback capability for program verification and internal node observability - Dedicated high-speed carry logic ~ internal 3-state bus capability - 8 global low-skew clock or signal distribution networks - EEE 1149.1-compatibie boundary scan logic support * Versatile I/O and packaging - Low cost plastic packages available in all densities - Footprint compatibility in common packages across all Spartan and Spartan-XL devices - Individually programmable output slew-rate control maximizes performance and reduces noise - Hold time of 0.0 ns for input registers simplifies system timing 12-mA sink current per output . Fully supported by powerful Xilinx development system - Foundation series: Fully integrated, shrink-wrap software - Alliance series: Over 100 PC and engineering workstation 32 party development systems supported - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Tabie 1: Spartan and Spartan-XL Series Field Programmable Gate Arrays Max | Typical Number Logic System Gate Range CLB Total of Max. Device Cells Gates (Logic and RAM)* Matrix CLBs Flip-Flops | User /O XCS05 & XCSOS5XL 238 5,000 2,000 - 5,000 10x10 100 360 80 XCS10 & XCS10XL 466 10,000 3,000 - 10,000 14x 14 196 616 112 XCS20 & XCS20XL 950 20,000 7,000 - 20,000 20 x 20 400 1,120 160 XCS30 & XCS3OXL | 1368 30,000 10,000 - 30,000 24x 24 576 | 1,536 192 XCS40 & XCS40XL | 1862 40,000 13,000- 40,000 | 28x28 784 | 2,016 224 * Max values of Typical Gate Range include 20-30% of CLBs used as RAM. November 25, 1997 (Version 0.6) 4-173Spartan and Spartan-XL Families Field Programmable Gate Arrays General Overview Spartan Series FPGAs are implemented with a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur- rounded by a perimeter of programmable Input/Output Biocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter- connect patterns. The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi- ble an unlimited number of times. The values stored in these memory cells determine the logic functions and inter- connections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode). Spartan FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month. Spartan Series devices achieve high-performance, low- cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. in contrast to other FPGA devices, Spartan offers the most cost-effective solu- tion while maintaining leading-edge performance. In addi- tion to the conventional benefit of high volume programmable logic solutions Spartan also offers on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features. The Spartan Series leverages the highly successful XC4000 architecture with many of that familys features and benefits. Technology advancements have been derived from the XC4000XL and XC4000XV process develop- ments. B- SCAI mr) ELE : ct I ct Ct ioBl |. Coa] joe Chast Cas f} Ppas fl) Poel tos fest] Tt J LEY Ut Tt = Th Ci io oe (OB po Tos Ic Mos) Clos tl Cleef) Posh fled foal TI Ti Ti t Tica] . ~: Routing Channels : tt Ci Ht T ios 108 [eels Plast) fJaef} last os | [eel Ct I I i cr. do ct To 1OB i08] feeb cpl) Tlasf). flab ll Cpa ft fio] rm mp mod ieee " 108 : =a Lat TH Tt i RDBK -UP VersaRing Routing Channel Poo Rev20 | Figure 1: Basic FPGA Block Diagram 4-174 November 25, 1997 (Version 0.6)Logic Functional Description The Spartan Series uses a standard FPGA structure as shown in Figure 1. The FPGA consists of an array of config- urable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels. CLBs provide the functional elements for implementing the user's logic. * 1OBs provide the interface between the package pins and internal signal lines. Routing channels provide paths to interconnect the inputs and outputs of the CLBs and lOBs. The functionality of each circuit block is customized during configuration by programming internal static memory ceils. The values stored in these memory ceils determine the logic functions and interconnections implemented in the FPGA. Configurable Logic Blocks (CLBs) The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli- $< XILINX fied block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description on page 4-183. Function Generators Two 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer- ing unrestricted logic implementation of any Boolean func- tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented. A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box A of Figure 2). These inputs can come from the F-LUT or G- LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, imple- ment certain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbitrarily defined Boolean function of five inputs. B | G-LUT N |g ~ G4 a4 | | SR . D Qr- YQ Logic G3 G3 Function i G G of TT @ | cK 2 G2 G1-G4 Y/ EC G1 G1 | ! H-LUT | N | Y $4) Psa] i ns A Ht | " ot Y FG,H1 pin @L\ | | x | | Fa lF4 | | SR Logic | A D Qr xa F3 F3 Function _ | cK r2tro vee | Te) f | e EC F1 F1 | \ | F-LUT x Multiplexer Controlied \/ K TO by Configuration Program __. EC Rev 1.6 Figure 2: Spartan Simplified CLB Logic Diagram (some features not shown) November 25, 1997 (Version 0.6) 4-175Spartan and Spartan-XL Families Field Programmable Gate Arrays A CLB can be used to implement any of the following func- tions: * Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables * Any single function of five variables * Any function of four variables together with some functions of six variables Some functions of up to nine variables. Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software fools can deal with each function generator independently. This flexibility improves cell usage. Flip-Flops Each CLB contains two flip-flops that can be used to regis- ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip- flop via the H-LUT with a slight additional delay. The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS on page 4-189. Functionality of the flip-flop is described in Table 2. Table 2: CLB Flip-Flop Functionality Mode cK EC SR D Q Power-Up or : GSR Xx x x SR X X 1 x SR Flip-Flop || / 1". 0" D D Operation oO xX o* x Q x 0 0* x Q Legend: x Dont care {7 Rising edge (clock not inverted) SR Set or Reset value. Reset is default. 0" Input is Low or unconnected (default value) 1" Input is High or unconnected (default value) Ciock Input Each flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops. However, the clock is individually invertible for each flip-flop GSR Multiplexer Controlled by Configuration Program Figure 3: CLB Flip-Flop Functional Block Diagram (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock Enable The clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left dis- connected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device. Set/Reset The set/reset line (SR) is an asynchronous active High con- trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SRis not specified for a flip-flop the set/reset for that flip- flop defaults to the inactive state. SR is not invertible within the CLB. CLB Signal Flow Control In addition to the H-LUT input control multiplexers (shown in box A of Figure 2) there are signal flow control multi- plexers (shown in box B of Figure 2) which select the sig- nals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y). 1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB. 4-176 November 25, 1997 (Version 0.6)Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source. Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X out- put can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT. Controi Signals There are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig- nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1 - C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals. The four internal control signais are: * EC - Enable Clock * SR - Asynchronous Set/Reset or H function generator Input * DIN - Direct tn or H function generator Input * 1-H function generator Input 1. Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each !O0B controls one package pin and can be con- $< XILINX DIN Hi ci @ : c2 + SR c3 -@ @ C4 oj ; Ec Multiplexer Controlled Rev by Configuration Program Figure 4: CLB Control Signal Interface figured for input, output, or bidirectional signals. Figure 5 shows a simplified functional block diagram of the Spartan JOB. OUTPUT DRIVER CO Programmable Slew Rate OK a Programmabie TTL/CMOS Drive | | EC 4 a Package ? 1 | rT INPUT BUFFER | 3 l2 | . D Q Programmable Pull-Up/ |_| | kK CK Pull-Down Network EC e EC Multiplexer Controlled by Configuration Program _Rav it Figure 5: Simplified Spartan |OB Block Diagram November 25, 1997 (Version 0.6) 4-177Spartan and Spartan-XL Families Field Programmable Gate Arrays 1OB Input Signal Path The input signal to the (OB can be configured to either go directly to the routing channels (via 11 and [2 in Figure 5) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Tabie 3, and a simplified block diagram of the register can be seen in Figure 6. Table 3: Input Register Functionality Mode CK EC D Q Power-Up or X x Xx SR GSR Flip-Flop _f- 17 D D : 0 x Xx Q Latch 1 1" X Q 0 1* D D Both x 0 X Qs Legend: Xx Don't care _f- Rising edge (clock not inverted) SR Set or Reset value. Reset is default. 0" Input is Low or unconnected (default value) 1 Input is High or unconnected (default value) The register choice is made by placing the appropriate library symbol. For exarnple, IFD is the basic input flip-flop {rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure 6 on the CK line. R | RD eC Vee || i Lo Ct! 1) Multiplexer Controlled by Configuration Program Figure 6: !OB Flip-Flop/Latch Functional Block Diagram The Spartan |OB data input path has a one-tap delay ele- ment: either the delay is inserted (default), or it is not. The added delay guarantees a zero hold time with respect to clocks routed through any of the Spartan global clock buff- ers. (See Global Nets and Buffers on page 4-182 for a description of the global clock buffers in the Spartan Series.) For a shorter input register setup time, with positive nold-time, attach a NODELAY attribute or property to the flip-flop. The output of the input register goes to the routing chan- nels (via 11 and 2 in Figure 5). The 11 and [2 signals that exit the [OB can each carry either the direct or registered input signal. The Spartan input buffers can be globally configured for either TTL (1.2 V) or CMOS (0.5 Vcc) thresholds, using an option in the bitstream generation software. The inputs of Spartan devices can be driven by the outputs of any 3.3 V device, if the Spartan inputs are in TTL mode. There is a slight input hysteresis of about 300 mV. Inputs on the Spar- tan-XL are TTL compatible and 3.3 V CMOS compatible. The Spartan output levels are also configurable; the two giobal adjustments of input threshold and output level are independent. Supported sources for Spartan Series device inputs are shown in Table 4. Table 4: Supported Sources for Spartan Series Device Inputs Spartan Spartan-XL | Inputs Inputs Source 5.0V, | 5.0V, 33V0 | TTL CMOS!) CMOS | Any device, Vcc = 3.3 V, J , : CMOS outputs : , Spartan Series, Vec=5V,) | Unreli TTL outputs ~able . poe nmenfe new Data Any device, Vcc = 5 V, vo J TTL outputs (Voh < 3.7 V} Any device, Vec = 5 V, J V V CMOS outputs The I/Os on the Spartan-XL are fully 5 V tolerant even though the Vcc is 3.3 volts. This allows 5 V signals to directly connect to the Spartan-XL inputs without damage, as shown in Table 4. In addition, the 3.3 volt Vcc can be applied before or after 5 volt signals are applied to the I/Os. This makes the Spartan-XL immune to power supply sequencing problems. 10B Output Signal Path Output signals can be optionally inverted within the 10B, and can pass directly to the output buffer or be stored in an 4-178 November 25, 1997 (Version 0.6)edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in Table 5. Table 5: Output Flip-Flop Functionality $= XILINX Table 6: Supported Destinations for Spartan Series Outputs Spartan-XL Spartan Outputs Outputs Destination 3.3 V, 5.0V, | 5.0V, CMOS TTL | CMOS Any device, Vcc = 3.3 V| V | some! CMOS-threshold inputs Any device, Vec = 5.0 V, y voy Nv TTL-threshold inputs Any device, Vec=5V, | sUnreliable y CMOS-threshold inputs Data Clock Mode Clock Enable T D Q - Power-Up x x o* X SR /or GSR x 0 0* x Q | Flip-Flop ! 1" 0 DD. x x 1 x Zz i 0 x o* xX Q Legend: xX Dont care _! Rising edge (clock not inverted) SR Set or Reset value. Reset is default. 0 Input is Low or unconnected (default value) 1* Input is High or unconnected (default value) zZ 3-state Output Buffer An active-High 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional /O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each !OB (see Figure 5). By default, a Spartan device output buffer puil-up structure is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshald below Vcc. Alternatively, the outputs can be globally configured as CMOS drivers, with addi- tional p-channel pull-up transistors pulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. ft is not individually pro- grammabie. in a Spartan-XL device, all outputs are configured as CMOS drivers, therefore driving rail-to-rail. Any Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3 V device. (For a detailed discussion of how to interface between 5.0 V and 3.3 V devices, see the 3V Products section of The Pro- grammable Logic Data Book.) Supported destinations for Spartan Series device outputs are shown in Tabie 6. Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. 1. Only if destination device has 5-V tolerant inputs Spartan Series devices have a feature called Soft Start- up, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter- mined by the individual configuration option for each IOB. Pull-up and Pull-down Network Programmable pull-up and pull-down resistors are used for tying unused pins to Vcc or Ground to minimize power con- sumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to Vcc. The configurable pull-down resistor is an n-channel transis- tor that pulls to Ground. The value of these resistors is typ- ically 20 kQ 100 kQ (see specifications section). This high value makes them unsuitable as wired-AND pull-up resistors. After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are configured with the internal pull-up resis- tor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull- up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Set/Reset As with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user- controlled set/reset signal is available to the 1/O flip-flops (see Figure 6). The choice of set or reset applies to both the November 25, 1997 (Version 0.6) 4-179Spartan and Spartan-XL Families Field Programmable Gate Arrays initial state of the flip-flop and the response to the GSR pulse. Independent Clocks Separate clock signals are provided for the input (1K) and output (OK) flip-flops. The clock can be independently inverted for each flip-tiop within the IOB, generating either falling-edge or rising-edge triggered flip-flops. The clock inputs for each 1OB are independent. Common Clock Enables The input and output flip-flops in each IOB have a common clock enable input (EC), which through configuration, can be activated individually (see EC signal in Figure 6) for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan Series CLB. It cannot be inverted within the JOB. Routing Channel Description All internal routing charinels are composed of metal seg- ments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing channels is provided to achieve efficient automated routing. ad WH 8 Singles 2 Doubles 3 Longs This section describes the routing channels available in Spartan series devices. Figure 7 shows a general block diagram of the CLB routing channels. The impiementation software automatically assigns the appropriate resources based on the density and timing requirements of the design. The following description of the routing channels is for information only and is simplified with some minor details omitted. For an exact interconnect description the designer should open a design in the EPIC design editor and review the actual connections in this tool. The routing channels will be discussed as follows: CLB routing channels which run along each row and column of the CLB array. * JOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels. * Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals. 8 Singles > 3 Longs 2 Doubles aavad Rev 1.4 3 Longs 2 Doubles Figure 7: Spartan Series CLB Routing Channels and Interface Block Diagram 4-180 November 25, 1997 (Version 0.6)CLB Routing Channels The routing channels around the CLB are derived from three types of interconnects; single-length, double-length, and longlines. At the intersection of each vertical and hori- zontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 7 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersec- tions. CLB interface A block diagram of the CLB interface signals is shown in Figure 8. The input signals to the CLB are distributed a > t+ zt 3 & CIN COUT Gl C1 Fi nN nN N g ue oO Figure 8: CLB Interconnect Signals Figure 9: Programmable Switch Matrix $2 XILINX evenly on all four sides providing maximum routing flexibil- ity. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and rout- ing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing conges- tion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as 4 single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated interconnects which do not interfere with the general rout- ing structure. The output signals frorn the CLB are available to drive both vertical and horizontal channeis. Programmable Switch Matrices The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transis- tors used to establish connections between the lines (see Figure 9). For example, a single-length signa! entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou- ble-length signal can be routed to a double-iength line on any or all of the other three edges of the programmable switch matrix. Single-Length Lines Single-length lines provide the greatest interconnect flexi- bility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switch- ing matrices that are located in every row and column of CLBs. Se Six Pass Transistors Per Switch Matrix Interconnect Point November 25, 1997 (Version 0.6) 4-181Spartan and Spartan-XL Families Field Programmable Gate Arrays Single-length lines are connected by way of the program- mable switch matrices, as shown in Figure 9. Routing con- nectivity is shown in Figure 7. Single-length tines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct sig- nals within a localized area and to provide the branching for nets with fanout greater than one. Double-Length Lines The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a PSM. Double-length lines are grouped in pairs with the PSMs staggered, so that each line goes through a PSM at every other row or column of CLBs (see Figure 7). There are four vertical and four horizontal doubie-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing flexibility. Longlines Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. Each Spartan series longline has a programmable splitter switch at its center. This switch can separate the line into 108 1oB [a] BUGS gS! 5 # 2 2 PGCKi L}-D Lj SGCK1 oy ! locals | of } . locais i im : a Any BUFGS 5 + _! os . roses | One BUFGP | 108 per Global Lina + moe q locals | i cls] sures /\ i Oj PGCK2 pa SGCKe _ > 2 i BUF SP 8 3 a qo. {OB |OB Figure 10: Spartan Series Global Net Distribution two independent routing channels, each running half the width or height of the array. Routing connectivity of the longlines is shown in Figure 7. The longlines also interface to some 3-state buffers which is described later in 3-State Long Line Drivers on page 4-188. VO Routing Spartan series devices have additional routing around the IOB ring. This routing is cailed a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines, and four longlines. Global Nets and Buffers The Spartan series devices have dedicated global net- works. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard intercon- nect. The four global lines can be driven by either of two types of global buffers; Primary Global buffers (BUFGP) or Secondary Global buffers (BUFGS). Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 10. The clock pins of every CLB and IOB can also be sourced from local interconnect. iOB iOS A . PGCK4 | 4 . It BUFGS 4 _ V Ld 108 ocais locals BUFGP locas: eat {[y rt a i | locals Zt} Any BUFGS ja] xa oa , h Ef One BUFGP - | ces 4 per Global Line i +] iOB (| tocais, t | BUFGP SGCK3 aoe - Pa we <}t "7 CKS 1g BUFGS =e oy co 8608 4-182 November 25, 1997 (Version 0.6)The four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to poten- tially heavier loading, but offer greater flexibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semi- dedicated pads (PGCK1-4). The Secondary Global buffers can be sourced by either semi-dedicated pads (SGCK1-4) or internal nets. Each corner of the device has one Primary buffer and one Secondary buffer. Using the library symbol called BUFG results in the soft- ware choosing the appropriate clock buffer, based on the timing requirements of the design. A global buffer should be specified for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. Advanced Features Description Distributed RAM Optional modes for each CLB allow the function generators (F-LUT and G-LUT) to be used as Random Access Mem- ory (RAM). Read and write operations are significantly faster for this on-chip RAM than for off-chip implementations. This speed advantage is due to the relatively short signal propagation delays within the FPGA. Memory Configuration Overview There are two available memory configuration modes: sin- gle-port RAM and dual-port RAM. For both these modes, write operations are synchronous (edge-triggered), while read operations are asynchronous. In the Single-Port Mode, a single CLB can be configured as either a 16 x 1, (16 x 1) x 2 or 32 x 1 RAM array. In the Dual-Port mode, a single CLB can be configured only as one 16 x 1 RAM array. The different CLB memory configurations are sum- marized in Table 7, Any of these possibilities can be individ- ually programmed into a Spartan Series CLB. The 16 x 1 Single-Port configuration contains a RAM array with 16 locations, each one-bit wide. One 4-bit address decoder determines the RAM location for write and read operations. There is one input for writing data and one output for reading data, all at the selected address. The (16 x 1) x 2 Single-Port configuration combines two 16 x 1 Single Port configurations (each according to the preceding description). There is one data input, one data output and one address decoder for each array. These arrays can be addressed independently. $= XILINX * The 32 x 1 Singte-Port configuration contains a RAM array with 32 locations, each one-bit wide. There is one data input, one data output, and one 5-bit address decoder. * The Dual Port mode 16 x 1 configuration contains a RAM array with 16 locations, each one-bit wide. There are two 4-bit address decoders, one for each port. One port consists of an input for writing and an output for reading, all at a selected address. The other port consists of one output for reading from an independently selected address. Table 7: CLB Memory Configurations Mode 16x1 (16x1)x2 32x1 Single-Port Vv V Dual-Port v : The appropriate choice of RAM configuration mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Selection criteria include the following: Whereas the 32 x 1 Single-Port, the (16 x 1) x 2 Single-Port and the 16 x 1 Dual-Port configurations each use one entire CLB, the 16 x 1 Single-Port configuration uses only one half of a CLB. Due to its simultaneous read/write capability, the Dual-Port RAM can transfer twice as much data as the Sin- gle-Port RAM, which permits only one data operation at any given time. CLB memory configuration options are selected by using the appropriate library symbol in the design entry. Single-Port Mode There are three CLB memory configurations for the Single- Port RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional organization of which is shawn in Figure 11. The Single-Port RAM signais and the CLB signals (Figure 2 on page 4-175) from which they are originally derived are shown in Table 8. Table 8: Singie-Port RAM Signais November 25, 1997 (Version 0.6) RAM Signal Function CLB Signal! 'D Data in DIN or Hy : A[3:0} Address F,-F4 or Gy-Gy | Ag (32 x 1 only)) Address H, | WE Write Enable SR i WCLK Clock K SPO Single Port Out Four or Gout (Data Out) | 4-183Spartan and Spartan-XL Families Field Programmable Gate Arrays Aln-1:0] WRITE ROW SELECT WE INPUT REGISTER Dg or Dy WCLK Figure 11: Logic Diagram for the Single-Port RAM 16x1 32 x1 RAM ARRAY READ ROW SELECT SPO NOTE: 1. The (16 x 1) x 2 configuration combines two 16 x 1 Single Port RAMs, each with its own independent address bus and data input. The same WE and WCLK signals are connected to both RAMs. 2. m= 4 for the 16 x 1 and (16 x 1) x 2 configurations. n = 5 for the 32 x 1 configuration Writing data to the Singie-Part RAM is essentiaily the same as writing to a data register. It is an edge-triggered (syn- chronous) operation performed by applying an address to the A inputs and data tc the D input during the active edge of WCLK while WE is High. The timing relationships are shown in Figure 12. The High logic level on WE enables the input data register for writing. The active edge of WCLK latches the address, input data, and WE signals. Then, an internal write pulse is generated that loads the data into the memory cell. WCLK (K) WE DATA IN ADDRESS DATA OUT X6461 Data Write and Access Timing for RAM Figure 12: WCLK can be configured as active on either the rising edge (default) or the falling edge. While the WCLK input to the RAM accepts the same signal as the clock input to the associated CLBs flip-flops, the sense of this WCLK input can be inverted with respect to the sense of the flip-flop clock inputs. Consequently, within the same CLB, data at the RAM's SPO line can be stored in a flip-flop with either the same or the inverse clock polarity used to write data to the RAM. The WE input is active-High and cannot be inverted within the CLB. Allowing for settling time, the data on the SPO output reflects the contents of the RAM location currently addressed. When the address changes, following the asyn- chronous delay Tyo, the data stored at the new address location will appear on SPO. If the data at a particular RAM address is overwritten, after the delay Twos, the new data will appear on SPO. Dual-Port Mode In dual-port mode, the function generators (F-LUT and G- LUT) are used to create a 16 x 1 Duai-Port memory. Of the two data ports available, one permits read and write opera- tions at the address specified by A[3:0] while the second provides only for read operations at the address specified independently by DPRA[3:0]. As a result, simultaneous read/write operations at different addresses (or even at the same address) are supported. The functional organization of the 16 x 1 Dual-Port RAM is shown in Figure 13. 4-184 November 25, 1997 (Version 0.6)AI3:0] WE INPUT REGISTER WCLK Figure 13: Logic Diagram for the Dual-Port RAM The Dual-Port RAM signals and the CLB signals from which they are originally derived are shown in Table 9. Table 9: Dual-Port RAM Signals : . CLB RAM Signal Function Signal D Data In DIN A[3:0} Read Address for Single-Port. | F,-F, Write Address for Single-Port and Duail-Port. DPRA[3:0] _ | Read Address for Dual-Port G4-G, WE Write Enable SR 'WCLK Clock K -SPO Single Port Out Fout : (addressed by A[3:0]) | /DPO Dual Port Out Gout | (addressed by DPRA[3:0]) The RAM16X1D primitive used to instantiate the Duai-Port consists of an upper and a lower 16 x 1 memory array. The address port labeled A[3:0] supplies both the read and write addresses for the lower memory array, which behaves the same as the 16 x 1 Single-Port RAM array described - WRITE ROW WRITE ROW $= XILINX SELECT SELECT READ ROW SPO DPRA[3:0] SELECT SELECT READ ROW DPO previously. Single Port Out (SPO) serves as the data output for the lower memory. Therefore, SPO reflects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the upper memory. The write address for this memory, however, comes from the address A[3:0]. Dual Port Out (DPO) serves as the data output for the upper memory. Therefore, DPO reflects the data at address DPRA[3:0]. By using A[3:0] for the write address and DPRA[3:0] for the tead address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. The simultaneous read/write capability possible with the Dual-Port RAM can provide twice the effective data throughput of a Singie-Port RAM alternating read and write operations. The timing relationships for the Dual-Port RAM mode are shown in Figure 12. Note that write operations to RAM are synchronous (edge- triggered); however, data access is asynchronous. November 25, 1997 (Version 0.6) 4-185Spartan and Spartan-XL Families Field Programmable Gate Arrays Initializing RAM at FPGA Configuration Both RAM and ROM implementations of the Spartan series are initialized during device configuration. The initial con- tents are defined via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. If not defined, all RAM contents are initialized to zeros, by default. RAM initialization occurs only during device configuration. The RAM content is not affected by GSR. More information on using RAM inside CLBs Three application notes are available from Xilinx that dis- cuss synchronous (edge-triggered) RAM: Xilinx Edge-Trig- gered and Dual-Port RAM Capability Implementing FIFOs in Xilinx RAM and Synchronous and Asynchro- nous FIFO Designs. All three application notes apply to both the Spartan and the Spartan-XL series. Fast Carry Logic Each CLB F-LUT and G-LUT contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of nor- mal routing resources. Dedicated fast carry logic greatly increases the efficiency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefficient. High-speed address offset calculations in micro- processor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be configured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efficient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benefit at the 32-bit level. This fast carry logic is one of the more significant features of the Spartan series, speeding up arithmetic and counting func- tions. The carry chain in Spartan devices can run either up or down. At the top and bottom of the columns where there are no CLBs above and below, the carry is propagated to the right. (See Figure 14.) cite || cLe Ls} cLB || cLe 1 4 : i if , \ f CLB CLB CLB CLB s 4 a J ~~ 4 $e G $$ F 4 Fs CLB CLB CLB CLB ; ~ I | | i | t | cLB |+ cre [s+ cts || cLB X6687 Figure 14: Available Spartan Carry Propagation Paths Figure 15 on page 4-187 shows a Spartan series CLB with dedicated fast carry logic. The carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to forrn the sums. Figure 16 on page 4-188 shows the details of the carry logic for the Spartan. This diagram shows the contents of the box labeled CARRY LOGIC in Figure 15. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Mac- ros (RPMs) that already include these symbols. 4-186 November 25, 1997 (Version 0.6)$< XILINX CARRY Cout CinDOWN Din G4 G3 G2 YQ G1 H1 xQ F4 F3 F2 Ft >) > Ff S/R Ec Cinup C out X6699 Figure 15: Fast Carry Logic in Spartan CLB November 25, 1997 (Version 0.6) 4-187Spartan and Spartan-XL Families Field Programmable Gate Arrays G4 Cour Fe Ft TO FUNCTION GENERATORS F3 X2000 Figure 16: Detail of Spartan Dedicated Carry Logic 3-State Long Line Drivers A pair of 3-state buffers is associated with each CLB in the array. These 3-state buffers (BUFT) can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal lon- glines, saving logic resources. There is a weak keeper at each end of these two horizontal longlines. This circuit prevents undefined floating levels. However, it is overridden by any driver. ' Cin Down Three-State Buffer Examples Figure 17 shows how to use the 3-state buffers to imple- ment a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 10. Table 10: Three-State Buffer Functionality The buffer enable is an active-High 3-state (i.e. an active- IN T OUT Low enable}, as shown in Table 10. x 1 IN 0 IN Vi cop Beb.cbem ai | 400 ke Z=D,eA+Dg B+D,.C+Dy N ! : ] Dy - Dg t % : <] i BUFT BUFT BUFT BUFT OA 8 c- Weak Keeper Figure 17: 3-State Buffers Implement a Multiplexer x6466 4-188 November 25, 1997 (Version 0.6)On-Chip Oscillator Spartan series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for config- uration memory clearing, and as the source of CCLK in Master configuration modes. The oscillator runs at a nomi- nal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 MHz and 10 MHz. The oscillator output is optionally available after configura- tion. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, four- teenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16 kHz, 490 Hz and 15 Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC library element in a schematic or in HDL code. The oscillator is automatically disabled after configuration if the OSC sym- bol is not used in the design. Global Signals: GSR and GTS Global Set/Reset A separate Global Set/Reset line, as shown in Figure 3 on page 4-176 for the CLB and Figure 6 on page 4-178 for the OB, sets or clears each flip-flop during power-up, reconfig- uration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each flip-flop is configured as either globally set or reset in the same way that the local set/reset (SR) is specified. Therefore, if a flip-flop is set by SR, it is also set by GSR. Similarly, if in reset mode, it is reset by both SR and GSR. STARTUP <PAD>->esR az Le IBUF GTS Q3 L Q1Q4 - -p> CLK DONEIN - X5260 Figure 18: Schematic Symbols for Global Set/Reset GSR can be driven from any user-programmabie pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 18.) A spe- cific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-program- mable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the GSR signal. Alterna- tively, GSR can be driven from any internal node. 92 XILINX Global 3-State A separate Global 3-State line (GTS) as shown in Figure 5 on page 4-177 forces all FPGA outputs to the high-imped- ance state, unless boundary scan is enabled and is execut- ing an EXTEST instruction. GTS does not compete with other routing resources; it uses a dedicated distribution net- work, GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. This is similar to what is shown in Figure 18 for GSR except the IBUF would be connected to GTS. A specific pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can option- ally be inserted after the input buffer to invert the sense of the Global 3-State signal. Alternatively, GTS can be driven from any internal node. Boundary Scan The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for i/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compati- ble devices may be serial daisy-chained together, con- nected in parallel, or a combination of the two. The Spartan Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan configuration option is selected, three normal user \/O pins become ded- icated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this sec- tion. By exercising these input signals, the user can serially load commands and data into these devices to control the driv- ing of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. it avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fifth pin, a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction regis- ter and a number of data registers. The functional details can be found in the IEEE 1149.1 specification and are also November 25, 1997 (Version 0.6) 4-189Spartan and Spartan-XL Families Field Programmable Gate Arrays discussed in the Xilinx application note: Boundary Sean in FPGA Devices. Figure 19 on page 4-190 is a diagram of the Spartan Series boundary scan logic. It includes three bits of Data Register per 1OB, the IEEE 1149.1 Test Access Port controller, and the instruction Register with decodes. Spartan Series devices can also be configured through the boundary scan logic. See Configuration Through the Boundary Scan Pins on page 4-197. Data Registers The primary data register is the boundary scan register. For each |OB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-iOB pins have appropriate partial bit population for In or Out only. PRO- GRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is always the last bit of the data register. These three bound- ary scan bits are special-purpose Xilinx test signals. Gof Oo Go y io | 108 | tog | ios | 108 L-. | CH 1B op EOI | [toe sop HIT} CH 10s 1OB.4 CRT we | CH tos i bo | ; Cy 108 my | ~ . pa SS | | - : { | t x | REGISTER : i ry oat i : [|rpo} er 44 oe PTD XL || i sOB4 Figure 19: Spartan Series Boundary Scan Logic The other standard data register is the singie flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specified using the BSCAN macro. The FPGA provides two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDOt and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to imple- ment with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE). instruction Set The Spartan Series boundary scan instruction set also includes instructions to configure the device and read back the configuration data. The instruction set is coded as shown in Table 11. DATA IN | i y Lo J i 1 sd { iD DO ape} Aenea mina a T 1 eH F | bee | | eo ee TOOL eT EEE | Loy sd Dre _-.J0 i i p- Do btLe o-] LE I SHIFT CAPTURE | | . -{ oe | t DATAOUT UPDATE CLOCK DATA REGISTER e EXTEST 4-190 November 25, 1997 (Version 0.6)$< XILINX Bit Sequence The bit sequence within each !OB is: In, Out, 3-State. The input-only pins contribute only the in bit to the boundary scan /O data register, while the output-only pins contrib- utes all three bits. The first two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal sig- nais. The final bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in EPIC), start- ing in the upper right chip corner, the boundary scan data- register bits are ordered as shown in Figure 20. The device- specific pinout tables for the Spartan Series include the boundary scan locations for each |OB pin. BSDL (Boundary Scan Description Language) files for Spartan Series devices are available on the Xilinx FTP site. Including Boundary Scan in a Schematic If boundary scan is only to be used during configuration, no special schematic elements need be included in the sche- matic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user func- tions after configuration. To indicate that boundary scan remain enabled after config- uration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 21. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TD! can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK. Table 11: Boundary Scan Instructions . Instruction Test 1/0 Data 12 11 10 Selected | TPOSource coitce 0:0/0 EXTEST DR DR / 01:0 14) SAMPLE/ DR Pin/Logic PRELOAD 0| 14,0 USER 1 BSCAN User Logic TDOt o/; 7/1) USER2 BSCAN User Logic TDO2 1 | 0; 0 | READBACK: Readback Data | Pin/Logic 1 | 0! 1 |CONFIGURE DOUT Disabled 1,1 0. Reserved | _ _ 1/111) BYPASS 'Bypass Register _ Bit 0 ( TDO end) TDO.T Bit 4 TDO.O Bit 2 f { Top-edge IOBs (Right to Left) l { Left-edge {OBs (Top to Bottom) MODE.| Bottom-edge {OBs (Left to Right) | Right-edge !OBs (Bottom to Top) (TDI end) B SCANT.UPD Figure 20: Boundary Scan Bit Sequenc5_ Avoiding Inadvertent Boundary Scan if TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant dur- ing configuration. In some applications, a situation may occur where TMS or TCK is driven during configuration. This may cause the device to go into boundary scan mode and disrupt the configuration process. To prevent activation of boundary scan during configura- tion, do either of the following: * TMS: Tie High to put the Test Access Port controller in a benign RESET state * TCK: Tie High or Lowdon't toggle this clock input. For more information regarding boundary scan, refer to the Xilinx Application Note, Boundary Scan in FPGA Devices. Optionai To User Logic IBUF BSCAN Tol TDI DO TOO [IMS > tus pAcK |- DLE F-~ TCK TOK To User From J ~~] TOOT SEL1 Logic UserLogic | Itpoe SEL2 R X2675 Figure 21: Boundary Scan Schematic Example November 25, 1997 (Version 0.6) 4-191Spartan and Spartan-XL Families Field Programmable Gate Arrays Configuration and Test Configuration is the process of loading design-specific pro- gramming data into one or more FPGAs to define the func- tional operation of the internal blocks and their interconnections. This is somewhat like loading the com- mand registers of a programmable peripheral chip. Spartan Series devices use several hundred bits of configuration data per CLB and its associated interconnects. Each con- figuration bit defines the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The Xilinx devel- opment system translates the design into a netlist file. It automatically partitions, places and routes the logic and generates the configuration data in PROM format. Configuration Mode Control Spartan series devices have two configuration modes. * MODE = 1 sets Slave Serial mode * MODE = 0 sets Master Serial mode The control pin (MODE) is sampled prior to starting contig- uration to determine the configuration mode. After configu- ration, this pin is unused. The MODE pin has a weak pull- up resistor turned on during configuration. With MODE High, Slave Serial mode is selected, which is the most pop- ular configuration mode used primarily for daisy-chained devices. Therefore, for the most common configuration mode, the MODE pin can be left unconnected. (Note, how- ever, that the internal pull-up resistor value can be as high as 100 kQ) If the Master Serial mode is desired, an exter- nal pull-down resistor value of 4.7 kQ, connected to the MODE pin, is recommended. During configuration, some of the I/O pins are used tempo- rarily for the configuration process. Ail pins used during configuration are shown in Table 12 on page 4-192. Master Serial Mode The Master serial mode uses an internal oscillator to gen- erate a Configuration Clock (CCLK) for driving potential slave devices and the Xilinx serial-configuration PROM (SPROM). The CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Configuration always starts at the default slow frequency, then can switch to the higher fre- quency during the first frame. Frequency tolerance is -50% to +25%. In Master Serial mode, the CCLK output of the device drives a Xilinx SPROM that feeds the FPGA DIN input. Each rising edge of the,CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The FPGA accepts this data on the subsequent rising CCLK edge. Table 12: Pin Functions During Configuration CONFIGURATION MODE <MODE Pin> SLAVE SERIAL MASTER SERIAL <Low> USER OPERATION MODE HDC HDC VO vO vO DONE DONE CCLK vO SGCK4-/O TDI-V/O TCK-I/O TMS-I/O CCLK DOUT : : : ALL OTHERS Notes 1. Ashaded table ceil represents the internal pull-up used before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration. When used in a daisy-chain configuration the Master Serial FPGA is placed as the first device in the chain and is referred to as the lead FPGA. The lead FPGA presents the preamble data, and all data that overflows the lead device, on its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. See the timing diagram in Figure 22. In the bitstream generation software, the user can specify Fast Configuration Rate, which, starting several bits into the first frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to the specifica- tion section. Be sure that the serial PROM and slaves are fast enough to support this data rate. Devices such as XC3000A and XC3100A do not support the Fast Configura- tion Rate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-l/O, but LDC is then restricted to be a permanently High user output after con- figuration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 23 shows a full master/slave system. The leftmost device is in Master Serial mode, ail other devices in the chain are in Siave Serial mode. Master Serial mode is selected by a Law on the MODE pin. 4-192 November 25, 1997 (Version 0.6)CCLK (Output) 2 XILINX Serial Data In Serial DOUT (Output) n-3 x n-2 X3223 Description Symbol Min Max Units DIN setup 1 Toscx 20 ns LK peer nee wees sanuae eo i ce DIN hold 2 Texps 0 ns Notes: 1. At power-up, Vcc rnust rise from 2.0 V to Vec min in less than 25 ms, otherwise delay configuration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode. Figure 22: Master Serial Mode Programming Switching Characteristics Slave Serial Mode In Slave Serial mode, the FPGA receives serial configura- tion data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. in this mode, an external signal drives the CCLK input of the FPGA (most often from a Master Serial device). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short setup time before each ris- ing CCLK edge. The lead FPGA then presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the sub- sequent rising CCLK edge. Figure 23 shows a full master/slave system. A Spartan series device in Slave Seriai mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a high on the MODE pin. Slave Seriai is the default mode if the MODE pin is left unconnected, as it has a weak pull-up resistors during con- figuration. Multipie slave devices with identical configurations can be wired with parallel DIN inputs. In this way, multiple devices can be configured simultaneously. Serial Daisy Chain Multiple devices with different configurations can be con- nected together in a daisy chain, and a single combined bitstream used to configure the chain of slave devices. To configure a daisy chain of devices, wire the CCLK pins of all devices in paraliel, as shown in Figure 23 on page 4-194. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized configuration data coming from a single source. The header data, including the length count, is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its configuration data, it passes on any additional frame start bits and configuration data on DOUT. When the total number of configuration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last configura- tion bit is received. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM file formatter must be used to combine the bitstreams for a daisy-chained con- figuration. November 25, 1997 (Version 0.6) 4-193Spartan and Spartan-XL Families Field Programmable Gate Arrays NOTE: M2, M1_ MO can be shorted to Vec if not used as VO * | VCC p- pg ark Soom S Bare | 1 | i pron] Mone NIG ~ MODE Lede SY BARON = our fren 3] ON OWT 3} iN pour Spartan Veo be cou beeen = PLCC MASTER XC17000 sv Spartan XC3100A SERIAL. i y SLAVE SLAVE SCLK ype} DIN TA we] PROGR AIA ibe cE CES; 9m PROGRAM ve RESET | my DONE int > +- RESETS | DONE NT <>, | cor INIT foe e | 7 | | (Low Reset Option Used) Pde \ | ii I +} : | L PROGRAM , J $9025.01 Figure 23: Master/Siave Serial Mode Circuit Diagram DIN x Bitn Bitn+1 I | e~ 4) Toec >} @) Toco = Teor te CCLK # \ / @)Tecx @teeo (Output) Bitn-1 ! Bit n X5379 Description Symbol Min Max Units DIN setup 1 Tpce 20 ns DIN hold 2 Teep 0 _ ns CCLK DIN to DOUT 3 Toco 30 ns High time 4 Tocn 45 ns Low time 5 Toot . 45 | _ ns Frequency Foo 10 MHz Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Figure 24: Slave Serial Mode Programming Switching Characteristics Setting CCLK Frequency in Master mode, CCLK can be generaied in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for Spartan series devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for Spartan series devices. The fre- quency is selected by an option when running the bitstream generation software. Slow mode is the default. Data Stream Format The data stream (bitstream) format is identical for both configuration modes. The data stream format is shown in Table 13. Bit-serial data is read from left to right. The configuration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator field of ones. This header is followed by the actual configuration data in frames. The length and number of frames depends on the device type (see Table 14). Each frame begins with a start field and ends with an error check. A postamble code is required fo signal the end of 4-194 November 25, 1997 (Version 0.6)data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the star- tup sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams created by the Xilinx software. Table 13: Spartan Series Data Stream Formats Data Type Fiil Byte 11114111b Preamble Code 0010b Length Count COUNT(23:0) Fill Bits 1111b Start Field Ob Data Frame DATA(n-1:0) CRC or Constant xxxx (CRC) Field Check or 0110b -Extend Write Cycle _ Postamible OMIM Tib | Start-Up Bytes xxh LEGEND: Unshaded Once per bitstream Light Once per data frame Dark | Once per device Table 14: Spartan Program Data $2 XILINX A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame field for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data load- ing and the pulling down of the INIT pin. In Master serial mode, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling Vec. Cyclic Redundancy Check (CRC) for Configuration and Readback The Cyclic Redundancy Check is a method of error detec- tion in data transmission applications. Generally, the trans- mitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and com- pares the result with the received checksum. Each data frame of the configuration bitstream has four error bits at the end, as shown in Table 13. If a frame data error is detected during the loading of the FPGA, the con- figuration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state. Device XCSO5/KL XCS10/XL XCS20/XL XCS30/XL XCS40/XL Max System Gates 5,000 10,000 20,000 30,000 40,000 CLBs 100 196 400 576 784 (Row x Col.) (10x10) (14 x 14) (20 x 20) (24 x 24) (28 x 28) iOBs 80 12 000CO sti<iaDSCC LC(SCO#*##CUN:SC 224 Flip-Flops 360 616 1,120 1,536 2,016 Horizontal Longlines 20 : 28 40 48 56 TBUFs per Longline 12 16 22 26 30 Bits per Frame 126 166 "226 266 306 Frames 428 572 788 932 1,076 Program Data 53,936 94,960 178,096 247,920 329,264 PROM Size (bits) 53,984 95,008 178,144 247,968 329,312 Notes: 1. Bits per Frame = (10 x number of rows) +7 for the top + 13 for the bottom +1+1startbit+4errorcheckbits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header. November 25, 1997 (Version 0.6) 4-195Spartan and Spartan-XL. Families Field Programmable Gate Arrays During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 25. The checksum consists of the 11 most signifi- cant bits of the 16-bit code. A change in the checksum indi- cates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB out- puts should not be included (Readback Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected. Configuration Sequence There are four major steps in the Spartan Series power-up configuration sequence. * Configuration Memory Clear * Initialization * Configuration Start-Up The full process is illustrated in Figure 26. Configuration Memory Clear When power is first applied or is reapplied to an FPGA, an internal circuit forces initialization of the configuration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of configu- ration bits, a time delay is started. This time delay is nomi- nally 16 ms, and up to 10% longer in the Spartan-XL devices. The delay is four times as long when in Master Serial Mode (MODE is Low), to allow ample time for all slaves to reach a stable Vcc. When ail INIT pins are tied together, as recommended, the longest delay takes prece- dence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. it is not caneied when reconfiguring an FPGA by pulsing the PROGRAM pin AIS, OT TE (2TSTsTsTeTe Tals frolspiaitsfra} SS & Pp i iP > SERIAL DATA Polynomial: X16 + X15 + X241 i : 1 t asym: iS) PS 2F io; 9 Pel Tl tm CRE - CHECKSUM -> tia itit LAST DATA FRAME m} START BIT [> Readback Date Stream Figure 25: Circuit for Generating CRC-16 Boundary Scan Instructions Available: Test MODE Ganerate One Time-Out Pulse PROGRAM > of 16 or 64 ms = Low i Yes Keep Clearing | | Configuration Meniory [0 | i | i EXTEST Fa SAMPLE/PRELOAD : BYPASS Completely Clear Configuration Mernory ~1.3 ps per Frame Once More i iNT : a Master ___--_ Yes Y--._.._ Master Delays Before Sampling Mode Lines Mode Lines ) en Master CCLK Goes Active H Load One y Configuration 4 Data Frame. & 2 6 9 a =z i Frame Yes (vuntin Pull INIT Low z Error and Kee 2 | 3 ine) Q oO Ct SAMPLE/PRELOAD BYPASS Contig- uration memary Fut Pass Configuration Data to DOUT CCLK Count Equats Length Court Start-Up Sequence ~ Operational EXTEST | SAMPLE PRELOAD | BYPASS USER t If Boundary Scan USER 2 is Selected CONFIGURE READBACK VO Active ->f- 8607601 Figure 26: Power-up Configuration Sequence 4-196 November 25, 1997 (Version 0.6)Low. During this time delay, or as tong as the PROGRAM input is asserted, the configuration logic is heid in a Config- uration Memory Clear state. The configuration-memory frames are consecutively initialized, using the internal oscil- lator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the configura- tion frames and then tests the INIT input. initialization During initialization and configuration, user pins HDC, CDC, INIT and DONE provide status outputs for the system inter- face. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the final initializa- tion pass through the frame addresses. There is a deliber- ate delay before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recog- nized as High, the device samples the MODE pin to deter- mine the configuration mode. The appropriate interface lines become active and the configuration preamble and data can be loaded. Configuration The 0010 preamble code indicates that the following 24 bits represent the length count. The length count is the total number of configuration clocks needed to load the com- plete configuration data. (Four additional configuration clocks are required to complete the configuration process, as discussed below.) After the preamble and the length count have been passed through to any device in the daisy chain, its DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. A specific configuration bit, early in the first frame of a mas- ter device, controls the configuration-clock rate and can increase it by a factor of eight. Therefore, if a fast configu- ration clock is selected by the bitstream, the slower clock rate is used until this configuration bit is detected. Each frame has a start field followed by the frame-configu- ration data bits and a frame error field. If a frame data error is detected, the FPGA halts foading, and signals the error by pulling the open-drain INIT pin Low. After all configura- tion frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device. Delaying Configuration After Power-Up There are two methods of delaying configuration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 26 on page 4-196.) = XILINX A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply rise time is excessive or poorly defined. As long as PRO- GRAM is Low, the FPGA keeps clearing its configuration memory. When PROGRAM goes High, the configuration memory is cleared one more time, followed by the begin- ning of configuration, provided the INIT input is not exter- nally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The Spartan Series PROGRAM pin has a permanent weak puil-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of configuration causes the FPGA to wait after completing the configuration memory clear operation. When INIT is no tonger held Low exter- nally, the device determines its configuration mode by cap- turing the state of the MODE pin, and is ready to start the configuration process. A master device waits up to an addi- tional 300 us to make sure that any slaves in the aptional daisy chain have seen that INIT is High. Configuration Through the Boundary Scan Pins Spartan Series devices can be configured through the boundary scan pins. The basic procedure is as follows: * Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after configuration if a resistor is used to hold INIT Low. * issue the CONFIG command to the TMS input * Wait for INIT to go High Sequence the boundary scan Test Access Port to the SHIFT-DR state * Toggle TCK to clock data into TDI pin. The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note, Boundary Scan in FPGA Devices. This application note alsa applies to Spartan and Spartan-XL devices. Readback The user can read back the content of configuration mem- ory and the level of certain internal nodes without interfer- ing with the normal operation of the device. Readback not only reports the downloaded configuration bits, but can also include the present state of the device, represented by the content of all flip-flops and latches in CLBs and |OBs, as well as the content of function genera- tors used as RAMs. November 25, 1997 (Version 0.6) 4-197Spartan and Spartan-XL Families Field Programmable Gate Arrays IF UNCONNECTED, DEFAULT IS CCLK oN cux| i, READ TRIGGER TRIG IBUF | DATA > READ.DATA ps, READBACK OBUF | RIP Figure 27: Readback Schematic Example Spartan Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any JOB. To access the internal Readback signals, place the READ- BACK library symbol and attach the appropriate pad sym- bols, as shown in Figure 27. After Readback has been initiated by a Low-to-High transi- tion on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with five dummy bits (all High) followed by the Start bit (Low) of the first frame. The first two data bits of the first frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before ROBK.RIP returns Low. Readback Options Readback options are: Readback Capture, Readback Abort, and Clock Select. They are set with the bitstream generation software. Readback Capture When the Readback Capture option is selected, the read- back data stream includes sampled values of CLB and lIOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the |OB output flip- flops and the input signals 11 and l2. Note that while the bits describing configuration (interconnect, function gener- ators, and RAM content) are not inverted, the CLB and [OB output signals are inverted. When the Readback Capture option is not selected, the val- ues of the capture bits reflect the configuration data origi- nally written to those memory locations. lf the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table configuration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 28. 81786_(4 Readback Abort When the Readback Abort option is selected, a High-to- Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per configuration frame) may be required to re-initialize the control logic. The status of readback is indi- cated by the output contro! net RDBK.RIP RDBK.RIP is High whenever a readback is in progress. Clock Select CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner, as shown in Figure 28. Violating the Maximum High and Low Time Specification for the Readback Clock The readback clock has a maximum High and Low time specification. In some cases, this specification cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specification. The specification is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mech- anism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the follow- ing frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. T T PROGRAMMABLE / INTERCONNECT i Figure 28: READBACK Symbol in Graphical Editor 4-198 November 25, 1997 (Version 0.6)Therefore, the specification only applies to the six clock cycles prior to and including any start bit, including the clocks before the first start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynarnic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the read- back data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 13 and Tabie 14. Readback with the XChecker Cable The XChecker Universal Download/Readback Cabie and Logic Probe uses the readback feature for bitstream verifi- cation. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-cir- cuit emulator. 4 Finished a7 internal Net rdbk. TRIG 22 XILINX Spartan Program Readback Switching Charac- teristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. The following guidelines reflect worst-case values over the recommended operating conditions. ~ MeTRCRTM CpyTATRC | ae (2) 1 rdelkt L\F}S\S- ce oy (a Tact e+ Trod 82 rdok.RIP oN ___ (a) >| Trcra > \ Cc 5 rdbk. DATA | aEn DUMMY vaio VALID / \ TRORO (5 Spartan and Spartan-XL X1780 Description Symbol Min Max Units rdbk. TRIG rdbk. TRIG setup to initiate and abort Readback | 1 Trtre 200 - ns rdbk. TRIG hold to initiate and abort Readback 2 Tacrt 50 - ns rdclk.1 rdbk.DATA delay 7 Trero - 250 ns : rdok.RIP delay 6 TRCRR - 250 ns High time 5 Tacx 250 500 ns Low time 4 Tree 250 500 ns Note 1: Timing parameters apply to all speed grades. Note 2: If rdbk. TRIG is High prior to Finished, Finished will trigger the first Readback. November 25, 1997 (Version 0.6) 4-199Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan Detailed Specification Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estinates based on simulation and/or extrapolation from other speed grades, cevices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Spartan Absolute Maximum Ratings Symbol Description Value Units Veco Supply voltage relative to GND -0.5 to +7.0 Vv Vin Input voltage relative to GND (Note 1) ~0.5 to Veg +0.5 V Vts Voltage applied to 3-state output (Note 1) -0.5 to Veg +0.5 Vv Tst@ Storage temperature (ambient) -65 to +150 C Tsar Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C Ty Junction temperature [Plastic packages +125 C Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is Note 2: easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts jess than 20 ns. Stresses beyond! those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Spartan Recommended Operating Conditions Symbol Description Min Max Units Voc Supply voltage relative to GND, Ty = -0 C to +85C Commercial 4.75 5.25 Vv Supply voltage relative to GND, Ty = -40C to +100C Industrial 45 5.5 Vv Vig High-level input voltage TTL inputs 2.0 Veco Vv CMOS inputs 70% 100% | Vec Vit Low-level input voitage TTL inputs 0 0.8 Vv CMOS inputs 0 20% Vec Tin Input signal transition time 250 ns Note: At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS. 1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice. 4-200 November 25, 1997 (Version 0.6)Spartan DC Characteristics Over Operating Conditions $< XILINX Symbol Description Min Max Units Von High-level output voltage @ Ipy = -4.0MA, Vee min TTL outputs 2.4 V High-level output voltage @ loy = -1.0MA, Veco min CMOS outputs Vec-0.5 Vv Vot Low-level output voltage @ lo, = 12.0MA, Veo min TTL outputs 0.4 Vv (Note 1) CMOS outputs 0.4 Vv leco Quiescent FPGA supply current (Note 2) Commercial 3.0 mA Industrial 6.0 mA IL input or output leakage current -10 +10 HA Cin Input capacitance (sample tested) PC, VQ, TQ, PQ, 10 pF BG packages IRPU Pad pull-up (when selected) @ Vin = OV (sample tested) -0.02 -0.25 mA lapp Pad pull-down (when selected) @ Vix = 5V (sample tested) 0.02 mA Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with the Tie option. November 25, 1997 (Version 0.6) 4-201Spartan and Spartan-XL Families Field Programmable Gate Arrays Spartan Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all Spartan devices unless otherwise noted. Speed Grade . pee 7 -3 4 Units Description Symbol Device Global Clock to Output Tickor XCSO05 8.7 6.0 ns (a in OFF | mo | 8 | | es XCS30 9.4 7.4 ns Tre oer (Max) XCS40 102 | 76 : Glovai Ciock-to-Output Deay ! : xaone ! Globai Clock to Output Ticko XCS05 15 7 8.0 ns (slew-limited) using OFF xo ' a0 | B4 ns oS / XCS30 128 , 94 ns Tro ore 7 (Max) = xcS40 128 96 | lal Coco Ouest dey _| . : ' . Kaen i oy Input Setup Time, using IFF Tesyur | CSO 2.3 17 ns (voce) ee fu 8 | ppd XCS30 0 0 ns oan i (Min) xCS40 0 0 Set-Up | f iFE : | we S| | Time | Lo input Hold Time, using IFF | TeHe XCS05 4.0 17 ns | i(no delay) / XCS10 45 2.2 ns | XCS20 5.5 27 ns | be / XCS30 55 3.2 ns | Input * ; i {Min) XCS40 5.7 3.7 Set-Up | iFF ! i od oe B.. 2 Input Setup Time, using IFF == sTpgy ss XC S05 6.0 52 ns : . 5. (with delay) ee xos20 | 60 52 | ons Cee ed p XCS30 6.0 8.2 ns input eo EE (Min) xC840 6.8 5.2 Set-Up : : iFF i i | Time > Bb) | woes : Input Hold Time, using |FF Tey Xcs0s 0 0 ns i | iS (with delay) _ ! XCS20 0 0 ns me lp XCS30 0 0 ns input | {Min) | = xcs4o D 0 Set- Up i : iFE | time <> Se | _| J OFF = Output Flip-Flop IFF = Input Flip-Flop/Latch : Advance _ 4-202 November 25, 1997 (Version 0.6)$2 XILINX Spartan-XL Detailed Specification Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: _Initial estirnates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. All specifications subject to change without notice. Spartan-XL Absolute Maximum Ratings Symbol Description Value Units Voc Supply valtage relative to GND -0.5 to 4.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to 5.5 Vv Vis Voltage applied to 3-state output (Note 1) -0.5 to 5.5 Vv Veet Longest Supply Voltage Rise Time from 1V to 3V 50 ms Tstq Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in. = 1.6 mm) +260 C Ty Junction temperature | Plastic packages 4125 C Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond thase listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those tisted under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Spartan-XL Recommended Operating Conditions Symbol Description Min Max Units Supply voltage relative to GND, Ty = 0C to +85C | Commercial 3.0 3.6 V Voc Supply voltage relative to GND, Ty = -40C to Industrial 3.0 3.6 Vv +100C Vin High-level input voltage 50% of Vec 5.5 Vv Vir Low-level input voltage 0 30% of Voc Vv Tin Input signal transition time 250 ns Notes: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. input and output measurement threshold is ~40% of Vgc. November 25, 1997 (Version 0.6) 4-203Spartan and Spartan-Xt. Families Field Programmable Gate Arrays Spartan-XL DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Vor High-level cutput voltage @ logy = -4.0 mA, Veg min (LVTTL) 24 Vv High-level output voltage @ loy = -500 pA, (LVCMOS) 90% Veco Vv VoL Low-level output voltage @ lo, = 12.0 mA, Veco min (LVTTL) (Note 1) 0.4 V Low-level output voltage @ lo, = 1500 nA, (LVCMOS) 10% Voc V Vor Data Retention Supply Voltage (below which configuration data may be lost) 25 v leco | Quiescent FPGA supply current (Note 2) 5 mA I Input or output leakage current -10 +10 A Cin Input capacitance (sample tested) | PC, VQ, TQ, PQ, BG packages 10 pF Irey Pad pull-up (when selected) @ V,, = OV (sample tested) 0.02 0.25 mA lnpp Pad pull-down (when selected) @ V;, = 3.3V (sampie tested) 0.02 mA Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input pull-up resistors, all package pins at Vec or GND, and the FPGA configured with the Tie option. 4-204 November 25, 1997 (Version 0.6)$< XILINX Spartan-XL Guaranteed Input and Output Parameters (Pin-to-Pin) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all Spartan-XL devices unless otherwise noted. Speed Grade ae | P ~ 3 : ~4 Units Description Symbol Device Global Clock to Output TickKOE XCSO5XL 8.7 6.0 ns j XCS10XL 9.4 6.4 ns (fast) using OFF XCS20XL 9.3 7.0 ns iB XCS30XL 9.4 7.4 ns toa on | | (Max) XCS40XL 10.2 7.6 ns Global Clock-to-Output Delay : xa20e Global Clock to Output Ticko XeSOsXi 15 ao.) ons limi i XCS10XL 12.0 8.4 ns (slew-limited) using OFF xCS20XE 122 90 ne i XCS30XL 12.8 9.4 ns pe cre Pe (Max) XCS40XL 12.8 9.6 ns Giobal Clock-to-Output Delay : _ Kg202 Input Setup Time, using IFF Tpsur XCSO5XL 23 17 ns (no delay) su XCS10XL 1.2 1.0 ns : pone XCS20XL 0.2 0 ns odd XCS30XL 0 0 ns runt | (Min) XCS40XL 0 0 ns Set-Up | IF | Hoid ! > JS | Time | nS i input Hold Time, using IFF | Tee XCSO5XL 40 17 ns (no delay) ' XCS10XL 45 2.2 ns ee i XCS20XL .5 27 ns oJ po . XCSIOXL 55 3.2 ns input 1 | (Min) XCS40XL 57 3.7 ns Set-Up | iFF : : Hold | Tee i Time / Cc>~ > > input Setup Time, using IFF / Tpgu XCSOSXL 6.0 520 [ons (with delay) XCS10XL 6.0 5.2 ns _ | XCGS20XL 6.0 .2 ns oI p ; XCS3OXL 6.0 5.2 ns input * (Min) XCS40XL 6.8 5.2 ns Set - Up i t (Fe i | PG. Fad po Be | 7! | Input Hold Time, using IFF Fy XCSO5XL 0 a ns | (with del XCS10XL 0 0 ns (with delay) __ XCS20XL 0 0 ns een p : . XCS30XL 0 0 ns | input | (Min) XCS40XL 0 0 ns Set-Up | 1 {FF I PG i Hd IS | | ON _ | OFF = Output Flip-Flop FF = Input Flip-Flop/Latch wa Advance a November 25, 1997 (Version 0.6) 4-205Spartan and Spartan-Xl. Families Field Programmabie Gate Arrays Pin Descriptions There are three types of pins in the Spartan Series devices: + Permanently dedicated pins * User I/O pins that can have special functions + Unrestricted user-programmable 1/O pins. Before and during configuration, all outputs not used for the configuration process are 3-stated with the i/O pull-up resistor network activated. After configuration, if an IOB is unused it is configurecl as an input with the 1/O pull-up Spartan Series devices have no dedicated Reset input. Any user I/O can be configured to drive the Global Set/Reset net, GSR. See Globa! Signals: GSR and GTS on page 4-189 for more information on GSR. Spartan Series devices have no dedicated 3-state pin, they use the global 3-state net, GTS, instead. This net 3-states all outputs. See Global Signals: GSR and GTS on page 4-189 for more information on GTS. Device pins for Spartan Series devices are described in Table 15. resistor network remaining activated. Table 15: Pin Descriptions vo During PinName | Config. vo After Contig. i Pin Description Permanently Dedicated ] i Pins vcc X X |Eight or more (depending on package) connections to the nominal +5 V supply voltage | (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled | with a 0.01 - 0.1 uF capacitor to Ground. | GND X Eight or more (depending on package type) connections to Ground. All must be con- nected. CCLK lor O During configuration, Configuration Glock (CCLK) is an output in Master mode and is an | input in Slave mode. After configuration, CCLK has a weak pull-up resistor and can be , selected as the Readback Clock. There is no CCLK High or Low time restriction on Spartan Series devices, except during Readback. See Vioiating the Maximum High and Low Time Specification for the Readback Clock on page 4-198 for an explanation: | of this exception. DONE vO 'DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE | can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the program that creates the configuration bitstream. The resistor is included by default. '*B AM \ PROGRAN is an active Low input that forces the FPGA to clear its configuration mem- ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it goes into a WAIT state and releases INIT. The PROGRAMN pin has a permanent weak pull-up, so it need not be externally Pulled up to Voc. MODE | The Mode input is sampled after INIT goes High to determine the configuration mode io be used. : During configuration, this pin has a weak pull-up resistor. Far the most popular contig: i uration mode, Slave Serial, the mode pin can be left unconnected. A pull-down resistor : value of 4.7 kQ is recommended for Master Serial mode. : | Dont Connect | Xx x Pins reserved for factory testing and possible future enhancements. Pins must be left ' floating. |User VO Pins That Can Have Special Functions i i | | TDO 0 if boundary scan is used, this pin is the Test Data Output. if boundary scan is not used, : this pin is a 3-state output without a register, after configuration is completed. : This pin can be user output only when called out by special schematic definitions. To | use this pin, place the library component TDO instead of the usual pad symbol. An out-. put buffer must still be used. 4-206 November 25, 1997 (Version 0.6)$= XILINX Table 15: Pin Descriptions (Continued) coo en) vO | : ; During | After | | Pin Name | Config. | Config. | Pin Description i i If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select | inputs respectively. They come directly from the pads, bypassing the IOBs. These pins | \ | yo. can also be used as inputs to the CLB logic after configuration is completed. i | TDI, TCK \ orl If the BSCAN symbol is not placed in the design, ail boundary scan functions are inhib TS | JTAG ited once configuration is completed, and these pins become user-programmable VO. | ( } jIn this case, they must be called out by special library elements. To use these pins, | \place the library components TDL, TCK, and TMS instead of the usual pad symbols. in-| | put or output buffers must still be used. | | High During Configuration (HDC) is driven High until the /O go active. It is available as | | HDC | | VO acontrol output indicating that configuration is not yet completed. After configuration, ! HDC isa user-programmabie 1/O pin. | | TLow During Configuration (CDG) is driven Low until the /O. go active. Itis available as a i cbc 0 0 |contro! output indicating that configuration is not yet completed. After configuration, | | LDC is a user-programmable 1/O pin. : Before and during configuration, INIT is a bidirectional signal. A 1 kQ - 10 kQ external - 4 | pull- up resistor is recommended. | As an active-Low open-drain output, INIT is heid Low during the power stabilization and | jinternal clearing of the configuration memory. As an active-Low input, it can be used | INIT vO vO ito hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 jis after INIT has gone High. | i i |Ouring configuration, a Low on this output indicates that a configuration data error has , occurred, After the /O go active, INIT is a user-programmable 1/O pin. ! ee pea fpr Tt i ee ee ae nn Four P Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro- | PGCKI - Weak | grammable 1/0. | | The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol iconnected directly to the input of a BUFGP symbol is automatically placed on one of| | . these pins. po + - [Four Secondary Global inputs each drive a dedicated internal global net with short delay _and minimal skew. These internal global nets can also be driven from internal logic. If SGCK1- | Weak | Lor liO | inot used to drive a globai net, any of these pins is a user-programmable I/O pin. SGCK4 Pull- Up The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff- i i | iers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto- | | matically placed on one at these pins. can tn nn a i During Slave Serial or Master Serial configuration, DIN is the serial configuration data | DIN I | WO jinput receiving data on the rising edge of CCLK. After configuration, DIN is a user-pro- igrammable Opin eee / a | __ 'During configuration, DOUT is the serial configuration data output that can drive the DIN vO of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one- jand-a-half CCLK periods after it was received at the DIN input. _jAfter configuration, DOUT i fs a user-programmable_ vO ) pin. Unrestricted User-Programmable vO Pins Weak These | pins can be c configured 10 be input and/or output after configuration is completed. ed. , vo | eak 0 |Before configuration is completed, these pins have an internal high-value pull-up resis- Pulkup itor network that defines the logic level as High. November 25, 1997 (Version 0.6) 4-207Spartan and Spartan-XL Families Field Programmable Gate Arrays Device-Specific Pinout Tables Device-specific tables include all packages for each Spartan and Spartan-XL device. They follow the pad locations around the die, and include boundary scan register locations. Pin Locations for XCS05 & XCSO5XL Devices / XS05 & XCSOS5XL_ XCSO5 & XCSO5XL | Pad Name | PC84 vat00 Bndry Scan Pad Name PCee ss VQ100 Bndry Scan vc P2 P89 : P88 : MK ~ P3 P90. 32 > P44 P39 157 vO ~ P4 Poy 350 vO Pa 160 vO - Pao 38 WO 163 HO - Pog ae [vO vO P65 Poof ed VO P6 Pgs a [vO Vo. P? P96 50 vo ie - par go lio vO VO, SGCK3 8a GND pie PA DO | vO, PGCK! / Pig [Pe 62} sec / vo Pia Pa 65 [PROGRAM | vO, TOI oo ib P4 eB 10 | 187 i: vO, TCK ~ Bt6 BE Aa VO, PGCK3 90 | 0. TMS Pi7 P6 74 vO 4 WO vo . vo HO hoe V0 _ VO Woo! [Pas | PIS | 92 I {1/0 - vO vec a vO GND vO VO . wo HO Vv vO wo~~~SY,S vO _ vO _ P28 WO VO, SGCK2 ah P29 vO | Don't Connect P30 YO GND P3t YO(DIN) MODE P32 VO, SGCK4 (DOUT) ivCc P33 COLK Don'tConnect p PRO vo,PGck2 PS [vO (HDC) 4-208 November 25, 1997 (Version 0.6)$< XILINX f + [esos & KCSOSxL 7 Pad Name j; Peed va100 Bndry Scan | 10 P84 P87 : 29 : GND P41 P88 2897 Pin Locations for XCS10 & XCS10XL Devices HERR ISSO | pope) owe | rome SBT SRRGSION | peas | voteo rome | MY VOC P2 P89 P128 - vo P28 P20 P32 164 io. pst go Pis8 ao VO, SGCK2 P29 P21 P33 167 vO _ P4 P91 P130 47 7 Don't Connect P30 P22 P34 770 VO : P92 Pi3t 50 | GND P31 P23 P35 - VO - P93 P12 53 MODE P32 pea P36 173 uO PS Pag P1338 56 vec Pos | eb | PS? : WO PE POs P1394 59 Don't Connect P34 P26 P38 174 VO : Pia5 62 VO, PGCK2 P35 P27 P39 178 vO . . - P136 65 /O (HDC) P36 P28 P40 178 | GND 5 - P1397 aan - Pai | Bt uc P7 P96 Piae ee vo : : Bap ea TO PB P97 P139 71 vO - P43 187 Pi40 74 vO (CBG) P37 ~ Pad 790 nie : Pia 7 GND - - Pas PS Pos Pi4e a0 vO - P46 793 WO. SGCKi Pio Pos P1435 33 vO EBay TE VCC PTT P00 P14d 10 P38 P31) P48 199 GND Pi2 Pi PY : Vo P39 P32 P49 202 vO. PGCK1 P13 P2 P2 86 vo - P33 P50 205 iO Pid P3 "BB go VO - P34 Pet 208 vO : Be a vO P40 P35 P52 214 iO. : PS 6 V0 (NIT) Pat P36 PHS 214 vO. TDI Ba egg VCC P42 P37 P54 - vO. TCK Pi6 P5 PF T04 GND P43 P38 P55 : GND ~ a BS a VO P44 ~ p3g 0 BEE 217 to - - 55 ig io. Pas P40 P57 220 ive = a ~ P10 107 Vo - P41 P58 223 VO. TMS Pi? P6 Pit 170 vo - _ Pae P59 226 io Bia a ais Wa V0 P46. PAS P60 229 vO. ee eee ee ee ee eee eee BR 6 vo P47 : P44 P61 232 i) - Pia We WO : _. P62 235 to Pia PIs 128 vo OU Pea 238 V0 P20 P16 125 GND : Pe4 GND Pei Pi7 oe VO P48 P45 P65 244 vor. p23 BET V0 Pag P46 P&G 244 VO Pag Pia 128 yO tt oe P67 247 yO P24 P20 131 vO - ae = ee PBB; 250 vO = Pot 134 10 P50 Pa7 P69 253 iO a ~ P22 437 VO, SGCK3 Pot p48 P70 256 io Pas Bag GND | Psa) Pd P7T iO P26 Pad 43S DONE __P53 P50 P72 - 2 afer Bas Wa yoo Pd P51 P73 : . P26 14g PROGRAM P55 P52 P74 : : a7 oe vat P56 P53 P75 259 BRT P18 P28 152 VO, PGCK3 PS? PS4 P76 262 i a P19 P29 155 vO P?7 265 | 10 : : P36 0 PB 268 lo : : Bai er v0 Psa P55 P79 art November 25, 1997 (Version 0.6) 4-209Spartan and Spartan-XL Families Field Programmable Gate Arrays XCS10 & XCSIOXL pca4 vaioo Tatas Brdry ee eS tOKL pced vatoo Tove = Bray VO : PBS PaO 274 CCLK P73 Pra PI07 - GND on Pai lvec P74 o75 P10B vO ~ - Pe2 277 lO. TDO P75 | P76 Pi09 ol LO - - Pag 280 GND : P76 P77 P110 - vO P59 P57 PB4 283 VO P77 P78 Pitt | 2 vo P60 P58 P85 286 vO, PGCK4 P78 P79 P112 5 10 : P59 SS 289 0 : : Pii3 8 VO : P60 SC*&P'G 292 : : - Pitd 1 VO P4 Pot P88 295 P79 Peo P15 14 0 P62 P62 P89 298 P80 Pet P16 rv Were P63 P63 P90 : ~ es Pti8 OS GND P64 P4 Pq ~~ : oe P1i9 20 | Vo P P65 PGS P92 301 : _ P4120 330 lo ; PR BSE P98 304 BBL a Pit 26 VO : P67 Pod 307 Pe2 | R83 P1220; 29 ro i 310 a4 BBB ca VO Be? P68 313 - PS PRG vO P68 P69 316 Pest P86 P125 38 0 : : 319 ; Pad Pa? PI26 ai vO : : S22 PA Pag BaF GND _ - 7 7 B24/97 : , VO P68 P70 325 0 P70 P71 328 . . MO rn oa Additional XCS10/XL Package Pins vo : 334 TOM4 10 (DIN) P71 P72 i 337 | _ Not Connected Pins - : WO, SGCK4 P72 P73 340 [Pi | 1 - a |{(DOUT) . . a Pin Locations for XCS20 & XCS20XL Devices XCS20 & XCS2OXL vatoo yards equi. | Bary 1 XOS20 B CS2OxL vatoo Ta1a4 Paz08 enary veG Pag P1428 P1383 7 10 - PI41 P205 113 vo P90 Pi29 To B84 62 V0 P98 i Pid2 P206 116 10 PS Pia0 185 85 VO, SGCK1 Poo PAB peor VO P92 Biat 2186 6B vec P100 Piaa P208 _ vO P93 Pia2 Bia? 7 GND PI Pt Pt vO : on BBE 74 VO, PGCK1 Pa Pa Pe fe 0 Soma wo Pe pea WO. Pigg P90 80 vo : : P4 Pa 128 yO ~ P95 Pigd PY 83 WO : 1 PS PS 134 VEG : : F192 : VO, TDI PaO Pe Be VO me : P135 193 86 vO, TCK P5 Pe Pr 7 io : 136 BY cae vO PB 140 GND : Pia?) 8S : i : PTO 148 10 ~~ - PIO? 95 /O PY 148 iO : - Bi98 98 i : a Pte 148 10 : : 5199 403 GND - P8 7 PB : 1. P86 Pigs 8200 104 vO : Po 182 vO POF Pi39 2201 107 VO : P10 PIS 185 WO : : 8503 176 vO, TMS Pe Pu P16 $88 WO : : ogg TT ag VO P7 ae PY 161 10 : Piao. 20a 7107 voc : : PxB 4-210 November 25, 1997 (Version 0.6)22 XILINX XGS20 & XCSZOXL vatoo Ta14s Pq208 Breiry | XG8R0 & XCS20XL vatoo | Ta144 Pa208 Baery VO P19 164 VO P3400 PS P75 28 | WO P26 167 10 P35 2 P76 301 iO Pi3 Pa 176 yO (NIT) P36 pag P77 304 vO Ps Pia P22 173 VCC P37 P54 P78 vO Po P15 P23 176 GND P38 PSS P79 - vO P10 P16 P24 179 10 P39 GND Pil Pi7 P25 iO Pao VCC P12 P1a "P26 vO [Pat VO Pid Pig p27 182 vO [| Paa - VO P14 P20 P28 185 0 _ : VO PIs Pat P29 188 oO ~ ~S pBS 22 vO a P22 P30 191 VCC V0 : Pat 494 vo Pag VO P32 197 VO Pad VCC Pas |v | vo Pi6 P23 P34 200 vO PI? Pod P35 203 GND . Oo a P25 P36 206 vO : VO a P26 Pa7 209 vO GND _ P27 P38 _ VO 10 ~P3g 212 uO : iO! : P40 215 vO _ VO Pat 218 vO Pas P65 97 349 vO . Pag 221 vO Pa COPE SCP 352 HO - : Pas 2 vo : PBF Pog 855 uo P28 Pad a4 WO Pa P100 358 VO P29 Pas 27 WO P47 P69 P101 364 Mo . P30 PAE 230 1/0. SGCK3 P48 P70 P102 364 0 P31 Pa? 233 GND Pag Pa PIS a VO. P20 P32 Pas 236 DONE ; P50 P72 P14 _ "yO, SGCK2 Pot PSS Pag 239 vec P54 PIS P05 Don't Connect P22 P34 P50 242 PROGHAM P52 P74 P106 ~ GND P23 P85 P51 - VO PBS P75 P107 367 MODE P24 P36 P52 245 WO, PGCK3 P54 P76 108 370 VCC P25 P37 P53 : VO P109 373 Don't Connect P26 P38 P54 246 vo PHO 376 VO. PGCK2 P27 P3g "PES 247 vO Pitt WO (HDC) P28 PaO P56 280 yO Pos CPS B112 379 WO P4i P57 283 VO P56 SCP Pita 382 WOU Pad P58 256 WO Prid | 385 WO P29 Pag P59 258 VO : PI15 388 vO (LOC) P30 P44 P60 262. | 10 ~T P16 331 vO - Pl 265 VO PB? 384 vO : Pea 265 GND Pat Pit6 - 10 : PS 268 iO : VO Pe4 a" vO Y : P6S 274 vec : GND : P45 P66 io 2|)7)FS*<s~*S*ii WO - Pag P67 277 vO P58 0 : Pay P68 280 al VO P31 Pag P69 283 vO : vo. | P82 [Pag P70 286 WO a) % : P7A V0 P60 P72 289 vo...)7) d~CS ~ P73 292 VO P62 P33 P50 P74 295 vec P63 November 25, 1997 (Version 0.6)Spartan and Spartan-XL. Families Field Programmable Gate Arrays | XeS20 & XCS2OKL vai0o Taras | Pazos | Beary XeS0 B XeS20Xt va1oo ro144 i P64 P91 BP I3t 0, TD0 P76 108 P65 P92 ; R132 427 GND P77 P10 P66 P93 P4133 430 | jo. P78 Pit . ee P13 Bria PIs PT16 BI? ~P118 VO. sae ~P120 P121 Bi22 P123 VO (DIN) P72 P105 Pi24- vO, SGCK4 P73 P106 P125 Piz6 P74 Biov Bie P75 P1086 ae Pin Locations for XCS30 & XCS30XL Devices [ XcBa0 & xcssoxt var0o Ta14s | paz0s pazao | Ba256 Bray | XESO0 & MCSSOXL | vatoo | Ta1a4 | Pages Passo | Baas | BITY Peo | Fi2e | Piea Pat2 | veo i - | VO : Pigg | P204 | P2s Ba 184 Poo) Fi2s | Piad pais 7 C107 WO | : Pia | Pos | Pes7 | Be 137 | Poi | Figo | Pies | paid | DIO [77 | vO Pee | Piae | Peos | Pease | Ae | 140 poo | Fis1 [Pia | Pais [As 80 = WO, SGCK1 Poo | Pras | Paor | Paso | ca | 43 Poa | Pia2 | Prey | Pate | Bo 83 vec Prog | Pisa | Peog | Peao | VeCe ry Pis | P2i7 | 8 86 GND Pr {Prop Pr Pr | GND 7 Pigg Pare Be a9 vO, PGCKI Pe | Pa Pe Pe Br 46 P94. 6733 ~~ Piso | R220 7 AB s JO Ps | PSPS Po; oe ae pgs | iad igi 7 Peet BB a vo _ . Pa P4 Pa be | 152 Pise | Page | vec vO - : PS | OPS 185 : : Paes [AG 88 vO, TDI t Pa | P6 6 158 : DO pea TSF tar WO, TOK PaO Pr | Pr 61 pias | pig3 | P2285] Be 104 | VO Pa Ps Di | $64 Biss | Pisa "Base | AS OF | : - | Po PS eS | er BTa7 | Pid5 P27 | GND* ~ vO Po Po | Fe | 170 ye Bi96; Page | Ge ito fo : PM Puy Et 3 OT Pid? -P229 [BS 4a _ Pra | Fe | 16 yet Pisa | P230; Ad) 116 PAS : Pigg | Pasi Ge ie | | Pe oy PIs Pia P96 | Pige | P200 | Pa32 Ba | 122 | Poy Pia PIS por PT pias 7 RaoT 7 P2330 125 | : Pro PIS PIS Ge - pae3 | pega 135 P Pi Big 7 a ~~ aod | P2as ~~ t8t Pry Piz) Piz Pie HS November 25, 1997 (Version 0.6)= XILINX | eee ee Xt | varoo | Taras | pazos | Pazso | Bazss | BMdry eee txt | vatoo | Tava | pazos | pags | Bazs6 Bndy VOC 5 - Pia Pia VCC - VO - Pa? | Pe Pi7 V7 334 0 ope : ag Ha iad "O) Pa | Bae aS Ba Ve aa vO - _ - Pat Hi 197 Me) P32 Pag 7 P70 | P79 we 340 0 : - Big Baa BGG ee : rs a ol vO - =) B29 P24 a 203 vO " - BPE Pat 8 343 vO - a P25) K2 206 VO : - PPB 1 P82 us| 346 VO Pa Pi4 P22 P26 KS 209 VO - oT Pad Ye 7348 vo Poo) PIs Bas PPAF KT ae Ng : a Pas | Wio | 352 VO Pid Pig | P24 Pag LA 216 VO P33 P50 P74) P8E vio | 368 GND Pit) PI P28 P29) GND" - | VO P34 P51 | P76 P87 Yio | 368 veo! P12 P18 Pee | Pag VGC : vO. P35 P52 P76 Pas Yir | 364 iO P13 Pig P27 P31 | Bia VO (INIT) P36 P53 PT? Pag | Wit | 364 0 Pi4 P20 P28 P32 U3 221 vec P37 P54 P78 Psa | VCC" - V0 P15 Pat Pag P33 4 224 "GND P38 p55. | P7a | Pot | GND - vo - P22 P30 P34 [Mt 227 V0 P39 P56 Peo P92 Vit ' 367 VO : : Por Pas Me 230 VO Pad | P87 Ber Bea un 370 VO : > P32 P36 M3 233) VO - Pat PSB | P82 Poa; i2 ava vO - - - Pag Ni 236 | VO P42 | P59 | Pas p95 | Wi2(876 10 oe - P39 Na 239 vo)77SOdNCOSdS P96 Vi2 1 379 VOC SP P33 Pao | VCC* : af pgs pa? Uiz | 382 WO P16 P23 P34 Pat PA oe - P99 VIZ) 385 vO PI? | P24 P35 P42 [Po ope P100 | Yia | 388 WO - P25 P36 P43 Ai : : Pas | P101 | VGC VO : 726 P37 Pag P3 P43 PEO Pe? Pio2_ | Yi5 | 391 GND - P27 P38 Pas | GND* P44 Pei | Pas , Pi0s | Via | 394 | iO - pT : Pas 7 Pe2 | Pao) Pidd | WIS | 397 Wo... Od y Paz ] T Pa Pi05Y16 | 400 i : "Pag T2 : P106 | GND io. - - Pat Pag Ut - Pio? VIB | 403 10 - : Pag P50 ~C*TS - Pi0g. = Wi | 406 0 : : P43 Pere PIOg. VIF | 409 vO P18 P28 Pad Pea) VA P10) VI6 | 472 vO P19 P29 P45 PS3 4 Pit | Wi?) 495 VO : P30 P46 P54 ua Pilg | i8 | 478 VO PR 8H Pa? Pas v2 P45 Pig | Ute vO P20. P32 P48 P56 wi P46 Pit4 Wi7 VO, SGCK2 P2i P33 i) P57 v3 | Pins wis Don't Connect P22 P34 P50 P58 we TP P6E TP IO0 PI6 | i9 GND P23 P35 P5t P59 | GNDY P47 6S PIO PVF Vie MODE P24) P36 P52 Peo vi 293 VO, SGCK3 Pas Pigg P18 | W19 VCC P25 P37 P53 Per | vec - GND Pigs Pig | GND | Don't Connect P26 | P38 P54 P62 W3 294 DONE Pi04 , P120 Y20 HO, PGCK2 P27 | P39) P55 P63 Y2 | 295 VCC Pios Pi2t | VCC VO (HDC} Peg "P40 P56 Pea WA} BSB PROGRAM Pid6 Pia2 | Vi9 iG - PS7 Pes 4 | 801 VO P75 1g? Pi2a U9 | 439 VO P58 PEE us 304 VO, PGCK3 P54 P76 P108 |) P1244) U1a | 442 vO : | Peo | Per | 8 | 307 WO | Pr Pog P12 | TIF 445 vO (LDC) P30 | Paa Peo PEs Ya | 310 | yO : Pra) prio P26 va0 448 VO ee Pet Peo V5) 313 VO - . R127 2048 VO Pe Pe2 P70 We | 316 VO - : Pili Pi28 | Tig 454 VO - : P63 P74 5 | 3i9 VO P55 P79 (Pitz -Pi2g | Ti9) 457 V0 - : P64 P72 ve | 322 VO P56 PEO | PITS P1307 120 460 vO : ; Pa 873 we | 325 vO - : Pil4d.) Pi3i, RIB | 463 WO : : : P74 Ye | 328 vO - - PHS | P1382 Rig 1 466 GND > f P45 P6 P75 GND* - 0 - - | PIG P133 R20 | 469 i) _ Ae en nL wh PI Pisa Pts ae November 25, 1997 (Version 0.6) 4-213Spartan and Spartan-XL Families Field Programmable Gate Arrays XeSa0 & XCSSOXL Pozos eaass | Ser _ NES30.&XCS3OXL | vatoo | Taiad | Poza | Pazo | BG256 _ Bary GND P18 GND* - VO - - Pies > P189 Cie; 20 iO _ ; P20 475 vO - pe - PIG | BIE [23 VO : Nig (478 Pri7 | Pree | Pigi Ale 26 vO Prig Nis | 481 Pievy | Pis2 0 CIS 29 vO Pi20 N20) 484 vO - : Pise | P193 BIS 32 voc Piz} vec* : vO : : Pigs | Piog AIS 35 Oo P122 Mi7 | 487 GND - Pita: Pi7o | P1968 GND* VO P1233 Mig | 490 VO ; PHO PI71 | 197 B14 38 VO Pi24 M20 | 493 lO - Piz0 ) Pi72 | P198 Aid 41 "vO PI25 Lis 496 VO : - : Pigg cra 44 a P4126 Lis 499 | VO - - : P200 Bis a7 yl Pi27 120 502 vec : : PI7s = Bagot | vec" ay P128 K20 505 V0 Pg2. P12t | PI74 | ~P202 C12 50 0 P1329 Ki9 508 vO P33 Pi22 P203 B12 53 VEC "P130 vec* - - 205 Ala GND P131 GND : P206 Bit WO P1g2 Kia Pad P1233 207 ci vO P133 Ki7 P85 P1234 P208 An WO Pi34 J20 at? Pes Pi26 Piao || P29 Aid 68 40 P135 Jig 520 | P87; P126 , Piai | P2i0 ; 810 71 tbo P136 Te Sa Peg P12?) P1a2 Patt | GND* : a P137 S17 526 27 bic Pia8 a6 528 Pads labelled GND* or VCC* are internally bonded to Ground or : LO 139 ig 538 vec planes within the package. They have no direct connection to veo tig 1 Jee any specific package pin. WO Pi4i Gis iO _ Pia2 (| Feo Additional XCS30/XL Package Pins yO _ Gis HO aad Pazdo _ (GND GND" __ GND Pins - iO Fig Paat | Pa7 | Pea [ Poet | Praag [ P158t ue a paode | Petey | LO i Not Connected Pins . ee 96 OT = oe 4 $ Pins marked with this symbo! are used for Ground connections on ee ox Be some revisions of the device. These pins may not physically con- SRE nect to anything on the current device revision, However, they 4 should be externally connected to Ground, if possible. Dis [bes | - cia) bt B20 574 VO (IN) cis | 87 VO, SGCKA BIg 880 (DOUT) __ CCLK P155 vec P156 0, TDO PIs? GND WO Net Connected Ping HO, PECK 4. a a WO jo MA v8. 7 WO ~ ~ vO vO. 4-214 November 25, 1997 (Version 0.6)$2 XILINX Pin Locations for XCS40 & XCS40XL Devices XCS40 & XGSAOKL panes panto pazse Bndry Xegto & XCSAOXL Pazos Pazdo BG2s6 nary | VCC P83 P22 vec" - vO P20 Ped an _ 238 lO Pipa P2138 cio 86 oO p2t P25 ke 242 0 Pigs P24. To 89 vO Pee Pe Ks 25 V0 Pig Pais AB 92 vo Pee Per mt eae 0 Pia? P2t6 89 96 vO | Pea __ Pee a 25 vO Pisa P2i7 co 98 GND | Ps P29 GND" oe iO. Pies | Pate 68 or voc P26 P30 vec" : V Piso P220 AB oa ie) 7 per ai Le loo Bin Basi a ie vO ~ P28 P32 is ar 40 ae : oe it0 VO 7 nc) i4 a 10 - - Ay Ta 10 a p34 i Mt 263 veo. Pigg) Paz vee" - vO _ Pst P86 Me Bee io men Bobs AE Tie 0 P32 a) M3 269 _ ~ P224 "CF 119 vo : Mee P2265 58 122 vo , __ P38 Nt ze P226 AS 1260 vO : P39 Ne 281 PaD? GND : VGC Pas Pag veo P228 C6 128 : vo P34 Pat Pt BB BaB8 BE ai 1 0 P35 pan P2 287 SCCS B80 aa {a4 VO ~ P36 P43 Rt 290 baat cS 137 vo PS? Rae P3 23 232 B4 ogo GND ~ P38 P45 ~GND* P2383 Aa 143 VO - PaaS Ti 296 : P2346 DS 152 vO P3e Par aa 298 : 236 ca 65 vO Pag Pas we 302 P2B6 ER 158 vO Pad pag 808 Peay Tet ' i vo P42 P50 13 : 308 mre 7) ia VO ~ P43 Pst) an vo, SOCK Bae Tae 3 tay VO P44 P52 vt 320 vec 208 240 veo" : : vO Pas PS3 am GND ar Pt au VO Pag P54 us VO, PGCK1 7 2 Bi "F7 vO : Pa7 Pes ve iG Bs a ag ia vO Paa P56 wi oy WO Pa ea BEE VO, SGCK2 Pas Ps? v8 38 a P5 pS 179 Don't Connect PSo P88 we 338 P PS Es 8 GND _ P51 a) GND : P?.OUL*Ci Cl 185 MODE _ Pe ica 4 aa Pa Pg ot 194 ee psa : P61 voce - Pg PO Ea Don't Connect Pea Pee we Pi0 BiG EB 200 yO PGCK2 PSs P63 ev TCUMS Bri Pit Ej 303 vO (HDC) P86 Pea we VO Pi2 Pi2 i) vO PS7 Pes Va 35 O - Bg 0 P58 Bes Us 352 GND 7 anor - VO [8 Per Ye 886 vO Pia P15 G3 : 212 vo (TBC) Pea Poe v4 38 WC PS : Pig G2 : 215 VO P61 Pee v8 | 367 0, TMS PI6 PIT Gt 218 vO ; {Pe ; P70 NS | 370 WO Piy SOT H3 ma vO Pea prt 5 373 yoo Be a ee vO Pes fe ve are 10 : P20 H2 : aa vO Pe6 a78 vO : BBY Hi BaF vO - 382 io. oe : WA 7330 GND Pee : HO : : Ba vO POT ae Se ir P19 Poa B a Ke) Pee ian . 388 November 25, 1997 (Version 0.6) 4-215Spartan and Spartan-XL Families Field Programmable Gate Arrays KOSAO & XCSAOXL Pazoa paso BG256 erary KOS i NCSAOXL Ppazos | Base faery vO Ped P78 ve 391 VO Pts i R19 Bag vO P7G P79 Ws 394 VO P16 R20 547 vec P71 P80 vec : vO Pity PIs 550 vO P72 Pat Ye 397 GND Pits GNO* 0 P73 Pez us 400 v0 : ' P29 553 VO : v9 403 vO : : NI oO vO - wo 406 0 P19 Nig ~ ~ 0 Ped Yo 408 VO Pi20 N20 vO : Pas Wio 412 Pi2t . vO P74 P86 Waa 415 i VO Pi22 . M17 565 iO P75 P87 10 418 10 Piza VO P76 Pas vit 424 0 0 (NTT) PY? bd wit 424 i VO Piza vec P76 P90 yee VO Pi2s GND P7O P91 GND* 0 P126 10 Pao P92 Vii 427 VO [Pie vO Pat P93 uit 430 vO Pize VO P&Z P94 viz 433 VO P129 VO P83 P95 wi2 436 | vec P7130 VO P84 POS viz 439 GND Pi3t iO Pas P97 ute Pig2 VO - vis P133 VO : wia P4a4 VO P99 Vi3 P13 YO - P100 Y14 P136 yec P&G Pidi vee" P137 vO P87 P12 Yis vO PBS F103 via P1386 v0 P89 P14 Wid P139 WO Poo P1085 Yi6 P140 GND POI P106 GND Prat VO P07 vis Pide 10 P92 P18 wis VO P93 PiD9 V7 : VO Pad Pri0 vie P143 WO P95 Pitt wi? Fis VO POG Pi vie Pi44 E19 840 VO Pa? Pit3 ut6 P14 20 643 VO Pgs PIA Vay Pi46 E18 646 WO P99 Pits wig PI? Die VO P1600 PH6 vie P148 C20 VO Piot Pit? vie P149 E17 HO. SGCK3 Pi02 Pit8 wig P150 Dis GND Pi08 Pit9 GNO* VO PI5t Cis DONE Pigs P126 ve : vO Pi62 B20 voc P1085 Ptat vec WO (DIN) P153 Cia 673 PROGRAM P106 PiZ2 vis V0, SACKa Pisa BIg 76 VO PiG? P1238 uis (DOUT) 0. PGCK3 P4108 Piz uta Pt68 vo Pied Pigs TW Bi7 P156 VO PO Pi26 v20 520 PIs? oe VO Pili Piz8 118 526. vO Pisa e VO Pie PiZ9 719 a vO, PGCK4 P160 Se oO ~ PTS P130 120" 38 vO - PI6t & uO pris Pia Rie Ba WO Pe? a 4-216 November 25, 1997 (Version 0.6)$2 XILINX XCS40.&XCS4OXL | Ooo, pazdo 8a256 Bndry Additional XCS40/XL Package Pins Pad Name Scan vO Pies Pre? Ate 14 POO cnt 0 Pi64 Pige Ai? 7 i GND Pins . am Big 5 paag | Pa7t eae Peat Piagy Ho [ Paoat | P2tot op - | Uf CUTS uO Prs0 Bie 29 [ "Not Connected Pins ~ WO P166 P1941 AI6 32 1 P1956 L. - | - [ ~ 7 vO pier Pree ors 38 + Pins marked with this symbol are used for Ground connections on 10 P16 Pies Bis 38 some revisions of the device. These pins may not physically con- vO F169 Pre ANS 4 nect to anything on the current device revision. However, they GND P176 P196 GND* should be externally connected to Ground, if possible. vo Pq?t Pig? Bi4 a4 vO P198 Ala 47 VO : Pigg C13 50 BG256 VO 7 P200 B13 5a - _ - vee BI7a F201 vec" VO - ANZ 56 vo Diz 59 vo PI74 P2902 ce 62 vO PIS F203 Bi2 a5 vO PI76 F208 6a Ke) PA?7 P206 74 V0 Pi78 P207 7a vo P179 P208 77 10 P180 P209 80 vo P18t P210 83 GND P1a2 Pet 123/97 _ November 25, 1997 (Version 0.6) 4-217Spartan and Spartan-XL Families Field Programmable Gate Arrays Product Availability Table 16 shows the packages and speed grades for Spartan Series devices. Table 17 shows the number of user 1Os avalable for each device/package combination. Table 16: Component Availability Chart for Spartan Series FPGAs PINS 84 100 144 208 240 256 TYPE | Plast. PLCC | Plast. VQFP | Plast. TQFP | Plast. PQFP | Piast. PQFP | Plast. BGA Device CODE PC84 VQ100 TQ144 PQ208 PQ240 BG256 3 Ci) C(I) XCS05 ri j C 3 Cti) C(I) Cl) XCS1 oo cs iA Cc Cc -3 C(I) C(I) cil) 2 XCS20 7 C C C 3 Ci) cil) cil) Cc c(h XCS30 -4 Cc Cc Cc Cc Cc -3 C(I) Cil) CCl) XCS4 cS40 4 C C -3 Ci) Cl) XCSO5XL 4 C C -3 Cl) C(I) CD XCS10XL 3 c C C 3 Ci) Cth) C(t) een TS C c c -3 C(I) Ci!) C(I) C{l) Ci) XCS30XL 4 C C c 6 C 3 C(I) ci) Cil) XCS40XL a G C C 9/24/97 C = Commercial Tj = 0 to +85C \= Industrial Tj = -40C to +100C Table 17: User I/O Chart for Spartan Series FPGAs Max Package Type Device vo PC84 | VQ100 TQ144 PQ208 PQ240 BG256 XCS05 80 61 TF xCS10 112 61 77 112 XCS20 160 77 113 160 ~ XCS30 192 77 113 169 192 192 XCS40 224 169 193 205 XCSOSXL 80 61 77 XCS10XL 112 61 7? 112 XCS20XL 160 77 413 160 f XCS30XL~Ssd|:ss192 77 113 169 192 192 XCS40XL 224 169 193 205 9/24/97 4-218 November 25, 1997 (Version 0.6)$= XILINX Ordering Information Example: XCS20XL-3 PQ208C Device Type __| L_ Temperature Range C = Commercial (Tj = 0 to +85C) | = industrial (Ty = -40 to +100C) Speed Grade a Number of Pins Package Type BG = Ball Grid Array VQ = Very Thin Quad Flat Pack PC = Plastic Lead Chip Carrier TQ = Thin Quad Flat Pack PQ = Plastic Quad Flat Pack November 25, 1997 (Version 0.6) 4-219