Revision 18 Axcelerator Family FPGAs Leading-Edge Performance * * * * 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications * * * * * Up to 2 Million Equivalent System Gates Up to 684 I/Os Up to 10,752 Dedicated Flip-Flops Up to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal Features * * * * * Single-Chip, Nonvolatile Solution Up to 100% Resource Utilization with 100% Pin Locking 1.5 V Core Voltage for Low Power Footprint Compatible Packaging Flexible, Multi-Standard I/Os: - 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation - Bank-Selectable I/Os - 8 Banks per Chip - Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3 V PCI-X - Differential I/O Standards: LVPECL and LVDS * * * * * * * - Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 - Registered I/Os - Hot-Swap Compliant I/Os (except PCI) - Programmable Slew Rate and Drive Strength on Outputs - Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory: - Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18, x36 Organizations Available) - Independent, Width-Configurable Read and Write Ports - Programmable Embedded FIFO Control Logic Segmentable Clock Resources Embedded Phase-Locked Loop: - 14-200 MHz Input Range - Frequency Synthesis Capabilities up to 1 GHz Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Microsemi Silicon Explorer II Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG) FuseLockTM Programming Technology Protects Against Reverse Engineering and Design Theft Table 1 * Axcelerator Family Product Profile Device Capacity (in Equivalent System Gates) Typical Gates Modules Register (R-cells) Combinatorial (C-cells) Maximum Flip-Flops Embedded RAM/FIFO Number of Core RAM Blocks Total Bits of Core RAM Clocks (Segmentable) Hardwired Routed PLLs I/Os I/O Banks Maximum User I/Os Maximum LVDS Channels Total I/O Registers Package PQ BG FG CQ CG March 2012 (c) 2012 Microsemi Corporation AX125 AX250 AX500 AX1000 AX2000 125,000 82,000 250,000 154,000 500,000 286,000 1,000,000 612,000 2,000,000 1,060,000 672 1,344 1,344 1,408 2,816 2,816 2,688 5,376 5,376 6,048 12,096 12,096 10,752 21,504 21,504 4 18,432 12 55,296 16 73,728 36 165,888 64 294,912 4 4 8 4 4 8 4 4 8 4 4 8 4 4 8 8 168 84 504 8 248 124 744 8 336 168 1,008 8 516 258 1,548 8 684 342 2,052 208 208 256, 484 208, 352 484, 676 208, 352 729 484, 676, 896 352 624 896, 1152 256, 352 624 256, 324 i Axcelerator Family FPGAs Ordering Information AX1000 _ 1 FG G 896 I Application Blank = Commercial (0 to +70 C) PP = Pre-Production I = Industrial (-40 to +85 C) M = Military (-55 to +125 C) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type BG = Ball Grid Array (1.27mm pitch) FG = Fine Ball Grid Array (1.0mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) CQ = Ceramic Quad Flat Pack (0.5mm pitch) CG = Ceramic Column Grid Array Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard Part Number AX125 = 125,000 Equivalent System Gates AX250 = 250,000 Equivalent System Gates AX500 = 500,000 Equivalent System Gates AX1000 = 1,000,000 Equivalent System Gates AX2000 = 2,000,000 Equivalent System Gates Device Resources User I/Os (Including Clock Buffers) Package AX125 AX250 AX500 AX1000 AX2000 PQ208 - 115 115 - - CQ208 - 115 115 - - CQ256 - - - - 136 FG256 138 138 - - - FG324 168 - - - - CQ352 - 198 198 198 198 FG484 - 248 317 317 - CG624 - - - 418 418 FG676 - - 336 418 - BG729 - - - 516 - FG896 - - - 516 586 FG1152 - - - - 684 Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint compatible with one another. ii R evis i o n 18 Axcelerator Family FPGAs Axcelerator Family Device Status Axcelerator(R) Devices Status AX125 Production AX250 Production AX500 Production AX1000 Production AX2000 Production Temperature Grade Offerings Package AX125 AX250 AX500 AX1000 AX2000 PQ208 - C, I, M C, I, M - - CQ208 - M M - - CQ256 - - - - M FG256 C, I C, I, M - - - FG324 C, I - - - - CQ352 - M M M M FG484 - C, I, M C, I, M C, I, M - CG624 - - - M M FG676 - - C, I, M C, I, M - BG729 - - - C, I, M - FG896 - - - C, I, M C, I, M FG1152 - - - - C, I, M C = Commercial I = Industrial M = Military Speed Grade and Temperature Grade Matrix Temperature Grade Std -1 -2 C 3 3 3 I 3 3 3 M 3 3 - C = Commercial I = Industrial M = Military R ev i si o n 1 8 iii Axcelerator Family FPGAs Packaging Data Refer to the following documents located on the Microsemi SoC Products Group website for additional packaging information. Package Mechanical Drawings Package Thermal Characteristics and Weights Hermatic Package Mechanical Information Contact your local Microsemi representative for device availability. iv Revision 18 Axcelerator Family FPGAs Table of Contents General Description Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-7 1-8 1-8 Detailed Specifications Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66 Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110 Package Pin Assignments BG729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 FG1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84 CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94 CQ352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98 CG624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 R ev i si o n 1 8 v 1 - General Description Axcelerator devices offer high performance at densities of up to two million equivalent system gates. Based upon the Microsemi AX architecture, Axcelerator has several system-level features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. Device Architecture AX architecture, derived from the highly-successful SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike in traditional FPGAs, the entire floor of the Axcelerator device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element The Axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, low-impedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the Axcelerator family abundant routing resources. The very nature of Microsemi's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock technology). Typical cloning attempts are impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-108). Routing Switch Matrix Logic Block Sea-of-Modules Architecture Traditional FPGA Architecture Logic Modules Figure 1-1 * Sea-of-Modules Comparison R ev i si o n 1 8 1 -1 General Description Figure 1-2 * Axcelerator Family Interconnect Elements Logic Modules Microsemi's Axcelerator family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The Axcelerator device can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3). FCI A[1:0] D B[1:0] D[3:0] C-cell Y DB E CLK PSET Q CLR CFN (Positive Edge Triggered) FCO C-Cell Figure 1-3 * R-Cell AX C-Cell and R-Cell The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. 1- 2 R ev isio n 1 8 Axcelerator Family FPGAs Two C-cells, a single R-cell, two Transmit (TX), and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-androute tool, minimizing system delays while improving logic utilization. C Figure 1-4 * C R TX TX RX RX B TX TX RX RX C C R AX SuperCluster The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-byside, giving a C-C-R - C-C-R pattern to the SuperCluster. This C-C-R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). FCI DCOUT C-Cell C-Cell Y Y Carry Logic FCO Figure 1-5 * AX 2-Bit Carry Logic The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the AX1000 is composed of a 3x3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250). Table 1-1 * Number of Core Tiles per Device Device Number of Core Tiles AX125 1 regular tile AX250 4 smaller tiles AX500 4 regular tiles AX1000 9 regular tiles AX2000 16 regular tiles R ev i si o n 1 8 1 -3 General Description The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6 on page 1-4). SuperCluster C 4k RAM/ FIFO 4k RAM/ FIFO Chip Layout 4k RAM/ FIFO 4k RAM/ FIFO C R TX TX RX RX RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC TX TX RX RX C C R SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SC Core TileSC B I/O Structure See Figure 7 Figure 1-6 * AX Device Architecture (AX1000 shown) Embedded Memory As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. I/O Logic The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all, Axcelerator FPGAs support at least 14 different I/O standards (single-ended, differential, voltage-referenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-11 for more information). All I/O standards are available in each bank. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-5). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module. 1- 4 R ev isio n 1 8 Axcelerator Family FPGAs I/O Module InReg I O B A N K 4k RAM/ FIFO I/O Module TX RX RX OutReg TX B RX RX EnReg I/O Module I/O Cluster 4k RAM/ FIFO 4k RAM/ FIFO CoreTile 4k RAM/ FIFO Figure 1-7 * I/O Cluster Arrangement Routing The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the FCO output of one two-bit, C-cell carry logic to the FCI input of the two-bit, C-cell carry logic of the SuperCluster below it. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. R ev i si o n 1 8 1 -5 General Description Figure 1-8 * AX Routing Structures Global Resources Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-2). Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. Each HCLK and CLK has an associated analog PLL (a total of eight per chip). Each embedded PLL can be used for clock delay minimization, clock delay adjustment, or clock frequency synthesis. The PLL is capable of operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by factors ranging from 1 to 64. Additionally, multiply and divide settings can be used in any combination as long as the resulting clock frequency is between 20 MHz and 1 GHz. Adjacent PLLs can be cascaded to create complex frequency combinations. The PLL can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps increments. The reference clock required to drive the PLL can be derived from three sources: external input pad (either single-ended or differential), internal logic, or the output of an adjacent PLL. Low Power (LP) Mode The AX architecture was created for high-performance designs but also includes a low power mode (activated via the LP pin). When the low power mode is activated, I/O banks can be disabled (inputs disabled, outputs tristated), and PLLs can be placed in a power-down mode. All internal register states are maintained in this mode. Furthermore, individual I/O banks can be configured to opt out of the LP mode, thereby giving the designer access to critical signals while the rest of the chip is in low power mode. The power can be further reduced by providing an external voltage source (VPUMP) to the device to bypass the internal charge pump (See "Low Power Mode" on page 2-106 for more information). 1- 6 R ev isio n 1 8 Axcelerator Family FPGAs Design Environment The Axcelerator family of FPGAs is fully supported by both Microsemi's Libero(R) Integrated Design Environment and Designer FPGA Development software. Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on the Microsemi SoC Products Group website). Libero IDE includes Synplify(R) Actel Edition (AE) from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), and Designer software from Microsemi. Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: * Timer - a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route * NetlistViewer - a design netlist schematic viewer * ChipPlanner - a graphical floorplanner viewer and editor * SmartPower - allows the designer to quickly estimate the power consumption of a design * PinEditor - a graphical application for editing pin assignments and I/O attributes * I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Microsemi's back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Microsemi's integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. Programming Programming support is provided through Silicon Sculptor II, a single-site programmer driven via a PCbased GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Microsemi devices. Factory programming is available for high-volume production needs. In-System Diagnostic and Debug Capabilities The Axcelerator family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation (Figure 1-9). Axcelerator FPGAs 16 Pin Connection TDI TCK Serial Connection TMS Silicon Explorer II TDO PRA PRB 22 Pin Connection CH3/PRC CH4/PRD Additional 14 Channels (Logic Analyzer) Figure 1-9 * Probe Setup R ev i si o n 1 8 1 -7 General Description Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II, Microsemi's integrated verification and logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG port (See "Silicon Explorer II Probe Interface" on page 2-109). Summary Microsemi's Axcelerator family of FPGAs extends the successful SX-A architecture, adding embedded RAM/FIFOs, PLLs, and high-speed I/Os. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an Axcelerator design yet still achieve high performance and efficient device utilization. Related Documents Application Notes Simultaneous Switching Noise and Signal Integrity http://www.microsemi.com/soc/documents/SSN_AN.pdf Axcelerator Family PLL and Clock Management http://www.microsemi.com/soc/documents/AX_PLL_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf User's Guides and Manuals Antifuse Macro Library Guide http://www.microsemi.com/soc/documents/libguide_UG.pdf SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder http://www.microsemi.com/soc/documents/genguide_ug.pdf Silicon Sculptor II User's Guide http://www.microsemi.com/soc/documents/silisculptII_sculpt3_ug.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf Miscellaneous Libero IDE flow diagram http://www.microsemi.com/soc/products/tools/libero/flow.html 1- 8 R ev isio n 1 8 2 - Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommendations in Table 2-2. Table 2-1 * Absolute Maximum Ratings Symbol Parameter Limits Units VCCA DC Core Supply Voltage -0.3 to 1.7 V VCCI DC I/O Supply Voltage -0.3 to 3.75 V VREF DC I/O Reference Voltage -0.3 to 3.75 V VI Input Voltage -0.5 to 4.1 V VO Output Voltage -0.5 to 3.75 V TSTG Storage Temperature -60 to +150 C VCCDA* Supply Voltage for Differential I/Os -0.3 to 3.75 V Note: * Should be the maximum of all VCCI. Table 2-2 * Recommended Operating Conditions Parameter Range Commercial Industrial Military Units Ambient Temperature (TA)1 0 to +70 -40 to +85 -55 to +125 C 1.5 V Core Supply Voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 V 1.5 V I/O Supply Voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 V 1.8 V I/O Supply Voltage 1.71 to 1.89 1.71 to 1.89 1.71 to 1.89 V 2.5 V I/O Supply Voltage 2.375 to 2.625 2.375 to 2.625 2.375 to 2.625 V 3.3 V I/O Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V VCCDA Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V VPUMP Supply Voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 V Notes: 1. Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 2. TJ max = 125C Power-Up/Down Sequence All Axcelerator I/Os are tristated during power-up until normal device operating conditions are reached, when I/Os enter user mode. VCCDA should be powered up before (or coincidentally with) VCCA and VCCI to ensure the behavior of user I/Os at system start-up. Conversely, VCCDA should be powered down after (or coincidentally with) VCCA and VCCI. Note that VCCI and VCCA can be powered up in any sequence with respect to each other, provided the requirement with respect to VCCDA is satisfied. R ev i si o n 1 8 2 -1 Detailed Specifications Calculating Power Dissipation Table 2-3 * Standby Current ICCA ICCDA Standby Standby Current, Current Differential (Core) I/O ICCBANK Standby Current per I/O Bank 2.5 V VCCI 3.3 V VCCI ICCCP1 ICCPLL Standby Current, Charge Pump Standby Current Bypassed IIH, IIL, IOZ2 Units per PLL Active Mode Device Temperature AX125 Typical at 25C 1.5 1.5 0.2 0.3 0.2 0.3 0.01 0.01 mA 70C 15 6 0.5 0.75 1 0.4 0.01 0.01 mA 85C 25 6 0.6 0.8 1 0.4 0.2 0.01 mA 125C 50 8 1 1.5 2 0.4 0.5 0.01 mA Typical at 25C 1.5 1.4 0.25 0.4 0.2 0.3 0.01 0.01 mA 70C 30 7 0.8 0.9 1 0.4 0.01 0.01 mA 85C 40 7 0.8 1 1 0.4 0.2 0.01 mA 125C 70 9 1.3 1.8 2 0.4 0.5 0.01 mA Typical at 25C 5 1.4 0.4 0.75 0.2 0.3 0.01 0.01 mA 70C 60 7 1 1.5 1 0.4 0.01 0.01 mA 85C 80 7 1 1.9 1 0.4 0.2 0.01 mA 125C 180 9 1.75 2.5 1.5 0.4 0.5 0.01 mA Typical at 25C 7.5 1.5 0.5 1.25 0.2 0.3 0.01 0.01 mA 70C 80 8 1.5 3 1 0.4 0.01 0.01 mA 85C 120 8 1.5 3.4 1 0.4 0.2 0.01 mA 125C 200 10 3 4 1.5 0.4 0.5 0.01 mA Typical at 25C 20 1.6 0.7 1.5 0.2 0.3 0.01 0.01 mA 70C 160 10 2 7 1 0.4 0.01 0.01 mA 85C 200 10 3 8 1 0.4 0.2 0.01 mA 125C 500 15 4 10 1.5 0.4 0.5 0.01 mA AX250 AX500 AX1000 AX2000 Notes: 1. ICCCP Active is the ICCDA or the Internal Charge Pump current. ICCCP Bypassed mode is the External Charge Pump current IIH (VPUMP pin). 2. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ. 2- 2 R ev isio n 1 8 Axcelerator Family FPGAs Table 2-4 * Default CLOAD/VCCI CLOAD (pF) VCCI (V) PLOAD (mw/MHz) P10 (mw/MHz) PI/O (mW/MHz)* LVTTL 24 mA High Slew 35 3.3 381.2 267.5 648.7 LVTTL 16 mA High Slew 35 3.3 381.2 225.1 606.3 LVTTL 12 mA High Slew 35 3.3 381.2 165.9 547.1 LVTTL 8 mA High Slew 35 3.3 381.2 130.3 511.5 LVTTL 24 mA Low Slew 35 3.3 381.2 169.2 550.4 LVTTL 16 mA Low Slew 35 3.3 381.2 150.8 532.0 LVTTL 12 mA Low Slew 35 3.3 381.2 138.6 519.8 LVTTL 8 mA Low Slew 35 3.3 381.2 118.7 499.9 LVCMOS - 25 35 2.5 218.8 148.0 366.8 LVCMOS - 18 35 1.8 113.4 73.4 186.8 LVCMOS - 15 (JESD8-11) 35 1.5 78.8 49.5 128.3 PCI 10 3.3 108.9 218.5 327.4 PCI-X 10 3.3 108.9 162.9 271.8 HSTL-I 20 1.5 - 40.9 40.9 SSTL2-I 30 2.5 - 171.2 171.2 SSTL2-II 30 2.5 - 147.8 147.8 SSTL3-I 30 3.3 - 327.2 327.2 SSTL3-II 30 3.3 - 288.4 288.4 GTLP - 25 10 2.5 - 61.5 61.5 GTLP - 33 10 3.3 - 68.5 68.5 N/A 3.3 - 260.6 260.6 N/A 2.5 - 145.8 145.8 Single-Ended without VREF Single-Ended with VREF Differential LVPECL - 33 LVDS - 25 Note: *PI/O = P10 + CLOAD * VCCI2 R ev i si o n 1 8 2 -3 Detailed Specifications Table 2-5 * Different Components Contributing to the Total Power Consumption in Axcelerator Devices Device Specific Value (in W/MHz) Component Definition AX125 AX250 AX500 AX1000 AX2000 P1 Core tile HCLK power component 33 49 71 130 216 P2 R-cell power component 0.2 0.2 0.2 0.2 0.2 P3 HCLK signal power dissipation 4.5 4.5 9 13.5 18 P4 Core tile RCLK power component 33 49 71 130 216 P5 R-cell power component 0.3 0.3 0.3 0.3 0.3 P6 RCLK signal power dissipation 6.5 6.5 13 19.5 26 P7 Power dissipation due to the switching activity on the R-cell 1.6 1.6 1.6 1.6 1.6 P8 Power dissipation due to the switching activity on the C-cell 1.4 1.4 1.4 1.4 1.4 P9 Power component associated with the input voltage 10 10 10 10 10 P10 Power component associated with the output voltage P11 Power component associated with the read operation in the RAM block 25 25 25 25 25 P12 Power component associated with the write operation in the RAM block 30 30 30 30 30 P13 Core PLL power component 1.5 1.5 1.5 1.5 1.5 See table Per pin contribution Ptotal = Pdc + Pac Pdc = ICCA * VCCA Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs s = the number of R-cells clocked by this clock Fs = the clock frequency PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs s = the number of R-cells clocked by this clock Fs = the clock frequency PR-cells = P7 * ms * Fs ms = the number of R-cells switching at each Fs cycle Fs the clock frequency = PC-cells = P8 * mc * Fs mc = the number of C-cells switching at each Fs cycle Fs = the clock frequency Pinputs = P9 * pi * Fpi pi = the number of inputs Fpi = the average input frequency 2- 4 R ev isio n 1 8 Axcelerator Family FPGAs Poutputs = PI/O * po * Fpo Cload = VCCI = po = Fpo = the output load (technology dependent) the output voltage (technology dependent) the number of outputs the average output frequency Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK Nblock = the number of RAM/FIFO blocks (1 block = 4k) FRCLK = the read-clock frequency of the memory FWCLK = the write-clock frequency of the memory PPLL = P13 * FCLK FRefCLK FCLK = the clock frequency of the clock input of the PLL = the clock frequency of the first clock output of the PLL Power Estimation Example This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input, and one LVTTL 12 mA output, with high slew. This design uses one HCLK at 100 MHz. ms = Fs = s = => 1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle) 100 MHz 1080 PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW and Fs = 100 MHz => PR-cells = P7 * ms * Fs = 173 mW mc = 1 (1 C-cell in this shift-register) and Fs = 100 MHz => PC-cells = P8 * mc * Fs = 0.14 mW Fpi ~ 0 MHz and pi= 1 (1 reset input => this is why Fpi=0) => Pinputs = P9 * pi * Fpi = 0 mW Fpo = 50 MHz and po = 1 => Poutputs = PI/O * po * Fpo= 27.10 mW No RAM/FIFO in this shift-register => Pmemory = 0 mW No PLL in this shift-register => PPLL = 0 mW Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL = 276 mW Pdc = 7.5mA * 1.5V = 11.25 mW Ptotal = Pdc + Pac = 11.25 mW + 276mW = 290.30 mW R ev i si o n 1 8 2 -5 Detailed Specifications Thermal Characteristics Introduction The temperature variable in Microsemi's Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + Ta EQ 1 Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P EQ 2 Where: P = Power ja = Junction to ambient of package. ja numbers are located under Table 2-6 on page 2-7. Package Thermal Characteristics The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. jc values are provided for reference. The absolute maximum junction temperature is 125C. The maximum power dissipation allowed for commercial- and industrial-grade devices is a function of ja. A sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and still air is as follows: junction temp. (C) - Max. ambient temp. (C) 125C - 70C Maximum Power Allowed = Max. -------------------------------------------------------------------------------------------------------------------------------------------------- = --------------------------------------- = 4.04 W ja ( C/W) 13.6C/W 2- 6 R ev isio n 1 8 Axcelerator Family FPGAs The maximum power dissipation allowed for Military temperature and Mil-Std 883B devices is specified as a function of jc. Table 2-6 * Package Thermal Characteristics Package Type Chip Scale Package (CSP) Pin Count jc 180 N/A ja Still Air ja 1.0m/s ja 2.5m/s Units 57.8 51.0 50 C/W Plastic Quad Flat Pack (PQFP) 208 8.0 26 23.5 20.9 C/W Plastic Ball Grid Array (PBGA) 729 2.2 13.7 10.6 9.6 C/W Fine Pitch Ball Grid Array (FBGA) 256 3.0 26.6 22.8 21.5 C/W Fine Pitch Ball Grid Array (FBGA) 324 3.0 25.8 22.1 20.9 C/W Fine Pitch Ball Grid Array (FBGA) 484 3.2 20.5 17.0 15.9 C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 13.0 12.0 C/W Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.4 9.4 C/W Fine Pitch Ball Grid Array (FBGA) 12.0 8.9 7.9 C/W 1152 1.8 1 Ceramic Quad Flat Pack (CQFP) 208 2.0 22 19.8 18.0 C/W Ceramic Quad Flat Pack (CQFP)1 352 2.0 17.9 16.1 14.7 C/W Ceramic Column Grid Array (CCGA)2 624 6.5 8.9 8.5 8 C/W Notes: 1. jc for the 208-pin and 352-pin CQFP refers to the thermal resistance between the junction and the bottom of the package. 2. jc for the 624-pin CCGA refers to the thermal resistance between the junction and the top surface of the package. Thermal resistance from junction to board (jb) for CCGA 624 package is 3.4C/W. Timing Characteristics Axcelerator devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-7 should be applied to all timing data contained within this datasheet. Table 2-7 * Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 1.425V) Junction Temperature VCCA -55C -40C 0C 25C 70C 85C 125C 1.4 V 0.83 0.86 0.91 0.96 1.02 1.05 1.15 1.425 V 0.82 0.84 0.90 0.94 1.00 1.04 1.13 1.5 V 0.78 0.80 0.85 0.89 0.95 0.98 1.07 1.575 V 0.74 0.76 0.81 0.85 0.90 0.94 1.02 1.6 V 0.73 0.75 0.80 0.84 0.89 0.92 1.01 Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of - 55C to 175C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. All timing numbers listed in this datasheet represent sample timing characteristics of Axcelerator devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Microsemi's Designer software after place-and-route. R ev i si o n 1 8 2 -7 Detailed Specifications Timing Model I/O Module (Nonregistered) Carry Chain Combinatorial Cell tPY = 2.24 ns Combinatorial Cell I/O LVPECL FCO + LVPECL tDP = 1.66 ns tICKLQ = 0.67 ns tSUD = 0.23 ns tRD2 = 0.53 ns Buffer Module I/O Module (Nonregistered) Combinatorial Cell Buffer Module LVTTL Output Drive Strength = 4 (24 mA) High Slew Rate tBFPD = 0.12 ns tRD1 = 0.45 ns tRD2 = 0.53 ns tRD3 = 0.56 ns Hardwired Clock I/O Module (Non- registered) tPY = 2.99 ns Y tBFPD = 0.12 ns tPD = 0.74 ns tHCKH = 3.03 ns FMAX (external) = 350 MHz FMAX (internal) = 870 MHz I/O tCCY = 0.61 ns tPDC = 0.57 ns I/O Module (Registered) Register Cell Combinatorial Cell tRD1 = 0.45 ns D Q Y I/O Module Register Cell tRCO = 0.67 ns tSUD = 0.23 ns D Q Buffer Module tIOCLKY = 0.67 ns tSUD = 0.23 ns D Q tBPFD = 0.12 ns tPD = 0.74 ns + LVDS tRCO = 0.67 ns tSUD = 0.23 ns tRCKL = 3.08 ns FMAX (external) = 350 MHz FMAX (internal) = 870 MHz Routed Clock tDP = 1.80 ns Hardwired or Routed Clock tHCKL = 3.02 ns tRCKL = 3.08 ns Note: Worst case timing data for the AX1000, -2 speed grade Figure 2-1 * Worst Case Timing Data Hardwired Clock - Using LVTTL 24 mA High Slew Clock I/O External Setup = (tDP + tRD2 + tSUD) - tHCKL = (1.72 + 0.53 + 0.23) - 3.02 = -0.54 ns Clock-to-Out (Pad-to-Pad) = tHCKL + tRCO + tRD1 + tPY = 3.02 + 0.67 + 0.45 + 2.99 = 7.13 ns Routed Clock - Using LVTTL 24 mA High Slew Clock I/O External Setup = (tDP + tRD2 + tSUD) - tRCKH = (1.72 + 0.53 + 0.23) - 3.13 = -0.65 ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tPY = 3.13 + 0.67 + 0.45 + 3.03 = 7.24 ns 2- 8 R ev isio n 1 8 tPY = 1.13 ns GTL + 3.3 V Axcelerator Family FPGAs I/O Specifications Pin Descriptions Supply Pins GND Ground Low supply voltage. VCCA Supply Voltage Supply voltage for array (1.5V). See "Operating Conditions" on page 2-1 for more information. VCCIBx Supply Voltage Supply voltage for I/Os. Bx is the I/O Bank ID - 0 to 7. See "Operating Conditions" on page 2-1 for more information. VCCDA Supply Voltage Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. See "Operating Conditions" on page 2-1 for more information. VCCDA should be tied to 3.3V. VCCPLA/B/C/D/E/F/G/H Supply Voltage PLL analog power supply (1.5V) for internal PLL. There are eight in each device. VCCPLA supports the PLL associated with global resource HCLKA, VCCPLB supports the PLL associated with global resource HCLKB, etc. The PLL analog power supply pins should be connected to 1.5V whether PLL is used or not. VCOMPLA/B/C/D/E/F/G/H Supply Voltage Compensation reference signals for internal PLL. There are eight in each device. VCOMPLA supports the PLL associated with global resource HCLKA, VCOMPLE supports the PLL associated with global resource CLKE, etc. (see Figure 2-2 on page 2-9 for correct external connection to the supply). The VCOMPLX pins should be left floating if PLL is not used. VPUMP Supply Voltage (External Pump) In the low power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches VIH1. In normal device operation, when using the internal charge pump, VPUMP should be tied to GND. Axcelerator Chip 250 1.5 V Supply VCCPLX 10 f 0.1 f VCOMPLX Figure 2-2 * 1. VCCPLX and VCOMPLX Power Supply Connect When VPUMP = VIH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-106. R ev i si o n 1 8 2 -9 Detailed Specifications User-Defined Supply Pins VREF Supply Voltage Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF pins are not in fixed locations. There can be one or more VREF pins in an I/O bank. Global Pins HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C and D These pins are the clock inputs for sequential modules or north PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are unused, it is recommended that they are tied to ground. CLKE/F/G/H Routed Clocks E, F, G, and H These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking the R-cells. When the CLK pins are unused, Microsemi recommends that they are tied to ground. JTAG/Probe Pins PRA/B/C/D Probe A, B, C and D The Probe pins are used to output data from any user-defined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins' probe capabilities can be permanently disabled to protect programmed design confidentiality. The probe pins are of LVTTL output levels. TCK Test Clock Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II). TDI Test Data Input Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal 10 k pull-up resistor. TDO Test Data Output Serial output for JTAG boundary-scan testing. TMS Test Mode Select The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal 10 k pull-up resistor. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a 10 k pull-up resistor. Special Functions LP Low Power Pin The LP pin controls the low power mode of Axcelerator devices. The device is placed in the low power mode by connecting the LP pin to logic high. To exit the low power mode, the LP pin must be set Low. Additionally, the LP pin must be set Low during chip powering-up or chip powering-down operations. See "Low Power Mode" on page 2-106 for more details. NC No Connection This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. 2- 10 R ev i sio n 1 8 Axcelerator Family FPGAs User I/Os2 Introduction The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-8 on page 2-12 contains the I/O standards supported by the Axcelerator family, and Table 2-10 on page 2-12 compares the features of the different I/O standards. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. The slew rate setting is effective for both rising and falling edges. I/O standards, except 3.3 V PCI and 3.3 V PCI-X, are capable of hot insertion. 3.3 V PCI and 3.3 V PCIX are 5 V tolerant with the aid of an external resistor. The input buffer has an optional user-configurable delay element. The element can reduce or eliminate the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature and voltage changes. Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). I/Os are organized into banks, and there are eight banks per device--two per side (Figure 2-6 on page 2-18). Each I/O bank has a common VCCI, the supply voltage for its I/Os. For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a VREF. The location of the VREF pin should be selected according to the following rules: * Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. * I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF pin. * Dedicated I/O pins such as GND and VCCI are counted as part of the 16. * The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only be used as inputs. The exception is when there is a VCCI/GND pair separating the VREF pin and the user I/O pad location. * The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed only for input and bidirectional I/Os. The differential amplifier supply voltage VCCDA should be connected to 3.3 V. A user can gain access to the various I/O standards in three ways: * Instantiate specific library macros that represent the desired specific standard. * Use generic I/O macros and then use Designer's PinEditor to specify the desired I/O standards (please note that this is not applicable to differential standards). * A combination of the first two methods. Refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library Guide for more details. 2. Do not use an external resister to pull the I/O above VCCI for a higher logic "1" voltage level. The desired higher logic "1" voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI. R ev i si o n 1 8 2- 11 Detailed Specifications Table 2-8 * I/O Standards Supported by the Axcelerator Family Input/Output Supply Voltage (VCCI) Input Reference Voltage (VREF) Board Termination Voltage (VTT) LVTTL 3.3 N/A N/A LVCMOS 2.5 V 2.5 N/A N/A LVCMOS 1.8 V 1.8 N/A N/A LVCMOS 1.5 V (JDEC8-11) 1.5 N/A N/A 3.3V PCI/PCI-X 3.3 N/A N/A GTL+ 3.3 V 3.3 1.0 1.2 I/O Standard GTL+ 2.5 V* 2.5 1.0 1.2 HSTL Class 1 1.5 0.75 0.75 SSTL3 Class 1 and II 3.3 1.5 1.5 SSTL2 Class1 and II 2.5 1.25 1.25 LVDS 2.5 N/A N/A LVPECL 3.3 N/A N/A Note: *2.5 V GTL+ is not supported across the full military temperature range. Table 2-9 * Supply Voltages VCCA VCCI Input Tolerance Output Drive Level 1.5 V 1.5 V 3.3 V 1.5 V 1.5 V 1.8 V 3.3 V 1.8 V 1.5 V 2.5 V 3.3 V 2.5 V 1.5 V 3.3 V 3.3 V 3.3 V Table 2-10 * I/O Features Comparison I/O Assignment LVTTL Clamp Diode Hot Insertion 5V Tolerance No Yes Yes1 Yes 1, 2 Input Buffer Enabled/Disabled Enabled/Disabled 3.3 V PCI, 3.3 V PCI-X Yes No LVCMOS 2.5 V No Yes No Enabled/Disabled LVCMOS 1.8 V No Yes No Enabled/Disabled LVCMOS 1.5 V (JESD8-11) No Yes No Enabled/Disabled Voltage-Referenced Input Buffer No Yes No Differential, LVDS/LVPECL, Input No Yes No Enabled Enabled/Disabled Disabled3 Differential, LVDS/LVPECL, Output No Yes No Disabled Enabled4 Notes: 1. 2. 3. 4. 2- 12 Output Buffer Can be implemented with an IDT bus switch. Can be implemented with an external resistor. The OE input of the output buffer must be deasserted permanently (handled by software). The OE input of the output buffer must be asserted permanently (handled by software). R ev i sio n 1 8 Axcelerator Family FPGAs 5 V Tolerance There are two schemes to achieve 5 V tolerance: 1. 3.3 V PCI and 3.3 V PCI-X are the only I/O standards that directly allow 5 V tolerance. To implement this, an internal clamp diode between the input pad and the VCCI pad is enabled so that the voltage at the input pin is clamped, as shown in EQ 3: Vinput = VCCI + Vdiode = 3.3 V + 0.7 V = 4.0 V EQ 3 The internal VCCI clamp diode is only enabled while the device is powered on, so the voltage at the input will not be clamped if the VCCI or VCCA are powered off. An external series resistor (~100 ) is required between the input pin and the 5 V signal source to limit the current to less than 20 mA (Figure 2-3). The 100 resistor was chosen to meet the input Tr/Tf requirement (Table 2-19 on page 2-21). The GND clamp diode is available for all I/O standards and always enabled. Non-Microsemi Part 5V Mirosemi FPGA 3.3 V 3.3 V VCCI clamp diode Rext Figure 2-3 * GND Clamp Diode Use of an External Resistor for 5 V Tolerance 2. 5 V tolerance can also be achieved with 3.3 V I/O standards (3.3 V PCI, 3.3 V PCI-X, and LVTTL) using a bus-switch product (e.g. IDTQS32X2384). This will convert the 5 V signal to a 3.3 V signal with minimum delay (Figure 2-4). Figure 2-4 * 5V 3.3 V 20X 5V 3.3 V Bus Switch IDTQS32X2384 Simultaneous Switching Outputs (SSO) When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or more commonly, ground bounce. SSN becomes more of an issue in high pin count packages and when using high performance devices such as the Axcelerator family. Based upon testing, Microsemi recommends that users not exceed eight simultaneous switching outputs (SSO) per each VCCI/GND pair. To ease this potential burden on designers, Microsemi has designed all of the Axcelerator BGAs3 to not exceed this limit with the exception of the CS180, which has an I/O to VCCI/GND pair ratio of nine to one. Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more information. 3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio. R ev i si o n 1 8 2- 13 Detailed Specifications I/O Banks and Compatibility Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage (VCCI), only I/Os with compatible standards can be assigned to the same bank. Table 2-11 shows the compatible I/O standards for a common VREF (for voltage-referenced standards). Similarly, Table 2-12 shows compatible standards for a common VCCI. Table 2-11 * Compatible I/O Standards for Different VREF Values VREF Compatible Standards 1.5 V SSTL 3 (Class I and II) 1.25 V SSTL 2 (Class I and II) 1.0 V GTL+ (2.5V and 3.3V Outputs) 0.75 V HSTL (Class I) Table 2-12 * Compatible I/O Standards for Different VCCI Values VCCI1 3.3 V Compatible Standards LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3 V 1.0 3.3 V SSTL 3 (Class I and II), LVTTL, PCI, LVPECL 1.5 2.5 V LVCMOS 2.5 V, GTL+ 2.5 V, LVDS2 1.0 2.5 V LVCMOS 2.5 V, SSTL 2 (Classes I and II), LVDS2 1.25 1.8 V LVCMOS 1.8 V N/A 1.5 V LVCMOS 1.5 V, HSTL Class I 0.75 Notes: 1. VCCI is used for both inputs and outputs 2. VCCI tolerance is 5% 2- 14 VREF R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-13 summarizes the different combinations of voltages and I/O standards that can be used together in the same I/O bank. HSTL Class I (1. 5V) SSTL2 Class I & II (2.5 V) SSTL3 Class I & II (3.3 V) LVDS (2.5 V) - - 3 3 - - - - - 3 LVTTL 3.3 V(VREF=1.5 V) 3 - - - 3 - - - - 3 - 3 LVCMOS 2.5 V (VREF=1.0 V) - 3 - - - - 3 - - - 3 - LVCMOS 2.5 V (VREF=1.25V) - 3 - - - - - - 3 - 3 - LVCMOS1.8 V - - 3 - - - - - - - - - LVCMOS1.5 V (VREF = 1.75 V) (JESD8-11) - - - 3 - - - 3 - - - - 3.3 V PCI/PCI-X (VREF = 1.0 V) 3 - - - 3 3 - - - - - 3 3.3 V PCI/PCI-X (VREF= 1.5 V) 3 - - - 3 - - - - 3 - 3 GTL + (3.3 V) 3 - - - 3 3 - - - - - 3 GTL + (2.5 V) - 3 - - - - 3 - - - - - HSTL Class I - - - 3 - - - 3 - - - - SSTL2 Class I & II - 3 - - - - - - 3 - 3 - SSTL3 Class I & II 3 - - - 3 - - - - 3 - 3 LVDS (VREF = 1.0 V) - 3 - - - - 3 - - - 3 - LVDS (VREF = 1.25 V) - 3 - - - - - - 3 - 3 - LVPECL (VREF = 1.0 V) 3 - - - 3 3 - - - - - 3 LVPECL (VREF = 1.5 V) 3 - - - 3 - - - - 3 - 3 LVPECL (3.3 V) GTL + (2.5 V) - GTL + (3.3 V) LVCMOS1.5 V (JESD8-11) 3 I/O Standard 3.3V PCI/PCI-X LVCMOS1.8 V LVTTL 3.3 V (VREF=1.0 V) LVTTL 3.3 V LVCMOS 2.5 V Table 2-13 * Legal I/O Usage Matrix Notes: 1. Note that GTL+ 2.5 V is not supported across the full military temperature range. 2. A "" indicates whether standards can be used within a bank at the same time. Examples: a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when VREF = 1.0V (GTL+ requirement). b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when VREF = 1.5V (SSTL3 requirement). Note that two I/O standards are compatible if: * Their VCCI values are identical. * Their VREF standards are identical (if applicable). For example, if LVTTL 3.3 V (VREF= 1.0 V) is used, then the other available (i.e. compatible) I/O standards in the same bank are LVTTL 3.3 V PCI/PCI-X, GTL+, and LVPECL. Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all I/O standards used in the bank. R ev i si o n 1 8 2- 15 Detailed Specifications I/O Clusters Each I/O cluster incorporates two I/O modules, four RX modules, two TX modules, and a buffer module. In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg) (Figure 2-5). I/O Cluster Routed Input Track EnReg DIN YOUT Routed Input Track OEP Routed Input Track OutReg DIN YOUT Routed Input Track UOP Output Track InReg DCIN Output Track UIP I/O Slew Rate Drive Strength Programmable Delay VREF FPGA Logic Core Y BSR P PAD N PAD EnReg DIN YOUT Routed Input Track Routed Input Track OutReg DIN YOUT Routed Input Track InReg DCIN Output Track Output Track Y Figure 2-5 * OEN UON UIN BSR Routed Input Track I/O Slew Rate Drive Strength Programmable Delay VREF I/O Cluster Interface Using an I/O Register To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os. Usage of each I/O register (register combining) is individually controlled and can be selected/deselected using the PinEditor tool in the Designer software. I/O register combining can also be controlled at the device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given design.4 In addition, Designer software provides a global option to enable/disable the usage of registers in the I/Os. This option is design-specific. The setting for each individual I/O overrides this global option. Furthermore, the global set fuse option in the Designer software, when checked, causes all I/O registers to output logic High at device power-up. 4. 2- 16 Please note that register combining for multi fanout nets is not supported. R ev i sio n 1 8 Axcelerator Family FPGAs Using the Weak Pull-Up and Pull-Down Circuits Each Axcelerator I/O comes with a weak pull-up/down circuit (on the order of 10 k). These are weak transistors with the gates tied on, so the on resistance of the transistor emulates a resistor. The weak pull-up and pull-down is active only when the device is powered up, and they must be biased to be on. When the rails are coming up, they are not biased fully, so they do not behave as resistors until the voltage is at sufficient levels to bias the transistors. The key is they really are transistors; they are not traces of poly silicon, which is another way to do an on-chip resistor (those take much more room). I/O macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5 V, 1.8 V, and 1.5 V) standards. These macros can be instantiated if a keeper circuit for any input buffer is required. Customizing the I/O * A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (Table 2-14). It is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the I/O). When the input buffer drives a register within the I/O, the delay element is activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer. * The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. * The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values - 8 mA, 12 mA, 16 mA, or 24 mA - that can be specified in Designer.5 Table 2-14 * Bank-Wide Delay Values Bits Setting Delay (ns) Bits Setting Delay (ns) 0 0.54 16 2.01 1 0.65 17 2.13 2 0.71 18 2.19 3 0.83 19 2.3 4 0.9 20 2.38 5 1.01 21 2.49 6 1.08 22 2.55 7 1.19 23 2.67 8 1.27 24 2.75 9 1.39 25 2.87 10 1.45 26 2.93 11 1.56 27 3.04 12 1.64 28 3.12 13 1.75 29 3.23 14 1.81 30 3.29 15 1.93 31 3.41 Note: Delay values are approximate and will vary with process, temperature, and voltage. 5. These values are minimum drive strengths. R ev i si o n 1 8 2- 17 Detailed Specifications Using the Differential I/O Standards Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Note that there are no tristated or bidirectional I/O buffers for differential standards. Using the Voltage-Referenced I/O Standards Using these I/O standards is similar to that of single-ended I/O standards. Their settings can be changed in Designer. Using DDR (Double Data Rate) In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very high-speed systems. To implement a DDR, users need to: 1. Instantiate an input buffer (with the required I/O standard) 2. Instantiate the DDR_REG macro (Figure 2-6) 3. Connect the output from the Input buffer to the input of the DDR macro D D PSET QR QF CLK CLR Figure 2-6 * DDR Register Macros for Specific I/O Standards There are different macro types for any I/O standard or feature that determine the required VCCI and VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and 24 mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals. Most of the macro symbols represent variations of the six generic symbol types: * CLKBUF: Clock Buffer * HCLKBUF: Hardwired Clock Buffer * INBUF: Input Buffer * OUTBUF: Output Buffer * TRIBUF: Tristate Buffer * BIBUF: Bidirectional Buffer Other macros include the following: 2- 18 * Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). * Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs unconnected without having the negative effect on simulation of propagating unknowns. * DDR_REG macro. It can be connected to any I/O standard input buffers (i.e. INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module. R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-15, Table 2-16, and Table 2-17 list all the available macro names differentiated by I/O standard, type, slew rate, and drive strength. Table 2-15 * Macros for Single-Ended I/O Standards Standard VCCI Macro Names LVTTL 3.3 V CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24, TRIBUF, TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24, TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24 3.3 V PCI 3.3 V CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUF_PCI, BIBUF_PCI 3.3 V PCI-X 3.3 V CLKBUF_PCI-X, HCLKBUF_PCI-X, INBUF_PCI-X, OUTBUF_PCI-X, TRIBUF_PCI-X, BIBUF_PCI-X LVCMOS25 2.5 V CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUF_LVCMOS25, BIBUF_LVCMOS25 LVCMOS18 1.8 V CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUF_LVCMOS18, BIBUF_LVCMOS18 LVCMOS15 (JESD8-11) 1.5 V CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUF_LVCMOS15, BIBUF_LVCMOS15 Table 2-16 * I/O Macros for Differential I/O Standards Standard VCCI Macro Names LVPECL 3.3 V CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL LVDS 2.5 V CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS Table 2-17 * I/O Macros for Voltage-Referenced I/O Standards Standard VCCI VREF Macro Names GTL+ 3.3 V 1.0 V CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUF_GTP33, BIBUF_GTP33 GTL+ 2.5 V 1.0 V CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUF_GTP25, BIBUF_GTP25 SSTL2 Class I 2.5 V 1.25 V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, INBUF_SSTL2_I, OUTBUF_SSTL2_I, TRIBUF_SSTL2_I, BIBUF_SSTL2_I SSTL2 Class II 2.5 V 1.25 V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, INBUF_SSTL2_II, OUTBUF_SSTL2_II, TRIBUF_SSTL2_II, BIBUF_SSTL2_II SSTL3 Class I 3.3 V 1.5 V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, INBUF_SSTL3_I, OUTBUF_SSTL3_I, TRIBUF_SSTL3_I, BIBUF_SSTL3_I SSTL3 Class II 3.3 V 1.5 V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, INBUF_SSTL3_II, OUTBUF_SSTL3_II, TRIBUF_SSTL3_II, BIBUF_SSTL3_II HSTL Class I 1.5 V 0.75 V CLKBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, TRIBUF_HSTL_I, BIBUF_HSTL_I R ev i si o n 1 8 2- 19 Detailed Specifications User I/O Naming Conventions Due to the complex and flexible nature of the Axcelerator family's user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7). GND VCCDA Corner2 I/O BANK 2 I/O BANK 1 VPUMP GND VCCA GND AX125 I/O BANK 6 VCCI6 GND VCCA GND GND VCCDA Corner4 VCCI2 GND VCCA GND Corner3 VCCI3 GND VCCA GND GND VCCDA GND VCCDA VCCI4 GND I/O Bank and Dedicated Pin Layout IOxxXBxFx Pair number in the bank, starting at 00, clockwise from IOB NW P - Positive Pin/ N - Negative Pin Bank I/D 0 through 7, clockwise from IOB NW Fx refers to an unimplemented feature and can be ignored. Figure 2-8 * I/O BANK 4 VCCA GND VCOMPLE VCCPLE VCOMPLF VCCPLF PRC PRD VCOMPLG VCCPLG VCOMPLH VCCPLH GND VCCDA VCCI5 GND VCCA GND VCCDA GND Figure 2-7 * I/O BANK 5 GND VCCDA GND VCCDA I/O BANK 3 VCCDA GND 2- 20 VCCI1 I/O BANK 0 I/O BANK 7 VCCI7 GND VCCA GND VCOMPLD VCCPLD VCOMPLC VCCPLC VCCDA GND VCOMPLB VCCPLB VCOMPLA VCCPLA Corner1 PRB PRA VCCI0 GND VCCA GND TDO TDI TCK TMS TRST LP GND VCCDA Examples: IO12PB1F1 is the positive pin of the thirteenth pair of the first I/O bank (IOB NE). IO12PB1 combined with IO12NB1 form a differential pair. For those I/Os that can be employed either as a user I/O or as a special function, the following nomenclature is used: IOxxXBxFx/special_function_name IOxxPB1Fx/xCLKx this pin can be configured as a clock input or as a user I/O. General Naming Schemes R ev i sio n 1 8 Axcelerator Family FPGAs I/O Standard Electrical Specifications Table 2-18 * Input Capacitance Symbol Parameter Conditions Min. Max. Units CIN Input Capacitance VIN = 0, f = 1.0 MHz 10 pF CINCLK Input Capacitance on HCLK and RCLK Pin VIN = 0, f = 1.0 MHz 10 pF Table 2-19 * I/O Input Rise Time and Fall Time* Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) LVTTL No Requirement 50 ns LVCMOS 2.5V No Requirement 50 ns LVCMOS 1.8V No Requirement 50 ns LVCMOS 1.5V No Requirement 50 ns PCI No Requirement 50 ns PCIX No Requirement 50 ns GTL+ No Requirement 50 ns HSTL No Requirement 50 ns SSTL2 No Requirement 50 ns HSTL3 No Requirement 50 ns LVDS No Requirement 50 ns LVPECL No Requirement 50 ns Note: *Input Rise/Fall time applies to all inputs, be it clock or data. Inputs have to ramp up/down linearly, in a monotonic way. Glitches or a plateau may cause double clocking. They must be avoided. For output rise/fall time, refer to the IBIS models for extraction. IN PAD INBUF Y Input High ln VTRIP VTRIP 0V VCCA GND Figure 2-9 * 50% 50% Y tDP tDP (Rising) (Falling) Input Buffer Delays R ev i si o n 1 8 2- 21 Detailed Specifications TRIBUF ln OUT Pad To AC Test Loads (shown below) En VCCA ln 50% VCCA 50% GND En VCCA 50% VTRIP VTRIP Out 50% 50% GND VTT VTRIP VOH 10% tPY tPY (tDLH) (tDHL) VOL tENZL tENLZ Figure 2-10 * Output Buffer Delays 2- 22 En GND VCCI / VTT VOH Out VOL 50% R ev i sio n 1 8 Out GND / VTT tENZH VTRIP 90% tENHZ VTT Axcelerator Family FPGAs I/O Module Timing Characteristics Output Register D E Q OutReg Input Register PRE/CLR D Q InReg E Output Enable Register PRE/CLR D E Q EnReg PRE/CLR CLK (Routed or Hardwired) Figure 2-11 * Timing Model D tSUD tHD CLK tCPWHL tICLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tHASYN tPRESET tREASYN tWASYN PRESET tSUE tHE E Figure 2-12 * Input Register Timing Characteristics R ev i si o n 1 8 2- 23 Detailed Specifications D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tPRESET tHASYN tREASYN tHASYN tREASYN tWASYN PRESET tSUE tHE E Figure 2-13 * Output Register Timing Characteristics D tSUD tHD CLK tCPWHL tOCLKQ tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tPRESET tWASYN PRESET tSUE tHE E Figure 2-14 * Output Enable Register Timing Characteristics 2- 24 R ev i sio n 1 8 Axcelerator Family FPGAs 3.3 V LVTTL Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-20 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA -0.3 0.8 2.0 3.6 0.4 2.4 24 -24 AC Loadings R=1k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz / tpzl R to GND for tphz / tpzh 35 pF for tpzh / tpzl 5 pF for tphz / tplz Figure 2-15 * AC Test Loads Table 2-21 * AC Waveforms, Measuring Points, and Capacitive Load Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 3.0 1.40 N/A 35 Note: * Measuring Point = VTRIP R ev i si o n 1 8 2- 25 Detailed Specifications Timing Characteristics Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 1 (8 mA) / Low Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 14.28 16.27 19.13 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 15.25 17.37 20.42 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 14.26 16.24 19.09 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.56 1.57 1.58 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 1.95 1.96 1.97 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 039 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 26 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 2 (12 mA) / Low Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 12.14 13.83 16.26 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 12.43 14.16 16.65 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 12.17 13.86 16.30 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.73 1.74 1.75 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.22 2.23 2.24 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.38 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 27 Detailed Specifications Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength =3 (16 mA) / Low Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 11.03 12.56 14.77 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 11.42 13.01 15.29 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 11.04 12.58 14.79 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.86 1.88 1.88 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.50 2.51 2.52 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 28 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 4 (24 mA) / Low Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 10.45 11.90 13.99 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 10.61 12.08 14.21 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 10.47 11.93 14.02 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.92 1.94 1.94 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.57 2.58 2.59 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 29 Detailed Specifications Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 1 (8 mA) / High Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 4.23 4.81 5.66 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 4.64 5.28 6.21 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 4.23 4.81 5.66 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.89 1.91 1.91 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.01 2.02 2.03 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 30 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 2 (12 mA) / High Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 3.30 3.76 4.42 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 3.74 4.26 5.00 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 3.06 3.49 4.10 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.89 1.91 1.91 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.29 2.30 2.31 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 31 Detailed Specifications Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength =3 (16 mA) / High Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 3.12 3.56 4.18 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 3.54 4.04 4.75 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 2.78 3.17 3.72 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.91 1.93 1.93 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 2.58 2.59 2.60 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 32 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-22 * 3.3 V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C (continued) -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVTTL Output Drive Strength = 4 (24mA) / High Slew Rate tDP Input Buffer 1.68 1.92 2.26 ns tPY Output Buffer 2.99 3.41 4.01 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 2.49 2.51 2.51 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 2.59 2.95 3.46 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 1.91 1.93 1.93 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 3.56 4.06 4.77 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 33 Detailed Specifications 2.5 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-23 * DC Input and Output Levels VOL VOH IOL IOH Min., V VIL Max., V Min., V VIH Max., V Max., V Min., V mA mA -0.3 0.7 1.7 3.6 0.4 2.0 12 -12 AC Loadings R=1k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz / tpzl R to GND for tphz / tpzh 35 pF for tpzh / tpzl 5 pF for tphz / tplz Figure 2-16 * AC Test Loads Table 2-24 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 2.5 1.25 N/A 35 Note: * Measuring Point = VTRIP 2- 34 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics Table 2-25 * 2.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVCMOS25 I/O Module Timing tDP Input Buffer 1.95 2.22 2.61 ns tPY Output Buffer 3.29 3.74 4.40 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 2.48 2.50 2.51 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 2.48 2.50 2.51 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 5.74 6.54 7.69 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 6.60 7.51 8.83 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 35 Detailed Specifications 1.8 V LVCMOS Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-26 * DC Input and Output Levels VOL VOH IOL IOH Min., V VIL Max., V Min., V VIH Max., V Max., V Min., V mA mA -0.3 0.2 VCCI 0.7 VCCI 3.6 0.2 VCCI - 0.2 8 mA -8 mA AC Loadings R=1k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz / tpzl R to GND for tphz / tpzh 35 pF for tpzh / tpzl 5 pF for tphz / tplz Figure 2-17 * AC Test Loads Table 2-27 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.8 0.5 VCCI N/A 35 Note: * Measuring Point = VTRIP 2- 36 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics Table 2-28 * 1.8V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.7 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVCMOS18 Output Module Timing tDP Input Buffer 3.26 3.71 4.37 ns tPY Output Buffer 4.55 5.18 6.09 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 2.82 2.83 2.84 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 3.43 3.45 3.46 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 6.01 6.85 8.05 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 6.73 7.67 9.01 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 0.13 R ev i si o n 1 8 0.15 0.17 ns 2- 37 Detailed Specifications 1.5 V LVCMOS (JESD8-11) Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V applications. It uses a 3.3 V tolerant CMOS input buffer and a push-pull output buffer. Table 2-29 * DC Input and Output Levels VOL VOH IOL IOH Min., V VIL Max., V Min., V VIH Max., V Max., V Min., V mA mA -0.3 0.35 VCCI 0.65 VCCI 3.6 0.4 VCCI - 0.4 8 mA -8 mA AC Loadings R=1k Test Point for tpd 35 pF Test Point for tristate R to VCCI for tplz / tpzl R to GND for tphz / tpzh 35 pF for tpzh / tpzl 5 pF for tphz / tplz Table 2-30 * AC Test Loads Table 2-31 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) 0 1.5 0.5VCCI N/A 35 Note: * Measuring Point = VTRIP 2- 38 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics Table 2-32 * 1.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVCMOS15 (JESD8-11) I/O Module Timing tDP Input Buffer 3.59 4.09 4.81 ns tPY Output Buffer 6.05 6.89 8.10 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 3.31 3.34 3.34 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 4.56 4.58 4.59 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 6.37 7.25 8.52 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 6.94 7.90 9.29 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 39 Detailed Specifications 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5 V tolerant with the aid of external components. Axcelerator 3.3 V PCI and 3.3 V PCI-X buffers are compliant with the PCI Local Bus Specification Rev. 2.1. The PCI Compliance Specification requires the clamp diodes to be able to withstand for 11 ns, -3.5 V in undershoot, and 7.1 V in overshoot. Table 2-33 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Max., V Min., V mA mA Min., V Max., V Min., V Max., V PCI -0.3 0.3 VCCI 0.5 VCCI VCCI + 0.5 (per PCI specification) PCI-X -0.5 0.35 VCCI 0.5 VCCI VCCI + 0.5 (per PCI specification) AC Loadings R = 1k R to VCCI for tplz / tpzl R to GND for tphz / tpzh Test Point for tristate R = 25 R to VCCI for tpl R to GND for tph Test point for data 10 pF 35 pF for tpzl / tpzh 5 pF for tphz / tplz GND Figure 2-18 * AC Test Loads Table 2-34 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) (Per PCI Spec and PCI-X Spec) Note: * Measuring Point = VTRIP 2- 40 R ev i sio n 1 8 VREF (typ) (V) Cload (pF) N/A 10 Axcelerator Family FPGAs Timing Characteristics Table 2-35 * 3.3 V PCI I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.3 V PCI Output Module Timing tDP Input Buffer 1.57 1.79 2.10 ns tPY Output Buffer 1.91 2.18 2.56 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 1.61 1.62 1.63 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 1.45 1.47 1.47 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 2.55 2.90 3.41 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 3.52 4.01 4.72 ns tIOCLKQ Sequential Register Input 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 Clock-to-Q for the I/O R ev i si o n 1 8 ns 2- 41 Detailed Specifications Table 2-36 * 3.3 V PCI-X I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.3 V PCI-X Output Module Timing tDP Input Buffer 1.57 1.79 2.10 ns tPY Output Buffer 2.10 2.40 2.82 ns tENZL Enable to Pad Delay through the Output Buffer--Z to Low 1.61 1.62 1.63 ns tENZH Enable to Pad Delay through the Output Buffer--Z to High 1.59 1.60 1.61 ns tENLZ Enable to Pad Delay through the Output Buffer--Low to Z 2.65 3.02 3.55 ns tENHZ Enable to Pad Delay through the Output Buffer--High to Z 3.11 3.55 4.17 ns tIOCLKQ Sequential Clock-to-Q for the I/O Input Register 0.67 0.77 0.90 ns tIOCLKY Clock-to-output Y for the I/O Output Register and the I/O Enable Register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 42 R ev i sio n 1 8 Axcelerator Family FPGAs Voltage-Referenced I/O Standards GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5 V or 3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range. Table 2-37 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA N/A VREF - 0.1 VREF + 0.1 N/A 0.6 NA NA NA AC Loadings VTT 25 Test Point 10 pF Figure 2-19 * AC Test Loads Table 2-38 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF - 0.2 VREF + 0.2 VREF 1.0 10 Note: * Measuring Point = VTRIP Timing Characteristics Table 2-39 * 2.5 V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 2.5 V GTL+ I/O Module Timing tDP Input Buffer 1.71 1.95 2.29 ns tPY Output Buffer 1.13 1.29 1.52 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 ns tCPWHL Clock Pulse Width High to Low tCPWLH Clock Pulse Width Low to High tWASYN Asynchronous Pulse Width tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 0.00 0.39 0.00 0.39 0.39 ns 0.39 0.39 0.39 ns 0.37 0.37 0.37 ns R ev i si o n 1 8 2- 43 Detailed Specifications Table 2-40 * 3.3 V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.3 V GTL+I/O Module Timing tDP Input Buffer 1.71 1.95 2.29 ns tPY Output Buffer 1.13 1.29 1.52 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 44 R ev i sio n 1 8 Axcelerator Family FPGAs HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer. Table 2-41 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA -0.3 VREF - 0.1 VREF + 0.1 3.6 0.4 VCC - 0.4 8 -8 AC Loadings VTT 50 Test Point 20 pF Figure 2-20 * AC Test Loads Table 2-42 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF -0.5 VREF + 0.5 VREF 0.75 20 Note: * Measuring Point = VTRIP Timing Characteristics Table 2-43 * 1.5 V HSTL Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.425 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 1.5 V HSTL Class I I/O Module Timing tDP Input Buffer 1.80 2.05 2.41 ns tPY Output Buffer 4.90 5.58 6.56 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 45 Detailed Specifications SSTL2 Stub Series Terminated Logic for 2.5 V is a general-purpose 2.5 V memory bus standard (JESD8-9). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-44 * DC Input and Output Levels VOL VOH IOL Min., V VIL Max., V Min., V VIH Max., V Max., V Min., V mA IOH mA -0.3 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.57 VREF + 0.57 7.6 -7.6 AC Loadings VTT 50 Test Point 25 30 pF Figure 2-21 * AC Test Loads Table 2-45 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF - 0.75 VREF + 0.75 VREF 1.25 30 Note: * Measuring Point = VTRIP Timing Characteristics Table 2-46 * 2.5 V SSTL2 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 2.5 V SSTL2 Class I I/O Module Timing tDP Input Buffer 1.83 2.08 2.45 ns tPY Output Buffer 2.39 2.72 3.20 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 46 0.00 0.00 0.37 R ev i sio n 1 8 0.37 ns Axcelerator Family FPGAs Class II Table 2-47 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min,. V mA mA -0.3 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.8 VREF + 0.8 15.2 -15.2 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-22 * AC Test Loads Table 2-48 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF - 0.75 VREF + 0.75 VREF 1.25 30 Note: * Measuring Point = Vtrip Timing Characteristics Table 2-49 * 2.5 V SSTL2 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 2.5 V SSTL2 Class II I/O Module Timing tDP Input Buffer 1.89 2.16 2.53 ns tPY Output Buffer 2.39 2.72 3.20 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 0.00 R ev i si o n 1 8 0.00 0.00 ns 2- 47 Detailed Specifications SSTL3 Stub Series Terminated Logic for 3.3 V is a general-purpose 3.3 V memory bus standard (JESD8-8). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer. Class I Table 2-50 * DC Input and Output Levels VOL VOH IOL IOH Min., V VIL Max., V Min., V VIH Max., V Max., V Min., V mA mA -0.3 VREF - 0.2 VREF +0.2 3.6 VREF - 0.6 VREF + 0.6 8 -8 AC Loadings VTT 50 Test Point 25 30 pF Figure 2-23 * AC Test Loads Table 2-51 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF - 1.0 VREF + 1.0 VREF 1.50 30 Note: *Measuring Point = VTRIP Timing Characteristics Table 2-52 * 3.3 V SSTL3 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.3 V SSTL3 Class I I/O Module Timing tDP Input Buffer 1.78 2.03 2.39 ns tPY Output Buffer 2.17 2.47 2.91 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold tCPWHL Clock Pulse Width High to Low tCPWLH Clock Pulse Width Low to High tWASYN Asynchronous Pulse Width tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 2- 48 0.00 0.39 0.00 0.00 ns 0.39 0.39 ns 0.39 0.39 0.39 ns 0.37 0.37 0.37 ns R ev i sio n 1 8 Axcelerator Family FPGAs Class II Table 2-53 * DC Input and Output Levels VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA -0.3 VREF - 0.2 VREF + 0.2 3.6 VREF - 0.8 VREF + 0.8 16 -16 AC Loadings VTT 25 Test Point 25 30 pF Figure 2-24 * AC Test Loads Table 2-54 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) VREF (typ) (V) Cload (pF) VREF - 1.0 VREF + 1.0 VREF 1.50 30 Note: * Measuring Point = VTRIP Timing Characteristics Table 2-55 * 3.3 V SSTL3 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.3 V SSTL3 Class II I/O Module Timing tDP Input Buffer 1.85 2.10 2.47 ns tPY Output Buffer 2.17 2.47 2.91 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns 0.00 R ev i si o n 1 8 0.00 2- 49 Detailed Specifications Differential Standards Physical Implementation Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting in a single internal signal. To facilitate construction of the differential pair, a single I/O Cluster contains the resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards. LVDS Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV. OUTBUF_LVDS FPGA P 165 FPGA P ZO = 50 INBUF_LVDS + 100 140 - 165 N ZO = 50 N Figure 2-25 * LVDS Board-Level Implementation The LVDS circuit consists of a differential driver connected to a terminated receiver through a constantimpedance transmission line. The receiver is a wide-common-mode-range differential amplifier. The common-mode range is from 0.2 V to 2.2 V for a differential input with 400 mV swing. To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the differential signals (note that the driver is not a current-mode driver). This driver provides a nominal constant current of 3.5 mA. When this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is controlled by the data fed to the driver. An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV. Therefore, four external resistors are required, three for the driver and one for the receiver. Table 2-56 * DC Input and Output Levels DC Parameter Min. Typ. Max. Units Supply Voltage 2.375 2.5 2.625 V VOH Output High Voltage 1.25 1.425 1.6 V VOL Output Low Voltage 0.9 1.075 1.25 V VODIFF Differential Output Voltage 250 350 450 mV VOCM Output Common Mode Voltage 1.125 1.25 1.375 V VICM2 Input Common Mode Voltage 0.2 1.25 2.2 V VCCI 1 Description Notes: 1. 5% 2. Differential input voltage = 350 mV. 2- 50 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-57 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.2 - 0.125 1.2 + 0.125 1.2 Note: * Measuring Point = VTRIP Timing Characteristics Table 2-58 * LVDS I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVDS Output Module Timing tDP Input Buffer 1.80 2.05 2.41 ns tPY Output Buffer 2.32 2.64 3.11 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the I/O output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 51 Detailed Specifications LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. FPGA OUTBUF_LVPECL P 100 ZO = 50 N + 100 187 ZO = 50 100 FPGA P INBUF_LVPECL - N Figure 2-26 * LVPECL Board-Level Implementation The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are different. Please note that the VOH levels are 200 mV below the standard LVPECL levels. Table 2-59 * DC Input and Output Levels Min. DC Parameter Min. VCCI Typ. Max. Min. 3 Max. Max. Min. 3.3 Max. 3.6 Units V VOH 1.8 2.11 1.92 2.28 2.13 2.41 V VOL 0.96 1.27 1.06 1.43 1.3 1.57 V VIH 1.49 2.72 1.49 2.72 1.49 2.72 V VIL 0.86 2.125 0.86 2.125 0.86 2.125 V Differential Input Voltage 0.3 0.3 0.3 V Table 2-60 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) 1.6 - 0.3 1.6 + 0.3 1.6 Note: * Measuring Point = VTRIP 2- 52 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics Table 2-61 * LVPECL I/O Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units LVPECL Output Module Timing tDP Input Buffer 1.66 1.89 2.22 ns tPY Output Buffer 2.24 2.55 3.00 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.39 0.39 0.39 ns tCPWLH Clock Pulse Width Low to High 0.39 0.39 0.39 ns tWASYN Asynchronous Pulse Width 0.37 0.37 0.37 ns tREASYN Asynchronous Recovery Time 0.13 0.15 0.17 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns R ev i si o n 1 8 2- 53 Detailed Specifications Module Specifications C-Cell Introduction The C-cell is one of the two logic module types in the AX architecture. It is the combinatorial logic resource in the Axcelerator device. The AX architecture implements a new combinatorial cell that is an extension of the C-cell implemented in the SX-A family. The main enhancement of the new C-cell is the addition of carry-chain logic. The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not required, it can be disabled. The C-cell features the following (Figure 2-27): * Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed clocks (CLKE/F/G/H). * Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell. * A carry input and a carry output. The carry input signal of the C-cell is the carry output from the Ccell directly to the north. * Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. * A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the east side of a SuperCluster with a signal propagation time of less than 0.1 ns. This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The carry-chain configuration is handled automatically for the user with Microsemi's extensive macro library (please see the Antifuse Macro Library Guide for a complete listing of available Axcelerator macros). CFN FCI D1 D3 B0 B1 0 1 0 1 0 1 0 1 0 1 D0 D2 DB A0 A1 Figure 2-27 * C-Cell 2- 54 R ev i sio n 1 8 FCO Y Axcelerator Family FPGAs Timing Model and Waveforms VCCA 50% 50% A, B, D, FCI GND VCCA 50% Y, FCO GND 50% tPD, tPDC tPD, tPDC VCCA Y, FCO 50% 50% GND tPD, tPDC tPD, tPDC Figure 2-28 * C-Cell Timing Model and Waveforms Timing Characteristics Table 2-62 * C-Cell Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units C-Cell Propagation Delays tPD Any input to output Y 0.74 0.84 0.99 ns tPDC Any input to carry chain output (FCO) 0.57 0.64 0.76 ns tPDB Any input through DB when one input is used 0.95 1.09 1.28 ns tCCY Input to carry chain (FCI) to Y 0.61 0.69 0.82 ns tCC Input to carry chain (FCI) to carry chain output (FCO) 0.08 0.09 0.11 ns R ev i si o n 1 8 2- 55 Detailed Specifications Carry-Chain Logic The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e. carry out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay from the FCI (i.e. carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-29. The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-4 on page 1-3 and Figure 2-30 on page 2-57). The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through Microsemi's macro library. CFN D1 D3 B0 B1 0 1 0 1 DCOUT 0 1 0 1 0 1 0 1 0 1 0 1 FCI D1 D3 B0 B1 CFN The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns. 2- 56 R ev i sio n 1 8 A1 A0 DB D0 D2 Y Figure 2-29 * Axcelerator's Two-Bit Carry Logic 0 1 FCO Y 0 1 A1 A0 DB D0 D2 0 1 Axcelerator Family FPGAs FCI1 C-cell1 C-cell2 DCOUT R-cell1 DCIN FCO2 FCI3 DCOUT DCIN FCO4 FCI5 n-2 Clusters FCI(2n-1) C-cell (2n-1) C-cell2n DCOUT R-celln CDIN FCO2n Note: The carry-chain sequence can end on either C-cell. Figure 2-30 * Carry-Chain Sequencing of C-Cells Timing Characteristics Refer to Table 2-62 on page 2-55 for more information on carry-chain timing. R ev i si o n 1 8 2- 57 Detailed Specifications R-Cell Introduction The R-cell, the sequential logic resource of the Axcelerator devices, is the second logic module type in the AX family architecture. It includes clock inputs for all eight global resources of the Axcelerator architecture as well as global presets and clears (Figure 2-31). The main features of the R-cell include the following: * Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a connection with less than 0.1 ns of routing delay. * The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using the R-Cell as a 2:1 MUXed flip-flop as well. * Provision of data enable-input (S0). * Independent active-low asynchronous clear (CLR). * Independent active-low asynchronous preset (PSET). If both CLR and PSET are low, CLR has higher priority. * Clock can be driven by any of the following (CKP selects clock polarity): * - One of the four high performance hardwired fast clocks (HCLKs) - One of the four routed clocks (CLKs) - User signals Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide basis. - When the Global Set Fuse option in the Designer software is unchecked (by default), GCLR = 0 and GPSET = 1 at device power-up. When the option is checked, GCLR = 1 and GPSET = 0. Both pins are pulled High when the device is in user mode. Refer to the "Simulation Support for GCLR/GPSET in Axcelerator" section of the Antifuse Macro Library Guide for information on simulation support for GCLR and GPSET. * S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals. * DIN and S1 can be driven by user signals. CKP As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Microsemi's extensive macro library (see the Antifuse Macro Library Guide for a complete listing of available AX macros). DIN(user signals) DCIN HCLKA/B/C/D CLKE/F/G/H Figure 2-31 * R-Cell 2- 58 R ev i sio n 1 8 Y PSET GPSET CLR GCLR S0 S1 CKS Internal Logic Axcelerator Family FPGAs Timing Models and Waveforms D tSUD tHD CLK tCPWHL tRCO tCPWLH Q CLR tHASYN tREASYN tWASYN tCLR tHASYN tPRESET tWASYN PRESET E tREASYN tSUE tHE Figure 2-32 * R-Cell Delays Timing Characteristics Table 2-63 * R-Cell Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units R-Cell Propagation Delays tRCO Sequential Clock-to-Q 0.67 0.77 0.90 ns tCLR Asynchronous Clear-to-Q 0.67 0.77 0.90 ns tPRESET Asynchronous Preset-to-Q 0.36 0.36 0.36 ns tSUD Flip-Flop Data Input Set-Up 0.34 0.34 0.34 ns tSUE Flip-Flop Enable Input Set-Up 0.00 0.00 0.00 ns tHD Flip-Flop Data Input Hold 0.67 0.77 0.90 ns tHE Flip-Flop Enable Input Hold 0.67 0.77 0.90 ns tWASYN Asynchronous Pulse Width tREASYN Asynchronous Recovery Time 0.23 0.27 0.31 ns tHASYN Asynchronous Removal Time 0.36 0.36 0.36 ns tCPWHL Clock Pulse Width High to Low 0.36 0.36 0.36 ns tCPWLH Clock Pulse Width Low to High 0.36 0.36 0.36 ns 0.48 0.48 R ev i si o n 1 8 0.48 ns 2- 59 Detailed Specifications Buffer Module Introduction An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets. Timing Models and Waveforms IN OUT Figure 2-33 * Buffer Module Timing Model VCCA 50% 50% GND IN VCCA OUT GND 50% 50% tBFPD tBFPD Figure 2-34 * Buffer Module Waveform Timing Characteristics Table 2-64 * Buffer Module Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 0.16 ns Buffer Module Propagation Delays tBFPD 2- 60 Any input to output Y 0.12 R ev i sio n 1 8 0.14 Axcelerator Family FPGAs Routing Specifications Routing Resources The routing structure found in Axcelerator devices enables any logic module to be connected to any other logic module while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are four primary types of routing within the AX architecture: DirectConnect, CarryConnect, FastConnect, and Vertical and Horizontal Routing. DirectConnect DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-35). This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. Figure 2-35 * DirectConnect and CarryConnect CarryConnect CarryConnects are used to build carry chains for arithmetic functions (Figure 2-35). The FCO output of the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster immediately below it. This pattern continues down both sides of each SuperCluster column. Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This connection has a delay of less than 0.1 ns from the FCO of one two-C-cell cluster to the FCI of the twoC-cell cluster immediately below it (see the "Carry-Chain Logic" section on page 2-56 for more information). FastConnect For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 2-36 on page 2-62). FastConnects provide a maximum delay of 0.3 ns. The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on the Output Tracks can then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below it. R ev i si o n 1 8 2- 61 Detailed Specifications Vertical and Horizontal Routing Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-37 on page 2-62). These tracks are composed of both short-distance, segmented routing and across-chip routing tracks (segmented at core tile boundaries). The short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. These short-distance routing tracks can be used within and between SuperClusters or between modules of non-adjacent SuperClusters. They can be connected to the Output Tracks and to any logic module input (R-cell, C-cell, Buffer, and TX module). The across-chip horizontal and vertical routing provides long-distance routing resources. These resources interface with the rest of the routing structures through the RX and TX modules (Figure 2-37). The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output Tracks within the SuperCluster. The TX module is used to drive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. Figure 2-36 * FastConnect Routing Figure 2-37 * Horizontal and Vertical Tracks 2- 62 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics Table 2-65 * AX125 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425 V, TJ = 70C Parameter Description -2 Speed -1 Speed Std Speed Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.35 0.40 0.47 ns tRD2 Routing delay for FO2 0.38 0.43 0.51 ns tRD3 Routing delay for FO3 0.43 0.48 0.57 ns tRD4 Routing delay for FO4 0.48 0.55 0.64 ns tRD5 Routing delay for FO5 0.55 0.62 0.73 ns tRD6 Routing delay for FO6 0.64 0.72 0.85 ns tRD7 Routing delay for FO7 0.79 0.89 1.05 ns tRD8 Routing delay for FO8 0.88 0.99 1.17 ns tRD16 Routing delay for FO16 1.49 1.69 1.99 ns tRD32 Routing delay for FO32 2.32 2.63 3.10 ns Table 2-66 * AX250 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425 V, TJ = 70C Parameter Description -2 Speed -1 Speed Std Speed Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.39 0.45 0.53 ns tRD2 Routing delay for FO2 0.41 0.46 0.54 ns tRD3 Routing delay for FO3 0.48 0.55 0.64 ns tRD4 Routing delay for FO4 0.56 0.63 0.75 ns tRD5 Routing delay for FO5 0.60 0.68 0.80 ns tRD6 Routing delay for FO6 0.84 0.96 1.13 ns tRD7 Routing delay for FO7 0.90 1.02 1.20 ns tRD8 Routing delay for FO8 1.00 1.13 1.33 ns tRD16 Routing delay for FO16 2.17 2.46 2.89 ns tRD32 Routing delay for FO32 3.55 4.03 4.74 ns R ev i si o n 1 8 2- 63 Detailed Specifications Table 2-67 * AX500 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425 V, TJ = 70C Parameter Description -2 Speed -1 Speed Std Speed Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.11 0.12 0.15 ns tFC FastConnect Routing Delay, FO1 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.39 0.45 0.53 ns tRD2 Routing delay for FO2 0.41 0.46 0.54 ns tRD3 Routing delay for FO3 0.48 0.55 0.64 ns tRD4 Routing delay for FO4 0.56 0.63 0.75 ns tRD5 Routing delay for FO5 0.60 0.68 0.80 ns tRD6 Routing delay for FO6 0.84 0.96 1.13 ns tRD7 Routing delay for FO7 0.90 1.02 1.20 ns tRD8 Routing delay for FO8 1.00 1.13 1.33 ns tRD16 Routing delay for FO16 2.17 2.46 2.89 ns tRD32 Routing delay for FO32 3.55 4.03 4.74 ns Table 2-68 * AX1000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425 V, TJ = 70C Parameter Description -2 Speed -1 Speed Std Speed Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.12 0.13 0.15 ns tFC FastConnect Routing Delay, FO1 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.45 0.51 0.60 ns tRD2 Routing delay for FO2 0.53 0.60 0.71 ns tRD3 Routing delay for FO3 0.56 0.63 0.74 ns tRD4 Routing delay for FO4 0.63 0.71 0.84 ns tRD5 Routing delay for FO5 0.73 0.82 0.97 ns tRD6 Routing delay for FO6 0.99 1.13 1.32 ns tRD7 Routing delay for FO7 1.02 1.15 1.36 ns tRD8 Routing delay for FO8 1.48 1.68 1.97 ns tRD16 Routing delay for FO16 2.57 2.91 3.42 ns tRD32 Routing delay for FO32 4.24 4.81 5.65 ns 2- 64 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-69 * AX2000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425 V, TJ = 70C Parameter Description -2 Speed -1 Speed Std Speed Typical Typical Typical Units Predicted Routing Delays tDC DirectConnect Routing Delay, FO1 0.12 0.13 0.15 ns tFC FastConnect Routing Delay, FO1 0.35 0.39 0.46 ns tRD1 Routing delay for FO1 0.50 0.56 0.66 ns tRD2 Routing delay for FO2 0.59 0.67 0.79 ns tRD3 Routing delay for FO3 0.70 0.80 0.94 ns tRD4 Routing delay for FO4 0.76 0.87 1.02 ns tRD5 Routing delay for FO5 0.98 1.11 1.31 ns tRD6 Routing delay for FO6 1.48 1.68 1.97 ns tRD7 Routing delay for FO7 1.65 1.87 2.20 ns tRD8 Routing delay for FO8 1.73 1.96 2.31 ns tRD16 Routing delay for FO16 2.58 2.92 3.44 ns tRD32 Routing delay for FO32 4.24 4.81 5.65 ns R ev i si o n 1 8 2- 65 Detailed Specifications Global Resources One of the most important aspects of any FPGA architecture is its global resources or clocks. The Axcelerator family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures. The AX architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed clock). Every Axcelerator device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density. Hardwired Clocks The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers, and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip. Timing Characteristics Table 2-70 * AX125 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 3.02 3.44 4.05 ns tHCKH Input High to Low 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.58 tHPWL Minimum Pulse Width Low 0.52 tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.65 0.77 0.59 0.06 1.15 0.69 0.07 1.31 870 ns ns 0.08 1.54 763 ns ns 649 MHz Table 2-71 * AX250 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units 3.45 ns Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High tHCKH Input High to Low tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 2- 66 2.57 2.93 2.61 2.97 0.06 1.15 0.07 1.31 870 R ev i sio n 1 8 3.50 0.08 ns 649 MHz 1.54 763 ns ns Axcelerator Family FPGAs Table 2-72 * AX500 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 2.35 2.68 3.15 ns tHCKH Input High to Low 2.44 2.79 3.27 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.06 1.15 0.07 1.31 870 0.08 1.54 763 ns ns 649 MHz Table 2-73 * AX1000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 3.02 3.44 4.05 ns tHCKH Input High to Low 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.06 1.15 0.07 1.31 870 0.08 1.54 763 ns ns 649 MHz Table 2-74 * AX2000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Dedicated (Hardwired) Array Clock Networks tHCKL Input Low to High 3.02 3.44 4.05 ns tHCKH Input High to Low 3.03 3.46 4.06 ns tHPWH Minimum Pulse Width High 0.58 0.65 0.77 ns tHPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tHCKSW Maximum Skew tHP Minimum Period tHMAX Maximum Frequency 0.06 1.15 0.07 1.31 870 R ev i si o n 1 8 0.08 1.54 763 ns ns 649 MHz 2- 67 Detailed Specifications Routed Clocks The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip. Timing Characteristics Table 2-75 * AX125 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 3.08 3.50 4.12 ns tRCKH Input High to Low 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.35 1.15 0.39 1.31 870 0.46 1.54 763 ns ns 649 MHz Table 2-76 * AX250 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.52 2.87 3.37 ns tRCKH Input High to Low 2.59 2.95 3.47 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 2- 68 0.35 1.15 0.39 1.31 870 R ev i sio n 1 8 0.46 1.54 763 ns ns 649 MHz Axcelerator Family FPGAs Table 2-77 * AX500 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.31 2.63 3.09 ns tRCKH Input High to Low 2.44 2.78 3.27 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.35 1.15 0.39 1.31 870 0.46 1.54 763 ns ns 649 MHz Table 2-78 * AX1000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 3.08 3.50 4.12 ns tRCKH Input High to Low 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.35 1.15 0.39 1.31 870 0.46 1.54 763 ns ns 649 MHz Table 2-79 * AX2000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 3.08 3.50 4.12 ns tRCKH Input High to Low 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew tRP Minimum Period tRMAX Maximum Frequency 0.35 1.15 0.39 1.31 870 R ev i si o n 1 8 0.46 1.54 763 ns ns 649 MHz 2- 69 Detailed Specifications Global Resource Distribution At the root of each global resource is a PLL. There are two groups of four PLLs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-38). Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 2-39). PLL P N PLL P N PLL P N PLL P N PLL Cluster HCLKA HCLKB HCLKC HCLKD CLKE CLKF CLKG CLKH PLL Cluster P N PLL P N PLL P N PLL P N PLL Figure 2-38 * PLL Group HCLK CLK PLL Group ClockTileDist Cluster 4 4 PLL Group Figure 2-39 * Example of HCLK and CLK Distributions on the AX2000 2- 70 R ev i sio n 1 8 Axcelerator Family FPGAs The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK branches propagate vertically through the center of the core tile to CLKRowDist (RD) modules in every SuperCluster row. Together, the HCLK and CLK branches provide for a low-skew global fanout within the core tile (Figure 2-40 and Figure 2-41). Figure 2-40 * CTD, CD, and HD Module Layout Figure 2-41 * HCLK and CLK Distribution within a Core Tile R ev i si o n 1 8 2- 71 Detailed Specifications The HM and CM modules can select between: * The HCLK or CLK source respectively * A local signal routed on generic routing resources This allows each core tile to have eight clocks independent of the other core tiles in the device. Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. Like the HM and CM modules, the HD and RD modules can select between: * The HCLK or CLK source from the HM or CM module respectively * A local signal routed on generic routing resources The AX architecture is capable of supporting a large number of local clocks--24 segments per HCLK driving north-south and 28 segments per CLK driving east-west per core tile. Microsemi's Designer software's place-and-route takes advantage of the segmented clock structure found in Axcelerator devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption. Global Resource Access Macros Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and PLLCLK. CLKBUF and HCLKBUF CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-42). P Clock Network CLKBUF HCLKBUF N Figure 2-42 * CLKBUF and HCLKBUF Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the P-pad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals. CLKINT and HCLKINT CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-43). Clock Network Logic CLKINT HCLKINT Figure 2-43 * CLKINT and HCLKINT 2- 72 R ev i sio n 1 8 Axcelerator Family FPGAs PLLRCLK and PLLHCLK PLLRCLK (PLLHCLK) is used to drive global resource CLK (HCLK) from a PLL (Figure 2-44). RefCLK Clock Network CLK1 PLL FB PLLRCLK PLLHCLK CLK2 Figure 2-44 * PLLRCLK and PLLHCLK Using Global Resources with PLLs Each global resource has an associated PLL at its root. For example, PLLA can drive HCLKA, PLLE can drive CLKE, etc. (Figure 2-45). HCLKAP RefCLK HCLKA Network CLK1 PLLA FB HCLKAN CLK2 PLLHCLK Figure 2-45 * Example of HCLKA Driven from a PLL with External Clock Source In addition, each clock pin of the package can be used to drive either its associated global resource or PLL. For example, package pins CLKEP and CLKEN can drive either the RefCLK input of PLLE or CLKE. There are two macros required when interfacing the embedded PLLs with the global resources: PLLINT and PLLOUT. PLLINT This macro is used to drive the RefCLK input of the PLL internally from user signals. PLLOUT This macro is used to connect either the CLK1 or CLK2 output of a PLL to the regular routing network (Figure 2-46). PLLHCLK PLLINT Logic RefCLK HCLKA Network CLK1 PLLA FB CLK2 Logic PLLOUT Figure 2-46 * Example of PLLINT and PLLOUT Usage R ev i si o n 1 8 2- 73 Detailed Specifications Implementation Example: Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2 output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both CLKF and CLKG global resources. Non-Clock Pins P INBUF PLLINT PLLRCLK N RefCLK CLK1 PLLE FB CLK2 CLKINT PLLOUT Logic PLLRCLK RefCLK CLK1 CLKF CLK2 CLKG PLLF FB PLLRCLK Figure 2-47 * Complex Clock Distribution Example 2- 74 R ev i sio n 1 8 CLKE Axcelerator Family FPGAs Axcelerator Clock Management System Introduction Each member of the Axcelerator family6 contains eight phase-locked loop (PLL) blocks which perform the following functions: * Programmable Delay (32 steps of 250 ps) * Clock Skew Minimization * Clock Frequency Synthesis Each PLL has the following key features: * Input Frequency Range - 14 to 200 MHz * Output Frequency Range - 20 MHz to 1 GHz * Output Duty Cycle Range - 45% to 55% * Maximum Long-Term Jitter - 1% or 100ps (whichever is greater) * Maximum Short-Term Jitter - 50ps + 1% of Output Frequency * Maximum Acquisition Time (lock) - 20s Physical Implementation The eight PLL blocks are arranged in two groups of four. One group is located in the center of the northern edge of the chip, while the second group is centered on the southern edge. The northern group is associated with the four HCLK networks (e.g. PLLA can drive HCLKA), while the southern group is associated with the four CLK networks (e.g. PLLE can drive CLKE). Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core. Figure 2-48 illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply through a 250 resistor. Furthermore, 0.1 F and 10 F decoupling capacitors should be connected across the VCCPLL and VCOMPPLL pins. DIVJ 6 PowerDown RefCLK Delay Line /i Delay Match /j CLK1 /j Delay Match CLK2 PLL FB Delay Line FBMuxSel 5 DelayLine Lock /i 6 DIVJ LowFreq 3 Osc Figure 2-48 * PLL Block Diagram Note: The VCOMPPLL pin should never be grounded (Figure 2-2 on page 2-9)! The I/O pads associated with the PLL can also be configured for regular I/O functions except when it is used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair, 6. AX2000-CQ256 does not support operation of the phase-locked loops. This is in order to support full pin compatibility with RTAX2000S/SL-CQ256. R ev i si o n 1 8 2- 75 Detailed Specifications single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair with [H]CLKxP. The block marked "/i Delay Match" is a fixed delay equal to that of the i divider. The "/j Delay Match" block has the same function as its j divider counterpart. Functional Description Figure 2-48 on page 2-75 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j, that allow frequency scaling of the clock signal: * The i divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64, and the resultant frequency is available at the output of the PLL block. * The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock is available at CLK1. * The two dividers together can implement any combination of multiplication and division up to a maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50 duty cycle. * The output frequencies of the two clocks are given by the following formulas (fREF is the reference clock frequency): fCLK1 = fREF * (DividerI) / (DividerJ) EQ 4 fCLK2 = fREF * (DividerI) EQ 5 * CLK2 provides the PLL output directly--without division The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These functions and their possible values are detailed in Table 2-80 on page 2-77. The delay lines shown in Figure 2-48 on page 2-75 are programmable. The feedback clock path can be delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in increments of 250 ps. Table 2-80 on page 2-77 describes the usage of these bits. The delay increments are independent of frequency, so this results in phase changes that vary with frequency. The delay value is highly dependent on VCC and the speed grade. Figure 2-49 is a logical diagram of the various control signals to the PLL and shows how the PLL interfaces with the global and routing networks of the FPGA. Note that not all signals are useraccessible. These non-user-accessible signals are used by the place-and-route tool to control the configuration of the PLL. The user gains access to these control signals either based upon the connections built in the user's design or through the special macros (Table 2-84 on page 2-81) inserted into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal. ROOTSEL REFSEL CLKINT CLK1 (PLLn-1) CLK1 (PLLn-1) RefCLK [H]CLKINT 0 1 2 3 CLK1 [H]CLKxP I/O Core net CLK net PLL CLK2 FBINT PLLSEL 1 FB [H]CLKxN OUTSEL FBMuxSEL To PLLn+1 Note: Not all signals are available to the user. Figure 2-49 * PLL Logical Interface 2- 76 0 R ev i sio n 1 8 [H]CLK CLK Out (Routed net out pin) Axcelerator Family FPGAs Table 2-80 * PLL Interface Signals Signal Name Type User Accessible RefCLK Input Yes Reference Clock for the PLL FB Input Yes Feedback port for the PLL PowerDown Input Yes PLL power down control DIVI[5:0] Input Yes DIVJ[5:0] Input Yes LowFreq Input Yes Allowable Values 0 PLL powered down 1 PLL active 1 to 64, in Sets value for feedback divider (multiplier) unsigned binary Sets value for CLK1 divider notation offset by -1 Input frequency range selector 0 1 Osc[2:0] Input Function Yes 50-200 MHz 14-50 MHz Output frequency range selector XX0 400-1000 MHZ 001 200-400 MHZ 011 100-200 MHZ 101 50-100 MHZ 111 20-50 MHZ DelayLine[4:0] Input Yes -15 to +15 Clock Delay (positive/negative) in increments (increments), in of 250 ps, with maximum value of 3.75 ns signed-andmagnitude binary representation FBMuxSel Input No Selects the source for the feedback input REFSEL Input No Selects the source for the reference clock OUTSEL Input No Selects the source for the routed net output PLLSEL Input No ROOTSEL & PLLSEL are used to select the source of the global clock network ROOTSEL Input No Lock Output Yes High value indicates PLL has locked CLK1 Output Yes PLL clock output CLK2 Output Yes PLL clock output Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate. R ev i si o n 1 8 2- 77 Detailed Specifications PLL Configurations The following rules apply to the different PLL inputs and outputs: Reference Clock The RefCLK can be driven by (Figure 2-50): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. CLK1 output of an adjacent PLL 3. [H]CLKxP (single-ended or voltage-referenced) 4. [H]CLKxP/[H]CLKxN pair (differential modes like LVPECL or LVDS) Feedback Clock The feedback clock can be driven by (Figure 2-51 on page 2-78): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell 3. An internal signal from the PLL block Regular, LVPECL, or LVDS IOPAD Non-clock Pins INBUF RefCLK P PLL N Any macro from the core, except HCLK nets RefCLK Logic PLL For cascading PLL CLK1 RefCLK PLL Figure 2-50 * Reference Clock Connections PLLOUT/PLLRCLK FB PLL Any macro except HCLK macros FB PLL Figure 2-51 * Feedback Clock Connections 2- 78 R ev i sio n 1 8 Axcelerator Family FPGAs CLK1 and CLK2 Both PLL outputs, CLK1 and CLK2, can be used to drive a global resource, an adjacent PLL RefCLK input, or a net in the FPGA core. Not all drive combinations are possible (Table 2-81). Table 2-81 * PLL General Connections Rules CLK1 CLK2 HCLK HCLK CLK CLK HCLK Routed net output Routed net output HCLK HCLK NONE NONE HCLK CLK NONE NONE CLK Note: The PLL outputs remain Low when REFCLK is constant (either Low or High). Restrictions on CLK1 and CLK2 * When both are driving global resources, they must be driving the same type of global resource (i.e. either HCLK or CLK). * Only one can drive a routed net at any given time. Table 2-82 and Table 2-83 specify all the possible CLK1 and CLK2 connections for the north and south PLLs. HCLK1 and HCLK2 are used to denote the different HCLK networks when two are being driven at the same time by a single PLL (Note that HCLK1 is the primary clock resource associated with the PLL, and HCLK2 is the clock resource associated with the adjacent PLL). Likewise, CLK1 and CLK2 are used to denote the different CLK networks when two are being driven at the same time by a single PLL (Figure 2-48 on page 2-75). Table 2-82 * North PLL Connections CLK1 CLK2 HCLK1 Routed net HCLK1 Unused HCLK2 HCLK1 HCLK2 Routed net HCLK2 Both HCLK1 and routed net HCLK2 Unused Unused HCLK1 Unused Routed net Unused Both HCLK1 and routed net Unused Unused Routed net HCLK1 Routed net Unused Both HCLK1 and HCLK2 Routed net Both HCLK1 and HCLK2 Unused Both HCLK1 and routed net Unusable Both HCLK2 and routed net HCLK1 Both HCLK2 and routed net Unused HCLK1, HCLK2, and routed net Unusable Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g.CLK1 driving HCLK1, and HCLK2 is not supported). R ev i si o n 1 8 2- 79 Detailed Specifications Table 2-83 * South PLL Connections CLK1 CLK2 CLK1 Routed net CLK1 Unused CLK2 CLK1 CLK2 Routed net CLK2 Both CLK1 and routed net CLK2 Unused Unused CLK1 Unused Routed net Unused Both CLK1 and routed net Unused Unused Routed net CLK1 Routed net Unused Both CLK1 and CLK2 Routed net Both CLK1 and CLK2 Unused Both CLK1 and routed net Unusable Both CLK2 and routed net CLK1 Both CLK2 and routed net Unused CLK1, CLK2, and routed net Unusable Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g., CLK1 driving both CLK1 and CLK2 is not supported). 2- 80 R ev i sio n 1 8 Axcelerator Family FPGAs Special PLL Macros Table 2-84 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing resources. Table 2-84 * PLL Special Macros Macro Name Usage PLLINT Connects RefCLK to a regular routed net or a pad. PLLRCLK Connects CLK1 or CLK2 to the CLK network. PLLHCLK Connects CLK1 or CLK2 to the HCLK network. PLLOUT Connects CLK1 or CLK2 to a regular routed net. Table 2-85 * Electrical Specifications Parameter Value Notes Frequency Ranges Reference Frequency (min.) 14 MHz Lowest input frequency Reference Frequency (max.) 200 MHz Highest input frequency OSC Frequency (min.) 20 MHz Lowest output frequency OSC Frequency (max.) 1 GHz Highest output frequency Jitter Long-Term Jitter (max.) 1% Long-Term Jitter (max.) 100ps Short-Term Jitter (max.) 50ps+1% Percentage frequencies of period, low reference clock High reference clock frequencies Percentage of output frequency Acquisition Time (lock) from Cold Start Acquisition Time (max.)* 400 cycles Acquisition Time (max.)* 1.5 s Period of low reference clock frequencies High reference clock frequencies Analog Supply Current (low freq.) 200 A Current at minimum oscillator frequency Analog Supply Current (high freq.) 200 A Frequency-dependent current Power Consumption Digital Supply Current (low freq.) Digital Supply Current (high freq.) 0.5 A/MHz Current at maximum oscillator frequency, unloaded 1 A/MHz Frequency-dependent current Duty Cycle Minimum Output Duty Cycle 45% Maximum Output Duty Cycle 55% Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency. R ev i si o n 1 8 2- 81 Detailed Specifications User Flow There are two methods of including a PLL in a design: * The recommended method of using a PLL is to create custom PLL blocks using Microsemi's macro generator, SmartGen, that can be instantiated in a design. * The alternative method is to instantiate one of the generic library primitives (PLL or PLLFB) into either a schematic or HDL netlist, using inverters for polarity control and tying all unused address and data bits to ground. Timing Model Lock CLK1 tPCLK* CLK FB Note: tPCLK is the delay in the clock signal Figure 2-52 * PLL Model 2- 82 R ev i sio n 1 8 5 3 OSC 6 DividerI/DividerJ Configuration Pins 6 Delay Line FBMux CLK2 Axcelerator Family FPGAs Sample Implementations Frequency Synthesis Figure 2-53 illustrates an example where the PLL is used to multiply a 155.5 MHz external clock up to 622 MHz. Note that the same PLL schematic could use an external 350 MHz clock, which is divided down to 155 MHz by the FPGA internal logic. Figure 2-54 illustrates the PLL using both dividers to synthesize a 133 MHz output clock from a 155 MHz input reference clock. The input frequency of 155 MHz is multiplied by 6 and divided by 7, giving a CLK1 output frequency of 132.86 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. DividerJ 6 Power-Down RefCLK 155.5 MHz Delay Line Lock /i Delay Match /j PLL CLK1 FB Delay Line /i /j Delay Match CLK2 622 MHz FBMuxSel 5 DelayLine 6 DividerI LowFreq 3 Osc +4 Figure 2-53 * Using the PLL 155.5 MHz In, 622 MHz Out Adjustable Clock Delay Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output clock is accomplished by using the delay line in the feedback path. R ev i si o n 1 8 2- 83 Detailed Specifications /7 DividerJ 6 Power-Down RefCLK 155 MHz Delay Line /i Delay Match 155 MHz Lock 132.8 MHz 930 MHz PLL CLK1 /j FB Delay Line 155 MHz /i CLK2 /j Delay Match Yes FBMuxSel 3 6 5 DelayLine DividerI LowFreq Osc +6 Figure 2-54 * Using the PLL 155 MHz In, 133 MHz Out DividerJ 6 PowerDown Lock RefCLK Delay Line 133 MHz /i Delay Match PLL CLK1 /j FB Delay Line /j /j Delay Match CLK2 133 MHz 5 FBMuxSel DelayLine 3 6 DividerI LowFreq 1 Figure 2-55 * Using the PLL Delaying the Reference Clock 2- 84 R ev i sio n 1 8 Osc Axcelerator Family FPGAs Clock Skew Minimization Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to the Axcelerator Family PLL and Clock Management application note for more information. DividerJ 6 Lock Power-Down RefCLK Input Clock /i Delay Match Delay Line 133 MHz 133 MHz PLL FB Delay Line /j /i /i Delay Match CLK1 CLK2 133 MHz FBMuxSel 6 DividerI 1 5 DelayLine Q LowFreq 3 Osc SET D QCLR Clock Network Figure 2-56 * Using the PLL for Clock Deskewing R ev i si o n 1 8 2- 85 Detailed Specifications Embedded Memory The AX architecture provides extensive, high-speed memory resources to the user. Each 4,608 bit block of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either RAM or FIFO. To meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write operations. However, the read and write clocks are completely independent, and each may operate up to and above 500 MHz. No additional core logic resources are required to cascade the address and data buses when cascading different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading. The AX memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A block diagram of the memory module is illustrated in Figure 2-57. During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion. RA [K:0] REN RCLK WD [(M-1):0] WA [J:0] WEN WCLK PIPE RW [2:0] WW [2:0] Figure 2-57 * Axcelerator Memory Module 2- 86 R ev i sio n 1 8 RD [(N-1):0] Axcelerator Family FPGAs RAM Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion (Table 2-86). Each block has independent read and write ports which enable simultaneous read and write operations. Table 2-86 * Memory Block WxD Options Data-word (in bits) Depth Address Bus Data Bus 1 4,096 RA/WA[11:0] RD/WD[0] 2 2,048 RA/WA[10:0] RD/WD[1:0] 4 1,024 RA/WA[9:0] RD/WD[3:0] 9 512 RA/WA[8:0] RD/WD[8:0] 18 256 RA/WA[7:0] RD/WD[17:0] 36 128 RA/WA[6:0] RD/WD[35:0] Clocks The RCLK and the WCLK have independent source polarity selection and can be sourced by any global or local signal. RAM Configurations The AX architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins. The D x W different configurations are: 128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in Table 2-87. Table 2-87 * Allowable RW and WW Values RW(2:0) WW(2:0) DxW 000 000 4k x 1 001 001 2k x 2 010 010 1k x 4 011 011 512 x 9 100 100 256 x 18 101 101 128 x 36 11x 11x reserved When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing ninebit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing fourbit values and reading nine-bit values, the ninth bit of a read operation will be undefined. R ev i si o n 1 8 2- 87 Detailed Specifications Note that the RAM blocks employ little-endian byte order for read and write operations. Table 2-88 * RAM Signal Description Signal Direction Description WCLK Input Write clock (can be active on either edge). WA[J:0] Input Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. WD[M-1:0] Input Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. RCLK Input Read clock (can be active on either edge). RA[K:0] Input Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. REN Input Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. WEN Input Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. RW[2:0] Input Width of the read operation dataword. WW[2:0] Input Width of the write operation dataword. Pipe Input Sets the pipe option to be on or off. Modes of Operation There are two read modes and one write mode: * Read Nonpipelined (synchronous - one clock edge) * Read Pipelined (synchronous - two clock edges) * Write (synchronous - one clock edge) In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the read-port active-clock edge and data appears at read-data after the RAM access time. Setting the PIPE to OFF enables this mode. The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements beginning in the "Timing Characteristics" section on page 2-89. 2- 88 R ev i sio n 1 8 Axcelerator Family FPGAs Timing Characteristics WD RD WA RA WCLK RCLK WEN REN Figure 2-58 * SRAM Model tWCKH tWCKP tWCKL WCLK tWxxSU tWxxHD WA<11:0>, WD<35:0>, WEN<4:0> Figure 2-59 * RAM Write Timing Waveforms tRCKH tRCKP tRCKL RCLK tRxxSU tRxxHD RA<11:0>, REN<4:0> tRCK2RD1 tRCK2RD2 RD <35:0> Figure 2-60 * RAM Read Timing Waveforms R ev i si o n 1 8 2- 89 Detailed Specifications Table 2-89 * One RAM Block Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.08 1.23 1.45 ns tWDAHD Write Data Hold vs. WCLK 0.22 0.25 0.30 ns tWADSU Write Address Setup vs. WCLK 1.08 1.23 1.45 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 1.08 1.23 1.45 ns tWENHD Write Enable Hold vs. WCLK 0.22 0.25 0.30 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 0.88 0.88 0.88 ns tWCKP WCLK Minimum Period 1.63 1.63 1.63 ns Read Mode tRADSU Read Address Setup vs. RCLK 0.81 0.92 1.08 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 0.81 0.92 1.08 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-to-OUT (Pipelined) 1.32 1.51 1.77 ns tRCK2RD2 RCLK-to-OUT (Non-Pipelined) 2.16 2.46 2.90 ns tRCLKH RCLK Minimum High Pulse Width 0.77 0.77 0.77 ns tRCLKL RCLK Minimum Low Pulse Width 0.93 0.93 0.93 ns tRCKP RCLK Minimum Period 1.70 1.70 1.70 ns Note: Timing data for this single block RAM has a depth of 4,096. For all other combinations, use Microsemi's timing software. 2- 90 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-90 * Two RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 1.39 1.59 1.87 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 1.39 1.59 1.87 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 1.39 1.59 1.87 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 1.76 1.76 1.76 ns tWCKP WCLK Minimum Period 2.51 2.51 2.51 ns Read Mode tRADSU Read Address Setup vs. RCLK 1.71 1.94 2.28 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 1.71 1.94 2.28 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.43 1.63 1.92 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.26 2.58 3.03 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 1.89 1.89 1.89 ns tRCKP RCLK Minimum Period 2.62 2.62 2.62 ns Note: Timing data for these two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use Microsemi's timing software. R ev i si o n 1 8 2- 91 Detailed Specifications Table 2-91 * Four RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 2.37 2.70 3.17 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 2.37 2.70 3.17 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 2.37 2.70 3.17 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 2.51 2.51 2.51 ns tWCKP WCLK Minimum Period 3.26 3.26 3.26 ns Read Mode tRADSU Read Address Setup vs. RCLK 3.08 3.51 4.13 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 3.08 3.51 4.13 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 2.36 2.69 3.16 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.83 3.23 3.79 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 2.96 2.96 2.96 ns tRCKP RCLK Minimum Period 3.69 3.69 3.69 ns Note: Timing data for these four cascaded RAM blocks uses a depth of 16,384. For all other combinations, use Microsemi's timing software. 2- 92 R ev i sio n 1 8 Axcelerator Family FPGAs Table 2-92 * Eight RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 5.78 6.58 7.74 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 5.78 6.58 7.74 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 5.78 6.58 7.74 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 5.13 5.13 5.13 ns tWCKP WCLK Minimum Period 5.88 5.88 5.88 ns Read Mode tRADSU Read Address Setup vs. RCLK 6.75 7.69 9.04 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 6.75 7.69 9.04 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.39 3.86 4.54 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 4.93 5.62 6.61 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 5.77 5.77 5.77 ns tRCKP RCLK Minimum Period 6.50 6.50 6.50 ns Note: Timing data for these eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use Microsemi's timing software. R ev i si o n 1 8 2- 93 Detailed Specifications Table 2-93 * Sixteen RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 16.54 18.84 22.15 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 16.54 18.84 22.15 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 16.54 18.84 22.15 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 13.40 13.40 13.40 ns tWCKP WCLK Minimum Period 14.15 14.15 14.15 ns Read Mode tRADSU Read Address Setup vs. RCLK 18.13 20.65 24.27 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 18.13 20.65 24.27 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 12.08 13.76 16.17 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 12.83 14.62 17.18 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 14.41 14.41 14.41 ns tRCKP RCLK Minimum Period 15.14 15.14 15.14 ns Note: Timing data for these sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use Microsemi's timing software. 2- 94 R ev i sio n 1 8 Axcelerator Family FPGAs FIFO Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one write port. This embedded FIFO controller uses no internal FPGA logic and features: * Glitch-free FIFO Flags * Gray-code address counters/pointers to prevent metastability problems * Overflow and underflow control Both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the RAM block size. Each port is fully synchronous. Read and write operations can be completely independent. Data on the appropriate WD pins are written to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output on the appropriate RD pins on every active RCLK edge as long as REN is asserted. The FIFO block offers programmable almost-empty (AEMPTY) and almost-full (AFULL) flags as well as EMPTY and FULL flags (Figure 2-61): * The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full. * The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty condition. Gray code counters are used to prevent metastability problems associated with flag logic. The depth of the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are synchronous with respect to the RCLK. The FIFO block may be reset to the empty state. RD [n-1:0] RD WD [n-1:0] RCLK WCLK RCLK WCLK RAM REN WEN PIPE RA [J:0] WA [J:0] RW[2:0] WW[2:0] WD FREN CNT 16 E FULL = AFULL AFVAL SUB 16 > AEMPTY >= AEVAL FWEN CNT 16 E WIDTH[2:0] DEPTH[3:0] = EMPTY CLR Figure 2-61 * Axcelerator RAM with Embedded FIFO Controller R ev i si o n 1 8 2- 95 Detailed Specifications FIFO Flag Logic The FIFO is user configurable into various DEPTHs and WIDTHs. Figure 2-62 shows the FIFO address counter details. * Bits 11 to 5 are active for all modes. * As the data word size is reduced, more least-significant bits are added to the address. * As the number of cascaded blocks increases, the number of significant bits in the address increases. For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each RAM block, whereas bits 13 and 12 will be used to specify the RAM block. FIFO Address Counters Mode when Active Counter Bits FIFO Address Alignment of Threshold bits Cas 16 blks CNTR [15] activate R/W EN[3] Cas 8 blks CNTR [14] activate R/W EN[2] AEVAL/AFVAL[6] Cas 4 blks CNTR [13] activate R/W EN[1] AEVAL/AFVAL[5] CNTR [12] activate R/W EN[0] AEVAL/AFVAL[4] Cas 2 blks by 36 R/W ADD[11:8] CNTR [11:5] R/W ADD[7:5] always active AEVAL/AFVAL[7] AEVAL/AFVAL[3:0] not compared by 18 CNTR [4] activate R/W ADD[4] not compared by 9 CNTR [3] activate R/W ADD[3] not compared by 4 CNTR [2] activate R/W ADD[2] not compared by 2 CNTR [1] activate R/W ADD[1] not compared by 1 CNTR [0] activate R/W ADD[0] not compared [15:W] [14:W] [13:W] [12:W] 128x36 256x18 [11:5] 512x9 [11:4] 1kx4 2kx2 4kx1 [11:3] [11:2] CNTR [15:0] [11:1] [11:0] Variable Active Address Space >> REN [4:0], RAD [11:0] >> WEN [4:0], WAD [11:0] Note: Inactive counter bits are set to zero. Figure 2-62 * FIFO Address Counters The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. The effective number of threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-94). Table 2-94 * FIFO Flag Logic Inactive AEVAL/AFVAL Bits Inactive DIFF Bits (set to 0) Non-cascade [7:4] [15:12] DIFF[11:8] withAE/FVAL[3:0] Cascade 2 blocks [7:5] [15:13] DIFF[12:8] withAE/FVAL[4:0] Cascade 4 blocks [7:6] [15:14] DIFF[13:8] withAE/FVAL[5:0] Cascade 8 blocks [7] [15] DIFF[14:8] withAE/FVAL[6:0] Cascade 16 blocks None None DIFF[15:8] withAE/FVAL[7:0] Mode 2- 96 R ev i sio n 1 8 DIFF Comparison to AFVAL/AEVAL Axcelerator Family FPGAs Figure 2-63 illustrates flag generation. ALMOST EMPTY and ALMOST FULL Logic AEMPTY AEVAL [7:0], GND [7:0] (MSB....LSB) X WCLK Y 16 WCNTR [15:0] X>=Y (16 bit) DIFF [15:0] RCLK 16 RCNTR [15:0] AFULL X AFVAL [7:0], GND [7:0] (MSB....LSB) Y Figure 2-63 * ALMOST-EMPTY and ALMOST-FULL Logic The Verilog codes for the flags are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-95). Table 2-95 * Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 1 1x1 4 2 1x2 4 2 2x1 5 4 1x4 4 4 2x2 5 4 4x1 6 8 1x8 4 8 2x4 5 8 4x2 6 8 8x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-100. R ev i si o n 1 8 2- 97 Detailed Specifications Glitch Elimination An analog filter is added to each FIFO controller to guarantee glitch-free FIFO-flag logic. Overflow and Underflow Control The counter MSB keeps track of the difference between the read address (RA) and the write address (WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the write address is double-sampled by the read clock prior to comparison with the read address (part A in Figure 2-64). To prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part B in Figure 2-64). A B RA WA RCLK RA = = EMPTY WCLK WA FULL Figure 2-64 * Overflow and Underflow Control FIFO Configurations Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO, the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable word widths, as shown in Table 2-96. Table 2-96 * FIFO Width Configurations WIDTH(2:0) WxD 000 1 x 4k 001 2 x 2k 010 4 x 1k 011 9 x 512 100 18 x 256 101 36 x 128 11x reserved The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2, 4, 8, and 16 to be specified. Table 2-86 on page 2-87 describes the FIFO depth options for various data width and memory blocks. Interface Figure 2-65 on page 2-99 shows a logic block diagram of the Axcelerator FIFO module. Cascading FIFO Blocks FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be taken into account when building the FIFO blocks manually. However, when using SmartGen, the user only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically configures these blocks to optimize performance. 2- 98 R ev i sio n 1 8 Axcelerator Family FPGAs Clock As with RAM configuration, the RCLK and WCLK pins have independent polarity selection. DEPTH [3:0] RD [35:0] WIDTH [2:0] PIPE FREN FULL RCLK AEVAL [7:0] EMPTY AFULL AEMPTY AFVAL [7:0] WD [35:0] FWEN WCLK CLR Figure 2-65 * FIFO Block Diagram Table 2-97 * FIFO Signal Description Signal Direction Description WCLK Input Write clock (active either edge). FWEN Input FIFO write enable. When this signal is asserted, the WD bus data is latched into the FIFO, and the internal write counters are incremented. WD[N-1:0] Input Write data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. FULL Output Active high signal indicating that the FIFO is FULL. When this signal is set, additional write requests are ignored. AFULL Output Active high signal indicating that the FIFO is AFULL. AFVAL Input 8-bit input defining the AFULL value of the FIFO. RCLK Input Read clock (active either edge). FREN Input FIFO read enable. RD[N-1:0] Output Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. EMPTY Output Empty flag indicating that the FIFO is EMPTY. When this signal is asserted, attempts to read the FIFO will be ignored. AEMPTY Output Active high signal indicating that the FIFO is AEMPTY. AEVAL Input 8-bit input defining the almost-empty value of the FIFO. PIPE Input Sets the pipe option on or off. CLR Input Active high clear input. DEPTH Input Determines the depth of the FIFO and the number of FIFOs to be cascaded. WIDTH Input Determines the width of the dataword/FIFO, and the number of the FIFOs to be cascaded. R ev i si o n 1 8 2- 99 Timing Characteristics WD RD AEMPTY EMPTY AFULL FULL FWEN FREN WCLK RCLK Clr Figure 2-66 * FIFO Model tWCKP tWCKH tWCKL WCLK tWSU tWHD WD<35:0>, FWEN tCLR2HF CLR tCLR2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-67 * FIFO Write Timing tCK2xF Axcelerator Family FPGAs tRCKH tRCKP RCLK tRSU tRCKL tRHD FREN tRCK2RD1 tRCK2RD2 RD <35:0> tCLRHF CLR tCLR2xF tCK2xF EMPTY, AEMPTY, AFULL, FULL Figure 2-68 * FIFO Read Timing R ev i si o n 1 8 2- 101 Detailed Specifications Table 2-98 * One FIFO Block Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 11.40 12.98 15.26 ns tWHD Write Hold 0.22 0.25 0.30 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 0.88 0.88 0.88 ns tWCKP Minimum WCLK Period tRSU Read Setup 11.63 13.25 15.58 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.77 0.77 0.77 ns tRCKL RCLK Low 0.93 0.93 0.93 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.32 1.51 1.77 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 2.16 2.46 2.90 ns 1.63 1.63 1.70 1.63 1.70 ns 1.70 ns Note: Timing data for this single block FIFO has a depth of 4,096. For all other combinations, use Microsemi's timing software. 2- 10 2 R ev isio n 1 8 Axcelerator Family FPGAs Table 2-99 * Two FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 13.75 15.66 18.41 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 1.76 1.76 1.76 ns tWCKP Minimum WCLK Period tRSU Read Setup 14.33 16.32 19.19 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 1.89 1.89 1.89 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.43 1.63 1.92 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.26 2.58 3.03 ns 2.51 2.51 2.62 2.51 2.62 ns 2.62 ns Note: Timing data for these two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, use Microsemi's timing software. R ev i si o n 1 8 2- 103 Detailed Specifications Table 2-100 * Four FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 14.60 16.63 19.55 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 2.51 2.51 2.51 ns tWCKP Minimum WCLK Period tRSU Read Setup 15.27 17.39 20.44 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 2.96 2.96 2.96 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 2.36 2.69 3.16 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.83 3.23 3.79 ns 3.26 3.26 3.69 3.26 3.69 ns 3.69 ns Note: Timing data for these four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, use Microsemi's timing software. 2- 10 4 R ev isio n 1 8 Axcelerator Family FPGAs Table 2-101 * Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 15.46 17.61 20.70 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 5.13 5.13 5.13 ns tWCKP Minimum WCLK Period tRSU Read Setup 16.22 18.47 21.72 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 5.77 5.77 5.77 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.39 3.86 4.54 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 4.93 5.62 6.61 ns 5.88 5.88 6.50 5.88 6.50 ns 6.50 ns Note: Timing data for these eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, use Microsemi's timing software. R ev i si o n 1 8 2- 105 Detailed Specifications Table 2-102 * Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70C -2 Speed Parameter Description Min. Max. -1 Speed Min. Max. Std Speed Min. Max. Units FIFO Module Timing tWSU Write Setup 16.32 18.60 21.86 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 13.40 13.40 13.40 ns tWCKP Minimum WCLK Period tRSU Read Setup 17.16 19.54 22.97 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 14.41 14.41 14.41 ns tRCKP Minimum RCLK period tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 12.08 13.76 16.17 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 12.83 14.62 17.18 ns 14.15 14.15 15.14 14.15 15.14 ns 15.14 ns Note: Timing data for these sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, use Microsemi's timing software. Building RAM and FIFO Modules RAM and FIFO modules can be generated and included in a design in two different ways: * Using the SmartGen Core Generator where the user defines the depth and width of the FIFO/RAM, and then instantiates this block into the design (refer to the SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User's Guide for more information). * The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground. Other Architectural Features Low Power Mode Although designed for high performance, the AX architecture also allows the user to place the device into a low power mode. Each I/O bank in an Axcelerator device can be configured individually, when in low power mode, to tristate all outputs, disable inputs, or both. The low power mode is activated by asserting the LP pin, which is grounded in normal operation. While in the low power mode, the device is still fully functional and all internal logic states are preserved. This allows a user to disable all but a few signals and operate the part in a low-frequency, watchdog 2- 10 6 R ev isio n 1 8 Axcelerator Family FPGAs mode if desired. Please note, if the I/O bank is not disabled, differential I/Os belonging to the I/O bank will still consume normal power, even when operating in the low power mode. The Axcelerator device will resume normal operation 10s after the LP pin is pulled Low. To further reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in no DC current draw. The Axcelerator family devices have a dedicated "VPUMP" pin that can be used to access an external charge pump device. In normal chip operation, when using the internal charge pump, VPUMP should be tied to GND. When the voltage level on VPUMP is set to 3.3V, the internal charge pump is turned off, and the VPUMP voltage will be used as the charge pump voltage. Adequate voltage regulation (i.e. high drive, low output impedance, and good decoupling) should be used at VPUMP. In addition, any PLL in use can be powered down to further reduce power consumption. This can be done with the PowerDown pin driven Low. Driving this pin High restarts the PLL with the output clock(s) being stable once lock is restored. JTAG Axcelerator offers a JTAG interface that is compliant with the IEEE 1149.1 standard. The user can employ the JTAG interface for probing a design and performing any JTAG Public Instructions as defined in the Table 2-103. Table 2-103 * JTAG Instruction Code Instruction (IR4:IR0) Binary Code Extest 00000 Preload / Sample 00001 Intest 00010 USERCODE 00011 IDCODE 00100 HIGHZ 01110 CLAMP 01111 Diagnostic 10000 Reserved All others Bypass 11111 Interface The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up resistors. TRST TRST (Test-Logic Reset) is an active-low, asynchronous reset signal to the TAP controller. The TRST input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the TRST state, it is recommended to connect TRST to ground via a 1 k resistor. There is an optional internal pull-up resistor available for the TRST input that can be set by the user at programming. Care should be exercised when using this option in combination with an external tie-off to ground. An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST," but it only occurs at power-up or during recovery from a VCCA and/or VCCDA voltage drop. R ev i si o n 1 8 2- 107 Detailed Specifications TDO TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or "Shift_IR" state. The least significant bit of the selected register (i.e. IR or DR) is clocked out to TDO first by the falling edge of TCK. TAP Controller The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that controls the Instruction Register (IR) and the Data Registers (such as BSR, IDCODE, USRCODE, BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at the rising edges of TCK. Instruction Register (IR) The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR." When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111". If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully" flag. Data Registers (DRs) Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data registers. Descriptions of the main registers are as follow: 1. IDCODE: The IDCODE is a 20-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code, which contains the Microsemi identity, part number, and version number in a specific JTAG format. 2. USERCODE: The USERCODE is a 33-bit programmable register. However, only 20 bits are allocated to use as JTAG Silicon Signature. It is a supplementary identity code for the user to program information to distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. 3. Boundary-Scan Register (BSR): Each I/O contains three Boundary-Scan Cells. Each cell has a shift register bit, a latch, and two MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I) registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan cells are then chained serially to form the Boundary-Scan Register (BSR). The length of the BSR is the number of I/Os in the die multiplied by three. 4. Bypass Register (BYR): This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to only one bit per device not being tested. It is also selected for all "reserved" or unused instructions. Probing Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB," "PRC," and "PRD." Special Fuses Security Microsemi antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live-at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device during power-up, thus protecting against device cloning. In addition, special security fuses are hidden 2- 10 8 R ev isio n 1 8 Axcelerator Family FPGAs throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an Axcelerator device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse FPGAs white paper). Look for this symbol to ensure your valuable IP is protected with highest level of security in the industry. TM u e Figure 2-69 * FuseLock Logo To ensure maximum security in Axcelerator devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. For more information, refer to the Implementation of Security in Actel Antifuse FPGAs application note. Global Set Fuse The Global Set Fuse determines if all R-cells and I/O registers (InReg, OutReg, and EnReg) are either cleared or preset by driving the GCLR and GPSET inputs of all R-cells and I/O Registers (Figure 2-31 on page 2-58). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and GPSET= 0). A local CLR or PRESET will take precedence over this setting. Both pins are pulled High during normal device operation. For use details, see the Libero IDE online help. Silicon Explorer II Probe Interface Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is operating in a prototype or a production system. The user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. Highlighted nets in Designer's ChipPlanner can be accessed using Silicon Explorer II in order to observe their real time values. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route program cycles, the integrity of the design is maintained throughout the debug process. Each member of the Axcelerator family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four probe signals from the Axcelerator device (note that the AX125 only has two probe signals that can be observed: PRA and PRB). Each core tile has up to two probe signals. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on page 2-108). Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-7). Once the design has been placed-and-routed, and the Axcelerator device has been programmed, Silicon Explorer II can be connected and the Explorer software can be launched. Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. R ev i si o n 1 8 2- 109 Detailed Specifications Programming Device programming is supported through the Silicon Sculptor II, a single-site, robust and compact device programmer for the PC. Up to four Silicon Sculptor IIs can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor II to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor II also provides a self-test to test its own hardware extensively. Programming an Axcelerator device using Silicon Sculptor II is similar to programming any other antifuse device. The procedure is as follows: 1. Load the *.AFM file. 2. Select the device to be programmed. 3. Begin programming. When the design is ready to go to production, Microsemi offers device volume-programming services either through distribution partners or via our In-House Programming Center. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Axcelerator devices. For more details on programming the Axcelerator devices, please refer to the Silicon Sculptor II User's Guide. 2- 11 0 R ev isio n 1 8 Axcelerator Family FPGAs R ev i si o n 1 8 2- 111 3 - Package Pin Assignments BG729 A1 Ball Pad Corner 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3 -1 Package Pin Assignments BG729 BG729 AX1000 Function Pin Number Bank 0 3- 2 BG729 AX1000 Function Pin Number AX1000 Function Pin Number IO18NB0F1 C10 IO36NB1F3 H15 IO00NB0F0 E6 IO18PB0F1 C9 IO36PB1F3 G15 IO00PB0F0 F6 IO19NB0F1 E11 IO37NB1F3 C17 IO01NB0F0 G8 IO19PB0F1 F11 IO37PB1F3 C16 IO01PB0F0 G7 IO20NB0F1 G12 IO38NB1F3 B18 IO02NB0F0 D7 IO20PB0F1 H12 IO38PB1F3 B17 IO02PB0F0 E7 IO21NB0F1 D11 IO39NB1F3 A18 IO03NB0F0 D5 IO21PB0F1 D10 IO39PB1F3 A17 IO03PB0F0 E5 IO22NB0F2 A10 IO40NB1F3 H16 IO04NB0F0 G9 IO22PB0F2 A9 IO40PB1F3 G16 IO04PB0F0 H9 IO23NB0F2 B11 IO41NB1F4 B19 IO05NB0F0 E8 IO23PB0F2 B10 IO41PB1F4 A19 IO05PB0F0 F8 IO24NB0F2 G13 IO42NB1F4 C19 IO06NB0F0 C6 IO24PB0F2 H13 IO42PB1F4 C18 IO06PB0F0 D6 IO25NB0F2 C12 IO43NB1F4 D18 IO07NB0F0 B5 IO25PB0F2 C11 IO43PB1F4 D17 IO07PB0F0 C5 IO26NB0F2 E12 IO44NB1F4 H17 IO08NB0F0 A6 IO26PB0F2 D12 IO44PB1F4 G17 IO08PB0F0 A5 IO27NB0F2 E13 IO45NB1F4 F17 IO09NB0F0 E9 IO27PB0F2 F13 IO45PB1F4 E17 IO09PB0F0 F9 IO28NB0F2 G14 IO46NB1F4 B20 IO10NB0F0 G10 IO28PB0F2 H14 IO46PB1F4 A20 IO10PB0F0 H10 IO29NB0F2 A12 IO47NB1F4 C21 IO11NB0F0 B7 IO29PB0F2 B12 IO47PB1F4 C20 IO11PB0F0 B6 IO30NB0F2/HCLKAN C13 IO48NB1F4 H18 IO12NB0F1 C8 IO30PB0F2/HCLKAP D13 IO48PB1F4 G18 IO12PB0F1 C7 IO31NB0F2/HCLKBN F14 IO49NB1F4 F18 IO13NB0F1 E10 IO31PB0F2/HCLKBP E14 IO49PB1F4 E18 IO13PB0F1 F10 Bank 1 IO50NB1F4 D20 IO14NB0F1 G11 IO32NB1F3/HCLKCN C14 IO50PB1F4 D19 IO14PB0F1 H11 IO32PB1F3/HCLKCP B14 IO51NB1F4 A22 IO15NB0F1 D9 IO33NB1F3/HCLKDN D16 IO51PB1F4 A21 IO15PB0F1 D8 IO33PB1F3/HCLKDP D15 IO52NB1F4 B22 IO16NB0F1 A8 IO34NB1F3 B16 IO52PB1F4 B21 IO16PB0F1 A7 IO34PB1F3 A16 IO53NB1F4 F19 IO17NB0F1 B9 IO35NB1F3 E15 IO53PB1F4 E19 IO17PB0F1 B8 IO35PB1F3 F15 IO54NB1F5 F20 R ev isio n 1 8 Axcelerator Family FPGAs BG729 BG729 BG729 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO54PB1F5 E20 IO72PB2F6 J23 IO91NB2F8 N25 IO55NB1F5 E21 IO73NB2F6 H24 IO91PB2F8 N24 IO55PB1F5 D21 IO73PB2F6 H23 IO92NB2F8 N27 IO56NB1F5 H19 IO74NB2F7 L21 IO92PB2F8 N26 IO56PB1F5 G19 IO74PB2F7 K21 IO93NB2F8 P26 IO57NB1F5 D22 IO75NB2F7 G27 IO93PB2F8 P27 IO57PB1F5 C22 IO75PB2F7 F27 IO94NB2F8 N19 IO58NB1F5 B23 IO76NB2F7 K23 IO94PB2F8 N20 IO58PB1F5 A23 IO76PB2F7 K22 IO95NB2F8 P23 IO59NB1F5 D23 IO77NB2F7 H26 IO95PB2F8 P22 IO59PB1F5 C23 IO77PB2F7 H25 IO60NB1F5 G21 IO78NB2F7 K25 IO96NB3F9 P25 IO60PB1F5 G20 IO78PB2F7 K24 IO96PB3F9 P24 IO61NB1F5 E23 IO79NB2F7 J26 IO97NB3F9 R26 IO61PB1F5 E22 IO79PB2F7 J25 IO97PB3F9 R27 IO62NB1F5 F22 IO80NB2F7 M20 IO98NB3F9 P21 IO62PB1F5 F21 IO80PB2F7 L20 IO98PB3F9 P20 IO63NB1F5 H20 IO81NB2F7 J27 IO99NB3F9 R24 IO63PB1F5 J19 IO81PB2F7 H27 IO99PB3F9 R25 IO82NB2F7 L23 IO100NB3F9 T26 Bank 2 Bank 3 IO64NB2F6 J21 IO82PB2F7 L22 IO100PB3F9 T27 IO64PB2F6 H21 IO83NB2F7 L25 IO101NB3F9 T24 IO65NB2F6 F24 IO83PB2F7 L24 IO101PB3F9 T25 IO65PB2F6 F23 IO84NB2F7 N21 IO102NB3F9 R20 IO66NB2F6 F26 IO84PB2F7 M21 IO102PB3F9 R21 IO66PB2F6 F25 IO85NB2F8 K27 IO103NB3F9 R23 IO67NB2F6 E26 IO85PB2F8 K26 IO103PB3F9 R22 IO67PB2F6 E25 IO86NB2F8 M23 IO104NB3F9 U26 IO68NB2F6 J22 IO86PB2F8 M22 IO104PB3F9 U27 IO68PB2F6 H22 IO87NB2F8 M25 IO105NB3F9 U24 IO69NB2F6 G24 IO87PB2F8 M24 IO105PB3F9 U25 IO69PB2F6 G23 IO88NB2F8 L27 IO106NB3F9 R19 IO70NB2F6 K20 IO88PB2F8 L26 IO106PB3F9 P19 IO70PB2F6 J20 IO89NB2F8 M27 IO107NB3F10 V26 IO71NB2F6 G26 IO89PB2F8 M26 IO107PB3F10 V27 IO71PB2F6 G25 IO90NB2F8 N23 IO108NB3F10 T23 IO72NB2F6 J24 IO90PB2F8 N22 IO108PB3F10 T22 R ev i si o n 1 8 3 -3 Package Pin Assignments BG729 3- 4 BG729 BG729 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO109NB3F10 V24 IO127PB3F11 AC27 IO145PB4F13 AD19 IO109PB3F10 V25 IO128NB3F11 Y20 IO146NB4F13 AC18 IO110NB3F10 T20 IO128PB3F11 W19 IO146PB4F13 AB18 IO110PB3F10 T21 IO147NB4F13 Y17 IO111NB3F10 W26 IO129NB4F12 AA20 IO147PB4F13 AA17 IO111PB3F10 W27 IO129PB4F12 Y21 IO148NB4F13 AF19 IO112NB3F10 U22 IO130NB4F12 AB22 IO148PB4F13 AF20 IO112PB3F10 U23 IO130PB4F12 AB23 IO149NB4F13 AC17 IO113NB3F10 Y26 IO131NB4F12 AC22 IO149PB4F13 AB17 IO113PB3F10 Y27 IO131PB4F12 AC23 IO150NB4F13 AE18 IO114NB3F10 U20 IO132NB4F12 AD23 IO150PB4F13 AE19 IO114PB3F10 U21 IO132PB4F12 AD24 IO151NB4F13 AA16 IO115NB3F10 W24 IO133NB4F12 AF23 IO151PB4F13 Y16 IO115PB3F10 W25 IO133PB4F12 AE23 IO152NB4F14 AG18 IO116NB3F10 V22 IO134NB4F12 AC21 IO152PB4F14 AG19 IO116PB3F10 V23 IO134PB4F12 AB21 IO153NB4F14 AC16 IO117NB3F10 Y24 IO135NB4F12 AC20 IO153PB4F14 AB16 IO117PB3F10 Y25 IO135PB4F12 AB20 IO154NB4F14 AF17 IO118NB3F11 V20 IO136NB4F12 AD21 IO154PB4F14 AF18 IO118PB3F11 V21 IO136PB4F12 AD22 IO155NB4F14 AB15 IO119NB3F11 AA26 IO137NB4F12 Y19 IO155PB4F14 AC15 IO119PB3F11 AA27 IO137PB4F12 AA19 IO156NB4F14 AE16 IO120NB3F11 W22 IO138NB4F12 AE21 IO156PB4F14 AE17 IO120PB3F11 W23 IO138PB4F12 AE22 IO157NB4F14 Y15 IO121NB3F11 AA24 IO139NB4F13 AF21 IO157PB4F14 AA15 IO121PB3F11 AA25 IO139PB4F13 AF22 IO158NB4F14 AG16 IO122NB3F11 W20 IO140NB4F13 AG22 IO158PB4F14 AG17 IO122PB3F11 W21 IO140PB4F13 AG23 IO159NB4F14/CLKEN AF15 IO123NB3F11 AB26 IO141NB4F13 Y18 IO159PB4F14/CLKEP AF16 IO123PB3F11 AB27 IO141PB4F13 AA18 IO160NB4F14/CLKFN AD14 IO124NB3F11 Y22 IO142NB4F13 AE20 IO160PB4F14/CLKFP AD15 IO124PB3F11 Y23 IO142PB4F13 AD20 IO125NB3F11 AB24 IO143NB4F13 AG20 IO161NB5F15/CLKGN AE14 IO125PB3F11 AB25 IO143PB4F13 AG21 IO161PB5F15/CLKGP AE15 IO126NB3F11 AA22 IO144NB4F13 AC19 IO162NB5F15/CLKHN AC13 IO126PB3F11 AA23 IO144PB4F13 AB19 IO162PB5F15/CLKHP AD13 IO127NB3F11 AC26 IO145NB4F13 AD18 IO163NB5F15 Y14 Bank 4 R ev isio n 1 8 Bank 5 Axcelerator Family FPGAs BG729 BG729 BG729 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO163PB5F15 AA14 IO182NB5F17 AF7 IO200NB6F18 AA4 IO164NB5F15 AE13 IO182PB5F17 AG7 IO200PB6F18 AA5 IO164PB5F15 AF13 IO183NB5F17 AD7 IO201NB6F18 W5 IO165NB5F15 AF12 IO183PB5F17 AE7 IO201PB6F18 W6 IO165PB5F15 AG12 IO184NB5F17 AC7 IO202NB6F18 AB1 IO166NB5F15 AD12 IO184PB5F17 AC8 IO202PB6F18 AC1 IO166PB5F15 AE12 IO185NB5F17 AF6 IO203NB6F19 Y3 IO167NB5F15 Y13 IO185PB5F17 AG6 IO203PB6F19 AA3 IO167PB5F15 AA13 IO186NB5F17 AB7 IO204NB6F19 AA2 IO168NB5F15 AD11 IO186PB5F17 AB8 IO204PB6F19 AB2 IO168PB5F15 AE11 IO187NB5F17 Y9 IO205NB6F19 U8 IO169NB5F15 AG11 IO187PB5F17 AA9 IO205PB6F19 V8 IO169PB5F15 AF11 IO188NB5F17 AD6 IO206NB6F19 V5 IO170NB5F15 AB11 IO188PB5F17 AE6 IO206PB6F19 V6 IO170PB5F15 AC11 IO189NB5F17 AB6 IO207NB6F19 Y1 IO171NB5F16 AF10 IO189PB5F17 AC6 IO207PB6F19 AA1 IO171PB5F16 AG10 IO190NB5F17 AF5 IO208NB6F19 W4 IO172NB5F16 AD10 IO190PB5F17 AG5 IO208PB6F19 Y4 IO172PB5F16 AE10 IO191NB5F17 AA6 IO209NB6F19 T7 IO173NB5F16 Y12 IO191PB5F17 AA7 IO209PB6F19 U7 IO173PB5F16 AA12 IO192NB5F17 Y8 IO210NB6F19 W2 IO174NB5F16 AB10 IO192PB5F17 AA8 IO210PB6F19 Y2 IO174PB5F16 AC10 IO211NB6F19 U5 IO175NB5F16 AF9 IO193NB6F18 W8 IO211PB6F19 U6 IO175PB5F16 AG9 IO193PB6F18 Y7 IO212NB6F19 V3 IO176NB5F16 AD9 IO194NB6F18 AB5 IO212PB6F19 W3 IO176PB5F16 AE9 IO194PB6F18 AC5 IO213NB6F19 R9 IO177NB5F16 Y11 IO195NB6F18 AC2 IO213PB6F19 T8 IO177PB5F16 AA11 IO195PB6F18 AC3 IO214NB6F20 U4 IO178NB5F16 AF8 IO196NB6F18 AC4 IO214PB6F20 V4 IO178PB5F16 AG8 IO196PB6F18 AD4 IO215NB6F20 T5 IO179NB5F16 AD8 IO197NB6F18 Y5 IO215PB6F20 T6 IO179PB5F16 AE8 IO197PB6F18 Y6 IO216NB6F20 V1 IO180NB5F16 AB9 IO198NB6F18 AB3 IO216PB6F20 W1 IO180PB5F16 AC9 IO198PB6F18 AB4 IO217NB6F20 R7 IO181NB5F17 Y10 IO199NB6F18 V7 IO217PB6F20 R8 IO181PB5F17 AA10 IO199PB6F18 W7 IO218NB6F20 U2 Bank 6 R ev i si o n 1 8 3 -5 Package Pin Assignments BG729 BG729 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO218PB6F20 V2 IO236PB7F22 L1 IO255NB7F23 F5 IO219NB6F20 T1 IO237NB7F22 L4 IO255PB7F23 G5 IO219PB6F20 U1 IO237PB7F22 L3 IO256NB7F23 F3 IO220NB6F20 R5 IO238NB7F22 L6 IO256PB7F23 F4 IO220PB6F20 R6 IO238PB7F22 M6 IO257NB7F23 H7 IO221NB6F20 T3 IO239NB7F22 M8 IO257PB7F23 J7 IO221PB6F20 T4 IO239PB7F22 M7 IO222NB6F20 R2 IO240NB7F22 K2 GND A1 IO222PB6F20 T2 IO240PB7F22 K1 GND A2 IO223NB6F20 P8 IO241NB7F22 K4 GND A25 IO223PB6F20 P9 IO241PB7F22 K3 GND A26 IO224NB6F20 R3 IO242NB7F22 K5 GND A27 IO224PB6F20 R4 IO242PB7F22 L5 GND A3 IO243NB7F22 J2 GND AC24 Bank 7 3- 6 BG729 Dedicated I/O IO225NB7F21 P1 IO243PB7F22 J1 GND AE1 IO225PB7F21 R1 IO244NB7F22 J4 GND AE2 IO226NB7F21 P3 IO244PB7F22 J3 GND AE25 IO226PB7F21 P2 IO245NB7F22 H2 GND AE26 IO227NB7F21 N7 IO245PB7F22 H1 GND AE27 IO227PB7F21 P7 IO246NB7F22 H4 GND AE3 IO228NB7F21 P5 IO246PB7F22 H3 GND AE5 IO228PB7F21 P4 IO247NB7F23 L8 GND AF1 IO229NB7F21 N2 IO247PB7F23 L7 GND AF2 IO229PB7F21 N1 IO248NB7F23 J6 GND AF25 IO230NB7F21 N6 IO248PB7F23 K6 GND AF26 IO230PB7F21 P6 IO249NB7F23 H5 GND AF27 IO231NB7F21 N9 IO249PB7F23 J5 GND AF3 IO231PB7F21 N8 IO250NB7F23 G2 GND AG1 IO232NB7F21 N4 IO250PB7F23 G1 GND AG2 IO232PB7F21 N3 IO251NB7F23 K8 GND AG25 IO233NB7F21 M2 IO251PB7F23 K7 GND AG26 IO233PB7F21 M1 IO252NB7F23 G4 GND AG27 IO234NB7F21 M4 IO252PB7F23 G3 GND AG3 IO234PB7F21 M3 IO253NB7F23 F2 GND B1 IO235NB7F21 M5 IO253PB7F23 F1 GND B2 IO235PB7F21 N5 IO254NB7F23 G6 GND B25 IO236NB7F22 L2 IO254PB7F23 H6 GND B26 R ev isio n 1 8 Axcelerator Family FPGAs BG729 BG729 BG729 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND B27 GND R11 VCCA K11 GND B3 GND R12 VCCA K17 GND C1 GND R13 VCCA K18 GND C2 GND R14 VCCA L10 GND C25 GND R15 VCCA L18 GND C26 GND R16 VCCA U10 GND C27 GND R17 VCCA U18 GND C3 GND T11 VCCA V10 GND E27 GND T12 VCCA V11 GND L11 GND T13 VCCA V17 GND L12 GND T14 VCCA V18 GND L13 GND T15 VCCPLA A13 GND L14 GND T16 VCCPLB J13 GND L15 GND T17 VCCPLC B15 GND L16 GND U11 VCCPLD C15 GND L17 GND U12 VCCPLE AG14 GND M11 GND U13 VCCPLF AF14 GND M12 GND U14 VCCPLG AB13 GND M13 GND U15 VCCPLH AG13 GND M14 GND U16 VCCDA A11 GND M15 GND U17 VCCDA AB12 GND M16 GND/LP J8 VCCDA AC12 GND M17 NC U3 VCCDA AC25 GND N11 PRA J14 VCCDA AD16 GND N12 PRB D14 VCCDA AD17 GND N13 PRC V14 VCCDA E16 GND N14 PRD AB14 VCCDA E2 GND N15 TCK E4 VCCDA E24 GND N16 TDI D4 VCCDA F12 GND N17 TDO J9 VCCDA F16 GND P11 TMS H8 VCCDA F7 GND P12 TRST E3 VCCDA K14 GND P13 VCCA AA21 VCCDA P10 GND P14 VCCA AD5 VCCDA P18 GND P15 VCCA E1 VCCDA W14 GND P16 VCCA G22 VCCDA W9 GND P17 VCCA K10 VCCIB0 A4 R ev i si o n 1 8 3 -7 Package Pin Assignments BG729 3- 8 BG729 AX1000 Function Pin Number AX1000 Function Pin Number VCCIB0 B4 VCCIB4 W17 VCCIB0 C4 VCCIB4 W18 VCCIB0 J10 VCCIB5 AE4 VCCIB0 J11 VCCIB5 AF4 VCCIB0 J12 VCCIB5 AG4 VCCIB0 K12 VCCIB5 V12 VCCIB0 K13 VCCIB5 V13 VCCIB1 A24 VCCIB5 W10 VCCIB1 B24 VCCIB5 W11 VCCIB1 C24 VCCIB5 W12 VCCIB1 J16 VCCIB6 AD1 VCCIB1 J17 VCCIB6 AD2 VCCIB1 J18 VCCIB6 AD3 VCCIB1 K15 VCCIB6 R10 VCCIB1 K16 VCCIB6 T10 VCCIB2 D25 VCCIB6 T9 VCCIB2 D26 VCCIB6 U9 VCCIB2 D27 VCCIB6 V9 VCCIB2 K19 VCCIB7 D1 VCCIB2 L19 VCCIB7 D2 VCCIB2 M18 VCCIB7 D3 VCCIB2 M19 VCCIB7 K9 VCCIB2 N18 VCCIB7 L9 VCCIB3 AD25 VCCIB7 M10 VCCIB3 AD26 VCCIB7 M9 VCCIB3 AD27 VCCIB7 N10 VCCIB3 R18 VCOMPLA B13 VCCIB3 T18 VCOMPLB A14 VCCIB3 T19 VCOMPLC A15 VCCIB3 U19 VCOMPLD J15 VCCIB3 V19 VCOMPLE AG15 VCCIB4 AE24 VCOMPLF W15 VCCIB4 AF24 VCOMPLG AC14 VCCIB4 AG24 VCOMPLH W13 VCCIB4 V15 VPUMP D24 VCCIB4 V16 VCCIB4 W16 R ev isio n 1 8 Axcelerator Family FPGAs FG256 A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3 -9 Package Pin Assignments FG256-Pin FBGA AX125 Function FG256-Pin FBGA Pin Number Bank 0 FG256-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number IO20NB2F2 F15 IO41PB3F3 L14 IO01NB0F0 B4 IO20PB2F2 E15 IO01PB0F0 B3 IO21NB2F2 C16 IO42NB4F4 N12 IO03NB0F0 A4 IO21PB2F2 B16 IO42PB4F4 N13 IO03PB0F0 A3 IO22NB2F2 H13 IO43NB4F4 T14 IO04NB0F0 B6 IO22PB2F2 G13 IO43PB4F4 R14 IO04PB0F0 B5 IO23NB2F2 E16 IO44PB4F4 T15 IO06NB0F0 A6 IO23PB2F2 D16 IO45NB4F4 R12 IO06PB0F0 A5 IO25NB2F2 H15 IO45PB4F4 R13 IO07NB0F0/HCLKAN B8 IO25PB2F2 G15 IO46NB4F4 P11 IO07PB0F0/HCLKAP B7 IO26NB2F2 H14 IO46PB4F4 P12 IO08NB0F0/HCLKBN A9 IO26PB2F2 G14 IO47PB4F4 T11 IO08PB0F0/HCLKBP A8 IO27NB2F2 G16 IO48NB4F4 T12 IO27PB2F2 F16 IO48PB4F4 T13 Bank 1 Bank 4 IO09NB1F1/HCLKCN C10 IO28NB2F2 K15 IO49NB4F4/CLKEN R9 IO09PB1F1/HCLKCP C9 IO28PB2F2 K16 IO49PB4F4/CLKEP R10 IO10NB1F1/HCLKDN B11 IO29NB2F2 J16 IO50NB4F4/CLKFN T8 IO10PB1F1/HCLKDP B10 IO29PB2F2 H16 IO50PB4F4/CLKFP T9 IO12NB1F1 A13 IO12PB1F1 A12 IO30NB3F3 K13 IO51NB5F5/CLKGN P7 IO13NB1F1 B13 IO30PB3F3 J13 IO51PB5F5/CLKGP P8 IO13PB1F1 B12 IO31NB3F3 K14 IO52NB5F5/CLKHN R6 IO14NB1F1 C12 IO31PB3F3 J14 IO52PB5F5/CLKHP R7 IO14PB1F1 C11 IO33NB3F3 L15 IO54NB5F5 T5 IO15NB1F1 A15 IO33PB3F3 L16 IO54PB5F5 T6 IO15PB1F1 B14 IO35NB3F3 P16 IO55NB5F5 P5 IO16NB1F1 C15 IO35PB3F3 N16 IO55PB5F5 P6 IO16PB1F1 C14 IO36PB3F3 M16 IO56NB5F5 T3 IO17NB1F1 D13 IO37NB3F3 P15 IO56PB5F5 T4 IO17PB1F1 D12 IO37PB3F3 R16 IO57NB5F5 R3 IO39NB3F3 N15 IO57PB5F5 R4 Bank 2 3- 10 Bank 3 Bank 5 IO18NB2F2 F13 IO39PB3F3 M15 IO58NB5F5 R1 IO18PB2F2 E13 IO40NB3F3 M13 IO58PB5F5 T2 IO19NB2F2 F14 IO40PB3F3 L13 IO59NB5F5 N4 IO19PB2F2 E14 IO41NB3F3 M14 IO59PB5F5 N5 R ev i sio n 1 8 Axcelerator Family FPGAs FG256-Pin FBGA AX125 Function FG256-Pin FBGA Pin Number Bank 6 FG256-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number IO81NB7F7 C2 GND M12 IO60NB6F6 L4 IO81PB7F7 B1 GND M5 IO60PB6F6 M4 IO82NB7F7 D2 GND P13 IO61NB6F6 L3 IO82PB7F7 D3 GND P3 IO61PB6F6 M3 IO83NB7F7 E3 GND R15 IO63NB6F6 P2 IO83PB7F7 F3 GND R2 IO63PB6F6 N2 GND T1 IO64NB6F6 J4 VCCDA E4 GND T16 IO64PB6F6 K4 GND A1 GND/LP D4 IO65NB6F6 N1 GND A16 NC A11 IO65PB6F6 P1 GND B15 NC R11 IO67NB6F6 L2 GND B2 NC R5 IO67PB6F6 M2 GND D15 PRA D8 IO69NB6F6 L1 GND E12 PRB C8 IO69PB6F6 M1 GND E5 PRC N9 IO70NB6F6 J3 GND F11 PRD P9 IO70PB6F6 K3 GND F6 TCK D5 IO71NB6F6 J2 GND G10 TDI C6 IO71PB6F6 K2 GND G7 TDO C4 GND G8 TMS C3 Bank 7 Dedicated I/O IO72NB7F7 J1 GND G9 TRST C5 IO72PB7F7 K1 GND H10 VCCA D14 IO73NB7F7 G2 GND H7 VCCA F10 IO73PB7F7 H2 GND H8 VCCA F4 IO74NB7F7 G3 GND H9 VCCA F7 IO74PB7F7 H3 GND J10 VCCA F8 IO75NB7F7 E1 GND J7 VCCA F9 IO75PB7F7 F1 GND J8 VCCA G11 IO76NB7F7 G1 GND J9 VCCA G6 IO77NB7F7 E2 GND K10 VCCA H11 IO77PB7F7 F2 GND K7 VCCA H6 IO78NB7F7 G4 GND K8 VCCA J11 IO78PB7F7 H4 GND K9 VCCA J6 IO79NB7F7 C1 GND L11 VCCA K11 IO79PB7F7 D1 GND L6 VCCA K6 R ev i si o n 1 8 3- 11 Package Pin Assignments FG256-Pin FBGA FG256-Pin FBGA AX125 Function Pin Number AX125 Function Pin Number VCCA L10 VCCIB4 M11 VCCA L7 VCCIB4 M9 VCCA L8 VCCIB5 M6 VCCA L9 VCCIB5 M7 VCCA N3 VCCIB5 M8 VCCA P14 VCCIB6 J5 VCCPLA C7 VCCIB6 K5 VCCPLB D6 VCCIB6 L5 VCCPLC A10 VCCIB7 F5 VCCPLD D10 VCCIB7 G5 VCCPLE P10 VCCIB7 H5 VCCPLF N11 VCOMPLA A7 VCCPLG T7 VCOMPLB D7 VCCPLH N7 VCOMPLC B9 VCCDA A2 VCOMPLD D11 VCCDA C13 VCOMPLE T10 VCCDA D9 VCOMPLF N10 VCCDA H1 VCOMPLG R8 VCCDA J15 VCOMPLH N6 VCCDA N14 VPUMP A14 VCCDA N8 VCCDA P4 VCCIB0 E6 VCCIB0 E7 VCCIB0 E8 VCCIB1 E10 VCCIB1 E11 VCCIB1 E9 VCCIB2 F12 VCCIB2 G12 VCCIB2 H12 VCCIB3 J12 VCCIB3 K12 VCCIB3 L12 VCCIB4 M10 3- 12 R ev i sio n 1 8 Axcelerator Family FPGAs FG256 AX250 Function FG256 Pin Number Bank 0 FG256 AX250 Function Pin Number AX250 Function Pin Number IO32NB2F2 C16 IO61PB3F3 L14 IO01NB0F0 B4 IO32PB2F2 B16 IO01PB0F0 B3 IO33NB2F2 F15 IO62NB4F4 N12 IO03NB0F0 A4 IO33PB2F2 E15 IO62PB4F4 N13 IO03PB0F0 A3 IO35NB2F2 H13 IO63NB4F4 T14 IO05NB0F0 B6 IO35PB2F2 G13 IO63PB4F4 R14 IO05PB0F0 B5 IO36NB2F2 E16 IO66PB4F4 T15 IO07NB0F0 A6 IO36PB2F2 D16 IO67NB4F4 R12 IO07PB0F0 A5 IO38NB2F2 H15 IO67PB4F4 R13 IO12NB0F0/HCLKAN B8 IO38PB2F2 G15 IO69NB4F4 P11 IO12PB0F0/HCLKAP B7 IO39NB2F2 H14 IO69PB4F4 P12 IO13NB0F0/HCLKBN A9 IO39PB2F2 G14 IO70PB4F4 T11 IO13PB0F0/HCLKBP A8 IO40NB2F2 G16 IO73NB4F4 T12 IO40PB2F2 F16 IO73PB4F4 T13 Bank 1 Bank 4 IO14NB1F1/HCLKCN C10 IO43NB2F2 K15 IO74NB4F4/CLKEN R9 IO14PB1F1/HCLKCP C9 IO43PB2F2 K16 IO74PB4F4/CLKEP R10 IO15NB1F1/HCLKDN B11 IO44NB2F2 J16 IO75NB4F4/CLKFN T8 IO15PB1F1/HCLKDP B10 IO44PB2F2 H16 IO75PB4F4/CLKFP T9 IO17NB1F1 A13 IO17PB1F1 A12 IO45NB3F3 K13 IO76NB5F5/CLKGN P7 IO19NB1F1 B13 IO45PB3F3 J13 IO76PB5F5/CLKGP P8 IO19PB1F1 B12 IO46NB3F3 K14 IO77NB5F5/CLKHN R6 IO21NB1F1 C12 IO46PB3F3 J14 IO77PB5F5/CLKHP R7 IO21PB1F1 C11 IO52NB3F3 L15 IO79NB5F5 T5 IO23NB1F1 A15 IO52PB3F3 L16 IO79PB5F5 T6 IO23PB1F1 B14 IO54NB3F3 P16 IO81NB5F5 P5 IO26NB1F1 C15 IO54PB3F3 N16 IO81PB5F5 P6 IO26PB1F1 C14 IO55PB3F3 M16 IO83NB5F5 T3 IO27NB1F1 D13 IO56NB3F3 P15 IO83PB5F5 T4 IO27PB1F1 D12 IO56PB3F3 R16 IO85NB5F5 R3 IO58NB3F3 N15 IO85PB5F5 R4 Bank 2 Bank 3 Bank 5 IO29NB2F2 F13 IO58PB3F3 M15 IO88NB5F5 R1 IO29PB2F2 E13 IO59NB3F3 M13 IO88PB5F5 T2 IO30NB2F2 F14 IO59PB3F3 L13 IO89NB5F5 N4 IO30PB2F2 E14 IO61NB3F3 M14 IO89PB5F5 N5 R ev i si o n 1 8 3- 13 Package Pin Assignments FG256 AX250 Function FG256 Pin Number Bank 6 AX250 Function Pin Number AX250 Function Pin Number IO117NB7F7 C2 GND M12 IO91NB6F6 L4 IO117PB7F7 B1 GND M5 IO91PB6F6 M4 IO118NB7F7 D2 GND P13 IO92NB6F6 L3 IO118PB7F7 D3 GND P3 IO92PB6F6 M3 IO119NB7F7 E3 GND R15 IO94NB6F6 P2 IO119PB7F7 F3 GND R2 IO94PB6F6 N2 GND T1 IO97NB6F6 J4 VCCDA E4 GND T16 IO97PB6F6 K4 GND A1 GND/LP D4 IO98NB6F6 N1 GND A16 PRA D8 IO98PB6F6 P1 GND B15 PRB C8 IO100NB6F6 L2 GND B2 PRC N9 IO100PB6F6 M2 GND D15 PRD P9 IO102NB6F6 L1 GND E12 TCK D5 IO102PB6F6 M1 GND E5 TDI C6 IO103NB6F6 J3 GND F11 TDO C4 IO103PB6F6 K3 GND F6 TMS C3 IO104NB6F6 J2 GND G10 TRST C5 IO104PB6F6 K2 GND G7 VCCA D14 GND G8 VCCA F10 Bank 7 3- 14 FG256 Dedicated I/O IO107NB7F7 J1 GND G9 VCCA F4 IO107PB7F7 K1 GND H10 VCCA F7 IO108NB7F7 G2 GND H7 VCCA F8 IO108PB7F7 H2 GND H8 VCCA F9 IO111NB7F7 G3 GND H9 VCCA G11 IO111PB7F7 H3 GND J10 VCCA G6 IO112NB7F7 E1 GND J7 VCCA H11 IO112PB7F7 F1 GND J8 VCCA H6 IO113NB7F7 G1 GND J9 VCCA J11 IO114NB7F7 E2 GND K10 VCCA J6 IO114PB7F7 F2 GND K7 VCCA K11 IO115NB7F7 G4 GND K8 VCCA K6 IO115PB7F7 H4 GND K9 VCCA L10 IO116NB7F7 C1 GND L11 VCCA L7 IO116PB7F7 D1 GND L6 VCCA L8 R ev i sio n 1 8 Axcelerator Family FPGAs FG256 FG256 AX250 Function Pin Number AX250 Function Pin Number VCCA L9 VCCIB4 M11 VCCA N3 VCCIB4 M9 VCCA P14 VCCIB5 M6 VCCPLA C7 VCCIB5 M7 VCCPLB D6 VCCIB5 M8 VCCPLC A10 VCCIB6 J5 VCCPLD D10 VCCIB6 K5 VCCPLE P10 VCCIB6 L5 VCCPLF N11 VCCIB7 F5 VCCPLG T7 VCCIB7 G5 VCCPLH N7 VCCIB7 H5 VCCDA A11 VCOMPLA A7 VCCDA A2 VCOMPLB D7 VCCDA C13 VCOMPLC B9 VCCDA D9 VCOMPLD D11 VCCDA H1 VCOMPLE T10 VCCDA J15 VCOMPLF N10 VCCDA N14 VCOMPLG R8 VCCDA N8 VCOMPLH N6 VCCDA P4 VPUMP A14 VCCDA R11 VCCDA R5 VCCIB0 E6 VCCIB0 E7 VCCIB0 E8 VCCIB1 E10 VCCIB1 E11 VCCIB1 E9 VCCIB2 F12 VCCIB2 G12 VCCIB2 H12 VCCIB3 J12 VCCIB3 K12 VCCIB3 L12 VCCIB4 M10 R ev i si o n 1 8 3- 15 Package Pin Assignments FG324 A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. 3- 16 R ev i sio n 1 8 Axcelerator Family FPGAs FG324 AX125 Function FG324 Pin Number Bank 0 AX125 Function FG324 Pin Number AX125 Function Pin Number IO16PB1F1 C15 IO33NB3F3 R18 IO00NB0F0 C5 IO17NB1F1 E14 IO33PB3F3 P18 IO00PB0F0 C4 IO17PB1F1 E13 IO34NB3F3 N15 IO01NB0F0 A3 IO34PB3F3 M15 IO01PB0F0 A2 IO18NB2F2 G14 IO35NB3F3 M16 IO02NB0F0 C7 IO18PB2F2 F14 IO35PB3F3 M17 IO02PB0F0 C6 IO19NB2F2 D16 IO36NB3F3 P16 IO03NB0F0 B5 IO19PB2F2 D15 IO36PB3F3 N16 IO03PB0F0 B4 IO20NB2F2 C18 IO37NB3F3 R17 IO04NB0F0 A5 IO20PB2F2 B18 IO37PB3F3 P17 IO04PB0F0 A4 IO21NB2F2 D17 IO38NB3F3 N14 IO05NB0F0 A7 IO21PB2F2 C17 IO38PB3F3 M14 IO05PB0F0 A6 IO22NB2F2 F17 IO39NB3F3 U18 IO06NB0F0 B7 IO22PB2F2 E17 IO39PB3F3 T18 IO06PB0F0 B6 IO23NB2F2 G16 IO40NB3F3 R16 IO07NB0F0/HCLKAN C9 IO23PB2F2 F16 IO40PB3F3 T17 IO07PB0F0/HCLKAP C8 IO24NB2F2 E18 IO41NB3F3 P13 IO08NB0F0/HCLKBN B10 IO24PB2F2 D18 IO41PB3F3 P14 IO08PB0F0/HCLKBP B9 IO25NB2F2 G18 IO25PB2F2 F18 IO42NB4F4 T13 Bank 1 Bank 2 Bank 4 IO09NB1F1/HCLKCN D11 IO26NB2F2 H17 IO42PB4F4 T14 IO09PB1F1/HCLKCP D10 IO26PB2F2 G17 IO43NB4F4 U15 IO10NB1F1/HCLKDN C12 IO27NB2F2 J16 IO43PB4F4 T15 IO10PB1F1/HCLKDP C11 IO27PB2F2 H16 IO44NB4F4 U13 IO11NB1F1 A15 IO28NB2F2 J18 IO44PB4F4 U14 IO11PB1F1 A14 IO28PB2F2 H18 IO45NB4F4 V15 IO12NB1F1 B14 IO29NB2F2 K17 IO45PB4F4 V16 IO12PB1F1 B13 IO29PB2F2 J17 IO46NB4F4 V13 IO13NB1F1 A17 IO46PB4F4 V14 IO13PB1F1 A16 IO30NB3F3 N18 IO47NB4F4 V12 IO14NB1F1 D13 IO30PB3F3 M18 IO47PB4F4 U12 IO14PB1F1 D12 IO31NB3F3 L18 IO48NB4F4 V10 IO15NB1F1 C14 IO31PB3F3 K18 IO48PB4F4 V11 IO15PB1F1 C13 IO32NB3F3 L16 IO49NB4F4/CLKEN T10 IO16NB1F1 B16 IO32PB3F3 L17 IO49PB4F4/CLKEP T11 Bank 3 R ev i si o n 1 8 3- 17 Package Pin Assignments FG324 AX125 Function FG324 Pin Number AX125 Function FG324 Pin Number AX125 Function IO50NB4F4/CLKFN U9 IO66PB6F6 N3 IO50PB4F4/CLKFP U10 IO67NB6F6 M2 IO67PB6F6 N2 VCCDA F5 Bank 5 IO83PB7F7 Pin Number C1 Dedicated I/O IO51NB5F5/CLKGN R8 IO68NB6F6 M1 GND A1 IO51PB5F5/CLKGP R9 IO68PB6F6 N1 GND A18 IO52NB5F5/CLKHN T7 IO69NB6F6 K4 GND B17 IO52PB5F5/CLKHP T8 IO69PB6F6 L4 GND B2 IO53NB5F5 U6 IO70NB6F6 K1 GND C16 IO53PB5F5 U7 IO70PB6F6 L1 GND C3 IO54NB5F5 V8 IO71NB6F6 K3 GND E16 IO54PB5F5 V9 IO71PB6F6 L3 GND F13 IO55NB5F5 V6 GND F6 IO55PB5F5 V7 IO72NB7F7 H4 GND G12 IO56NB5F5 U4 IO72PB7F7 J4 GND G7 IO56PB5F5 U5 IO73NB7F7 K2 GND H10 IO57NB5F5 T4 IO73PB7F7 L2 GND H11 IO57PB5F5 T5 IO74NB7F7 H2 GND H8 IO58NB5F5 V4 IO74PB7F7 H1 GND H9 IO58PB5F5 V5 IO75NB7F7 H3 GND J10 IO59NB5F5 V2 IO75PB7F7 J3 GND J11 IO59PB5F5 V3 IO76NB7F7 F2 GND J8 IO76PB7F7 G2 GND J9 Bank 6 3- 18 Bank 7 IO60NB6F6 P5 IO77NB7F7 F1 GND K10 IO60PB6F6 P6 IO77PB7F7 G1 GND K11 IO61NB6F6 T2 IO78NB7F7 D2 GND K8 IO61PB6F6 U3 IO78PB7F7 E2 GND K9 IO62NB6F6 T1 IO79NB7F7 F3 GND L10 IO62PB6F6 U1 IO79PB7F7 G3 GND L11 IO63NB6F6 P1 IO80NB7F7 E3 GND L8 IO63PB6F6 R1 IO80PB7F7 E4 GND L9 IO64NB6F6 R3 IO81NB7F7 D1 GND M12 IO64PB6F6 P3 IO81PB7F7 E1 GND M7 IO65NB6F6 P2 IO82NB7F7 D3 GND N13 IO65PB6F6 R2 IO82PB7F7 C2 GND N6 IO66NB6F6 M3 IO83NB7F7 B1 GND R14 R ev i sio n 1 8 Axcelerator Family FPGAs FG324 AX125 Function FG324 Pin Number AX125 Function FG324 Pin Number AX125 Function Pin Number GND R4 NC N4 VCCA M8 GND T16 NC N5 VCCA M9 GND T3 NC R12 VCCA P4 GND U17 NC R13 VCCA R15 GND U2 NC R6 VCCPLA D8 GND V1 NC R7 VCCPLB E7 GND V18 NC T12 VCCPLC B11 GND/LP E5 NC T6 VCCPLD E11 NC A10 NC U16 VCCPLE R11 NC A11 NC V17 VCCPLF P12 NC A12 PRA E9 VCCPLG U8 NC A13 PRB D9 VCCPLH P8 NC A8 PRC P10 VCCDA B3 NC A9 PRD R10 VCCDA D14 NC B12 TCK E6 VCCDA E10 NC F15 TDI D7 VCCDA J2 NC F4 TDO D5 VCCDA K16 NC G15 TMS D4 VCCDA P15 NC G4 TRST D6 VCCDA P9 NC H14 VCCA E15 VCCDA R5 NC H15 VCCA G10 VCCIB0 F7 NC H5 VCCA G11 VCCIB0 F8 NC J1 VCCA G5 VCCIB0 F9 NC J14 VCCA G8 VCCIB1 F10 NC J15 VCCA G9 VCCIB1 F11 NC J5 VCCA H12 VCCIB1 F12 NC K14 VCCA H7 VCCIB2 G13 NC K15 VCCA J12 VCCIB2 H13 NC K5 VCCA J7 VCCIB2 J13 NC L14 VCCA K12 VCCIB3 K13 NC L15 VCCA K7 VCCIB3 L13 NC L5 VCCA L12 VCCIB3 M13 NC M4 VCCA L7 VCCIB4 N10 NC M5 VCCA M10 VCCIB4 N11 NC N17 VCCA M11 VCCIB4 N12 R ev i si o n 1 8 3- 19 Package Pin Assignments FG324 AX125 Function 3- 20 Pin Number VCCIB5 N7 VCCIB5 N8 VCCIB5 N9 VCCIB6 K6 VCCIB6 L6 VCCIB6 M6 VCCIB7 G6 VCCIB7 H6 VCCIB7 J6 VCOMPLA B8 VCOMPLB E8 VCOMPLC C10 VCOMPLD E12 VCOMPLE U11 VCOMPLF P11 VCOMPLG T9 VCOMPLH P7 VPUMP B15 R ev i sio n 1 8 Axcelerator Family FPGAs FG484 A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3- 21 Package Pin Assignments FG484 AX250 Function FG484 Pin Number Bank 0 AX250 Function FG484 Pin Number AX250 Function Pin Number IO17NB1F1 B14 IO34PB2F2 D22 IO00NB0F0 D7 IO17PB1F1 B13 IO35NB2F2 J18 IO00PB0F0 D6 IO18NB1F1 A14 IO35PB2F2 H18 IO01NB0F0 E7 IO18PB1F1 A13 IO36NB2F2 G21 IO01PB0F0 E6 IO19NB1F1 A16 IO36PB2F2 F21 IO02NB0F0 C5 IO19PB1F1 A15 IO37NB2F2 K19 IO02PB0F0 C4 IO20NB1F1 B16 IO37PB2F2 J19 IO03NB0F0 C7 IO20PB1F1 B15 IO38NB2F2 J20 IO03PB0F0 C6 IO21NB1F1 C17 IO38PB2F2 H20 IO04NB0F0 E9 IO21PB1F1 C16 IO39NB2F2 L16 IO04PB0F0 E8 IO22NB1F1 F15 IO39PB2F2 K16 IO05NB0F0 D9 IO22PB1F1 F14 IO40NB2F2 J21 IO05PB0F0 D8 IO23NB1F1 D16 IO40PB2F2 H21 IO06NB0F0 B7 IO23PB1F1 D15 IO41NB2F2 L17 IO06PB0F0 B6 IO24NB1F1 E16 IO41PB2F2 K17 IO07NB0F0 C9 IO24PB1F1 E15 IO42NB2F2 J22 IO07PB0F0 C8 IO25NB1F1 F18 IO42PB2F2 H22 IO08NB0F0 A7 IO25PB1F1 F17 IO43NB2F2 L18 IO08PB0F0 A6 IO26NB1F1 D18 IO43PB2F2 K18 IO09NB0F0 B9 IO26PB1F1 E17 IO44NB2F2 L20 IO09PB0F0 B8 IO27NB1F1 G16 IO44PB2F2 K20 IO10NB0F0 A9 IO27PB1F1 G15 IO10PB0F0 A8 IO11NB0F0 B10 IO28NB2F2 IO11PB0F0 A10 IO12NB0F0/HCLKAN Bank 3 IO45NB3F3 M19 F19 IO45PB3F3 L19 IO28PB2F2 E19 IO46NB3F3 M21 E11 IO29NB2F2 J16 IO46PB3F3 L21 IO12PB0F0/HCLKAP E10 IO29PB2F2 H16 IO47NB3F3 N17 IO13NB0F0/HCLKBN D12 IO30NB2F2 E20 IO47PB3F3 M17 IO13PB0F0/HCLKBP D11 IO30PB2F2 D20 IO48NB3F3 N18 IO31NB2F2 J17 IO48PB3F3 N19 Bank 1 Bank 2 IO14NB1F1/HCLKCN F13 IO31PB2F2 H17 IO49NB3F3 N16 IO14PB1F1/HCLKCP F12 IO32NB2F2 G20 IO49PB3F3 M16 IO15NB1F1/HCLKDN E14 IO32PB2F2 F20 IO50NB3F3 N20 IO15PB1F1/HCLKDP E13 IO33NB2F2 H19 IO50PB3F3 M20 IO16NB1F1 C13 IO33PB2F2 G19 IO51NB3F3 P21 IO16PB1F1 C12 IO34NB2F2 E22 IO51PB3F3 N21 3- 22 R ev i sio n 1 8 Axcelerator Family FPGAs FG484 AX250 Function FG484 Pin Number AX250 Function FG484 Pin Number AX250 Function Pin Number IO52NB3F3 P18 IO69PB4F4 AA17 IO87NB5F5 Y4 IO52PB3F3 P19 IO70NB4F4 AB14 IO87PB5F5 Y5 IO53NB3F3 R20 IO70PB4F4 AB15 IO88NB5F5 V6 IO53PB3F3 P20 IO71NB4F4 Y14 IO88PB5F5 V7 IO54NB3F3 T21 IO71PB4F4 W14 IO89NB5F5 T7 IO54PB3F3 R21 IO72NB4F4 AA14 IO89PB5F5 T8 IO55NB3F3 R17 IO72PB4F4 AA15 IO55PB3F3 P17 IO73NB4F4 AA13 IO90NB6F6 V4 IO56NB3F3 U20 IO73PB4F4 AB13 IO90PB6F6 W5 IO56PB3F3 T20 IO74NB4F4/CLKEN V12 IO91NB6F6 P7 IO57NB3F3 T18 IO74PB4F4/CLKEP V13 IO91PB6F6 R7 IO57PB3F3 R18 IO75NB4F4/CLKFN W11 IO92NB6F6 U5 IO58NB3F3 U19 IO75PB4F4/CLKFP W12 IO92PB6F6 T5 IO58PB3F3 T19 Bank 5 IO93NB6F6 P6 IO59NB3F3 R16 IO76NB5F5/CLKGN U10 IO93PB6F6 R6 IO59PB3F3 P16 IO76PB5F5/CLKGP U11 IO94NB6F6 T4 IO60NB3F3 W20 IO77NB5F5/CLKHN V9 IO94PB6F6 U4 IO60PB3F3 V20 IO77PB5F5/CLKHP V10 IO95NB6F6 P5 IO61NB3F3 U18 IO78NB5F5 AA9 IO95PB6F6 R5 IO61PB3F3 V19 IO78PB5F5 AA10 IO96NB6F6 T3 IO79NB5F5 AB9 IO96PB6F6 U3 Bank 4 Bank 6 IO62NB4F4 T15 IO79PB5F5 AB10 IO97NB6F6 P3 IO62PB4F4 T16 IO80NB5F5 AA7 IO97PB6F6 R3 IO63NB4F4 W17 IO80PB5F5 AA8 IO98NB6F6 R2 IO63PB4F4 V17 IO81NB5F5 W8 IO98PB6F6 T2 IO64NB4F4 V15 IO81PB5F5 W9 IO99NB6F6 P4 IO64PB4F4 V16 IO82NB5F5 AB5 IO99PB6F6 R4 IO65NB4F4 Y19 IO82PB5F5 AB6 IO100NB6F6 P1 IO65PB4F4 W18 IO83NB5F5 AA5 IO100PB6F6 R1 IO66NB4F4 AB18 IO83PB5F5 AA6 IO101NB6F6 M7 IO66PB4F4 AB19 IO84NB5F5 U8 IO101PB6F6 N7 IO67NB4F4 W15 IO84PB5F5 U9 IO102NB6F6 N2 IO67PB4F4 W16 IO85NB5F5 Y6 IO102PB6F6 P2 IO68NB4F4 U14 IO85PB5F5 Y7 IO103NB6F6 M6 IO68PB4F4 U15 IO86NB5F5 W6 IO103PB6F6 N6 IO69NB4F4 AA16 IO86PB5F5 W7 IO104NB6F6 M4 R ev i si o n 1 8 3- 23 Package Pin Assignments FG484 AX250 Function FG484 Pin Number Pin Number AX250 Function Pin Number IO104PB6F6 N4 IO122NB7F7 G5 GND J9 IO105NB6F6 M5 IO122PB7F7 G6 GND K10 IO105PB6F6 N5 IO123NB7F7 F5 GND K11 IO106NB6F6 M3 IO123PB7F7 E4 GND K12 IO106PB6F6 N3 GND K13 Bank 7 3- 24 AX250 Function FG484 Dedicated I/O VCCDA H7 GND L1 IO107NB7F7 M2 GND A1 GND L10 IO107PB7F7 N1 GND A11 GND L11 IO108NB7F7 L3 GND A12 GND L12 IO108PB7F7 L2 GND A2 GND L13 IO109NB7F7 K2 GND A21 GND L22 IO109PB7F7 K1 GND A22 GND M1 IO110NB7F7 K5 GND AA1 GND M10 IO110PB7F7 L5 GND AA2 GND M11 IO111NB7F7 K6 GND AA21 GND M12 IO111PB7F7 L6 GND AA22 GND M13 IO112NB7F7 K4 GND AB1 GND M22 IO112PB7F7 K3 GND AB11 GND N10 IO113NB7F7 K7 GND AB12 GND N11 IO113PB7F7 L7 GND AB2 GND N12 IO114NB7F7 H1 GND AB21 GND N13 IO114PB7F7 J1 GND AB22 GND P14 IO115NB7F7 H2 GND B1 GND P9 IO115PB7F7 J2 GND B2 GND R15 IO116NB7F7 H4 GND B21 GND R8 IO116PB7F7 J4 GND B22 GND U16 IO117NB7F7 H5 GND C20 GND U6 IO117PB7F7 J5 GND C3 GND V18 IO118NB7F7 F2 GND D19 GND V5 IO118PB7F7 G2 GND D4 GND W19 IO119NB7F7 H6 GND E18 GND W4 IO119PB7F7 J6 GND E5 GND Y20 IO120NB7F7 F1 GND G18 GND Y3 IO120PB7F7 G1 GND H15 GND/LP G7 IO121NB7F7 F4 GND H8 NC A17 IO121PB7F7 G4 GND J14 NC A18 R ev i sio n 1 8 Axcelerator Family FPGAs FG484 AX250 Function FG484 Pin Number AX250 Function FG484 Pin Number AX250 Function Pin Number NC A19 NC G22 PRA G11 NC A4 NC G3 PRB F11 NC A5 NC H3 PRC T12 NC AA11 NC J3 PRD U12 NC AA12 NC K21 TCK G8 NC AA18 NC K22 TDI F9 NC AA19 NC N22 TDO F7 NC AA4 NC P22 TMS F6 NC AB16 NC R19 TRST F8 NC AB17 NC R22 VCCA G17 NC AB4 NC T1 VCCA J10 NC AB7 NC T22 VCCA J11 NC AB8 NC U1 VCCA J12 NC B11 NC U2 VCCA J13 NC B12 NC U21 VCCA J7 NC B17 NC U22 VCCA K14 NC B18 NC V1 VCCA K9 NC B19 NC V2 VCCA L14 NC B4 NC V21 VCCA L9 NC B5 NC V22 VCCA M14 NC C10 NC V3 VCCA M9 NC C11 NC W1 VCCA N14 NC C14 NC W2 VCCA N9 NC C15 NC W21 VCCA P10 NC C18 NC W22 VCCA P11 NC C19 NC W3 VCCA P12 NC D1 NC Y10 VCCA P13 NC D2 NC Y11 VCCA T6 NC D21 NC Y12 VCCA U17 NC D3 NC Y13 VCCPLA F10 NC E1 NC Y15 VCCPLB G9 NC E2 NC Y16 VCCPLC D13 NC E21 NC Y17 VCCPLD G13 NC E3 NC Y18 VCCPLE U13 NC F22 NC Y8 VCCPLF T14 NC F3 NC Y9 VCCPLG W10 R ev i si o n 1 8 3- 25 Package Pin Assignments FG484 FG484 AX250 Function 3- 26 Pin Number AX250 Function Pin Number VCCPLH T10 VCCIB4 R14 VCCDA D14 VCCIB5 AA3 VCCDA D5 VCCIB5 AB3 VCCDA F16 VCCIB5 R10 VCCDA G12 VCCIB5 R11 VCCDA L4 VCCIB5 R9 VCCDA M18 VCCIB6 M8 VCCDA T11 VCCIB6 N8 VCCDA T17 VCCIB6 P8 VCCDA U7 VCCIB6 Y1 VCCDA V14 VCCIB6 Y2 VCCDA V8 VCCIB7 C1 VCCIB0 A3 VCCIB7 C2 VCCIB0 B3 VCCIB7 J8 VCCIB0 H10 VCCIB7 K8 VCCIB0 H11 VCCIB7 L8 VCCIB0 H9 VCOMPLA D10 VCCIB1 A20 VCOMPLB G10 VCCIB1 B20 VCOMPLC E12 VCCIB1 H12 VCOMPLD G14 VCCIB1 H13 VCOMPLE W13 VCCIB1 H14 VCOMPLF T13 VCCIB2 C21 VCOMPLG V11 VCCIB2 C22 VCOMPLH T9 VCCIB2 J15 VPUMP D17 VCCIB2 K15 VCCIB2 L15 VCCIB3 M15 VCCIB3 N15 VCCIB3 P15 VCCIB3 Y21 VCCIB3 Y22 VCCIB4 AA20 VCCIB4 AB20 VCCIB4 R12 VCCIB4 R13 R ev i sio n 1 8 Axcelerator Family FPGAs FG484 AX500 Function FG484 Pin Number Bank 0 FG484 AX500 Function Pin Number AX500 Function Pin Number IO19NB0F1/HCLKAN E11 IO37PB1F3 F17 IO00NB0F0 E3 IO19PB0F1/HCLKAP E10 IO38NB1F3 D18 IO00PB0F0 D3 IO20NB0F1/HCLKBN D12 IO38PB1F3 E17 IO01NB0F0 E7 IO20PB0F1/HCLKBP D11 IO39NB1F3 E21 IO01PB0F0 E6 Bank 1 IO39PB1F3 D21 IO02NB0F0 C5 IO21NB1F2/HCLKCN F13 IO40NB1F3 E20 IO02PB0F0 C4 IO21PB1F2/HCLKCP F12 IO40PB1F3 D20 IO03NB0F0 D7 IO22NB1F2/HCLKDN E14 IO41NB1F3 G16 IO03PB0F0 D6 IO22PB1F2/HCLKDP E13 IO41PB1F3 G15 IO04NB0F0 B5 IO24NB1F2 A14 IO04PB0F0 B4 IO24PB1F2 A13 IO42NB2F4 F19 IO05NB0F0 C7 IO25NB1F2 B14 IO42PB2F4 E19 IO05PB0F0 C6 IO25PB1F2 B13 IO43NB2F4 J16 IO06NB0F0 A5 IO26NB1F2 C15 IO43PB2F4 H16 IO06PB0F0 A4 IO27NB1F2 A16 IO44NB2F4 E22 IO07NB0F0 A7 IO27PB1F2 A15 IO44PB2F4 D22 IO07PB0F0 A6 IO28NB1F2 B16 IO45NB2F4 H19 IO08NB0F0 B7 IO28PB1F2 B15 IO45PB2F4 G19 IO08PB0F0 B6 IO29NB1F2 D16 IO46NB2F4 G22 IO10NB0F0 B9 IO29PB1F2 D15 IO46PB2F4 F22 IO10PB0F0 B8 IO30NB1F2 A18 IO47NB2F4 J17 IO11NB0F0 E9 IO30PB1F2 A17 IO47PB2F4 H17 IO11PB0F0 E8 IO31NB1F2 F15 IO48NB2F4 G20 IO12NB0F1 D9 IO31PB1F2 F14 IO48PB2F4 F20 IO12PB0F1 D8 IO32NB1F3 C17 IO49NB2F4 J18 IO13NB0F1 C9 IO32PB1F3 C16 IO49PB2F4 H18 IO13PB0F1 C8 IO33NB1F3 E16 IO50NB2F4 G21 IO14NB0F1 A9 IO33PB1F3 E15 IO50PB2F4 F21 IO14PB0F1 A8 IO34NB1F3 B18 IO51NB2F4 K19 IO15NB0F1 B10 IO34PB1F3 B17 IO51PB2F4 J19 IO15PB0F1 A10 IO35NB1F3 B19 IO52NB2F5 J21 IO16NB0F1 B12 IO35PB1F3 A19 IO52PB2F5 H21 IO16PB0F1 B11 IO36NB1F3 C19 IO53NB2F5 J20 IO18NB0F1 C13 IO36PB1F3 C18 IO53PB2F5 H20 IO18PB0F1 C12 IO37NB1F3 F18 IO54NB2F5 J22 R ev i si o n 1 8 Bank 2 3- 27 Package Pin Assignments FG484 FG484 FG484 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO54PB2F5 H22 IO72PB3F6 P20 IO90NB4F8 Y17 IO55NB2F5 L17 IO73PB3F6 R19 IO90PB4F8 Y18 IO55PB2F5 K17 IO74NB3F7 V21 IO91NB4F8 V15 IO56NB2F5 K21 IO74PB3F7 U21 IO91PB4F8 V16 IO56PB2F5 K22 IO75NB3F7 V22 IO92PB4F8 AB17 IO58NB2F5 L20 IO75PB3F7 U22 IO93NB4F8 Y15 IO58PB2F5 K20 IO76NB3F7 U20 IO93PB4F8 Y16 IO59NB2F5 L18 IO76PB3F7 T20 IO94NB4F9 AA16 IO59PB2F5 K18 IO77NB3F7 R17 IO94PB4F9 AA17 IO60NB2F5 M21 IO77PB3F7 P17 IO95NB4F9 AB14 IO60PB2F5 L21 IO78NB3F7 W21 IO95PB4F9 AB15 IO61NB2F5 L16 IO78PB3F7 W22 IO96NB4F9 W15 IO61PB2F5 K16 IO79NB3F7 T18 IO96PB4F9 W16 IO62NB2F5 M19 IO79PB3F7 R18 IO97NB4F9 AA13 IO62PB2F5 L19 IO80NB3F7 W20 IO97PB4F9 AB13 IO80PB3F7 V20 IO98NB4F9 AA14 Bank 3 3- 28 IO63NB3F6 N16 IO81NB3F7 U19 IO98PB4F9 AA15 IO63PB3F6 M16 IO81PB3F7 T19 IO100NB4F9 Y14 IO64NB3F6 P22 IO82NB3F7 U18 IO100PB4F9 W14 IO64PB3F6 N22 IO82PB3F7 V19 IO101NB4F9 Y12 IO65NB3F6 N20 IO83NB3F7 R16 IO101PB4F9 Y13 IO65PB3F6 M20 IO83PB3F7 P16 IO102NB4F9 AA11 IO66NB3F6 P21 IO102PB4F9 AA12 IO66PB3F6 N21 IO84NB4F8 AB18 IO103NB4F9/CLKEN V12 IO67NB3F6 N18 IO84PB4F8 AB19 IO103PB4F9/CLKEP V13 IO67PB3F6 N19 IO85NB4F8 T15 IO104NB4F9/CLKFN W11 IO68NB3F6 T22 IO85PB4F8 T16 IO104PB4F9/CLKFP W12 IO68PB3F6 R22 IO86NB4F8 AA18 IO69NB3F6 N17 IO86PB4F8 AA19 IO105NB5F10/CLKGN U10 IO69PB3F6 M17 IO87NB4F8 W17 IO105PB5F10/CLKGP U11 IO70NB3F6 T21 IO87PB4F8 V17 IO106NB5F10/CLKHN V9 IO70PB3F6 R21 IO88NB4F8 Y19 IO106PB5F10/CLKHP V10 IO71NB3F6 P18 IO88PB4F8 W18 IO107NB5F10 Y10 IO71PB3F6 P19 IO89NB4F8 U14 IO107PB5F10 Y11 IO72NB3F6 R20 IO89PB4F8 U15 IO108NB5F10 AA9 Bank 4 R ev i sio n 1 8 Bank 5 Axcelerator Family FPGAs FG484 FG484 FG484 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO108PB5F10 AA10 IO127NB6F12 P7 IO146NB6F13 M3 IO110NB5F10 AB9 IO127PB6F12 R7 IO146PB6F13 N3 IO110PB5F10 AB10 IO128NB6F12 V1 IO111NB5F10 Y8 IO128PB6F12 W1 IO147NB7F14 K7 IO111PB5F10 Y9 IO129NB6F12 U5 IO147PB7F14 L7 IO112NB5F10 AB7 IO129PB6F12 T5 IO148NB7F14 M2 IO113NB5F10 W8 IO130NB6F12 T1 IO148PB7F14 N1 IO113PB5F10 W9 IO130PB6F12 U1 IO149NB7F14 K5 IO114NB5F11 AA7 IO131NB6F12 P6 IO149PB7F14 L5 IO114PB5F11 AA8 IO131PB6F12 R6 IO150NB7F14 L3 IO115NB5F11 AB5 IO132NB6F12 T4 IO150PB7F14 L2 IO115PB5F11 AB6 IO132PB6F12 U4 IO151NB7F14 K6 IO116NB5F11 Y6 IO133NB6F12 U2 IO151PB7F14 L6 IO116PB5F11 Y7 IO134NB6F12 T3 IO152NB7F14 K2 IO117NB5F11 U8 IO134PB6F12 U3 IO152PB7F14 K1 IO117PB5F11 U9 IO135NB6F12 P5 IO153NB7F14 K4 IO118NB5F11 AA5 IO135PB6F12 R5 IO153PB7F14 K3 IO118PB5F11 AA6 IO136NB6F13 R2 IO154NB7F14 H3 IO119NB5F11 AA4 IO136PB6F13 T2 IO154PB7F14 J3 IO119PB5F11 AB4 IO138NB6F13 P4 IO155NB7F14 H5 IO120NB5F11 Y4 IO138PB6F13 R4 IO155PB7F14 J5 IO120PB5F11 Y5 IO139NB6F13 N2 IO156NB7F14 H4 IO121NB5F11 W6 IO139PB6F13 P2 IO156PB7F14 J4 IO121PB5F11 W7 IO140NB6F13 P3 IO157NB7F14 H2 IO122NB5F11 V3 IO140PB6F13 R3 IO157PB7F14 J2 IO122PB5F11 W3 IO141NB6F13 M6 IO158NB7F15 H1 IO123NB5F11 T7 IO141PB6F13 N6 IO158PB7F15 J1 IO123PB5F11 T8 IO142NB6F13 P1 IO159NB7F15 F1 IO124NB5F11 V4 IO142PB6F13 R1 IO159PB7F15 G1 IO124PB5F11 W5 IO143NB6F13 M5 IO160NB7F15 F2 IO125NB5F11 V6 IO143PB6F13 N5 IO160PB7F15 G2 IO125PB5F11 V7 IO144NB6F13 M4 IO161NB7F15 H6 IO144PB6F13 N4 IO161PB7F15 J6 Bank 6 Bank 7 IO126NB6F12 V2 IO145NB6F13 M7 IO162NB7F15 F3 IO126PB6F12 W2 IO145PB6F13 N7 IO162PB7F15 G3 R ev i si o n 1 8 3- 29 Package Pin Assignments FG484 FG484 FG484 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO163NB7F15 G5 GND D4 GND V5 IO163PB7F15 G6 GND E18 GND W19 IO164NB7F15 D1 GND E5 GND W4 IO164PB7F15 E1 GND G18 GND Y20 IO165NB7F15 F4 GND H15 GND Y3 IO165PB7F15 G4 GND H8 GND/LP G7 IO166NB7F15 D2 GND J14 NC AB8 IO166PB7F15 E2 GND J9 NC AB16 IO167NB7F15 F5 GND K10 NC C10 IO167PB7F15 E4 GND K11 NC C11 GND K12 NC C14 Dedicated I/O 3- 30 VCCDA H7 GND K13 PRA G11 GND A1 GND L1 PRB F11 GND A11 GND L10 PRC T12 GND A12 GND L11 PRD U12 GND A2 GND L12 TCK G8 GND A21 GND L13 TDI F9 GND A22 GND L22 TDO F7 GND AA1 GND M1 TMS F6 GND AA2 GND M10 TRST F8 GND AA21 GND M11 VCCA G17 GND AA22 GND M12 VCCA J10 GND AB1 GND M13 VCCA J11 GND AB11 GND M22 VCCA J12 GND AB12 GND N10 VCCA J13 GND AB2 GND N11 VCCA J7 GND AB21 GND N12 VCCA K14 GND AB22 GND N13 VCCA K9 GND B1 GND P14 VCCA L14 GND B2 GND P9 VCCA L9 GND B21 GND R15 VCCA M14 GND B22 GND R8 VCCA M9 GND C20 GND U16 VCCA N14 GND C3 GND U6 VCCA N9 GND D19 GND V18 VCCA P10 R ev i sio n 1 8 Axcelerator Family FPGAs FG484 FG484 FG484 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number VCCA P11 VCCIB2 C22 VCOMPLG V11 VCCA P12 VCCIB2 J15 VCOMPLH T9 VCCA P13 VCCIB2 K15 VPUMP D17 VCCA T6 VCCIB2 L15 VCCA U17 VCCIB3 M15 VCCPLA F10 VCCIB3 N15 VCCPLB G9 VCCIB3 P15 VCCPLC D13 VCCIB3 Y21 VCCPLD G13 VCCIB3 Y22 VCCPLE U13 VCCIB4 AA20 VCCPLF T14 VCCIB4 AB20 VCCPLG W10 VCCIB4 R12 VCCPLH T10 VCCIB4 R13 VCCDA D14 VCCIB4 R14 VCCDA D5 VCCIB5 AA3 VCCDA F16 VCCIB5 AB3 VCCDA G12 VCCIB5 R10 VCCDA L4 VCCIB5 R11 VCCDA M18 VCCIB5 R9 VCCDA T11 VCCIB6 M8 VCCDA T17 VCCIB6 N8 VCCDA U7 VCCIB6 P8 VCCDA V14 VCCIB6 Y1 VCCDA V8 VCCIB6 Y2 VCCIB0 A3 VCCIB7 C1 VCCIB0 B3 VCCIB7 C2 VCCIB0 H10 VCCIB7 J8 VCCIB0 H11 VCCIB7 K8 VCCIB0 H9 VCCIB7 L8 VCCIB1 A20 VCOMPLA D10 VCCIB1 B20 VCOMPLB G10 VCCIB1 H12 VCOMPLC E12 VCCIB1 H13 VCOMPLD G14 VCCIB1 H14 VCOMPLE W13 VCCIB2 C21 VCOMPLF T13 R ev i si o n 1 8 3- 31 Package Pin Assignments FG484 AX1000 Function FG484 Pin Number Bank 0 3- 32 FG484 AX1000 Function Pin Number AX1000 Function Pin Number IO29NB0F2 B12 IO51PB1F4 D22 IO01NB0F0 E3 IO29PB0F2 B11 IO52NB1F4 E16 IO01PB0F0 D3 IO30NB0F2/HCLKAN E11 IO52PB1F4 E15 IO02NB0F0 E7 IO30PB0F2/HCLKAP E10 IO57NB1F5 E21 IO02PB0F0 E6 IO31NB0F2/HCLKBN D12 IO57PB1F5 D21 IO05NB0F0 D2 IO31PB0F2/HCLKBP D11 IO60NB1F5 G16 IO05PB0F0 E2 Bank 1 IO60PB1F5 G15 IO06NB0F0 C5 IO32NB1F3/HCLKCN F13 IO61NB1F5 D18 IO06PB0F0 C4 IO32PB1F3/HCLKCP F12 IO61PB1F5 E17 IO12NB0F1 D7 IO33NB1F3/HCLKDN E14 IO63NB1F5 E20 IO12PB0F1 D6 IO33PB1F3/HCLKDP E13 IO63PB1F5 D20 IO13NB0F1 B5 IO34NB1F3 C13 IO13PB0F1 B4 IO34PB1F3 C12 IO64NB2F6 F18 IO14NB0F1 E9 IO37NB1F3 B14 IO64PB2F6 F17 IO14PB0F1 E8 IO37PB1F3 B13 IO67NB2F6 F19 IO15NB0F1 C7 IO38NB1F3 A16 IO67PB2F6 E19 IO15PB0F1 C6 IO38PB1F3 A15 IO68NB2F6 J16 IO16NB0F1 A5 IO40NB1F3 C15 IO68PB2F6 H16 IO16PB0F1 A4 IO42NB1F4 A18 IO70NB2F6 J17 IO17NB0F1 B7 IO42PB1F4 A17 IO70PB2F6 H17 IO17PB0F1 B6 IO43NB1F4 B16 IO74NB2F7 J18 IO18NB0F1 A7 IO43PB1F4 B15 IO74PB2F7 H18 IO18PB0F1 A6 IO44NB1F4 B18 IO75NB2F7 G20 IO19NB0F1 C9 IO44PB1F4 B17 IO75PB2F7 F20 IO19PB0F1 C8 IO45NB1F4 B19 IO79NB2F7 H19 IO20NB0F1 D9 IO45PB1F4 A19 IO79PB2F7 G19 IO20PB0F1 D8 IO46NB1F4 C19 IO80NB2F7 L16 IO21NB0F1 B9 IO46PB1F4 C18 IO80PB2F7 K16 IO21PB0F1 B8 IO48NB1F4 F15 IO84NB2F7 L17 IO22NB0F2 A9 IO48PB1F4 F14 IO84PB2F7 K17 IO22PB0F2 A8 IO49NB1F4 D16 IO85NB2F8 G21 IO23NB0F2 B10 IO49PB1F4 D15 IO85PB2F8 F21 IO23PB0F2 A10 IO50NB1F4 C17 IO86NB2F8 G22 IO26NB0F2 A14 IO50PB1F4 C16 IO86PB2F8 F22 IO26PB0F2 A13 IO51NB1F4 E22 IO87NB2F8 J20 R ev i sio n 1 8 Bank 2 Axcelerator Family FPGAs FG484 FG484 FG484 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO87PB2F8 H20 IO106PB3F9 P17 IO142PB4F13 V20 IO88NB2F8 L18 IO107NB3F10 T21 IO143NB4F13 W15 IO88PB2F8 K18 IO107PB3F10 R21 IO143PB4F13 W16 IO89NB2F8 K19 IO110NB3F10 V22 IO144NB4F13 AA18 IO89PB2F8 J19 IO110PB3F10 U22 IO144PB4F13 AA19 IO90NB2F8 J21 IO113NB3F10 V21 IO145NB4F13 U14 IO90PB2F8 H21 IO113PB3F10 U21 IO145PB4F13 U15 IO91NB2F8 J22 IO114NB3F10 P18 IO146NB4F13 Y15 IO91PB2F8 H22 IO114PB3F10 P19 IO146PB4F13 Y16 IO93NB2F8 K21 IO116PB3F10 R19 IO147NB4F13 AB18 IO93PB2F8 K22 IO117NB3F10 U20 IO147PB4F13 AB19 IO94NB2F8 L20 IO117PB3F10 T20 IO149NB4F13 Y14 IO94PB2F8 K20 IO118NB3F11 T18 IO149PB4F13 W14 IO95NB2F8 M21 IO118PB3F11 R18 IO150NB4F13 AA16 IO95PB2F8 L21 IO121NB3F11 U19 IO150PB4F13 AA17 IO121PB3F11 T19 IO152NB4F14 AA14 Bank 3 IO96NB3F9 N16 IO124NB3F11 R16 IO152PB4F14 AA15 IO96PB3F9 M16 IO124PB3F11 P16 IO154NB4F14 AB14 IO97NB3F9 M19 IO127NB3F11 W21 IO154PB4F14 AB15 IO97PB3F9 L19 IO127PB3F11 W22 IO155NB4F14 AA13 IO98NB3F9 P22 IO155PB4F14 AB13 IO98PB3F9 N22 IO129PB4F12 AB17 IO158NB4F14 Y12 IO99NB3F9 N20 IO132NB4F12 Y19 IO158PB4F14 Y13 IO99PB3F9 M20 IO132PB4F12 W18 IO159NB4F14/CLKEN V12 IO100NB3F9 N17 IO133NB4F12 W17 IO159PB4F14/CLKEP V13 IO100PB3F9 M17 IO133PB4F12 V17 IO160NB4F14/CLKFN W11 IO101NB3F9 P21 IO135NB4F12 T15 IO160PB4F14/CLKFP W12 IO101PB3F9 N21 IO135PB4F12 T16 IO103NB3F9 R20 IO138NB4F12 Y17 IO161NB5F15/CLKGN U10 IO103PB3F9 P20 IO138PB4F12 Y18 IO161PB5F15/CLKGP U11 IO104NB3F9 N18 IO139NB4F13 V15 IO162NB5F15/CLKHN V9 IO104PB3F9 N19 IO139PB4F13 V16 IO162PB5F15/CLKHP V10 IO105NB3F9 T22 IO140NB4F13 U18 IO163NB5F15 Y10 IO105PB3F9 R22 IO140PB4F13 V19 IO163PB5F15 Y11 IO106NB3F9 R17 IO142NB4F13 W20 IO167NB5F15 AA11 Bank 4 R ev i si o n 1 8 Bank 5 3- 33 Package Pin Assignments FG484 FG484 FG484 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO167PB5F15 AA12 IO194NB6F18 V2 IO223NB6F20 M7 IO169NB5F15 AA9 IO194PB6F18 W2 IO223PB6F20 N7 IO169PB5F15 AA10 IO195NB6F18 U5 IO224NB6F20 M4 IO170NB5F15 AB9 IO195PB6F18 T5 IO224PB6F20 N4 IO170PB5F15 AB10 IO200NB6F18 T4 IO171NB5F16 W8 IO200PB6F18 U4 IO225NB7F21 M2 IO171PB5F16 W9 IO201NB6F18 P6 IO225PB7F21 N1 IO172NB5F16 Y8 IO201PB6F18 R6 IO226NB7F21 K2 IO172PB5F16 Y9 IO203NB6F19 U2 IO226PB7F21 K1 IO173NB5F16 U8 IO204NB6F19 T3 IO228NB7F21 L3 IO173PB5F16 U9 IO204PB6F19 U3 IO228PB7F21 L2 IO174NB5F16 AA7 IO205NB6F19 P5 IO229NB7F21 K5 IO174PB5F16 AA8 IO205PB6F19 R5 IO229PB7F21 L5 IO175NB5F16 AB5 IO208NB6F19 V1 IO230NB7F21 H1 IO175PB5F16 AB6 IO208PB6F19 W1 IO230PB7F21 J1 IO176NB5F16 AA5 IO209NB6F19 P7 IO231NB7F21 H2 IO176PB5F16 AA6 IO209PB6F19 R7 IO231PB7F21 J2 IO177NB5F16 AA4 IO212NB6F19 P4 IO232NB7F21 K4 IO177PB5F16 AB4 IO212PB6F19 R4 IO232PB7F21 K3 IO178NB5F16 Y6 IO214NB6F20 P3 IO233NB7F21 K6 IO178PB5F16 Y7 IO214PB6F20 R3 IO233PB7F21 L6 IO179NB5F16 T7 IO215NB6F20 M6 IO234NB7F21 F1 IO179PB5F16 T8 IO215PB6F20 N6 IO234PB7F21 G1 IO180NB5F16 W6 IO216NB6F20 R2 IO235NB7F21 F2 IO180PB5F16 W7 IO216PB6F20 T2 IO235PB7F21 G2 IO181NB5F17 Y4 IO217NB6F20 T1 IO236NB7F22 H3 IO181PB5F17 Y5 IO217PB6F20 U1 IO236PB7F22 J3 IO184NB5F17 AB7 IO219NB6F20 M5 IO237NB7F22 K7 IO187NB5F17 V3 IO219PB6F20 N5 IO237PB7F22 L7 IO187PB5F17 W3 IO220NB6F20 P1 IO241NB7F22 H6 IO188NB5F17 V4 IO220PB6F20 R1 IO241PB7F22 J6 IO188PB5F17 W5 IO221NB6F20 N2 IO242NB7F22 H4 IO192NB5F17 V6 IO221PB6F20 P2 IO242PB7F22 J4 IO192PB5F17 V7 IO222NB6F20 M3 IO243NB7F22 H5 IO222PB6F20 N3 IO243PB7F22 J5 Bank 6 3- 34 R ev i sio n 1 8 Bank 7 Axcelerator Family FPGAs FG484 FG484 FG484 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO246NB7F22 F3 GND D4 GND V5 IO246PB7F22 G3 GND E18 GND W19 IO250NB7F23 F4 GND E5 GND W4 IO250PB7F23 G4 GND G18 GND Y20 IO253NB7F23 G5 GND H15 GND Y3 IO253PB7F23 G6 GND H8 GND/LP G7 IO254NB7F23 D1 GND J14 PRA G11 IO254PB7F23 E1 GND J9 PRB F11 IO257NB7F23 F5 GND K10 PRC T12 IO257PB7F23 E4 GND K11 PRD U12 GND K12 TCK G8 Dedicated I/O VCCDA H7 GND K13 TDI F9 GND A1 GND L1 TDO F7 GND A11 GND L10 TMS F6 GND A12 GND L11 TRST F8 GND A2 GND L12 VCCA G17 GND A21 GND L13 VCCA J10 GND A22 GND L22 VCCA J11 GND AA1 GND M1 VCCA J12 GND AA2 GND M10 VCCA J13 GND AA21 GND M11 VCCA J7 GND AA22 GND M12 VCCA K14 GND AB1 GND M13 VCCA K9 GND AB11 GND M22 VCCA L14 GND AB12 GND N10 VCCA L9 GND AB2 GND N11 VCCA M14 GND AB21 GND N12 VCCA M9 GND AB22 GND N13 VCCA N14 GND B1 GND P14 VCCA N9 GND B2 GND P9 VCCA P10 GND B21 GND R15 VCCA P11 GND B22 GND R8 VCCA P12 GND C20 GND U16 VCCA P13 GND C3 GND U6 VCCA T6 GND D19 GND V18 VCCA U17 R ev i si o n 1 8 3- 35 Package Pin Assignments FG484 FG484 FG484 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number VCCPLA F10 VCCIB2 C22 VCOMPLG V11 VCCPLB G9 VCCIB2 J15 VCOMPLH T9 VCCPLC D13 VCCIB2 K15 VPUMP D17 VCCPLD G13 VCCIB2 L15 VCCPLE U13 VCCIB3 M15 VCCPLF T14 VCCIB3 N15 VCCPLG W10 VCCIB3 P15 VCCPLH T10 VCCIB3 Y21 VCCDA AB16 VCCIB3 Y22 VCCDA AB8 VCCIB4 AA20 VCCDA C10 VCCIB4 AB20 VCCDA C11 VCCIB4 R12 VCCDA C14 VCCIB4 R13 VCCDA D14 VCCIB4 R14 VCCDA D5 VCCIB5 AA3 VCCDA F16 VCCIB5 AB3 VCCDA G12 VCCIB5 R10 VCCDA L4 VCCIB5 R11 VCCDA M18 VCCIB5 R9 VCCDA T11 VCCIB6 M8 VCCDA T17 VCCIB6 N8 VCCDA U7 VCCIB6 P8 VCCDA V14 VCCIB6 Y1 VCCDA V8 VCCIB6 Y2 VCCIB0 A3 VCCIB7 C1 VCCIB0 B3 VCCIB7 C2 VCCIB0 H10 VCCIB7 J8 VCCIB0 H11 VCCIB7 K8 VCCIB0 H9 VCCIB7 L8 VCCIB1 A20 VCOMPLA D10 VCCIB1 B20 VCOMPLB G10 VCCIB1 H12 VCOMPLC E12 VCCIB1 H13 VCOMPLD G14 VCCIB1 H14 VCOMPLE W13 VCCIB2 C21 VCOMPLF T13 3- 36 R ev i sio n 1 8 Axcelerator Family FPGAs FG676 A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3- 37 Package Pin Assignments FG676 AX500 Function FG676 Pin Number Bank 0 3- 38 FG676 AX500 Function Pin Number AX500 Function Pin Number IO17NB0F1 F12 IO34NB1F3 D20 IO00NB0F0 F8 IO17PB0F1 G12 IO34PB1F3 C20 IO00PB0F0 E8 IO18NB0F1 C12 IO35NB1F3 D21 IO01NB0F0 A5 IO18PB0F1 C11 IO35PB1F3 C21 IO01PB0F0 A4 IO19NB0F1/HCLKAN A12 IO36NB1F3 D22 IO02NB0F0 E7 IO19PB0F1/HCLKAP B12 IO36PB1F3 C22 IO02PB0F0 E6 IO20NB0F1/HCLKBN C13 IO37NB1F3 F19 IO03NB0F0 D6 IO20PB0F1/HCLKBP B13 IO37PB1F3 E19 IO03PB0F0 D5 Bank 1 IO38NB1F3 B23 IO04NB0F0 B5 IO21NB1F2/HCLKCN C15 IO38PB1F3 A23 IO04PB0F0 C5 IO21PB1F2/HCLKCP C14 IO39NB1F3 E21 IO05NB0F0 B6 IO22NB1F2/HCLKDN A15 IO39PB1F3 E20 IO05PB0F0 C6 IO22PB1F2/HCLKDP B15 IO40NB1F3 D23 IO06NB0F0 C7 IO23NB1F2 F15 IO40PB1F3 C23 IO06PB0F0 D7 IO23PB1F2 G15 IO41NB1F3 D25 IO07NB0F0 A7 IO24NB1F2 B16 IO41PB1F3 C25 IO07PB0F0 A6 IO24PB1F2 A16 IO08NB0F0 C8 IO25NB1F2 A18 IO42NB2F4 G24 IO08PB0F0 D8 IO25PB1F2 A17 IO42PB2F4 G23 IO09NB0F0 F10 IO26NB1F2 D16 IO43NB2F4 G26 IO09PB0F0 F9 IO26PB1F2 E16 IO43PB2F4 F26 IO10NB0F0 B8 IO27NB1F2 F16 IO44NB2F4 F25 IO10PB0F0 B7 IO27PB1F2 G16 IO44PB2F4 E25 IO11NB0F0 D10 IO28NB1F2 C18 IO45NB2F4 J21 IO11PB0F0 E10 IO28PB1F2 C17 IO45PB2F4 J22 IO12NB0F1 B9 IO29NB1F2 B19 IO46NB2F4 H25 IO12PB0F1 C9 IO29PB1F2 B18 IO46PB2F4 G25 IO13NB0F1 F11 IO30NB1F2 D19 IO47NB2F4 K23 IO13PB0F1 G11 IO30PB1F2 C19 IO47PB2F4 J23 IO14NB0F1 D11 IO31NB1F2 F17 IO48NB2F4 J24 IO14PB0F1 E11 IO31PB1F2 E17 IO48PB2F4 H24 IO15NB0F1 B10 IO32NB1F3 B20 IO49NB2F4 K21 IO15PB0F1 C10 IO32PB1F3 A20 IO49PB2F4 K22 IO16NB0F1 A10 IO33NB1F3 B22 IO50NB2F4 K25 IO16PB0F1 A9 IO33PB1F3 B21 IO50PB2F4 J25 R ev i sio n 1 8 Bank 2 Axcelerator Family FPGAs FG676 FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO51NB2F4 L20 IO68NB3F6 V26 IO85NB4F8 AE23 IO51PB2F4 L21 IO68PB3F6 U26 IO85PB4F8 AE24 IO52NB2F5 K26 IO69NB3F6 V25 IO86NB4F8 AC21 IO52PB2F5 J26 IO69PB3F6 U25 IO86PB4F8 AC22 IO53NB2F5 L23 IO70NB3F6 Y25 IO87NB4F8 AF22 IO53PB2F5 L22 IO70PB3F6 W25 IO87PB4F8 AF23 IO54NB2F5 L24 IO71NB3F6 W24 IO88NB4F8 AD22 IO54PB2F5 K24 IO71PB3F6 V24 IO88PB4F8 AD23 IO55NB2F5 M20 IO72NB3F6 V23 IO89NB4F8 AC19 IO55PB2F5 M21 IO72PB3F6 U23 IO89PB4F8 AC20 IO56NB2F5 L26 IO73NB3F6 T21 IO90NB4F8 AE21 IO56PB2F5 L25 IO73PB3F6 T20 IO90PB4F8 AE22 IO57NB2F5 M23 IO74NB3F7 AA26 IO91NB4F8 AA17 IO57PB2F5 M22 IO74PB3F7 Y26 IO91PB4F8 AA18 IO58NB2F5 M26 IO75NB3F7 AA24 IO92NB4F8 AD20 IO58PB2F5 M25 IO75PB3F7 Y24 IO92PB4F8 AD21 IO59NB2F5 N22 IO76NB3F7 Y23 IO93NB4F8 AF20 IO59PB2F5 N23 IO76PB3F7 W23 IO93PB4F8 AF21 IO60NB2F5 N24 IO77NB3F7 V21 IO94NB4F9 AE19 IO60PB2F5 M24 IO77PB3F7 U21 IO94PB4F9 AE20 IO61NB2F5 N20 IO78NB3F7 AB25 IO95NB4F9 AC17 IO61PB2F5 N21 IO78PB3F7 AA25 IO95PB4F9 AC18 IO62NB2F5 P25 IO79NB3F7 AC26 IO96NB4F9 AD18 IO62PB2F5 N25 IO79PB3F7 AB26 IO96PB4F9 AD19 IO80NB3F7 AC24 IO97NB4F9 AA16 Bank 3 IO63NB3F6 T26 IO80PB3F7 AB24 IO97PB4F9 Y16 IO63PB3F6 R26 IO81NB3F7 AB23 IO98NB4F9 AE17 IO64NB3F6 R24 IO81PB3F7 AA23 IO98PB4F9 AE18 IO64PB3F6 P24 IO82NB3F7 AA22 IO99NB4F9 AC16 IO65NB3F6 P20 IO82PB3F7 Y22 IO99PB4F9 AB16 IO65PB3F6 P21 IO83NB3F7 AE26 IO100NB4F9 AF17 IO66NB3F6 T25 IO83PB3F7 AD26 IO100PB4F9 AF18 IO66PB3F6 R25 IO101NB4F9 AA15 IO67NB3F6 T23 IO84NB4F8 AB21 IO101PB4F9 Y15 IO67PB3F6 R23 IO84PB4F8 AA21 IO102NB4F9 AC15 Bank 4 R ev i si o n 1 8 3- 39 Package Pin Assignments FG676 FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO102PB4F9 AB15 IO119PB5F11 AE6 IO136PB6F13 U5 IO103NB4F9/CLKEN AE16 IO120NB5F11 AE5 IO137NB6F13 T6 IO103PB4F9/CLKEP AF16 IO120PB5F11 AF5 IO137PB6F13 T7 IO104NB4F9/CLKFN AE14 IO121NB5F11 AF4 IO138NB6F13 T5 IO104PB4F9/CLKFP AE15 IO121PB5F11 AE4 IO138PB6F13 T4 IO122NB5F11 AC5 IO139NB6F13 R6 Bank 5 IO105NB5F10/CLKGN AE12 IO122PB5F11 AC6 IO139PB6F13 R7 IO105PB5F10/CLKGP AE13 IO123NB5F11 AD4 IO140NB6F13 T3 IO106NB5F10/CLKHN AE11 IO123PB5F11 AD5 IO140PB6F13 U3 IO106PB5F10/CLKHP AF11 IO124NB5F11 AB6 IO141NB6F13 U1 IO107NB5F10 Y12 IO124PB5F11 AB7 IO141PB6F13 U2 IO107PB5F10 AA13 IO125NB5F11 AE3 IO142NB6F13 R2 IO108NB5F10 AC12 IO125PB5F11 AF3 IO142PB6F13 T2 IO108PB5F10 AB12 IO143NB6F13 P3 IO109NB5F10 AC10 IO126NB6F12 AB3 IO143PB6F13 R3 IO109PB5F10 AC11 IO126PB6F12 AC3 IO144NB6F13 P5 IO110NB5F10 AF9 IO127NB6F12 AA2 IO144PB6F13 P4 IO110PB5F10 AF10 IO127PB6F12 AB2 IO145NB6F13 P6 IO111NB5F10 Y11 IO128NB6F12 AC2 IO145PB6F13 P7 IO111PB5F10 AA12 IO128PB6F12 AD2 IO146NB6F13 R1 IO112NB5F10 AE9 IO129NB6F12 Y1 IO146PB6F13 T1 IO112PB5F10 AE10 IO129PB6F12 AA1 IO113NB5F10 AC9 IO130NB6F12 Y3 IO147NB7F14 N6 IO113PB5F10 AD9 IO130PB6F12 AA3 IO147PB7F14 N7 IO114NB5F11 AF6 IO131NB6F12 U6 IO148NB7F14 N5 IO114PB5F11 AF7 IO131PB6F12 V6 IO148PB7F14 N4 IO115NB5F11 AA10 IO132NB6F12 W2 IO149NB7F14 N2 IO115PB5F11 AB10 IO132PB6F12 Y2 IO149PB7F14 N3 IO116NB5F11 AE7 IO133NB6F12 V4 IO150NB7F14 L1 IO116PB5F11 AE8 IO133PB6F12 W4 IO150PB7F14 M1 IO117NB5F11 AD7 IO134NB6F12 V3 IO151NB7F14 M2 IO117PB5F11 AD8 IO134PB6F12 W3 IO151PB7F14 M3 IO118NB5F11 AC7 IO135NB6F12 V1 IO152NB7F14 M5 IO118PB5F11 AC8 IO135PB6F12 V2 IO152PB7F14 M4 IO119NB5F11 AD6 IO136NB6F13 U4 IO153NB7F14 M7 3- 40 Bank 6 R ev i sio n 1 8 Bank 7 Axcelerator Family FPGAs FG676 FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO153PB7F14 M6 GND A8 GND L11 IO154NB7F14 K2 GND AC23 GND L12 IO154PB7F14 L2 GND AC4 GND L13 IO155NB7F14 K3 GND AD24 GND L14 IO155PB7F14 L3 GND AD3 GND L15 IO156NB7F14 L5 GND AE2 GND L16 IO156PB7F14 L4 GND AE25 GND L17 IO157NB7F14 L6 GND AF1 GND M10 IO157PB7F14 L7 GND AF13 GND M11 IO158NB7F15 J1 GND AF14 GND M12 IO158PB7F15 K1 GND AF19 GND M13 IO159NB7F15 J4 GND AF26 GND M14 IO159PB7F15 K4 GND AF8 GND M15 IO160NB7F15 H2 GND B2 GND M16 IO160PB7F15 J2 GND B25 GND M17 IO161NB7F15 K6 GND B26 GND N1 IO161PB7F15 K5 GND C24 GND N10 IO162NB7F15 H3 GND C3 GND N11 IO162PB7F15 J3 GND G20 GND N12 IO163NB7F15 G2 GND G7 GND N13 IO163PB7F15 G1 GND H1 GND N14 IO164NB7F15 G4 GND H19 GND N15 IO164PB7F15 H4 GND H26 GND N16 IO165NB7F15 F3 GND H8 GND N17 IO165PB7F15 G3 GND J18 GND N26 IO166NB7F15 E2 GND J9 GND P1 IO166PB7F15 F2 GND K10 GND P10 IO167NB7F15 F5 GND K11 GND P11 IO167PB7F15 G5 GND K12 GND P12 GND K13 GND P13 Dedicated I/O GND A1 GND K14 GND P14 GND A13 GND K15 GND P15 GND A14 GND K16 GND P16 GND A19 GND K17 GND P17 GND A26 GND L10 GND P26 R ev i si o n 1 8 3- 41 Package Pin Assignments FG676 FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number GND R10 NC A22 NC C4 GND R11 NC A24 NC D1 GND R12 NC A25 NC D13 GND R13 NC AA11 NC D14 GND R14 NC AA19 NC D17 GND R15 NC AA20 NC D18 GND R16 NC AA4 NC D2 GND R17 NC AA5 NC D26 GND T10 NC AA6 NC D3 GND T11 NC AA7 NC D9 GND T12 NC AA8 NC E1 GND T13 NC AA9 NC E18 GND T14 NC AB1 NC E23 GND T15 NC AB11 NC E24 GND T16 NC AB17 NC E26 GND T17 NC AB18 NC E3 GND U10 NC AB19 NC E4 GND U11 NC AB20 NC E9 GND U12 NC AB8 NC F1 GND U13 NC AB9 NC F18 GND U14 NC AC1 NC F20 GND U15 NC AC13 NC F21 GND U16 NC AC14 NC F22 GND U17 NC AC25 NC F23 GND V18 NC AD1 NC F24 GND V9 NC AD11 NC F4 GND W1 NC AD16 NC F6 GND W19 NC AD25 NC F7 GND W26 NC AE1 NC G21 GND W8 NC AF2 NC G22 GND Y20 NC AF25 NC H21 GND Y7 NC B11 NC H22 GND/LP C2 NC B24 NC H23 NC A11 NC B4 NC H5 NC A21 NC C16 NC H6 3- 42 R ev i sio n 1 8 Axcelerator Family FPGAs FG676 FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number NC J5 VCCA J10 VCCDA AD10 NC J6 VCCA J11 VCCDA AD13 NC P22 VCCA J12 VCCDA AD17 NC R20 VCCA J13 VCCDA B1 NC R21 VCCA J14 VCCDA B17 NC R22 VCCA J15 VCCDA D24 NC R4 VCCA J16 VCCDA E14 NC R5 VCCA J17 VCCDA P2 NC T22 VCCA K18 VCCDA P23 NC T24 VCCA K9 VCCIB0 G10 NC U22 VCCA L18 VCCIB0 G8 NC U24 VCCA L9 VCCIB0 G9 NC V22 VCCA M18 VCCIB0 H10 NC V5 VCCA M9 VCCIB0 H11 NC W21 VCCA N18 VCCIB0 H12 NC W22 VCCA N9 VCCIB0 H13 NC W5 VCCA P18 VCCIB0 H9 NC W6 VCCA P9 VCCIB1 G17 NC Y21 VCCA R18 VCCIB1 G18 NC Y4 VCCA R9 VCCIB1 G19 NC Y5 VCCA T18 VCCIB1 H14 NC Y6 VCCA T9 VCCIB1 H15 PRA E13 VCCA U18 VCCIB1 H16 PRB B14 VCCA U9 VCCIB1 H17 PRC Y14 VCCA V10 VCCIB1 H18 PRD AD14 VCCA V11 VCCIB2 H20 TCK E5 VCCA V12 VCCIB2 J19 TDI B3 VCCA V13 VCCIB2 J20 TDO G6 VCCA V14 VCCIB2 K19 TMS D4 VCCA V15 VCCIB2 K20 TRST A2 VCCA V16 VCCIB2 L19 VCCA AB4 VCCA V17 VCCIB2 M19 VCCA AF24 VCCDA A3 VCCIB2 N19 VCCA C1 VCCDA AB22 VCCIB3 P19 VCCA C26 VCCDA AB5 VCCIB3 R19 R ev i si o n 1 8 3- 43 Package Pin Assignments FG676 FG676 AX500 Function Pin Number AX500 Function Pin Number VCCIB3 T19 VCCIB7 L8 VCCIB3 U19 VCCIB7 M8 VCCIB3 U20 VCCIB7 N8 VCCIB3 V19 VCCPLA E12 VCCIB3 V20 VCCPLB F13 VCCIB3 W20 VCCPLC E15 VCCIB4 W14 VCCPLD G14 VCCIB4 W15 VCCPLE AF15 VCCIB4 W16 VCCPLF AA14 VCCIB4 W17 VCCPLG AF12 VCCIB4 W18 VCCPLH AB13 VCCIB4 Y17 VCOMPLA D12 VCCIB4 Y18 VCOMPLB G13 VCCIB4 Y19 VCOMPLC D15 VCCIB5 W10 VCOMPLD F14 VCCIB5 W11 VCOMPLE AD15 VCCIB5 W12 VCOMPLF AB14 VCCIB5 W13 VCOMPLG AD12 VCCIB5 W9 VCOMPLH Y13 VCCIB5 Y10 VPUMP E22 VCCIB5 Y8 VCCIB5 Y9 VCCIB6 P8 VCCIB6 R8 VCCIB6 T8 VCCIB6 U7 VCCIB6 U8 VCCIB6 V7 VCCIB6 V8 VCCIB6 W7 VCCIB7 H7 VCCIB7 J7 VCCIB7 J8 VCCIB7 K7 VCCIB7 K8 3- 44 R ev i sio n 1 8 Axcelerator Family FPGAs FG676 AX1000 Function FG676 Pin Number Bank 0 FG676 AX1000 Function Pin Number AX1000 Function Pin Number IO21PB0F1 C10 IO48NB1F4 F17 IO00NB0F0 B4 IO22NB0F2 F11 IO48PB1F4 E17 IO00PB0F0 C4 IO22PB0F2 G11 IO49NB1F4 A22 IO02NB0F0 E7 IO24NB0F2 D11 IO49PB1F4 A21 IO02PB0F0 E6 IO24PB0F2 E11 IO50NB1F4 E18 IO03NB0F0 D6 IO26NB0F2 C12 IO50PB1F4 F18 IO03PB0F0 D5 IO26PB0F2 C11 IO51NB1F4 D19 IO04NB0F0 B5 IO28NB0F2 F12 IO51PB1F4 C19 IO04PB0F0 C5 IO28PB0F2 G12 IO52NB1F4 D20 IO05NB0F0 A5 IO30NB0F2/HCLKAN A12 IO52PB1F4 C20 IO05PB0F0 A4 IO30PB0F2/HCLKAP B12 IO54NB1F5 B22 IO06NB0F0 F7 IO31NB0F2/HCLKBN C13 IO54PB1F5 B21 IO06PB0F0 F6 IO31PB0F2/HCLKBP B13 IO55NB1F5 D21 IO07NB0F0 B6 Bank 1 IO55PB1F5 C21 IO07PB0F0 C6 IO32NB1F3/HCLKCN C15 IO56NB1F5 F19 IO08NB0F0 C7 IO32PB1F3/HCLKCP C14 IO56PB1F5 E19 IO08PB0F0 D7 IO33NB1F3/HCLKDN A15 IO57NB1F5 B23 IO10NB0F0 F8 IO33PB1F3/HCLKDP B15 IO57PB1F5 A23 IO10PB0F0 E8 IO35NB1F3 B16 IO58NB1F5 D22 IO11NB0F0 A7 IO35PB1F3 A16 IO58PB1F5 C22 IO11PB0F0 A6 IO36NB1F3 F15 IO59NB1F5 B24 IO12NB0F1 C8 IO36PB1F3 G15 IO59PB1F5 A24 IO12PB0F1 D8 IO38NB1F3 F16 IO60NB1F5 E21 IO13NB0F1 B8 IO38PB1F3 G16 IO60PB1F5 E20 IO13PB0F1 B7 IO40NB1F3 A18 IO62NB1F5 D23 IO14NB0F1 D9 IO40PB1F3 A17 IO62PB1F5 C23 IO14PB0F1 E9 IO41NB1F4 C18 IO63NB1F5 F21 IO16NB0F1 F10 IO41PB1F4 C17 IO63PB1F5 F20 IO16PB0F1 F9 IO42NB1F4 D16 IO18NB0F1 B9 IO42PB1F4 E16 IO64NB2F6 H21 IO18PB0F1 C9 IO44NB1F4 D18 IO64PB2F6 G21 IO19NB0F1 A10 IO44PB1F4 D17 IO65NB2F6 G22 IO19PB0F1 A9 IO45NB1F4 B19 IO65PB2F6 F22 IO20NB0F1 D10 IO45PB1F4 B18 IO66NB2F6 F24 IO20PB0F1 E10 IO46NB1F4 B20 IO66PB2F6 F23 IO21NB0F1 B10 IO46PB1F4 A20 IO67NB2F6 E24 R ev i si o n 1 8 Bank 2 3- 45 Package Pin Assignments FG676 FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO67PB2F6 E23 IO88PB2F8 M22 IO110NB3F10 T21 IO68NB2F6 H23 IO89NB2F8 M26 IO110PB3F10 T20 IO68PB2F6 H22 IO89PB2F8 M25 IO112NB3F10 V23 IO69NB2F6 D25 IO90NB2F8 M20 IO112PB3F10 U23 IO69PB2F6 C25 IO90PB2F8 M21 IO113NB3F10 Y25 IO70NB2F6 G24 IO91NB2F8 N24 IO113PB3F10 W25 IO70PB2F6 G23 IO91PB2F8 M24 IO114NB3F10 V21 IO71NB2F6 F25 IO92NB2F8 N22 IO114PB3F10 U21 IO71PB2F6 E25 IO92PB2F8 N23 IO115NB3F10 W24 IO72NB2F6 G26 IO94NB2F8 N20 IO115PB3F10 V24 IO72PB2F6 F26 IO94PB2F8 N21 IO116NB3F10 AA26 IO73NB2F6 E26 IO95NB2F8 P25 IO116PB3F10 Y26 IO73PB2F6 D26 IO95PB2F8 N25 IO118NB3F11 AC26 IO74NB2F7 J21 IO118PB3F11 AB26 IO74PB2F7 J22 IO98NB3F9 P20 IO119NB3F11 AB25 IO75NB2F7 J24 IO98PB3F9 P21 IO119PB3F11 AA25 IO75PB2F7 H24 IO99NB3F9 R24 IO120NB3F11 W22 IO76NB2F7 K23 IO99PB3F9 P24 IO120PB3F11 V22 IO76PB2F7 J23 IO100NB3F9 R22 IO121NB3F11 Y23 IO77NB2F7 H25 IO100PB3F9 P22 IO121PB3F11 W23 IO77PB2F7 G25 IO101NB3F9 T26 IO122NB3F11 AA24 IO78NB2F7 K25 IO101PB3F9 R26 IO122PB3F11 Y24 IO78PB2F7 J25 IO102NB3F9 R21 IO123NB3F11 AE26 IO80NB2F7 K21 IO102PB3F9 R20 IO123PB3F11 AD26 IO80PB2F7 K22 IO103NB3F9 T25 IO124NB3F11 Y21 IO81NB2F7 K26 IO103PB3F9 R25 IO124PB3F11 W21 IO81PB2F7 J26 IO105NB3F9 V26 IO125NB3F11 AD25 IO82NB2F7 L24 IO105PB3F9 U26 IO125PB3F11 AC25 IO82PB2F7 K24 IO106NB3F9 T23 IO126NB3F11 AB23 IO83NB2F7 L23 IO106PB3F9 R23 IO126PB3F11 AA23 IO83PB2F7 L22 IO107NB3F10 U24 IO127NB3F11 AC24 IO84NB2F7 L20 IO107PB3F10 T24 IO127PB3F11 AB24 IO84PB2F7 L21 IO108NB3F10 U22 IO128NB3F11 AA22 IO86NB2F8 L26 IO108PB3F10 T22 IO128PB3F11 Y22 IO86PB2F8 L25 IO109NB3F10 V25 IO88NB2F8 M23 IO109PB3F10 U25 3- 46 Bank 3 R ev i sio n 1 8 Bank 4 IO129NB4F12 AB21 Axcelerator Family FPGAs FG676 FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO129PB4F12 AA21 IO153PB4F14 AE18 IO177NB5F16 AA10 IO131NB4F12 AD22 IO154NB4F14 AF17 IO177PB5F16 AB10 IO131PB4F12 AD23 IO154PB4F14 AF18 IO179NB5F16 AD7 IO132NB4F12 AE23 IO155NB4F14 AA15 IO179PB5F16 AD8 IO132PB4F12 AE24 IO155PB4F14 Y15 IO180NB5F16 AC7 IO133NB4F12 AB20 IO157NB4F14 AC15 IO180PB5F16 AC8 IO133PB4F12 AA20 IO157PB4F14 AB15 IO181NB5F17 AA9 IO134NB4F12 AC21 IO159NB4F14/CLKEN AE16 IO181PB5F17 AB9 IO134PB4F12 AC22 IO159PB4F14/CLKEP AF16 IO183NB5F17 AD6 IO135NB4F12 AF22 IO160NB4F14/CLKFN AE14 IO183PB5F17 AE6 IO135PB4F12 AF23 IO160PB4F14/CLKFP AE15 IO184NB5F17 AE5 IO137NB4F12 AB19 Bank 5 IO184PB5F17 AF5 IO137PB4F12 AA19 IO161NB5F15/CLKGN AE12 IO185NB5F17 AA8 IO139NB4F13 AC19 IO161PB5F15/CLKGP AE13 IO185PB5F17 AB8 IO139PB4F13 AC20 IO162NB5F15/CLKHN AE11 IO187NB5F17 AC5 IO140NB4F13 AE21 IO162PB5F15/CLKHP AF11 IO187PB5F17 AC6 IO140PB4F13 AE22 IO163NB5F15 AC12 IO188NB5F17 AD4 IO141NB4F13 AD20 IO163PB5F15 AB12 IO188PB5F17 AD5 IO141PB4F13 AD21 IO165NB5F15 Y12 IO189NB5F17 AB6 IO143NB4F13 AB17 IO165PB5F15 AA13 IO189PB5F17 AB7 IO143PB4F13 AB18 IO167NB5F15 Y11 IO190NB5F17 AF4 IO144NB4F13 AE19 IO167PB5F15 AA12 IO190PB5F17 AE4 IO144PB4F13 AE20 IO168NB5F15 AF9 IO191NB5F17 AE3 IO145NB4F13 AC17 IO168PB5F15 AF10 IO191PB5F17 AF3 IO145PB4F13 AC18 IO169NB5F15 AB11 IO192NB5F17 AA6 IO146NB4F13 AD18 IO169PB5F15 AA11 IO192PB5F17 AA7 IO146PB4F13 AD19 IO171NB5F16 AE9 IO147NB4F13 AA17 IO171PB5F16 AE10 IO193NB6F18 Y5 IO147PB4F13 AA18 IO173NB5F16 AC10 IO193PB6F18 AA5 IO148NB4F13 AF20 IO173PB5F16 AC11 IO194NB6F18 AB3 IO148PB4F13 AF21 IO174NB5F16 AE7 IO194PB6F18 AC3 IO149NB4F13 AA16 IO174PB5F16 AE8 IO195NB6F18 Y4 IO149PB4F13 Y16 IO175NB5F16 AC9 IO195PB6F18 AA4 IO151NB4F13 AC16 IO175PB5F16 AD9 IO196NB6F18 AC2 IO151PB4F13 AB16 IO176NB5F16 AF6 IO196PB6F18 AD2 IO153NB4F14 AE17 IO176PB5F16 AF7 IO197NB6F18 W6 R ev i si o n 1 8 Bank 6 3- 47 Package Pin Assignments FG676 FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO197PB6F18 Y6 IO217PB6F20 R4 IO241NB7F22 K6 IO198NB6F18 AD1 IO218NB6F20 R2 IO241PB7F22 K5 IO198PB6F18 AE1 IO218PB6F20 T2 IO242NB7F22 H2 IO199NB6F18 AA2 IO219NB6F20 P3 IO242PB7F22 J2 IO199PB6F18 AB2 IO219PB6F20 R3 IO243NB7F22 J4 IO200NB6F18 Y3 IO220NB6F20 R1 IO243PB7F22 K4 IO200PB6F18 AA3 IO220PB6F20 T1 IO244NB7F22 H3 IO201NB6F18 V5 IO221NB6F20 P6 IO244PB7F22 J3 IO201PB6F18 W5 IO221PB6F20 P7 IO245NB7F22 G2 IO202NB6F18 AB1 IO223NB6F20 P5 IO245PB7F22 G1 IO202PB6F18 AC1 IO223PB6F20 P4 IO247NB7F23 J6 IO203NB6F19 V4 IO247PB7F23 J5 IO203PB6F19 W4 IO225NB7F21 N5 IO248NB7F23 E1 IO204NB6F19 V3 IO225PB7F21 N4 IO248PB7F23 F1 IO204PB6F19 W3 IO226NB7F21 N2 IO249NB7F23 E2 IO205NB6F19 U6 IO226PB7F21 N3 IO249PB7F23 F2 IO205PB6F19 V6 IO227NB7F21 N6 IO250NB7F23 G4 IO206NB6F19 W2 IO227PB7F21 N7 IO250PB7F23 H4 IO206PB6F19 Y2 IO229NB7F21 M7 IO251NB7F23 F3 IO207NB6F19 U4 IO229PB7F21 M6 IO251PB7F23 G3 IO207PB6F19 U5 IO231NB7F21 M5 IO253NB7F23 H6 IO208NB6F19 Y1 IO231PB7F21 M4 IO253PB7F23 H5 IO208PB6F19 AA1 IO232NB7F21 L1 IO254NB7F23 D2 IO209NB6F19 T6 IO232PB7F21 M1 IO254PB7F23 D1 IO209PB6F19 T7 IO233NB7F21 M2 IO255NB7F23 E4 IO211NB6F19 T3 IO233PB7F21 M3 IO255PB7F23 F4 IO211PB6F19 U3 IO235NB7F21 K2 IO256NB7F23 D3 IO212NB6F19 V1 IO235PB7F21 L2 IO256PB7F23 E3 IO212PB6F19 V2 IO236NB7F22 L5 IO257NB7F23 F5 IO213NB6F19 T5 IO236PB7F22 L4 IO257PB7F23 G5 IO213PB6F19 T4 IO237NB7F22 L6 IO214NB6F20 U1 IO237PB7F22 L7 GND A1 IO214PB6F20 U2 IO238NB7F22 K3 GND A13 IO215NB6F20 R6 IO238PB7F22 L3 GND A14 IO215PB6F20 R7 IO240NB7F22 J1 GND A19 IO217NB6F20 R5 IO240PB7F22 K1 GND A26 3- 48 Bank 7 R ev i sio n 1 8 Dedicated I/O Axcelerator Family FPGAs FG676 FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND A8 GND L12 GND R12 GND AC23 GND L13 GND R13 GND AC4 GND L14 GND R14 GND AD24 GND L15 GND R15 GND AD3 GND L16 GND R16 GND AE2 GND L17 GND R17 GND AE25 GND M10 GND T10 GND AF1 GND M11 GND T11 GND AF13 GND M12 GND T12 GND AF14 GND M13 GND T13 GND AF19 GND M14 GND T14 GND AF26 GND M15 GND T15 GND AF8 GND M16 GND T16 GND B2 GND M17 GND T17 GND B25 GND N1 GND U10 GND B26 GND N10 GND U11 GND C24 GND N11 GND U12 GND C3 GND N12 GND U13 GND G20 GND N13 GND U14 GND G7 GND N14 GND U15 GND H1 GND N15 GND U16 GND H19 GND N16 GND U17 GND H26 GND N17 GND V18 GND H8 GND N26 GND V9 GND J18 GND P1 GND W1 GND J9 GND P10 GND W19 GND K10 GND P11 GND W26 GND K11 GND P12 GND W8 GND K12 GND P13 GND Y20 GND K13 GND P14 GND Y7 GND K14 GND P15 GND/LP C2 GND K15 GND P16 NC A25 GND K16 GND P17 NC AC13 GND K17 GND P26 NC AC14 GND L10 GND R10 NC AF2 GND L11 GND R11 NC AF25 R ev i si o n 1 8 3- 49 Package Pin Assignments FG676 FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number NC D13 VCCA T9 VCCIB0 G10 NC D14 VCCA U18 VCCIB0 G8 PRA E13 VCCA U9 VCCIB0 G9 PRB B14 VCCA V10 VCCIB0 H10 PRC Y14 VCCA V11 VCCIB0 H11 PRD AD14 VCCA V12 VCCIB0 H12 TCK E5 VCCA V13 VCCIB0 H13 TDI B3 VCCA V14 VCCIB0 H9 TDO G6 VCCA V15 VCCIB1 G17 TMS D4 VCCA V16 VCCIB1 G18 TRST A2 VCCA V17 VCCIB1 G19 VCCA AB4 VCCPLA E12 VCCIB1 H14 VCCA AF24 VCCPLB F13 VCCIB1 H15 VCCA C1 VCCPLC E15 VCCIB1 H16 VCCA C26 VCCPLD G14 VCCIB1 H17 VCCA J10 VCCPLE AF15 VCCIB1 H18 VCCA J11 VCCPLF AA14 VCCIB2 H20 VCCA J12 VCCPLG AF12 VCCIB2 J19 VCCA J13 VCCPLH AB13 VCCIB2 J20 VCCA J14 VCCDA A11 VCCIB2 K19 VCCA J15 VCCDA A3 VCCIB2 K20 VCCA J16 VCCDA AB22 VCCIB2 L19 VCCA J17 VCCDA AB5 VCCIB2 M19 VCCA K18 VCCDA AD10 VCCIB2 N19 VCCA K9 VCCDA AD11 VCCIB3 P19 VCCA L18 VCCDA AD13 VCCIB3 R19 VCCA L9 VCCDA AD16 VCCIB3 T19 VCCA M18 VCCDA AD17 VCCIB3 U19 VCCA M9 VCCDA B1 VCCIB3 U20 VCCA N18 VCCDA B11 VCCIB3 V19 VCCA N9 VCCDA B17 VCCIB3 V20 VCCA P18 VCCDA C16 VCCIB3 W20 VCCA P9 VCCDA D24 VCCIB4 W14 VCCA R18 VCCDA E14 VCCIB4 W15 VCCA R9 VCCDA P2 VCCIB4 W16 VCCA T18 VCCDA P23 VCCIB4 W17 3- 50 R ev i sio n 1 8 Axcelerator Family FPGAs FG676 FG676 AX1000 Function Pin Number AX1000 Function Pin Number VCCIB4 W18 VCOMPLH Y13 VCCIB4 Y17 VPUMP E22 VCCIB4 Y18 VCCIB4 Y19 VCCIB5 W10 VCCIB5 W11 VCCIB5 W12 VCCIB5 W13 VCCIB5 W9 VCCIB5 Y10 VCCIB5 Y8 VCCIB5 Y9 VCCIB6 P8 VCCIB6 R8 VCCIB6 T8 VCCIB6 U7 VCCIB6 U8 VCCIB6 V7 VCCIB6 V8 VCCIB6 W7 VCCIB7 H7 VCCIB7 J7 VCCIB7 J8 VCCIB7 K7 VCCIB7 K8 VCCIB7 L8 VCCIB7 M8 VCCIB7 N8 VCOMPLA D12 VCOMPLB G13 VCOMPLC D15 VCOMPLD F14 VCOMPLE AD15 VCOMPLF AB14 VCOMPLG AD12 R ev i si o n 1 8 3- 51 Package Pin Assignments FG896 A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. 3- 52 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 AX1000 Function FG896 Pin Number Bank 0 FG896 AX1000 Function Pin Number AX1000 Function Pin Number IO17NB0F1 B11 IO34NB1F3 A17 IO00NB0F0 D6 IO17PB0F1 B10 IO34PB1F3 B17 IO00PB0F0 E6 IO18NB0F1 D11 IO35NB1F3 D18 IO01NB0F0 A5 IO18PB0F1 E11 IO35PB1F3 C18 IO01PB0F0 B5 IO19NB0F1 C12 IO36NB1F3 H17 IO02NB0F0 G9 IO19PB0F1 C11 IO36PB1F3 J17 IO02PB0F0 G8 IO20NB0F1 F12 IO37NB1F3 B19 IO03NB0F0 F8 IO20PB0F1 G12 IO37PB1F3 A19 IO03PB0F0 F7 IO21NB0F1 D12 IO38NB1F3 H18 IO04NB0F0 D7 IO21PB0F1 E12 IO38PB1F3 J18 IO04PB0F0 E7 IO22NB0F2 H13 IO39NB1F3 B20 IO05NB0F0 C7 IO22PB0F2 J13 IO39PB1F3 A20 IO05PB0F0 C6 IO23NB0F2 A12 IO40NB1F3 C20 IO06NB0F0 H9 IO23PB0F2 A11 IO40PB1F3 C19 IO06PB0F0 H8 IO24NB0F2 F13 IO41NB1F4 E20 IO07NB0F0 D8 IO24PB0F2 G13 IO41PB1F4 E19 IO07PB0F0 E8 IO25NB0F2 B13 IO42NB1F4 F18 IO08NB0F0 E9 IO25PB0F2 B12 IO42PB1F4 G18 IO08PB0F0 F9 IO26NB0F2 E14 IO43NB1F4 A22 IO09NB0F0 A7 IO26PB0F2 E13 IO43PB1F4 A21 IO09PB0F0 B7 IO27NB0F2 B14 IO44NB1F4 F20 IO10NB0F0 H10 IO27PB0F2 A14 IO44PB1F4 F19 IO10PB0F0 G10 IO28NB0F2 H14 IO45NB1F4 D21 IO11NB0F0 C9 IO28PB0F2 J14 IO45PB1F4 D20 IO11PB0F0 C8 IO29NB0F2 B15 IO46NB1F4 D22 IO12NB0F1 E10 IO29PB0F2 A15 IO46PB1F4 C22 IO12PB0F1 F10 IO30NB0F2/HCLKAN C14 IO47NB1F4 A25 IO13NB0F1 D10 IO30PB0F2/HCLKAP D14 IO47PB1F4 A24 IO13PB0F1 D9 IO31NB0F2/HCLKBN E15 IO48NB1F4 H19 IO14NB0F1 F11 IO31PB0F2/HCLKBP D15 IO48PB1F4 G19 IO14PB0F1 G11 Bank 1 IO49NB1F4 C24 IO15NB0F1 A10 IO32NB1F3/HCLKCN E17 IO49PB1F4 C23 IO15PB0F1 A9 IO32PB1F3/HCLKCP E16 IO50NB1F4 G20 IO16NB0F1 H12 IO33NB1F3/HCLKDN C17 IO50PB1F4 H20 IO16PB0F1 H11 IO33PB1F3/HCLKDP D17 IO51NB1F4 F21 R ev i si o n 1 8 3- 53 Package Pin Assignments FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO51PB1F4 E21 IO68PB2F6 K24 IO86NB2F8 N28 IO52NB1F4 F22 IO69NB2F6 F27 IO86PB2F8 N27 IO52PB1F4 E22 IO69PB2F6 E27 IO87NB2F8 P29 IO53NB1F4 B25 IO70NB2F6 J26 IO87PB2F8 P30 IO53PB1F4 B24 IO70PB2F6 J25 IO88NB2F8 P25 IO54NB1F5 D24 IO71NB2F6 H27 IO88PB2F8 P24 IO54PB1F5 D23 IO71PB2F6 G27 IO89NB2F8 P28 IO55NB1F5 F23 IO72NB2F6 J28 IO89PB2F8 P27 IO55PB1F5 E23 IO72PB2F6 H28 IO90NB2F8 P22 IO56NB1F5 H21 IO73NB2F6 G28 IO90PB2F8 P23 IO56PB1F5 G21 IO73PB2F6 F28 IO91NB2F8 R26 IO57NB1F5 D25 IO74NB2F7 L23 IO91PB2F8 P26 IO57PB1F5 C25 IO74PB2F7 L24 IO92NB2F8 R24 IO58NB1F5 F24 IO75NB2F7 L26 IO92PB2F8 R25 IO58PB1F5 E24 IO75PB2F7 K26 IO93NB2F8 R29 IO59NB1F5 D26 IO76NB2F7 M25 IO93PB2F8 R30 IO59PB1F5 C26 IO76PB2F7 L25 IO94NB2F8 R22 IO60NB1F5 G23 IO77NB2F7 K27 IO94PB2F8 R23 IO60PB1F5 G22 IO77PB2F7 J27 IO95NB2F8 T27 IO61NB1F5 B27 IO78NB2F7 M27 IO95PB2F8 R27 IO61PB1F5 A27 IO78PB2F7 L27 IO62NB1F5 F25 IO79NB2F7 K30 IO96NB3F9 T29 IO62PB1F5 E25 IO79PB2F7 K29 IO96PB3F9 T30 IO63NB1F5 H23 IO80NB2F7 M23 IO97NB3F9 U29 IO63PB1F5 H22 IO80PB2F7 M24 IO97PB3F9 U30 IO81NB2F7 M28 IO98NB3F9 T22 Bank 2 3- 54 Bank 3 IO64NB2F6 K23 IO81PB2F7 L28 IO98PB3F9 T23 IO64PB2F6 J23 IO82NB2F7 N26 IO99NB3F9 U26 IO65NB2F6 J24 IO82PB2F7 M26 IO99PB3F9 T26 IO65PB2F6 H24 IO83NB2F7 N25 IO100NB3F9 U24 IO66NB2F6 H26 IO83PB2F7 N24 IO100PB3F9 T24 IO66PB2F6 H25 IO84NB2F7 N22 IO101NB3F9 V28 IO67NB2F6 G26 IO84PB2F7 N23 IO101PB3F9 U28 IO67PB2F6 G25 IO85NB2F8 M29 IO102NB3F9 U23 IO68NB2F6 K25 IO85PB2F8 L29 IO102PB3F9 U22 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO103NB3F9 V27 IO120PB3F11 Y24 IO137PB4F12 AC21 IO103PB3F9 U27 IO121NB3F11 AB25 IO138NB4F12 AK24 IO104NB3F9 W29 IO121PB3F11 AA25 IO138PB4F12 AK25 IO104PB3F9 V29 IO122NB3F11 AC26 IO139NB4F13 AE21 IO105NB3F9 Y28 IO122PB3F11 AB26 IO139PB4F13 AE22 IO105PB3F9 W28 IO123NB3F11 AG28 IO140NB4F13 AG23 IO106NB3F9 V25 IO123PB3F11 AF28 IO140PB4F13 AG24 IO106PB3F9 U25 IO124NB3F11 AB23 IO141NB4F13 AF22 IO107NB3F10 W26 IO124PB3F11 AA23 IO141PB4F13 AF23 IO107PB3F10 V26 IO125NB3F11 AF27 IO142NB4F13 AJ23 IO108NB3F10 W24 IO125PB3F11 AE27 IO142PB4F13 AJ24 IO108PB3F10 V24 IO126NB3F11 AD25 IO143NB4F13 AD19 IO109NB3F10 Y27 IO126PB3F11 AC25 IO143PB4F13 AD20 IO109PB3F10 W27 IO127NB3F11 AE26 IO144NB4F13 AG21 IO110NB3F10 V23 IO127PB3F11 AD26 IO144PB4F13 AG22 IO110PB3F10 V22 IO128NB3F11 AC24 IO145NB4F13 AE19 IO111NB3F10 AA29 IO128PB3F11 AB24 IO145PB4F13 AE20 IO111PB3F10 Y29 IO146NB4F13 AF20 IO112NB3F10 Y25 IO129NB4F12 AD23 IO146PB4F13 AF21 IO112PB3F10 W25 IO129PB4F12 AC23 IO147NB4F13 AC19 IO113NB3F10 AB27 IO130NB4F12 AK26 IO147PB4F13 AC20 IO113PB3F10 AA27 IO130PB4F12 AK27 IO148NB4F13 AH22 IO114NB3F10 Y23 IO131NB4F12 AF24 IO148PB4F13 AH23 IO114PB3F10 W23 IO131PB4F12 AF25 IO149NB4F13 AC18 IO115NB3F10 AA26 IO132NB4F12 AG25 IO149PB4F13 AB18 IO115PB3F10 Y26 IO132PB4F12 AG26 IO150NB4F13 AK21 IO116NB3F10 AC28 IO133NB4F12 AD22 IO150PB4F13 AJ21 IO116PB3F10 AB28 IO133PB4F12 AC22 IO151NB4F13 AE18 IO117NB3F10 AE29 IO134NB4F12 AE23 IO151PB4F13 AD18 IO117PB3F10 AD29 IO134PB4F12 AE24 IO152NB4F14 AJ20 IO118NB3F11 AE28 IO135NB4F12 AH24 IO152PB4F14 AK20 IO118PB3F11 AD28 IO135PB4F12 AH25 IO153NB4F14 AG19 IO119NB3F11 AD27 IO136NB4F12 AJ25 IO153PB4F14 AG20 IO119PB3F11 AC27 IO136PB4F12 AJ26 IO154NB4F14 AH19 IO120NB3F11 AA24 IO137NB4F12 AD21 IO154PB4F14 AH20 Bank 4 R ev i si o n 1 8 3- 55 Package Pin Assignments FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO155NB4F14 AC17 IO172NB5F16 AK9 IO189PB5F17 AD9 IO155PB4F14 AB17 IO172PB5F16 AK10 IO190NB5F17 AH6 IO156NB4F14 AK19 IO173NB5F16 AE12 IO190PB5F17 AG6 IO156PB4F14 AJ19 IO173PB5F16 AE13 IO191NB5F17 AG5 IO157NB4F14 AE17 IO174NB5F16 AG9 IO191PB5F17 AH5 IO157PB4F14 AD17 IO174PB5F16 AG10 IO192NB5F17 AC8 IO158NB4F14 AJ17 IO175NB5F16 AE11 IO192PB5F17 AC9 IO158PB4F14 AJ18 IO175PB5F16 AF11 IO159NB4F14/CLKEN AG18 IO176NB5F16 AH8 IO193NB6F18 AB7 IO159PB4F14/CLKEP AH18 IO176PB5F16 AH9 IO193PB6F18 AC7 IO160NB4F14/CLKFN AG16 IO177NB5F16 AC12 IO194NB6F18 AD5 IO160PB4F14/CLKFP AG17 IO177PB5F16 AD12 IO194PB6F18 AE5 IO178NB5F16 AJ7 IO195NB6F18 AB6 Bank 5 Bank 6 IO161NB5F15/CLKGN AG14 IO178PB5F16 AJ8 IO195PB6F18 AC6 IO161PB5F15/CLKGP AG15 IO179NB5F16 AF9 IO196NB6F18 AE4 IO162NB5F15/CLKHN AG13 IO179PB5F16 AF10 IO196PB6F18 AF4 IO162PB5F15/CLKHP AH13 IO180NB5F16 AE9 IO197NB6F18 AA8 IO163NB5F15 AE14 IO180PB5F16 AE10 IO197PB6F18 AB8 IO163PB5F15 AD14 IO181NB5F17 AC11 IO198NB6F18 AF3 IO164NB5F15 AJ12 IO181PB5F17 AD11 IO198PB6F18 AG3 IO164PB5F15 AJ13 IO182NB5F17 AK6 IO199NB6F18 AC4 IO165NB5F15 AB14 IO182PB5F17 AK7 IO199PB6F18 AD4 IO165PB5F15 AC15 IO183NB5F17 AF8 IO200NB6F18 AB5 IO166NB5F15 AK11 IO183PB5F17 AG8 IO200PB6F18 AC5 IO166PB5F15 AK12 IO184NB5F17 AG7 IO201NB6F18 Y7 IO167NB5F15 AB13 IO184PB5F17 AH7 IO201PB6F18 AA7 IO167PB5F15 AC14 IO185NB5F17 AC10 IO202NB6F18 AD3 IO168NB5F15 AH11 IO185PB5F17 AD10 IO202PB6F18 AE3 IO168PB5F15 AH12 IO186NB5F17 AJ5 IO203NB6F19 Y6 IO169NB5F15 AD13 IO186PB5F17 AJ6 IO203PB6F19 AA6 IO169PB5F15 AC13 IO187NB5F17 AE7 IO204NB6F19 Y5 IO170NB5F15 AJ10 IO187PB5F17 AE8 IO204PB6F19 AA5 IO170PB5F15 AJ11 IO188NB5F17 AF6 IO205NB6F19 W8 IO171NB5F16 AG11 IO188PB5F17 AF7 IO205PB6F19 Y8 IO171PB5F16 AG12 IO189NB5F17 AD8 IO206NB6F19 AA4 3- 56 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO206PB6F19 AB4 IO224NB6F20 R2 IO241NB7F22 M8 IO207NB6F19 W6 IO224PB6F20 T2 IO241PB7F22 M7 IO207PB6F19 W7 IO242NB7F22 K4 IO208NB6F19 AB3 IO225NB7F21 R7 IO242PB7F22 L4 IO208PB6F19 AC3 IO225PB7F21 R6 IO243NB7F22 L6 IO209NB6F19 V8 IO226NB7F21 R4 IO243PB7F22 M6 IO209PB6F19 V9 IO226PB7F21 R5 IO244NB7F22 K5 IO210NB6F19 AA2 IO227NB7F21 R8 IO244PB7F22 L5 IO210PB6F19 AA1 IO227PB7F21 R9 IO245NB7F22 J4 IO211NB6F19 V5 IO228NB7F21 P1 IO245PB7F22 J3 IO211PB6F19 W5 IO228PB7F21 R1 IO246NB7F22 G2 IO212NB6F19 Y3 IO229NB7F21 P9 IO246PB7F22 H2 IO212PB6F19 Y4 IO229PB7F21 P8 IO247NB7F23 L8 IO213NB6F19 V7 IO230NB7F21 N2 IO247PB7F23 L7 IO213PB6F19 V6 IO230PB7F21 P2 IO248NB7F23 G3 IO214NB6F20 W3 IO231NB7F21 P7 IO248PB7F23 H3 IO214PB6F20 W4 IO231PB7F21 P6 IO249NB7F23 G4 IO215NB6F20 U8 IO232NB7F21 N3 IO249PB7F23 H4 IO215PB6F20 U9 IO232PB7F21 P3 IO250NB7F23 J6 IO216NB6F20 W1 IO233NB7F21 P4 IO250PB7F23 K6 IO216PB6F20 W2 IO233PB7F21 P5 IO251NB7F23 H5 IO217NB6F20 U7 IO234NB7F21 L1 IO251PB7F23 J5 IO217PB6F20 U6 IO234PB7F21 M1 IO252NB7F23 F2 IO218NB6F20 U4 IO235NB7F21 M4 IO252PB7F23 F1 IO218PB6F20 V4 IO235PB7F21 N4 IO253NB7F23 K8 IO219NB6F20 T5 IO236NB7F22 N7 IO253PB7F23 K7 IO219PB6F20 U5 IO236PB7F22 N6 IO254NB7F23 F4 IO220NB6F20 U3 IO237NB7F22 N8 IO254PB7F23 F3 IO220PB6F20 V3 IO237PB7F22 N9 IO255NB7F23 G6 IO221NB6F20 T8 IO238NB7F22 M5 IO255PB7F23 H6 IO221PB6F20 T9 IO238PB7F22 N5 IO256NB7F23 F5 IO222NB6F20 U2 IO239NB7F22 L2 IO256PB7F23 G5 IO222PB6F20 V2 IO239PB7F22 M2 IO257NB7F23 H7 IO223NB6F20 T7 IO240NB7F22 L3 IO257PB7F23 J7 IO223PB6F20 T6 IO240PB7F22 M3 Bank 7 R ev i si o n 1 8 Dedicated I/O 3- 57 Package Pin Assignments FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND A13 GND AK18 GND M13 GND A18 GND AK2 GND M14 GND A2 GND AK23 GND M15 GND A23 GND AK29 GND M16 GND A29 GND AK8 GND M17 GND A8 GND B1 GND M18 GND AA10 GND B2 GND M19 GND AA21 GND B22 GND N1 GND AA28 GND B29 GND N12 GND AA3 GND B30 GND N13 GND AB2 GND B9 GND N14 GND AB22 GND C10 GND N15 GND AB29 GND C15 GND N16 GND AB9 GND C16 GND N17 GND AC1 GND C21 GND N18 GND AC30 GND C28 GND N19 GND AE25 GND C3 GND N30 GND AE6 GND D27 GND P12 GND AF26 GND D28 GND P13 GND AF5 GND D4 GND P14 GND AG27 GND E26 GND P15 GND AG4 GND E5 GND P16 GND AH10 GND H1 GND P17 GND AH15 GND H30 GND P18 GND AH16 GND J2 GND P19 GND AH21 GND J22 GND R12 GND AH28 GND J29 GND R13 GND AH3 GND J9 GND R14 GND AJ1 GND K10 GND R15 GND AJ2 GND K21 GND R16 GND AJ22 GND K28 GND R17 GND AJ29 GND K3 GND R18 GND AJ30 GND L11 GND R19 GND AJ9 GND L20 GND R28 GND AK13 GND M12 GND R3 3- 58 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND T12 GND W19 NC AJ4 GND T13 GND Y11 NC AK14 GND T14 GND Y20 NC AK15 GND T15 GND/LP E4 NC AK16 GND T16 NC A16 NC AK17 GND T17 NC A26 NC AK22 GND T18 NC A4 NC AK4 GND T19 NC A6 NC AK5 GND T28 NC AA30 NC B16 GND T3 NC AB1 NC B18 GND U12 NC AB30 NC B21 GND U13 NC AC2 NC B23 GND U14 NC AC29 NC B26 GND U15 NC AD1 NC B4 GND U16 NC AD2 NC B6 GND U17 NC AD30 NC B8 GND U18 NC AE1 NC C27 GND U19 NC AE15 NC D1 GND V1 NC AE16 NC D2 GND V12 NC AE2 NC D29 GND V13 NC AE30 NC D30 GND V14 NC AF1 NC E1 GND V15 NC AF2 NC E2 GND V16 NC AF29 NC E29 GND V17 NC AF30 NC E30 GND V18 NC AG1 NC F15 GND V19 NC AG2 NC F16 GND V30 NC AG29 NC F29 GND W12 NC AG30 NC F30 GND W13 NC AH27 NC G1 GND W14 NC AH4 NC G29 GND W15 NC AJ14 NC G30 GND W16 NC AJ15 NC H29 GND W17 NC AJ16 NC J1 GND W18 NC AJ27 NC J30 R ev i si o n 1 8 3- 59 Package Pin Assignments FG896 FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number NC K1 VCCA N20 VCCDA AF19 NC K2 VCCA P11 VCCDA C13 NC L30 VCCA P20 VCCDA C5 NC M30 VCCA R11 VCCDA D13 NC N29 VCCA R20 VCCDA D19 NC T1 VCCA T11 VCCDA D3 NC U1 VCCA T20 VCCDA E18 NC W30 VCCA U11 VCCDA F26 NC Y1 VCCA U20 VCCDA G16 NC Y2 VCCA V11 VCCDA T25 NC Y30 VCCA V20 VCCDA T4 PRA G15 VCCA W11 VCCIB0 A3 PRB D16 VCCA W20 VCCIB0 B3 PRC AB16 VCCA Y12 VCCIB0 J10 PRD AF16 VCCA Y13 VCCIB0 J11 TCK G7 VCCA Y14 VCCIB0 J12 TDI D5 VCCA Y15 VCCIB0 K11 TDO J8 VCCA Y16 VCCIB0 K12 TMS F6 VCCA Y17 VCCIB0 K13 TRST C4 VCCA Y18 VCCIB0 K14 VCCA AD6 VCCA Y19 VCCIB0 K15 VCCA AH26 VCCPLA G14 VCCIB1 A28 VCCA E28 VCCPLB H15 VCCIB1 B28 VCCA E3 VCCPLC G17 VCCIB1 J19 VCCA L12 VCCPLD J16 VCCIB1 J20 VCCA L13 VCCPLE AH17 VCCIB1 J21 VCCA L14 VCCPLF AC16 VCCIB1 K16 VCCA L15 VCCPLG AH14 VCCIB1 K17 VCCA L16 VCCPLH AD15 VCCIB1 K18 VCCA L17 VCCDA AD24 VCCIB1 K19 VCCA L18 VCCDA AD7 VCCIB1 K20 VCCA L19 VCCDA AF12 VCCIB2 C29 VCCA M11 VCCDA AF13 VCCIB2 C30 VCCA M20 VCCDA AF15 VCCIB2 K22 VCCA N11 VCCDA AF18 VCCIB2 L21 3- 60 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 AX1000 Function Pin Number AX1000 Function Pin Number VCCIB2 L22 VCCIB5 AK3 VCCIB2 M21 VCCIB6 AA9 VCCIB2 M22 VCCIB6 AH1 VCCIB2 N21 VCCIB6 AH2 VCCIB2 P21 VCCIB6 T10 VCCIB2 R21 VCCIB6 U10 VCCIB3 AA22 VCCIB6 V10 VCCIB3 AH29 VCCIB6 W10 VCCIB3 AH30 VCCIB6 W9 VCCIB3 T21 VCCIB6 Y10 VCCIB3 U21 VCCIB6 Y9 VCCIB3 V21 VCCIB7 C1 VCCIB3 W21 VCCIB7 C2 VCCIB3 W22 VCCIB7 K9 VCCIB3 Y21 VCCIB7 L10 VCCIB3 Y22 VCCIB7 L9 VCCIB4 AA16 VCCIB7 M10 VCCIB4 AA17 VCCIB7 M9 VCCIB4 AA18 VCCIB7 N10 VCCIB4 AA19 VCCIB7 P10 VCCIB4 AA20 VCCIB7 R10 VCCIB4 AB19 VCOMPLA F14 VCCIB4 AB20 VCOMPLB J15 VCCIB4 AB21 VCOMPLC F17 VCCIB4 AJ28 VCOMPLD H16 VCCIB4 AK28 VCOMPLE AF17 VCCIB5 AA11 VCOMPLF AD16 VCCIB5 AA12 VCOMPLG AF14 VCCIB5 AA13 VCOMPLH AB15 VCCIB5 AA14 VPUMP G24 VCCIB5 AA15 VCCIB5 AB10 VCCIB5 AB11 VCCIB5 AB12 VCCIB5 AJ3 R ev i si o n 1 8 3- 61 Package Pin Assignments FG896 AX2000 Function FG896 Pin Number Bank 0 3- 62 FG896 AX2000 Function Pin Number IO19NB0F1 D11 Bank 1 AX2000 Function Pin Number IO00NB0F0 B4 IO19PB0F1 E11 IO43NB1F4/HCLKCN E17 IO00PB0F0 A4 IO20PB0F1 B8 IO43PB1F4/HCLKCP E16 IO01NB0F0 F8 IO21NB0F1 H12 IO44NB1F4/HCLKDN C17 IO01PB0F0 F7 IO21PB0F1 H11 IO44PB1F4/HCLKDP D17 IO02NB0F0 D6 IO23NB0F2 A10 IO45NB1F4 A16 IO02PB0F0 E6 IO23PB0F2 A9 IO45PB1F4 B16 IO04NB0F0 A5 IO25NB0F2 F12 IO47NB1F4 H17 IO04PB0F0 B5 IO25PB0F2 G12 IO47PB1F4 J17 IO05NB0F0 H8 IO26NB0F2 B11 IO48NB1F4 A17 IO05PB0F0 G8 IO26PB0F2 B10 IO48PB1F4 B17 IO06NB0F0 D7 IO27NB0F2 D12 IO49NB1F4 H18 IO06PB0F0 E7 IO27PB0F2 E12 IO49PB1F4 J18 IO07NB0F0 D8 IO28NB0F2 C12 IO51NB1F4 F18 IO07PB0F0 E8 IO28PB0F2 C11 IO51PB1F4 G18 IO08NB0F0 C7 IO30NB0F2 A12 IO52NB1F4 B18 IO08PB0F0 C6 IO30PB0F2 A11 IO53NB1F4 D18 IO09NB0F0 G9 IO31NB0F2 F13 IO53PB1F4 C18 IO09PB0F0 H9 IO31PB0F2 G13 IO55NB1F5 H19 IO10NB0F0 A6 IO33NB0F2 H13 IO55PB1F5 G19 IO10PB0F0 B6 IO33PB0F2 J13 IO56NB1F5 B19 IO11NB0F0 H10 IO34NB0F3 B13 IO56PB1F5 A19 IO11PB0F0 G10 IO34PB0F3 B12 IO57NB1F5 E20 IO12NB0F1 E9 IO37NB0F3 E14 IO57PB1F5 E19 IO12PB0F1 F9 IO37PB0F3 E13 IO58NB1F5 C20 IO13NB0F1 E10 IO38NB0F3 B14 IO58PB1F5 C19 IO13PB0F1 F10 IO38PB0F3 A14 IO59NB1F5 B20 IO15NB0F1 F11 IO39NB0F3 H14 IO59PB1F5 A20 IO15PB0F1 G11 IO39PB0F3 J14 IO61NB1F5 F20 IO16NB0F1 A7 IO40NB0F3 B15 IO61PB1F5 F19 IO16PB0F1 B7 IO40PB0F3 A15 IO62NB1F5 A22 IO17NB0F1 D10 IO41NB0F3/HCLKAN C14 IO62PB1F5 A21 IO17PB0F1 D9 IO41PB0F3/HCLKAP D14 IO63NB1F5 D21 IO18NB0F1 C9 IO42NB0F3/HCLKBN E15 IO63PB1F5 D20 IO18PB0F1 C8 IO42PB0F3/HCLKBP D15 IO65NB1F6 G20 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO65PB1F6 H20 IO85NB1F7 F25 IO102PB2F9 D30 IO66NB1F6 B23 IO85PB1F7 E25 IO103NB2F9 L26 IO66PB1F6 B21 IO103PB2F9 K26 IO67NB1F6 H21 IO86NB2F8 G26 IO104NB2F9 F29 IO67PB1F6 G21 IO86PB2F8 G25 IO105NB2F9 M25 IO68NB1F6 D22 IO87NB2F8 K23 IO105PB2F9 L25 IO68PB1F6 C22 IO87PB2F8 J23 IO106NB2F9 K30 IO69NB1F6 A25 IO88NB2F8 J24 IO106PB2F9 K29 IO69PB1F6 A24 IO88PB2F8 H24 IO107NB2F10 M23 IO70NB1F6 F22 IO89NB2F8 E29 IO107PB2F10 M24 IO70PB1F6 E22 IO89PB2F8 D29 IO109NB2F10 M27 IO71NB1F6 F21 IO90NB2F8 F27 IO109PB2F10 L27 IO71PB1F6 E21 IO90PB2F8 E27 IO110NB2F10 M28 IO73NB1F6 C24 IO91NB2F8 H26 IO110PB2F10 L28 IO73PB1F6 C23 IO91PB2F8 H25 IO111NB2F10 N22 IO74NB1F6 D24 IO92NB2F8 G28 IO111PB2F10 N23 IO74PB1F6 D23 IO92PB2F8 F28 IO112NB2F10 M29 IO75NB1F6 H23 IO93NB2F8 J26 IO112PB2F10 L29 IO75PB1F6 H22 IO93PB2F8 J25 IO113NB2F10 N26 IO76NB1F7 B25 IO94NB2F8 H27 IO113PB2F10 M26 IO76PB1F7 B24 IO94PB2F8 G27 IO114NB2F10 M30 IO78NB1F7 B26 IO95NB2F8 H29 IO114PB2F10 L30 IO78PB1F7 A26 IO95PB2F8 G29 IO115NB2F10 N28 IO79NB1F7 F23 IO96NB2F9 G30 IO115PB2F10 N27 IO79PB1F7 E23 IO96PB2F9 F30 IO117NB2F10 N25 IO80NB1F7 D25 IO97NB2F9 K25 IO117PB2F10 N24 IO80PB1F7 C25 IO97PB2F9 K24 IO118NB2F11 N29 IO81NB1F7 G23 IO98NB2F9 J28 IO119NB2F11 P22 IO81PB1F7 G22 IO98PB2F9 H28 IO119PB2F11 P23 IO82NB1F7 B27 IO99NB2F9 L23 IO121NB2F11 P25 IO82PB1F7 A27 IO99PB2F9 L24 IO121PB2F11 P24 IO83NB1F7 F24 IO100NB2F9 K27 IO122NB2F11 P28 IO83PB1F7 E24 IO100PB2F9 J27 IO122PB2F11 P27 IO84NB1F7 D26 IO101PB2F9 J30 IO123NB2F11 R26 IO84PB1F7 C26 IO102NB2F9 E30 IO123PB2F11 P26 Bank 2 R ev i si o n 1 8 3- 63 Package Pin Assignments FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO124NB2F11 P29 IO145NB3F13 W24 IO163NB3F15 AC26 IO124PB2F11 P30 IO145PB3F13 V24 IO163PB3F15 AB26 IO125NB2F11 R22 IO146NB3F13 W27 IO164NB3F15 AE28 IO125PB2F11 R23 IO146PB3F13 W28 IO164PB3F15 AD28 IO127NB2F11 R24 IO147NB3F13 Y28 IO165NB3F15 AC24 IO127PB2F11 R25 IO147PB3F13 Y27 IO165PB3F15 AB24 IO128NB2F11 R29 IO148NB3F13 Y30 IO166NB3F15 AG28 IO128PB2F11 R30 IO148PB3F13 W30 IO166PB3F15 AF28 IO149NB3F13 Y25 IO167NB3F15 AE26 Bank 3 3- 64 IO129NB3F12 T27 IO149PB3F13 W25 IO167PB3F15 AD26 IO129PB3F12 R27 IO150NB3F14 AA29 IO168NB3F15 AD25 IO130NB3F12 T29 IO150PB3F14 Y29 IO168PB3F15 AC25 IO130PB3F12 T30 IO151NB3F14 AC29 IO169NB3F15 AF27 IO131NB3F12 T22 IO152NB3F14 AA26 IO169PB3F15 AE27 IO131PB3F12 T23 IO152PB3F14 Y26 IO170NB3F15 AB23 IO132NB3F12 U26 IO153NB3F14 Y23 IO170PB3F15 AA23 IO132PB3F12 T26 IO153PB3F14 W23 IO133NB3F12 U24 IO154NB3F14 AB30 IO171NB4F16 AG29 IO133PB3F12 T24 IO154PB3F14 AA30 IO171PB4F16 AG30 IO135NB3F12 U23 IO155NB3F14 AB27 IO172NB4F16 AF24 IO135PB3F12 U22 IO155PB3F14 AA27 IO172PB4F16 AF25 IO136NB3F12 U29 IO156NB3F14 AC28 IO173NB4F16 AG25 IO136PB3F12 U30 IO156PB3F14 AB28 IO173PB4F16 AG26 IO137NB3F12 V28 IO157NB3F14 AA24 IO174NB4F16 AJ25 IO137PB3F12 U28 IO157PB3F14 Y24 IO174PB4F16 AJ26 IO138NB3F12 V27 IO158NB3F14 AF29 IO175NB4F16 AK26 IO138PB3F12 U27 IO158PB3F14 AF30 IO175PB4F16 AK27 IO139NB3F13 V25 IO159NB3F14 AB25 IO176NB4F16 AE23 IO139PB3F13 U25 IO159PB3F14 AA25 IO176PB4F16 AE24 IO141NB3F13 V23 IO160NB3F14 AE30 IO177NB4F16 AH24 IO141PB3F13 V22 IO160PB3F14 AD30 IO177PB4F16 AH25 IO142NB3F13 W29 IO161NB3F15 AE29 IO178NB4F16 AD23 IO142PB3F13 V29 IO161PB3F15 AD29 IO178PB4F16 AC23 IO143NB3F13 W26 IO162NB3F15 AD27 IO179PB4F16 AJ27 IO143PB3F13 V26 IO162PB3F15 AC27 IO180NB4F16 AG23 R ev i sio n 1 8 Bank 4 Axcelerator Family FPGAs FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO180PB4F16 AG24 IO201PB4F18 AJ19 IO225NB5F21 AH11 IO181NB4F17 AK24 IO202NB4F18 AC18 IO225PB5F21 AH12 IO181PB4F17 AK25 IO202PB4F18 AB18 IO226NB5F21 AC13 IO182NB4F17 AD22 IO206NB4F19 AE18 IO226PB5F21 AD13 IO182PB4F17 AC22 IO206PB4F19 AD18 IO227NB5F21 AE12 IO183NB4F17 AF22 IO207NB4F19 AJ17 IO227PB5F21 AE13 IO183PB4F17 AF23 IO207PB4F19 AJ18 IO228NB5F21 AG11 IO184NB4F17 AE21 IO208NB4F19 AE17 IO228PB5F21 AG12 IO184PB4F17 AE22 IO208PB4F19 AD17 IO229NB5F21 AK11 IO185NB4F17 AJ23 IO209NB4F19 AK17 IO229PB5F21 AK12 IO185PB4F17 AJ24 IO210NB4F19 AC17 IO230NB5F21 AC12 IO187NB4F17 AH22 IO210PB4F19 AB17 IO230PB5F21 AD12 IO187PB4F17 AH23 IO211NB4F19 AJ16 IO232NB5F21 AE11 IO188NB4F17 AD21 IO211PB4F19 AK16 IO232PB5F21 AF11 IO188PB4F17 AC21 IO212NB4F19/CLKEN AG18 IO233NB5F21 AJ10 IO189PB4F17 AK22 IO212PB4F19/CLKEP AH18 IO233PB5F21 AJ11 IO190NB4F17 AF20 IO213NB4F19/CLKFN AG16 IO234NB5F21 AC11 IO190PB4F17 AF21 IO213PB4F19/CLKFP AG17 IO234PB5F21 AD11 IO191NB4F17 AG21 Bank 5 IO236NB5F22 AK9 IO191PB4F17 AG22 IO214NB5F20/CLKGN AG14 IO236PB5F22 AK10 IO192NB4F17 AE19 IO214PB5F20/CLKGP AG15 IO237NB5F22 AG9 IO192PB4F17 AE20 IO215NB5F20/CLKHN AG13 IO237PB5F22 AG10 IO195NB4F18 AK21 IO215PB5F20/CLKHP AH13 IO238NB5F22 AF9 IO195PB4F18 AJ21 IO216NB5F20 AB14 IO238PB5F22 AF10 IO196NB4F18 AD19 IO216PB5F20 AC15 IO239NB5F22 AH8 IO196PB4F18 AD20 IO217NB5F20 AK15 IO239PB5F22 AH9 IO197NB4F18 AJ20 IO217PB5F20 AJ15 IO240NB5F22 AC10 IO197PB4F18 AK20 IO218NB5F20 AE14 IO240PB5F22 AD10 IO198NB4F18 AC19 IO218PB5F20 AD14 IO242NB5F22 AE9 IO198PB4F18 AC20 IO219NB5F20 AK14 IO242PB5F22 AE10 IO199NB4F18 AG19 IO219PB5F20 AJ14 IO243NB5F22 AJ7 IO199PB4F18 AG20 IO222NB5F20 AB13 IO243PB5F22 AJ8 IO200NB4F18 AH19 IO222PB5F20 AC14 IO244NB5F22 AK6 IO200PB4F18 AH20 IO223NB5F21 AJ12 IO244PB5F22 AK7 IO201NB4F18 AK19 IO223PB5F21 AJ13 IO245NB5F23 AF8 R ev i si o n 1 8 3- 65 Package Pin Assignments FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO245PB5F23 AG8 IO263NB6F24 AD3 IO281PB6F26 Y2 IO246NB5F23 AD8 IO263PB6F24 AE3 IO282NB6F26 V5 IO246PB5F23 AD9 IO264NB6F24 AB6 IO282PB6F26 W5 IO247NB5F23 AG7 IO264PB6F24 AC6 IO284NB6F26 V7 IO247PB5F23 AH7 IO265NB6F24 AD1 IO284PB6F26 V6 IO248NB5F23 AK5 IO265PB6F24 AE1 IO285NB6F26 W3 IO249NB5F23 AJ5 IO266NB6F24 AA8 IO285PB6F26 W4 IO249PB5F23 AJ6 IO266PB6F24 AB8 IO286NB6F26 U8 IO250NB5F23 AC8 IO267NB6F25 AB5 IO286PB6F26 U9 IO250PB5F23 AC9 IO267PB6F25 AC5 IO287NB6F26 W1 IO251NB5F23 AH6 IO268NB6F25 AB3 IO287PB6F26 W2 IO251PB5F23 AG6 IO268PB6F25 AC3 IO288NB6F26 U7 IO252NB5F23 AF6 IO269NB6F25 AC2 IO288PB6F26 U6 IO252PB5F23 AF7 IO269PB6F25 AD2 IO290NB6F27 U4 IO253NB5F23 AG2 IO270NB6F25 Y7 IO290PB6F27 V4 IO253PB5F23 AG1 IO270PB6F25 AA7 IO291NB6F27 U3 IO254NB5F23 AE7 IO271NB6F25 AA4 IO291PB6F27 V3 IO254PB5F23 AE8 IO271PB6F25 AB4 IO292NB6F27 T5 IO255NB5F23 AG5 IO272NB6F25 Y6 IO292PB6F27 U5 IO255PB5F23 AH5 IO272PB6F25 AA6 IO293NB6F27 U2 IO256NB5F23 AJ4 IO273NB6F25 AB1* IO293PB6F27 V2 IO256PB5F23 AK4 IO273PB6F25 AE2* IO294NB6F27 T8 IO274NB6F25 W8 IO294PB6F27 T9 Bank 6 3- 66 IO257NB6F24 AE4 IO274PB6F25 Y8 IO296NB6F27 T1 IO257PB6F24 AF4 IO275NB6F25 Y5 IO296PB6F27 U1 IO258NB6F24 AB7 IO275PB6F25 AA5 IO298NB6F27 T7 IO258PB6F24 AC7 IO277NB6F25 AA2 IO298PB6F27 T6 IO259NB6F24 AD5 IO277PB6F25 AA1 IO299NB6F27 R2 IO259PB6F24 AE5 IO278NB6F26 W6 IO299PB6F27 T2 IO260NB6F24 AF1 IO278PB6F26 W7 IO260PB6F24 AF2 IO279NB6F26 Y3 IO300NB7F28 R8 IO261NB6F24 AF3 IO279PB6F26 Y4 IO300PB7F28 R9 IO261PB6F24 AG3 IO280NB6F26 V8 IO302NB7F28 R4 IO262NB6F24 AC4 IO280PB6F26 V9 IO302PB7F28 R5 IO262PB6F24 AD4 IO281NB6F26 Y1 IO303NB7F28 P1 R ev i sio n 1 8 Bank 7 Axcelerator Family FPGAs FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO303PB7F28 R1 IO324NB7F30 K5 GND A13 IO304NB7F28 R7 IO324PB7F30 L5 GND A18 IO304PB7F28 R6 IO326NB7F30 G1* GND A2 IO306NB7F28 N2 IO326PB7F30 K2* GND A23 IO306PB7F28 P2 IO327NB7F30 J4 GND A29 IO307NB7F28 N3 IO327PB7F30 J3 GND A8 IO307PB7F28 P3 IO328NB7F30 L8 GND AA10 IO308NB7F28 P9 IO328PB7F30 L7 GND AA21 IO308PB7F28 P8 IO329NB7F30 G2 GND AA28 IO309NB7F28 P4 IO329PB7F30 H2 GND AA3 IO309PB7F28 P5 IO330NB7F30 G3 GND AB2 IO310NB7F29 P7 IO330PB7F30 H3 GND AB22 IO310PB7F29 P6 IO331NB7F30 K8 GND AB29 IO311NB7F29 L1 IO331PB7F30 K7 GND AB9 IO311PB7F29 M1 IO332NB7F31 J6 GND AC1 IO312NB7F29 M5 IO332PB7F31 K6 GND AC30 IO312PB7F29 N5 IO333NB7F31 D1 GND AE25 IO313NB7F29 M4 IO333PB7F31 D2 GND AE6 IO313PB7F29 N4 IO334NB7F31 G4 GND AF26 IO315NB7F29 L2 IO334PB7F31 H4 GND AF5 IO315PB7F29 M2 IO335NB7F31 F2 GND AG27 IO316NB7F29 N7 IO335PB7F31 F1 GND AG4 IO316PB7F29 N6 IO336NB7F31 H5 GND AH10 IO317NB7F29 L3 IO336PB7F31 J5 GND AH15 IO317PB7F29 M3 IO337NB7F31 E2 GND AH16 IO318NB7F29 N8 IO337PB7F31 E1 GND AH21 IO318PB7F29 N9 IO338NB7F31 H7 GND AH28 IO320NB7F29 L6 IO338PB7F31 J7 GND AH3 IO320PB7F29 M6 IO339NB7F31 F4 GND AJ1 IO321NB7F30 K4 IO339PB7F31 F3 GND AJ2 IO321PB7F30 L4 IO340NB7F31 F5 GND AJ22 IO322NB7F30 M8 IO340PB7F31 G5 GND AJ29 IO322PB7F30 M7 IO341NB7F31 G6 GND AJ30 IO323NB7F30 J1 IO341PB7F31 H6 GND AJ9 IO323PB7F30 K1 GND AK13 Dedicated I/O R ev i si o n 1 8 3- 67 Package Pin Assignments FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND AK18 GND M13 GND T12 GND AK2 GND M14 GND T13 GND AK23 GND M15 GND T14 GND AK29 GND M16 GND T15 GND AK8 GND M17 GND T16 GND B1 GND M18 GND T17 GND B2 GND M19 GND T18 GND B22 GND N1 GND T19 GND B29 GND N12 GND T28 GND B30 GND N13 GND T3 GND B9 GND N14 GND U12 GND C10 GND N15 GND U13 GND C15 GND N16 GND U14 GND C16 GND N17 GND U15 GND C21 GND N18 GND U16 GND C28 GND N19 GND U17 GND C3 GND N30 GND U18 GND D27 GND P12 GND U19 GND D28 GND P13 GND V1 GND D4 GND P14 GND V12 GND E26 GND P15 GND V13 GND E5 GND P16 GND V14 GND H1 GND P17 GND V15 GND H30 GND P18 GND V16 GND J2 GND P19 GND V17 GND J22 GND R12 GND V18 GND J29 GND R13 GND V19 GND J9 GND R14 GND V30 GND K10 GND R15 GND W12 GND K21 GND R16 GND W13 GND K28 GND R17 GND W14 GND K3 GND R18 GND W15 GND L11 GND R19 GND W16 GND L20 GND R28 GND W17 GND M12 GND R3 GND W18 3- 68 R ev i sio n 1 8 Axcelerator Family FPGAs FG896 FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND W19 VCCA U11 VCCDA G16 GND Y11 VCCA U20 VCCDA T25 GND Y20 VCCA V11 VCCDA T4 GND/LP E4 VCCA V20 VCCIB0 A3 PRA G15 VCCA W11 VCCIB0 B3 PRB D16 VCCA W20 VCCIB0 J10 PRC AB16 VCCA Y12 VCCIB0 J11 PRD AF16 VCCA Y13 VCCIB0 J12 TCK G7 VCCA Y14 VCCIB0 K11 TDI D5 VCCA Y15 VCCIB0 K12 TDO J8 VCCA Y16 VCCIB0 K13 TMS F6 VCCA Y17 VCCIB0 K14 TRST C4 VCCA Y18 VCCIB0 K15 VCCA AD6 VCCA Y19 VCCIB1 A28 VCCA AH26 VCCDA AD24 VCCIB1 B28 VCCA E28 VCCDA AD7 VCCIB1 J19 VCCA E3 VCCDA AE15 VCCIB1 J20 VCCA L12 VCCDA AE16 VCCIB1 J21 VCCA L13 VCCDA AF12 VCCIB1 K16 VCCA L14 VCCDA AF13 VCCIB1 K17 VCCA L15 VCCDA AF15 VCCIB1 K18 VCCA L16 VCCDA AF18 VCCIB1 K19 VCCA L17 VCCDA AF19 VCCIB1 K20 VCCA L18 VCCDA AH27 VCCIB2 C29 VCCA L19 VCCDA AH4 VCCIB2 C30 VCCA M11 VCCDA C13 VCCIB2 K22 VCCA M20 VCCDA C27 VCCIB2 L21 VCCA N11 VCCDA C5 VCCIB2 L22 VCCA N20 VCCDA D13 VCCIB2 M21 VCCA P11 VCCDA D19 VCCIB2 M22 VCCA P20 VCCDA D3 VCCIB2 N21 VCCA R11 VCCDA E18 VCCIB2 P21 VCCA R20 VCCDA F15 VCCIB2 R21 VCCA T11 VCCDA F16 VCCIB3 AA22 VCCA T20 VCCDA F26 VCCIB3 AH29 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev i si o n 1 8 3- 69 Package Pin Assignments FG896 FG896 AX2000 Function Pin Number AX2000 Function Pin Number VCCIB3 AH30 VCCIB6 W9 VCCIB3 T21 VCCIB6 Y10 VCCIB3 U21 VCCIB6 Y9 VCCIB3 V21 VCCIB7 C1 VCCIB3 W21 VCCIB7 C2 VCCIB3 W22 VCCIB7 K9 VCCIB3 Y21 VCCIB7 L10 VCCIB3 Y22 VCCIB7 L9 VCCIB4 AA16 VCCIB7 M10 VCCIB4 AA17 VCCIB7 M9 VCCIB4 AA18 VCCIB7 N10 VCCIB4 AA19 VCCIB7 P10 VCCIB4 AA20 VCCIB7 R10 VCCIB4 AB19 VCCPLA G14 VCCIB4 AB20 VCCPLB H15 VCCIB4 AB21 VCCPLC G17 VCCIB4 AJ28 VCCPLD J16 VCCIB4 AK28 VCCPLE AH17 VCCIB5 AA11 VCCPLF AC16 VCCIB5 AA12 VCCPLG AH14 VCCIB5 AA13 VCCPLH AD15 VCCIB5 AA14 VCOMPLA F14 VCCIB5 AA15 VCOMPLB J15 VCCIB5 AB10 VCOMPLC F17 VCCIB5 AB11 VCOMPLD H16 VCCIB5 AB12 VCOMPLE AF17 VCCIB5 AJ3 VCOMPLF AD16 VCCIB5 AK3 VCOMPLG AF14 VCCIB6 AA9 VCOMPLH AB15 VCCIB6 AH1 VPUMP G24 VCCIB6 AH2 VCCIB6 T10 VCCIB6 U10 VCCIB6 V10 VCCIB6 W10 3- 70 R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 A1 Ball Pad Corner 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3- 71 Package Pin Assignments FG1152 AX2000 Function FG1152 Pin Number Bank 0 3- 72 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number IO17NB0F1 F12 IO34PB0F3 D14 IO00NB0F0 D6 IO17PB0F1 F11 IO35NB0F3 A15 IO00PB0F0 C6 IO18NB0F1 E11 IO35PB0F3 B15 IO01NB0F0 H10 IO18PB0F1 E10 IO36NB0F3 B16 IO01PB0F0 H9 IO19NB0F1 F13 IO36PB0F3 A16 IO02NB0F0 F8 IO19PB0F1 G13 IO37NB0F3 G16 IO02PB0F0 G8 IO20NB0F1 A10 IO37PB0F3 G15 IO03NB0F0 A6 IO20PB0F1 A9 IO38NB0F3 D16 IO03PB0F0 B6 IO21NB0F1 K14 IO38PB0F3 C16 IO04NB0F0 C7 IO21PB0F1 K13 IO39NB0F3 K16 IO04PB0F0 D7 IO22NB0F2 B11 IO39PB0F3 L16 IO05NB0F0 K10 IO22PB0F2 B10 IO40NB0F3 D17 IO05PB0F0 J10 IO23NB0F2 C12 IO40PB0F3 C17 IO06NB0F0 F9 IO23PB0F2 C11 IO41NB0F3/HCLKAN E16 IO06PB0F0 G9 IO24NB0F2 A12 IO41PB0F3/HCLKAP F16 IO07NB0F0 F10 IO24PB0F2 A11 IO42NB0F3/HCLKBN G17 IO07PB0F0 G10 IO25NB0F2 H14 IO42PB0F3/HCLKBP F17 IO08NB0F0 E9 IO25PB0F2 J14 Bank 1 IO08PB0F0 E8 IO26NB0F2 D13 IO43NB1F4/HCLKCN G19 IO09NB0F0 J11 IO26PB0F2 D12 IO43PB1F4/HCLKCP G18 IO09PB0F0 K11 IO27NB0F2 F14 IO44NB1F4/HCLKDN E19 IO10NB0F0 C8 IO27PB0F2 G14 IO44PB1F4/HCLKDP F19 IO10PB0F0 D8 IO28NB0F2 E14 IO45NB1F4 C18 IO11NB0F0 K12 IO28PB0F2 E13 IO45PB1F4 D18 IO11PB0F0 J12 IO29NB0F2 B13 IO46NB1F4 A18 IO12NB0F1 G11 IO29PB0F2 B12 IO46PB1F4 B18 IO12PB0F1 H11 IO30NB0F2 C14 IO47NB1F4 K19 IO13NB0F1 G12 IO30PB0F2 C13 IO47PB1F4 L19 IO13PB0F1 H12 IO31NB0F2 H15 IO48NB1F4 C19 IO14NB0F1 A7 IO31PB0F2 J15 IO48PB1F4 D19 IO14PB0F1 B7 IO32NB0F2 A14 IO49NB1F4 K20 IO15NB0F1 H13 IO32PB0F2 B14 IO49PB1F4 L20 IO15PB0F1 J13 IO33NB0F2 K15 IO50NB1F4 A19 IO16NB0F1 C9 IO33PB0F2 L15 IO50PB1F4 B19 IO16PB0F1 D9 IO34NB0F3 D15 IO51NB1F4 H20 R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO51PB1F4 J20 IO69NB1F6 C27 IO86NB2F8 J28 IO52NB1F4 B20 IO69PB1F6 C26 IO86PB2F8 J27 IO52PB1F4 A20 IO70NB1F6 H24 IO87NB2F8 M25 IO53NB1F4 F20 IO70PB1F6 G24 IO87PB2F8 L25 IO53PB1F4 E20 IO71NB1F6 H23 IO88NB2F8 L26 IO54NB1F5 B21 IO71PB1F6 G23 IO88PB2F8 K26 IO54PB1F5 A21 IO72NB1F6 B28 IO89NB2F8 G31 IO55NB1F5 K21 IO72PB1F6 A28 IO89PB2F8 F31 IO55PB1F5 J21 IO73NB1F6 E26 IO90NB2F8 H29 IO56NB1F5 D21 IO73PB1F6 E25 IO90PB2F8 G29 IO56PB1F5 C21 IO74NB1F6 F26 IO91NB2F8 K28 IO57NB1F5 G22 IO74PB1F6 F25 IO91PB2F8 K27 IO57PB1F5 G21 IO75NB1F6 K25 IO92NB2F8 J30 IO58NB1F5 E22 IO75PB1F6 K24 IO92PB2F8 H30 IO58PB1F5 E21 IO76NB1F7 D27 IO93NB2F8 L28 IO59NB1F5 D22 IO76PB1F7 D26 IO93PB2F8 L27 IO59PB1F5 C22 IO77NB1F7 B29 IO94NB2F8 K29 IO60NB1F5 B23 IO77PB1F7 A29 IO94PB2F8 J29 IO60PB1F5 A23 IO78NB1F7 D28 IO95NB2F8 K31 IO61NB1F5 H22 IO78PB1F7 C28 IO95PB2F8 J31 IO61PB1F5 H21 IO79NB1F7 H25 IO96NB2F9 J32 IO62NB1F5 C24 IO79PB1F7 G25 IO96PB2F9 H32 IO62PB1F5 C23 IO80NB1F7 F27 IO97NB2F9 M27 IO63NB1F5 F23 IO80PB1F7 E27 IO97PB2F9 M26 IO63PB1F5 F22 IO81NB1F7 J25 IO98NB2F9 L30 IO64NB1F6 B24 IO81PB1F7 J24 IO98PB2F9 K30 IO64PB1F6 A24 IO82NB1F7 D29 IO99NB2F9 N25 IO65NB1F6 J22 IO82PB1F7 C29 IO99PB2F9 N26 IO65PB1F6 K22 IO83NB1F7 H26 IO100NB2F9 M29 IO66NB1F6 B25 IO83PB1F7 G26 IO100PB2F9 L29 IO66PB1F6 A25 IO84NB1F7 F28 IO101NB2F9 L33 IO67NB1F6 K23 IO84PB1F7 E28 IO101PB2F9 L32 IO67PB1F6 J23 IO85NB1F7 H27 IO102NB2F9 K34 IO68NB1F6 F24 IO85PB1F7 G27 IO102PB2F9 K33 IO68PB1F6 E24 IO103NB2F9 N28 Bank 2 R ev i si o n 1 8 3- 73 Package Pin Assignments FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO103PB2F9 M28 IO121NB2F11 T27 IO138NB3F12 Y29 IO104NB2F9 M34 IO121PB2F11 T26 IO138PB3F12 W29 IO104PB2F9 L34 IO122NB2F11 T30 IO139NB3F13 Y27 IO105NB2F9 P27 IO122PB2F11 T29 IO139PB3F13 W27 IO105PB2F9 N27 IO123NB2F11 U28 IO140NB3F13 AA33 IO106NB2F9 M32 IO123PB2F11 T28 IO140PB3F13 Y33 IO106PB2F9 M31 IO124NB2F11 T31 IO141NB3F13 Y25 IO107NB2F10 P25 IO124PB2F11 T32 IO141PB3F13 Y24 IO107PB2F10 P26 IO125NB2F11 U24 IO142NB3F13 AA31 IO108NB2F10 N33 IO125PB2F11 U25 IO142PB3F13 Y31 IO108PB2F10 M33 IO126NB2F11 U33 IO143NB3F13 AA28 IO109NB2F10 P29 IO126PB2F11 U34 IO143PB3F13 Y28 IO109PB2F10 N29 IO127NB2F11 U26 IO144NB3F13 AA34 IO110NB2F10 P30 IO127PB2F11 U27 IO144PB3F13 Y34 IO110PB2F10 N30 IO128NB2F11 U31 IO145NB3F13 AA26 IO111NB2F10 R24 IO128PB2F11 U32 IO145PB3F13 Y26 IO111PB2F10 R25 IO146NB3F13 AA29 IO112NB2F10 P31 IO129NB3F12 V29 IO146PB3F13 AA30 IO112PB2F10 N31 IO129PB3F12 U29 IO147NB3F13 AB30 IO113NB2F10 R28 IO130NB3F12 V31 IO147PB3F13 AB29 IO113PB2F10 P28 IO130PB3F12 V32 IO148NB3F13 AB32 IO114NB2F10 P32 IO131NB3F12 V24 IO148PB3F13 AA32 IO114PB2F10 N32 IO131PB3F12 V25 IO149NB3F13 AB27 IO115NB2F10 R30 IO132NB3F12 W28 IO149PB3F13 AA27 IO115PB2F10 R29 IO132PB3F12 V28 IO150NB3F14 AC31 IO116NB2F10 P34 IO133NB3F12 W26 IO150PB3F14 AB31 IO116PB2F10 P33 IO133PB3F12 V26 IO151NB3F14 AD33 IO117NB2F10 R27 IO134NB3F12 W33 IO151PB3F14 AC33 IO117PB2F10 R26 IO134PB3F12 V33 IO152NB3F14 AC28 IO118NB2F11 R34 IO135NB3F12 W25 IO152PB3F14 AB28 IO118PB2F11 R33 IO135PB3F12 W24 IO153NB3F14 AB25 IO119NB2F11 T24 IO136NB3F12 W31 IO153PB3F14 AA25 IO119PB2F11 T25 IO136PB3F12 W32 IO154NB3F14 AD32 IO120NB2F11 T33 IO137NB3F12 Y30 IO154PB3F14 AC32 IO120PB2F11 T34 IO137PB3F12 W30 IO155NB3F14 AD29 3- 74 Bank 3 R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO155PB3F14 AC29 IO172PB4F16 AH27 IO190NB4F17 AH22 IO156NB3F14 AE30 IO173NB4F16 AJ27 IO190PB4F17 AH23 IO156PB3F14 AD30 IO173PB4F16 AJ28 IO191NB4F17 AJ23 IO157NB3F14 AC26 IO174NB4F16 AL27 IO191PB4F17 AJ24 IO157PB3F14 AB26 IO174PB4F16 AL28 IO192NB4F17 AG21 IO158NB3F14 AH33 IO175NB4F16 AM28 IO192PB4F17 AG22 IO158PB3F14 AG33 IO175PB4F16 AM29 IO193NB4F18 AP23 IO159NB3F14 AD27 IO176NB4F16 AG25 IO193PB4F18 AP24 IO159PB3F14 AC27 IO176PB4F16 AG26 IO194NB4F18 AN22 IO160NB3F14 AG32 IO177NB4F16 AK26 IO194PB4F18 AN23 IO160PB3F14 AF32 IO177PB4F16 AK27 IO195NB4F18 AM23 IO161NB3F15 AG31 IO178NB4F16 AF25 IO195PB4F18 AL23 IO161PB3F15 AF31 IO178PB4F16 AE25 IO196NB4F18 AF21 IO162NB3F15 AF29 IO179NB4F16 AP28 IO196PB4F18 AF22 IO162PB3F15 AE29 IO179PB4F16 AN28 IO197NB4F18 AL22 IO163NB3F15 AE28 IO180NB4F16 AJ25 IO197PB4F18 AM22 IO163PB3F15 AD28 IO180PB4F16 AJ26 IO198NB4F18 AE21 IO164NB3F15 AG30 IO181NB4F17 AM26 IO198PB4F18 AE22 IO164PB3F15 AF30 IO181PB4F17 AM27 IO199NB4F18 AJ21 IO165NB3F15 AE26 IO182NB4F17 AF24 IO199PB4F18 AJ22 IO165PB3F15 AD26 IO182PB4F17 AE24 IO200NB4F18 AK21 IO166NB3F15 AJ30 IO183NB4F17 AH24 IO200PB4F18 AK22 IO166PB3F15 AH30 IO183PB4F17 AH25 IO201NB4F18 AM21 IO167NB3F15 AG28 IO184NB4F17 AG23 IO201PB4F18 AL21 IO167PB3F15 AF28 IO184PB4F17 AG24 IO202NB4F18 AE20 IO168NB3F15 AF27 IO185NB4F17 AL25 IO202PB4F18 AD20 IO168PB3F15 AE27 IO185PB4F17 AL26 IO203NB4F19 AN21 IO169NB3F15 AH29 IO186NB4F17 AP25 IO203PB4F19 AP21 IO169PB3F15 AG29 IO186PB4F17 AP26 IO204NB4F19 AP20 IO170NB3F15 AD25 IO187NB4F17 AK24 IO204PB4F19 AN20 IO170PB3F15 AC25 IO187PB4F17 AK25 IO205NB4F19 AN19 IO188NB4F17 AF23 IO205PB4F19 AP19 Bank 4 IO171NB4F16 AP29 IO188PB4F17 AE23 IO206NB4F19 AG20 IO171PB4F16 AN29 IO189NB4F17 AN24 IO206PB4F19 AF20 IO172NB4F16 AH26 IO189PB4F17 AM24 IO207NB4F19 AL19 R ev i si o n 1 8 3- 75 Package Pin Assignments FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO207PB4F19 AL20 IO224PB5F21 AP14 IO242NB5F22 AG11 IO208NB4F19 AG19 IO225NB5F21 AK13 IO242PB5F22 AG12 IO208PB4F19 AF19 IO225PB5F21 AK14 IO243NB5F22 AL9 IO209NB4F19 AN18 IO226NB5F21 AE15 IO243PB5F22 AL10 IO209PB4F19 AP18 IO226PB5F21 AF15 IO244NB5F22 AM8 IO210NB4F19 AE19 IO227NB5F21 AG14 IO244PB5F22 AM9 IO210PB4F19 AD19 IO227PB5F21 AG15 IO245NB5F23 AH10 IO211NB4F19 AL18 IO228NB5F21 AJ13 IO245PB5F23 AJ10 IO211PB4F19 AM18 IO228PB5F21 AJ14 IO246NB5F23 AF10 IO212NB4F19/CLKEN AJ20 IO229NB5F21 AM13 IO246PB5F23 AF11 IO212PB4F19/CLKEP AK20 IO229PB5F21 AM14 IO247NB5F23 AJ9 IO213NB4F19/CLKFN AJ18 IO230NB5F21 AE14 IO247PB5F23 AK9 IO213PB4F19/CLKFP AJ19 IO230PB5F21 AF14 IO248NB5F23 AN7 IO231NB5F21 AN12 IO248PB5F23 AP7 Bank 5 IO214NB5F20/CLKGN AJ16 IO231PB5F21 AP12 IO249NB5F23 AL7 IO214PB5F20/CLKGP AJ17 IO232NB5F21 AG13 IO249PB5F23 AL8 IO215NB5F20/CLKHN AJ15 IO232PB5F21 AH13 IO250NB5F23 AE10 IO215PB5F20/CLKHP AK15 IO233NB5F21 AL12 IO250PB5F23 AE11 IO216NB5F20 AD16 IO233PB5F21 AL13 IO251NB5F23 AK8 IO216PB5F20 AE17 IO234NB5F21 AE13 IO251PB5F23 AJ8 IO217NB5F20 AM17 IO234PB5F21 AF13 IO252NB5F23 AH8 IO217PB5F20 AL17 IO235NB5F22 AN11 IO252PB5F23 AH9 IO218NB5F20 AG16 IO235PB5F22 AP11 IO253NB5F23 AN6 IO218PB5F20 AF16 IO236NB5F22 AM11 IO253PB5F23 AP6 IO219NB5F20 AM16 IO236PB5F22 AM12 IO254NB5F23 AG9 IO219PB5F20 AL16 IO237NB5F22 AJ11 IO254PB5F23 AG10 IO220NB5F20 AP16 IO237PB5F22 AJ12 IO255NB5F23 AJ7 IO220PB5F20 AN16 IO238NB5F22 AH11 IO255PB5F23 AK7 IO221NB5F20 AN15 IO238PB5F22 AH12 IO256NB5F23 AL6 IO221PB5F20 AP15 IO239NB5F22 AK10 IO256PB5F23 AM6 IO222NB5F20 AD15 IO239PB5F22 AK11 IO222PB5F20 AE16 IO240NB5F22 AE12 IO257NB6F24 AG6 IO223NB5F21 AL14 IO240PB5F22 AF12 IO257PB6F24 AH6 IO223PB5F21 AL15 IO241NB5F22 AN10 IO258NB6F24 AD9 IO224NB5F21 AN14 IO241PB5F22 AP10 IO258PB6F24 AE9 3- 76 R ev i sio n 1 8 Bank 6 Axcelerator Family FPGAs FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO259NB6F24 AF7 IO276PB6F25 AD2 IO294NB6F27 V10 IO259PB6F24 AG7 IO277NB6F25 AC4 IO294PB6F27 V11 IO260NB6F24 AH3 IO277PB6F25 AC3 IO295NB6F27 Y1 IO260PB6F24 AH4 IO278NB6F26 AA8 IO295PB6F27 Y2 IO261NB6F24 AH5 IO278PB6F26 AA9 IO296NB6F27 W1 IO261PB6F24 AJ5 IO279NB6F26 AB5 IO296PB6F27 W2 IO262NB6F24 AE6 IO279PB6F26 AB6 IO297NB6F27 V1 IO262PB6F24 AF6 IO280NB6F26 Y10 IO297PB6F27 V2 IO263NB6F24 AF5 IO280PB6F26 Y11 IO298NB6F27 V9 IO263PB6F24 AG5 IO281NB6F26 AB3 IO298PB6F27 V8 IO264NB6F24 AD8 IO281PB6F26 AB4 IO299NB6F27 U4 IO264PB6F24 AE8 IO282NB6F26 Y7 IO299PB6F27 V4 IO265NB6F24 AF3 IO282PB6F26 AA7 IO265PB6F24 AG3 IO283NB6F26 AC2 IO300NB7F28 U10 IO266NB6F24 AC10 IO283PB6F26 AC1 IO300PB7F28 U11 IO266PB6F24 AD10 IO284NB6F26 Y9 IO301NB7F28 U2 IO267NB6F25 AD7 IO284PB6F26 Y8 IO301PB7F28 U1 IO267PB6F25 AE7 IO285NB6F26 AA5 IO302NB7F28 U6 IO268NB6F25 AD5 IO285PB6F26 AA6 IO302PB7F28 U7 IO268PB6F25 AE5 IO286NB6F26 W10 IO303NB7F28 T3 IO269NB6F25 AE4 IO286PB6F26 W11 IO303PB7F28 U3 IO269PB6F25 AF4 IO287NB6F26 AA3 IO304NB7F28 U9 IO270NB6F25 AB9 IO287PB6F26 AA4 IO304PB7F28 U8 IO270PB6F25 AC9 IO288NB6F26 W9 IO305NB7F28 R2 IO271NB6F25 AC6 IO288PB6F26 W8 IO305PB7F28 R1 IO271PB6F25 AD6 IO289NB6F27 AA1 IO306NB7F28 R4 IO272NB6F25 AB8 IO289PB6F27 AA2 IO306PB7F28 T4 IO272PB6F25 AC8 IO290NB6F27 W6 IO307NB7F28 R5 IO273NB6F25 AE1 IO290PB6F27 Y6 IO307PB7F28 T5 IO273PB6F25 AE2 IO291NB6F27 W5 IO308NB7F28 T11 IO274NB6F25 AA10 IO291PB6F27 Y5 IO308PB7F28 T10 IO274PB6F25 AB10 IO292NB6F27 V7 IO309NB7F28 T6 IO275NB6F25 AB7 IO292PB6F27 W7 IO309PB7F28 T7 IO275PB6F25 AC7 IO293NB6F27 W4 IO310NB7F29 T9 IO276NB6F25 AD1 IO293PB6F27 Y4 IO310PB7F29 T8 R ev i si o n 1 8 Bank 7 3- 77 Package Pin Assignments FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO311NB7F29 N3 IO328PB7F30 N9 GND A33 IO311PB7F29 P3 IO329NB7F30 J4 GND A4 IO312NB7F29 P7 IO329PB7F30 K4 GND A8 IO312PB7F29 R7 IO330NB7F30 J5 GND AA14 IO313NB7F29 P6 IO330PB7F30 K5 GND AA15 IO313PB7F29 R6 IO331NB7F30 M10 GND AA16 IO314NB7F29 M2 IO331PB7F30 M9 GND AA17 IO314PB7F29 N2 IO332NB7F31 L8 GND AA18 IO315NB7F29 N4 IO332PB7F31 M8 GND AA19 IO315PB7F29 P4 IO333NB7F31 F2 GND AA20 IO316NB7F29 R9 IO333PB7F31 F1 GND AA21 IO316PB7F29 R8 IO334NB7F31 J6 GND AB1 IO317NB7F29 N5 IO334PB7F31 K6 GND AB13 IO317PB7F29 P5 IO335NB7F31 H4 GND AB22 IO318NB7F29 R10 IO335PB7F31 H3 GND AB34 IO318PB7F29 R11 IO336NB7F31 K7 GND AC12 IO319NB7F29 L2 IO336PB7F31 L7 GND AC23 IO319PB7F29 L1 IO337NB7F31 G4 GND AC30 IO320NB7F29 N8 IO337PB7F31 G3 GND AC5 IO320PB7F29 P8 IO338NB7F31 K9 GND AD11 IO321NB7F30 M6 IO338PB7F31 L9 GND AD24 IO321PB7F30 N6 IO339NB7F31 H6 GND AD31 IO322NB7F30 P10 IO339PB7F31 H5 GND AD4 IO322PB7F30 P9 IO340NB7F31 H7 GND AE3 IO323NB7F30 L3 IO340PB7F31 J7 GND AE32 IO323PB7F30 M3 IO341NB7F31 J8 GND AF2 IO324NB7F30 M7 IO341PB7F31 K8 GND AF33 IO324PB7F30 N7 GND AG1 IO325NB7F30 K2 GND A13 GND AG27 IO325PB7F30 K1 GND A2 GND AG34 IO326NB7F30 G2 GND A22 GND AG8 IO326PB7F30 H2 GND A27 GND AH28 IO327NB7F30 L6 GND A3 GND AH7 IO327PB7F30 L5 GND A31 GND AJ29 IO328NB7F30 N10 GND A32 GND AJ6 3- 78 Dedicated I/O R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND AK12 GND AN34 GND D1 GND AK17 GND AN4 GND D11 GND AK18 GND AN9 GND D2 GND AK23 GND AP13 GND D24 GND AK30 GND AP2 GND D3 GND AK5 GND AP22 GND D31 GND AL1 GND AP27 GND D32 GND AL11 GND AP3 GND D33 GND AL2 GND AP31 GND D34 GND AL24 GND AP32 GND D4 GND AL3 GND AP33 GND E12 GND AL31 GND AP4 GND E17 GND AL32 GND AP8 GND E18 GND AL33 GND B1 GND E23 GND AL34 GND B2 GND E30 GND AL4 GND B26 GND E5 GND AM1 GND B3 GND F29 GND AM10 GND B31 GND F30 GND AM15 GND B32 GND F6 GND AM2 GND B33 GND G28 GND AM20 GND B34 GND G7 GND AM25 GND B4 GND H1 GND AM3 GND B9 GND H34 GND AM31 GND C1 GND J2 GND AM32 GND C10 GND J33 GND AM33 GND C15 GND K3 GND AM34 GND C2 GND K32 GND AM4 GND C20 GND L11 GND AN1 GND C25 GND L24 GND AN2 GND C3 GND L31 GND AN26 GND C31 GND L4 GND AN3 GND C32 GND M12 GND AN31 GND C33 GND M23 GND AN32 GND C34 GND M30 GND AN33 GND C4 GND M5 R ev i si o n 1 8 3- 79 Package Pin Assignments FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND N1 GND U19 NC A26 GND N13 GND U20 NC AB2 GND N22 GND U21 NC AB33 GND N34 GND U30 NC AC34 GND P14 GND U5 NC AD3 GND P15 GND V14 NC AD34 GND P16 GND V15 NC AE31 GND P17 GND V16 NC AE33 GND P18 GND V17 NC AE34 GND P19 GND V18 NC AF1 GND P20 GND V19 NC AF34 GND P21 GND V20 NC AG2 GND R14 GND V21 NC AG4 GND R15 GND V30 NC AH1 GND R16 GND V5 NC AH2 GND R17 GND W14 NC AH31 GND R18 GND W15 NC AH32 GND R19 GND W16 NC AH34 GND R20 GND W17 NC AJ1 GND R21 GND W18 NC AJ2 GND R3 GND W19 NC AJ3 GND R32 GND W20 NC AJ31 GND T14 GND W21 NC AJ32 GND T15 GND Y14 NC AJ33 GND T16 GND Y15 NC AJ34 GND T17 GND Y16 NC AJ4 GND T18 GND Y17 NC AL29 GND T19 GND Y18 NC AM19 GND T20 GND Y19 NC AM7 GND T21 GND Y20 NC AN13 GND U14 GND Y21 NC AN17 GND U15 GND Y3 NC AN25 GND U16 GND Y32 NC AN27 GND U17 GND/LP G6 NC AN8 GND U18 NC A17 NC AP17 3- 80 R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number NC AP9 PRB F18 VCCA T22 NC B17 PRC AD18 VCCA U13 NC B22 PRD AH18 VCCA U22 NC B27 TCK J9 VCCA V13 NC B8 TDI F7 VCCA V22 NC D10 TDO L10 VCCA W13 NC D20 TMS H8 VCCA W22 NC D23 TRST E6 VCCA Y13 NC D25 VCCA AA13 VCCA Y22 NC F3 VCCA AA22 VCCDA AF26 NC F32 VCCA AB14 VCCDA AF9 NC F33 VCCA AB15 VCCDA AG17 NC F34 VCCA AB16 VCCDA AG18 NC F4 VCCA AB17 VCCDA AH14 NC G1 VCCA AB18 VCCDA AH15 NC G32 VCCA AB19 VCCDA AH17 NC G33 VCCA AB20 VCCDA AH20 NC G34 VCCA AB21 VCCDA AH21 NC H31 VCCA AF8 VCCDA AK29 NC H33 VCCA AK28 VCCDA AK6 NC J1 VCCA G30 VCCDA E15 NC J3 VCCA G5 VCCDA E29 NC J34 VCCA N14 VCCDA E7 NC M1 VCCA N15 VCCDA F15 NC M4 VCCA N16 VCCDA F21 NC P1 VCCA N17 VCCDA F5 NC P2 VCCA N18 VCCDA G20 NC R31 VCCA N19 VCCDA H17 NC T1 VCCA N20 VCCDA H18 NC T2 VCCA N21 VCCDA H28 NC V3 VCCA P13 VCCDA J18 NC V34 VCCA P22 VCCDA V27 NC W3 VCCA R13 VCCDA V6 NC W34 VCCA R22 VCCIB0 A5 PRA J17 VCCA T13 VCCIB0 B5 R ev i si o n 1 8 3- 81 Package Pin Assignments FG1152 FG1152 FG1152 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number VCCIB0 C5 VCCIB3 AA24 VCCIB6 AA11 VCCIB0 D5 VCCIB3 AB23 VCCIB6 AA12 VCCIB0 L12 VCCIB3 AB24 VCCIB6 AB11 VCCIB0 L13 VCCIB3 AC24 VCCIB6 AB12 VCCIB0 L14 VCCIB3 AK31 VCCIB6 AC11 VCCIB0 M13 VCCIB3 AK32 VCCIB6 AK1 VCCIB0 M14 VCCIB3 AK33 VCCIB6 AK2 VCCIB0 M15 VCCIB3 AK34 VCCIB6 AK3 VCCIB0 M16 VCCIB3 V23 VCCIB6 AK4 VCCIB0 M17 VCCIB3 W23 VCCIB6 V12 VCCIB1 A30 VCCIB3 Y23 VCCIB6 W12 VCCIB1 B30 VCCIB4 AC18 VCCIB6 Y12 VCCIB1 C30 VCCIB4 AC19 VCCIB7 E1 VCCIB1 D30 VCCIB4 AC20 VCCIB7 E2 VCCIB1 L21 VCCIB4 AC21 VCCIB7 E3 VCCIB1 L22 VCCIB4 AC22 VCCIB7 E4 VCCIB1 L23 VCCIB4 AD21 VCCIB7 M11 VCCIB1 M18 VCCIB4 AD22 VCCIB7 N11 VCCIB1 M19 VCCIB4 AD23 VCCIB7 N12 VCCIB1 M20 VCCIB4 AL30 VCCIB7 P11 VCCIB1 M21 VCCIB4 AM30 VCCIB7 P12 VCCIB1 M22 VCCIB4 AN30 VCCIB7 R12 VCCIB2 E31 VCCIB4 AP30 VCCIB7 T12 VCCIB2 E32 VCCIB5 AC13 VCCIB7 U12 VCCIB2 E33 VCCIB5 AC14 VCCPLA J16 VCCIB2 E34 VCCIB5 AC15 VCCPLB K17 VCCIB2 M24 VCCIB5 AC16 VCCPLC J19 VCCIB2 N23 VCCIB5 AC17 VCCPLD L18 VCCIB2 N24 VCCIB5 AD12 VCCPLE AK19 VCCIB2 P23 VCCIB5 AD13 VCCPLF AE18 VCCIB2 P24 VCCIB5 AD14 VCCPLG AK16 VCCIB2 R23 VCCIB5 AL5 VCCPLH AF17 VCCIB2 T23 VCCIB5 AM5 VCOMPLA H16 VCCIB2 U23 VCCIB5 AN5 VCOMPLB L17 VCCIB3 AA23 VCCIB5 AP5 VCOMPLC H19 3- 82 R ev i sio n 1 8 Axcelerator Family FPGAs FG1152 AX2000 Function Pin Number VCOMPLD K18 VCOMPLE AH19 VCOMPLF AF18 VCOMPLG AH16 VCOMPLH AD17 VPUMP J26 R ev i si o n 1 8 3- 83 Package Pin Assignments PQ208 1 208 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. 3- 84 R ev i sio n 1 8 Axcelerator Family FPGAs PQ208 PQ208 AX250 Function Pin Number Bank 0 AX250 Function PQ208 Pin Number AX250 Function Pin Number IO43PB2F2 134 IO76PB5F5/CLKGP 77 IO02NB0F0 197 IO44NB2F2 131 IO77NB5F5/CLKHN 70 IO03NB0F0 198 IO44PB2F2 133 IO77PB5F5/CLKHP 71 IO03PB0F0 199 IO78NB5F5 66 IO12NB0F0/HCLKAN 191 IO45NB3F3 127 IO78PB5F5 67 IO12PB0F0/HCLKAP 192 IO45PB3F3 129 IO86NB5F5 62 IO13NB0F0/HCLKBN 185 IO46NB3F3 126 IO87NB5F5 60 IO13PB0F0/HCLKBP 186 IO46PB3F3 128 IO87PB5F5 61 IO48NB3F3 122 IO88NB5F5 56 Bank 1 Bank 3 IO14NB1F1/HCLKCN 180 IO48PB3F3 123 IO88PB5F5 57 IO14PB1F1/HCLKCP 181 IO50NB3F3 120 IO89NB5F5 54 IO15NB1F1/HCLKDN 174 IO50PB3F3 121 IO89PB5F5 55 IO15PB1F1/HCLKDP 175 IO55NB3F3 116 IO16NB1F1 170 IO55PB3F3 117 IO91NB6F6 47 IO16PB1F1 171 IO57NB3F3 114 IO91PB6F6 49 IO24NB1F1 165 IO57PB3F3 115 IO92NB6F6 48 IO24PB1F1 166 IO59NB3F3 110 IO92PB6F6 50 IO26NB1F1 161 IO59PB3F3 111 IO93NB6F6 42 IO26PB1F1 162 IO60NB3F3 108 IO93PB6F6 43 IO27NB1F1 159 IO60PB3F3 109 IO94PB6F6 44 IO27PB1F1 160 IO61NB3F3 106 IO96NB6F6 40 IO61PB3F3 107 IO96PB6F6 41 IO101NB6F6 35 Bank 2 Bank 6 IO29NB2F2 151 IO29PB2F2 153 IO62NB4F4 100 IO101PB6F6 36 IO30NB2F2 152 IO62PB4F4 103 IO102PB6F6 37 IO30PB2F2 154 IO63NB4F4 101 IO103NB6F6 33 IO31PB2F2 148 IO63PB4F4 102 IO103PB6F6 34 IO32NB2F2 146 IO64NB4F4 96 IO105NB6F6 28 IO32PB2F2 147 IO64PB4F4 97 IO105PB6F6 30 IO34NB2F2 144 IO72NB4F4 91 IO106NB6F6 27 IO34PB2F2 145 IO72PB4F4 92 IO106PB6F6 29 IO39NB2F2 139 IO74NB4F4/CLKEN 87 IO39PB2F2 140 IO74PB4F4/CLKEP 88 IO107NB7F7 23 IO40PB2F2 141 IO75NB4F4/CLKFN 81 IO107PB7F7 25 IO41NB2F2 137 IO75PB4F4/CLKFP 82 IO108NB7F7 22 IO41PB2F2 138 Bank 5 IO108PB7F7 24 IO43NB2F2 132 IO76NB5F5/CLKGN IO110NB7F7 18 Bank 4 R ev i si o n 1 8 76 Bank 7 3- 85 Package Pin Assignments PQ208 AX250 Function PQ208 Pin Number Pin Number AX250 Function Pin Number IO110PB7F7 19 GND 94 VCCPLB 187 IO112NB7F7 16 GND 99 VCCPLC 178 IO112PB7F7 17 GND 113 VCCPLD 176 IO117NB7F7 12 GND 119 VCCPLE 85 IO117PB7F7 13 GND 125 VCCPLF 83 IO119NB7F7 10 GND 136 VCCPLG 74 IO119PB7F7 11 GND 143 VCCPLH 72 IO121PB7F7 7 GND 150 VCCIB0 193 IO122NB7F7 5 GND 155 VCCIB0 200 IO122PB7F7 6 GND 164 VCCIB1 163 IO123NB7F7 3 GND 169 VCCIB1 172 IO123PB7F7 4 GND 173 VCCIB2 135 GND 194 VCCIB2 149 Dedicated I/O 3- 86 AX250 Function PQ208 VCCDA 1 GND 196 VCCIB3 112 VCCDA 26 GND 201 VCCIB3 124 VCCDA 53 GND/LP 208 VCCIB4 89 VCCDA 63 PRA 184 VCCIB4 98 VCCDA 78 PRB 183 VCCIB5 58 VCCDA 95 PRC 80 VCCIB5 68 VCCDA 105 PRD 79 VCCIB6 31 VCCDA 130 TCK 205 VCCIB6 45 VCCDA 157 TDI 204 VCCIB7 8 VCCDA 167 TDO 203 VCCIB7 20 VCCDA 182 TMS 206 VCOMPLA 190 VCCDA 202 TRST 207 VCOMPLB 188 GND 104 VCCA 2 VCOMPLC 179 GND 9 VCCA 52 VCOMPLD 177 GND 15 VCCA 156 VCOMPLE 86 GND 21 VCCA 14 VCOMPLF 84 GND 32 VCCA 38 VCOMPLG 75 GND 39 VCCA 64 VCOMPLH 73 GND 46 VCCA 93 VPUMP 158 GND 51 VCCA 118 GND 59 VCCA 142 GND 65 VCCA 168 GND 69 VCCA 195 GND 90 VCCPLA 189 R ev i sio n 1 8 Axcelerator Family FPGAs PQ208 PQ208 AX500 Function Pin Number Bank 0 PQ208 AX500 Function Pin Number AX500 Function Pin Number IO61PB2F5 134 IO105PB5F10/CLKGP 77 IO03NB0F0 198 IO62NB2F5 131 IO106NB5F10/CLKHN 70 IO03PB0F0 199 IO62PB2F5 133 IO106PB5F10/CLKHP 71 IO04NB0F0 197 IO107NB5F10 66 IO19NB0F1/HCLKAN 191 IO63NB3F6 127 IO107PB5F10 67 IO19PB0F1/HCLKAP 192 IO63PB3F6 129 IO119NB5F11 62 IO20NB0F1/HCLKBN 185 IO64NB3F6 126 IO121NB5F11 60 IO20PB0F1/HCLKBP 186 IO64PB3F6 128 IO121PB5F11 61 IO66NB3F6 122 IO123NB5F11 56 Bank 1 Bank 3 IO21NB1F2/HCLKCN 180 IO66PB3F6 123 IO123PB5F11 57 IO21PB1F2/HCLKCP 181 IO68NB3F6 120 IO125NB5F11 54 IO22NB1F2/HCLKDN 174 IO68PB3F6 121 IO125PB5F11 55 IO22PB1F2/HCLKDP 175 IO77NB3F7 116 IO23NB1F2 170 IO77PB3F7 117 IO127NB6F12 47 IO23PB1F2 171 IO79NB3F7 114 IO127PB6F12 49 IO37NB1F3 165 IO79PB3F7 115 IO128NB6F12 48 IO37PB1F3 166 IO81NB3F7 110 IO128PB6F12 50 IO39NB1F3 161 IO81PB3F7 111 IO129NB6F12 42 IO39PB1F3 162 IO82NB3F7 108 IO129PB6F12 43 IO41NB1F3 159 IO82PB3F7 109 IO130PB6F12 44 IO41PB1F3 160 IO83NB3F7 106 IO132NB6F12 40 IO83PB3F7 107 IO132PB6F12 41 IO141NB6F13 35 Bank 2 Bank 6 IO43NB2F4 151 IO43PB2F4 153 IO84PB4F8 103 IO141PB6F13 36 IO44NB2F4 152 IO85NB4F8 100 IO142PB6F13 37 IO44PB2F4 154 IO86NB4F8 101 IO143NB6F13 33 IO45PB2F4 148 IO86PB4F8 102 IO143PB6F13 34 IO46NB2F4 146 IO87NB4F8 96 IO145NB6F13 28 IO46PB2F4 147 IO87PB4F8 97 IO145PB6F13 30 IO48NB2F4 144 IO101NB4F9 91 IO146NB6F13 27 IO48PB2F4 145 IO101PB4F9 92 IO146PB6F13 29 IO57NB2F5 139 IO103NB4F9/CLKEN 87 IO57PB2F5 140 IO103PB4F9/CLKEP 88 IO147NB7F14 23 IO58PB2F5 141 IO104NB4F9/CLKFN 81 IO147PB7F14 25 IO59NB2F5 137 IO104PB4F9/CLKFP 82 IO148NB7F14 22 IO59PB2F5 138 Bank 5 IO148PB7F14 24 IO61NB2F5 132 IO150NB7F14 18 Bank 4 IO105NB5F10/CLKGN R ev i si o n 1 8 76 Bank 7 3- 87 Package Pin Assignments PQ208 PQ208 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO150PB7F14 19 GND 94 VCCPLB 187 IO152NB7F14 16 GND 99 VCCPLC 178 IO152PB7F14 17 GND 113 VCCPLD 176 IO161NB7F15 12 GND 119 VCCPLE 85 IO161PB7F15 13 GND 125 VCCPLF 83 IO163NB7F15 10 GND 143 VCCPLG 74 IO163PB7F15 11 GND 136 VCCPLH 72 IO165PB7F15 7 GND 150 VCCIB0 200 IO166NB7F15 5 GND 155 VCCIB0 193 IO166PB7F15 6 GND 164 VCCIB1 172 IO167NB7F15 3 GND 169 VCCIB1 163 IO167PB7F15 4 GND 173 VCCIB2 149 GND 194 VCCIB2 135 Dedicated I/O 3- 88 PQ208 VCCDA 1 GND 196 VCCIB3 124 VCCDA 26 GND 201 VCCIB3 112 VCCDA 53 GND/LP 208 VCCIB4 98 VCCDA 63 PRA 184 VCCIB4 89 VCCDA 78 PRB 183 VCCIB5 68 VCCDA 95 PRC 80 VCCIB5 58 VCCDA 105 PRD 79 VCCIB6 45 VCCDA 130 TCK 205 VCCIB6 31 VCCDA 157 TDI 204 VCCIB7 20 VCCDA 167 TDO 203 VCCIB7 8 VCCDA 182 TMS 206 VCOMPLA 190 VCCDA 202 TRST 207 VCOMPLB 188 GND 104 VCCA 2 VCOMPLC 179 GND 9 VCCA 14 VCOMPLD 177 GND 15 VCCA 38 VCOMPLE 86 GND 21 VCCA 52 VCOMPLF 84 GND 32 VCCA 64 VCOMPLG 75 GND 39 VCCA 93 VCOMPLH 73 GND 46 VCCA 118 VPUMP 158 GND 51 VCCA 142 GND 59 VCCA 156 GND 65 VCCA 168 GND 69 VCCA 195 GND 90 VCCPLA 189 R ev i sio n 1 8 Axcelerator Family FPGAs 208 207 206 205 160 159 158 157 CQ208 Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 49 50 51 52 101 102 103 104 53 54 55 56 108 107 106 105 Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3- 89 Package Pin Assignments CQ208 CQ208 AX250 Function Pin Number Bank 0 CQ208 AX250 Function Pin Number AX250 Function Pin Number IO43PB2F2 134 IO76PB5F5/CLKGP 77 IO02NB0F0 197 IO44NB2F2 131 IO77NB5F5/CLKHN 70 IO03NB0F0 198 IO44PB2F2 133 IO77PB5F5/CLKHP 71 IO03PB0F0 199 IO78NB5F5 66 IO12NB0F0/HCLKAN 191 IO45NB3F3 127 IO78PB5F5 67 IO12PB0F0/HCLKAP 192 IO45PB3F3 129 IO86NB5F5 62 IO13NB0F0/HCLKBN 185 IO46NB3F3 126 IO87NB5F5 60 IO13PB0F0/HCLKBP 186 IO46PB3F3 128 IO87PB5F5 61 IO48NB3F3 122 IO88NB5F5 56 Bank 1 Bank 3 IO14NB1F1/HCLKCN 180 IO48PB3F3 123 IO88PB5F5 57 IO14PB1F1/HCLKCP 181 IO50NB3F3 120 IO89NB5F5 54 IO15NB1F1/HCLKDN 174 IO50PB3F3 121 IO89PB5F5 55 IO15PB1F1/HCLKDP 175 IO55NB3F3 116 IO16NB1F1 170 IO55PB3F3 117 IO91NB6F6 47 IO16PB1F1 171 IO57NB3F3 114 IO91PB6F6 49 IO24NB1F1 165 IO57PB3F3 115 IO92NB6F6 48 IO24PB1F1 166 IO59NB3F3 110 IO92PB6F6 50 IO26NB1F1 161 IO59PB3F3 111 IO93NB6F6 42 IO26PB1F1 162 IO60NB3F3 108 IO93PB6F6 43 IO27NB1F1 159 IO60PB3F3 109 IO94PB6F6 44 IO27PB1F1 160 IO61NB3F3 106 IO96NB6F6 40 IO61PB3F3 107 IO96PB6F6 41 IO101NB6F6 35 Bank 2 3- 90 Bank 6 IO29NB2F2 151 IO29PB2F2 153 IO62NB4F4 100 IO101PB6F6 36 IO30NB2F2 152 IO62PB4F4 103 IO102PB6F6 37 IO30PB2F2 154 IO63NB4F4 101 IO103NB6F6 33 IO31PB2F2 148 IO63PB4F4 102 IO103PB6F6 34 IO32NB2F2 146 IO64NB4F4 96 IO105NB6F6 28 IO32PB2F2 147 IO64PB4F4 97 IO105PB6F6 30 IO34NB2F2 144 IO72NB4F4 91 IO106NB6F6 27 IO34PB2F2 145 IO72PB4F4 92 IO106PB6F6 29 IO39NB2F2 139 IO74NB4F4/CLKEN 87 IO39PB2F2 140 IO74PB4F4/CLKEP 88 IO107NB7F7 23 IO40PB2F2 141 IO75NB4F4/CLKFN 81 IO107PB7F7 25 IO41NB2F2 137 IO75PB4F4/CLKFP 82 IO108NB7F7 22 IO41PB2F2 138 IO108PB7F7 24 IO43NB2F2 132 IO110NB7F7 18 Bank 4 Bank 5 IO76NB5F5/CLKGN R ev i sio n 1 8 76 Bank 7 Axcelerator Family FPGAs CQ208 CQ208 CQ208 AX250 Function Pin Number AX250 Function Pin Number AX250 Function Pin Number IO110PB7F7 19 GND 194 VCCIB0 200 IO112NB7F7 16 GND 196 VCCIB1 163 IO112PB7F7 17 GND 201 VCCIB1 172 IO117NB7F7 12 GND/LP 208 VCCIB2 135 IO117PB7F7 13 PRA 184 VCCIB2 149 IO119NB7F7 10 PRB 183 VCCIB3 112 IO119PB7F7 11 PRC 80 VCCIB3 124 IO121PB7F7 7 PRD 79 VCCIB4 89 IO122NB7F7 5 TCK 205 VCCIB4 98 IO122PB7F7 6 TDI 204 VCCIB5 58 IO123NB7F7 3 TDO 203 VCCIB5 68 IO123PB7F7 4 TMS 206 VCCIB6 31 TRST 207 VCCIB6 45 Dedicated I/O GND 9 VCCA 2 VCCIB7 8 GND 15 VCCA 14 VCCIB7 20 GND 21 VCCA 38 VCCPLA 189 GND 32 VCCA 52 VCCPLB 187 GND 39 VCCA 64 VCCPLC 178 GND 46 VCCA 93 VCCPLD 176 GND 51 VCCA 118 VCCPLE 85 GND 59 VCCA 142 VCCPLF 83 GND 65 VCCA 156 VCCPLG 74 GND 69 VCCA 168 VCCPLH 72 GND 90 VCCA 195 VCOMPLA 190 GND 94 VCCDA 1 VCOMPLB 188 GND 99 VCCDA 26 VCOMPLC 179 GND 104 VCCDA 53 VCOMPLD 177 GND 113 VCCDA 63 VCOMPLE 86 GND 119 VCCDA 78 VCOMPLF 84 GND 125 VCCDA 95 VCOMPLG 75 GND 136 VCCDA 105 VCOMPLH 73 GND 143 VCCDA 130 VPUMP 158 GND 150 VCCDA 157 GND 155 VCCDA 167 GND 164 VCCDA 182 GND 169 VCCDA 202 GND 173 VCCIB0 193 R ev i si o n 1 8 3- 91 Package Pin Assignments CQ208 CQ208 AX500 Function Pin Number Bank 0 CQ208 AX500 Function Pin Number AX500 Function Pin Number IO61PB2F5 134 IO105PB5F10/CLKGP 77 IO03NB0F0 198 IO62NB2F5 131 IO106NB5F10/CLKHN 70 IO03PB0F0 199 IO62PB2F5 133 IO106PB5F10/CLKHP 71 IO04NB0F0 197 IO107NB5F10 66 IO19NB0F1/HCLKAN 191 IO63NB3F6 127 IO107PB5F10 67 IO19PB0F1/HCLKAP 192 IO63PB3F6 129 IO119NB5F11 62 IO20NB0F1/HCLKBN 185 IO64NB3F6 126 IO121NB5F11 60 IO20PB0F1/HCLKBP 186 IO64PB3F6 128 IO121PB5F11 61 IO66NB3F6 122 IO123NB5F11 56 Bank 1 Bank 3 IO21NB1F2/HCLKCN 180 IO66PB3F6 123 IO123PB5F11 57 IO21PB1F2/HCLKCP 181 IO68NB3F6 120 IO125NB5F11 54 IO22NB1F2/HCLKDN 174 IO68PB3F6 121 IO125PB5F11 55 IO22PB1F2/HCLKDP 175 IO77NB3F7 116 IO23NB1F2 170 IO77PB3F7 117 IO127NB6F12 47 IO23PB1F2 171 IO79NB3F7 114 IO127PB6F12 49 IO37NB1F3 165 IO79PB3F7 115 IO128NB6F12 48 IO37PB1F3 166 IO81NB3F7 110 IO128PB6F12 50 IO39NB1F3 161 IO81PB3F7 111 IO129NB6F12 42 IO39PB1F3 162 IO82NB3F7 108 IO129PB6F12 43 IO41NB1F3 159 IO82PB3F7 109 IO130PB6F12 44 IO41PB1F3 160 IO83NB3F7 106 IO132NB6F12 40 IO83PB3F7 107 IO132PB6F12 41 IO141NB6F13 35 Bank 2 3- 92 Bank 6 IO43NB2F4 151 IO43PB2F4 153 IO84PB4F8 103 IO141PB6F13 36 IO44NB2F4 152 IO85NB4F8 100 IO142PB6F13 37 IO44PB2F4 154 IO86NB4F8 101 IO143NB6F13 33 IO45PB2F4 148 IO86PB4F8 102 IO143PB6F13 34 IO46NB2F4 146 IO87NB4F8 96 IO145NB6F13 28 IO46PB2F4 147 IO87PB4F8 97 IO145PB6F13 30 IO48NB2F4 144 IO101NB4F9 91 IO146NB6F13 27 IO48PB2F4 145 IO101PB4F9 92 IO146PB6F13 29 IO57NB2F5 139 IO103NB4F9/CLKEN 87 IO57PB2F5 140 IO103PB4F9/CLKEP 88 IO147NB7F14 23 IO58PB2F5 141 IO104NB4F9/CLKFN 81 IO147PB7F14 25 IO59NB2F5 137 IO104PB4F9/CLKFP 82 IO148NB7F14 22 IO59PB2F5 138 IO148PB7F14 24 IO61NB2F5 132 IO150NB7F14 18 Bank 4 Bank 5 IO105NB5F10/CLKGN R ev i sio n 1 8 76 Bank 7 Axcelerator Family FPGAs CQ208 CQ208 CQ208 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO150PB7F14 19 GND 173 VCCIB0 200 IO152NB7F14 16 GND 194 VCCIB1 163 IO152PB7F14 17 GND 196 VCCIB1 172 IO161NB7F15 12 GND 201 VCCIB2 135 IO161PB7F15 13 GND/LP 208 VCCIB2 149 IO163NB7F15 10 PRA 184 VCCIB3 112 IO163PB7F15 11 PRB 183 VCCIB3 124 IO165PB7F15 7 PRC 80 VCCIB4 89 IO166NB7F15 5 PRD 79 VCCIB4 98 IO166PB7F15 6 TCK 205 VCCIB5 58 IO167NB7F15 3 TDI 204 VCCIB5 68 IO167PB7F15 4 TDO 203 VCCIB6 31 TMS 206 VCCIB6 45 Dedicated I/O VCCDA 1 TRST 207 VCCIB7 8 GND 9 VCCA 2 VCCIB7 20 GND 15 VCCA 14 VCCPLA 189 GND 21 VCCA 38 VCCPLB 187 GND 32 VCCA 52 VCCPLC 178 GND 39 VCCA 64 VCCPLD 176 GND 46 VCCA 93 VCCPLE 85 GND 51 VCCA 118 VCCPLF 83 GND 59 VCCA 142 VCCPLG 74 GND 65 VCCA 156 VCCPLH 72 GND 69 VCCA 168 VCOMPLA 190 GND 90 VCCA 195 VCOMPLB 188 GND 94 VCCDA 26 VCOMPLC 179 GND 99 VCCDA 53 VCOMPLD 177 GND 104 VCCDA 63 VCOMPLE 86 GND 113 VCCDA 78 VCOMPLF 84 GND 119 VCCDA 95 VCOMPLG 75 GND 125 VCCDA 105 VCOMPLH 73 GND 136 VCCDA 130 VPUMP 158 GND 143 VCCDA 157 GND 150 VCCDA 167 GND 155 VCCDA 182 GND 164 VCCDA 202 GND 169 VCCIB0 193 R ev i si o n 1 8 3- 93 Package Pin Assignments 256 255 254 253 196 195 194 193 CQ256 Pin 1 1 2 3 4 192 191 190 189 Ceramic Tie Bar 256-Pin CQFP 132 131 130 129 65 66 67 68 125 126 127 128 61 62 63 64 Note For Package Manufacturing and Environmental information, visit the Resource center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 3- 94 R ev i sio n 1 8 Axcelerator Family FPGAs CQ256 AX2000 Function CQ256 Pin Number Bank 0 CQ256 AX2000 Function Pin Number AX2000 Function Pin Number IO87PB2F8 188 IO149PB3F13 137 IO89PB2F8 186 IO01NB0F0 248 IO01PB0F0 249 IO04NB0F0 246 IO107NB2F10 IO04PB0F0 247 IO05NB0F0 Bank 3 IO165NB3F15 135 184 IO167NB3F15 133 IO107PB2F10 185 IO167PB3F15 134 242 IO110NB2F10 180 IO05PB0F0 243 IO110PB2F10 181 IO181NB4F17 124 IO08NB0F0 240 IO111NB2F10 178 IO181PB4F17 125 IO08PB0F0 241 IO111PB2F10 179 IO182NB4F17 122 IO112NB2F10 174 IO182PB4F17 123 Bank 0 Bank 2 Bank 4 IO37NB0F3 234 IO112PB2F10 175 IO183NB4F17 118 IO37PB0F3 235 IO113NB2F10 172 IO183PB4F17 119 IO41NB0F3/HCLKAN 232 IO113PB2F10 173 IO184NB4F17 116 IO41PB0F3/HCLKAP 233 IO114NB2F10 168 IO184PB4F17 117 IO42NB0F3/HCLKBN 228 IO114PB2F10 169 IO190NB4F17 112 IO42PB0F3/HCLKBP 229 IO115NB2F10 166 IO190PB4F17 113 IO115PB2F10 167 IO192NB4F17 110 IO192PB4F17 111 Bank 1 IO43NB1F4/HCLKCN 220 IO117NB2F10 162 IO43PB1F4/HCLKCP 221 IO117PB2F10 163 IO44NB1F4/HCLKDN 216 IO44PB1F4/HCLKDP 217 Bank 1 Bank 3 Bank 4 IO212NB4F19/CLKEN 104 IO139NB3F13 158 IO212PB4F19/CLKEP 105 IO139PB3F13 159 IO213NB4F19/CLKFN 100 IO213PB4F19/CLKFP 101 IO65NB1F6 210 IO141NB3F13 154 IO65PB1F6 211 IO141PB3F13 155 IO69NB1F6 208 IO142NB3F13 152 IO214NB5F20/CLKGN 92 IO69PB1F6 209 IO142PB3F13 153 IO214PB5F20/CLKGP 93 IO70NB1F6 199 IO145NB3F13 148 IO215NB5F20/CLKHN 88 IO71NB1F6 204 IO145PB3F13 149 IO215PB5F20/CLKHP 89 IO71PB1F6 205 IO146NB3F13 146 IO73NB1F6 202 IO146PB3F13 147 IO236NB5F22 82 IO73PB1F6 203 IO147NB3F13 140 IO236PB5F22 83 IO74NB1F6 197 IO147PB3F13 141 IO238NB5F22 80 IO74PB1F6 198 IO148NB3F13 142 IO238PB5F22 81 IO148PB3F13 143 IO240NB5F22 76 IO149NB3F13 136 IO240PB5F22 77 Bank 2 IO87NB2F8 187 R ev i si o n 1 8 Bank 5 Bank 5 3- 95 Package Pin Assignments CQ256 CQ256 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO242NB5F22 74 IO315PB7F29 21 GND 121 IO242PB5F22 75 IO316NB7F29 18 GND 128 IO243NB5F22 70 IO316PB7F29 19 GND 129 IO243PB5F22 71 IO317NB7F29 14 GND 132 IO244NB5F22 68 IO317PB7F29 15 GND 139 IO244PB5F22 69 IO318NB7F29 12 GND 145 IO318PB7F29 13 GND 151 Bank 6 IO257PB6F24 60 IO320NB7F29 8 GND 157 IO258NB6F24 58 IO320PB7F29 9 GND 161 IO258PB6F24 59 GND 165 Bank 6 Bank 7 IO341NB7F31 6 GND 171 IO341PB7F31 7 GND 177 GND 183 IO279NB6F26 56 IO279PB6F26 57 Dedicated I/O IO280NB6F26 52 GND 1 GND 190 IO280PB6F26 53 GND 5 GND 192 IO281NB6F26 50 GND 11 GND 193 IO281PB6F26 51 GND 17 GND 201 IO282NB6F26 46 GND 23 GND 207 IO282PB6F26 47 GND 29 GND 213 IO284NB6F26 44 GND 33 GND 219 IO284PB6F26 45 GND 37 GND 225 IO285NB6F26 40 GND 43 GND 231 IO285PB6F26 41 GND 49 GND 239 IO286NB6F26 38 GND 55 GND 245 IO286PB6F26 39 GND 62 GND 256 IO287NB6F26 34 GND 64 PRA 227 IO287PB6F26 35 GND 65 PRB 226 GND 73 PRC 99 Bank 7 9 3- 96 CQ256 IO310NB7F29 30 GND 79 PRD 98 IO310PB7F29 31 GND 85 TCK 253 IO311NB7F29 26 GND 91 TDI 252 IO311PB7F29 27 GND 97 TDO 250 IO312NB7F29 24 GND 103 TMS 254 IO312PB7F29 25 GND 109 TRST 255 IO315NB7F29 20 GND 115 VCCA 3 R ev i sio n 1 8 Axcelerator Family FPGAs CQ256 CQ256 AX2000 Function Pin Number AX2000 Function Pin Number VCCA 4 VCCDA 224 VCCA 22 VCCDA 236 VCCA 42 VCCDA 237 VCCA 61 VCCDA 251 VCCA 63 VCCIB0 230 VCCA 84 VCCIB0 244 VCCA 108 VCCIB1 200 VCCA 127 VCCIB1 206 VCCA 131 VCCIB1 218 VCCA 150 VCCIB2 164 VCCA 170 VCCIB2 176 VCCA 189 VCCIB2 182 VCCA 191 VCCIB3 138 VCCA 212 VCCIB3 144 VCCA 238 VCCIB3 156 VCCDA 2 VCCIB4 102 VCCDA 32 VCCIB4 114 VCCDA 66 VCCIB4 120 VCCDA 67 VCCIB5 72 VCCDA 86 VCCIB5 78 VCCDA 87 VCCIB5 90 VCCDA 94 VCCIB6 36 VCCDA 95 VCCIB6 48 VCCDA 96 VCCIB6 54 VCCDA 106 VCCIB7 10 VCCDA 107 VCCIB7 16 VCCDA 126 VCCIB7 28 VCCDA 130 VPUMP 195 VCCDA 160 VCCDA 194 VCCDA 196 VCCDA 214 VCCDA 215 VCCDA 222 VCCDA 223 R ev i si o n 1 8 3- 97 Package Pin Assignments 268 267 266 265 339 338 337 336 335 334 333 332 331 352 351 350 349 CQ352 Pin 1 1 2 3 4 264 263 262 261 Ceramic Tie Bar 41 42 43 44 45 46 47 48 49 223 222 221 220 219 218 217 216 215 352-Pin CQFP 180 179 178 177 173 174 175 176 127 128 129 130 131 132 133 134 135 89 90 91 92 85 86 87 88 Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. 3- 98 R ev i sio n 1 8 Axcelerator Family FPGAs CQ352 AX250 Function CQ352 Pin Number Bank 0 CQ352 AX250 Function Pin Number IO24NB1F1 275 AX250 Function Pin Number Bank 3 IO00NB0F0 341 IO24PB1F1 276 IO45NB3F3 217 IO00PB0F0 342 IO25NB1F1 271 IO45PB3F3 218 IO01NB0F0 343 IO25PB1F1 272 IO46NB3F3 219 IO02NB0F0 337 IO27NB1F1 269 IO46PB3F3 220 IO02PB0F0 338 IO27PB1F1 270 IO47NB3F3 213 IO04NB0F0 335 IO47PB3F3 214 IO04PB0F0 336 IO29NB2F2 261 IO48NB3F3 211 IO06NB0F0 331 IO29PB2F2 262 IO48PB3F3 212 IO06PB0F0 332 IO30NB2F2 259 IO49NB3F3 207 IO08NB0F0 325 IO30PB2F2 260 IO49PB3F3 208 IO08PB0F0 326 IO31NB2F2 255 IO51NB3F3 205 IO10NB0F0 323 IO31PB2F2 256 IO51PB3F3 206 IO10PB0F0 324 IO33NB2F2 249 IO52NB3F3 201 IO12NB0F0/HCLKAN 319 IO33PB2F2 250 IO52PB3F3 202 IO12PB0F0/HCLKAP 320 IO34NB2F2 253 IO53NB3F3 199 IO13NB0F0/HCLKBN 313 IO34PB2F2 254 IO53PB3F3 200 IO13PB0F0/HCLKBP 314 IO35NB2F2 247 IO54NB3F3 195 IO35PB2F2 248 IO54PB3F3 196 Bank 1 Bank 2 IO14NB1F1/HCLKCN 305 IO36NB2F2 243 IO55NB3F3 193 IO14PB1F1/HCLKCP 306 IO36PB2F2 244 IO55PB3F3 194 IO15NB1F1/HCLKDN 299 IO37NB2F2 241 IO56NB3F3 187 IO15PB1F1/HCLKDP 300 IO37PB2F2 242 IO56PB3F3 188 IO16NB1F1 289 IO38NB2F2 237 IO57NB3F3 189 IO16PB1F1 290 IO38PB2F2 238 IO57PB3F3 190 IO17NB1F1 295 IO39NB2F2 235 IO59NB3F3 183 IO17PB1F1 296 IO39PB2F2 236 IO59PB3F3 184 IO18NB1F1 287 IO41NB2F2 231 IO60NB3F3 181 IO18PB1F1 288 IO41PB2F2 232 IO60PB3F3 182 IO20NB1F1 283 IO42NB2F2 229 IO61NB3F3 179 IO20PB1F1 284 IO42PB2F2 230 IO61PB3F3 180 IO22NB1F1 277 IO43NB2F2 225 IO22PB1F1 278 IO43PB2F2 226 IO62NB4F4 172 IO23NB1F1 281 IO44NB2F2 223 IO62PB4F4 173 IO23PB1F1 282 IO44PB2F2 224 IO64NB4F4 166 R ev i si o n 1 8 Bank 4 3- 99 Package Pin Assignments CQ352 CQ352 CQ352 AX250 Function Pin Number AX250 Function Pin Number AX250 Function Pin Number IO64PB4F4 167 IO85PB5F5 105 IO106NB6F6 46 IO65NB4F4 170 IO86NB5F5 98 IO106PB6F6 47 IO65PB4F4 171 IO86PB5F5 99 Bank 7 IO66NB4F4 164 IO87NB5F5 94 IO107NB7F7 40 IO66PB4F4 165 IO87PB5F5 95 IO107PB7F7 41 IO67NB4F4 160 IO89NB5F5 92 IO108NB7F7 42 IO67PB4F4 161 IO89PB5F5 93 IO108PB7F7 43 IO68NB4F4 158 IO109NB7F7 36 IO68PB4F4 159 IO90PB6F6 86 IO109PB7F7 37 IO70NB4F4 154 IO91NB6F6 84 IO110NB7F7 34 IO70PB4F4 155 IO91PB6F6 85 IO110PB7F7 35 IO72NB4F4 152 IO92NB6F6 78 IO111NB7F7 30 IO72PB4F4 153 IO92PB6F6 79 IO111PB7F7 31 IO73NB4F4 146 IO93NB6F6 82 IO113NB7F7 28 IO73PB4F4 147 IO93PB6F6 83 IO113PB7F7 29 IO74NB4F4/CLKEN 142 IO95NB6F6 76 IO114NB7F7 24 IO74PB4F4/CLKEP 143 IO95PB6F6 77 IO114PB7F7 25 IO75NB4F4/CLKFN 136 IO96NB6F6 72 IO115NB7F7 22 IO75PB4F4/CLKFP 137 IO96PB6F6 73 IO115PB7F7 23 IO97NB6F6 70 IO116NB7F7 18 Bank 5 Bank 6 IO76NB5F5/CLKGN 128 IO97PB6F6 71 IO116PB7F7 19 IO76PB5F5/CLKGP 129 IO98NB6F6 66 IO117NB7F7 16 IO77NB5F5/CLKHN 122 IO98PB6F6 67 IO117PB7F7 17 IO77PB5F5/CLKHP 123 IO99NB6F6 64 IO118NB7F7 12 IO78NB5F5 112 IO99PB6F6 65 IO118PB7F7 13 IO78PB5F5 113 IO100NB6F6 60 IO119NB7F7 10 IO79NB5F5 118 IO100PB6F6 61 IO119PB7F7 11 IO79PB5F5 119 IO101NB6F6 58 IO121NB7F7 6 IO80NB5F5 110 IO101PB6F6 59 IO121PB7F7 7 IO80PB5F5 111 IO103NB6F6 54 IO123NB7F7 4 IO82NB5F5 106 IO103PB6F6 55 IO123PB7F7 5 IO82PB5F5 107 IO104NB6F6 52 Dedicated I/O IO84NB5F5 100 IO104PB6F6 53 GND 1 IO84PB5F5 101 IO105NB6F6 48 GND 9 IO85NB5F5 104 IO105PB6F6 49 GND 15 3- 10 0 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 CQ352 CQ352 AX250 Function Pin Number AX250 Function Pin Number AX250 Function Pin Number GND 21 GND 240 TDI 348 GND 27 GND 246 TDO 347 GND 33 GND 252 TMS 350 GND 39 GND 258 TRST 351 GND 45 GND 264 VCCA 3 GND 51 GND 265 VCCA 14 GND 57 GND 274 VCCA 32 GND 63 GND 280 VCCA 56 GND 69 GND 286 VCCA 74 GND 75 GND 292 VCCA 87 GND 81 GND 298 VCCA 102 GND 88 GND 310 VCCA 114 GND 89 GND 322 VCCA 150 GND 97 GND 330 VCCA 162 GND 103 GND 334 VCCA 175 GND 109 GND 340 VCCA 191 GND 115 GND 345 VCCA 209 GND 121 GND 352 VCCA 233 GND 133 NC 91 VCCA 251 GND 145 NC 117 VCCA 263 GND 151 NC 130 VCCA 279 GND 157 NC 131 VCCA 291 GND 163 NC 148 VCCA 329 GND 169 NC 174 VCCA 339 GND 176 NC 268 VCCDA 2 GND 177 NC 294 VCCDA 44 GND 186 NC 307 VCCDA 90 GND 192 NC 308 VCCDA 116 GND 198 NC 327 VCCDA 132 GND 204 NC 328 VCCDA 149 GND 210 PRA 312 VCCDA 178 GND 216 PRB 311 VCCDA 221 GND 222 PRC 135 VCCDA 266 GND 228 PRD 134 VCCDA 293 GND 234 TCK 349 VCCDA 309 R ev i si o n 1 8 3- 101 Package Pin Assignments CQ352 CQ352 3- 10 2 AX250 Function Pin Number AX250 Function Pin Number VCCDA 346 VCCPLG 126 VCCIB0 321 VCCPLH 124 VCCIB0 333 VCOMPLA 318 VCCIB0 344 VCOMPLB 316 VCCIB1 273 VCOMPLC 304 VCCIB1 285 VCOMPLD 302 VCCIB1 297 VCOMPLE 141 VCCIB2 227 VCOMPLF 139 VCCIB2 239 VCOMPLG 127 VCCIB2 245 VCOMPLH 125 VCCIB2 257 VPUMP 267 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 VCCIB5 108 VCCIB5 120 VCCIB6 50 VCCIB6 62 VCCIB6 68 VCCIB6 80 VCCIB7 8 VCCIB7 20 VCCIB7 26 VCCIB7 38 VCCPLA 317 VCCPLB 315 VCCPLC 303 VCCPLD 301 VCCPLE 140 VCCPLF 138 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 AX500 Function CQ352 Pin Number Bank 0 CQ352 AX500 Function Pin Number IO35NB1F3 275 AX500 Function Pin Number Bank 3 IO00PB0F0 343 IO35PB1F3 276 IO63NB3F6 217 IO03NB0F0 341 IO37NB1F3 271 IO63PB3F6 218 IO03PB0F0 342 IO37PB1F3 272 IO64NB3F6 219 IO05NB0F0 337 IO41NB1F3 269 IO64PB3F6 220 IO05PB0F0 338 IO41PB1F3 270 IO65NB3F6 213 IO07NB0F0 335 IO65PB3F6 214 IO07PB0F0 336 IO43NB2F4 261 IO67NB3F6 207 IO09NB0F0 331 IO43PB2F4 262 IO67PB3F6 208 IO09PB0F0 332 IO45NB2F4 259 IO68NB3F6 211 IO15NB0F1 325 IO45PB2F4 260 IO68PB3F6 212 IO15PB0F1 326 IO47NB2F4 255 IO69NB3F6 205 IO17NB0F1 323 IO47PB2F4 256 IO69PB3F6 206 IO17PB0F1 324 IO49NB2F4 253 IO71NB3F6 201 IO19NB0F1/HCLKAN 319 IO49PB2F4 254 IO71PB3F6 202 IO19PB0F1/HCLKAP 320 IO50NB2F4 247 IO73NB3F6 199 IO20NB0F1/HCLKBN 313 IO50PB2F4 248 IO73PB3F6 200 IO20PB0F1/HCLKBP 314 IO51NB2F4 249 IO75NB3F7 193 IO51PB2F4 250 IO75PB3F7 194 Bank 1 Bank 2 IO21NB1F2/HCLKCN 305 IO53NB2F5 243 IO76NB3F7 195 IO21PB1F2/HCLKCP 306 IO53PB2F5 244 IO76PB3F7 196 IO22NB1F2/HCLKDN 299 IO54NB2F5 241 IO77NB3F7 189 IO22PB1F2/HCLKDP 300 IO54PB2F5 242 IO77PB3F7 190 IO23NB1F2 289 IO55NB2F5 237 IO79NB3F7 187 IO23PB1F2 290 IO55PB2F5 238 IO79PB3F7 188 IO24NB1F2 295 IO57NB2F5 235 IO80NB3F7 183 IO24PB1F2 296 IO57PB2F5 236 IO80PB3F7 184 IO25NB1F2 287 IO58NB2F5 231 IO81NB3F7 181 IO25PB1F2 288 IO58PB2F5 232 IO81PB3F7 182 IO27NB1F2 283 IO59NB2F5 229 IO83NB3F7 179 IO27PB1F2 284 IO59PB2F5 230 IO83PB3F7 180 IO29NB1F2 281 IO61NB2F5 225 IO29PB1F2 282 IO61PB2F5 226 IO85NB4F8 172 IO31NB1F2 277 IO62NB2F5 223 IO85PB4F8 173 IO31PB1F2 278 IO62PB2F5 224 IO87NB4F8 170 R ev i si o n 1 8 Bank 4 3- 103 Package Pin Assignments CQ352 CQ352 CQ352 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number IO87PB4F8 171 IO119PB5F11 101 IO146NB6F13 46 IO89NB4F8 166 IO121NB5F11 98 IO146PB6F13 47 IO89PB4F8 167 IO121PB5F11 99 IO94NB4F9 164 IO123NB5F11 94 IO147NB7F14 40 IO94PB4F9 165 IO123PB5F11 95 IO147PB7F14 41 IO95NB4F9 160 IO125NB5F11 92 IO148NB7F14 42 IO95PB4F9 161 IO125PB5F11 93 IO148PB7F14 43 IO97NB4F9 158 IO149NB7F14 36 IO97PB4F9 159 IO126PB6F12 86 IO149PB7F14 37 IO99NB4F9 154 IO127NB6F12 84 IO151NB7F14 30 IO99PB4F9 155 IO127PB6F12 85 IO151PB7F14 31 IO100NB4F9 146 IO129NB6F12 82 IO152NB7F14 34 IO100PB4F9 147 IO129PB6F12 83 IO152PB7F14 35 IO101NB4F9 152 IO131NB6F12 78 IO153NB7F14 28 IO101PB4F9 153 IO131PB6F12 79 IO153PB7F14 29 IO103NB4F9/CLKEN 142 IO133NB6F12 76 IO155NB7F14 24 IO103PB4F9/CLKEP 143 IO133PB6F12 77 IO155PB7F14 25 IO104NB4F9/CLKFN 136 IO134NB6F12 72 IO157NB7F14 22 IO104PB4F9/CLKFP 137 IO134PB6F12 73 IO157PB7F14 23 IO135NB6F12 70 IO159NB7F15 16 Bank 5 Bank 6 Bank 7 IO105NB5F10/CLKGN 128 IO135PB6F12 71 IO159PB7F15 17 IO105PB5F10/CLKGP 129 IO137NB6F13 66 IO160NB7F15 18 IO106NB5F10/CLKHN 122 IO137PB6F13 67 IO160PB7F15 19 IO106PB5F10/CLKHP 123 IO138NB6F13 64 IO161NB7F15 12 IO107NB5F10 118 IO138PB6F13 65 IO161PB7F15 13 IO107PB5F10 119 IO139NB6F13 60 IO163NB7F15 10 IO114NB5F11 112 IO139PB6F13 61 IO163PB7F15 11 IO114PB5F11 113 IO141NB6F13 54 IO165NB7F15 6 IO115NB5F11 110 IO141PB6F13 55 IO165PB7F15 7 IO115PB5F11 111 IO142NB6F13 58 IO167NB7F15 4 IO116NB5F11 106 IO142PB6F13 59 IO167PB7F15 5 IO116PB5F11 107 IO143NB6F13 52 Dedicated I/O IO117NB5F11 104 IO143PB6F13 53 GND 1 IO117PB5F11 105 IO145NB6F13 48 GND 9 IO119NB5F11 100 IO145PB6F13 49 GND 15 3- 10 4 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 CQ352 CQ352 AX500 Function Pin Number AX500 Function Pin Number AX500 Function Pin Number GND 21 GND 240 TDI 348 GND 27 GND 246 TDO 347 GND 33 GND 252 TMS 350 GND 39 GND 258 TRST 351 GND 45 GND 264 VCCA 3 GND 51 GND 265 VCCA 14 GND 57 GND 274 VCCA 32 GND 63 GND 280 VCCA 56 GND 69 GND 286 VCCA 74 GND 75 GND 292 VCCA 87 GND 81 GND 298 VCCA 102 GND 88 GND 310 VCCA 114 GND 89 GND 322 VCCA 150 GND 97 GND 330 VCCA 162 GND 103 GND 334 VCCA 175 GND 109 GND 340 VCCA 191 GND 115 GND 345 VCCA 209 GND 121 GND/LP 352 VCCA 233 GND 133 NC 91 VCCA 251 GND 145 NC 117 VCCA 263 GND 151 NC 130 VCCA 279 GND 157 NC 131 VCCA 291 GND 163 NC 148 VCCA 329 GND 169 NC 174 VCCA 339 GND 176 NC 268 VCCDA 2 GND 177 NC 294 VCCDA 44 GND 186 NC 307 VCCDA 90 GND 192 NC 308 VCCDA 116 GND 198 NC 327 VCCDA 132 GND 204 NC 328 VCCDA 149 GND 210 PRA 312 VCCDA 178 GND 216 PRB 311 VCCDA 221 GND 222 PRC 135 VCCDA 266 GND 228 PRD 134 VCCDA 293 GND 234 TCK 349 VCCDA 309 R ev i si o n 1 8 3- 105 Package Pin Assignments CQ352 CQ352 3- 10 6 AX500 Function Pin Number AX500 Function Pin Number VCCDA 346 VCCPLG 126 VCCIB0 321 VCCPLH 124 VCCIB0 333 VCOMPLA 318 VCCIB0 344 VCOMPLB 316 VCCIB1 273 VCOMPLC 304 VCCIB1 285 VCOMPLD 302 VCCIB1 297 VCOMPLE 141 VCCIB2 227 VCOMPLF 139 VCCIB2 239 VCOMPLG 127 VCCIB2 245 VCOMPLH 125 VCCIB2 257 VPUMP 267 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 VCCIB5 108 VCCIB5 120 VCCIB6 50 VCCIB6 62 VCCIB6 68 VCCIB6 80 VCCIB7 8 VCCIB7 20 VCCIB7 26 VCCIB7 38 VCCPLA 317 VCCPLB 315 VCCPLC 303 VCCPLD 301 VCCPLE 140 VCCPLF 138 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 AX1000 Function CQ352 Pin Number Bank 0 CQ352 AX1000 Function Pin Number IO60NB1F5 275 AX1000 Function Pin Number Bank 3 IO02NB0F0 341 IO60PB1F5 276 IO96NB3F9 217 IO02PB0F0 342 IO61NB1F5 271 IO96PB3F9 218 IO03PB0F0 343 IO61PB1F5 272 IO97NB3F9 219 IO04NB0F0 337 IO63NB1F5 269 IO97PB3F9 220 IO04PB0F0 338 IO63PB1F5 270 IO99NB3F9 213 IO08NB0F0 331 IO99PB3F9 214 IO08PB0F0 332 IO64NB2F6 259 IO108NB3F10 211 IO09NB0F0 335 IO64PB2F6 260 IO108PB3F10 212 IO09PB0F0 336 IO67NB2F6 261 IO109NB3F10 207 IO24NB0F2 325 IO67PB2F6 262 IO109PB3F10 208 IO24PB0F2 326 IO68NB2F6 255 IO111NB3F10 205 IO25NB0F2 323 IO68PB2F6 256 IO111PB3F10 206 IO25PB0F2 324 IO69NB2F6 253 IO112NB3F10 199 IO30NB0F2/HCLKAN 319 IO69PB2F6 254 IO112PB3F10 200 IO30PB0F2/HCLKAP 320 IO74NB2F7 249 IO113NB3F10 201 IO31NB0F2/HCLKBN 313 IO74PB2F7 250 IO113PB3F10 202 IO31PB0F2/HCLKBP 314 IO75NB2F7 247 IO115NB3F10 195 IO75PB2F7 248 IO115PB3F10 196 Bank 1 Bank 2 IO32NB1F3/HCLKCN 305 IO76NB2F7 243 IO116NB3F10 193 IO32PB1F3/HCLKCP 306 IO76PB2F7 244 IO116PB3F10 194 IO33NB1F3/HCLKDN 299 IO77NB2F7 241 IO117NB3F10 189 IO33PB1F3/HCLKDP 300 IO77PB2F7 242 IO117PB3F10 190 IO38NB1F3 295 IO78NB2F7 237 IO124NB3F11 183 IO38PB1F3 296 IO78PB2F7 238 IO124PB3F11 184 IO54NB1F5 287 IO79NB2F7 235 IO125NB3F11 187 IO54PB1F5 288 IO79PB2F7 236 IO125PB3F11 188 IO55NB1F5 289 IO82NB2F7 231 IO127NB3F11 181 IO55PB1F5 290 IO82PB2F7 232 IO127PB3F11 182 IO56NB1F5 281 IO83NB2F7 229 IO128NB3F11 179 IO56PB1F5 282 IO83PB2F7 230 IO128PB3F11 180 IO57NB1F5 283 IO94NB2F8 225 IO57PB1F5 284 IO94PB2F8 226 IO130NB4F12 172 IO59NB1F5 277 IO95NB2F8 223 IO130PB4F12 173 IO59PB1F5 278 IO95PB2F8 224 IO131NB4F12 170 R ev i si o n 1 8 Bank 4 3- 107 Package Pin Assignments CQ352 CQ352 CQ352 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO131PB4F12 171 IO187PB5F17 99 IO224NB6F20 46 IO132NB4F12 166 IO188NB5F17 100 IO224PB6F20 47 IO132PB4F12 167 IO188PB5F17 101 IO133NB4F12 164 IO190NB5F17 94 IO225NB7F21 40 IO133PB4F12 165 IO190PB5F17 95 IO225PB7F21 41 IO134NB4F12 160 IO192NB5F17 92 IO226NB7F21 42 IO134PB4F12 161 IO192PB5F17 93 IO226PB7F21 43 IO136NB4F12 158 IO237NB7F22 34 IO136PB4F12 159 IO193PB6F18 86 IO237PB7F22 35 IO137NB4F12 154 IO194NB6F18 84 IO238NB7F22 36 IO137PB4F12 155 IO194PB6F18 85 IO238PB7F22 37 IO138NB4F12 152 IO196NB6F18 78 IO240NB7F22 30 IO138PB4F12 153 IO196PB6F18 79 IO240PB7F22 31 IO153NB4F14 146 IO197NB6F18 82 IO241NB7F22 28 IO153PB4F14 147 IO197PB6F18 83 IO241PB7F22 29 IO159NB4F14/CLKEN 142 IO198NB6F18 76 IO242NB7F22 24 IO159PB4F14/CLKEP 143 IO198PB6F18 77 IO242PB7F22 25 IO160NB4F14/CLKFN 136 IO203NB6F19 72 IO244NB7F22 22 IO160PB4F14/CLKFP 137 IO203PB6F19 73 IO244PB7F22 23 IO204NB6F19 70 IO245NB7F22 18 Bank 5 Bank 6 Bank 7 IO161NB5F15/CLKGN 128 IO204PB6F19 71 IO245PB7F22 19 IO161PB5F15/CLKGP 129 IO205NB6F19 66 IO246NB7F22 16 IO162NB5F15/CLKHN 122 IO205PB6F19 67 IO246PB7F22 17 IO162PB5F15/CLKHP 123 IO206NB6F19 64 IO249NB7F23 12 IO167NB5F15 118 IO206PB6F19 65 IO249PB7F23 13 IO167PB5F15 119 IO207NB6F19 60 IO250NB7F23 10 IO183NB5F17 110 IO207PB6F19 61 IO250PB7F23 11 IO183PB5F17 111 IO208NB6F19 58 IO256NB7F23 4 IO184NB5F17 112 IO208PB6F19 59 IO256PB7F23 5 IO184PB5F17 113 IO211NB6F19 54 IO257NB7F23 6 IO185NB5F17 104 IO211PB6F19 55 IO257PB7F23 7 IO185PB5F17 105 IO212NB6F19 52 Dedicated I/O IO186NB5F17 106 IO212PB6F19 53 GND 1 IO186PB5F17 107 IO223NB6F20 48 GND 9 IO187NB5F17 98 IO223PB6F20 49 GND 15 3- 10 8 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 CQ352 CQ352 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND 21 GND 240 VCCA 14 GND 27 GND 246 VCCA 32 GND 33 GND 252 VCCA 56 GND 39 GND 258 VCCA 74 GND 45 GND 264 VCCA 87 GND 51 GND 265 VCCA 102 GND 57 GND 274 VCCA 114 GND 63 GND 280 VCCA 150 GND 69 GND 286 VCCA 162 GND 75 GND 292 VCCA 175 GND 81 GND 298 VCCA 191 GND 88 GND 310 VCCA 209 GND 89 GND 322 VCCA 233 GND 97 GND 330 VCCA 251 GND 103 GND 334 VCCA 263 GND 109 GND 340 VCCA 279 GND 115 GND 345 VCCA 291 GND 121 GND 352 VCCA 329 GND 133 NC 91 VCCA 339 GND 145 NC 130 VCCDA 2 GND 151 NC 131 VCCDA 44 GND 157 NC 174 VCCDA 90 GND 163 NC 268 VCCDA 116 GND 169 NC 307 VCCDA 117 GND 176 NC 308 VCCDA 132 GND 177 PRA 312 VCCDA 148 GND 186 PRB 311 VCCDA 149 GND 192 PRC 135 VCCDA 178 GND 198 PRD 134 VCCDA 221 GND 204 TCK 349 VCCDA 266 GND 210 TDI 348 VCCDA 293 GND 216 TDO 347 VCCDA 294 GND 222 TMS 350 VCCDA 309 GND 228 TRST 351 VCCDA 327 GND 234 VCCA 3 VCCDA 328 R ev i si o n 1 8 3- 109 Package Pin Assignments CQ352 CQ352 AX1000 Function Pin Number AX1000 Function Pin Number VCCDA 346 VCCPLG 126 VCCIB0 321 VCCPLH 124 VCCIB0 333 VCOMPLA 318 VCCIB0 344 VCOMPLB 316 VCCIB1 273 VCOMPLC 304 VCCIB1 285 VCOMPLD 302 VCCIB1 297 VCOMPLE 141 VCCIB2 227 VCOMPLF 139 VCCIB2 239 VCOMPLG 127 VCCIB2 245 VCOMPLH 125 VCCIB2 257 VPUMP 267 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 VCCIB5 108 VCCIB5 120 VCCIB6 50 VCCIB6 62 VCCIB6 68 VCCIB6 80 VCCIB7 8 VCCIB7 20 VCCIB7 26 VCCIB7 38 VCCPLA 317 VCCPLB 315 VCCPLC 303 VCCPLD 301 VCCPLE 140 VCCPLF 138 3- 11 0 R ev isio n 1 8 Axcelerator Family FPGAs CQ352 AX2000 Function CQ352 Pin Number Bank 0 CQ352 AX2000 Function Pin Number IO71NB1F6 277 AX2000 Function Pin Number Bank 3 IO01NB0F0 341 IO71PB1F6 278 IO129NB3F12 219 IO01PB0F0 342 IO73NB1F6 269 IO129PB3F12 220 IO02PB0F0 343 IO73PB1F6 270 IO132NB3F12 217 IO04NB0F0 337 IO74NB1F6 271 IO132PB3F12 218 IO04PB0F0 338 IO74PB1F6 272 IO137NB3F12 213 IO05NB0F0 335 IO137PB3F12 214 IO05PB0F0 336 IO87NB2F8 261 IO139NB3F13 211 IO08NB0F0 331 IO87PB2F8 262 IO139PB3F13 212 IO08PB0F0 332 IO88NB2F8 255 IO141NB3F13 205 IO37NB0F3 325 IO88PB2F8 256 IO141PB3F13 206 IO37PB0F3 326 IO89NB2F8 259 IO142NB3F13 207 IO38NB0F3 323 IO89PB2F8 260 IO142PB3F13 208 IO38PB0F3 324 IO91NB2F8 253 IO145NB3F13 199 IO41NB0F3/HCLKAN 319 IO91PB2F8 254 IO145PB3F13 200 IO41PB0F3/HCLKAP 320 IO99NB2F9 249 IO146NB3F13 201 IO42NB0F3/HCLKBN 313 IO99PB2F9 250 IO146PB3F13 202 IO42PB0F3/HCLKBP 314 IO100NB2F9 247 IO147NB3F13 193 IO100PB2F9 248 IO147PB3F13 194 Bank 1 Bank 2 IO43NB1F4/HCLKCN 305 IO107NB2F10 243 IO148NB3F13 195 IO43PB1F4/HCLKCP 306 IO107PB2F10 244 IO148PB3F13 196 IO44NB1F4/HCLKDN 299 IO110NB2F10 241 IO149NB3F13 189 IO44PB1F4/HCLKDP 300 IO110PB2F10 242 IO149PB3F13 190 IO48NB1F4 295 IO111NB2F10 237 IO161NB3F15 183 IO48PB1F4 296 IO111PB2F10 238 IO161PB3F15 184 IO65NB1F6 283 IO112NB2F10 235 IO163NB3F15 187 IO65PB1F6 284 IO112PB2F10 236 IO163PB3F15 188 IO66NB1F6 289 IO113NB2F10 231 IO165NB3F15 181 IO66PB1F6 290 IO113PB2F10 232 IO165PB3F15 182 IO68NB1F6 287 IO114NB2F10 229 IO167NB3F15 179 IO68PB1F6 288 IO114PB2F10 230 IO167PB3F15 180 IO69NB1F6 275 IO115NB2F10 225 IO69PB1F6 276 IO115PB2F10 226 IO181NB4F17 172 IO70NB1F6 281 IO117NB2F10 223 IO181PB4F17 173 IO70PB1F6 282 IO117PB2F10 224 IO182NB4F17 170 R ev i si o n 1 8 Bank 4 3- 111 Package Pin Assignments CQ352 CQ352 CQ352 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number IO182PB4F17 171 IO240PB5F22 101 IO296NB6F27 46 IO183NB4F17 166 IO242NB5F22 94 IO296PB6F27 47 IO183PB4F17 167 IO242PB5F22 95 IO184NB4F17 164 IO243NB5F22 98 IO300NB7F28 42 IO184PB4F17 165 IO243PB5F22 99 IO300PB7F28 43 IO185NB4F17 160 IO244NB5F22 92 IO303NB7F28 40 IO185PB4F17 161 IO244PB5F22 93 IO303PB7F28 41 IO190NB4F17 158 IO310NB7F29 34 IO190PB4F17 159 IO257PB6F24 86 IO310PB7F29 35 IO191NB4F17 154 IO258NB6F24 84 IO311NB7F29 36 IO191PB4F17 155 IO258PB6F24 85 IO311PB7F29 37 IO192NB4F17 152 IO261NB6F24 82 IO312NB7F29 28 IO192PB4F17 153 IO261PB6F24 83 IO312PB7F29 29 IO207NB4F19 146 IO262NB6F24 78 IO315NB7F29 30 IO207PB4F19 147 IO262PB6F24 79 IO315PB7F29 31 IO212NB4F19/CLKEN 142 IO265NB6F24 76 IO316NB7F29 22 IO212PB4F19/CLKEP 143 IO265PB6F24 77 IO316PB7F29 23 IO213NB4F19/CLKFN 136 IO279NB6F26 72 IO317NB7F29 24 IO213PB4F19/CLKFP 137 IO279PB6F26 73 IO317PB7F29 25 IO280NB6F26 70 IO318NB7F29 18 Bank 5 Bank 6 Bank 7 IO214NB5F20/CLKGN 128 IO280PB6F26 71 IO318PB7F29 19 IO214PB5F20/CLKGP 129 IO281NB6F26 66 IO320NB7F29 16 IO215NB5F20/CLKHN 122 IO281PB6F26 67 IO320PB7F29 17 IO215PB5F20/CLKHP 123 IO282NB6F26 64 IO334NB7F31 10 IO217NB5F20 118 IO282PB6F26 65 IO334PB7F31 11 IO217PB5F20 119 IO284NB6F26 60 IO335NB7F31 12 IO236NB5F22 110 IO284PB6F26 61 IO335PB7F31 13 IO236PB5F22 111 IO285NB6F26 58 IO338NB7F31 6 IO237NB5F22 112 IO285PB6F26 59 IO338PB7F31 7 IO237PB5F22 113 IO286NB6F26 54 IO341NB7F31 4 IO238NB5F22 104 IO286PB6F26 55 IO341PB7F31 5 IO238PB5F22 105 IO287NB6F26 52 IO239NB5F22 106 IO287PB6F26 53 GND 1 IO239PB5F22 107 IO294NB6F27 48 GND 9 IO240NB5F22 100 IO294PB6F27 49 GND 15 3- 11 2 R ev isio n 1 8 Dedicated I/O Axcelerator Family FPGAs CQ352 CQ352 CQ352 AX2000 Function Pin Number AX2000 Function Pin Number AX2000 Function Pin Number GND 21 GND 240 VCCA 150 GND 27 GND 246 VCCA 162 GND 33 GND 252 VCCA 175 GND 39 GND 258 VCCA 191 GND 45 GND 264 VCCA 209 GND 51 GND 265 VCCA 233 GND 57 GND 274 VCCA 251 GND 63 GND 280 VCCA 263 GND 69 GND 286 VCCA 279 GND 75 GND 292 VCCA 291 GND 81 GND 298 VCCA 329 GND 88 GND 310 VCCA 339 GND 89 GND 322 VCCDA 2 GND 97 GND 330 VCCDA 44 GND 103 GND 334 VCCDA 90 GND 109 GND 340 VCCDA 91 GND 115 GND 345 VCCDA 116 GND 121 GND 352 VCCDA 117 GND 133 PRA 312 VCCDA 130 GND 145 PRB 311 VCCDA 131 GND 151 PRC 135 VCCDA 132 GND 157 PRD 134 VCCDA 148 GND 163 TCK 349 VCCDA 149 GND 169 TDI 348 VCCDA 174 GND 176 TDO 347 VCCDA 178 GND 177 TMS 350 VCCDA 221 GND 186 TRST 351 VCCDA 266 GND 192 VCCA 3 VCCDA 268 GND 198 VCCA 14 VCCDA 293 GND 204 VCCA 32 VCCDA 294 GND 210 VCCA 56 VCCDA 307 GND 216 VCCA 74 VCCDA 308 GND 222 VCCA 87 VCCDA 309 GND 228 VCCA 102 VCCDA 327 GND 234 VCCA 114 VCCDA 328 R ev i si o n 1 8 3- 113 Package Pin Assignments CQ352 CQ352 AX2000 Function Pin Number AX2000 Function Pin Number VCCDA 346 VCCPLG 126 VCCIB0 321 VCCPLH 124 VCCIB0 333 VCOMPLA 318 VCCIB0 344 VCOMPLB 316 VCCIB1 273 VCOMPLC 304 VCCIB1 285 VCOMPLD 302 VCCIB1 297 VCOMPLE 141 VCCIB2 227 VCOMPLF 139 VCCIB2 239 VCOMPLG 127 VCCIB2 245 VCOMPLH 125 VCCIB2 257 VPUMP 267 VCCIB3 185 VCCIB3 197 VCCIB3 203 VCCIB3 215 VCCIB4 144 VCCIB4 156 VCCIB4 168 VCCIB5 96 VCCIB5 108 VCCIB5 120 VCCIB6 50 VCCIB6 62 VCCIB6 68 VCCIB6 80 VCCIB7 8 VCCIB7 20 VCCIB7 26 VCCIB7 38 VCCPLA 317 VCCPLB 315 VCCPLC 303 VCCPLD 301 VCCPLE 140 VCCPLF 138 3- 11 4 R ev isio n 1 8 Axcelerator Family FPGAs CG624 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Note For Package Manufacturing and Environmental information, visit Resource center at http://www.microsemi.com/soc/products/rescenter/package/index.html. R ev i si o n 1 8 3- 115 Package Pin Assignments CG624 AX1000 Function CG624 Pin Number Bank 0 3- 11 6 CG624 AX1000 Function Pin Number AX1000 Function Pin Number IO23NB0F2 E11 IO42NB1F4 G21 IO00NB0F0 F8 IO23PB0F2 F11 IO42PB1F4 G20 IO00PB0F0 F7 IO24NB0F2 D7 IO43NB1F4 A16 IO02NB0F0 G7 IO24PB0F2 E7 IO43PB1F4 A15 IO02PB0F0 G6 IO25PB0F2 B12 IO44NB1F4 A20 IO04NB0F0 E9 IO26NB0F2 H11 IO44PB1F4 A19 IO04PB0F0 D8 IO26PB0F2 G11 IO45NB1F4 B17 IO06NB0F0 G9 IO27NB0F2 C11 IO45PB1F4 B16 IO06PB0F0 G8 IO27PB0F2 B8 IO46NB1F4 G17 IO07PB0F0 B6 IO28NB0F2 J13 IO46PB1F4 H17 IO08NB0F0 F10 IO28PB0F2 K13 IO47NB1F4 A17 IO08PB0F0 F9 IO29NB0F2 J8 IO48NB1F4 C19 IO09PB0F0 C7 IO29PB0F2 J7 IO48PB1F4 C18 IO10NB0F0 H8 IO30NB0F2/HCLKAN G13 IO49NB1F4 B20 IO10PB0F0 H7 IO30PB0F2/HCLKAP G12 IO49PB1F4 B19 IO11NB0F0 D10 IO31NB0F2/HCLKBN C13 IO50NB1F4 H20 IO11PB0F0 D9 IO31PB0F2/HCLKBP C12 IO50PB1F4 H19 IO12NB0F1 B5 Bank 1 IO51NB1F4 A22 IO12PB0F1 B4 IO32NB1F3/HCLKCN G15 IO51PB1F4 A21 IO13NB0F1 A7 IO32PB1F3/HCLKCP G14 IO52NB1F4 C21 IO13PB0F1 A6 IO33NB1F3/HCLKDN B14 IO52PB1F4 C20 IO14NB0F1 C9 IO33PB1F3/HCLKDP B13 IO53NB1F4 B22 IO14PB0F1 C8 IO34NB1F3 G16 IO53PB1F4 B21 IO15PB0F1 B7 IO34PB1F3 H16 IO54NB1F5 J18 IO16NB0F1 A5 IO35NB1F3 C17 IO54PB1F5 J19 IO16PB0F1 A4 IO35PB1F3 B18 IO55NB1F5 D18 IO17NB0F1 A9 IO36NB1F3 H18 IO55PB1F5 D17 IO17PB0F1 B9 IO36PB1F3 H15 IO56NB1F5 F20 IO18NB0F1 D12 IO37NB1F3 H13 IO56PB1F5 F19 IO18PB0F1 D11 IO38NB1F3 E15 IO58NB1F5 E17 IO20NB0F1 B11 IO38PB1F3 F15 IO58PB1F5 F17 IO20PB0F1 B10 IO39NB1F3 D14 IO60NB1F5 D20 IO21NB0F1 A11 IO39PB1F3 C14 IO60PB1F5 D19 IO21PB0F1 A10 IO40NB1F3 D16 IO62NB1F5 E18 IO22NB0F2 H10 IO40PB1F3 D15 IO62PB1F5 F18 IO22PB0F2 H9 IO41NB1F4 F16 IO63NB1F5 G19 R ev isio n 1 8 Axcelerator Family FPGAs CG624 CG624 CG624 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO63PB1F5 G18 IO84NB2F7 M20 IO105NB3F9 R23 IO84PB2F7 M21 IO105PB3F9 P23 Bank 2 IO64NB2F6 M17 IO86NB2F8 E25 IO106NB3F9 R19 IO64PB2F6 G22 IO86PB2F8 D25 IO106PB3F9 R20 IO65NB2F6 J21 IO87NB2F8 L24 IO107NB3F10 AB24 IO65PB2F6 J20 IO87PB2F8 K24 IO108NB3F10 R25 IO66NB2F6 L23 IO88NB2F8 G24 IO108PB3F10 P25 IO66PB2F6 K20 IO88PB2F8 F24 IO109NB3F10 U25 IO67NB2F6 F23 IO89NB2F8 J25 IO109PB3F10 T25 IO67PB2F6 E23 IO90NB2F8 G25 IO110NB3F10 U24 IO68NB2F6 L18 IO90PB2F8 F25 IO110PB3F10 U23 IO68PB2F6 K18 IO91NB2F8 L25 IO112NB3F10 T24 IO70NB2F6 E24 IO91PB2F8 K25 IO112PB3F10 R24 IO70PB2F6 D24 IO92NB2F8 J24 IO113NB3F10 Y25 IO71NB2F6 H23 IO92PB2F8 H24 IO113PB3F10 W25 IO71PB2F6 G23 IO93PB2F8 J23 IO114NB3F10 V23 IO72NB2F6 L19 IO94NB2F8 N24 IO114PB3F10 V24 IO72PB2F6 K19 IO94PB2F8 M24 IO116NB3F10 AA24 IO74NB2F7 J22 IO95NB2F8 N25 IO116PB3F10 Y24 IO74PB2F7 H22 IO95PB2F8 M25 IO117NB3F10 AB25 IO75NB2F7 N23 IO117PB3F10 AA25 IO75PB2F7 M23 IO96NB3F9 T18 IO118NB3F11 T20 IO76NB2F7 N17 IO96PB3F9 R18 IO118PB3F11 R21 IO76PB2F7 N16 IO97NB3F9 N20 IO120NB3F11 W22 IO77NB2F7 L22 IO97PB3F9 P24 IO120PB3F11 W23 IO77PB2F7 K22 IO98NB3F9 P20 IO122NB3F11 V22 IO78NB2F7 M19 IO98PB3F9 P19 IO122PB3F11 U22 IO78PB2F7 M18 IO99NB3F9 P21 IO124NB3F11 Y23 IO79NB2F7 N19 IO100NB3F9 T22 IO124PB3F11 AA23 IO79PB2F7 N18 IO100PB3F9 W24 IO126NB3F11 V21 IO80NB2F7 L21 IO101NB3F9 R22 IO126PB3F11 U21 IO80PB2F7 L20 IO101PB3F9 P22 IO128NB3F11 Y22 IO82NB2F7 P18 IO102NB3F9 U19 IO128PB3F11 Y21 IO82PB2F7 P17 IO102PB3F9 T19 IO83NB2F7 N22 IO104NB3F9 V20 IO129NB4F12 W20 IO83PB2F7 M22 IO104PB3F9 U20 IO129PB4F12 Y20 Bank 3 R ev i si o n 1 8 Bank 4 3- 117 Package Pin Assignments CG624 CG624 CG624 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO131NB4F12 V19 IO153NB4F14 Y15 IO173PB5F16 Y11 IO131PB4F12 W19 IO153PB4F14 Y16 IO174NB5F16 AB10 IO133NB4F12 Y18 IO155NB4F14 V15 IO174PB5F16 AB11 IO133PB4F12 Y19 IO155PB4F14 V16 IO175NB5F16 AC9 IO135NB4F12 W18 IO156NB4F14 AB14 IO175PB5F16 AE9 IO135PB4F12 V18 IO156PB4F14 AB15 IO177NB5F16 AA8 IO137NB4F12 Y17 IO157NB4F14 AE14 IO177PB5F16 Y8 IO137PB4F12 AA17 IO157PB4F14 AC18 IO178NB5F16 Y6 IO138NB4F12 AB19 IO158NB4F14 AC15 IO178PB5F16 W6 IO138PB4F12 AB18 IO158PB4F14 AC19 IO179NB5F16 Y10 IO139NB4F13 AA19 IO159NB4F14/CLKEN W14 IO179PB5F16 W10 IO139PB4F13 U18 IO159PB4F14/CLKEP W15 IO180NB5F16 Y7 IO140NB4F13 AC20 IO160NB4F14/CLKFN AC13 IO180PB5F16 W7 IO140PB4F13 AC21 IO160PB4F14/CLKFP AD13 IO181NB5F17 AD9 IO141NB4F13 AD17 IO181PB5F17 AD10 IO141PB4F13 AD18 IO161NB5F15/CLKGN W13 IO182NB5F17 AE10 IO142NB4F13 AD21 IO161PB5F15/CLKGP Y13 IO182PB5F17 AE11 IO142PB4F13 AD22 IO162NB5F15/CLKHN AC12 IO183NB5F17 AD7 IO143NB4F13 AB17 IO162PB5F15/CLKHP AD12 IO183PB5F17 AD8 IO143PB4F13 AC17 IO163NB5F15 V9 IO184NB5F17 AB9 IO144PB4F13 AE22 IO163PB5F15 V10 IO185NB5F17 AE6 IO145NB4F13 AE15 IO164NB5F15 V11 IO185PB5F17 AE7 IO145PB4F13 AE16 IO164PB5F15 T13 IO186NB5F17 AE4 IO146NB4F13 AD19 IO165NB5F15 U13 IO186PB5F17 AE5 IO146PB4F13 AD20 IO165PB5F15 V13 IO187NB5F17 AA9 IO147NB4F13 AD15 IO167NB5F15 W11 IO187PB5F17 Y9 IO147PB4F13 AD16 IO167PB5F15 W12 IO188NB5F17 U8 IO148PB4F13 AE21 IO168NB5F15 AB6 IO189NB5F17 AD5 IO149NB4F13 AD14 IO168PB5F15 AA6 IO189PB5F17 AD6 IO149PB4F13 AC14 IO169NB5F15 V8 IO191NB5F17 AC5 IO150NB4F13 AE19 IO169PB5F15 V7 IO191PB5F17 AC6 IO150PB4F13 AE20 IO171NB5F16 W8 IO192NB5F17 AB7 IO151NB4F13 V17 IO171PB5F16 W9 IO192PB5F17 AC7 IO151PB4F13 W17 IO172NB5F16 AB8 IO152NB4F14 AB16 IO172PB5F16 AC8 IO193NB6F18 U6 IO152PB4F14 W16 IO173NB5F16 AA11 IO193PB6F18 U5 3- 11 8 Bank 5 R ev isio n 1 8 Bank 6 Axcelerator Family FPGAs CG624 CG624 CG624 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number IO194NB6F18 Y3 IO215PB6F20 V4 IO237NB7F22 N8 IO194PB6F18 AA3 IO216NB6F20 P8 IO237PB7F22 N7 IO195NB6F18 V6 IO216PB6F20 R3 IO238NB7F22 M5 IO195PB6F18 W4 IO217NB6F20 P7 IO239NB7F22 L6 IO197NB6F18 R5 IO217PB6F20 R7 IO239PB7F22 L5 IO197PB6F18 U3 IO219NB6F20 R4 IO240NB7F22 M4 IO198NB6F18 P6 IO219PB6F20 T4 IO241NB7F22 L7 IO199NB6F18 Y5 IO220NB6F20 P2 IO241PB7F22 M7 IO199PB6F18 W5 IO220PB6F20 R2 IO242NB7F22 J3 IO200NB6F18 V3 IO221NB6F20 N4 IO243NB7F22 M9 IO200PB6F18 W3 IO221PB6F20 P4 IO243PB7F22 M8 IO201NB6F18 T7 IO223NB6F20 M2 IO244NB7F22 P9 IO201PB6F18 U7 IO223PB6F20 N2 IO244PB7F22 N6 IO202NB6F18 V2 IO224NB6F20 N3 IO245NB7F22 K8 IO203NB6F19 W2 IO224PB6F20 P3 IO245PB7F22 L8 IO203PB6F19 Y2 IO246NB7F22 F3 IO204NB6F19 AA1 IO225NB7F21 J2 IO246PB7F22 E3 IO204PB6F19 AB1 IO225PB7F21 J1 IO247NB7F23 K7 IO205NB6F19 R6 IO226PB7F21 G2 IO247PB7F23 K6 IO205PB6F19 T6 IO227NB7F21 H3 IO248NB7F23 D2 IO206NB6F19 W1 IO227PB7F21 H2 IO249NB7F23 G4 IO206PB6F19 Y1 IO229NB7F21 K2 IO249PB7F23 G3 IO207NB6F19 T2 IO229PB7F21 L2 IO251NB7F23 N10 IO207PB6F19 U2 IO230NB7F21 K1 IO251PB7F23 N9 IO208NB6F19 T1 IO230PB7F21 L1 IO253NB7F23 H4 IO208PB6F19 U1 IO231NB7F21 E2 IO253PB7F23 J4 IO209NB6F19 AA2 IO231PB7F21 F2 IO255NB7F23 J6 IO209PB6F19 AB2 IO232NB7F21 F1 IO255PB7F23 J5 IO210NB6F19 P5 IO232PB7F21 G1 IO257NB7F23 H5 IO211NB6F19 M1 IO233NB7F21 L3 IO257PB7F23 H6 IO211PB6F19 N1 IO233PB7F21 M3 IO212NB6F19 P1 IO234NB7F21 D1 GND K5 IO212PB6F19 R1 IO234PB7F21 E1 GND A18 IO213NB6F19 R8 IO235NB7F21 K4 GND A2 IO213PB6F19 T8 IO235PB7F21 L4 GND A24 IO215NB6F20 U4 IO236NB7F22 M6 GND A25 Bank 7 R ev i si o n 1 8 Dedicated I/O 3- 119 Package Pin Assignments CG624 CG624 CG624 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number GND A8 GND/LP E8 GND V1 GND AA10 GND H1 GND V25 GND AA16 GND H21 GND V5 GND AA18 GND H25 NC A14 GND AA21 GND K21 NC AA20 GND AA5 GND K23 NC AB13 GND AB22 GND K3 NC AD4 GND AB4 GND L11 NC AE12 GND AC10 GND L12 NC F21 GND AC16 GND L13 NC G10 GND AC23 GND L14 PRA F13 GND AC3 GND L15 PRB A13 GND AD1 GND M11 PRC AB12 GND AD2 GND M12 PRD AE13 GND AD24 GND M13 TCK F5 GND AD25 GND M14 TDI C5 GND AE1 GND M15 TDO F6 GND AE18 GND N11 TMS D6 GND AE2 GND N12 TRST E6 GND AE24 GND N13 VCCA AB20 GND AE25 GND N14 VCCA F22 GND AE8 GND N15 VCCA F4 GND B1 GND P11 VCCA J17 GND B2 GND P12 VCCA J9 GND B24 GND P13 VCCA K10 GND B25 GND P14 VCCA K11 GND C10 GND P15 VCCA K15 GND C16 GND R11 VCCA K16 GND C23 GND R12 VCCA L10 GND C3 GND R13 VCCA L16 GND D22 GND R14 VCCA R10 GND D4 GND R15 VCCA R16 GND E10 GND T21 VCCA T10 GND E16 GND T23 VCCA T11 GND E21 GND T3 VCCA T15 GND E5 GND T5 VCCA T16 3- 12 0 R ev isio n 1 8 Axcelerator Family FPGAs CG624 CG624 CG624 AX1000 Function Pin Number AX1000 Function Pin Number AX1000 Function Pin Number VCCA U17 VCCIB2 D23 VCCIB7 E4 VCCA U9 VCCIB2 E22 VCCIB7 K9 VCCA Y4 VCCIB2 K17 VCCIB7 L9 VCCDA A12 VCCIB2 L17 VCCIB7 M10 VCCDA AA13 VCCIB2 M16 VCCPLA E12 VCCDA AA15 VCCIB3 AA22 VCCPLB J12 VCCDA AA7 VCCIB3 AB23 VCCPLC E14 VCCDA AC11 VCCIB3 AC24 VCCPLD H14 VCCDA AD11 VCCIB3 AC25 VCCPLE Y14 VCCDA AE17 VCCIB3 P16 VCCPLF U14 VCCDA B15 VCCIB3 R17 VCCPLG Y12 VCCDA C15 VCCIB3 T17 VCCPLH U12 VCCDA C6 VCCIB4 AB21 VCOMPLA F12 VCCDA D13 VCCIB4 AC22 VCOMPLB H12 VCCDA E13 VCCIB4 AD23 VCOMPLC F14 VCCDA E19 VCCIB4 AE23 VCOMPLD J14 VCCDA G5 VCCIB4 T14 VCOMPLE AA14 VCCDA N21 VCCIB4 U15 VCOMPLF V14 VCCDA N5 VCCIB4 U16 VCOMPLG AA12 VCCDA W21 VCCIB5 AB5 VCOMPLH V12 VCCIB0 A3 VCCIB5 AC4 VPUMP E20 VCCIB0 B3 VCCIB5 AD3 VCCIB0 C4 VCCIB5 AE3 VCCIB0 D5 VCCIB5 T12 VCCIB0 J10 VCCIB5 U10 VCCIB0 J11 VCCIB5 U11 VCCIB0 K12 VCCIB6 AA4 VCCIB1 A23 VCCIB6 AB3 VCCIB1 B23 VCCIB6 AC1 VCCIB1 C22 VCCIB6 AC2 VCCIB1 D21 VCCIB6 P10 VCCIB1 J15 VCCIB6 R9 VCCIB1 J16 VCCIB6 T9 VCCIB1 K14 VCCIB7 C1 VCCIB2 C24 VCCIB7 C2 VCCIB2 C25 VCCIB7 D3 R ev i si o n 1 8 3- 121 Package Pin Assignments CG624 AX2000 Function CG624 Pin Number Bank 0 Pin Number AX2000 Function Pin Number IO27NB0F2 H10 IO51NB1F4 E15 IO00NB0F0 D7* IO27PB0F2 H9 IO51PB1F4 F15 IO00PB0F0 E7* IO28NB0F2 A9 IO52NB1F4 A17 IO01NB0F0 G7 IO28PB0F2 B9 IO55NB1F5 G16 IO01PB0F0 G6 IO30NB0F2 B11 IO55PB1F5 H16 IO02NB0F0 B5 IO30PB0F2 B10 IO56NB1F5 A20 IO02PB0F0 B4 IO31NB0F2 E11 IO56PB1F5 A19 IO04PB0F0 C7 IO31PB0F2 F11 IO57NB1F5 D16 IO05NB0F0 F8 IO33NB0F2 D12 IO57PB1F5 D15 IO05PB0F0 F7 IO33PB0F2 D11 IO58NB1F5 A22 IO06NB0F0 H8 IO34NB0F3 A11 IO58PB1F5 A21 IO06PB0F0 H7 IO34PB0F3 A10 IO59NB1F5 F16 IO11NB0F0 J8 IO37NB0F3 J13 IO61NB1F5 G17 IO11PB0F0 J7 IO37PB0F3 K13 IO61PB1F5 H17 IO12PB0F1 B6 IO38NB0F3 H11 IO62NB1F5 B17 IO13NB0F1 E9* IO38PB0F3 G11 IO62PB1F5 B16 IO13PB0F1 D8* IO40PB0F3 B12 IO63NB1F5 H18 IO15NB0F1 C9 IO41NB0F3/HCLKAN G13 IO65NB1F6 C17 IO15PB0F1 C8 IO41PB0F3/HCLKAP G12 IO66PB1F6 B18 IO16NB0F1 A5 IO42NB0F3/HCLKBN C13 IO67NB1F6 J18 IO16PB0F1 A4 IO42PB0F3/HCLKBP C12 IO67PB1F6 J19 IO17NB0F1 D10 IO68NB1F6 B20 IO17PB0F1 D9 IO43NB1F4/HCLKCN G15 IO68PB1F6 B19 IO18NB0F1 A7 IO43PB1F4/HCLKCP G14 IO69NB1F6 E17 IO18PB0F1 A6 IO44NB1F4/HCLKDN B14 IO69PB1F6 F17 IO19NB0F1 G9 IO44PB1F4/HCLKDP B13 IO70NB1F6 B22 IO19PB0F1 G8 IO45NB1F4 H13 IO70PB1F6 B21 IO20PB0F1 B7 IO47NB1F4 D14 IO71PB1F6 G18 IO23NB0F2 F10 IO47PB1F4 C14 IO73NB1F6 G19 IO23PB0F2 F9 IO48NB1F4 A16 IO74NB1F6 C19 IO26NB0F2 C11* IO48PB1F4 A15 IO74PB1F6 C18 IO26PB0F2 B8* IO49PB1F4 H15 IO75NB1F6 D18 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 12 2 AX2000 Function CG624 Bank 1 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev isio n 1 8 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs CG624 AX2000 Function CG624 Pin Number AX2000 Function CG624 Pin Number AX2000 Function Pin Number IO75PB1F6 D17 IO99PB2F9 K19 IO127NB2F11 P18 IO76NB1F7 C21 IO100NB2F9 E25 IO127PB2F11 P17 IO76PB1F7 C20 IO100PB2F9 D25 IO128NB2F11 N25 IO79NB1F7 H20 IO103PB2F9 K20 IO128PB2F11 M25 IO79PB1F7 H19 IO105NB2F9 M19 IO80NB1F7 E18 IO105PB2F9 M18 IO129NB3F12 N20 IO80PB1F7 F18 IO106NB2F9 J24 IO130PB3F12 P24 IO81NB1F7 G21 IO106PB2F9 H24 IO131NB3F12 P21 IO81PB1F7 G20 IO107NB2F10 L23* IO133NB3F12 P20 IO82NB1F7 F20 IO107PB2F10 N16* IO133PB3F12 P19 IO82PB1F7 F19 IO109NB2F10 L22 IO138NB3F12 R23 IO85NB1F7 D20* IO109PB2F10 K22 IO138PB3F12 P23 IO85PB1F7 D19* IO110NB2F10 G25 IO139NB3F13 R22 IO110PB2F10 F25 IO139PB3F13 P22 Bank 2 Bank 3 IO86NB2F8 F23 IO111NB2F10 L21 IO141NB3F13 R19 IO86PB2F8 E23 IO111PB2F10 L20 IO142NB3F13 R25 IO87NB2F8 H23 IO112NB2F10 L24 IO142PB3F13 P25 IO87PB2F8 G23 IO112PB2F10 K24 IO143PB3F13 R21 IO88NB2F8 E24 IO113NB2F10 N17 IO145NB3F13 T18 IO88PB2F8 D24 IO115NB2F10 M20 IO145PB3F13 R18 IO89NB2F8 M17* IO115PB2F10 M21 IO146NB3F13 T24 IO89PB2F8 G22* IO117NB2F10 N19 IO146PB3F13 R24 IO91NB2F8 J22 IO117PB2F10 N18 IO147NB3F13 T20 IO91PB2F8 H22 IO118NB2F11 J25 IO147PB3F13 R20 IO92NB2F8 L18 IO121NB2F11 N24 IO148NB3F13 U25 IO92PB2F8 K18 IO121PB2F11 M24 IO148PB3F13 T25 IO96NB2F9 G24 IO122NB2F11 L25 IO149NB3F13 T22 IO96PB2F9 F24 IO122PB2F11 K25 IO153NB3F14 U19 IO97NB2F9 J21 IO123NB2F11 N22 IO153PB3F14 T19 IO97PB2F9 J20 IO123PB2F11 M22 IO154NB3F14 Y25 IO98PB2F9 J23 IO124NB2F11 N23 IO154PB3F14 W25 IO99NB2F9 L19 IO124PB2F11 M23 IO157NB3F14 V20 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev i si o n 1 8 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 123 Package Pin Assignments CG624 AX2000 Function CG624 Pin Number Pin Number AX2000 Function Pin Number IO157PB3F14 U20 IO177PB4F16 AB18 IO208PB4F19 W16 IO158NB3F14 AB25 IO182NB4F17 V19 IO209NB4F19 AE14 IO158PB3F14 AA25 IO182PB4F17 W19 IO210NB4F19 V15 IO160PB3F14 W24 IO183PB4F17 AC19 IO210PB4F19 V16 IO161NB3F15 U24 IO184NB4F17 AB17 IO211NB4F19 AD14 IO161PB3F15 U23 IO184PB4F17 AC17 IO211PB4F19 AC14 IO162NB3F15 AA24 IO185NB4F17 AD19 IO212NB4F19/CLKEN W14 IO162PB3F15 Y24 IO185PB4F17 AD20 IO212PB4F19/CLKEP W15 IO163NB3F15 V22 IO187PB4F17 AC18 IO213NB4F19/CLKFN AC13 IO163PB3F15 U22 IO188NB4F17 Y17 IO213PB4F19/CLKFP AD13 IO164NB3F15 V23 IO188PB4F17 AA17 IO164PB3F15 V24 IO189PB4F17 AE22 IO214NB5F20/CLKGN W13 IO166NB3F15 AB24 IO191NB4F17 W18 IO214PB5F20/CLKGP Y13 IO167NB3F15 V21 IO191PB4F17 V18 IO215NB5F20/CLKHN AC12 IO167PB3F15 U21 IO192PB4F17 U18 IO215PB5F20/CLKHP AD12 IO168NB3F15 Y23 IO195PB4F18 AE21 IO216NB5F20 U13 IO168PB3F15 AA23 IO196NB4F18 AB16 IO216PB5F20 V13 IO169NB3F15 W22* IO197NB4F18 AD17 IO217NB5F20 AE10 IO169PB3F15 W23* IO197PB4F18 AD18 IO217PB5F20 AE11 IO170NB3F15 Y22 IO198NB4F18 V17 IO218NB5F20 W11 IO170PB3F15 Y21 IO198PB4F18 W17 IO218PB5F20 W12 IO199NB4F18 AE19 IO222NB5F20 AA11 Bank 4 Bank 5 IO171NB4F16 AC20* IO199PB4F18 AE20 IO222PB5F20 Y11 IO171PB4F16 AC21* IO200NB4F18 AC15 IO223PB5F21 AE9 IO172NB4F16 W20 IO201NB4F18 AD15 IO225NB5F21 AE6 IO172PB4F16 Y20 IO201PB4F18 AD16 IO225PB5F21 AE7 IO173NB4F16 AD21 IO202NB4F18 Y15 IO226NB5F21 Y10 IO173PB4F16 AD22 IO202PB4F18 Y16 IO226PB5F21 W10 IO174NB4F16 AA19 IO206NB4F19 AB14 IO227PB5F21 T13 IO176NB4F16 Y18 IO206PB4F19 AB15 IO228NB5F21 AB10 IO176PB4F16 Y19 IO207NB4F19 AE15 IO228PB5F21 AB11 IO177NB4F16 AB19 IO207PB4F19 AE16 IO229NB5F21 AD9 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 12 4 AX2000 Function CG624 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev isio n 1 8 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs CG624 AX2000 Function CG624 Pin Number AX2000 Function IO229PB5F21 AD10 IO230NB5F21 V11 IO233NB5F21 AD7 IO257NB6F24 IO233PB5F21 AD8 IO234NB5F21 CG624 Pin Number AA6* Pin Number IO284NB6F26 R8 IO284PB6F26 T8 Y3 IO285NB6F26 W1 IO257PB6F24 AA3 IO285PB6F26 Y1 V9 IO258NB6F24 V3 IO286NB6F26 P2 IO234PB5F21 V10 IO258PB6F24 W3 IO286PB6F26 R2 IO236NB5F22 AC9 IO259NB6F24 AA2 IO287NB6F26 T1 IO238NB5F22 W8 IO259PB6F24 AB2 IO287PB6F26 U1 IO238PB5F22 W9 IO260NB6F24 V6* IO288NB6F26 P5 IO239NB5F22 AE4 IO260PB6F24 W4* IO290NB6F27 P6 IO239PB5F22 AE5 IO262NB6F24 U4 IO291NB6F27 P1 IO240NB5F22 AB9 IO262PB6F24 V4 IO291PB6F27 R1 IO242NB5F22 AA9 IO263NB6F24 Y5 IO292NB6F27 P7 IO242PB5F22 Y9 IO263PB6F24 W5 IO292PB6F27 R7 IO243NB5F22 AD5 IO268NB6F25 U6 IO293NB6F27 M1 IO243PB5F22 AD6 IO268PB6F25 U5 IO293PB6F27 N1 IO244NB5F22 U8 IO269PB6F25 U3 IO294NB6F27 P8 IO246NB5F23 AB8 IO272NB6F25 T2 IO296NB6F27 N3 IO246PB5F23 AC8 IO272PB6F25 U2 IO296PB6F27 P3 IO247NB5F23 AB7 IO273NB6F25 W2 IO298NB6F27 N4 IO247PB5F23 AC7 IO273PB6F25 Y2 IO298PB6F27 P4 IO250NB5F23 AA8 IO274NB6F25 R6 IO299NB6F27 M2 IO250PB5F23 Y8 IO274PB6F25 T6 IO299PB6F27 N2 IO251NB5F23 V8 IO275NB6F25 T7 IO251PB5F23 V7 IO275PB6F25 U7 IO300NB7F28 P9* IO252NB5F23 Y7 IO277NB6F25 V2 IO300PB7F28 N6* IO252PB5F23 W7 IO278NB6F26 R4 IO302NB7F28 M6 IO253NB5F23 AC5 IO278PB6F26 T4 IO304NB7F28 N8 IO253PB5F23 AC6 IO279PB6F26 R3 IO304PB7F28 N7 IO254NB5F23 Y6 IO280NB6F26 R5 IO308NB7F28 M4 IO254PB5F23 W6 IO281NB6F26 AA1 IO309NB7F28 L3 IO256NB5F23 AB6* IO281PB6F26 AB1 IO309PB7F28 M3 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. IO256PB5F23 AX2000 Function Bank 6 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev i si o n 1 8 Bank 7 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 125 Package Pin Assignments CG624 AX2000 Function CG624 Pin Number Pin Number AX2000 Function Pin Number IO310NB7F29 N10 IO335PB7F31 H6 GND AE1 IO310PB7F29 N9 IO337NB7F31 D2 GND AE18 IO311NB7F29 K1 IO338NB7F31 J6 GND AE2 IO311PB7F29 L1 IO338PB7F31 J5 GND AE24 IO313NB7F29 M5 IO339NB7F31 F3 GND AE25 IO316NB7F29 L6 IO339PB7F31 E3 GND AE8 IO316PB7F29 L5 IO340NB7F31 G4* GND B1 IO317NB7F29 K2 IO340PB7F31 G3* GND B2 IO317PB7F29 L2 IO341NB7F31 K8 GND B24 IO318NB7F29 K4 IO341PB7F31 L8 GND B25 IO318PB7F29 L4 GND C10 IO320NB7F29 J3 GND K5 GND C16 IO321NB7F30 J2 GND A18 GND C23 IO321PB7F30 J1 GND A2 GND C3 IO323NB7F30 L7 GND A24 GND D22 IO323PB7F30 M7 GND A25 GND D4 IO324NB7F30 M9 GND A8 GND E10 IO324PB7F30 M8 GND AA10 GND E16 IO327NB7F30 F1 GND AA16 GND E21 IO327PB7F30 G1 GND AA18 GND E5 IO328NB7F30 K7 GND AA21 GND E8 IO328PB7F30 K6 GND AA5 GND H1 IO329NB7F30 D1 GND AB22 GND H21 IO329PB7F30 E1 GND AB4 GND H25 IO331PB7F30 G2 GND AC10 GND K21 IO332NB7F31 H3 GND AC16 GND K23 IO332PB7F31 H2 GND AC23 GND K3 IO333NB7F31 E2 GND AC3 GND L11 IO333PB7F31 F2 GND AD1 GND L12 IO334NB7F31 H4 GND AD2 GND L13 IO334PB7F31 J4 GND AD24 GND L14 IO335NB7F31 H5 GND AD25 GND L15 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 12 6 AX2000 Function CG624 Dedicated I/O Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev isio n 1 8 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Axcelerator Family FPGAs CG624 AX2000 Function CG624 Pin Number AX2000 Function CG624 Pin Number AX2000 Function Pin Number GND M11 TDI C5 VCCDA AD11 GND M12 TDO F6 VCCDA AD4 GND M13 TMS D6 VCCDA AE12 GND M14 TRST E6 VCCDA AE17 GND M15 VCCA AB20 VCCDA B15 GND N11 VCCA F22 VCCDA C15 GND N12 VCCA F4 VCCDA C6 GND N13 VCCA J17 VCCDA D13 GND N14 VCCA J9 VCCDA E13 GND N15 VCCA K10 VCCDA E19 GND P11 VCCA K11 VCCDA F21 GND P12 VCCA K15 VCCDA G10 GND P13 VCCA K16 VCCDA G5 GND P14 VCCA L10 VCCDA N21 GND P15 VCCA L16 VCCDA N5 GND R11 VCCA R10 VCCDA W21 GND R12 VCCA R16 VCCIB0 A3 GND R13 VCCA T10 VCCIB0 B3 GND R14 VCCA T11 VCCIB0 C4 GND R15 VCCA T15 VCCIB0 D5 GND T21 VCCA T16 VCCIB0 J10 GND T23 VCCA U17 VCCIB0 J11 GND T3 VCCA U9 VCCIB0 K12 GND T5 VCCA Y4 VCCIB1 A23 GND V1 VCCDA A12 VCCIB1 B23 GND V25 VCCDA A14 VCCIB1 C22 GND V5 VCCDA AA13 VCCIB1 D21 PRA F13 VCCDA AA15 VCCIB1 J15 PRB A13 VCCDA AA20 VCCIB1 J16 PRC AB12 VCCDA AA7 VCCIB1 K14 PRD AE13 VCCDA AB13 VCCIB2 C24 TCK F5 VCCDA AC11 VCCIB2 C25 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. R ev i si o n 1 8 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 127 Package Pin Assignments CG624 CG624 AX2000 Function Pin Number AX2000 Function Pin Number VCCIB2 D23 VCCIB6 T9 VCCIB2 E22 VCCIB7 C1 VCCIB2 K17 VCCIB7 C2 VCCIB2 L17 VCCIB7 D3 VCCIB2 M16 VCCIB7 E4 VCCIB3 AA22 VCCIB7 K9 VCCIB3 AB23 VCCIB7 L9 VCCIB3 AC24 VCCIB7 M10 VCCIB3 AC25 VCCPLA E12 VCCIB3 P16 VCCPLB J12 VCCIB3 R17 VCCPLC E14 VCCIB3 T17 VCCPLD H14 VCCIB4 AB21 VCCPLE Y14 VCCIB4 AC22 VCCPLF U14 VCCIB4 AD23 VCCPLG Y12 VCCIB4 AE23 VCCPLH U12 VCCIB4 T14 VCOMPLA F12 VCCIB4 U15 VCOMPLB H12 VCCIB4 U16 VCOMPLC F14 VCCIB5 AB5 VCOMPLD J14 VCCIB5 AC4 VCOMPLE AA14 VCCIB5 AD3 VCOMPLF V14 VCCIB5 AE3 VCOMPLG AA12 VCCIB5 T12 VCOMPLH V12 VCCIB5 U10 VPUMP E20 VCCIB5 U11 VCCIB6 AA4 VCCIB6 AB3 VCCIB6 AC1 VCCIB6 AC2 VCCIB6 P10 VCCIB6 R9 Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O. 3- 12 8 R ev isio n 1 8 4 - Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Revision Revision 18 (March 2012) Changes Page Table 2-1 * Absolute Maximum Ratings was updated to correct the maximum DC core supply voltage (VCCA) from 1.6 V to 1.7 V (SAR 36786). The maximum input voltage (VI) was corrected from 3.75 V to 4.1 V (SAR 35419). 2-1 Values for tristate leakage current IOZ, and IIH and IIL were added to Table 2-3 * Standby Current (SARs 35774, 32021). 2-2 Figure 2-2 * VCCPLX and VCOMPLX Power Supply Connect was updated to correct the units for the resistance from "W" to (SAR 36415). 2-9 In the Introduction to the "User I/Os" section, the following sentence was added to clarify the slew rate setting (SAR 34943): 2-11 The slew rate setting is effective for both rising and falling edges. Revision 17 (September 2011) Figure 2-3 * Use of an External Resistor for 5 V Tolerance was revised to show the VCCI and GND clamp diodes. The explanatory text above the figure was revised as well (SAR 34942). 2-13 EQ 3 for 5 V tolerance was corrected to change Vdiode from 0.6 V to 0.7 V (SAR 36786). 2-13 Additional information was added to the "Using the Weak Pull-Up and Pull-Down Circuits" section to clarify how the weak pull-up and pull-down resistors are physically implemented (SAR 34945). 2-17 The description for the CINCLK parameter in Table 2-18 * Input Capacitance was changed from "Input capacitance on clock pin" to "Input capacitance on HCLK and RCLK pin" (SAR 34944). 2-21 Table 2-19 * I/O Input Rise Time and Fall Time* is new (SAR 34942). 2-21 The minimum VIL for 1.5 V LVCMOS and PCI was corrected from -0.5 to -0.3 in Table 2-29 * DC Input and Output Levels and Table 2-33 * DC Input and Output Levels (SAR 34358). 2-38, 2-40 Support for simulating the GCLR/ GPSET feature in the Axcelerator Family was added in Libero software v9.0 SPI1. Reference to the section explaining this in the Antifuse Macro Library Guide was added to the "R-Cell" section (SAR 26413). 2-58 The enable signal in Figure 2-32 * R-Cell Delays was corrected to show it is active low rather than active high (SAR 34946). 2-59 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "Axcelerator Family Device Status" table indicates the status for each device in the device family. iii The "Features" section, "Programmable Interconnect Element" section, and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 32865). i, 1-1, 2-108 R ev i si o n 1 8 4 -1 Datasheet Information Revision Revision 17 (continued) Changes Page The C180 package was removed from product tables and the "Package Pin Assignments" section (PDN 0909). 3-1 Package names used in the"Axcelerator Family Product Profile" and "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 27395). i, 3-1 The "Introduction" section for "User I/Os" was updated as follows: 2-11 "The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed only for input and bidirectional I/Os" (SARs 24181, 24309). Power values in Table 2-4 * Default CLOAD/VCCI were updated to reflect those of SmartPower (SAR 33945). 2-3 Two parameter names were corrected in Figure 2-10 * Output Buffer Delays. One occurrence of tENLZ was changed to tENZL and one occurrence of tENHZ was changed to tENZH (SAR 33890). 2-22 The "Timing Model" section was updated with new timing values. Timing tables in the "I/O Specifications" section were updated to include enable paths. Values in the timing tables in the "Voltage-Referenced I/O Standards" section and "Differential Standards" section were updated. Table 2-63 * R-Cell was updated (SAR 33945). 2-8, 2-26 to 2-53 Figure 2-11 * Timing Model was replaced (SAR 33043). The timing tables for "RAM" and "FIFO" were updated (SAR 33945). Revision 16 (v2.8, Oct. 2009) 2-23 2-90 to 2-106 "Data Registers (DRs)" values were modified for IDCODE and USERCODE (SARs 18257, 26406). 2-108 The package diagram for the "CQ208" package was incorrect and has been replaced with the correct diagram (SARs 23865, 26345). 3-89 The datasheet was updated to include AX2000-CQ2526 information. N/A MIL-STD-883 Class B is no longer supported by Axcelerator FPGAs and as a result was removed. N/A A footnote was added to the "Introduction" in the "Axcelerator Clock Management System" section. 2-75 Revision 15 (v2.7, Nov. 2008) RoHS-compliant information was added to the "Ordering Information". ACTgen was changed to SmartGen because ACTgen is obsolete. N/A Revision 14 (v2.6) In Table 2-4, the units for the PLOAD, P10, and PI/O were updated from mW/MHz to mW/MHz. 2-3 In the "Pin Descriptions"section, the HCLK and CLK descriptions were updated to include tie-off information. 2-9 The "Global Resource Distribution" section was updated. 2-70 The " CG624" table was updated. 3-116 Revision 13 (v2.5) 4- 2 ii A note was added to Table 2-2. 2-1 In the "Package Thermal Characteristics", the temperature was changed from 150C to 125C. 2-6 R ev isio n 1 8 Axcelerator Family FPGAs Revision Revision 12 (v2.4) Revision 11 (v2.3) Revision 10 (v2.2) Changes Page Revised ordering information and timing data to reflect phase out of -3 speed grade options. Table 2-3 was updated. 2 The "Packaging Data" section is new. iv Table 2-2 was updated. 2-1 "VCCDA Supply Voltage" was updated. 2-9 "PRA/B/C/D Probe A, B, C and D" was updated. 2-10 The "User I/Os" was updated. 2-11 Figure 1-3 was updated. 1-2 Table 2-2 was updated. 2-1 The "Power-Up/Down Sequence" section was updated. 2-1 Table 2-4 was updated. 2-3 Table 2-5 was updated. 2-4 The "Timing Characteristics" section was added. 2-7 Table 2-7 was updated. 2-7 Figure 2-1 was updated. 2-8 The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired Clock - Using LVTTL 24 mA High Slew Clock I/O" section were updated. 2-8 The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock - Using LVTTL 24 mA High Slew Clock I/O" section were updated. 2-8 The "Global Pins" section was updated. 2-10 The "User I/Os" section was updated. 2-11 Table 2-17 was updated. 2-19 Figure 2-8 was updated. 2-20 Figure 2-13 and Figure 2-14 were updated. 2-24 The following timing parameters were renamed in I/O timing characteristic tables from Table 2-22 to Table 2-60: 2-26 to 2-52 tIOCLKQ > tICLKQ tIOCLKY > tOCLKQ Timing numbers were updated from Table 2-22 to Table 2-78. 2-26 to 2-69 The "R-Cell" section was updated. 2-58 Figure 2-59 was updated. 2-89 Figure 2-60 was updated. 2-89 Figure 2-67 was updated. 2-100 Figure 2-68 was updated. 2-101 Table 2-89 to Table 2-93 were updated. 2-90 to 2-94 Table 2-98 to Table 2-102 were updated. 2-102 to 2-106 R ev i si o n 1 8 4 -3 Datasheet Information Revision Revision 10 (continued) Revision 9 (v2.1) Revision 8 (v2.0) Changes The "TRST" section was updated. 2-107 The "Global Set Fuse" section was added. 2-109 A footnote was added to "FG896" for the AX2000 regarding pins AB1, AE2, G1, and K2. 3-52 Pinouts for the AX250, AX500, and AX1000 were added for "CQ352". 3-98 Pinout for the AX1000 was added for "CG624". 3-115 Table 2-79 was updated. 2-69 The "Low Power Mode" section was updated. 2-106 Table 1 has been updated. i The "Ordering Information" section has been updated. ii The "Device Resources" section has been updated. ii The "Temperature Grade Offerings" section is new. iii The "Speed Grade and Temperature Grade Matrix" section has been updated. iii Table 2-9 has been updated. 2-12 Table 2-10 has been updated. 2-12 Table 2-1 has been updated. 2-1 Table 2-2 has been updated. 2-1 Table 2-3 has been updated. 2-2 Table 2-4 has been updated. 2-3 Table 2-5 has been updated. 2-4 The "Power Estimation Example" section has been updated. 2-5 The "Thermal Characteristics" section has been updated. 2-6 The "Package Thermal Characteristics" section has been updated. 2-6 The "Timing Characteristics" section has been updated. 2-7 The "Pin Descriptions" section has been updated. 2-9 Timing numbers have been updated from the "3.3 V LVTTL" section to the "Timing Characteristics" section. Many AC Loads were updated as well. 2-25 to 2-59 Timing characteristics for the "Hardwired Clocks" and "Routed Clocks" sections were updated. 2-66, 2-68 Table 2-89 to Table 2-92 and Table 2-98 to Table 2-99 were updated. The following sections were updated: "Low Power Mode", "Interface", "Data Registers (DRs)", "Security", "Silicon Explorer II Probe Interface", and "Programming" In the "PQ208" (AX500) section, pins 2, 52, and 156 changed from VCCDA to VCCA. For pins 170 and 171, the I/O names refer to pair 23 instead of 24. 4- 4 Page R ev isio n 1 8 2-90 to 2-93, 2-102 to 2-103 2-106 to 2-110 3-84 Axcelerator Family FPGAs Revision Revision 8 (continued) Changes The following changes were made in the "FG676"(AX500) section: AE2, AE25 Change from NC to GND. AF2, AF25 Changed from GND to NC AB4, AF24, C1, C26 Changed from VCCDA to VCCA AD15 Change from VCCDA to VCOMPLE AD17 Changed from VCOMPLE to VCCDA 3-37 In the "FG896" (AX2000) section, the AK28 changed from VCCIB5 to VCCIB4. 3-52 The "CQ352" and "CG624" sections are new. Revision 7 (Advance v1.6) Revision 6 (Advance v1.5) Revision 5 (Advance v1.4) Page All I/O FIFO capability was removed. Table 1 was updated. 3-98, 3-115 n/a i Figure 1-9 was updated. 1-7 Figure 2-5 was updated. 2-16 The "Using an I/O Register" section was updated. 2-16 The AX250 and AX1000 descriptions were added to the "FG484"section. 3-21 Table 2-3 was updated. 2-2 Figure 2-1 was updated. 2-8 Figure 2-48 was updated. 2-75 Figure 2-52 was updated. 2-82 In the "PQ208" table, pin 196 was missing, but it has been added in this version with a function of GND. 3-84 The following pins in the "FG484" table for AX500 were changed: 3-21 Pin G7 is GND/LP Pins AB8, C10, C11, C14, AB16 are NC. The "FG676" table was updated. Revision 4 (Advance v1.3) Revision 3 (Advance v1.2) 3-37 The "Device Resources" section was updated for the CS180. The "Programmable Interconnect Element" and Figure 1-2 are new. ii 1-1 and 1-2 The "CS180" table is new. 3-1 The "PQ208" tables for the AX500 were updated. The following pins were not defined in the previous version: GND 21 IO106PB5F10/CLKHP 71 GND 136 3-84 Table 1, "Ordering Information", "Device Resources", and the Product Plan table were updated. i, ii The following figures and tables were updated: Figure 1-3 Figure 1-8 (new) Table 2-3 Figure 2-2 Table 2-8 Figure 2-11 1-2 1-6 2-2 2-9 2-12 2-23 The "Design Environment" section was updated. 1-7 The "Package Thermal Characteristics" was updated. 2-6 R ev i si o n 1 8 4 -5 Datasheet Information Revision Revision 3 (continued) Changes The timing characteristics tables from pages 2-26 to 2-60 were updated. The "Global Resources" section was updated. The timing characteristics tables from pages 2-102 to 2-103 were updated. The "PQ208", "FG256", and "FG324" tables are new. 4- 6 R ev isio n 1 8 Page 2-26 to 2-60 2-66 2-102 to 2-103 3-9,3-16, 3-84 Axcelerator Family FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "Axcelerator Family Device Status" table on page iii, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group's products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. R ev i si o n 1 8 4 -7 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 (c) 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 5172160-18/3.12 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microsemi: AX250-FGG484 AX125-2FGG324I AX250-2FGG256I AX125-2FGG324 AX250-1PQG208M AX250-2FGG256 AX1000-2BG729 AX1000-FG896 AX2000-2FG1152 AX2000-1FG1152M AX2000-2FG896 AX1000-1FG676M AX125-1FG256I AX250-2PQ208 AX250-2FG256 AX2000-2FG1152I AX2000-FG896M AX2000-1CQ352M AX10002FG896I AX250-1FG484I AX1000-2FG896 AX2000-FG896I AX250-1FG256I AX1000-1FG676 AX1000-1FG676I AX1000-1FG896 AX1000-CQ352M AX2000-1FG1152 AX2000-FG1152I AX2000-FG896 AX2000-2FG896I AX2000FG1152M AX2000-1FG896 AX2000-FG1152 AX2000-1FG896M AX1000-BG729 AX1000-FG676M AX1000FG896M AX2000-1FG1152I AX1000-1FG896M AX2000-1FGG1152 AX2000-FGG896 AX1000-FGG484 AX1000FG896I AX1000-FG484M AX250-1PQG208I AX125-FGG324I AX1000-1BG729 AX1000-1CQ352M AX20001FG896I AX1000-FG676 AX125-2FG324I AX250-CQ208M AX2000-CQ352M AX1000-BG729I AX1000-1BG729M AX1000-2FG676 AX1000-FG676I AX1000-BGG729 AX1000-1FGG896 AX1000-FGG484I AX1000-FGG896 AX2501PQ208 AX1000-FG484I AX1000-BG729M AX1000-1FG484 AX1000-2FG484 AX125-1FG256 AX125-2FG324 AX250-1PQ208M AX250-2FG256I AX125-FG256 AX250-FGG256I AX2000-FGG1152I AX250-2PQ208I AX250FG484I AX250-2FG484I AX250-1FGG256I AX1000-BGG729I AX1000-FGG676I AX1000-2FG676I AX125-2FG256I AX250-FG256 AX250-1FG256M AX250-1FG484 AX1000-1BGG729 AX250-1FG256 AX125-FG256I AX250FG256I AX250-2FG484 AX250-FG484M AX250-1CQ208M AX1000-2BG729I AX1000-1FG484M AX125-1FG324I AX250-FG484 AX1000-1FG896I AX125-FGG324 AX2000-1FGG896I AX1000-1FGG676