1
Features
•High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
•In-System Programmability (ISP) via JTAG
•Flexible Logic Macrocell
– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
•Advanced Power Management Features
•Automatic 10 µA Standby for “L” Version
•Pin-controlled 1 mA Standby Mode
•Programmable Pin-keeper Inputs and I/Os
•Reduced-power Feature per Macrocell
•Available in Commercial and Industrial Temperature Ranges
•Available in 44-lead PLCC and TQFP
•Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
•JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
•PCI-compliant
•Security Fuse Feature
•Green (Pb/Halide-fee/RoHS Compliant) Package Options
Enhanced Features
•Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
•Output Enable Product Terms
•D Latch Mode
•Combinatorial Output with Registered Feedback within Any Macrocell
•Three Global Clock Pins
•ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
(“L” Versions)
•Fast Registered Input from Product Term
•Programmable “Pin-keeper” Option
•VCC Power-up Reset Option
•Pull-up Option on JTAG Pins TMS and TDI
•Advanced Power Management Features
– Input Transition Detection
– Power-down (“L” Versions)
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
High-
performance
EEPROM CPLD
ATF1502AS
ATF1502ASL
Rev. 0995K–PLD–6/05
2ATF1502AS(L)
0995K–PLD–6/05
44-lead TQFP
Top View
44-lead PLCC
Top View
Description The ATF1502AS is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and
the odds of successful pin-locked design modifications.
The ATF1502AS has up to 32 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
3
ATF1502AS(L)
0995K–PLD–6/05
Block Diagram
Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input
and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40
individual signals from the global bus. Each macrocell also generates a foldback logic term
that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast,
efficient generation of complex logic functions. The ATF1502AS contains four such logic
chains, each capable of creating sum term logic with a fan-in of up to 40 product terms.
The ATF1502AS macrocell, shown in Figure 1, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused product terms are automatically disabled by the compiler to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the ATF1502AS. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF1502AS device is an in-system programmable (ISP) device. It uses the industry stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-
scan Description Language (BSDL). ISP allows the device to be programmed without remov-
ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.
B
32
4ATF1502AS(L)
0995K–PLD–6/05
Figure 1. ATF1502AS Macrocell
Product Terms and
Select Mux
Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of
product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
Flip-flop The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
5
ATF1502AS(L)
0995K–PLD–6/05
The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual prod-
uct term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used
as the clock, one of the macrocell product terms can be selected as a clock enable. When the
clock enable function is active and the enable signal (product term) is low, all clock edges are
ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear
(GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a prod-
uct term. The asynchronous preset (AP) can be a product term or always off.
Extra Feedback The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The four foldback terms in each region allow generation of high fan-in sum
terms (up to nine product terms) with little additional delay.
Programmable
Pin-keeper
Option for
Inputs and I/Os
The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir-
cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it
will stay at that previous high or low level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
6ATF1502AS(L)
0995K–PLD–6/05
Input Diagram
I/O Diagram
Speed/Power
Management
The ATF1502AS has several built-in speed and power management features. The
ATF1502AS contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 50 MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
The ATF1502AS also has an optional power-down mode. In this mode, current drops to below
10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be
used to power down the part. The power-down option is selected in the design source file.
When enabled, the device goes into power-down when either PD1 or PD2 is high. In the
power-down mode, all internal logic signals are latched and held, as are any enabled outputs.
7
ATF1502AS(L)
0995K–PLD–6/05
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit
turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which
include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1502AS macrocell also has an option whereby the power can be reduced on a per-
macrocell basis. By enabling this power-down option, macrocells that are not used in an appli-
cation can be turned down, thereby reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
Design
Software
Support
ATF1502AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages and formats.
Power-up Reset The ATF1502AS is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and
the state of each output will depend on the polarity of its buffer. However, due to the asynchro-
nous nature of reset and uncertainty of how VCC actually rises in the system, the following
conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF1502AS has two options for the hysteresis about the reset level, VRST, Small and
Large. During the fitting process users may configure the device with the Power-up Reset hys-
teresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred microamps as
well.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns.
Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains
accessible.
Programming ATF1502AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-
tocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
8ATF1502AS(L)
0995K–PLD–6/05
Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the
PC. ISP is performed by using either a download cable, a comparable board tester or a simple
microprocessor interface.
When using the ISP hardware or software to program the ATF1502AS devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities.
ATF1502AS devices can also be programmed using standard third-party programmers. With a
third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional
I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP
Programming
Protection
The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition, the pin-keeper option preserves the
previous state of the input and I/O PMS during programming.
All ATF1502AS devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and
I/O pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The
ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is
automatically reset at power-up. The five JTAG modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can
be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows
ATF1502AS programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502AS has the option of using four JTAG-standard I/O pins for boundary-scan test-
ing (BST) and in-system programming (ISP) purposes. The ATF1502AS is programmable
through the four JTAG pins using the IEEE standard JTAG programming protocol established
by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for
in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is
not needed, then the four JTAG control pins are available as I/O pins.
9
ATF1502AS(L)
0995K–PLD–6/05
JTAG
Boundary-scan
Cell (BSC)
Testing
The ATF1502AS contains up to 32 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update regis-
ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the capture registers. Input to the capture
register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture
registers are used to capture active device data signals, to shift data in and out of the device
and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is
shown below.
BSC
Configuration
for Input and I/O
Pins (Except
JTAG TAP Pins)
Note: 1. The ATF1502AS has a pull-up option on TMS and TDI pins. This feature is selected as a
design option.
BSC
Configuration
for Macrocell
0
1
0
1
DQ DQ
Capture
DR
Update
DR
0
1
0
1
DQ DQ
TDI
OUTJ
OEJ
Shift Clock
Mode
TDO
BSC for I/O Pins and Macrocells
0
1
D
Q
TDI
CLOCK
TDO
Pin
10 ATF1502AS(L)
0995K–PLD–6/05
PCI Compliance The ATF1502AS also supports the growing need in the industry to support the new Peripheral
Component Interconnect (PCI) interface standard in PCI-based designs and specifications.
The PCI interface calls for high current drivers, which are much larger than the traditional TTL
drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required
by the PCI interface. The ATF1502AS allows this without contributing to system noise while
delivering low output to output skew. Having a programmable high drive option is also possible
without increasing output delay or pin capacitance. The PCI electrical characteristics appear
on the next page.
PCI Voltage-to-
current Curves
for +5V
Signaling in
Pull-up Mode
PCI Voltage-to-
current Curves
for +5V
Signaling in
Pull-down Mode
2.4
VCC
1.4
-2 -44 -178
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Up
Test Point
2.2
VCC
0.55
3,6 95 380
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Down
Test Point
11
ATF1502AS(L)
0995K–PLD–6/05
Note: 1. Leakage current is with pin-keeper off.
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
PCI DC Characteristics (Preliminary)
Symbol Parameter Conditions Min Max Units
VCC Supply Voltage 4.75 5.25 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.5 0.8 V
IIH Input High Leakage Current(1) VIN = 2.7V 70 µA
IIL Input Low Leakage Current(1) VIN = 0.5V -70 µA
VOH Output High Voltage IOUT = -2 mA 2.4 V
VOL Output Low Voltage IOUT = 3 mA, 6 mA 0.55 V
CIN Input Pin Capacitance 10 pF
CCLK CLK Pin Capacitance 12 pF
CIDSEL IDSEL Pin Capacitance 8 pF
LPIN Pin Inductance 20 nH
PCI AC Characteristics (Preliminary)
Symbol Parameter Conditions Min Max Units
IOH(AC) Switching
Current High
(Test High)
0 < VOUT ≤ 1.4 -44 mA
1.4 < VOUT < 2.4 -44 + (VOUT - 1.4)
/0.024
mA
3.1 < VOUT < VCC Equation A mA
VOUT = 3.1V -142 µA
IOL(AC) Switching
Current Low
(Test Point)
VOUT >2.2V 95 mA
2.2 > VOUT > 0 VOUT/0.023 mA
0.1 > VOUT > 0 Equation B mA
VOUT = 0.71 206 mA
ICL Low Clamp Current -5 < VIN ≤-1 -25 + (VIN + 1)
/0.015
mA
SLEWROutput Rise Slew Rate 0.4V to 2.4V load 1 5 V/ns
SLEWFOutput Fall Slew Rate 2.4V to 0.4V load 1 5 V/ns
12 ATF1502AS(L)
0995K–PLD–6/05
Power-down
Mode
The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply
current is reduced to less than 5 mA. During power-down, all output data and internal logic
states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. The power-down pin feature is enabled in the logic design file. Designs using
the power-down pin may not use the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried feedback and foldback product term
array inputs.
Notes: 1. For slow slew outputs, add tSSO.
2. Pin or product term.
Power-down AC Characteristics(1)(2)
Symbol Parameter
-7 -10 -15 -25
UnitsMin Max Min Max Min Max Min Max
tIVDH Valid I, I/O before PD High 7 10 15 25 ns
tGVDH Valid OE(2) before PD High 7 10 15 25 ns
tCVDH Valid Clock(2) before PD High 7 10 15 25 ns
tDHIX I, I/O Don’t Care after PD High 12 15 25 35 ns
tDHGX OE(2) Don’t Care after PD High 12152535ns
tDHCX Clock(2) Don’t Care after PD High 12152535ns
tDLIV PD Low to Valid I, I/O 1 1 1 1 µs
tDLGV PD Low to Valid OE (Pin or Term) 1 1 1 1 µs
tDLCV PD Low to Valid Clock (Pin or Term) 1 1 1 1 µs
tDLOV PD Low to Valid Output 1 1 1 1 µs
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
13
ATF1502AS(L)
0995K–PLD–6/05
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C-40°C - 85°C
VCC (5V) Power Supply 5V ± 5% 5V ± 10%
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input or I/O Low
Leakage Current
VIN = VCC -2 -10 µA
IIH Input or I/O High
Leakage Current
210
IOZ Tri-state Output
Off-state Current
VO = VCC or GND -40 40 µA
ICC1 Power Supply Current, Standby VCC = Max
VIN = 0, VCC
Std Mode Com. 60 mA
Ind. 75 mA
“L” Mode Com. 10 µA
Ind. 10 µA
ICC2 Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode 1 5 mA
ICC3(2) Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode Com. 35 mA
Ind. 40 mA
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.0 VCCIO + 0.3 V
VOL Output Low Voltage (TTL) VIN = VIH or VIL
VCC = MIN, IOL = 12 mA
Com. 3.0 0.45 V
Ind. 0.45
Output Low Voltage (CMOS) VIN = VIH or VIL
VCC = MIN, IOL = 0.1 mA
Com. 0.2 V
Ind. 0.2 V
VOH Output High Voltage (TTL) VIN = VIH or VIL
VCC = MIN, IOH = -4.0 mA
2.4 V
14 ATF1502AS(L)
0995K–PLD–6/05
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
Timing Model
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
Output AC Test Loads
Pin Capacitance(1)
Typ Max Units Conditions
CIN 810pF V
IN = 0V; f = 1.0 MHz
CI/O 810pF V
OUT = 0V; f = 1.0 MHz
15
ATF1502AS(L)
0995K–PLD–6/05
AC Characteristics (1)
Symbol Parameter
-7 -10 -15 -25
UnitsMin Max Min Max Min Max Min Max
tPD1 Input or Feedback to Non-registered Output 7.5 10 3 15 25 ns
tPD2 I/O Input or Feedback to Non-registered
Feedback
7931225ns
tSU Global Clock Setup Time 6 7 11 20 ns
tHGlobal Clock Hold Time 0 0 0 0 ns
tFSU Global Clock Setup Time of Fast Input 3 3 3 5 ns
tFH Global Clock Hold Time of Fast Input 0.5 0.5 1 2 MHz
tCOP Global Clock to Output Delay 4.5 5 8 13 ns
tCH Global Clock High Time 3 4 5 7 ns
tCL Global Clock Low Time 3 4 5 7 ns
tASU Array Clock Setup Time 3 3 4 5 ns
tAH Array Clock Hold Time 2 3 4 6 ns
tACOP Array Clock Output Delay 7.5 10 15 25 ns
tACH Array Clock High Time 3 4 6 10 ns
tACL Array Clock Low Time 3 4 6 10 ns
tCNT Minimum Clock Global Period 8 10 13 22 ns
fCNT Maximum Internal Global Clock Frequency 125 100 76.9 50 MHz
tACNT Minimum Array Clock Period 8 10 13 22 ns
fACNT Maximum Internal Array Clock Frequency 125 100 76.9 50 MHz
fMAX Maximum Clock Frequency 166.7 125 100 60 MHz
tIN Input Pad and Buffer Delay 0.5 0.5 2 2 ns
tIO I/O Input Pad and Buffer Delay 0.5 0.5 2 2 ns
tFIN Fast Input Delay 1 1 2 2 ns
tSEXP Foldback Term Delay 4 5 8 12 ns
tPEXP Cascade Logic Delay 0.8 0.8 1 2 ns
tLAD Logic Array Delay 3 5 6 8 ns
tLAC Logic Control Delay 3 5 6 8 ns
tIOE Internal Output Enable Delay 2 2 3 4 ns
tOD1 Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCC = 5V; CL = 35 pF)
21.5 4 6ns
tZX1 Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
4.0 5.0 7 10 ns
tZX2 Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
4.5 5.5 7 10 ns
16 ATF1502AS(L)
0995K–PLD–6/05
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
tZX3 Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
9 9 10 12 ns
tXZ Output Buffer Disable Delay (CL = 5 pF) 4 5 6 8 ns
tSU Register Setup Time 3 3 4 6 ns
tHRegister Hold Time 2 3 4 6 ns
tFSU Register Setup Time of Fast Input 3 3 2 3 ns
tFH Register Hold Time of Fast Input 0.5 0.5 2 5 ns
tRD Register Delay 1 2 1 2 ns
tCOMB Combinatorial Delay 1 2 1 2 ns
tIC Array Clock Delay 3 5 6 8 ns
tEN Register Enable Time 3 5 6 8 ns
tGLOB Global Control Delay 1 1 1 1 ns
tPRE Register Preset Time 2 3 4 6 ns
tCLR Register Clear Time 2 3 4 6 ns
tUIM Switch Matrix Delay 1 1 2 2 ns
tRPA Reduced-power Adder(2) 10 11 13 15 ns
AC Characteristics (Continued)(1)
Symbol Parameter
-7 -10 -15 -25
UnitsMin Max Min Max Min Max Min Max
17
ATF1502AS(L)
0995K–PLD–6/05
SUPPLY CURRENT VS. SUPPLY VOLTAGE
AS VERSION (TA = 25°C, F = 0)
0
10
20
30
40
50
60
70
4.5 4.75 5 5.25 5.5
VCC (V)
ICC (mA)
STANDARD POWER
REDUCED POWER
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0)
0
2
4
6
8
10
12
14
4.5 4.75 5 5.25 5.5
VCC (V)
ICC (mA)
TBD
SUPPLY CURRENT VS. FREQUENCY
AS VERSION (TA = 25°C)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0.00 20.00 40.00 60.00 80.00 100.00
FREQUENCY (MHz)
ICC (mA)
STANDARD POWER
REDUCED POWER
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE
(VOH = 2.4V, TA = 25°C)
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)
IOH (mA)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(T = 25°C, NON-TURBO, BIT6 = 0, BIT 30 = 0)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
4.00 4.50 4.75 5.00 5.25 5.50 6.00
VCC (V)
ICC (µA)
SUPPLY CURRENT VS. FREQUENCY
ASL (LOW-POWER) VERSION (TA = 25°C)
0.0
10.0
20.0
30.0
40.0
50.0
60.0
0.00 10.00 20.00 30.00 40.00 50.00
FREQUENCY (MHz)
ICC (mA)
STANDARD POWER
REDUCED POWER
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE
(VCC = 5V, TA = 25°C)
-100.0
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
OUTPUT VOLTAGE (V)
IOH (mA)
18 ATF1502AS(L)
0995K–PLD–6/05
INPUT CLAMP CURRENT VS. INPUT VOLTAGE
(VCC = 5V, TA = 25°C)
-60
-50
-40
-30
-20
-10
0
-1.00 -0.80 -0.60 -0.40 -0.20 0.00
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE
(VOL = 0.5V, TA = 25°C)
34
35
36
37
38
39
40
41
42
43
4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)
IOL (mA)
NORMALIZED TPD
VS. SUPPLY VOLTAGE (TA = 25°C)
0.80
0.90
1.00
1.10
1.20
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TPD
INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V, TA = 25°C)
-30
-20
-10
0
10
20
30
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE
(VCC = 5V, TA = 25°C)
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
OUTPUT VOLTAGE (V)
IOL (mA)
NORMALIZED TPD
VS. TEMPERATURE (VCC = 5.0V)
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED TPD
19
ATF1502AS(L)
0995K–PLD–6/05
NORMALIZED TCO
VS. SUPPLY VOLTAGE (TA = 25°C)
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TPD
NORMALIZED TSU VS. SUPPLY VOLTAGE (TA = 25°C)
0.8
0.9
1.0
1.1
1.2
4.5 4.8 5.0 5.3 5.5
SUPPLY VOLTAGE (V)
NORMALIZED TSU
NORMALIZED TCO
VS. TEMPERATURE (VCC = 5.0V)
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED TCO
NORMALIZED TSU
VS. TEMPERATURE (VCC = 5.0V)
0.8
0.9
1.0
1.1
1.2
-40.0 0.0 25.0 75.0
TEMPERATURE (C)
NORMALIZED TSU
20 ATF1502AS(L)
0995K–PLD–6/05
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GND Ground pins
VCC VCC pins for the device (+5V)
ATF1502AS Dedicated Pinouts
Dedicated Pin
44-lead
TQFP
44-lead
J-lead
INPUT/OE2/GCLK2 40 2
INPUT/GCLR 39 1
INPUT/OE1 38 44
INPUT/GCLK1 37 43
I/O / GCLK3 35 41
I/O / PD (1,2) 5, 19 11, 25
I/O / TDI (JTAG) 1 7
I/O / TMS (JTAG) 7 13
I/O / TCK (JTAG) 26 32
I/O / TDO (JTAG) 32 38
GND 4, 16, 24, 36 10, 22, 30, 42
VCC 9, 17, 29, 41 3, 15, 23, 35
# of Signal Pins 36 36
# User I/O Pins 32 32
21
ATF1502AS(L)
0995K–PLD–6/05
ATF1502AS I/O Pinouts
MC PLC 44-lead PLCC 44-lead TQFP
1A442
2A543
3A/PD1 644
4/TDI A71
5A82
6A93
7A115
8A126
9/TMS A137
10 A 14 8
11 A 16 10
12 A 17 11
13 A 18 12
14 A 19 13
15 A 20 14
16 A 21 15
17 B 41 35
18 B 40 34
19 B 39 33
20/TDO B3832
21 B 37 31
22 B 36 30
23 B 34 28
24 B 33 27
25/TCK B3226
26 B 31 25
27 B 29 23
28 B 28 22
29 B 27 21
30 B 26 20
31 B 25 19
32 B 24 18
22 ATF1502AS(L)
0995K–PLD–6/05
Ordering Information
Notes: 1. The last time buy date is Sept. 30, 2005 for shaded parts.
2. In 2004, Atmel briefly offered the lead-free products ATF1502AS-7JL44 and ATF1502AS-10JJ44. They have since been dis-
continued effective Sept. 30,2005 and replaced with Green “U” packages.
Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Standard Package Options
tPD
(ns)
tCO1
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
7.5 4.5 166.7 ATF1502AS-7 AC44
ATF1502AS-7 JC44
44A
44J
Commercial
(0°C to 70°C)
10 5 125
ATF1502AS-10 AC44
ATF1502AS-10 JC444
44A
44J
Commercial
(0°C to 70°C)
ATF1502AS-10 AI44
ATF1502AS-10 JI44
44A
44J
Industrial
(-40°C to +85°C)
15 8 100
ATF1502AS-15 AC44
ATF1502AS-15 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502AS-15 AI44
ATF1502AS-15 JI44
44A
44J
Industrial
(-40°C to +85°C)
25 13 60
ATF1502ASL-25 AC44
ATF1502ASL-25 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502ASL-25 AI44 44A
44J
Industrial
(-40°C to +85°C)
ATF1502ASL-25 JI44
Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
7.5 4.5 166.7 ATF1502AS-7 AX44
ATF1502AS-7 JX44
44A
44J
Commercial
(0°C to 70°C)
10 5 125 ATF1502AS-10 AU44
ATF1502AS-10 JU44
44A
44J
Industrial
(-40°C to +85°C)
25 13 60 ATF1502ASL-25 AU44
ATF1502ASL-25 JU44
44A
44J
Industrial
(-40°C to +85°C)
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
23
ATF1502AS(L)
0995K–PLD–6/05
Packaging Information
44A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B
44A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
24 ATF1502AS(L)
0995K–PLD–6/05
44J – PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
25
ATF1502AS(L)
0995K–PLD–6/05
Revision History
Revision Comments
0995K Green package options added.
Printed on recycled paper.
0995K–PLD–6/05 xM
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