1
®CA3130, CA3130A
15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.
Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, ver y -low-input current, and exceptional speed
perf ormance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to
0.5V below the negative-supply ter mi nal, an important
attribute in single-supply applications.
A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.
The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have
ter m inals for adjustment of offset v oltage for applications
requiring offset-null capability. Terminal provisions are also
made to per mit strobing of the output stage.
• The CA3130A offers superior input characteristics over
those of the CA3130.
Features
• MOSFET Input Stage Provides:
- Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ)
- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . .= 2pA (Typ) at 5V Operation
• Ideal for Single-Supply Applications
• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negativ e Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails
•Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Ground-Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long-Duration Timers/Monostables
• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)
• High-Input-Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)
• Voltag e Regulators (Permits Control of Ou tput Voltage
Down to 0V)
• Peak Detectors
• Single-Supply Full-Wave Precision Rectifiers
• Photo-Diode Sensor Amplifiers
Pinout CA3130, CA3130A
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NO.
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG.
DWG. #
CA3130AE -55 to 125 8 Ld PDIP E8.3
CA3130AM
(3130A) -55 to 125 8 Ld SOIC M8.15
CA3130AM96
(3130A) -55 to 125 8 Ld SOIC
Tape and Reel M8.15
CA3130AMZ
(3130AZ) (Note) -55 to 125 8 Ld SOIC
(Pb-free) M8.15
CA3130AMZ96
(3130AZ) (Note) -55 to 125 8 Ld SOIC
Tape and Reel (Pb-free) M8.15
CA3130E -55 to 125 8 Ld PDIP E8.3
CA3130EZ
(Note) -55 to 125 8 Ld PDIP*
(Pb-free) E8.3
CA3130M
(3130) -55 to 125 8 Ld SOIC M8.15
CA3130M96
(3130) -55 to 125 8 Ld SOIC
Tape and Reel M8.15
CA3130MZ
(3130MZ) (Note) -55 to 125 8 Ld SOIC
(Pb-free) M8.15
CA3130MZ96
(3130MZ) -55 to 125 8 Ld SOIC
Tape and Reel (Pb-free) M8.15
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not
intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
OFFSET
INV.
NON-INV.
V-
1
2
3
4
8
7
6
5
STROBE
V+
OUTPUT
OFFSET
-
+
NULL
INPUT
INPUT
NULL
Data Sheet August 1, 2005 FN817.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input-Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC
Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . 115 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operationa l sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified
PARAMETER SYMBOL TEST
CONDITIONS
CA3130 CA3130A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage |VIO|V
S = ±7.5V - 8 15 - 2 5 mV
Input Offset Voltage
Temperature Drift ∆VIO/∆T - 10 - - 10 - µV/oC
Input Offset Current |IIO|V
S = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current IIVS = ±7.5V - 5 50 - 5 30 pA
Large-Signal Voltage Gain AOL VO = 10VP-P
RL = 2kΩ50 320 - 50 320 - kV/V
94 110 - 94 110 - dB
Common-Mode
Rejection Ratio CMRR 70 90 - 80 90 - dB
Common-Mode Input
Voltage Range VICR 0 -0.5 to 12 10 0 -0.5 to 12 10 V
Power-Supply
Rejection Ratio ∆VIO/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V
Maximum Output Voltage VOM+R
L = 2kΩ12 13.3 - 12 13.3 - V
VOM-R
L = 2kΩ- 0.002 0.01 - 0.002 0.01 V
VOM+R
L = ∞14.99 15 - 14.99 15 - V
VOM-R
L = ∞- 0 0.01 - 0 0.01 V
Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA
IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA
Supply Current I+ VO = 7.5V,
RL = ∞- 10 15 - 10 15 mA
I+ VO = 0V,
RL = ∞-23-23mA
CA3130, CA3130A
3
Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS CA3130,
CA3130A UNITS
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or
4 and 1 ±22 mV
Input Resistance RI1.5 TΩ
Input Capacitance CIf = 1MHz 4.3 pF
Equivalent Input Noise Voltage eNBW = 0.2MHz, RS = 1MΩ
(Note 3) 23 µV
Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability ≥47pF Required.) fTCC = 0 15 MHz
CC = 47pF 4 MHz
Slew Rate: SR
CC = 0 30 V/µsOpen Loop
Closed Loop CC = 56pF 10 V/µs
Transient Response: CC = 56pF,
CL = 25pF,
RL = 2kΩ
(Voltage Follower)
0.09 µsRise Time tr
Overshoot OS 10 %
Settling Time (To <0.1%, VIN = 4VP-P)t
S1.2 µs
NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)
PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS
Input Offset Voltage VIO 82mV
Input Offset Current IIO 0.1 0.1 pA
Input Current II22pA
Common-Mode Rejection Ratio CMRR 80 90 dB
Large-Signal Voltage Gain AOL VO = 4VP-P, RL = 5kΩ100 100 kV/V
100 100 dB
Common-Mode Input Voltage Range VICR 0 to 2.8 0 to 2.8 V
Supply Current I+ VO = 5V, RL = ∞300 300 µA
VO = 2.5V, RL = ∞500 500 µA
Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V
NOTE:
4. Operation at 5V is not recommended for temperatures below 25oC.
CA3130, CA3130A
4
Schematic Diagram
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials fo r
common use in the first and second stages.
Terminal 8 can be used both for phase compensation and to
strobe the out put stag e into qui esce nce . When Terminal 8 is
tied to the negative supply rail (Terminal 4) by mechanical or
electrical means, the output potential at Terminal 6
essentially rises to the positive supply-rail potential at
Terminal 7. This condition of essentially zero current drain in
the output stage under the strobed “OFF” condition can only
be achieved when the ohmic load resistance presented to
the amplifier is very high (e.g.,when the amplifier output is
used to drive CMOS digital circuits in Comparator
applications).
Input Stage
The circuit of the CA3130 is show n in the schematic diagr am.
It consists of a diff erential-input sta ge using PMOS field-eff ect
transistors (Q6, Q7) working into a mirror-pair of bipolar
transistors (Q9, Q10) functioning as load resistors together
with resistors R3 through R6.
The mirror-pair transistors also function as a differential-to-
single-ended con verter to provide base driv e to th e se cond-
stage bipolar transisto r (Q11). Offset n ulling, when desired,
can be eff ected b y conne cting a 100,00 0Ω potentiometer
across Terminals 1 and 5 and the potentiometer sli der arm to
Terminal 4.
3
2
1 8 4
6
7
Q1Q2
Q4
D1
D2
D3
D4
Q3
Q5
D5D6D7D8
Q9Q10
Q6Q7
5
Z1
8.3V
INPUT STAGE
R3
1kΩR4
1kΩ
R6
1kΩ
R5
1kΩ
NON-INV.
INPUT
INV.-INPUT
+
-
R1
40kΩ
5kΩ
R2
BIAS CIRCUIT CURRENT SOURCE FOR “CURRENT SOURCE
LOAD” FOR Q11
Q6 AND Q7
V+
OUTPUT
OUTPUT
STAGE Q8
Q12
V-
Q11
SECOND
STAGE
OFFSET NULL COMPENSATION STROBING
(NOTE 5)
NOTE:
5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
CA3130, CA3130A
5
Cascade-connected PMOS transistors Q2, Q4 are the
constant-current source f or the input stage. The biasing circuit
f or the constant-current source is subsequen tly described.
The small diodes D5 through D8 pro vide gate-oxide protection
against high-v o ltage tr ansi ents , incl uding static ele ctricity
during handling for Q6 and Q7.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascade-connected load resistance provided by
PMOS transistors Q3 and Q5. The source of bias potentials
f or these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somew hat above 8.3V, resistor R2
and zen er diode Z1 serve to establish a v oltage of 8.3V across
the series-connected circuit, consisting of resistor R1, diodes
D1 throu gh D4, and PMOS transistor Q1. A tap at the juncti on
of resistor R1 and diode D4 provides a gate-bi as potential o f
about 4.5V f or PMOS tr ansistors Q 4 an d Q5 with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q 1 with respect to Terminal
7 to provide gate bias for PMOS transistors Q2 and Q3. It
should be noted that Q1 is “mirror-connecte d (see Note 8)” to
both Q2 an d Q3. Since transistors Q 1, Q2, Q3 are designed to
be identical, the approximately 200µA current in Q1
establ ishes a simil ar current in Q2 a nd Q3 as constant current
sources f or both the first and second amplifier stages,
respectively.
At total supply voltages somewhat less than 8.3V, zener
diode Z1 becomes nonconductive and the potential,
developed across series-connected R1, D1-D4, and Q1,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier , its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear , requiring feedbac k f or good
waveform reproduction, transient delays may be
encountered. As a voltage follow er , the amplifier can achiev e
0.01% accuracy levels, including the negative supply rail.
NOTE:
8. For general information on the characteristics of CMOS
transistor-pairs in linear-circuit applications, see File Number
619, data sheet on CA3600E “CMOS Transistor Array”.
3
2
7
4
815
6
BIAS CKT.
COMPENSATION
(WHEN REQUIRED)
AV ≈ 5X AV ≈AV ≈
6000X 30X
INPUT
+
-
200µA 200µA
1.35mA 8mA
0mA
V+
OUTPUT
V-
STROBE
CC
OFFSET
NULL
CA3130
(NOTE 7)
(NOTE 5)
NOTES:
6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above
Terminal 4.
7. Total supply voltage (f or indicated voltage gains) = 15V with
output terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
17.5 2012.5 15107.52.5 50
2.5
7.5
5
10
15
12.5
17.5
0
SUPPLY VOLTAGE: V+ = 15, V- = 0V
TA = 25oCLOAD RESISTANCE = 5kΩ
500Ω
1kΩ
2kΩ
FIGURE 2. V OL TA GE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
CA3130, CA3130A
6
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
TA = 25oC when Terminal s 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at TA = 25oC.
These data show that circuit designers can advantageously
ex ploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage.
Although the finite resista nce of the glass terminal-to-case
insulator of the metal can package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if
it is connected to Terminal 4 potential, and the Metal Can
case of the CA3130 is also internally tied to Terminal 4, input
Terminal 3 is essentially “guarded” from spur ious leakage
currents.
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
eff ected with the slider arm positioned in the mid-point of the
potentiometer’s total range.
Input-Current Variation with Temperature
The input current of the CA3130 Series circuits is typically
5pA at 25oC . The major portion of this input current is due to
leakage current through the gate-protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10oC
increase in temperature. Figure 4 provides data on the
typical variation of input bias current as a function of
temperature in the CA3130.
In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
eff ects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat-
sinking can also very markedly reduce and stabilize input
current variations.
Input Offset Voltage (VIO) Variati on with DC Bias
and Device Operating Life
It is well known that the characteristics of a MOSFET de vice
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA3130 should be alert to the possible impacts
of this effect if the application of the device inv olves e xtended
operation at high temperatures with a significant differential
DC bias voltage applied across Terminals 2 and 3. Figure 5
shows typical data pertinent to shifts in offset voltage
encountered with CA3130 devices (metal can package)
during life testing. At lower temperatures (metal can and
plastic), for example at 85oC, this change in volta ge is
considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same ma gnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2VDC differential voltage
e xample represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.
10
7.5
5
2.5
0-101234567
INPUT CURRENT (pA)
INPUT VOLTAGE (V)
TA = 25oC
3
27
48
6
PA
VIN
CA3130
15V
TO
5V
0V
TO
-10V
V+
V-
FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE
VS = ±7.5V
4000
1000
100
10
1-80 -60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA)
TEMPERATURE (oC)
FIGURE 4. INPUT CURRENT vs TEMPERATURE
CA3130, CA3130A
7
o
Power-Supply Considerations
Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B show the
CA3130 connected for both dual-and single-supply
operation.
Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q8 and Q12 are driven
increasingly positive with respect to ground, current flow
through Q12 (from the nega tive supply) to the load is
increased and current flow through Q8 (from the positive
supply) decreases correspondingly. When the gate terminals
of Q8 and Q12 are driven increasingly negative with respect
to ground, current flow through Q8 is increased and current
flow through Q12 is decreased accordingly.
Single-supply Oper ation: Initially, let it be assumed that the
va lue of RL is very high (or disconnected), and that the inp ut-
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
across Q8 and Q12 are of equal magnitude . Figure 20 sho ws
typical quiescent supply-current vs suppl y-voltage for the
CA3130 operated unde r these conditi ons . Sin ce the output
stage is operating as a Cla ss A amplifier, the supply-current
will remain constant under dynamic oper ating conditi ons as
long as the transistors are operated in the lin ear portion of
their v oltage-tr ansfer characteristics (see Figure 2). If either
Q8 or Q12 are swung out of their linear regions tow ard cut-off
(a non-linear region), there will be a co rrespond ing reduction
in supply-current. In the e xtreme case, e.g., with Terminal 8
s wung down to ground potential (or tied to ground), NMOS
transistor Q12 is completely cut off and the supply-current to
series-connected transistors Q8, Q12 goes essentially to z ero.
The two preceding stages in the CA3130, however, continue
to dra w mo dest supply-current (see the lower curve in Figure
20) e ven though the output stage is strobed off. Figure 6A
shows a dual-sup ply arr angemen t for the output stage that
can also be strobed off, assuming RL = ∞ by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Terminals 2 and 3) is such that
the output term inal (No. 6) voltage is at V+/2. Since PMOS
transistor Q8 must now supply quiescent current to both RL
and transistor Q12, it should be apparent that unde r these
conditions the supply-current must increase as an inverse
function of the RL magnitude. Figure 22 shows the voltage-
drop across PMOS transistor Q8 as a function of load
current at several supply voltages. Figure 2 shows the
voltage-transfer characteristics of the output stage for
several values of load resistance.
Wideband Noise
From the standpoint of low-noise performance
considerations, the use of the CA3130 is most advantageous
in applications where in the source resistance of the input
signal is on the order of 1MΩ or more. In this case, the total
input-referred noise voltage is typically only 23µV when the
test-circuit amplifier of Figure 7 is operated at a total supply
voltage of 15V. This value of total input-referred noise
remains essentially constant, e ven though the value of
source resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
SHIFT vs OPERATING LIFE
FIGURE 6A. DUAL POWER SUPPLY OPERATION
FIGURE 6B. SINGLE POWER SUPPLY OPERATION
FIGURE 6. CA3130 OUTPUT STAGE IN DU AL AND SINGLE
POWER SUPPLY OPERATION
T
A
= 125
o
C FOR T O-5 PACKAGES
7
6
5
4
3
2
1
0 500 1000 1500 2000 2500 3000 3500 4000
OFFSET VOLTAGE SHIFT (mV)
TIME (HOURS)
DIFFERENTIAL DC VO LTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
0
3
2
8
4
7
6
RL
Q8
Q12
CA3130
+
-
V+
V-
3
2
8
4
7
6
RL
Q8
Q12
CA3130
+
-
V+
CA3130, CA3130A
8
values of source resistance very much greater than 1MΩ,
the total noise voltage generated can be dominated by the
thermal noise contributions of both the feedback and source
resistors.
Typical Applications
Voltage F ol lowers
Operational amplifiers with very high input resistan ces, like
the CA3130, are particularly suited to service as voltage
followers. Fig ure 8 shows the circuit of a classical voltage
follower, together with per tinent waveforms using the
CA3130 in a split-supply configuration.
A voltage f ollower, operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 9A with
input-signal ramping. The waveforms in Figure 9B show that
the follower does not lose its input-to-output phase-sense,
even though the input is being swung 7.5V below ground
potenti al . Th i s un i q ue characteristic is an im po rtant attrib ut e
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in which the CMOS output
stage permits the output signal to swing down to the
negative supply-rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustr ates the pr actical use of the CA3130 in
a single-supply voltage-follower application.
9-Bit CMOS DAC
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3130 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.
The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
ar ms at either the positi ve or the negative power-supply
ter minal. Each CD4007A contains three “inverters”, each
“inv erter” functioning as a single-pole double-throw s witch to
ter mi nate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-o xide film resistors. The five
ar ms requiring the highest accuracy are assembled with
series and parall el combinations of 806,000Ω resistors from
the same manufacturing lot.
A single 15V supply provides a positive bus for the CA3130
f ollo wer amplifier and feeds the CA3085 voltage regulator . A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line-
voltage regulation (approximate ly 0.2%) permits a 9-bi t
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforde d by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.
Single-Supply, Absolute-Value, Ideal Full-Wave
Rectifier
The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fe d
through the feedback netw ork directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. Duri ng a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R2/R1. When the equality of the two equations
shown in Figure 11 is satisfied, the full-wave output is
symmetrical.
Peak Detectors
Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative
circuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
positive-going signal excursion at the collector of transistor
Q11, which is loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the other hand, during
a negative-going signal ex cursion at the collector of Q11, the
transistor functions in an active “pull-down” mode so that the
intri nsic capacitance can be discharged more expeditiously.
3
2
184
7
6
+
-
Rs
1MΩ
47pF -7.5V
0.01
µF
+7.5V
0.01µF
NOISE
VOLTAGE
OUTPUT
30.1kΩ
1kΩ
BW (-3dB) = 200kHz
TOTAL NOISE VO LTAGE (REFERRED
TO INPUT) = 23µV (TYP)
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED
FOR WIDEBAND NOISE MEASUREMENTS
CA3130, CA3130A
9
3
2
184
7
6
+
-
10kΩ
CC = 56pF
-7.5V 0.01µF
+7.5V
0.01µF
2kΩ
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs
25pF
0.1µF
Top Trace: Output
Center Trace: Input
FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,
200ns/DIV.)
Top Trace: Output Signal; 2V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
Bottom Trace: Input Signal; 2V/Div., 5µs/Div.
FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGN AL SHOWING
SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)
FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS
3
2
81
4
7
6
+
-
10kΩ
56pF OFFSET
+15V
0.01µF
2kΩ
0.1µF
5
ADJUST
100kΩ
FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL
RAMPING (2V/DIV., 500µs/DIV.)
Top Trace: Output; 5V/Div., 200µs/Div.
Bottom Trace: Input Signal; 5V/Div., 200µs/Div.
FIGURE 9B. OUTPUT WAVEFORM WITH GROUND
REFERENCE SINE-WAVE INPUT
FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
ASSOCIATED WAVEFORMS. (E.G., FOR USE IN
SINGLE-SUPPLY D/A CONVER TER; SEE FIGURE 9
IN AN6080)
CA3130, CA3130A
10
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
6 3 101036
4
8
36
7
9
4
10
2
3
13
812 12
1
58
1313 112
8 5
14
11
2
6
51
7
7
1
6
8
4
3
2
10V LOGIC INPUTS
+10.010V
LSB
987 654 321
MSB
806K
1%
PARALLELED
RESISTORS
+15V
VOLTAGE
FOLLOWER
CA3130
OUTPUT
LOAD
100K
OFFSET
NULL
56pF
2K
0.1µF
REGULATED
VOLTAGE
ADJ
22.1k
1%
1K
3.83k
1%
0.001µF
CA3085
VOLTAGE
REGULATOR
+15V
2µF
25V
+
-
+10.010V
CD4007A
“SWITCHES” CD4007A
“SWITCHES”
402K
1% 200K
1% 100K
1% 806K
1% 806K
1%
806K
1% 750K
1%
806K
1% 806K
1% 806K
1% 806K
1%
(2) (4) (8)
806K
1%
+
-
62
BIT
1
2
3
4
5
6 - 9
REQUIRED
RATIO-MATCH
STANDARD
±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS
NO TE: All resistances are in ohms.
CD4007A
“SWITCHES”
1
5
10K
2
34
6
815
7
R2
2kΩ+15V
0.01
µF
1N914
R3
5.1kΩ
PEAK
ADJUST
2kΩ
100kΩ
OFFSET
ADJUST
20pF
CA3130
R1
4kΩ
+
-
20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
G
ain = R2
R1
------- = X = R3
R1 + R2 + R3
-------------------------------------
R3 = R1 X + X2
1 - X
------------------
For X = 0.5: 2KΩ
4kΩ
------------ = R2
R1
-------
R3= 4kΩ 0.75
0.5
-----------
= 6kΩ
Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
Time base on both traces: 0.2ms/Div.
0V
0V
CA3130, CA3130A
11
FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGA TIVE DETECTOR CIRCUIT
FIGURE 12. PEAK-DETECTOR CIRCUITS
FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
3
26
4
7
CA3130
+7.5V
0.01µF
+DC
OUTPUT
5µF
+
-
100
kΩ
1N914
0.01µF
-7.5V
2kΩ
10kΩ+
-
6VP-P INPUT;
BW (-3dB) = 1.3MHz
0.3VP-P INPUT;
BW (-3dB) = 240kHz 3
26
4
7
CA3130
+7.5V
0.01µF
-DC
OUTPUT
5µF
+
-
100
kΩ
1N914
0.01µF
-7.5V
2kΩ
10kΩ+
-
6VP-P INPUT;
BW (-3dB) = 360kHz
0.3VP-P INPUT;
BW (-3dB) = 320kHz
6
3
2
1
8
7
4
CA3086
CURRENT
LIMIT
ADJ
3Ω
R2
1kΩ
Q513
14
12
Q1
Q2
Q3
Q4
10 7 3
4269
11 8 1 5
390Ω1kΩ
20kΩ
+
-
5µF
25V
56pF
ERROR
AMPLIFIER
CA3130
30kΩ
100kΩ
IC1
0.01
VOLTAGE
ADJUST
50kΩ
R1
14
13
Q5
12
62kΩ
IC3
OUTPUT
0 TO 13V
AT
40mA
+
-
0.01µF
+20V
INPUT
2.2kΩ
+
-25µF
IC2
CA3086 10 11 1, 2
Q4Q1
8, 7 5
Q3Q2
64
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0 .02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz
+
-
+
-
1kΩ
9
µF
3
CA3130, CA3130A
12
Error-Amplifier in Regulated-Power Supplies
The CA3130 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error-
amplifier when the regulated outp ut voltage is required to
approach zero. Figure 13 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment ov er the range from 0V to
13V. Q3 and Q4 in lC2 (a CA3086 transistor-array lC)
function as zeners to provide supply-voltage for the CA3130
comparator (IC1). Q1, Q2, and Q5 in IC2 are configured as a
low impedance, temperature-compensated source of
adjustable reference voltage for the error amplifier.
Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086
transistor-array lC) are connected in parallel as the series-
pass element. Transistor Q5 in lC3 functions as a current -
limiting device by diverting base drive from the series-pass
transistors, in accordance with the adjustment of resisto r R2.
Figure 14 contains the schematic diagram of a regulated
power-supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC1) and circuitry
associated with lC2 function as previously described,
although the output of lC1 is boosted by a discrete transistor
(Q4) to provide adequate base drive for the Darlingto n-
connected series-pass transistors Q1, Q2. Transistor Q3
functions in the previously described current-limiting circuit.
Multivibrators
The exceptionally high input resistance presented by the
CA3130 is an attractive f eature for m ultivibrator circuit design
because it permits the use of timing circuits with high R/C
ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 15. Resistors R1
and R2 are used to bias the CA3130 to the mid-point of the
supply-voltage and R3 is the feedback resistor. The pulse
repetition rate is selected by positioning S1 to the desired
position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.
Function Generator
Figure 16 contains a schemat ic diag r am of a function
generator using the CA3130 in the i nteg r ator and threshold
detector functions. This circuit gene r ates a triangular or
square-wa ve output that can be s w ept o ver a 1,000,000:1
range (0.1Hz to 100kHz) by means of a single control, R1. A
vo ltage-control inpu t is al so availab le for remote s w eep-
control.
FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
6
2
3
1
8
7
4
4.3kΩ
1Ω
+
-
43kΩ100µF
ERROR
AMPLIFIER
IC1
VOLTAGE
ADJUST
14
13
100µF
+55V
INPUT
2.2kΩ
+
-
IC2
CA3086 10, 11
Q4Q1
Q2
6
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT : <250µVRMS UP TO 100kHz
+
-
+
-
CA3130
+
-
+
-
1W
3.3kΩ
1W
5µF
9
8, 7
Q3
1, 2
3
5
4
1kΩ
62kΩ
Q5
12
10kΩ
Q2
Q1
50kΩ
Q3
1kΩ
2N3055
2N2102 CURRENT
LIMIT
ADJUST
2N5294
2N2102
Q4
1000pF
10kΩ
8.2kΩ
OUTPUT:
0.1 TO 50V
AT 1A
CA3130, CA3130A
13
The heart of the frequency-determining system is an
operational-transconductance-amplifier (O TA) (see Note 10),
lC1, oper ated as a voltage-controlled current-source . The
output, IO, is a current applied directly to the integ rating
capacitor , C1, in the feedbac k loop of th e integr ator lC2, using
a CA3130, to provide the triangular-wave output.
Potentiometer R2 is used to adjust the circuit f or slope
symmetry of positive-going and negative-going signal
excursions.
Another CA3130, IC3, is used as a controlled s witch to set the
e xcursion li mits of the triangular outp ut from the integ r a tor
circuit. Capacitor C2 is a “peaking adjustment” to optimize the
high-frequency square-w ave performance of the circuit.
Potentiometer R3 is adjustable to perfect the “amplitu de
symmetry” of the square-wave output signals. Output from
the threshold detector is fed back via resistor R4 to the input
of lC1 so as to toggle the current source from plus to minus
in generating the linear triangular wave.
Operation with Output-Stage Power-Booster
The current-sourcing and-sinking capability of the CA31 30
output stage is ea sily supplemented to provide power-boost
capability. In the circuit of Figure 17, three CMOS transistor-
pairs in a single CA3600E (see Note 12 ) lC arr ay are shown
parallel co nnected with the output stage in the CA3130. In the
Class A mode of CA3600E shown, a typical device consumes
20mA of supply current at 15V opera tion. This arrange ment
boosts the current-handling capability of the CA313 0 output
stage by abou t 2.5X.
The amplifier circuit in Figure 17 employs feedback to
establish a closed-loop gain of 48dB. The typical large-signal
bandwidth (-3dB) is 50kHz.
NOTE:
9. See file number 619 for technical information.
7
4
6
3
2
R1
100kΩ
R2
100kΩ
R3
100kΩ
ON-PERIOD
ADJUST
1MΩ
2kΩ2kΩ
OFF-PERIOD
ADJUST
1MΩ
+15V
0.01µF
OUTPUT
2kΩ
0.001µF
0.01µF
0.1µF
1µFS1CA3130
+
-
FIGURE 15. PULSE GENERATOR (ASTABLE MUL TIVIBRA T OR)
WITH PROVISIONS FOR INDEPE NDENT CON TR OL
OF “ON” AND “OFF” PERIODS
FREQUENCY RANGE:
POSITION OF S1
0.001µF
0.01µF
0.1µF
1µF
PULSE PERIOD
4µs to 1ms
40µs to 10ms
0.4ms to 100ms
4ms to 1s
NOTE:
10. See file number 475 and AN6668 for technical information.
FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
6
3
2
1
4
7
5
6
2
34
7
8
1
5
4
6
7
3
2
R4
270kΩ
+7.5V
VOLTAGE-CONTROLLED
CURRENT SOURCE
IC1
3kΩ3kΩ
10MΩ
+7.5V
R2
100kΩSLOPE
SYMMETRY
ADJUST
VOLTAGE
CONTROLLED
INPUT
-7.5V
10kΩ
10kΩ
R1
-7.5V
FREQUENCY
ADJUST
(100kHz MAX)
-7.5V
+7.5V
IOIC2
+7.5V
C1
100pF
INTEGRATOR
-7.5V
56pF
CA3130
+
-
CA3080A
+
-39kΩ
3 - 30pF
C2
ADJUST
HIGH - FREQ. DETECTOR
THRESHOLD
150kΩ
IC3
+7.5V
CA3130
+
-
R3
100kΩ
AMPLITUDE
SYMMETRY
ADJUST
22kΩ
-7.5V
(NO TE 10)
CA3130, CA3130A
14
NOTES:
11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.
12. See file number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTP UT STAGE OF THE C A3130
8
7
3
2
+15V
2kΩCA3130
+
-
41036
4 97
6
14
750kΩ
1µF
211
13 1
12
58
1µF
1MΩ0.01µF
510kΩ
500µF
QP3
QN1 QN2 QN3
QP2
QP1
CA3600E
AV(CL) = 48dB
LARGE SIGNAL
BW (-3 dB) = 50kHz
RL = 100Ω
(PO = 150mW
AT THD = 10%)
(NOTE 12)
INPUT
Typical Performance Curves
FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE
LOAD RESISTANCE = 2kΩ
150
140
130
120
110
100
90
80
-100 -50 0 50 100
OPEN LOOP VOLTAGE GAIN (dB)
TEMPERATURE (oC)
SUPPLY VOLTAGE: V+ = 15V; V- = 0
TA = 25oC
φ OL
3
2
1
1
2
3
4
4
AOL
1 - CL = 9pF, CC = 0pF, RL = ∞
2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - CL = 30pF, CC = 150pF, RL = 2kΩ
120
100
80
60
40
20
0
OPEN LOOP VOLTAGE GAIN (dB)
-100
-200
-300
OPEN LOOP PHASE (DEGREES)
102103104105106107108
FREQUENCY (Hz)
101
CA3130, CA3130A
15
FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q12) vs LOAD CURRENT
Typical Performance Curves (Continued)
LOAD RESISTANCE = ∞
TA = 25oC
V- = 0 OUTPUT VOLTAGE BALANCED = V+/2
OUTPUT VOLTAGE HIGH = V+
OR LOW = V-
17.5
12.5
10
7.5
5
2.5
06 8 10 12 14 16 18
TOTAL SUPPLY VOLTAGE (V)
QUIESCENT SUPPLY CURRENT (mA)
4
OUTPUT VOLTAGE = V+/2
V- = 0
14
12
10
8
6
4
2
0246810121416
QUIESCENT SUPPLY CURRENT (mA)
TOTAL SUPPLY VOLTAGE (V)
TA = -55oC
25oC
125oC
0
50
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1.0 10 100
MAGNITUDE OF LOAD CURRENT (mA)
VOLTAGE DROP ACROSS PMOS OUTPUT
STAGE TRANSISTOR (V)
15V
10V
NEGATIVE SUPPLY VOLTA GE = 0V
TA = 25oC
POSITIVE SUPPLY VOLTAGE = 5V
NEGATIVE SUPPLY VOLTAGE = 0V
TA = 25oC
50
10
1
0.1
0.01
0.001
0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)
VOLTAGE DROP A C ROSS NMOS OUTPUT
STAGE TRANSISTOR (V)
15V
10V
POSITIVE SUPPLY VOLTAGE = 5V
CA3130, CA3130A
16
CA3130, CA3130A
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal po sitions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.355 0.400 9.01 10.16 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
17
All Intersil U.S. products are manuf actured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. Howeve r, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license i s gr a nted b y imp lica tion or oth erw ise unde r any patent or patent rights of Intersi l or its subs idi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
CA3130, CA3130A
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
α0° 8° 0° 8° -
Rev. 1 6/05
