TL/F/11505
74VHC74 #74VHCT74 Dual D-Type Flip Flop with Preset and Clear
October 1995
74VHC74 #74VHCT74
Dual D-Type Flip Flop with Preset and Clear
General Description
The VHC/VHCT74 is an advanced high speed CMOS Dual
D-Flip Flop fabricated with silicon gate CMOS technology. It
achieves the high speed operation similar to equivalent Bi-
polar Schottky TTL while maintaining the CMOS low power
dissipation. The signal level applied to the D INPUT is trans-
ferred to the Q OUTPUT during the positive going transition
of the CK pulse. CLR and PR are independent of the CK
and are accomplished by setting the appropriate input low.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply voI-
tage. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply and
input voltages.
Features
YHigh noise immunity:
VHC VNIH eVNIL e28% VCC (min)
VHCT VIH e2.0V, VIL e0.8V
YPower down protection:
VHC inputs only
VHCT inputs and outputs
YLow power dissipation:
ICC e2mA (max) at TAe25§C
YBalanced propagation delays: tPLH jtPHL
NOTE: ADD EXTERNAL PULL UP RESISTOR TO ’VHCT
OUTPUTS TO DRIVE CMOS INPUTS
Commercial Package Number Package Description
74VHC74M M14A 14-Lead Molded JEDEC SOIC
74VHC74SJ M14D 14-Lead Molded EIAJ SOIC
74VHC74MSC MSC14 14-Lead Molded EIAJ Type 1 SSOP
74VHC74MTC MTC14 14-Lead Molded JEDEC Type 1 TSSOP
74VHC74N N14A 14-Lead Molded DIP
74VHCT74M M14A 14-Lead Molded JEDEC SOIC
74VHCT74SJ M14D 14-Lead Molded EIAJ SOIC
74VHCT74MTC MTC14 14-Lead Molded JEDEC Type 1 TSSOP
74VHCT74N N14A 14-Lead Molded DIP
Note: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter ‘‘X’’ to the ordering code.
EIAJ Type 1 SSOP available on Tape and Reel only, Order MSCX.
Logic Symbol
IEEE/IEC
TL/F/11505–1
Connection Diagram
Pin Assignment for DIP,
SSOP, TSSOP and SOIC
TL/F/11505–2
Pin Names Description
D1,D
2Data Inputs
CK1,CK
2Clock Pulse Inputs
CLR1, CLR2Direct Clear Inputs
PR1,PR
2Direct Preset Inputs
Q1,Q
1
,Q
2
,Q
2Outputs
Inputs Outputs Function
CLR PR DCK Q Q
L H X X L H Clear
H L X X H L Preset
LLXXHH
HHL£LH
HHH£HL
HHXÞQ
n
Q
n
No Change
C1995 National Semiconductor Corporation RRD-B30M125/Printed in U. S. A.