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LP38859

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LP38859 3-A Fast-Response High-Accuracy LDO Linear Regulator With Soft Start

1 Features 3 Description

The LP38859 is a high-current, fast-response

1• Input Voltage: 1.1 V to 5.5 V regulator which can maintain output voltage

• Wide VBIAS Supply Operating Range: 3 V to 5.5 V regulation with extremely low input to output voltage

• Standard VOUT Values: 0.8 V and 1.2 V drop. Fabricated on a CMOS process, the device

operates from two input voltages: VBIAS provides

• Stable With 10-µF Ceramic Capacitors voltage to drive the gate of the N-MOS power

• Dropout Voltage of 240 mV (typical) at 3-A Load transistor, while VIN is the input voltage which

Current supplies power to the load. The use of an external

• Programmable Soft-Start Time bias rail allows the part to operate from ultra-low VIN

voltages. Unlike bipolar regulators, the CMOS

• Precision Output Voltage Across All Line and architecture consumes extremely low quiescent

Load Conditions: current at any output load current. The use of an N-

– ±1% VOUT for TJ= 25°C MOS power transistor results in wide bandwidth, yet

– ±2% VOUT for 0°C ≤TJ≤+125°C minimum external capacitance is required to maintain

loop stability.

– ±3% VOUT for –40°C ≤TJ≤+125°C

• Overtemperature and Overcurrent Protection The fast transient response of this device makes it

suitable for use in powering DSP microcontroller core

• Operating Temperature Range: −40°C to +125°C voltages and switch-mode power-supply post-

regulators. The LP38859 is available in 5-pin TO-220

2 Applications and DDPAK/TO-263 packages.

• ASIC Power Supplies In: Device Information(1)

– Desktops, Notebooks, Graphics Cards, and PART

Servers PACKAGE BODY SIZE (NOM)

NUMBER

– Gaming Set Top Boxes, Printers, and Copiers DDPAK/TO-263 (5) 10.16 mm × 8.42 mm

LP38859

• Server Core and I/O Supplies TO-220 (5) 14.986 mm × 10.16 mm

• DSP and FPGA Power Supplies (1) For all available packages, see the orderable addendum at

• SMPS Post-Regulator the end of the data sheet.

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP38859

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Table of Contents

7.3 Feature Description................................................. 10

1 Features.................................................................. 17.4 Device Functional Modes........................................ 12

2 Applications ........................................................... 18 Application and Implementation ........................ 13

3 Description............................................................. 18.1 Application Information............................................ 13

4 Revision History..................................................... 28.2 Typical Application ................................................. 13

5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 16

6 Specifications......................................................... 410 Layout................................................................... 17

6.1 Absolute Maximum Ratings ...................................... 410.1 Layout Guidelines ................................................. 17

6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 17

6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 18

6.4 Thermal Information.................................................. 411.1 Community Resources.......................................... 18

6.5 Electrical Characteristics........................................... 511.2 Trademarks........................................................... 18

6.6 Typical Characteristics.............................................. 711.3 Electrostatic Discharge Caution............................ 18

7 Detailed Description............................................ 10 11.4 Glossary................................................................ 18

7.1 Overview................................................................. 10 12 Mechanical, Packaging, and Orderable

7.2 Functional Block Diagram....................................... 10 Information ........................................................... 18

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (April 2013) to Revision F Page

• Added Device Information,Pin Configuration and Functions and ESD Ratings sections, update Thermal Values, add

Feature Description,Device Functional Modes,Application and Implementation,Power Supply Recommendations,

Layout,Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections................. 1

Changes from Revision D (April 2013) to Revision E Page

• Changed layout of National data sheet to TI format .............................................................................................................. 1

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TAB

GND

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OUT

GND

SS 1

LP38859T-x.x

TAB

GND

BIAS

OUT

GND

SS 1

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5 Pin Configuration and Functions

KTT Package

5-Pin DDPAK/TO-263

Top View

NDH Package

5-Pin TO-220

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NUMBER

BIAS 5 I The supply for the internal control and reference circuitry.

GND 3 — Ground

IN 2 I The unregulated voltage input pin.

OUT 4 O The regulated output voltage pin.

SS 1 I Soft-start capacitor connection. Used to slow the rise time of VOUT at turnon.

The TAB is a thermal connection that is physically attached to the backside of the die, and

TAB TAB — used as a thermal heat-sink connection. See the Application and Implementation section for

details.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

VIN supply voltage (survival) −0.3 6 V

VBIAS supply voltage (survival) −0.3 6 V

VSS soft-start voltage (survival) −0.3 6 V

VOUT voltage (survival) −0.3 6 V

IOUT current (survival) Internally limited

Power dissipation(3) Internally limited

Junction temperature 40 150 °C

Storage temperature, Tstg −65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.

(3) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to

ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not

exceed the maximum operating rating. See the Application and Implementation section for details.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

VIN supply voltage (VOUT + VDO) VBIAS V

VBIAS supply voltage 3 5.5 V

IOUT 0 3 A

Junction temperature(1) −40 125 °C

(1) Device power dissipation must be de-rated based on device power dissipation (PD), ambient temperature (TA), and package junction to

ambient thermal resistance (RθJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not

exceed the maximum operating rating. See the Application and Implementation section for details.

6.4 Thermal Information LP38859

THERMAL METRIC(1) KTT (DDPAK/TO-263 NDH (TO-220) UNIT

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 43.2 70.7(2) °C/W

RθJC(top) Junction-to-case (top) thermal resistance 43.5 43.0 °C/W

RθJB Junction-to-board thermal resistance 23.1 n/a(2) °C/W

ψJT Junction-to-top characterization parameter 11.6 23.6(2) °C/W

ψJB Junction-to-board characterization parameter 22.0 52.2(2) °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 1.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The NDH (TO-220) package is vertically mounted in center of JEDEC High-K test board (JESD 51-7) with no additional heat sink. This is

athrough-hole package; this is NOT a surface mount package.

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6.5 Electrical Characteristics

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open.

Typical limits apply for TJ= 25°C; minimum and maximum limits apply over the junction temperature (TJ) range of -40°C to

+125°C, unless otherwise specified. Minimum and maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOUT(NOM) + 1 V ≤VIN ≤VBIAS

3 V ≤VBIAS ≤5.5 V -1% 1%

10 mA ≤IOUT ≤3 A, TJ= 25°C

VOUT(NOM) + 1 V ≤VIN ≤VBIAS

3 V ≤VBIAS ≤5.5 V –3% 3%

VOUT VOUT accuracy 10 mA ≤IOUT ≤3 A

VOUT(NOM) + 1 V ≤VIN ≤VBIAS

3 V ≤VBIAS ≤5.5 V –2% 2%

10 mA ≤IOUT ≤3 A

0°C ≤TJ≤+125°C

ΔVOUT/ΔVIN Line regulation, VIN(1) VOUT(NOM) + 1 V ≤VIN ≤VBIAS 0.04 %/V

ΔVOUT/ΔVBIAS Line regulation, VBIAS(1) 3 V ≤VBIAS ≤5.5 V 0.10 %/V

ΔVOUT/ΔIOUT Output voltage load regulation(2) 10 mA ≤IOUT ≤3 A 0.2 %/A

IOUT = 3 A, TJ= 25°C 240 300

VDO Dropout voltage(3) mV

IOUT = 3 A 450

LP38859-0.8 7 8.5

10 mA ≤IOUT ≤3 A, TJ= 25°C

LP38859-0.8 9

10 mA ≤IOUT ≤3 A

Quiescent current drawn from

IGND(IN) mA

VIN supply LP38859-1.2 11 12

10 mA ≤IOUT ≤3 A, TJ= 25°C

LP38859-1.2 15

10 mA ≤IOUT ≤3 A

10 mA ≤IOUT ≤3 A, TJ= 25°C 3 3.8

Quiescent current drawn from

IGND(BIAS) mA

VBIAS supply 10 mA ≤IOUT ≤3 A 4.5

VBIAS rising until device is functional 2.2 2.45 2.7

TJ= 25°C

UVLO Undervoltage lockout threshold V

VBIAS rising until device is functional 2 2.9

VBIAS falling from UVLO threshold

until device is non-functional 60 150 300

TJ= 25°C

UVLO(HYS) Undervoltage lockout hysteresis mV

VBIAS falling from UVLO threshold 50 350

until device is non-functional

VIN = VOUT(NOM) + 1 V

ISC Output short-circuit current 6.2 A

VBIAS = 3 V, VOUT = 0 V

SOFT-START

LP38859-0.8 11 13.5 16

rSS Soft-start internal resistance kΩ

LP38859-1.2 13.5 16 18.5

LP38859-0.8, CSS = 10 nF 675

Soft-start time

tSS μs

tSS = CSS × rSS × 5 LP38859-1.2, CSS = 10 nF 800

(1) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

(2) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load

to full load.

(3) Dropout voltage is defined the as input to output voltage differential (VIN – VOUT) where the input voltage is low enough to cause the

output voltage to drop no more than 2% from the nominal value.

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Electrical Characteristics (continued)

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1 µF, CSS = open.

Typical limits apply for TJ= 25°C; minimum and maximum limits apply over the junction temperature (TJ) range of -40°C to

+125°C, unless otherwise specified. Minimum and maximum limits are specified through test, design, or statistical correlation.

Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC PARAMETERS

VIN = VOUT(NOM) + 1 V 80

ƒ = 120 Hz

PSRR Ripple rejection for VIN input

(VIN) voltage VIN = VOUT(NOM) + 1 V 65

ƒ = 1 kHz dB

VBIAS = VOUT(NOM) + 3 V 58

f = 120 Hz

PSRR Ripple rejection for VBIAS voltage

(VBIAS)VBIAS = VOUT(NOM) + 3 V 58

ƒ = 1 kHz

Output noise density ƒ = 120 Hz 1 µV/√Hz

BW = 10 Hz −100 kHz, VOUT = 1.8 V 150

enOutput noise voltage µVRMS

BW = 300 Hz −300 kHz, VOUT = 1.8 90

THERMAL PARAMETERS

Thermal shutdown junction

TSD 160 °C

temperature

TSD(HYS) Thermal shutdown hysteresis 10 °C

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6.6 Typical Characteristics

Unless otherwise specified: TJ= 25°C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-µF ceramic, CBIAS =

1-µF ceramic, CSS = open.

Figure 1. VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS Figure 2. VBIAS Ground Pin Current (IGND(BIAS)) vs

Temperature

Figure 3. VIN Ground Pin Current vs Temperature Figure 4. Load Regulation vs Temperature

Figure 5. Dropout Voltage (VDO) vs Temperature Figure 6. Output Current Limit (ISC) vs Temperature

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Typical Characteristics (continued)

Unless otherwise specified: TJ= 25°C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-µF ceramic, CBIAS =

1-µF ceramic, CSS = open.

Figure 8. UVLO Thresholds vs Temperature

Figure 7. VOUT vs Temperature

Figure 9. Soft-Start Resistor (RSS) vs Temperature Figure 10. Soft-Start RSS Variation vs Temperature

10 nF To 47 nF

Figure 11. VOUT vs CSS Figure 12. VIN Line Transient Response

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Typical Characteristics (continued)

Unless otherwise specified: TJ= 25°C, VIN = VOUT(NOM) + 1 V, VBIAS = 3 V, IOUT = 10 mA, CIN = COUT = 10-µF ceramic, CBIAS =

1-µF ceramic, CSS = open.

Figure 13. VIN Line Transient Response Figure 14. VBIAS Line Transient Response

Figure 15. VBIAS Line Transient Response Figure 16. VBIAS PSRR

Figure 17. VIN PSRR Figure 18. Output Noise

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7 Detailed Description

7.1 Overview

The LP38559 is a fast-response, high-current, low-dropout regulator, available in output voltages are 0.8 V and

1.2 V. This part is capable of delivering 3-A continuous load current. Standard regulator features, such as

overcurrent and over temperature protection, are also included. The LP38559 contains several features:

• Low dropout voltage, typical 240 mV at 3-A load.

• The bias voltage(VBIAS) provides voltage to drive the gate of the N-MOS power transistor.

• The input voltage(VIN) is the input voltage which supplies power to the load.

• Programmable soft-start time.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Input Voltage

The input voltage (VIN) is the high current external voltage rail that is regulated down to a lower voltage, which is

applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever values is used

for VBIAS.

7.3.2 Bias Voltage

The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide

gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3 V to 5.5 V to ensure proper

operation of the device.

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Feature Description (continued)

7.3.3 Undervoltage Lockout

The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is

below the undervoltage lockout (UVLO) threshold of approximately 2.45 V.

As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is

approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.

When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V, the device

is functional, but the operating parameters are not within the specified limits.

7.3.4 Supply Sequencing

There is no requirement for the order that VIN or VBIAS are applied or removed.

One practical limitation is that the soft-start circuit starts charging CSS when VBIAS rises above the UVLO

threshold. If the application of VIN is delayed beyond this point the benefits of soft start are compromised.

In any case, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified

operating values.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin

must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.

7.3.5 Reverse Voltage

A reverse voltage condition exists when the voltage at the output pin is higher than the voltage at the input pin.

Typically this happens when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that

the input to output voltage becomes reversed.

The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass

element is not driven, there is no reverse current flow through the pass element during a reverse voltage event.

The gate of the pass element is not driven when VBIAS is below the UVLO threshold.

When VBIAS is above the UVLO threshold, the control circuitry is active and attempts to regulate the output

voltage. Because the input voltage is less than the output voltage the control circuit drives the gate of the pass

element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current flows

from the OUT pin to the IN pin , limited only by the RDS(ON) of the pass element and the output to input voltage

differential. This condition is outside the specified operating range and must be avoided.

7.3.6 Soft-Start

The LP38859 incorporates a soft-start function that reduces the start-up current surge into the output capacitor

(COUT) by allowing VOUT to rise slowly to the final value. This is accomplished by controlling VREF at the SS pin.

The soft-start timing capacitor (CSS) is internally held to ground until VBIAS rises above the UVLO threshold.

VREF rises at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor

connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state

regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is

sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in

current limit.

Soft-Start Time = CSS × rSS × 5 (1)

Because the VOUT rise is exponential, not linear, the in-rush current peaks during the first time constant (τ), and

VOUT requires four additional time constants (4τ) to reach the final value (5τ) .

After achieving normal operation, if VBIAS falsl below the ULVO threshold, the device output is disabled, and the

soft-start capacitor (CSS) discharge circuit becomes active. The CSS discharge circuit remains active until VBIAS

falls to 500 mV (typical). When VBIAS falls below 500 mV (typical), the CSS discharge circuit ceases to function

due to a lack of sufficient biasing to the control circuitry.

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Feature Description (continued)

Because VREF appears on the SS pin, any leakage through CSS causes VREF to fall, and thus affect VOUT. A

leakage of 50 nA (about 10 MΩ) through CSS causes VOUT to be approximately 0.1% lower than nominal, while a

leakage of 500 nA (about 1 MΩ) causes VOUT to be approximately 1% lower than nominal. Typical ceramic

capacitors have a factor of 10× difference in leakage between 25°C and 85°C, so the maximum ambient

temperature must be included in the capacitor selection process.

Typical CSS values are in the range of 1 nF to 100 nF, providing typical soft-start times in the range of 70 μs to 7

ms (5τ). Values less than 1 nF can be used, but the soft-start effect is minimal. Values larger than 100 nF

provide soft start, but may not be fully discharged if VBIAS falls from the UVLO threshold to less than 500 mV in

less than 100 µs.

Figure 19 shows the relationship between the COUT value and a typical CSS value.

Figure 19. Typical CSS vs COUT Values

The CSS capacitor must be connected to a clean ground path back to the device ground pin. No components,

other than CSS, should be connected to the SS pin, as there could be adverse effects to VOUT.

If the soft-start function is not needed, the SS pin must be left open, although some minimal capacitance value is

always recommended.

7.4 Device Functional Modes

7.4.1 Operation with 3 V ≤VBIAS ≤5.5 V, VOUT(TARGET)+ 0.3 V ≤VIN ≤VBIAS

The device operates if the bias voltage is equal to, or exceeds, 3 V, and input voltage is equal to, or exceeds,

VOUT(TARGET) + 0.3 V. At bias voltages below the minimum VBIAS requirement, the device does not operate

correctly, and output voltage may not reach target value.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP38859 can provide 3-A output current with 240-mV dropout voltage (typical). The bias voltage must be in

the range of 3 V to 5.5 V to ensure proper operation of the device. The input voltage must be at least VOUT +

VDO, and no higher than whatever value is used for VBIAS. Minimal input and output capacitors are each 10 μF.

The capacitor on the BIAS pin must be at least 1 μF.

8.2 Typical Application

Figure 20. LP38859 Typical Application

8.2.1 Design Requirements

For typical high-accuracy LDO linear regulator applications, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Bias voltage 3 V to 5.5 V

Input voltage 1.1 V to 5.5 V

Output voltages 0.8 V, 1.2 V

Output current 3 A (maximum)

Bias capacitor 1 μF (minimum)

Input capacitor 10 μF (minimum)

Output capacitor 10 uF (minimum)

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

To assure regulator stability, input and output capacitors are required as shown in the Figure 20.

8.2.2.1.1 Output Capacitor

A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can

be increased without limit. The output capacitor must be located less than 1 cm from the OUT pin of the device

and returned to the device GND pin with a clean analog ground.

Only high quality ceramic types such as X5R or X7R must be used, as the Z5U and Y5F types do not provide

sufficient capacitance over temperature.

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Tantalum capacitors also provide stable operation across the entire operating temperature range. However, the

effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum

recommended 10-µF ceramic capacitor at the output allows unlimited capacitance, tantalum, and/or aluminum, to

be added in parallel.

8.2.2.1.2 Input Capacitor

The input capacitor must be at least 10 µF, but can be increased without limit. Its purpose is to provide a low

source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.

Tantalum capacitors may also be used at the IN pin. There is no specific ESR limitation on the input capacitor

(the lower, the better).

Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at

cold temperatures. They are not recommended for any application where the ambient temperature falls below

0°C.

8.2.2.1.3 Bias Capacitor

The capacitor on the BIAS pin must be at least 1 µF and can be any good-quality capacitor (ceramic is

recommended).

8.2.2.2 Power Dissipation and Heat-Sinking

Additional copper area for heat-sinking may be required depending on the maximum device dissipation (PD) and

the maximum anticipated ambient temperature (TA) for the device. Under all possible conditions, the junction

temperature must be within the range specified under operating conditions.

The total power dissipation of the device is the sum of three different points of dissipation in the device.

The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula:

PD(PASS) = (VIN – VOUT)×IOUT (2)

The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the

formula:

PD(BIAS) = VBIAS × IGND(BIAS)

where

• IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS. (3)

The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with

the formula:

PD(IN) = VIN × IGND(IN)

where

• IGND(IN) is the portion of the operating ground current of the device that is related to VIN. (4)

The total power dissipation is then:

PD= PD(PASS) + PD(BIAS) + PD(IN) (5)

The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient

temperature (TA) for the application, and the maximum allowable operating junction temperature (TJ(MAX)) .

ΔTJ= TJ(MAX) – TA(MAX) (6)

The maximum allowable value for junction-to-ambient thermal resistance, RθJA, can be calculated using

Equation 7.

RθJA ≤ ΔTJ/ PD(7)

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8.2.3 Application Curves

COUT = 10-µF ceramic COUT = 10-µF ceramic

Figure 21. Load Transient Response Figure 22. Load Transient Response

COUT = 100-µF ceramic COUT = 100-µF ceramic

Figure 23. Load Transient Response Figure 24. Load Transient Response

COUT = 100-µF tantalum COUT = 100-µF tantalum

Figure 25. Load Transient Response Figure 26. Load Transient Response

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9 Power Supply Recommendations

The LP38859 device is designed to operate from an input voltage supply range from 3 V and 5.5 V. The input

voltage range provides adequate headroom in order for the device to have a regulated output. This input supply

must be well regulated. An input capacitor of at least 10 μF is required.

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10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP38859 is dependent on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38859. Best

performance is achieved by placing CIN and COUT on the same side of the PCB as the LP38859, and as close as

is practical to the package. The ground connections for CIN and COUT must be back to the LP38859 ground pin

using as wide and short of a copper trace as is practical.

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP38859 using

traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND

pins. The regulator ground pin must be connected to the external circuit ground so that the regulator and its

capacitors have a single-point ground.

Stability problems have been seen in applications where vias to an internal ground plane were used at the

ground points of the LP38859 device and the input and output capacitors. This was caused by varying ground

potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground

technique for the regulator and its capacitors fixed the problem.

Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect

the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors.

10.2 Layout Example

Figure 27. LP38859 Layout Example

Product Folder Links: LP38859

LP38859

SNVS337F –JUNE 2006–REVISED SEPTEMBER 2015

www.ti.com

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LP38859

PACKAGE OPTION ADDENDUM

www.ti.com 8-Oct-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP38859S-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38859S

-1.2

LP38859SX-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38859S

-1.2

LP38859T-0.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38859T

-0.8

LP38859T-1.2/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38859T

-1.2

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Oct-2015

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP38859SX-1.2/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP38859SX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

MECHANICAL DATA

NDH0005D

www.ti.com

MECHANICAL DATA

KTT0005B

www.ti.com

BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

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LP38859S-0.8 LP38859S-0.8/NOPB LP38859S-1.2 LP38859S-1.2/NOPB LP38859SX-0.8 LP38859SX-0.8/NOPB

LP38859SX-1.2 LP38859SX-1.2/NOPB LP38859T-0.8 LP38859T-0.8/NOPB LP38859T-1.2 LP38859T-1.2/NOPB