19-1979; Rev 1; 9/05 Quad-Output TFT LCD DC-DC Converters with Buffer Features The MAX1778/MAX1880-MAX1885 multiple-output DC-DC converters provide the regulated voltages required by active matrix thin-film transistor (TFT) liquid crystal displays (LCD) in a low-profile TSSOP package. One high-power step-up converter and two low-power charge pumps convert the 2.7V to 5.5V input voltage into three independent output voltages. A built-in linear regulator and VCOM buffer complete the power-supply requirements. The main step-up converter accurately generates an externally set output voltage up to 13V that can supply the display's row/column drivers. The converter's high switching frequency and current-mode PWM architecture provide fast transient response and allow the use of small low-profile inductors and ceramic capacitors. The low-power BiCMOS control circuitry and internal 14V switch (0.35 N-channel MOSFET) enable efficiencies up to 91%. 500kHz/1MHz Current-Mode PWM Step-Up Regulator Up to +13V Main High-Power Output 1% Accurate High Efficiency (91%) Dual Regulated Charge-Pump Outputs (MAX1778/MAX1880/MAX1881/MAX1882 only) Up to +40V Positive Charge-Pump Output Up to -40V Negative Charge-Pump Output Low-Dropout 40mA Linear Regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) Up to +15V LDO Input Optional Higher Current with External Transistor The dual low-power charge pumps (MAX1778/ MAX1880/MAX1881/MAX1882 only) independently regulate one positive output (VPOS) and one negative output (V NEG ). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages up to +40V and -40V. A unique control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. A resistor-programmable, 40mA, low-dropout linear regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) provides preregulation or postregulation for any of the supplies. For higher current applications, an external transistor can be added. Additionally, the VCOM buffer provides a high current output that is ideal for driving the capacitive backplane of TFT LCD panels. The VCOM buffer's output voltage is preset with an internal 50% resistive-divider or can be externally adjusted for other voltages. The MAX1778/MAX1880-MAX1885 are protected against output undervoltage and thermal overload conditions by a latched fault detection circuit that shuts down the device. All devices are available in the ultrathin TSSOP package (1.1mm max height). Adjustable Fault-Detection Latch Applications 2.7V to 5.5V Input Supply Internal Supply Sequencing and Soft-Start Power-Ready Output Thermal Protection (+160C) 0.1A Shutdown Current 0.7mA IN Quiescent Current Ultra-Small External Components Thin TSSOP Package (1.1mm max height) Ordering Information TEMP RANGE PIN-PACKAGE MAX1778EUG PART -40C to +85C 24 TSSOP MAX1778EUG+ -40C to +85C 24 TSSOP MAX1880EUG -40C to +85C 24 TSSOP MAX1881EUG -40C to +85C 24 TSSOP MAX1882EUG -40C to +85C 24 TSSOP MAX1883EUP -40C to +85C 20 TSSOP MAX1884EUP -40C to +85C 20 TSSOP MAX1885EUP -40C to +85C 20 TSSOP + Denotes lead-free package. TFT LCD Notebook Displays TFT LCD Desktop Monitor Panels Typical Operating Circuit appears at end of data sheet. Pin Configurations and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX1778/MAX1880-MAX1885 General Description MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer ABSOLUTE MAXIMUM RATINGS IN, SHDN, TGND, FLTSET to GND...........................-0.3V to +6V DRVN to GND .........................................-0.3V to (VSUPN + 0.3V) DRVP to GND..........................................-0.3V to (VSUPP + 0.3V) PGND to GND.....................................................................0.3V RDY, SUPB to GND ................................................-0.3V to +14V LX, SUPP, SUPN to PGND .....................................-0.3V to +14V SUPL to GND..........................................................-0.3V to +18V LDOOUT to GND ....................................-0.3V to (VSUPL + 0.3V) INTG, REF, FB, FBN, FBP to GND ...............-0.3V to (VIN + 0.3V) FBL to GND .............-0.3V to the lower of (VSUPL + 0.3V) or +6V BUFOUT, BUF+, BUF- to GND ...............-0.3V to (VSUPB + 0.3V) Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 10.9mW/C above +70C) ......879mW 24-Pin TSSOP (derate 12.2mW/C above +70C) ......975mW Operating Temperature Range MAX1778EUG, MAX1883EUP ........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER Input Supply Range Input Undervoltage Threshold IN Quiescent Supply Current SUPP Quiescent Current SUPN Quiescent Current SYMBOL CONDITIONS VIN VUVLO IIN ISUPP ISUPN MIN TYP 2.7 VIN rising, 40mV hysteresis (typ) VFB = VFBP = 1.5V, VFBN = -0.2V VFBP = 1.5V VFBN = -0.2V 2.2 MAX UNITS 5.5 V V 2.4 2.6 MAX1778/MAX1880/ MAX1883 (fOSC = 1MHz) 0.7 1 MAX1881/MAX1882/ MAX1884/MAX1885 (fOSC = 500kHz) 0.6 1 MAX1778/MAX1880 (fOSC = 1MHz) 0.4 0.7 MAX1881/MAX1882 (fOSC = 500kHz) 0.3 0.5 MAX1778/MAX1880 (fOSC = 1MHz) 0.4 0.7 MAX1881/MAX1882 (fOSC = 500kHz) 0.3 0.5 mA mA mA IN Shutdown Current VSHDN = 0, VIN = 5V 0.1 10 A SUPP Shutdown Current VSHDN = 0, VSUPP = 13V, MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 A SUPN Shutdown Current VSHDN = 0, VSUPN = 13V, MAX1778/MAX1880/MAX1881/MAX1882 0.1 10 A SUPL Shutdown Current VSHDN = 0, VSUPL = 13V MAX1778/MAX1881/MAX1883/MAX1884 0.1 10 A SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 6 13 A 2 _______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 13 V 1.247 1.260 MAIN STEP-UP CONVERTER Main Output Voltage Range VMAIN FB Regulation Voltage VFB FB Input Bias Current IFB Operating Frequency fOSC VIN Integrator enabled, CINTG = 1000pF 1.234 Integrator disabled (INTG = REF) 1.220 V VFB = 1.25V, INTG = GND -50 +50 nA MAX1778/MAX1880/MAX1883 0.85 1 1.15 MHz MAX1881/MAX1882/MAX1884/MAX1885 425 500 575 kHz 80 85 91 % Oscillator Maximum Duty Cycle ILX = 0 to 200mA, VMAIN = 10V Load Regulation 1.280 Integrator enabled, CINTG = 1000pF 0.01 Integrator disabled (INTG = REF) 0.2 % Line Regulation 0.1 %/V Integrator Transconductance 317 s LX Switch On-Resistance LX Leakage Current RLX(ON) ILX ILX = 100mA 0.35 0.7 VLX = 13V 0.01 20 A 0.38 0.5 Phase I = soft-start (1024/fOSC) LX Current Limit ILIM 0.275 Phase II = soft-start (1024/fOSC) 0.75 Phase III = soft-start (1024/fOSC) 1.12 Phase IV = fully-on (after 3072/fOSC) 1.15 Maximum RMS LX Current Soft-Start Period tSS FB Fault Trip Level Power-up to the end of Phase III fCHP FBP Regulation Voltage VFBP FBP Input Bias Current DRVP PCH On-Resistance DRVP NCH On-Resistance IFBP FBP Fault Trip Level A s 1.07 1.1 1.14 0.955 0.99 1.025 2.7 13 VFBP = 1.5V 1.25 V 1.3 V +50 nA 5 10 2 4 -50 VFBP = 1.2V V Hz 0.5 x fOSC 1.2 k VFBP = 1.3V 20 Rising edge 1.09 1.125 Falling edge, FLTSET = GND 1.08 1.11 1.16 Falling edge, FLTSET = 1V 0.955 0.99 1.025 Maximum RMS DRVP Current FBP Power-Ready Trip Level 1 3072 / fOSC Falling edge, FLTSET = GND RPCH(ON) RNCH(ON) 1.85 Falling edge, FLTSET = 1V POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only) VSUPP SUPP Input Supply Range Operating Frequency 1.5 A A 0.1 1.16 V V _______________________________________________________________________________________ 3 MAX1778/MAX1880-MAX1885 ELECTRICAL CHARACTERISTICS (continued) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer ELECTRICAL CHARACTERISTICS (continued) (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only) SUPN Input Supply Range VSUPN Operating Frequency fCHP FBN Regulation Voltage VFBN FBN Input Bias Current IFBN DRVN PCH On-Resistance RPCH(ON) DRVN NCH On-Resistance RNCH(ON) 2.7 13 0.5 x fOSC -50 VFBN = 0 0 +50 mV +50 nA 5 10 2 4 -50 VFBN = +50mV 20 VFBN = -50mV k 0.1 Maximum RMS DRVN Current V Hz A FBN Power-Ready Trip Level Falling edge 80 125 165 mV FBN Fault Trip Level Rising edge 80 140 190 mV 15 V 4 4.3 V A LOW-DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only) SUPL Input Supply Range VSUPL SUPL Undervoltage Lockout SUPL Quiescent Current Dropout Voltage (Note 1) FBL Regulation Voltage 4.5 Rising edge, 50mV hysteresis (typ) ISUPL ILDO = 100A VDROP LDO is set to regulate at 9V VFBL 3.8 120 220 ILDO = 40mA 130 300 ILDO = 5mA 70 VSUPL = 10V, LDO regulating at 9V, ILDO = 15mA 1.235 1.25 mV 1.265 V LDO Load Regulation VSUPL = 10V, LDO regulating at 9V, ILDO = 100A to 40mA 1.2 % LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT, ILDO = 15mA 0.02 %/V +0.8 A 220 mA 13 V 850 A +10 A FBL Input Bias Current LDO Current Limit IFBL ILDOLIM VFBL = 1.25V VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V -0.8 40 130 VCOM BUFFER SUPB Input Supply Range VSUPB SUPB Quiescent Current ISUPB 4.5 VSUPB = 13V BUFOUT Leakage Current Power-Supply Rejection Ratio PSRR Input Common-Mode Voltage Range VCM Common-Mode Rejection Ratio Input Bias Current Input Offset Current Gain Bandwidth Product 4 420 -10 CMRR VSUPB = 4.5V to 13V, VCM = 2.25V 85 |VOS| < 10mV 1.2 VCM = 1.2V to 8.8V VCM = 5V -100 IOS VCM = 5V -100 CBUF = 1F 8.8 V dB 75 IBIAS GBW dB 98 -10 13 _______________________________________________________________________________________ +100 nA +100 nA kHz Quad-Output TFT LCD DC-DC Converters with Buffer (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.) PARAMETER Output Voltage SYMBOL VBUFOUT Input Offset Voltage Output Voltage Swing High Output Voltage Swing Low Peak Buffer Output Current VOS VOH CONDITIONS BUF+ = GND VSUPB = 4.5V to 13V, VCM = 1.2V to (VSUPB -1.2V) MIN MAX IBUFOUT = 0 4.99 5.01 IBUFOUT = 5mA 4.97 5.03 IBUFOUT = 45mA 4.93 5.07 IBUFOUT = 5mA -30 30 IBUFOUT = 45mA -70 70 UNITS V mV IBUFOUT = -45mA, VOS = 1V 9 VOL IBUFOUT = +45mA, VOS = 1V Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. BUF+ Dual ModeTM Threshold Voltage TYP Falling edge, 20mV hysteresis (typ) 9.6 0.4 V 1 150 V mA 80 125 170 mV 1.231 1.25 1.269 V 0.9 1.05 1.2 V 0.9 V REFERENCE Reference Voltage VREF -2A < IREF < 50A Reference Undervoltage Threshold LOGIC SIGNALS SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current 2.1 ISHDN V 0.01 0.67 x VREF FLTSET Input Voltage Range 80 1 A 0.85 x VREF V FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 125 170 mV FLTSET Input Current VFLTSET = 1V 0.1 50 nA RDY Output Low Voltage ISINK = 2mA 0.25 0.5 V RDY Output High Leakage V RDY = 13V 0.01 1 A Thermal Shutdown Rising temperature 160 C Dual Mode is a registered trademark of Maxim Integrated Products, Inc. _______________________________________________________________________________________ 5 MAX1778/MAX1880-MAX1885 ELECTRICAL CHARACTERISTICS (continued) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer ELECTRICAL CHARACTERISTICS (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL Input Supply Range VIN Input Undervoltage Threshold VUVLO IN Quiescent Supply Current SUPP Quiescent Current SUPN Quiescent Current IIN ISUPP ISUPN CONDITIONS VIN Rising, 40mV hysteresis (typ) VFB = VFBP = 1.5V, VFBN = -0.2V VFBP = 1.5V VFBN = -0.2V MIN MAX UNITS 2.7 5.5 V 2.2 2.6 V MAX1778/MAX1880/ MAX1883 (fOSC = 1MHz) 1 MAX1881/MAX1882/MAX1884/ MAX1885 (fOSC = 500kHz) 1 mA MAX1778/MAX1880 (fOSC = 1MHz) 0.7 MAX1881/MAX1882 (fOSC = 500kHz) 0.5 MAX1778/MAX1880 (fOSC = 1MHz) 0.7 MAX1881/MAX1882 (fOSC = 500kHz) 0.5 mA mA IN Shutdown Current VSHDN = 0, VIN = 5V 10 A SUPP Shutdown Current VSHDN = 0, VSUPP = 13V, MAX1778/MAX1880/MAX1881/MAX1882 10 A SUPN Shutdown Current VSHDN = 0, VSUPN = 13V, MAX1778/MAX1880/MAX1881/MAX1882 10 A SUPL Shutdown Current VSHDN = 0, VSUPL = 13V, MAX1778/MAX1881/MAX1883/MAX1884 10 A SUPB Shutdown Current VSHDN = 0, VSUPB = 13V 13 A VIN 13 V Integrator enabled, CINTG = 1000pF 1.223 1.269 Integrator disabled (INTG = REF) 1.21 1.29 VFB = 1.25V, INTG = GND -50 +50 nA MAX1778/MAX1880/MAX1883 0.75 1.25 MHz MAX1881/MAX1882/MAX1884/MAX1885 375 625 kHz 79 91 % MAIN STEP-UP CONVERTER Main Output Voltage Range VMAIN FB Regulation Voltage VFB FB Input Bias Current IFB Operating Frequency FOSC Oscillator Maximum Duty Cycle LX Switch On-Resistance ILX LX Current Limit ILIM FB Fault Trip Level 6 RLX(ON) LX Leakage Current V ILX = 100mA 0.7 VLX = 13V 20 A Phase I = soft-start (1024/fOSC) 0.275 0.525 Phase IV = fully on (after 3072/fOSC) 1.1 2.05 Falling edge, FLTSET = GND 1.07 1.14 _______________________________________________________________________________________ A V Quad-Output TFT LCD DC-DC Converters with Buffer (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS POSITIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only) SUPP Input Supply Range FBP Regulation Voltage FBP Input Bias Current DRVP PCH On-Resistance DRVP NCH On-Resistance VSUPP 2.7 13 V VFBP 1.2 1.3 V -50 +50 nA 10 4 IFBP VFBP = 1.5V RPCH(ON) RNCH(ON) FBP Power-Ready Trip Level VFBP = 1.2V VFBP = 1.3V 20 Rising edge 1.09 k 1.16 V NEGATIVE CHARGE PUMP (MAX1778/MAX1880/MAX1881/MAX1882 only) SUPN Input Supply Range VSUPN 2.7 13 V FBN Regulation Voltage VFBN -50 +50 mV FBN Input Bias Current IFBN -50 +50 nA DRVN PCH On-Resistance DRVN NCH On-Resistance VFBN = 0 RPCH(ON) RNCH(ON) FBN Power-Ready Trip Level VFBN = +50mV VFBN = -50mV 20 Falling edge 80 10 4 k 165 mV LOW DROPOUT LINEAR REGULATOR (MAX1778/MAX1881/MAX1883/MAX1884 only) SUPL Input Supply Range VSUPL SUPL Undervoltage Lockout Rising edge, 50mV hysteresis (typ) 4.5 15 V 3.8 4.3 V SUPL Quiescent Current ISUPL ILDO = 100A 240 A Dropout Voltage (Note 1) VDROP LDO regulating to 9V, ILDO = 40mA 330 mV VFBL VSUPL = 10V, LDO regulating to 9V, ILDO = 15mA 1.265 V FBL Regulation Voltage 1.222 LDO Load Regulation VSUPL = 10V, LDO regulating to 9V, ILDO = 100A to 40mA 1.2 % LDO Line Regulation VSUPL = 4.5V to 15V, FBL = LDOOUT, ILDO = 15mA 0.02 %/V FBL Input Bias Current LDO Current Limit IFBL ILDOLIM VFBL = 1.25V VSUPL = 10V, VLDOOUT = 9V, VFBL = 1.2V -1.2 +1.2 A 40 260 mA VCOM BUFFER SUPB Input Supply Range VSUPB SUPB Quiescent Current ISUPB VSUPB = 13V 4.5 BUFOUT Leakage Current Input Common-Mode Voltage VCM |VOS| < 10mV 13 V 850 A -10 +10 A 1.2 8.8 V _______________________________________________________________________________________ 7 MAX1778/MAX1880-MAX1885 ELECTRICAL CHARACTERISTICS (continued) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer ELECTRICAL CHARACTERISTICS (continued) (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = VSUPB = VSUPL = 10V, LDOOUT = FBL, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, CREF = 0.22F, CBUF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER Input Bias Current Input Offset Current Output Voltage Input Offset Voltage SYMBOL CONDITIONS MIN MAX UNITS IBIAS VCM = 5V -500 +500 nA IOS VCM = 5V -500 +500 nA IBUFOUT = 0 4.988 5.012 VBUFOUT VOS BUF+ = GND VSUPB = 4.5V to 13V VCM = 1.2V to (VSUPB - 1.2V) IBUFOUT = 5mA 4.97 5.03 IBUFOUT = 45mA 4.93 5.07 IBUFOUT = 5mA -30 30 IBUFOUT = 45mA -70 70 mV Output Voltage Swing High VOH IBUFOUT = -45mA, VOS = 1V Output Voltage Swing Low VOL IBUFOUT = +45mA, VOS = 1V BUF+ Dual Mode Threshold Voltage V Falling edge, 20mV hysteresis (typ) 9 V 1 V 80 170 mV 1.223 1.269 V 0.9 1.2 V 0.9 V 1 A REFERENCE Reference Voltage VREF -2A < IREF < 50A Reference Undervoltage Threshold LOGIC SIGNALS SHDN Input Low Voltage SHDN Input High Voltage SHDN Input Current 2.1 V I SHDN FLTSET Input Voltage Range 0.74 x VREF 0.85 x VREF 80 FLTSET Threshold Voltage Rising edge, 25mV hysteresis (typ) 170 mV FLTSET Input Current VFLTSET = 1V 50 nA RDY Output Low Voltage ISINK = 2mA 0.5 V RDY Output High Leakage V RDY = 13V 1 A Note 1: Dropout Voltage is defined as the VSUPL - VLDOOUT, when VSUPL is 100mV below the set value of VLDOOUT. Note 2: Specifications to -40C are guaranteed by design, not production tested. 8 V _______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer MAIN 8V OUTPUT EFFICIENCY vs. LOAD CURRENT VIN = 5V 8.00 90 EFFICIENCY (%) 7.96 CINTG = 470pF RCOMP = 24k CCOMP = 470pF 7.92 70 200 400 600 800 VIN = 5V VOUT = 8V RCOMP = 24k CCOMP = 470pF CINTG = 470pF 11.84 0 200 FIGURE 8 CINTG = 470pF 11.76 400 600 0 800 100 200 300 400 500 600 IOUT (mA) MAIN 12V OUTPUT EFFICIENCY vs. LOAD CURRENT STEP UP CONVERTERS SWITCHING FREQUENCY vs. INPUT VOLTAGE POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT 70 60 FIGURE 8 VOUT = 12V CINTG = 470pF 50 MAX1778 toc05 20.2 1.15 1.05 1.00 300 400 500 VSUPP = 8V 19.6 0.95 0.90 VSUPP = 7.5V VSUPP = 7V 19.4 19.2 0.80 200 19.8 0.85 40 100 VSUPP = 10V 20.0 1.10 VPOS (V) VIN = 3.3V MAX1778 SWITCHING FREQUENCY (MHz) MAX1778 toc04 90 1.20 MAX1778 toc06 IOUT (mA) VIN = 5V 0 12.00 IOUT (mA) 100 80 VIN = 3.3V 11.92 60 40 0 2.5 600 3.0 3.5 4.0 4.5 5.0 0 5.5 5 10 15 20 IOUT (mA) VIN (V) IPOS (mA) POSITIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT MAXIMUM POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT VSUPP = 7.5V 80 35 VPOS (V) 70 VSUPP = 10V 60 50 40 VPOS = 20V 30 5 10 INEG (mA) 15 20 VSUPN = 6V VSUPN = 7V IPOS = 1mA 25 IPOS = 10mA 20 -4.96 -4.98 15 -5.00 10 -5.02 VSUPN = 8V -5.04 5 0 -4.92 -4.94 30 VSUPP = 8V -4.90 MAX1778 toc09 VSUPP = 7V 90 40 MAX1778 toc07 100 VNEG (V) EFFICIENCY (%) 12.08 VIN = 3.3V 50 7.88 EFFICIENCY (%) 80 12.16 MAX1778 toc08 VOUT (V) 8.04 VIN = 5V VOUT (V) VIN = 3.3V 12.24 MAX1778 toc02 8.08 100 MAX1778 toc01 8.12 MAIN 12V OUTPUT VOLTAGE vs. LOAD CURRENT MAX1778 toc03 MAIN 8V OUTPUT VOLTAGE vs. LOAD CURRENT 2 4 6 8 VSUPP (V) 10 12 14 0 10 20 INEG (mA) 30 _______________________________________________________________________________________ 40 9 MAX1778/MAX1880-MAX1885 Typical Operating Characteristics (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) 90 -4 VSUPN = 6V 1.26 -6 60 VNEG (V) VSUPN = 7V 70 INEG = 10mA -8 VREF (V) 80 INEG = 1mA VSUPN = 8V 1.25 -10 50 1.24 -12 40 30 1.23 -14 0 10 20 INEG (mA) 30 2 40 4 6 8 10 12 0 14 20 40 60 80 100 IREF (A) VSUPN (V) STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE WITHOUT INTEGRATOR STEP-UP CONVERTER LOAD-TRANSIENT RESPONSE (1s PULSES) MAX1778 toc13 MAX1778 toc14 MAX1778 toc15 200mA 0.5A 200mA A 0 8.1V B 8.0V A A 0 0 8.1V 8.0V B 8.0V 7.9V 1A 1A 1A 0.5A C C C 0 0 40s/div A. IMAIN = 20mA to 200mA, 200mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 1A/div CINTG = 1000pF B 7.9V 7.9V 0 10 1.27 MAX1778 toc12 VNEG = -5V MAX1778 toc11 -2 MAX1778 toc10 100 REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT MAXIMUM NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE NEGATIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT EFFICIENCY (%) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer 40s/div A. IMAIN = 20mA to 200mA, 200mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 1A/div INTG = REF 4s/div A. IMAIN = 0 to 500mA, 500mA/div B. VMAIN = 8V, 100mV/div C. INDUCTOR CURRENT, 500mA/div ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer STEP-UP CONVERTER SOFT-START (LIGHT LOAD) RIPPLE VOLTAGE WAVEFORMS STEP-UP CONVERTER SOFT-START (HEAVY LOAD) MAX1778 toc17 MAX1778 toc16 MAX1778 toc18 2V A A 8V 0 -5V 8V B 6V 4V B 6V 4V 0.5A 20V A 0 8V B 2V 1.0A C C 0 C 0.5A 0 1ms/div A. VSHDN = O TO 2V, 2V/div B. VMAIN = 8V, 2V/div C. INDUCTOR CURRENT, 500mA/div RLOAD = 400 1s/div A. VMAIN = 8V, IMAIN = 200mA, 10mV/div B. VNEG = -5V, INEG = 10mA, 20mV/div C. VPOS = 20V, IPOS = 5mA, 20mV/div 1ms/div A. VSHDN = O TO 2V, 2V/div B. VMAIN = 8V, 2V/div C. INDUCTOR CURRENT, 500mA/div RLOAD = 20 POWER-UP SEQUENCE (CIRCUIT OF FIGURE 10) POWER-UP SEQUENCE MAX1778 toc19 MAX1778 toc20 4V MAX1778 toc21 A 2V 2V POWER-UP INTO SHORT-CIRCUIT (CIRCUIT OF FIGURE 10) A 4V 0 0 5V 20V B 0 10V C 5V 0 20V 10V B C 0 D 0 B 0 D -5V 0 A 2V 10V C 5V E -10V 0 2ms/div A. VSHDN = O TO 2V, 2V/div B. RDY, 5V/div C. POSITIVE CHARGE PUMP = VPOS = 20V, RLOAD = 4k, 10V/div D. STEP-UP CONVERTER: VMAIN = 8V, RLOAD = 40, 10V/div E. NEGATIVE CHARGE PUMP: VNEG = -5V, RLOAD = 500, 10V/div 1ms/div A. RDY, 2V/div B. POSITIVE CHARGE PUMP, VPOS(SYS) = 20V, 10V/div C. STEP-UP CONVERTER: VMAIN(SYS) = 8V, 10V/div D. NEGATIVE CHARGE PUMP, VNEG = -5V, -5V/div 100s/div A. RDY, 2V/div B. GATE OF N-CH MOSFET, 5V/div C. STEP-UP CONVERTER, VMAIN(START) = 8V, 5V/div VMAIN(SYS) = GND ______________________________________________________________________________________ 11 MAX1778/MAX1880-MAX1885 Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) LDO OUTPUT VOLTAGE vs. LDO OUTPUT CURRENT (INTERNAL LINEAR REGULATOR) 5.00 5.02 VLDOOUT (V) 4.95 ILDOOUT = 40mA 4.90 4.85 5.10 5.08 5.06 5.00 5.04 4.98 5.02 VLDO (V) ILDOOUT = 0 MAX1778 toc23 5.04 MAX1778 toc22 5.05 LDO OUTPUT VOLTAGE vs. TEMPERATURE (INTERNAL LINEAR REGULATOR) 4.96 MAX1778 toc24 LDO OUTPUT VOLTAGE vs. LDO INPUT VOLTAGE (INTERNAL LINEAR REGULATOR) ILDOOUT = 0 5.00 ILDOOUT = 40mA 4.98 4.96 4.94 4.94 4.80 4.92 4.75 4.90 4 6 8 10 4.92 4.90 0.01 12 VSUPL (V) 0.1 1 10 -15 VLDOOUT = 5V 4.0 VLDOOUT = 5V 3.5 ISUPL - ILDOOUT (mA) 160 35 60 LDO SUPPLY CURRENT vs. LDO OUTPUT CURRENT (INTERNAL LINEAR REGULATOR) MAX1778 toc25 200 10 TEMPERATURE (C) ILDOOUT (mA) DROPOUT VOLTAGE vs. LDO LOAD CURRENT (INTERNAL LINEAR REGULATOR) VSUPL - VLDOOUT (mV) -40 100 120 80 MAX1778 toc26 VLDOOUT (V) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer 3.0 2.5 2.0 1.5 1.0 40 0.5 0 0 0 10 20 ILDOOUT (mA) 12 30 40 0 10 20 30 ILDOOUT (mA) ______________________________________________________________________________________ 40 85 Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778 toc28 CLDOOUT = 1F 4OmA 10 CLDOOUT ESR () PSRR (dB) 80 MAX1778 toc29 100 MAX1778 toc27 100 LOAD-TRANSIENT RESPONSE (INTERNAL LINEAR REGULATOR) REGION OF STABLE CLDOOUT ESR vs. LOAD CURRENT POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 60 40 A 5.00V B 1 STABLE REGION 0.1 20 0 CLDOOUT = 4.7F ILDOOUT = 40mA 4.96V 0.01 0 0 20 ILDOOUT (mA) LOAD-TRANSIENT RESPONSE NEAR DROPOUT (INTERNAL LINEAR REGULATOR) INTERNAL LINEAR-REGULATOR RIPPLE REJECTION 10 100 1000 10 100s/div 40 FREQUENCY (kHz) 1 30 A. ILDO = 100A TO 40mA, 40mA/div B. VLDO = 5V, 20mV/div VSUPL = VLDO + 500mV INTERNAL LINEAR-REGULATOR STARTUP MAX1778 toc31 MAX1778 toc30 4OmA 5.0V MAX1778 toc32 A 0 A 0 A 2V B 8.0V 5.00V B 4V 2V B 1.0A C 0 0.5A C 0 4.94V 4V 2V 100s/div A. ILDO = 100A TO 40mA, 40mA/div B. VLDO = 5V, 20mV/div VIN = VLDO + 100mV 10s/div A. VLDOOUT = 5V, ILDOOUT = 40mA, 10mV/div B. VMAIN = VSUPL = 8V, 200mV/div C. IMAIN = 0 TO 750mA, 500mA/div 400s/div A. VSHDN = 0 TO 2V, 2V/div B. VLDOOUT = 5V, RLDOOUT = 125, 2V/div C. VMAIN = 8V, RMAIN = 40, 2V/div ______________________________________________________________________________________ 13 MAX1778/MAX1880-MAX1885 Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) 2.55 MAX1778 toc33 2.55 LINEAR-REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT (EXTERNAL LINEAR REGULATOR) 2.53 ILDO = 750mA 2.49 2.53 VLDO (V) ILDO = 0 2.51 FIGURE 7 EXTERNAL LINEAR-REGULATOR LOAD-TRANSIENT RESPONSE MAX1778 toc35 MAX1778 toc34 LINEAR-REGULATOR OUTPUT VOLTAGE vs. INPUT VOLTAGE (EXTERNAL LINEAR REGULATOR) VLDO (V) A 2.51 2.55V 2.50V B 2.45V 2.47 2.47 250mA 50mA 2.49 FIGURE 7 2.45 2.5 3.0 3.5 4.0 4.5 5.0 0.1 5.5 1 10 VIN (V) 100 EXTERNAL LINEAR-REGULATOR RIPPLE REJECTION A. ILDO = 50mA TO 250mA, 200mA/div B. VLDO = 2.5V, 50mV/div FIGURE 7 INPUT OFFSET VOLTAGE DEVIATION vs. COMMON-MODE VOLTAGE MAX1778 toc36 1.5 7.8V 1A 0.5A C 1.0 VSUPB = 4.5V VSUPB = 13V 0.5 VCM = VSUPB / 2 0.6 VOS (mV) B 8.0V INPUT OFFSET VOLTAGE DEVIATION vs. BUFFER SUPPLY VOLTAGE MAX1778 toc37 2.5 A 2.5V 100s/div 1000 ILDO (mA) -0.5 MAX1778 toc38 2.45 VOS (mV) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer 0.2 -0.2 -0.6 -1.5 0 -2.5 10s/div A. VLDO = 2.5V, ILDO = 200mA, 10mV/div B. VMAIN = VSUPL = 8V, 200mV/div C. IMAIN = 0 TO 750mA, 500mA/div FIGURE 7 14 -1.0 0 2 4 6 8 VCM (V) 10 12 14 4 6 8 10 VSUPB (V) ______________________________________________________________________________________ 12 14 Quad-Output TFT LCD DC-DC Converters with Buffer (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) VSUPB = 13V VCM = VSUPB / 2 0.6 -0.2 -0.6 0 0.2 VSUPB = 13V 8 4 -0.6 2 10 35 60 85 0 -40 -15 TEMPERATURE (C) 10 35 60 85 0 2 4 TEMPERATURE (C) BUFFER INPUT BIAS CURRENT vs. BUFFER SUPPLY VOLTAGE BUFFER INPUT BIAS CURRENT vs. TEMPERATURE VCM = VSUPB / 2 11 12 14 VSUPB = 13V 0.46 ISUPB (mA) IBIAS (nA) IBIAS (nA) 9 8 7 6 10 0.50 10 8 8 BUFFER SUPPLY CURRENT vs. COMMON-MODE VOLTAGE 12 MAX1778 toc42 10 6 VCM (V) MAX1778 toc43 -15 VSUPB = 4.5V -0.2 0 -40 6 6 MAX1778 toc44 0.2 10 IBIAS (nA) VOS (mV) 0.6 BUFFER INPUT BIAS CURRENT vs. COMMON-MODE VOLTAGE MAX1778 toc39 VSUPB = 13V VCM = VSUPB / 2 VOS (mV) 1.0 MAX1778 toc39 1.0 INPUT OFFSET VOLTAGE DEVIATION vs. TEMPERATURE MAX1778 toc41 INPUT OFFSET VOLTAGE DEVIATION vs. TEMPERATURE 0.42 VSUPB = 4.5V 0.38 0.34 5 VCM = VSUPB / 2 4 4 6 8 10 12 14 0.30 -40 -15 10 35 60 2 4 6 8 10 12 VSUPB (V) TEMPERATURE (C) VCM (V) BUFFER SUPPLY CURRENT vs. BUFFER SUPPLY VOLTAGE NO-LOAD BUFFER SUPPLY CURRENT vs. TEMPERATURE VCOM BUFFER SMALL-SIGNAL RESPONSE 0.46 VSUPB = 13V VCM = VSUPB / 2 0.9 0.8 ISUPB (mA) 0.38 0.5 0.4 4.05V 3.95V 0.1 0.30 B 4.00V 0.2 VCM = VSUPB / 2 A 3.95V 0.6 0.3 0.34 4.05V 4.00V 0.7 0.42 14 MAX1778 toc47 1.0 MAX1778 toc45 0.50 ISUPB (mA) 0 85 MAX1778 toc46 4 0 4 6 8 10 VSUPB (V) 12 14 -40 -15 10 35 TEMPERATURE (C) 60 85 4s/div A. VBUF+ = 3.95V TO 4.05V, 50mV/div B. BUFOUT = BUF-, 50mV/div CBUF = 1F, VSUPB = 8V ______________________________________________________________________________________ 15 MAX1778/MAX1880-MAX1885 Typical Operating Characteristics (continued) MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer Typical Operating Characteristics (continued) (Circuit of Figure 1, V IN = +3.3V, SHDN = IN, V MAIN = V SUPP = V SUPN = V SUPB = V SUPL = 8V, BUF- = BUFOUT, BUF+ = FLTSET = TGND = PGND = GND, TA = +25C.) VCOM BUFFER LARGE-SIGNAL RESPONSE VCOM BUFFER LOAD-TRANSIENT RESPONSE MAX1778 toc48 VCOM BUFFER LOAD-TRANSIENT RESPONSE MAX1778 toc49 4.50V MAX1778 toc50 200mA 0 A 4.00V 3.50V 4.50V 500mA A -200mA -500mA 4.2V 4.5V 4.0V B 4.00V B 3.8V 4.0V B 3.5V 8.0V 3.50V A 0 C 10s/div 8.0V C 4s/div A. VBUF+ = 3.50V TO 4.50V, 0.5V/div B. BUFOUT = BUF-, 0.5V/div CBUF = 1F, VSUPB = 8V 4s/div A. IBUFOUT = 200mA PULSES, 200mA/div B. BUFOUT = BUF-, 200mV/div C. VMAIN = 8V, 50mV/div VSUPB = VMAIN, BUF+ = GND, CBUF = 1F A. IBUFOUT = 400mA PULSES, 500mA/div B. BUFOUT = BUF-, 0.5V/div C. VMAIN = 8V, 100mV/div VSUPB = VMAIN, BUF+ = GND, CBUF = 1F VCOM BUFFER STARTUP VCOM BUFFER STARTUP MAX1778 toc51 4V 2V MAX1778 toc51 4V A 0 2V A 0 4V 4V B 2V 0 B 2V 0 8.1V C 7.8V 8.1V C 7.8V 100s/div A. RDY, 2V/div B. BUFOUT = BUF-, CBUF = 1F, 2V/div C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div BUF+ = GND 16 100s/div A. RDY, 2V/div B. BUFOUT = BUF-, CBUF = 1F, 2V/div C. VSUPB = VMAIN = 8V, IMAIN = 20mA, 200mV/div BUF+ = GND ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer PIN MAX1778 MAX1881 MAX1880 MAX1882 MAX1883 MAX1884 MAX1885 NAME 1 1 1 1 FB 2 2 2 2 INTG 3 3 3 3 FUNCTION Main Step-Up Regulator Feedback Input. Regulates to 1.25V nominal. Connect a resistive divider from the output (VMAIN) to FB to analog ground (GND). Main Step-Up Integrator Output. When using the integrator, connect 1000pF to analog ground (GND). To disable the integrator, connect INTG to REF. IN Main Supply Voltage. The supply voltage powers the control circuitry for all of the regulators and may range from 2.7V to 5.5V. Bypass with a 0.1F capacitor between IN and GND, as close to the pins as possible. 4 4 4 4 BUF+ VCOM Buffer (Operational Transconductance Amplifier) Positive Feedback Input. Connect to GND to select the internal resistive divider that sets the positive input to half the amplifier's supply voltage (VBUF+ = V SUPB /2). 5 5 5 5 BUF- VCOM Buffer (Operational Transconductance Amplifier) Negative Feedback Input 6 6 6 6 SUPB VCOM Buffer (Operational Transconductance Amplifier) Supply Voltage 7 7 7 7 BUFOUT VCOM Buffer (Operational Transconductance Amplifier) Output 8 8 8 8 GND Analog Ground. Connect to power ground (PGND) underneath the IC. 9 9 9 9 REF Internal Reference Bypass Terminal. Connect a 0.22F ceramic capacitor from REF to analog ground (GND). External load capability up to 50A. 10 10 - - FBP Positive Charge-Pump Regulator Feedback Input. Regulates to 1.25V nominal. Connect a resistive divider from the positive charge-pump output (VPOS) to FBP to analog ground (GND). 11 11 - - FBN Negative Charge-Pump Regulator Feedback Input. Regulates to 0V nominal. Connect a resistive divider from the negative chargepump output (VNEG) to FBN to the reference (REF). 12 12 10 10 SHDN Active-Low Shutdown Control Input. Pull SHDN low to force the controller into shutdown. If unused, connect SHDN to IN for normal operation. A rising edge on SHDN clears the fault latch. SUPL Low-Dropout Linear Regulator Input Voltage. Can range from 4.5V to 15V. Bypass with a 1F capacitor to GND (see Capacitor Selection and Regulator Stability). Connect both input pins together externally. 13 - 11 - ______________________________________________________________________________________ 17 MAX1778/MAX1880-MAX1885 Pin Description MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer Pin Description (continued) PIN MAX1778 MAX1881 MAX1880 MAX1882 MAX1883 MAX1884 MAX1885 NAME FUNCTION Linear Regulator Output. Sources up to 40mA. Bypass to GND with a ceramic capacitor determined by: 18 14 - 12 - LDOOUT 15 - 13 - FBL Voltage Setting Input. Connect a resistive divider from the linear regulator output (VLDOOUT) to FBL to analog ground (GND). ILDOOUT(MAX) CLDOOUT 0.5ms X VLDOOUT 16 16 14 14 FLTSET Fault Trip-Level Set Input. Connect to a resistive divider between REF and GND to set the main step-up converter's and positive charge pump's fault thresholds between 0.67 x VREF and 0.85 x VREF. Connect to GND for the preset fault threshold (0.9 x VREF). 17 17 - - SUPN Negative Charge-Pump Driver Supply Voltage. Bypass to power ground (PGND) with a 0.1F capacitor. 18 18 - - DRVN Negative Charge-Pump Driver Output. Output high level is VSUPN and low level is PGND. 19 19 - - SUPP Positive Charge-Pump Driver Supply Voltage. Bypass to power ground (PGND) with a 0.1F capacitor. 20 20 - - DRVP Positive Charge-Pump Driver Output. Output high level is VSUPP and low level is PGND 21 21 17 17 PGND Power Ground. Connect to analog ground (GND) underneath the IC. 22 22 18 18 LX Main Step-Up Regulator Power MOSFET N-Channel Drain. Place output diode and output capacitor as close to PGND as possible. 23 23 19 19 TGND 24 24 20 20 RDY Active-Low, Open-Drain Output. Indicates all outputs are ready. On-resistance is 125 (typ). - 13, 14, 15 15, 16 11, 12, 13, 15, 16 N.C. No Connection. Not internally connected. Must be connected to ground. ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885 L1 6.8H INPUT VIN = 3.3V CIN 4.7F RRDY 100k C1 0.22F MAIN (8V) R8 49.9k LX SHDN FB RDY SUPL LDOOUT TO LOGIC LDO VLDOOUT = 5V CLDO 4.7F IN R7 150k SUPB SUPN SUPP MAX1778 MAIN VMAIN = 8V COUT (2) 4.7F R2 274k R2 49.9k C4 0.1F C5 1.0F DRVP C2 0.1F FBL C4 0.1F C7 1.0F DRVN POSITIVE VPOS = 20V R3 750k NEGATIVE VNEG = -5V FBN C3 1.0F FBP R5 200k R6 49.9k CREF 0.22F R4 49.9k REF INTG FLTSET PGND BUFOUT BUFBUF+ GND CBUF 1.0F BUFFER OUTPUT VBUFOUT = VSUPB/2 TGND Figure 1. Typical Application Circuit Detailed Description The MAX1778/MAX1880-MAX1885 are highly efficient multiple-output power supplies for thin-film transistor (TFT) liquid crystal display (LCD) applications. The devices contain one high-power step-up converter, two low-power charge pumps, an operational transconductance amplifier (VCOM buffer), and a low-dropout linear regulator. The primary step-up converter uses an internal N-channel MOSFET to provide maximum efficiency and to minimize the number of external components. The output voltage of the main step-up converter (VMAIN) can be set from VIN to 13V with external resistors. The dual charge pumps (MAX1778/MAX1880/ MAX1881/MAX1882 only) independently regulate a positive output (VPOS) and a negative output (VNEG). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages from -40V to +40V. A unique control scheme minimizes output ripple as well as capacitor sizes for both charge pumps. A resistor-programmable 40mA linear regulator (MAX1778/MAX1881/MAX1883/MAX1884 only) can provide preregulation or postregulation for any of the supplies. For higher current applications, an external transistor can be added. Additionally, the VCOM buffer provides a high current output that is ideal for driving capacitive loads, such as the backplane of a TFT LCD panel. The positive feedback input features dual mode operation, allowing this input to be connected to an internal 50% resistivedivider between the buffer's supply voltage and ground, or externally adjusted for other voltages. Also included in the MAX1778/MAX1880-MAX1885 is a precision 1.25V reference that sources up to 50A, logic shutdown, soft-start, power-up sequencing, adjustable fault detection, thermal shutdown, and an active-low, open-drain ready output. ______________________________________________________________________________________ 19 MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer in the feedback voltage-error signal shift the switch-current trip level, consequently modulating the MOSFET duty cycle. Under very light loads, an inherent switchover to pulseskipping takes place (Figure 3). When this occurs, the controller skips most of the oscillator pulses in order to reduce the switching frequency and gate charge losses. When pulse-skipping, the step-up controller initiates a new switching cycle only when the output voltage drops too low. The N-channel MOSFET turns on, allowing the inductor current to ramp up until the multi-input comparator trips. Then, the MOSFET turns off and the diode turns on, forcing the inductor current to ramp down. When the inductor current reaches zero, the diode turns off, so the inductor stops conducting current. This forces the threshold between pulse-skipping and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation: Main Step-up Controller During normal pulse-width modulation (PWM) operation, the MAX1778/MAX1880-MAX1885 main step-up controllers switch at a constant frequency of 500kHz or 1MHz (see Selector Guide), allowing the use of lowprofile inductors and output capacitors. Depending on the input-to-output voltage ratio, the controller regulates the output voltage and controls the power transfer by modulating the duty cycle (D) of each switching cycle: D VMAIN - VIN VMAIN On the rising edge of the internal clock, the controller sets a flip-flop when the output voltage is too low, which turns on the N-channel MOSFET (Figure 2). The inductor current ramps up linearly, storing energy in a magnetic field. Once the sum of the feedback voltage error amplifier, slope-compensation, and current-feedback signals trip the multi-input comparator, the MOSFET turns off, the flip-flop resets, and the diode (D1) turns on. This forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and load. The MOSFET remains off for the rest of the clock cycle. Changes ILOAD(CROSSOVER) 1 VIN 2 VMAIN L1 VIN (2.7V TO 5.5V) OSC (80% DUTY) MAX1778 MAX1880 MAX1881 MAX1882 MAX1883 MAX1884 MAX1885 2 CIN LX D1 VMAIN (UP TO 13V) S COUT R Q ILIM PWM COMPARATOR R1 PGND ILIM COMPARATOR RCOMP (OPTIONAL) FB CCOMP (OPTIONAL) gm ERROR AMPLIFIER REF VREF 1.25V INTG R2 CREF GND ( )V VMAIN = 1 + R1 R2 VREF = 1.25V REF CINTG Figure 2. Main Step-Up Converter Block Diagram 20 ______________________________________________________________________________________ VMAIN - VIN fOSCL Quad-Output TFT LCD DC-DC Converters with Buffer The MAX1778/MAX1880/MAX1881/MAX1882 controllers contain two independent low-power charge pumps (Figure 4). One charge pump inverts the input voltage and provides a regulated negative output voltage. The second charge pump doubles the input voltage and provides a regulated positive output voltage. The controllers contain internal P-channel and N-channel MOSFETs to control the power transfer. The internal MOSFETs switch at a constant frequency (fCHP = fOSC/2). INDUCTOR CURRENT IPEAK Positive Charge Pump During the first half-cycle, the N-channel MOSFET turns on and charges flying capacitor CX(POS) (Figure 4). This initial charge is controlled by the variable N-channel on-resistance. During the second half-cycle, the Nchannel MOSFET turns off and the P-channel MOSFET turns on, level shifting CX(POS) by VSUPP volts. This connects CX(POS) in parallel with the reservoir capacitor COUT(POS). If the voltage across COUT(POS) plus a diode drop (VPOS + VDIODE) is smaller than the levelshifted flying capacitor voltage (VCX(POS) + VSUPP), charge flows from CX(POS) to COUT(POS) until the diode (D3) turns off. ILOAD TIME tON tOFF Figure 3. Discontinuous-to-Continuous Conduction Crossover Point MAX1778 MAX1880 MAX1881 MAX1882 SUPP VSUPP 2.7V TO 13V SUPN VSUPN 2.7V TO 13V OSC D2 VSUPD CX(POS) DRVP DRVN D3 CX(NEG) D4 D5 R3 R5 FBN FBP VPOS VNEG COUT(POS) COUT(NEG) R4 R6 VREF 1.25V REF ( )V VPOS = 1 + R3 R4 VREF = 1.25V REF GND PGND CREF 0.22F ( ) VNEG = - R5 VREF R6 VREF = 1.25V Figure 4. Low-Power Charge Pump Block Diagram ______________________________________________________________________________________ 21 MAX1778/MAX1880-MAX1885 Dual Charge-Pump Regulator (MAX1778/ MAX1880/MAX1881/MAX1882 Only) The switching waveforms will appear noisy and asynchronous when light loading causes pulse-skipping operation; this is a normal operating condition that improves light-load efficiency. MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer Negative Charge Pump During the first half-cycle, the P-channel MOSFET turns on, and flying capacitor C X(NEG) charges to V SUPN minus a diode drop (Figure 4). During the second halfcycle, the P-channel MOSFET turns off, and the Nchannel MOSFET turns on, level shifting CX(NEG). This connects CX(NEG) in parallel with reservoir capacitor COUT(NEG). If the voltage across COUT(NEG) minus a diode drop is greater than the voltage across CX(NEG), charge flows from COUT(NEG) to CX(NEG) until the diode (D5) turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance. Low-Dropout Linear Regulator (MAX1778/ MAX1881/MAX1883/MAX1884 Only) The MAX1778/MAX1881/MAX1883/MAX1884 contain a low-dropout linear regulator (Figure 5) that uses an internal PNP pass transistor (QP) to supply loads up to 40mA. As illustrated in Figure 5, the 1.25V reference is connected to the error amplifier, which compares this reference with the feedback voltage and amplifies the difference. If the feedback voltage is higher than the reference voltage, the controller lowers the base current of QP, which reduces the amount of current to the output. If the feedback voltage is too low, the device increases the pass transistor base current, which allows more current to pass to the output and increases the output voltage. However, the linear regulator also includes an output current limit to protect the internal pass transistor against short circuits. The low-dropout linear regulator monitors and controls the pass transistor's base current, limiting the output current to 130mA (typ). In conjunction with the thermal overload protection, this current limit protects the output, allowing it to be shorted to ground for an indefinite period of time without damaging the part. VCOM Buffer The MAX1778/MAX1880-MAX1885 include a VCOM buffer, which uses an operational transconductance amplifier (OTA) to provide a current output that is ideal for driving capacitive loads, such as the backplane of a TFT LCD panel. The unity-gain bandwidth of this current-output buffer is: GBW = gm/COUT where gm is the amplifier's transconductance. The bandwidth is inversely proportional to the output capacitor, so large capacitive loads improve stability; however, lower bandwidth decreases the buffer's transient response time. To improve the transient response MAX1778 MAX1881 MAX1883 MAX1884 SUPL CSUPL VSUPL 4.5V TO 15V THERMAL SENSOR CURRENT LIMIT QP VLDOOUT 1.25V TO (VSUPL - 0.3V) LDOOUT CLDOOUT R7 FBL ERROR AMPLIFIER R8 VREF 1.25V ( VLDOOUT = 1 + GND ) R7 VREF R8 VREF = 1.25V Figure 5. Low-Dropout Linear Regulator Block Diagram 22 ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer VSUPB 4.5V TO 13V VBUFOUT 1.2V TO (VSUPB - 1.2V) CBUF BUFOUT gm BUF- R R11 BUF+ R R12 125mV GND VBUFOUT = ( R11R12+ R12 )V SUPB Figure 6. VCOM Buffer Block Diagram times, the amplifier's transconductance increases as the output current increases (see Typical Operating Characteristics). The VCOM buffer's positive feedback input features dual mode operation. The buffer's output voltage can be internally set by a 50% resistive divider connected to the buffer's supply voltage (SUPB), or the output voltage can be externally adjusted for other voltages. Shutdown (SHDN) A logic-low level on SHDN shuts down all of the converters and the reference. When shut down, the supply current drops to 0.1A to maximize battery life, and the reference is pulled to ground. The output capacitance, feedback resistors, and load current determine the rate at which each output voltage will decay. A logic-level high on SHDN power activates the MAX1778/ MAX1880-MAX1885 (see Power-Up Sequencing). Do not leave SHDN floating. If unused, connect SHDN to IN. A logic-level transition on SHDN clears the fault latch. Power-Up Sequencing Upon power-up or exiting shutdown, the MAX1778/ MAX1880-MAX1885 start a power-up sequence. First, the reference powers up. Then, the main DC-DC stepup converter powers up with soft-start enabled. The linear regulator powers up at the same time as the main step-up converter; however, the power sequence and ready output signal are not affected by the regulation of the linear regulator. While the main step-up converter powers up, the output of the PWM comparator remains low (Figure 2), and the step-up converter charges the output capacitors, limited only by the maximum duty cycle and current-limit comparator. When the step-up converter approaches its nominal regulation value and the PWM comparator's output changes states for the first time, the negative charge pump turns on. When the negative output voltage reaches approximately 90% of its nominal value (VFBN < 110mV), the positive charge pump starts up. Finally, when the positive output voltage reaches 90% of its nominal value (VFBP > 1.125V), the active-low ready signal (RDY) goes low (see Power Ready), and the VCOM buffer powers up. The MAX1883/MAX1884/MAX1885 do not contain the charge pumps, but the power-up sequence still contains the charge pumps' startup logic, which appears as a delay (2 4096/fOSC) between the step-up converter reaching regulation and when the ready signal and VCOM buffer are activated. Soft-Start For the main step-up regulator, soft-start allows a gradual increase of the current-limit level during startup to reduce input surge currents. The MAX1778/MAX1880- MAX1885 divide the soft-start period into four phases. During the first phase, the controller limits the current limit to only 0.38A (see Electrical Characteristics), approximately a quarter of the maximum current limit ______________________________________________________________________________________ 23 MAX1778/MAX1880-MAX1885 SUPB MAX1778 MAX1880 MAX1881 MAX1882 MAX1883 MAX1884 MAX1885 MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer (ILX(MAX)). If the output does not reach regulation within 1ms, soft-start enters phase II, and the current limit is increased by another 25%. This process is repeated for phase III. The maximum 1.5A (typ) current limit is reached within 3072 clock cycles or when the output reaches regulation, whichever occurs first (see the startup waveforms in the Typical Operating Characteristics). For the charge pumps (MAX1778/MAX1880/ MAX1881/MAX1882 only), soft-start is achieved by controlling the rate of rise of the output voltage. Both charge-pump output voltages are controlled to be in regulation within 4096 clock cycles, irregardless of output capacitance and load, limited only by the charge pump's output impedance. Although the MAX1883/ MAX1884/MAX1885 controllers do not include the charge pumps, the soft-start logic still contains the 4096 clock cycle startup periods for both charge pumps. Fault Trip Level (FLTSET) The MAX1778/MAX1880-MAX1885 feature dual mode operation to allow operation with either a preset fault trip level or an adjustable trip level for the step-up converter and positive charge-pump outputs. Connect FLTSET to GND to select the preset 0.9 V REF fault threshold. The fault trip level may also be adjusted by connecting a voltage divider from REF to FLTSET (Figure 8). For greatest accuracy, the total load on the reference (including current through the negative charge-pump feedback resistors) should not exceed 50A so that VREF is guaranteed to be in regulation (see Electrical Characteristics Table). Therefore, select R10 in the 100k to 1M range, and calculate R9 with the following equation: R9 = R10 [(VREF / VFLTSET) - 1] where VREF = 1.25V, and VFLTSET may range from 0.67 x VREF to 0.85 x VREF. FLTSET's input bias current has a maximum value of 50nA. For 1% error, the current through R10 should be at least 100 times the FLTSET input bias current (IFLTSET). Fault Condition Once RDY is low, if the output of the main regulator or either low-power charge pump falls below its fault detection threshold, or if the input drops below its undervoltage threshold, then RDY goes high impedance and all outputs shut down; however, the reference remains active. After removing the fault condition, toggle shutdown (below 0.8V) or cycle the input voltage (below 0.2V) to clear the fault latch and reactivate the device. 24 The reference fault threshold is 1.05V. For the step-up converter and positive charge-pump, the fault trip level is set by FLTSET (see Fault Trip Level). For the negative charge pump, the fault threshold measured at the charge-pump's feedback input (FBN) is 140mV (typ). Power Ready (RDY) Power ready is an open-drain output. When the powerup sequence for the main step-up converter and lowpower charge pumps has properly completed, the 14V MOSFET turns on and pulls RDY low with a 125 (typ) on-resistance. If a fault is detected on any of these three outputs, the internal open-drain MOSFET appears as a high impedance. Connect a 100k pullup resistor between RDY and IN for a logic-level output. Voltage Reference (REF) The voltage at REF is nominally 1.25V. The reference can source up to 50A with good load regulation (see Typical Operating Characteristics). Connect a 0.22F ceramic bypass capacitor between REF and GND. Thermal-Overload Protection Thermal-overload protection limits total power dissipation in the MAX1778/MAX1880-MAX1885. When the junction temperature exceeds TJ = +160C, a thermal sensor activates the fault protection, which shuts down the controller, allowing the IC to cool. Once the device cools down by 15C, toggle shutdown (below 0.8V) or cycle the input voltage (below 0.2V) to clear the fault latch and reactivate the controller. Thermal-overload protection protects the controller in the event of fault conditions. For continuous operation, do not exceed the absolute maximum junction-temperature rating of TJ = +150C. Operating Region and Power Dissipation The MAX1778/MAX1880-MAX1885s' maximum power dissipation depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of any airflow. The power dissipated in the device depends on the operating conditions of each regulator and the buffer. The step-up controller dissipates power across the internal N-channel MOSFET as the controller ramps up the inductor current. In continuous conduction, the power dissipated internally can be approximated by: 2 2 I V 1 VIND PSTEP - UP MAIN MAIN + VIN 12 fOSCL x RDS(ON)D ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer Main Step-Up Converter When driving an external transistor, the internal linear regulator provides the base drive current. Depending on the external transistor's current gain () and the maximum load current, the power dissipated by the internal linear regulator may still be significant: ] I PLDO(INT) = LDO VSUPL - (VLDO + 0.7V ) = ILDOOUT (VSUPL - VLDOOUT ) [ IPOS [(VSUPP - 2VDIODE )N + PPOS = ] VSUPD - VPOS Output Voltage Selection Adjust the output voltage by connecting a voltagedivider from the output (VMAIN) to FB to GND (see Typical Operating Circuit). Select R2 in the 10k to 50k range. Calculate R1 with the following equations: R1 = R2 [(VMAIN / VREF) - 1] where VREF = 1.25V. VMAIN may range from VIN to 13V. The charge pumps provide regulated output voltages by dissipating power in the low-side N-channel MOSFET, so they could be modeled as linear regulators followed by unregulated charge pumps. Therefore, their power dissipation is similar to a linear regulator: PNEG = INEG (VSUPN - 2VDIODE )N - VNEG where TJ - TA is the temperature difference between the controller's junction and the surrounding air, JB (or JC) is the thermal resistance of the package to the board, and BA is the thermal resistance from the printed circuit board to the surrounding air. Design Procedure PLDO(INT) = ILDO (VSUPL - VLDO ) [ PMAX = (TJ(MAX) - TA) / ( JB + BA) ] where N is the number of charge-pump stages, VDIODE is the diodes' forward voltage, and VSUPD is the positive charge-pump diode supply (Figure 4). The VCOM buffer's power dissipation depends on the capacitive load (C LOAD) being driven, the peak-topeak voltage change (VP-P) across the load, and the load's switching rate: PBUF = VP - PCLOADfLOADVSUPB To find the total power dissipated in the device, the power dissipated by each regulator and the buffer must be added together: PTOTAL = PSTEP - UP + PLDO(INT) + PNEG + PPOS + PBUF The maximum allowed power dissipation is 975mW (24pin TSSOP) / 879mW (20-pin TSSOP) or: Inductor Selection Inductor selection depends upon the minimum required inductance value, saturation rating, series resistance, and size. These factors influence the converter's efficiency, maximum output load capability, transient response time, and output voltage ripple. For most applications, values between 4.7H and 22H work best with the controller's switching frequency (Tables 1 and 2). The inductor value depends on the maximum output load the application must support, input voltage, output voltage, and switching frequency. With high inductor values, the MAX1778/MAX1880-MAX1885 source higher output currents, have less output ripple, and enter continuous conduction operation with lighter loads; however, the circuit's transient response time is slower. On the other hand, low-value inductors respond faster to transients, remain in discontinuous conduction operation, and typically offer smaller physical size for a given series resistance and current rating. The equations provided here include a constant LIR, which is the ratio of the peak-to-peak AC inductor current to the average DC inductor current. For a good compromise between the size of the inductor, power loss, and output voltage ripple, select an LIR of 0.3 to 0.5. The inductance value is then given by: 2 VIN(MIN) VMAIN - VIN(MIN) 1 LMIN = VMAIN IMAIN(MAX)fOSC LIR ______________________________________________________________________________________ 25 MAX1778/MAX1880-MAX1885 where IMAIN includes the primary load current and the input supply currents for the charge pumps (see Charge-Pump Input Power and Efficiency Considerations), linear regulator, and VCOM buffer. The linear regulator generates an output voltage by dissipating power across an internal pass transistor, so the power dissipation is simply the load current times the input-to-output voltage differential: MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer where is the efficiency, fOSC is the oscillator frequency (see Electrical Characteristics), and IMAIN includes the primary load current and the input supply currents for the charge pumps (see Charge-Pump Input Power and Efficiency Considerations), linear regulator, and VCOM buffer. Considering the typical application circuit, the maximum average DC load current (IMAIN(MAX)) is 300mA with an 8V output. Based on the above equations and assuming 85% efficiency, the inductance value is then chosen to be 4.7H. The inductor's saturation current rating should exceed the peak inductor current throughout the normal operating range. The peak inductor current is then given by: Output voltage ripple has two components: variations in the charge stored in the output capacitor with each LX pulse, and the voltage drop across the capacitor's equivalent series resistance (ESR) caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) VRIPPLE(ESR) IPEAKRESR(COUT) , AND V - VIN IMAIN VRIPPLE(C) MAIN C VMAIN OUT fOSC IMAIN(MAX) VMAIN LIR 1 IPEAK = 1 + VIN(MIN) 2 where IPEAK is the peak inductor current (see Inductor Selection). For ceramic capacitors, the output voltage ripple is typically dominated by VRIPPLE(C). The voltage rating and temperature characteristics of the output capacitor must also be considered. Under fault conditions, the inductor current may reach up to 1.85A (ILIM(MAX)), see Electrical Characteristics). However, the controller's fast current-limit circuitry allows the use of soft-saturation inductors while still protecting the IC. Feedback Compensation For stability, add a pole-zero pair from FB to GND in the form of a compensation resistor (RCOMP) in series with a compensation capacitor (CCOMP) as shown in Figure 2. Select RCOMP to be half the value of R2, the low-side feedback resistor. The inductor's DC resistance may significantly affect efficiency due to the power loss in the inductor. The power loss due to the inductor's series resistance (PLR) may be approximated by the following equation: I X VMAIN PLR RL MAIN VIN 2 where RL is the inductor's series resistance. For best performance, select inductors with resistance less than the internal N-channel MOSFET on-resistance (0.35 typ). Use inductors with a ferrite core or equivalent. To minimize radiated noise in sensitive applications, use a shielded inductor. Output Capacitor Output capacitor selection depends on circuit stability and output voltage ripple. A 10F ceramic capacitor works well in most applications (Tables 1 and 2). Additional feedback compensation is required (see Feedback Compensation) to increase the margin for stability by reducing the bandwidth further. In cases where the output capacitance is sufficiently large, additional feedback compensation will not be necessary. 26 Integrator Capacitor The MAX1778/MAX1880-MAX1885 contain an internal current integrator that improves the DC load regulation but increases the peak-to-peak transient voltage (see the load-transient waveforms in the Typical Operating Characteristics). For highly accurate DC load regulation, enable the current integrator by connecting a 470pF ( OSC = 1MHz)/1000pF ( OSC = 500kHz) capacitor to INTG. To minimize the peak-to-peak transient voltage at the expense of DC regulation, disable the integrator by connecting INTG to REF. When using the MAX1883/MAX1884/MAX1885, connect a 100k resistor to GND when disabling the integrator. Input Capacitor The input capacitor (CIN) in step-up designs reduces the current peaks drawn from the input supply and reduces noise injection. The value of C IN is largely determined by the source impedance of the input supply. High source impedance requires high input capacitance, particularly as the input voltage falls. Since step-up DC-DC converters act as "constant-power" loads to their input supply, input current rises as input voltage falls. A good starting point is to use the same capacitance value for CIN as for COUT. ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer charge pump's output impedance may be approximated using the following equation: 1 RTX = 2(RPCH(ON) + RNCH(ON) ) + CX fCHP 1 + COUT fCHP Charge Pumps (MAX1778/ MAX1880/ MAX1881/MAX1882 Only) Selecting the Number of Charge-Pump Stages The number of charge-pump stages required to regulate the output voltage depends on the supply voltage, output voltage, load current, switching frequency, the diode's forward voltage drop, and ceramic capacitor values. For positive charge-pump outputs, the number of required stages may be determined by: VPOS - VSUPD NPOS VSUPP - 1.1(2VDIODE + RTXILOAD ) where VSUPD is the positive charge-pump diode supply (Figure 4), VDIODE is the diode's forward voltage drop, and RTX is the charge pump's output impedance. The where the charge pump's switching frequency (fCHP) is equal to 0.5 x fOSC, the P-channel MOSFET's on-resistance (RPCH(ON)) is 10, and the N-channel MOSFET's on-resistance (R NCH(ON )) is 4 (see Electrical Characteristics). For negative charge pump outputs, the number of required stages may be determined by: VNEG NNEG VSUPN - 1.1(2VDROP + RTXILOAD ) where NNEG is rounded up to the nearest integer. Table 1. MAX1778/MAX1880/MAX1883 Component Values (fOSC = 1MHz) CIRCUIT 1 CIRCUIT 2 CIRCUIT 3 CIRCUIT 4 VIN 3.3V 3.3V 3.3V 5V CIRCUIT 5 5V VMAIN 9V 9V 9V 12V 12V IMAIN(MAX) 100mA 200mA 200mA 220mA 220mA VNEG -5V -5V -5V -5V -5V 5mA INEG 2mA 5mA 5mA 5mA VPOS 24V 24V 24V 24V 24V IPOS 2mA 5mA 5mA 5mA 5mA 6.8H L 2.2H 4.7H 4.7H 6.8H IPEAK >1A >1A >1A >1A >1A COUT 4.7F 10F 20F 10F 20F R1 309k 309k 309k 429k 429k R2 49.9k 49.9k 49.9k 49.9k 49.9k RCOMP None None 39k* None 20k* CCOMP None None 100pF* None 200pF* *RCOMP and CCOMP are connected between the step-up converter's output (VMAIN) and FB. ______________________________________________________________________________________ 27 MAX1778/MAX1880-MAX1885 Rectifier Diode Use a Schottky diode with an average current rating equal to or greater than the peak inductor current, and a voltage rating at least 1.5 times the main output voltage (VMAIN). MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer Table 2. MAX1881/MAX1882/MAX1884/MAX1885 Component Values (fOSC = 500kHz) CIRCUIT 6 CIRCUIT 7 CIRCUIT 8 CIRCUIT 9 VIN 3.3V 3.3V 3.3V 3.3V VMAIN 9V 9V 9V 9V IMAIN(MAX) 100mA 100mA 200mA 200mA VNEG -5V -5V -5V -5V INEG 2mA 2mA 5mA 5mA VPOS 24V 24V 24V 24V IPOS 2mA 2mA 5mA 5mA L 4.7H 10H 10H 10H IPEAK >1A >1A >1A >1A COUT 4.7F 10F 10F 20F R1 309k 309k 309k 309k R2 49.9k 49.9k 49.9k 49.9k RCOMP None None None 20k* CCOMP None None None 200pF* *RCOMP and CCOMP are connected between the step-up converter's output (VMAIN) and FB. Table 3. Component Suppliers SUPPLIER PHONE FAX INDUCTORS Coilcraft 847-639-6400 847-639-1469 Coiltronics 561-241-7876 561-241-9339 Sumida USA 847-956-0666 847-956-0702 Toko 847-297-0070 847-699-1194 CAPACITORS AVX 803-946-0690 803-626-3123 Kemet 408-986-0424 408-986-1442 Sanyo 619-661-6835 619-661-1055 Taiyo Yuden 408-573-4150 408-573-4159 Central Semiconductor 516-435-1110 516-435-1824 International Rectifier 310-322-3331 310-322-3332 Motorola 602-303-5454 602-994-6430 Nihon 847-843-7500 847-843-2798 Zetex 516-543-7100 516-864-7630 Charge-Pump Input Power and Efficiency Considerations The charge pumps in the MAX1778/MAX1880/ MAX1881/MAX1882 provide regulated output voltages by controlling the voltage drop across the low-side Nchannel MOSFET, so they can be modeled as linear regulators followed by an unregulated charge pump when determining the input power requirements and efficiency. The charge pump only provides charge to the output capacitor during half the period (50% duty cycle), so the input current is a function of the number of stages and the load current: ISUPP = IPOS (N + 1) DIODES 28 for the positive charge pump, and: ISUPP = IPOS (N + 1) for the negative charge pump, where N is the number of charge pump stages. The efficiency characteristics of the MAX1778/ MAX1880/MAX1881/MAX1882 regulated charge pumps are similar to a linear regulator. It is dominated by quiescent current at low output currents and by the ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer POS for the negative charge pump, where N is the stage number in which the flying capacitor appears, and V SUPD is the positive charge pump's diode supply (Figure 4). For example, the two-stage positive charge pump in the typical application circuit (Figure 1) where VSUPP = VSUPD = 8V contains two flying capacitors. The flying capacitor in the first stage (C4) requires a voltage rating over 12V. The flying capacitor in the second stage (C6) requires a voltage rating over 24V. VPOS VSUPD + VSUPPN for the positive charge pump, and: NEG VNEG VSUPNN for the negative charge pump, where VSUPD is the positive charge pump's diode supply (Figure 4). Output Voltage Selection Adjust the positive output voltage by connecting a voltage divider from the output (VPOS) to FBP to GND (see Typical Operating Circuit). Adjust the negative output voltage by connecting a voltage-divider from the output (VNEG) to FBN to REF. Select R4 and R6 in the 50k to 100k range. Higher resistor values improve efficiency at low output current but increase output voltage error due to the feedback input bias current. For the negative charge pump, higher resistor values also reduce the load on the reference, which should not exceed 50A for greatest accuracy (including current through the FLTSET resistors) to guarantee that VREF remains in regulation (see Electrical Characteristics Table). Calculate the remaining resistors with the following equations: R3 = R4 [(VPOS / VREF) - 1] R5 = R6 |VNEG / VREF| where VREF = 1.25V. VPOS may range from VSUPP to 40V, and VNEG may range from 0V to -40V. Flying Capacitor Increasing the flying capacitor (CX) value increases the output current capability. Above a certain point, increasing the capacitance has a negligible effect because the output current capability becomes dominated by the internal switch resistance and the diode impedance. The flying capacitor's voltage rating must exceed the following: [ ] VCXN(POS) > 1.5 VSUPD + VSUPP (N - 1) for the positive charge pump, and: VCXN(NEG) > 1.5(VSUPNN) Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. With ceramic capacitors, the output voltage ripple is dominated by the capacitance value. Use the following equation to approximate the required capacitor value: COUT ILOAD fCHP VRIPPLE where f CHP is typically f OSC /2 (see Electrical Characteristics). Charge-Pump Input Capacitor Use a bypass capacitor with a value equal to or greater than the flying capacitor. Place the capacitor as close to the IC as possible. Connect directly to power ground (PGND). Charge-Pump Rectifier Diodes Use Schottky diodes with a current rating equal to or greater than two times the average charge-pump input current, and a voltage rating at least 1.5 times VSUPP for the positive charge pump and VSUPN for the negative charge pump. Low-Dropout Linear Regulator (MAX1778/ MAX1881/MAX1883/MAX1884 Only) Output Voltage Selection Adjust the linear-regulator output voltage by connecting a voltage-divider from LDOOUT to FBL to GND (Figure 5). Select R8 in the 5k to 50k range. Calculate R7 with the following equation: R7 = R8 [(VLDOOUT / VFBL) - 1] where VFBL = 1.25V, and VLDOOUT may range from 1.25V to (VSUPL - 300mV). FBL's input bias current is ______________________________________________________________________________________ 29 MAX1778/MAX1880-MAX1885 input voltage at higher output currents (see Typical Operating Characteristics). So the maximum efficiency may be approximated by: MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer 0.8A (max). For less than 0.5% error due to FBL input bias current (IFBL), R8 must be less than 8k. Capacitor Selection and Regulator Stability Capacitors are required at the input and output of the MAX1778/MAX1881/MAX1883/MAX1884 for stable operation over the full temperature range and with load currents up to 40mA. Connect a 1F input bypass capacitor (CSUPL) between SUPL and ground to lower the source impedance of the input supply. Connect a ceramic capacitor between LDOOUT and ground, using the following equation to determine the lowest value required for stable operation: ILDOOUT(MAX) CLDOOUT 0.5ms X VLDOOUT For example, with a 5V linear regulator output voltage and a maximum 40mA load, use at least 4F of output capacitance. Applications that experience high-current load pulses may require more output capacitance. The ESR of the linear regulator's output capacitor (CLDOOUT) affects stability and output noise. Use output capacitors with an ESR of 0.1 or less to ensure stability and optimum transient response. Surfacemount ceramic capacitors are good for this purpose. Place CSUPL and CLDOOUT as close to the linear regulator as possible to minimize the impact of PC board trace inductance. External Pass Transistor For applications where the linear regulator currents exceed 40mA or where the power dissipation in the IC needs to be reduced, an external NPN transistor can be used. In this case, the internal LDO only provides the necessary base drive while the external NPN transistor supports the load, so most of the power dissipation occurs across the external transistor's collector and emitter. Selection of the external NPN transistor is based on three factors: the package's power dissipation, the current gain (), and the collector-to-emitter saturation voltage (VCE(SAT)). First, the maximum power dissipation should not exceed the transistor's package rating: P = (VCOLLECTOR - VLDO ) x ILOAD(MAX) Once the appropriate package type is selected, consider the NPN transistor's current gain. Since the internal LDO cannot source more than 40mA (min), the transistor's current gain must be high enough at the lowest collector-to-emitter voltage to support the maximum output load: 30 MIN ILOAD(MAX) - 40mA 40mA For stable operation, place a capacitor (CLDOOUT) and a minimum load resistor (R5) at the output of the internal linear regulator (the base of the external transistor) to set the dominant pole: 1 CLDOOUT 0.5ms VLDO ILOAD(MAX) V + 0.7V x LDO + R5 MIN Since the LDO cannot sink current, a minimum pulldown resistor (R5) is required at the base of the NPN transistor to sink leakage currents and improve the high-to-low load-transient response. Under no-load conditions, leakage currents from the internal pass transistor supply the output capacitor (CLDOOUT), even when the transistor is off. As the leakage currents increase over temperature, charge may build up on C LDOOUT , making the linear regulator's output rise above its set point. Therefore, R5 must sink at least 100A to guarantee proper regulation. Additionally, the minimum load current provided by R5 improves the high-to-low load transients by lowering the impedance seen by CLDOOUT after the transient occurs. Therefore, if large load transients are expected, select R5 so that the minimum load current is 10% of the transistor's maximum base current: R5 = VLDO + 0.7V = 0.1 ILDOOUT(MIN) (V + 0.7V)MIN LDO I LOAD(MAX) Alternatively, output capacitance placed on the external linear regulator's output (the emitter) adds a second pole that could destabilize the regulator. A capacitive-divider from the transistor's base to the feedback input (C2 and C3, Figure 7) circumvents this second pole by adding a pole-zero pair. Furthermore, to minimize excessive overshoot, the capacitive-divider's ratio must be the same as the resistive-divider's ratio. Once the output capacitor is selected, using the following equations to determine the required capacitive-divider values: CLDO R4 1 + 100 R3 C2 R4 V = = REF C2 + C3 R3 + R4 VLDO C2 + C3 ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer voltage-divider from SUPB to BUF+ to GND (Figure 6). Select R12 in the 10k to 100k range. Calculate R11 with the following equation: V R11 = R12 SUPB - 1 V BUF + where VSUPB may range from 4.5V to 13V, and VBUF+ may range from 1.2V to (VSUPB - 1.2V). Connect a minimum 1F ceramic capacitor from BUFOUT to ground. PC Board Layout and Grounding Careful PC board layout is extremely important for proper operation. Follow the following guidelines for good PC board layout: 1) Place the main step-up converter output diode and output capacitor less than 0.2in (5mm) from the LX and PGND pins with wide traces and no vias. 2) Separate analog ground and power ground. The ground connections for the step-up converter's and charge pump's input and output capacitors should be connected to the power ground plane. The linear regulator's and VCOM buffer's input and output capacitors should be connected to a separate power-ground path, star-connected to the PGND pin to minimize voltage drops. When using multilayer boards, the top layer should contain the boost VCOM Buffer (Operational Transconductance Amplifier) Buffer Output Voltage and Capacitor Selection The positive input (BUF+) features dual mode operation. Connect BUF+ to GND for the preset VSUPB/2 output voltage, set by an internal 50% resistive-divider. Adjust the amplifier's output voltage by connecting a INPUT VIN = 3.3V L1 6.8H CIN 4.7F IN C1 0.22F SHDN LX MAIN VMAIN = 8V COUT (2) 4.7F R1 274k FB MAX1778 MAX1883 (MAX1881)* (MAX1884)* SUPL LDOOUT INTG R2 49.9k Q1 R5 1.5k REF CREF 0.22F CLDOIN 1F CLDOOUT 4.7F C2 0.01F R3 49.9k CLDO 1F LDO VLDO = 2.5V FBL PGND GND C3 0.01F R4 49.9k Figure 7. External Linear Regulator ______________________________________________________________________________________ 31 MAX1778/MAX1880-MAX1885 Input-Output (Dropout) Voltage and Startup A linear regulator's minimum input-to-output voltage differential (dropout voltage) determines the lowest useable supply voltage. Because the MAX1778/ MAX1881/MAX1883/MAX1884 use an internal PNP transistor (or external NPN transistor), their dropout voltage is a function of the transistor's collector-to-emitter saturation voltage (see Typical Operating Characteristics). The linear regulator's quiescent current increases when in dropout. The internal linear regulator will try to start up once its supply voltage (VSUPL) exceeds 4V. When the linear regulator powers up, the linear regulator may be in dropout if the linear regulator's output set voltage is higher than its input supply voltage. Therefore, during this brief period, the linear regulator draws additional supply current until the input supply voltage exceeds the output set voltage plus the pass transistor's saturation voltage (VLDO(SET) + VCE(SAT)). MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer regulator and charge-pump power ground plane, and the inner layer should contain the analog ground plane and power-ground plane/path for the VCOM buffer and LDO. Connect all three ground planes together at one place near the PGND pin. high-impedance nodes on the bottom layer. The fast-charging nodes, such as the LX and chargepump driver nodes, should not have any other traces or ground planes near by. 5) Keep the charge-pump circuitry as close to the IC as possible, using wide traces and avoiding vias when possible. Place 0.1F ceramic bypass capacitors near the charge-pump input pins (SUPP and SUPN) to the PGND pin. 6) To maximize output power and efficiency and minimize output ripple voltage, use extra wide, power ground traces, and solder the IC's power ground pin directly to it. 3) Locate all feedback resistive-dividers as close to their respective feedback pins as possible. The voltage-divider's center trace should be kept short. Avoid running any feedback trace near the LX switching node or the charge-pump drivers. The resistive-dividers' ground connections should be to analog ground (GND). 4) When using multilayer boards, separate the top signal layer and bottom signal layer with a ground plane between to eliminate capacitive coupling between fast-charging nodes on the top layer and INPUT VIN = 5V Refer to the MAX1778/MAX1880-MAX1885 evaluation kit for an example of proper board layout. L1 10H CIN (2) 4.7F C1 0.22F RRDY 100k TO LOGIC IN LX SHDN FB R1 86.6k RDY LDO VLDO = 3.3V LDOOUT CLDOOUT 4.7F C6 1F R8 10k R7 16.4k R8 1.5k C4 0.1F MAX1778 DRVP C6 0.01F FBL C7 0.01F NEGATIVE VNEG = -8V SUPB SUPN SUPP FBP R4 49.9k DRVN C2 0.1F FBN C3 1.0F R5 316k R6 49.9k CREF 0.22F BUFOUT BUF- INTG PGND BUF+ GND TGND C5 1.0F R3 750k CBUF 1.0F FLTSET REF BUFFER OUTPUT VBUFOUT = VSUPB/2 R9 30k REF R10 100k Figure 8. 5V Input Monitor Application 32 MAIN VMAIN = 12V CCOMP 470pF R2 10k SUPL Q1 RCOMP 4.7k COUT (2) 10F ______________________________________________________________________________________ POSITIVE VPOS = 20V Quad-Output TFT LCD DC-DC Converters with Buffer Larger output capacitors with higher voltage ratings allow configurations with output voltages above 10V. Additionally, physically larger inductors with less series resistance and higher saturation ratings provide more output current and higher efficiency. Low-Profile Components Notebook applications generally require low-profile components, potentially limiting the circuit's performance. For example, low-profile inductors typically have lower saturation ratings and more series resistance, limiting output current and efficiency. Low-profile capacitors have lower voltage ratings for a given capacitance value, so 3.3F low-profile capacitors with voltage ratings greater than 10V were not available at the time of publication. Input Voltage Above and Below the Output Voltage Combining the step-up converter and linear regulator as shown in Figure 9 provides output voltage regulation above and below the input voltage. Supplied by the step-up converter, the linear regulator output provides a constant output voltage (VLDO). When the input voltage exceeds the main step-up converter's nominal output voltage, the controller stops switching but the linear regulator maintains the output voltage. When the input voltage drops below the output voltage, the step-up Desktop Monitors Monitor applications do not have the same component height restrictions associated with laptops, allowing more flexibility in component selection (Figure 8). POWER INPUT VBATT = 10V TO 15V INPUT VIN = 3.3V TO 5V L1 6.8H CIN 4.7F LX IN C1 0.1F FB RRDY 100k RDY SUPL BUFOUT CBUF 1.0F BUFC2 0.1F SUPB SUPN SUPP R5 475k R7 470k R9 6.8k LDO VLDO = 13V CLDO (2) 3.3F R8 49.9k C4 0.1F REF DRVP R9 30k R10 100k FBP FLTSET CINTG 470pF C7 0.1F FBL R6 49.9k CREF 0.22F CLDOOUT 3.3F C6 0.1F FBN C3 1.0F Q1 LDOOUT MAX1778 DRVN NEGATIVE VNEG = -12V R2 49.9k SHDN TO LOGIC BUFFER OUTPUT VBUFOUT = VSUPB/2 COUT (3) 3.3F R1 511k INTG BUF+ GND PGND TGND R4 49.9k R3 909k C5 1.0F POSITIVE VPOS = 24V Figure 9. Input Voltage Above and Below the Output Voltage ______________________________________________________________________________________ 33 MAX1778/MAX1880-MAX1885 Applications Information MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer INPUT VIN = 3.3V L1 6.8H CIN 4.7F STARTUP MAIN VMAIN(START) = 8V C1 0.22F SHDN C8 3.3F COUT (2) 3.3F R1 274k LX IN SYSTEM MAIN VMAIN(SYS) = 8V FB R2 49.9k C10 0.1F SUPP C4 0.1F MAX1778 C5 1.0F DRVP C6 0.1F INTG R7 10k C7 1.0F REF CREF 0.22F R3 750k R9 30k FBP FLTSET R4 49.9k R10 100k STARTUP POSITIVE VPOS(START) = 20V SYSTEM POSITIVE VPOS(SYS) = 20V Q3 Q2 INPUT VIN = 3.3V RDY TGND PGND GND RRDY 5.1k R8 100k Figure 10. Power-Up Sequencing and Fault Protection; converter steps up the input voltage so that the linear regulator will not drop out. Therefore, to guarantee that the external pass transistor does not saturate, the stepup converter's output voltage must be set above the linear regulator's output voltage plus the transistor's saturation rating (VMAIN VLDO + VSAT). Power-Up Sequencing and Fault Protection The MAX1778/MAX1880-MAX1885's fault protection cannot be activated until the power-up sequence is successfully completed and the power ready output goes low. Therefore, faults on the main output or positive charge-pump output could damage the controller or external components. Additional fault protection may be added as shown in Figure 10. The external MOSFET and PNP transistor isolate the positive outputs during startup. When the controller finishes the power-up sequence, the power-ready output goes low, turning on 34 the PNP transistor. Any fault on the positive chargepump output will pull down the charge pump's output voltage and trigger the fault protection; otherwise, the MOSFET's gate slow charges. Once the MOSFET turns on, any faults on the main step-up converter's output will pull down the main output voltage and trigger the fault protection. VCOM Buffer Startup The VCOM buffer does not include soft-start. Therefore, once the VCOM buffer turns on, it draws high surge currents while charging the output capacitance. In some applications, the buffer's high startup surge current could potentially trip the fault detection circuit, forcing the controller to shut down. In these cases, adding a soft-start resistive divider between SUPB and BUFOUT reduces the startup surge current and voltage drops associated with this load (Figure 11), as shown in ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer CIN 4.7F LX IN C1 0.22F SHDN R2 49.9k SUPB REF CREF 0.22F R1 274k FB MAX1778 INTG MAIN VMAIN = 8V COUT (2) 4.7F BUF- R3 10k CSUPB 1.0F BUFFER OUTPUT VBUFOUT = VSUPB/2 BUFOUT BUF+ PGND GND R4 10k CBUF 1.0F [( VV R3 = R4 SUPB BUFOUT ) -1] Figure 11. VCOM Buffer Soft-Start; Selector Guide the Typical Operating Characteristics. Set the resistive divider to precharge BUFOUT, matching the buffer's output set voltage: V R 3 = R4 SUPB - 1 VBUFOUT These resistor values are selected to charge the output capacitor close to the output set voltage before the buffer starts up: CBUFOUT (R3 || R4) 5000 fOSC PART STEP-UP SWITCHING FREQUENCY (Hz) DUAL CHARGE PUMPS LINEAR REGULATOR Yes MAX1778 1M Yes MAX1880 1M Yes No MAX1881 500k Yes Yes MAX1882 500k Yes No MAX1883 1M No Yes MAX1884 500k No Yes MAX1885 500k No No ______________________________________________________________________________________ 35 MAX1778/MAX1880-MAX1885 INPUT VIN = 3.3V L1 6.8H Quad-Output TFT LCD DC-DC Converters with Buffer MAX1778/MAX1880-MAX1885 Typical Operating Circuit MAIN INPUT TO LOGIC LDO OUTPUT IN LX SHDN FB RDY SUPL LDOOUT SUPB SUPN SUPP FBL MAX1778 DRVP DRVN NEGATIVE FBP POSITIVE FBN REF BUFOUT BUF- BUFFER OUTPUT BUF+ INTG PGND 36 FLTSET GND TGND ______________________________________________________________________________________ Quad-Output TFT LCD DC-DC Converters with Buffer TOP VIEW FB 1 24 RDY INTG 2 23 TGND IN 3 22 LX BUF+ 4 FB 1 24 RDY INTG 2 23 TGND IN 3 22 LX 21 PGND BUF+ 4 20 DRVP BUF- 5 SUPB 6 19 SUPP SUPB 6 19 SUPP BUFOUT 7 18 DRVN BUFOUT 7 18 DRVN GND 8 17 SUPN GND 8 17 SUPN REF 9 16 FLTSET REF 9 16 FLTSET FBP 10 15 FBL FBP 10 15 N.C. FBN 11 14 LDOOUT FBN 11 14 N.C. SHDN 12 13 N.C. BUF- 5 MAX1778 MAX1881 SHDN 12 13 SUPL TSSOP 21 PGND MAX1880 MAX1882 20 DRVP TSSOP TOP VIEW 20 RDY FB 1 19 TGND INTG 2 18 LX IN 3 BUF+ 4 BUF- 5 SUPB 6 MAX1883 MAX1884 BUFOUT 7 16 N.C. BUF- 5 GND 8 13 FBL REF 9 12 LDOOUT SHDN 10 11 SUPL TSSOP 18 LX IN 3 BUF+ 4 14 FLTSET 19 TGND INTG 2 17 PGND 15 N.C. 20 RDY FB 1 17 PGND MAX1885 16 N.C. 15 N.C. SUPB 6 14 FLTSET BUFOUT 7 GND 8 13 N.C. REF 9 12 N.C. SHDN 10 11 N.C. TSSOP ______________________________________________________________________________________ 37 MAX1778/MAX1880-MAX1885 Pin Configurations MAX1778/MAX1880-MAX1885 Quad-Output TFT LCD DC-DC Converters with Buffer Chip Information TRANSISTOR COUNT: 3739 38 ______________________________________________________________________________________ Quad-Output TFT LCD DC/DC Converters with Buffer TSSOP4.40mm.EPS PACKAGE OUTLINE, TSSOP 4.40mm BODY 21-0066 G 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 39 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX1778/MAX1880-MAX1885 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)