PentiumII-266 - Intel

Pentium® II Processor - Low Power

Datasheet

Product Features

The IntelPentiumII Processor - Low Power introduces a higher level of performance for

today’s applied compu ting environment, includin g multimedia enhancements and improv ed

Internet and communications capabilities. On top of its built-in power management capabilities,

the Pentium II Processor - Low Power takes advantage of software designed for Intel’s MMX

technolog y to unleash enhanced color, smoother graphics and other multimedia and

communications enhancements.

■Available at 266 MHz and 333 MHz

■Supports the Intel architecture with

dynamic execution

■Integrated primary 16-Kbyte instruction

cache and 16-Kbyte write back data cache

■Integrated 256-Kbyte second-level cache

■BGA packaging technology

— Supports thin form factor designs

— Exposed die enables more ef ficient heat

dissipation

■Fully com patible with previous Intel

microprocessors

— Binary compatible with all applicatio ns

— Support for MMX™ technology

■Power Management Features

— Quick Start and Deep Sleep modes

provide extremely low power

dissipation

■Low-Power GTL+ processor system bus

interface

■Integrated math co-processor

■Integrated thermal diode

Order Number: 273268-001

September, 1999

Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intend ed for use in medical, life sa ving, or life sustaining ap plications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Pentium® II Processor - Low Power may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Datasheet 3
 Pentium
®
 
II
 Processor - Low Power
Contents
0 Introduction..................................................................................................................7
1 Overview ...............................................................................................................8
2 Terminology...........................................................................................................8
3 References............................................................................................................9
0 Pentium® II Processor - Low Power Features.............................................10
1 New Features in the Pentium® II Proc es so r - Low Power............ ...... ....... ...... ....1 0
1.1 Integrated L2 Cache...............................................................................10
1.2 Signal Differences from the Mini-Cartridge Processors .........................10
2 Power Management............................................................................................11
2.1 Clock Control Architec ture.............. .................... ................... ....... ..........11
2.2 Normal State ..........................................................................................12
2.3 Auto Halt State ............ ....... ...... ...... ....... ...... ....... ...... ....... ...... .................1 2
2.4 Stop Grant State................. ...... ...... ....... ................... .................... ...... ....1 3
2.5 Quick Start State ....................................................................................13
2.6 Halt/Grant Snoop State ..........................................................................14
2.7 Sleep State.............................................................................................14
2.8 Deep Sleep State...................................................................................14
2.9 Operating System Implications of Quick Start and Sleep States ...........15
3 Low Power GTL+ ................................................................................................15
3.1 GTL+ Signals..........................................................................................16
4 Pentium® II Processor - Low Power CPUID........................................................16
0 Electrical Specifica tions........................................................................................17
1 Processor System Signals ..................................................................................17
1.1 Power Sequencing Requirements..........................................................18
1.2 Test Access Port (TAP) Connection.......................................................18
1.3 Catastrophic Thermal Protection............................................................19
1.4 Unused Signals ......................................................................................19
1.5 Signal State in Low Power States..........................................................19
1.5.1 System Bus Signals ..................................................................19
1.5.2 CMOS and Open-Drain Signals ................................................19
1.5.3 Other Signa ls......... ...... ...... ....... ...... ....... ................... .................1 9
2 Power Supply Requirements...............................................................................20
2.1 Decoupling Recommendations ..............................................................20
2.2 Voltage Planes .......................................................................................20
3 System Bus Clock and Processor Clocking........................................................21
4 Maximum Ratings................................................................................................21
5 DC Specificat ion s.. ...... ....... ...... ....... ...... ...... ....... ...... ....... ................... .................2 2
6 AC Specifications................................................................................................24
6.1 System Bus, Clock, APIC, TAP, CMOS and Open-Drain 
AC Specifications ...................................................................................24
0 System Signal Simulations..................................................................................33
1 System Bus Clock (BCLK) Signal Quality Specifications....................................33
2 Low Power GTL+ Signal Quality Specifications..................................................34
3 Non-Low Pow er GTL+ Si gna l Quali ty Spe cif icat ions ...... ...... ....... .......................35

Pentium
®
 
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 Processor - Low Power 
Datasheet
3.1 Overshoot and Undershoot Guidelines..................................................35
3.2 Ringback Specification...........................................................................36
3.3 Settling Limit Guideline ..........................................................................36
0 Mechanical Specifications ...................................................................................37
1 Dimensions .........................................................................................................37
2 Signal Listings.....................................................................................................39
0 T hermal Specifications..........................................................................................48
1 Thermal Diode.....................................................................................................49
2 Case Temperature ..............................................................................................50
0 Processor Initialization and Configuration....................................................51
1 Description..........................................................................................................51
1.1 Quick Start Ena ble ......... ....... ................... ................... ....... ................... .51
1.2 System Bus Frequency..........................................................................51
1.3 APIC Disable..........................................................................................51
2 Clock Frequencies and Ratios ............................................................................51
0 Processor Interface.................................................................................................52
1 Alphabetical Signal Reference............................................................................52
1.1 A[35:3]# (I/O - Low Power GTL+)...........................................................52
1.2 A20M# (I - 2.5V Tolerant)............ ...... ....... ...... ....... ................... ..............52
1.3 ADS# (I/O - Low Power GTL+)...............................................................52
1.4 AERR# (I/O - Low Power GTL+)............................................................52
1.5 AP[1:0]# (I/O - Low Power GTL+)..........................................................53
1.6 BCLK (I - 2.5V Tolerant).........................................................................53
1.7 BERR# (I/O - Low Power GTL+)............................................................53
1.8 BINIT# (I/O - Low Power GTL+).............................................................53
1.9 BNR# (I/O - Low Power GTL+) ..............................................................53
1.10 BP[3:2]# (I/O - Low Power GTL+)..........................................................54
1.11 BPM[1: 0]# (I/O - Low Power GTL+)...................... ...... .................... .......54
1.12 BPRI# (I - Low Power GTL+) .................................................................54
1.13 BREQ0# (I/O - Low Power GTL+)..........................................................54
1.14 BSEL (I - 2.5 V Tolerant)........................................................................54
1.15 D[63:0]# (I/O - Low Power GTL+) ..........................................................54
1.16 DBSY# (I/O - Low Power GTL+)............................................................55
1.17 DEFER# (I - Low Power GTL+)..............................................................55
1.18 DEP[7:0]# (I/O - Low Power GTL+)........................................................55
1.19 DRDY# (I/O - Low Power GTL+)............................................................55
1.20 EDGCTRLN (Analog).............................................................................55
1.21 FERR# (O - 2.5 V Tolerant Open-drain).................................................55
1.22 FLUSH# (I - 2.5 V Tolerant) ...................................................................55
1.23 HIT# (I/O - Low Power GTL+), HITM# (I/O - Low Power GTL+)............56
1.24 IERR# (O - 2.5 V Tolerant Open-drain)..................................................56
1.25 IGNNE# (I - 2.5 V Tolerant)....................................................................56
1.26 INIT# (I - 2.5 V Tolerant) ........................................................................56
1.27 INTR (I - 2.5 V Tolerant).........................................................................56
1.28 LOCK# (I/O - Low Power GTL+)............................................................57
1.29 NMI (I - 2.5 V Tolerant) ..........................................................................57
1.30 PICCLK (I - 2.5 V Tolerant)....................................................................57

Datasheet 5
 Pentium
®
 
II
 Processor - Low Power
1.31 PICD[1:0] (I/O - 2.5 V Tolerant Open-drain)...........................................57
1.32 PRDY# (O - Low Power GTL+)..............................................................57
1.33 PREQ# (I - 2.5 V Tolerant).....................................................................58
1.34 PWRGOOD (I - 2.5 V Tolerant)..............................................................58
1.35 REQ[4:0]# (I/O - Low Power GTL+) .......................................................58
1.36 RESET# (I - Low Power GTL+)..............................................................58
1.37 RP# (I/O - Low Power GTL+).................................................................59
1.38 RS[2:0]# (I - Low Power GTL+)..............................................................59
1.39 RSP# (I - Low Power GTL+)...................................................................59
1.40 SLP# (I - 2.5V Tolerant) .........................................................................59
1.41 SMI# (I - 2.5 V Tolerant).........................................................................60
1.42 STPCLK# (I - 2.5 V Tolerant) .................................................................60
1.43 TCK (I - 2.5 V Tolerant)..........................................................................60
1.44 TDI (I - 2.5 V Tolerant) ...........................................................................60
1.45 TDO (O - 2.5 V Tolerant Open-drain).....................................................60
1.46 THERMDA, THERMDC (Analog)...........................................................60
1.47 TMS (I - 2.5 V Tolerant)..........................................................................60
1.48 TRDY# (I - Low Power GTL+)................................................................60
1.49 TRST# (I - 2.5 V Tolerant)......................................................................61
2 Signal Summaries...............................................................................................61
Figures 1 Components of a Pentium® II Processor - Low Power-based System .................7
Cl ock Control  States.... ....... ...... ....... ...... ...... ....... ...... ....... ................... ....... ..........11
Ramp Rate Requirement.....................................................................................18
PLL LC Filter .......................................................................................................20
Generic Clock Waveform ....................................................................................28
Valid Delay Timings.............................................................................................28
Setup and Hold Timings......................................................................................29
Cold/Warm Reset and Configuration Timings.....................................................29
Power-On Reset Timings....................................................................................30
Test Timings (Boundary Scan)............................................................................30
Test Reset Timings .............................................................................................31
Quick Start/Deep Sleep Timing...........................................................................31
Stop Grant/S lee p/De ep Sleep Timi ng................ ...... .................... ................... ....3 2
BCLK Generic Clock Waveform..........................................................................33
Low to High, Low Power GTL+ Receiver Ringback Tolerance ...........................34
Non-GTL+ Overshoot/Undershoot and Ringback ...............................................35
Surface-Mount BGA1 Package-Top and Side View............................................38
Surface-Mount BGA1 Package-Bottom View......................................................38
Ball Map - Top View............................................................................................39
Technique for Measuring Case Temperature......................................................50
PWRGOOD Relationship at Power-On...............................................................58

Pentium
®
 
II
 Processor - Low Power 
Datasheet
Tables 1 New Pentium® II  Processor - Low Power Signals...............................................10
Removed Mini-Cartridge Processor Signals.......................................................10
Clock State Characteristics.................................................................................13
4Pentium
® II Processor - Low Power CPUID .......................................................16
5Pentium
® II Processor - Low Power CPUID Cache and TLB Descriptors ..........16
System Signal Groups ........................................................................................17
Recommended Resistors for Open Drain Signals ..............................................18
LC Filter Specifications .......................................................................................20
Core Frequency to System Bus Ratio Configuration ..........................................21
Pentium® II Processor - Low Power Absolute Maximum Ratings.......................22
Pentium® II Processor - Low Power Specifications ............................................22
Low Power GTL+ Signal Group DC Specifications.............................................23
Low Power GTL+ Bus DC Specifications............................................................24
Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications.....24
System Bus Clock AC Specifications1................................................................25
Valid Pentium® II Processor - Low Power Frequencies......................................25
Low Power GTL+ Signal Groups AC Specifications ...........................................25
CMOS and Open-Drain Signal Groups AC Specifications..................................26
Reset Configuration AC Specifications...............................................................26
TAP Signal AC Specifications.............................................................................27
Quick Start/Deep Sleep AC Specifications .........................................................27
Stop Grant/Sleep/Deep Sleep AC Specifications................................................28
BCLK Signal Quality Specifications ....................................................................33
Low Power GTL+ Signal Group Ringback Specification.....................................34
Signal Ringback Specifications for Non-GTL+ Signals.......................................36
Surface-Mount BGA1 Package Specifications....................................................37
Signal Listing in Order by Ball Number ...............................................................40
Signal Listing in Order by Signal Name ..............................................................44
Voltage and No-Connect Ball Locations .............................................................47
Pentium® II Processor - Low Power Specifications ............................................48
Thermal Diode Interface......................................................................................49
Thermal Diode Specifications .............................................................................49
Input Signals .......................................................................................................61
Output Signals.....................................................................................................62
Input/Output Signals (Single Driver)....................................................................62
Input/Output Signals (Multiple Driver) .................................................................62

Pentium

Processor - Low Power

Datasheet 7

1.0 Introduction

The Pentium® II Processor - Low Power is offered at 333 MHz and 266 MHz, with a system bus

speed of 66 MHz. The Pentium II Processor - Low Power has an integrated L2 cache and a 64-bit

high perform ance system bus. The in tegrated L2 cache is designed to help impro ve performance; it

complements the system bus by providing critical data faster and reducing total system power

consumption. The Pentium I I Processor - Low Power’s 64-bit wide Low Power Gunning

Transceiver Logic (GTL+) system bus is compatible with the 440BX AGPset and provides a glue-

less, point-to-point interface for an I/O bridge/memory controller. Figure 1 shows the components

of a Pentium II Processor - Low Power-based system and how the components connect to the

processor.

Figure 1. Components of a Pentium® II Processor - Low Power-based System

PIIX4E

South Bridge

Pentium® II

Processor TAP

443BX

North Bridge DRAM

PCI Bus

System Bus

ISA/EIO Bus

System

Controller

Thermal

Sensor

SMBus

CMOS/Open Drain

Pentium

Processor - Low Power

8Datasheet

1.1 Overview

•Performance for Applied Computing applications

— Supports the Intel Architecture with Dynamic Execution

— Supports the Intel Architecture MMX technology

— Integrated Intel Floating-Poin t Unit compatible w ith the IEEE Std 754

•Integrated primary (L1) instruction and data caches

— 4-way set associative, 32-byte line size, one line per sector

— 16-Kbyte instruction cache and 16-Kbyte writeback data cache

— Cacheable range programmable by processor programmable registers

•Integrated second level (L2) cache

— 4-way set-associative, 32-byte line size, one line per sector

— Operates at full core speed

— 256-Kbyte, ECC protected cache data array

— 4 Gbyte cacheable range

•Low Power GTL+ system bus interface

— 64-bit data bus, 66-MHz operation

— Uni-processor, two loads only (processor and I/O bridge/memory controller)

— Short trace length and low capacitance allows for single-ended termination

•Voltage reduction technology

•Pentium II processor clock control

— Quick Start for low power, low exit latenc y clock “throttling”

— Deep Sleep mode for extremely low power dissipation

•Thermal diode for measuring processor temperature

1.2 Terminology

In this document a ‘#’ symbol following a signal name indicates that the signal is active low. This

means that when the signal is asserted (based on the name of the signal) it is in an electrical low

state. Otherwise, signals are driven in an electrical high state when they are asserted. In state

machine diagrams, a signal n ame in a condition indicates the conditio n of that signal being

asserted. If the signal name is preceded by a ‘!’ symbol, then it indicates the condition of that signal

not being asserted. For example, the condition ‘!STPCLK# and HS’ is equivalent to ‘the active low

signal STPCLK# is unasserted (i.e., it is at 2.5 V) and the HS condition is true.’ The symbols ‘L’

and ‘H’ refer respectively to electrical low and electrical high signal levels. The symbols ‘0’ and

‘1’ refer respectively to logical low and logical high signal levels. For example, BD[3:0] = ‘1010’

= ‘HLHL’ refers to a hexadecimal ‘A’, and D[3:0]# = ‘1010’ = ‘LHLH’ also refers to a

hexadecimal ‘A’.

Pentium

Processor - Low Power

Datasheet 9

1.3 References

Document Order Number

Pentium®

Processor at 233 MHz, 266 MHz, 300 MHz and 333 MHz

datasheet 243335

Pentium®

Processor Developer’s Manual

243502

Intel Architecture Software Developer ’s Manual

V olume I: Basic Architecture

Volume II: Instruction Set Reference

Volume III: System Programming Guide

243190

243191

243192

Mobile Pentium®

Processor System Bus Layout Guideline

243672

Mobile Pentium®

Processor Mechanical and Thermal User’s Guide

243671

Pentium

Processor - Low Power

10 Datasheet

2.0 Pentium® II Processor - Low Power Features

2.1 New Features in the Pentium® II Processor - Low Power

New features include an integrated L2 cache, and various signal differences from the mini-

cartridge processors.

2.1.1 Integrated L2 Cache

The Pentium II Processor - Low Power has a 2 56-Kbyte L2 cache integr ated onto the processor die.

The L2 cache is 4-way set associative and runs at the sp eed of the processor core. Th e L2 cache can

cache up to 4 Gbytes of memory.

2.1.2 Signal Differences from the Mini-Cartridge Processors

Table 1. New Pentium® II Processor - Low Power Signals

Signals Purpose

EDGCTRLN GTL+ output buffer edge rate control signals

NC No Connect (same as RSVD signals on mini-cartridge)

BSEL Bus speed select

TESTHI, TESTHI3 Testability signals. Pull-up to VCC.

TESTHI2 Testability signals. Pull-up to VCCP.

TESTLO Testability signals. Connect to VSS.

THERMDA, THERMDC Thermal diode

PLL1, PLL2 PLL analog power supply

VREF GTL+ reference voltage

Table 2. Removed Mini-Cartridge Processor Signals

Signals Purpose

SMBALERT#, SMBCLK, SMBDA TA SMBus interface for the thermal sensor

VCC_S, VCCP_S, VSS_S Voltage sense signals

VCC3 3.3 V supply for ex tern al L2 cache components

VID[3:0] Voltage identification

Pentium

Processor - Low Power

Datasheet 11

2.2 Power Management

2.2.1 Clock Control Architecture

The Pentium II Processor - Low Power clock control arch itecture (Figure 2) has been optimized for

leading edge “Deep Green” designs.

Figure 2. Clock Control States

NOTES: halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#

HLT - HLT instruction executed

HS - Processor Halt State

QSE - Quick Start State Enabled

SGA - Stop Grant Acknowledge bus cycle issued

Stop break - BINIT#, FLUSH#, RESET#

HALT/Grant

Snoop

Normal

HS=false

Stop

Grant

Auto

Halt

HS=true

Quick

Start

Sleep

Deep

Sleep

(!STPCLK#

and !HS) or

stop break

STPCLK# and

!QSE and SGA

Snoop

occurs

Snoop

serviced

STPCLK# and

QSE and SGA

(!STPCLK# and !HS)

or RESET#

Snoop

serviced Snoop

occurs

!STPCLK#

and HS

STPCLK# and

!QSE and SGA

HLT and

halt bus cycle

halt

break

Snoop

serviced

Snoop

occurs

STPCLK# and

QSE and SGA

!STPCLK#

and HS

!SLP# or

RESET#

SLP#

BCLK

stopped

BCLK on

and !QSE

BCLK

stopped

BCLK on

and QSE

V0001-00

Pentium

Processor - Low Power

12 Datasheet

The Auto Halt state provides a low power clock state that can be controlled through the software

execution of the HLT instruction. The Quick Start state provides a very low power, low exit latency

clock state that can be used for hardware controlled “idle” computer states. The Deep Sleep state

provides an extremely low power state that can be used for “Power-on Suspend” computer states,

which is an alternative to shutting off the processor ’s power. Compared to the Pentium processor

exit latency of 1 ms, the exit latency of the Deep Sleep state has been reduced to 30 µs in the

Pentium II Processor - Low Power. Performing state transitions not shown in Figu re 2 is neither

recommended nor supported.

The clock control architecture consists of seven different clock states: Normal, Stop Grant, Auto

Halt, Quick Start, HALT/Grant Snoop, Sleep and Deep Sleep states. The Stop Grant and Quick

Start clock states are mutually exclusive; a strapping option on signal A15# chooses which state is

entered when the STPCLK# signal is assert ed. Strapping the A15# signal to ground at Reset

enables the Quick Start state; otherwise, asserting the STPCLK# signal puts the processor into the

Stop Grant state. The Stop Grant state has a higher power level than the Quick Start state and is

designed for SMP platforms. The Quick Start state has a much lower power level, b ut it can only be

used in uniprocessor platforms. Table 3 provides clock state characteristics (power numbers based

on estimat es fo r a P e nti um II Processor - Low Power r unn i ng at 36 6 MHz), whic h are des cri bed in

detail in the followin g sections.

2.2.2 Nor mal State

The Normal state of the processor is the normal operating mode in which the processor’s internal

clock is running and the processor is actively executing instructions.

2.2.3 Auto Halt State

This is a low power mo de entered by the process or throu gh the execution of the HLT instruction.

The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is

made by a halt break event (one of th e following signals going active: NMI, INTR , BINIT#, INIT#,

RESET#, FLUSH# or SMI#).

Asserting the STPCLK# signal while in the Auto Halt state causes the processor to transition to the

Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle is issued. Deasserting

STPCLK# causes the process or to return to the Auto Halt state withou t issuing a new Halt bus

cycle.

The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management

Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel®

Ar ch itecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more

information. No Halt bus cycle is issued when returning to the Auto Halt state from System

Management Mode (SMM).

The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have

been flushed, the processor returns to the Auto Halt state without issuing a Halt bus cycle.

Transitions in the A20M# and PREQ# signals are recognized while in the Auto Halt state.

Pentium

Processor - Low Power

Datasheet 13

2.2.4 Stop Grant State

The processor enters this mode with the assertion of the STPCLK# signal when it is configured for

Stop Grant s tate (via th e A15# strapping option). The processor is still able to respond to snoop

requests and latch interrupts. Latched interrupt s will b e serviced when the p rocessor returns to the

Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the

Normal state can be made by the deassertion of the STPCLK# signal, or t he occurrence of a stop

break event (a BINIT#, FLUSH# or RESET# assertion).

The processor returns to th e Stop Grant state after the completio n of a BINIT# bus initiali zation

unless STPCLK# has been de-asserted. RESET# assertion causes the processor to immediately

initialize itself, but the processor stays in the Stop Grant state after initialization until STPCLK# is

deasserted. When the FLUSH# signal is asserted, the processor flushes the on-chip caches and

returns to the Stop Grant state. A trans ition to the Sleep state can be ma de by the assertion of the

SLP# signal.

While in the Stop Grant state, assertions of SMI#, INIT#, INTR and NMI are latched by the

processor. These latched events are not serviced u ntil the processor returns to the Normal state.

Only one of each event is recognized upon return to the Normal state.

2.2.5 Quick Start State

This is a mode entered b y the processor with the assertio n of the STPCLK# signal w hen it is

configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the

processor is only capable of acting on snoop transactions generated by the system bus priority

device. Because of its snooping behavior, Quick Start can only be used in a Uniprocessor (UP)

configuration.

Table 3. Clock State Characteristics

Clock State Exit Latency Power Snooping? System Uses

Normal N/A Varies Yes Normal program execution

Auto Halt Approximately 10 bus clocks 1.25 W Yes S/W controlled entry idle

mode

Stop Grant Approximately 10 bus clocks 1.25 W Yes H/W controlled entry/exit

power throttling

Quick Start

Through snoop, to HALT/

Grant Snoop state: immediate

through STPCLK#, to Normal

state: 8 bus clocks

0.5 W Yes H/W controlled entry/exit

power throttling

HALT/Grant

Snoop A few bus clocks after the end

of snoop activity. Not specified Yes Supports snooping in the low

power states

Sleep To Stop Grant state 10 bus

clocks 0.5 W N o H/W controlled entry/exit

desktop idle mode support

Deep Sleep 30 ms 150 mW No H/W controlled entry/exit

powered-on suspend suppo rt

NOTE: Not 100% tested. Specified at 50° C by design/characterization.

Pentium

Processor - Low Power

14 Datasheet

A transition to the Deep Sleep state can be made by s topping the clock input to the processor. A

transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal

is deasserted.

While in this state th e processor is limited in its ability to respon d to input. It is incapable of

latching any interrupts, servicing snoop transact ions from symmetric bus masters or responding to

FLUSH# or BINIT# assertio ns. While the processo r is in the Quick Start state, it wil l not respond

properly to any input signal other than STPCLK#, RESET# or BPRI#. If any other input signal

changes, the behavior of the processor will be unpredictable. No serial interrupt messages may

begin or be in progress while the processor is in the Quick Start state.

RESET# assertion causes the processor to im m e diately initial ize itself, bu t the processor stays in

the Quick Start state after initialization until STPCLK# is deasserted.

2.2.6 Halt/Grant Snoop State

The processor responds to snoop transactions on the system bus while in the Auto Halt, Stop Grant

or Quick Start state. When a snoop transaction is presented on the system bus the processor enters

the HALT/Grant Snoop state. The processor remains in this state until the snoop has been serviced

and the system bus is quiet. Af ter the sn oop has b een serv iced, th e pr ocessor retu rns to its previou s

state. When the HALT/Grant Snoop state is entered from the Quick Start state, the input signal

restrictions of the Qu ick Start state still apply in the HALT/Grant S noop state, except for those

signal transitions that are required to perform the snoop.

2.2.7 Sleep State

The Sleep state is a very low power state in which the processor maintains its context and the

phase-locked loop (PLL) maintains ph ase lock. The Sleep state can only be entered from the Stop

Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the

processor to enter the Sleep state. The SLP# signal is not recognized in the Normal or Auto Halt

states.

The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven

active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be

driven inactiv e to ensure that the process or correctly initializes itself.

Input signals (other than RESET#) may not change while the processor is in the Sleep state or

transitioning into or out of the Sleep state. Input signal changes at these times will cause

unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the

Sleep state.

While in the Sleep state, the processor can enter its lowest power s tate, the Deep Sleep state.

Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be

removed in the Sleep state.

2.2.8 Deep Sleep State

The Deep Sleep state is the lowest p ower mode the processor can enter while maintaining its

context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is in

the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the low

state.

Pentium

Processor - Low Power

Datasheet 15

The processor returns to the Sleep or Quick Start state from the Deep Sleep state when the BCLK

input is restarted. Due to the PLL lock latency, there is a 30 µs delay after the clocks have started

before this state transition happens. PICCLK may be removed in the Deep Sleep state. PICCLK

should be designed to turn on when BCLK turns on when transitioning ou t of the Deep Sleep state.

The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that

RESET# assertion will result in unpredictable behavior.

2.2.9 Operating System Implications of Quick Start and Sleep States

There are a number of architectural features of the Pentium II Processor - Low Power that are not

available when the Quick Start state is enabled or do not function in the Quick Start or Sleep state

as they do in the Stop Grant state. These features are part of the time-stamp counter and

performance monitor counters. The time-stamp counter and the performance monitor counters are

not guaranteed to count in the Quick Start or Sleep states.

2.3 Low Power GTL+

The Pentium II Processor - Low Power system bus signals use a variation of the low voltage swing

GTL signaling technology. The Pentium II Processor - Low Power system bus specification is

similar to the Pentium II processor system bus sp ecification, which is itself a versio n of GTL with

enhanced noise margins and less ringing. The Pentium II Processor - Low Power system bus

specification reduces system cost and power consumption by raising the termination voltage and

termination resistance and changing the termination from dual ended to single ended. Because the

specification is different from the standard GTL specification and from the Pentium II processor

GTL+ specification, it is referred to as Low Power GTL+.

The Pentium II processor GTL+ system bus depends on incident wave switching and uses flight

time for timing calculati ons of the GTL+ signals. The Low Power GTL+ system bus is short and

lightly loaded. With Low Power GTL+ signals, timin g calculations are based on capacitive

derating. Analog signal simulation of the system bus including trace lengths is highly

recommended to ensure that there are no significant transmission line effects. Contact your field

sales representative to receive the IBIS models for the Pentium II Processor - Low Power.

The GTL+ system bus of the Pentium II processor was designed to support high-speed data

transfers with multiple lo ads on a long bus that behave s like a transmission line. However, in a

mobile system, the system bus on ly has two loads (the processor an d the ch ipset) and the bus traces

are short enoug h that tran smission line ef fects are not sign ificant. It is possibl e to change the layout

and termination of the system bus to take advantage of the mobile environment using the same

GTL+ I/O buffers. The benefit is that it reduces the nu mber of termi nating resistors in half and

substantially reduces the AC and DC power dissipation of the system bu s. Low Power GTL+ uses

GTL+ I/O buffers but only two loads are allowed. The trace length is limited and the bus is

terminated at one end only. Since the system bus is small and lightly loaded, it behaves like a

capacitor, and the GTL+ I/O buffers behave like high-speed open-drain buffers. With a 66-MHz

bus frequenc y, the pull-up would be 120 Ω. VTT has been increased from 1. 5 V to processor VCC to

eliminate the need for a 1.5 V power plane. If 100 Ω termination resis tors are used rather than

120 Ω, th en 20% more power will be dissipated in the termination resisto rs. 120 Ω termination is

recommended to conserve power.

Refer to the Pentium® II Processor - Low Powe r System Bus La yout Guideline (order number

243672) for details on laying out the Low Power GTL+ system bus.

Pentium

Processor - Low Power

16 Datasheet

2.3.1 GTL+ Signals

Two signals o f t h e s ys tem bu s can pot en ti al ly not meet the Low Power GTL + l ayo ut r e quirements:

PRDY# and RESET#. These two signals connect to the debug port and might not meet the

maximum length requirements. If PRDY# or RESET# do not meet the layout requirements for

Low Power GTL+, then they must be terminated using du a l-end e d term ination at 120 Ω. Higher

resistor values can be used if simulations show that the signal quality specifications in “System

Signal Simulations” on page 33 are met.

2.4 Pentium® II Processor - Low Power CPUID

The Pentium II Processor - Low Power has the same CPUID family and model number as some

Celeron™ processors. The Pentium II Processor - Low Power can be distinguished from these

Celeron processors by l ooking at the stepping number and the CPUID cache descriptor

information. A Pentium II Processor - Low Power has a stepping number in the range of 0AH to

0CH and an L2 cache descriptor of 042H ( 256-Kby te L2 cache). I f the stepping number is less than

0AH or the L2 cache des criptor is not 042H the processor is a Celeron processor. The L2 cache

must be properly initialized for the L2 cache descriptor information to be correct. After a power -on

RESET, or when the CPUID instruction is executed, the EAX register contains the values shown in

Table 4. After the L2 cache is initialized, the CPUID cache/TLB descriptors will be the values

shown in Table 5.

Table 4. Pentium® II Processor - Low Power CPUID

Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]

X 0 6 6 A - C

Table 5. Pentium® II Processor - Low Power CPUID Cache and TLB Descriptors

Cache and TLB Descriptors 01H, 02H, 03H, 04H, 08H, 0CH, 42H

Pentium

Processor - Low Power

Datasheet 17

3.0 Electrical Specifications

3.1 Processor System Sig nals

Table 6 lists the processor system signals by type.

All Low Power GTL+ signals are synchronous with the BCLK signal. All TAP signals are

synchronous with the TCK sig nal except TRST#. All CMOS input signals can be applied

asynchronously.

The CMOS, Clock , APIC an d TAP input s can be d riven from ground to 2.5 V. The TAP outputs are

open drain and should be pulled up to 2.5 V using resistors with the values shown in Table 7. If

open drain drivers are used for inpu t signals, then they should also be pulled up to 2.5 V using

resistors with the v a lues show n in Table 7.

Table 6. System Signal Groups

Group Name Signals

Low Power GTL+ Input BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#

Low Power GTL+ Output PRDY#

Low Power GTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,

BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#,

LOCK#, REQ[4:0]#, RP#

CMOS Input 1, 2 BSEL, A20M#, FLUSH#, IGNNE#, INIT#, INTR, NMI, PREQ#, PWRGOOD,

SLP#, SMI#, STPCLK#

Open Drain Output 2FERR#, IERR#

Clock 2BCLK

APIC Clock 2PICCLK

API C I/O 2PICD[1:0]

Thermal Diode THERMDA, THERMDC

TAP Input 2TCK, TDI, TMS, TRST#

TAP Output 2TDO

Power/Other 3EDGECTRLN, NC, PLL1, PLL2, TESTHI, TESTHI2, TESTHI3, TESTLO, VCC,

VCCP, VREF, VSS

NOTE:

1. See “Alphabetical Signal Reference” on page 52 for information on the PWRGOOD signal.

2. These signals are tolerant to 2.5 V only. See Table 7 for the recommended pull-up resistor.

3. VCC is the power supply for the core logic.

PLL1 and PLL2 are the power supply for the PLL analog section.

VCCP is the power supply for the CMOS voltage references.

VREF is the voltage reference for the Low Power GTL+ input buffers.

VSS is system ground.

Pentium

Processor - Low Power

18 Datasheet

3.1.1 Power Sequencing Requirements

The Pentium II Processor - Low Power h as no po wer sequencin g req uirements. It is recomm ended

that all of the processor power planes rise to their specified values within one second of each other.

The VCC power pl an e mu st n ot rise too fast . At l east 200 µs (TR) mu st pass from t h e time that V CC

is at 10% of its nominal val ue unti l the time that VCC is at 90% of its nominal value (see Figure 3).

3.1.2 Test Access Port (TAP) Connection

The TAP interface is an implementation of the IEEE 1149.1 (JTAG) standard. Due to the voltage

levels su pported by the TAP in terface, it is recommended that the Pentium II Processor - Low

Power and the other 2.5 V JTAG specification compliant devices be last in the JTAG chain after

any devices with 3.3 V or 5 V JTAG interfaces within the system. A translation buffer should be

used to reduce the TDO output voltage of the last 3.3/5 V device down to the 2.5 V range that the

Pentium II Processor - Lo w Power can tolerate. Multiple copi es of TCK, TMS, and TRST# must be

provided, one for each voltage level.

A Debug Port and connector may be placed at the start and end of the JTAG chain containing the

processor, with TDI to the first compon ent coming from the Debug Port and TDO from the last

component going to the Debug Port. There are no requirements for placement of the Pentium II

Processor - Low Power in the JTAG chain, except for those that are dictated by vo ltage

requirements of the TAP signals.

Table 7. Recomme nded Resi stors for Open Drain Signals

Recommended

Resistor Value (Ω)Open Drain Signal 1

150 pull-up TDI, TDO

680 pull-up STPCLK#

1K pull-up INIT#, TCK, TESTHI, TESTHI2, TESTHI3, TMS

680 - 1K pull-down TRST#

4.7K pull-up A20M#, FERR#, FLUSH#, IERR#, IGNNE#, INTR, NMI, PREQ#, PWRGOOD,

SLP#, SMI#

NOTE: Refer to “Unused Signals” on page 19 for the required pull-up or pull-down resistors for signals that

are not being used.

Figure 3. Ramp Rate Requirement

90% Vcc (nominal)

Volts

Vcc

10% Vcc (nominal)

Time

Pentium

Processor - Low Power

Datasheet 19

3.1.3 Catas tr ophic Thermal Protec tion

The Pentium II Processor - Low Power does not support catastrophic thermal protection or the

THERMTRIP# signal. An external thermal sensor should use the thermal diode t o protect the

processor and the system against excessive temperatures.

3.1.4 Unused Signals

All signals named NC must be unconnected. All signals named TESTLO must be pulled down to

VSS, and may be tied directly to VSS. All signals named TESTHI or TESTHI3 mu st be pulled u p to

VCC with a resistor. All signals named TESTHI2 must be pulled up to VCCP with a resistor. Each

TESTHI and TESTHI2 signal m ust have an indi vidual, 1 KΩ pull-up resistor . The TESTHI3 signals

can share a single 1 KΩ pull-up resistor.

Unused Low Power GTL+ inputs, outputs and bidirectional signals should be individually

connected to VCC with 120 Ω pull-up resistors. Unused CMOS active lo w inputs should b e

connected to 2.5 V and unused active high inputs should be connected to VSS. Unused open-drain

outputs should be unconnected. If the processor is configured to enter the Quick Start state rather

than the Stop Grant state, then the SLP# signal should be connected to 2.5 V. When tying any

signal to po wer or ground, a resistor will allow for system testab ility. For unused signals, it is

suggested that 10 KΩ resistors be used for pull-ups and 1 KΩ resist ors be used for pu ll-downs.

PICCLK and PICD[1:0] must be tied to VSS with a 1 KΩ resistor. BSEL must b e co nnected to VSS.

3.1.5 Signal State in Low Power States

3.1.5.1 System Bus Signals

All of the system bus signals have Low Power GTL+ input, output or input/output drivers. Except

when servicing snoops, the system bus signals are three-stated and pulled up by the termination

resistors. Snoops are not permitted in the Sleep and Deep Sleep states.

3.1.5.2 CMOS and Open-Drain Signals

The CMOS input signals are allowed to be in either the logic high or low state when the processor

is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggl e.

These input buf fers have no intern al pull-up or pull -down resistors and sy stem logic can use CMOS

or open-drain drivers to drive them.

The open-drain output signals have open drain drivers and external pull-up resistors are required.

One of the two output signals (IERR#) is a catastrophic error indicator and is three-stated (and

pulled-up) when the processor is functioning normally. The FERR# output can be either three-

stated or driven to VSS when the processor is in a low power state depending on the condition of

the floating point un it. Since this signal is a DC current path when it is driven to VSS, it is

recommended that the software clear or mask any floating point error condition before putting the

processor into the Deep Sleep state.

3.1.5.3 Other Signals

The system bus clock (BCLK) must be driven in all of the low power states except the Deep Sleep

state.

Pentium

Processor - Low Power

20 Datasheet

3.2 Power Supply Requirem ents

3.2.1 Decoupling Recommendations

The amount of bulk decoupling required to meet the processor voltage tolerance requirements is a

strong f uncti on of the p ower s up ply desi gn . Con t act you r Int el Fi el d Sales Rep res ent ati ve fo r tool s

to help determine how much decoupling is r equired . The processor core power plane (VCC) should

have at least twenty-six 0. 1 µF high freq uency decouplin g capacitors. The CMOS voltage ref erence

power plane (VCCP) requires 50 to 100 µF of bulk decoupling and at least eight 0.1 µF high

frequency decoupling capacitors.

For the Low Power GTL+ pull-up resistors, one 0.1 µF high frequency decoupling capacitor is

recommended per resistor pack. There should be no more than eight pull-up resistors per resistor

pack. The Low Power GTL+ vo ltage reference power plane (VREF) should have at least three

0.1 µF high frequency decoupling capacitors.

3.2.2 Voltage Planes

All VCC and VSS balls must be connected to the appropriate voltage plane. All VCCP and VREF

balls must be connected to the appropriate traces on the system electronics.

In addition to the main VCC, VCCP an d VSS power supp ly signal s, PLL1 and PL L2 provide isol ated

power to the PLL section. PLL1 and PLL2 should be connected according to Figure 4. Do not

connect PLL2 directly to VSS. Table 8 contains the requirements for C1 and L1.

Figure 4. PLL LC Filter

Table 8. LC Filter Specifications

Symbol Parameter Min Max Unit Notes

C1 LC Filter Capacitance 47 µF≤30% tolerance, 1 Ω max series

resistance, ~2 nH series inductance

L1 LC Filter Inductance 20 47 µHlow-Q type choke, ≤30% tolerance, 1.5 Ω

max series resistance, ≥50 mA current,

self-resonant frequency >10 MHz

PLL1

PLL2

VCCP

V0027-00

 Pentium
®
 
II
 Processor - Low Power
 Datasheet 21
3.3 Syst em Bus Clock and Processor Clocking
The 2.5 V BCLK clock input directly controls the operating speed of the system bus interface. All 
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The 
Pentium II Processor - Low Power core frequency is a multiple of the BCLK frequen c y. 
The processor core frequency must be configured during Reset by using the A20M#, IGNNE#, 
NMI, and INTR pins (see Table 9). The value on these pins during Reset determines the multiplier 
that the PLL will use for the internal core clock. See th e Pentium®II Pro cessor Developer’s 
Manual (order number 243502) for the definition of these pins during Reset and the operation of 
the pins after Reset.
A multiplexer is  required between the system electronics and the processor to drive the bus ratio 
configuration signals during Reset. Figure 8 and Figure 14 describe the timing requirements for 
this operation. The 443BX CRESET# signal has suitab le timing to control the multiplexer. After 
RESET# and PWRGOOD are asserted, the multiplexer logic must guarantee that the bus rat io 
configuration signals encode  on e of  the b us ratios in  Table 9 and  that the bu s  ratio co rrespo nds to  a 
core frequency at or below the marked core frequency for the processor. The selected bus ratio is 
visible to software in the Power-O n configuration register, see “Clock Frequencies and Ratios” on 
page 51 for details.
Multiplying the bus clock frequency is necessary to increase perf ormance while allowing for  easier 
distributio n of signals  within the system. Clock multiplication within the p r ocessor is pro vid ed by 
the internal Phase Lock Loop  (PLL), which requires a constant frequency BCLK input. 
During Reset, or on exit from the Deep Sleep state, the PLL requires some amount of time to 
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in “AC 
Specifications” on page 24 (T18 and T47). The system bus frequency ratio can be changed when 
RESET# is active, assuming that all Re set specifications are met. The BCLK frequency should  no t 
be changed during Deep Sleep state (see “Deep Sleep State” on page 14).
3.4 Maxi mum Ratings
Table 10 contains the Pentium II Processor - Low Power stress ratings. Functional operation at the 
absolute maximum and minimum is neither implied nor guaranteed. The processor should not 
receive a clock while subjected to these conditions. Functional operating conditions are provided in 
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. 
Furthermore, although the processor contains protective circuitry to resist damage from static 
electric discharge, one should always take precautions to avoid high static voltages or electric 
fields.
Table 9.  Core Frequency to System Bus Ratio Configuration
Processor Core Frequency to 
System Bus Frequency Ratio NMI INTR IGNNE# A20M# Powerup Configuration
[25:22]
1/4 (266 MHz) L L L H 0010
1/5 (333 MHz) L L H H 0000

Pentium

Processor - Low Power

22 Datasheet

3.5 DC Specifications

Table 11 through Table 14 list the DC specifications for the Pentium II Processor - Low Power.

Specifications are valid only while meeting specifications for case temperature, clock frequency

and input voltages. Care should be taken to read all notes associated with each parameter.

Table 10. Pentium® II Processor - Low Power Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

TStorage Storage Temperature –40 85 °C Note1

VCC(Abs) Supply Voltage with respect to VSS –0.5 3.0 V

VCCP CMOS Reference Voltage with respect to VSS –0.3 3.0 V

VIN GTL+ Buffer DC Input Voltage with respect to VSS –0.3 VCC + 0.7 V Note 2

VIN25 2.5 V Buffer DC Input Voltage with respect to VSS –0.3 3.3 V Note 3

NOTES:

1. The shipping container is only rated for 65° C.

2. Parameter applies to the Low Power GTL+ signal groups only.

3. Parameter applies to CMOS, Open-Drain, APIC and TAP bus signal groups only.

Table 11. Pentium® II Processor - Low Power Specifications (Sheet 1 of 2)

TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV

Symbol Parameter Min Typ Max Unit Notes1

VCC VCC of core logic for regular voltage

processors 1.465 1.6 1.735 V ±135 mV

VCC,LP VCC when ICC < 300 mA 1.465 1.6 1.805 V +205/-135 mV 2

VCCP VCC for CMOS voltage references 1.71 1.8 1.89 V 1.8 V ±90 mV

ICC

ICC for VCC at core frequency:

333 MHz

266 MHz 7.95

6.63 A

ANote 5

ICCP Current for VCCP 75 mA Notes 3, 4, 5

ICC,SG Processor Stop Grant and

Auto Halt current 1190 mA Note 5

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. A higher VCC,MAX is allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator.

3. ICCP is the current supply for the CMOS voltage references.

4. Not 100% tested. Specified by design/characterization.

5. ICCx,max spec ifications are specified at VCC,max, VCCP,max and 100° C and under maximum signal loading

conditions.

6. Bas ed on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator. This parameter is not tested.

7. Maximum values specified by design/characterization at nominal VCC and VCCP.

Pentium

Processor - Low Power

Datasheet 23

The signals on the Pentium II Processor - Low Power system bus are included in the Low Power

GTL+ signal group. These signals are specified to be terminated to VCC. The DC specifications for

these signals are listed in Table 12. The termination and reference voltage specifications for these

signals are listed in Table 13. The Pentium II Processor - Low Power requires external termination

and a VREF. Refer to Mobile Pentium® II Proces sor System Bu s Layout Guid eline (order number

243672) fo r full details of system VTT and VREF requirements.

The Clock, CMOS, Open-Drain and TAP signals are designed to interface at 2.5 V CMOS levels to

allow connection to other devices. The DC specifications for these 2.5 V tolerant signals are listed

in Table 14.

ICC,QS Processor Quick Start and

Sleep current 880 mA Note 5

ICC,DSLP Processor Deep Sleep leakage

current 650 mA Note 5

dICC/dt VCC power supply current slew rate 20 A/µs Notes 6, 7

Table 11. Pentium® II Processor - Low Power Specifications (Sheet 2 of 2)

TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV

Symbol Parameter Min Typ Max Unit Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. A higher VCC,MAX is allowed when the processor is in a low power state to enable high efficiency, low

current modes in the power regulator .

3. ICCP is the current supply for the CMOS voltage references.

4. Not 100% tested. Specified by design/characterization.

5. ICCx,max specifications are specified at VCC,max, VCCP,max and 100° C and under maximum signal loading

conditions.

6. B ased on simulations and averaged over the duration of any change in current. Use to compute the

maximum inductance and reaction time of the voltage regulator . This parameter is not tested.

7. Maximum values spec ified by design/characterization at nominal VCC and VCCP.

Table 12. Low Power GTL+ Signal Group DC Specifications

TCASE = 0° C to TCASE,max; VCC = 1.6 V ± 135 mV; VCCP = 1.8 V ± 90 mV

Symbol Parameter Min Max Unit Notes

VIL Input Low Voltage –0.3 5/9VTT – 0.2 V See Table 131

VIH Input High Voltage 5/9VTT + 0.2 VCC V Note 1

VOH Output High Voltage — — V See VTT max in Table

13.

RON Output Low Drive Strength 35 ohms

ILLeakage Current ±100 µA Note 2

ILO Output Leakage Current ±15 µA Note 3

NOTES:

1. VREF wors t case, not nominal. Noise on VREF should be accounted for.

2. ( 0 ≤ VIN ≤ VCC).

3. (0 ≤ VOUT ≤ VCC).

Pentium
®
 
II
 Processor - Low Power 
24 Datasheet
3.6 AC Specifications
3.6.1 System Bus, Clock, APIC, TAP, CMOS and Open-Drain 
AC Specifications
Table 15 through Table 22 provide AC specifications associated with the Pentium II Processor - 
Low Power. The AC  specifi cations are  divid ed in to th e fo llowing  cate gories:  Table 15  co ntains the 
system bus clock specifications; Table 16 contains the processor core frequencies; Table 17 
contains the Low Power  GTL+ specifications;  Table 18 c ontains the CMOS and  Open-Drain  signal 
groups specifications; Table 19 contains timings for th e res e t conditions; Table 20  contain s th e 
APIC specifications; Table 20 contains the TAP specifications; and Table 21 and Table 22 contain 
the power mana gem ent timing  specifications.
All system bus AC specifications for the Low Power GTL+ signal group are relative to the rising 
edge of the BCLK input at 1.25 V. All Low Power GTL+ timings are referenced to VREF for both 
‘0’ and ‘1’ logic levels unless otherwise specified.
Table 13.  Low Power GTL+ Bus DC Specifications
TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV
Symbol Parameter Min Typ Max Unit Notes
VTT Bus Termination Voltage VCC,MIN VCC VCC,MAX V Note 1
VREF Input Reference Voltage 5/9VTT – 2% 5/9VTT 5/9VTT + 2% V ±2% 2
NOTES:
1. The intent is to use the same power supply for VCC and VTT.
2. VREF for the system logic should be created from VTT by a voltage divider.
Table 14.  Clock, APIC, TAP, CMOS and Open-Drain Signal Group DC Specifications
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.7 V
VIL,BCLK I nput Low Voltage, BCLK –0.3 0.7 V
VIH Input High Voltage 1.7 2.625 V
VIH,BCLK Input High Voltage, BCLK 1.8 2.625 V
VOL Output Low Voltage 0.4 V Note 1
VOH Output High Voltage N/A 2.625 V All outputs are open-drain
IOL Output Low Current 14 mA
ILI Input Leakage Current ±100 µA Note 2
ILO Output Leakage Current ±30 µA Note 2
NOTES:
1. Parameter measured at 14 mA.
2. (0 ≤ VIN ≤ 2.625 V).

 Pentium
®
 
II
 Processor - Low Power
 Datasheet 25
Table 15.  System Bus Clock AC Specifications1
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; V CCP = 1.8 V ±90 mV
Symbol Parameter Min Typ Max Unit Figure Notes
System Bus Frequency 66.67 MHz
T1 BCLK Period 15 ns 5 Note 2
T2 BCLK Period Stability ±250 ps Notes 3, 4
T3 BCLK High Time 5.0 ns 5 @>1.8 V 
T4 BCLK Low Time 5.0 ns 5 @<0.7 V 
T5 BCLK Rise Time 0.175 0.875 ns 5 (0.9 V – 1.6 V), Note 4
T6 BCLK Fall T ime 0.175 0.875 ns 5 (1.6 V – 0.9 V), Note 4
NOTES:
1. All AC timings for Low Power GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25 V. 
All CMOS signals are referenced at 1.25 V.
2. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3. Not 100% tested. Specified by design/characterization.
4. M easured on the rising edge of adjac ent BCLKs at 1.25 V. The jitter present must be accounted for as a 
component of BCLK skew between devices.
Table 16.  Valid Pentium® II Processor - Low Power Frequencies
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; V CCP = 1.8 V ±90 mV
BCLK Frequency (MHz) Frequency Multiplier Core Frequency (MHz)
66.67 4 266.67
66.67 5 333.33
Table 17.  Low Power GTL+ Signal Groups AC Specifications
 RTT = 120 Ω terminated to VCC; VREF = 5/9 VCC; load = 0 pF
 TCASE = 0° C  to  TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure Notes
T7 Low Power GTL+ Output Valid Delay 0.00 7.78 ns 6  Note 1
T8 Low Power GTL+ Input Setup Ti me 2.98 ns 7 Notes 1, 2, 3
T9 Low Power GTL+ Input Hold Ti me 0.90 ns 7 Notes 1, 4
T10 RESET# Pulse Width 1 ms 8, 9 Notes 1, 5
NOTES:
1. A ll AC timings for Low Power GTL+ signals are referenced to the BCLK rising edge at 1.25 V. All Low 
Power GTL+ signals are referenced at VREF.
2. RESET# can be asserted (active) asynchronous ly, but must be deasserted synchronously.
3. Specification is for a minimum 0.40 V swing.
4. Specification is for a maximum 1.0 V swing.
5. After VCC, VCCP and BCLK become stable and PWRGOOD is asserted.

Pentium
®
 
II
 Processor - Low Power 
26 Datasheet
Table 18.  CMOS and Open-Drain Signal Groups AC Specifications
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure Notes
T14 2.5 V Input Pulse Width, except 
PWRGOOD 2 BCLKs 6 Active and Inactive 
states; Notes 1, 2
T15 PWRGOOD Inactive Pulse Width 10 BCLKs 9  Notes 1,2, 3, 4
NOTES:
1. All AC timings for CMOS and Open-Drain signals are referenced to the BCLK rising edge at 1.25 V. All 
CMOS and Open-Drain signals are referenced at 1.25 V.
2. Minimum output pulse width on CMOS outputs is 2 BCLKs.
3. When driven inactive, or after VCC, VCCP and BCLK become stable. PWRGOOD must remain below 
VIL,max from Table 14 until all t he voltage planes meet the vol tage tolerance specifications in Table 11, and 
BCLK has met the BCLK AC specifications in Table 15 for at least 10 clock cycles. PWRGOOD must rise 
glitch-free and monotonically to 2.5 V.
4. If the BCLK signal meets its AC specification within 150 ns of turning on then the PWRGOOD Inactive 
Pulse Width specification (T15) is  waived and BCLK may start after PWRGOOD is asserted. PWRGOOD 
must still remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
Table 19.  Reset Configuration AC Specifications
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure Notes
T16 Reset Configuration Signals 
(A[15:5]#, BR0#, FLUSH#, INIT#, 
PICD0) Setup Time 4 BCLKs 7, 8 Before 
deassertion of 
RESET#
T17 Reset Configuration Signals 
(A[15:5]#, BR0#, FLUSH#, INIT#, 
PICD0) Hold Time 2 20 BCLKs 7, 8 After clock that
deasserts 
RESET#
T18 Reset Configuration Signals (A20M#, 
IGNNE#, INTR, NMI) Setup Time 1ms9
Before 
deassertion of 
RESET# 1
T19 Reset Configuration Signals (A20M#, 
IGNNE#, INTR, NMI) Delay Time 5 BCLKs 9 A fter assertion of 
RESET# 2
T20 Reset Configuration Signals (A20M#, 
IGNNE#, INTR, NMI) Hold Time 2 20 BCLKs 7, 9 After clock that
deasserts 
RESET#
NOTES:
1. At least 1 ms must pass after PWRGOOD rises above VIH,min from Table 14, and BCLK meets its AC 
timing specification, until RESET# may be deasserted.
2. For a Reset, the clock ratio defined by these signals must be a safe value (their final value or a lower  
multiplier) within this delay after RESET# is asserted unless PWRGOOD is inactive (below VIL,max).

 Pentium
®
 
II
 Processor - Low Power
 Datasheet 27
Table 20.  TAP Signal AC Specifications
TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure Notes
T30 TCK Frequency — 16.67 MHz Note 1
T31 TCK  Period 60 — ns 5  Note 1
T32 TCK  High Time 25.0 ns 5 ≥ 1.7 V; Notes 1, 2
T33 TCK Low Time 25.0 ns 5 ≤ 0.7 V; Notes 1, 2
T34 TCK Rise Time 5.0 ns 5 (0.7 V-1.7 V); Notes 1, 2, 3
T35 TCK Fall Ti me 5.0 ns 5 (1.7 V-0.7 V); Notes 1, 2, 3
T36 TRS T# Pulse Width 40.0 ns 11 Asynchronous; Notes 1, 2
T37 TDI, TMS Setup Time 5.0 ns 10 Notes 1, 4
T38 TDI, TMS Hold Time 14.0 ns 10 Notes 1, 4
T39 TDO Valid Delay 1.0 10.0 ns 10 Notes 1, 5, 6
T40 TDO Float Delay 25.0 ns 10 Notes 1, 2, 5, 6
T41 A ll Non-Test Outputs Valid Delay 2.0 25.0 ns 10 Notes 1, 5, 7, 8
T42 A ll Non-Test Outputs Float Delay 25.0 ns 10 Notes 1, 2, 5, 7, 8
T43 A ll Non-Test Inputs Setup Time 5.0 ns 10 Notes 1, 4, 7, 8
T44 A ll Non-Test Inputs Hold Time 13.0 ns 10 Notes 1, 4, 7, 8
NOTES:
1. A ll AC timings for TAP signals are referenced to the TCK rising edge at 1.25 V. All CMOS signals are 
referenced at 1.25 V.
2. Not 100% tested. Specified by design/characterization.
3. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. V alid delay timing for this signal is specified into 150 Ω terminated to 2.5 V and 50 pF.
7. Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO and 
TMS). These timings correspond to the response of these signals due to boundary scan operations.
8. During Debug Port operation use the normal specified timings rather than the TAP signal timings.
Table 21.  Quick Start/Deep Sleep AC Specifications
 TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; V CCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure
T45 S top Grant Cycle Completion to Clock Stop 100 BCLKs 12
T46 S top Grant Cycle Completion to Input Signals Stable 0 ns 12
T47 Deep Sleep PLL Lock  Latency 30 µs 12
T48 STPCLK# Hold Time from PLL Lock 0 ns 12
T49 I nput Signal Hold Tim e from STPCLK# Deass ertion 8 BCLKs 12
NOTE: Input signals other than RESET# and BPRI# must be held constant in the Quick Start state.

Pentium
®
 
II
 Processor - Low Power 
28 Datasheet
Figure 5 through Figure 13 are to be used in conjunction with Table 15 through Table 22.
Table 22.  Stop Grant/Sleep/Deep Sleep AC Specifications
TCASE = 0° C to TCASE,max; VCC = 1.6 V ±135 mV; VCCP = 1.8 V ±90 mV 
Symbol Parameter Min Max Unit Figure
T50 SLP# Signal Hold Time from Stop Grant Cycle 
Completion 100 BCLKs 13
T51 SLP# Assertion to Input Signals Stable 0 ns 13
T52 SLP# Assertion to Clock Stop 10 BCLKs 13
T54 SLP# Hold Tim e from PLL Lock 0 ns 13
T55 STPCLK# Hold Time from SLP# Deassertion 10 BCLKs 13
T56 Input Signal Hold Time from SLP# Deassertion 10 BCLK s 13
NOTE: Input signals other than RE SET# mus t be held constant in the Sleep state.
Figure 5.  Generic Clock Waveform 
NOTES:Tr=T5, T34 (Rise Time)
Tf=T6, T35 (Fall T ime)
Th=T3, T32 (High Time)
Tl=T4, T33 (Low Time)
Tp=T1, T31 (Period) 
Figure 6.  Valid Delay Timings
NOTES:Tx=T7, T11 (Valid Delay)
Tpw=T14 (Pulse Width)
V=VREF for Low Power GTL+ signal group; 1.25 V for CMOS, Open-Drain,
   and TAP signal groups
CLK VIH
VIL 1.25V
Th
Tl
Tp
Tr
Tf
D0003-00
CLK
Signal
TxTx
Tpw
V Valid Valid
D0004-00

Pentium

Processor - Low Power

Datasheet 29

Figure 7. Setup and Hold Timings

NOTES:Ts=T8, T12 (Setup Time)

Th=T9, T13 (Hold Time)

V=VREF for Low Power GTL+ signals; 1.25 V for CMOS and TAP signals

Figure 8. Cold/Warm Reset and Configuration Timings

NOTES:Tt=T9 (Low P ower GTL+ Input Hold Tim e)

Tu=T8 (Low Power GTL+ Input Setup Time)

Tv=T10 (RESET# Pulse Width)

Tw=T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Setup Time)

Tx=T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0)

Hold Time)

T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

Ty=T19 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Delay Time)

Tz=T18 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Setup Time)

CLK

Signal V Valid

D0005-00

BCLK

RESET#

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid

D0006-01

Configuration

(A[15:5], BREQ0#,

FLUSH#, I NIT#,

PICD0)

Valid

Safe

Pentium

Processor - Low Power

30 Datasheet

Figure 9. Power-On Reset Timings

NOTES:Ta=T15 (PWRGOOD Inactive Pulse Width)

Tb=T10 (RESET# Pulse Width)

Tc=T20 (Rese t Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)

Figure 10. Test Timings (Boundary Scan)

NOTES:Tr=T43 (All Non-Test Inputs Setup Tim e)

Ts=T44 (All Non-Test Inputs Hold Time)

Tu=T40 (TDO Float Delay)

Tv=T37 (TDI, TMS Setup Time)

Tw=T38 (TDI, TMS Hold Time)

Tx=T39 (TDO Valid Delay)

Ty=T41 (All Non-Test Outputs Valid Delay)

Tz=T42 (All Non-Test Outputs Float Delay)

BCLK

PWRGOOD

RESET#

TaTb

V ,

VREF

D0007-01

V ,

CCP,

VIL,max

Configuration

(A20M#, IGNNE#,

INTR, NMI)

Valid Ratio

VIH,min

TCK

TDI, TMS

Input

Signals

TDO

Output

Signals

1.25V

TvTw

TrTs

TxTu

TyTz

D0008-00

Pentium

Processor - Low Power

Datasheet 31

Figure 11. Test Reset Timings

NOTES:Tq=T36 (TRST# Pulse Width)

Figure 12. Quick Start/Deep Sleep Timing

NOTES:Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay)

Tw=T46 (Setup T ime to Input Signal Hold Requirement)

Tx=T47 (Deep Sleep PLL Lock Latency)

Ty=T48 (PLL lock to STPCLK# Hold Time)

Tz=T49 (Input Signal Hold Time)

TRST# 1.25V

TqD0009-00

stpgnt

Running Running

BCLK

STPCLK#

CPU bus

SLP#

Compatibility

Signals Changing

Normal Quick Start Deep Sleep Quick Start Normal

Frozen

V0010-00

Pentium

Processor - Low Power

32 Datasheet

Figure 13. Stop Grant/Sleep/Deep Sleep Timing

NOTES:Tt=T50 (Stop Grant Acknowledge Bus Cycle Completion to SLP# Assertion Delay)

Tu=T51 (Setup Time to Input Signal Hold Requirement)

Tv=T52 (SLP# assertion to clock shut off delay)

Tw=T47 (Deep Sleep PLL lock latency)

Tx=T54 (SLP# H old Time)

Ty=T55 (STPCLK# Hold Tim e)

Tz=T56 (Input Signal Hold Time)

stpgnt

Running

BCLK

STPCLK#

CPU bus

SLP#

Compatibility

Signals FrozenChanging

Normal Stop

Grant Sleep Deep Sleep Sleep Stop

Grant Normal

Running

TwTx

V0011-00

Changing

 Pentium
®
 
II
 Processor - Low Power
 Datasheet 33
4.0 System Signal Simulations
Many scenarios have been simulated to generate a set of Low Power GTL+ processor system bus 
layout guidelines which are available in the Mobile Pentium® II Processor System Bus Layout 
Guideline (order number  243672).  Systems mu st be simu lated us ing the IBI S model to  determine i f 
they are compliant with this specification . 
4.1 System Bus Clock (BCLK) Signal Quality Specifications
Table 23  and Figure 14 show th e signal quality for the sys tem  bus clo c k (BCLK) signal as 
measured at the processor. The timings illustrated in Figure 14 are taken fro m Table 15 on page 25. 
BCLK is a 2.5 V clock.
Table 23.  BCLK Signal Quality Specifications 
Symbol Parameter Min Max Unit Figure Notes
V1 VIL,BCLK 0.7 V 14 Note 1
V2 VIH,BCLK 1.8 V 14 Note 1
V3 VIN Absolute Voltage Range –0.7 3.5 V 14 Undershoot, Overshoot
V4 Rising Edge Ringback 1.8 V 14 Absolute Value 2
V5 Falling Edge Ringback 0.7 V 14 Absolute Value 2
BCLK rising/falling slew rate 0.8 4 V/ns 14
NOTE:
1. B CLK  must rise/fall monotonically between VIL,BCLK and VIH,BCLK.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute 
voltage the BCLK signal can dip back to after passing the VIH,BCLK (rising) or VIL,BCLK (falling) voltage 
limits.
Figure 14. BCLK Generic Clock Waveform
V1
V3
V2 V4
V3
V5
V0012-00
T3
T6 T4 T5

Pentium

Processor - Low Power

34 Datasheet

4.2 Low Power GTL+ Signal Quality Specific ations

Table 24 and Figure 15 illustrate the Low Power GTL+ signal quality specifications for the

Pentium I I Processor - Low P ower. Refer to the Pentium® II Processor Developer’s Manual for the

GTL+ buffer specification.

Table 24. Low Power GTL+ Signal Group Ringback Specification

Symbol Parameter Min Unit Figure Notes

αOvershoot 100 mV 15 Notes 1, 2

τMinimum Time at High 1 ns 15 Notes 1, 2

ρAmplitude of Ringback -100 mV 15 Notes 1, 2, 3

φFinal Settling Voltage 100 mV 15 Notes 1, 2

δDuration of Sequential Ringback N/A ns 15 Notes 1, 2

NOTE:

1. Specified for the edge rate of 0.3 – 0.8 V/ns. See Figure 15 for the generic waveform.

2. All values determined by design/characterization.

3. Ringback below VREF +100 mV is not authorized during low to high transitions. Ringback above VREF -

100 mV is not authorized during high to low transitions.

Figure 15. Low to High, Low Power GTL+ Receiver Ringback Tolerance

NOTE: High-to-low case is analogous.

VREF+0.2V

Time

VREF-0.2V

VREF

Vstart

Clock

VIL,BCLK

VIH,BCLK

V0014-00

Pentium

Processor - Low Power

Datasheet 35

4.3 Non-Low Power GTL+ Signal Quality Specifications

Signals d r iven to the Pentiu m II Processor - Low Power s ho uld meet signal quality specifications

to ensure that the processor reads data properly and that incoming signals do not affect the long-

term reliability of the processor. There are three signal quality parameters defined: overshoot/

undershoot, ringback and settling limit. All three signal quality parameters are shown in Figure 16

for non-GTL+ signal groups.

4.3.1 Overshoot and Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maxi mum voltage above the nominal high

voltage or below VSS. The overshoot/undershoot guideline limits transitions beyond VCC or VSS

due to the fast signal edge rates. The processor can be damaged by repeat ed overshoot events on

2.5 V tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough).

However, excessive ring back is the dominant detrimental system tim ing effect resulting from

overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make it difficult to

satisfy the ringback specification). The overshoot/undershoot guideline is 0.8 V and as sumes the

absence of diodes on the input. These guidelines should be ve rified in simu lations without the on-

chip ESD protection diodes pres ent because the diodes will begin clamping the 2.5 V tolerant

signals beginning at approximately 1.25 V above VCC and 0.5 V below VSS. If the signals do not

reach the clamping voltage, this will not be an issue. A system should not rely on the diodes for

overshoot/unde rs hoot protection as this will negatively affect the life of the components and make

meeting the ringback specification very difficult.

Figure 16. Non-GTL+ Overshoot/Undershoot and Ringback

VLO

VHI=2.5V

VSS

Time

Settling Limit

Undershoot

Overshoot

Rising-Edge

Ringback

Falling-Edge

Ringback

V0015-00

Pentium

Processor - Low Power

36 Datasheet

4.3.2 Ringbac k Specifi cation

Ringback refers to the amount of reflection seen after a signal has switched. The ringback

specification is the voltage that the signal rings back to after achievin g its maximum absolute

value. Excessive ringback can cause false signal detection or extend the propagation delay. The

ringback specification applies to the input signal of each receiving agent. Violations of the signal

Ringback specification are not allowed under any circumstances for the non-GTL+ signals.

Ringback can be simulated with or without the input protection diodes that can be added to the

input buffer model. However, signals that reach the clamping voltage should be evaluated further.

See Table 25 for the signal ringback specifications fo r non-GTL+ signals.

4.3.3 Settling Limit Guideline

Settling limit defines the maximum amount of ringing at the receiving signal that a signal may

reach before its next transition. The amount allowed is 10% of the total signal swing (VHI – VLO)

above and below its final value. A signal should be within the settling limits of its final value, when

either in its hig h state or low state, before its next transition.

Signals that are not within their settling limit before transitionin g are at ri sk of unwanted

oscillatio ns that could je opardize signal in tegrity. Simulations to verify settling limit ma y be done

either with or without the input protection diodes present. V iolation of the settling limit guideline is

acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing

increasing in the subsequent trans itions.

Table 25. Signal Ringback Specifications for Non-GTL+ Signals

Input Signal Group Transition Maximum Ringback

(with Input Diodes Present) Figure

Non-GTL+ Signals 0 → 11.7 V 16

Non-GTL+ Signals 1 → 00.7 V 16

Pentium

Processor - Low Power

Datasheet 37

5.0 Mechanical Specifications

5.1 Dimensions

The Pentium® II Processor - Low Power is packaged in a PBGA-B615 package (also known as

BGA1) with the back of the processor die exposed on top.

The mechanical specifications for the surface-moun t package are provided in Table 26. Figure 17

shows the top and side views of the surface-mount package, and Figure 18 shows the bottom view

of the surface-mount package. For component handling, the substrate may only be contacted within

the shaded region between the keepout outline and the edge of the substrate.

Table 26. Surface-Mount BGA1 Package Specifications

Symbol Parameter Min Max Unit

A Ov erall Height, as delivered 2.29 2.79 mm

A1Ball Height, as delivered 0.76 1.10 mm

A2Die Height 1.23 1.38 mm

b Ball Diameter 0.78 REF mm

D Package Width 30.850 31.150 mm

D1Die Width 10.36 REF mm

E Package Length 34.850 35.150 mm

e Ball Pitch 1.270 mm

E1Die Length 17.36 REF mm

K Keepout Outline to Edge of Substrate 5 REF mm

K1Keepout Outline to Edge of S ubstrate at Corner 7 REF mm

N Ball Count 615 each

S1Outer Ball Center to Short Edge of Substrate 1.625 REF mm

S2Outer Ball Center to Long Edge of Substrate 0.895 REF mm

PDIE Allowable Pressure on the Die for Thermal Solution — 689 kPa

W Package Weight 3.71 4.52 grams

Pentium

Processor - Low Power

38 Datasheet

Figure 17. Surface-Mount BGA1 Package-Top and Side View

NOTES: Dimensions in parentheses are for reference only. All dimensions are in millimeters.

Figure 18. Surface-Mount BGA1 Package-Bottom View

V0026-00

(2x 1.800)

(2x 0.570)

(Ø 0.650)

(Ø 1.150)

(2x 2.032)

substrate

keepout

outline

die

(2x 1.500)

4x K

8x K

ink swatch

3456 910111213 15161718192021222324

2V0025-01

7 81 14

Øb

eS1

Pentium

Processor - Low Power

Datasheet 39

5.2 Signal Listings

Figure 19 is a topside view of the bal l map of the Pentium II Processor - Low Power with the

voltage balls called out. Table 27 lists the signals in ball number order. Table 28 and Table 29 list

the signals in signal name order.

Figure 19. Ball Map - Top View

V0024-01

VCC OtherVCCP VSS Analog

Decoupling

NCVSSD16#D18#VSSD3#D5#VSSVSSD0#VSSNCNCVSSNCVSSVSSA34#A26#VSSA29#VSSVSS

VSSVSSD31#D26#D13#D7#D2#D17#D15#D6#NCNCNCNCNCNCTESTHIA24#A30#A22#A19#A35#

EDG

CTRLN

VSS

D35#D29#D27#D24#D21#D19#D14#D10#D1#D4#NCNCNCNCNCBERR#RESET#A33#A31#A17#A25#NCNCVSS

D33#VSSD28#D32#VSSD22#D20#VSSD9#VREFVSSNCNCVSSVREFA27#VSSA20#A23#VSSTESTLOTESTLOVSSA28#

NCD39#D34#VREFVSSD25#D23#D30#D11#D12#D8#NCNCNCA32#A18#VREFA21#NCVSSTESTLOA13#A12#A16#

VCCPNCD43#D36#D37A10#A5#A15#A3#A11#

NCD44#VSSD38A14#VSSA6#A8#

D49#D51#D42#D45#AP0#A9#A4#A7#

D40#D52#D41#D47#D48#VREFAP1#RSP#BNR#TESTHI3

VSSD57#VSSVSSD59#TESTHI3VSSVSSTESTHI3VSS

D53#D46#D55#VREFD54#TESTHIREQ0#REQ4#BPRI#REQ1#

D60#D58#D50#D56#D61#TRDY#LOCK#TESTHI3REQ2#DEFER#

VSSD62#D63#VSSDEP7#VREFVSSHITM#REQ3#VSS

VSSDEP6#DEP5#DEP3#DEP0#HIT#DRDY#RP#DBSY#VSS

DEP4#DEP2#DEP1#VREFBPM1#PWRGOODRS1#RS2#RS0#BREQ0#

VSSBINIT#PRDY#VSSBP3#SLP#VSSTHERMDAADS#VSS

BPM0#BP2#TESTHI3PICCLKPICD1TDINCTHERMDCVCCPAERR#

TESTHIPREQ#INTRNCVCCPTMSNCBSEL

PICD0VSSVSSNCVCCPVSSVSSTRST#

VSSVCCPVCCPNCNCTESTLOFERR#SMI#TCKVSS

NMINCNCNCNCNCIERR#INIT#A20M#STPCLK#

NCNCNCNCNCNCNCIGNNE#TDO

VSSVSSNCNCNCTESTLONCTESTHI2FLUSH#

NCTESTHI2VCCPVSS NC

VSSVSS

VSSVSSBCLKVSSNC

242322212019181716151413121110987654321

PLL1PLL2

NC NC

VSS VSS VSS VSSVSS

NCNCNCVCCVSSVCCVSSVCCVSSVCCVSSNCNCNC