
AUIRFP4409
2 2017-09-21
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 300 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.24 ––– V/°C Reference to 25°C, ID = 3.5mA
RDS(on) Static Drain-to-Source On-Resistance ––– 56 69 m VGS = 10V, ID = 24A
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS =300 V, VGS = 0V
––– ––– 250 VDS =300V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Gate Resistance ––– 1.3 –––
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
gfs Forward Transconductance 45 ––– ––– S VDS = 50V, ID =24A
Qg Total Gate Charge ––– 83 125
nC
ID = 24A
Qgs Gate-to-Source Charge ––– 28 42 VDS = 150V
Qgd Gate-to-Drain Charge ––– 26 39 VGS = 10V
td(on) Turn-On Delay Time ––– 18 –––
ns
VDD = 195V
tr Rise Time ––– 23 ––– ID = 24A
td(off) Turn-Off Delay Time ––– 34 ––– RG= 2.2
tf Fall Time ––– 20 ––– VGS = 10V
Ciss Input Capacitance ––– 5168 –––
pF
VGS = 0V
Coss Output Capacitance ––– 300 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 77 ––– ƒ = 1.0MHz
Coss eff.(ER) Effective Output Capacitance (Energy Related) ––– 196 ––– VGS = 0V, VDS = 0V to 240V
See Fig.11
Coss eff.(TR) Output Capacitance (Time Related) ––– 265 ––– VGS = 0V, VDS = 0V to 240V
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 40
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 160 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 24A,VGS = 0V
trr Reverse Recovery Time ––– 302 ––– ns TJ = 25°C VDD = 255V
––– 379 ––– TJ = 125°C IF = 24A,
Qrr Reverse Recovery Charge ––– 1739 ––– nC TJ = 25°C di/dt = 100A/µs
––– 2497 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 13 ––– A TJ = 25°C
D
S
G
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Recommended max EAS limit, starting TJ = 25°C, L = 2.05mH, RG = 50, IAS = 24A, VGS =10V.
I
SD 24A, di/dt 1771A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
C
oss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
C
oss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994 http://www.irf.com/technical-info/ app notes/an-994.pdf
Ris measured at TJ approximately 90°C